drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32
  33 #include "resource.h"
  34
  35 #include "clock_source.h"
  36 #include "dc_bios_types.h"
  37
  38 #include "dce_calcs.h"
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "timing_generator.h"
  43 #include "virtual/virtual_link_encoder.h"
  44
  45 #include "link_hwss.h"
  46 #include "link_encoder.h"
  47
  48 #include "dc_link_ddc.h"
  49 #include "dm_helpers.h"
  50 #include "mem_input.h"
  51
  52 /*******************************************************************************
  53  * Private functions
  54  ******************************************************************************/
  55 static void destroy_links(struct core_dc *dc)
  56 {
  57         uint32_t i;
  58
  59         for (i = 0; i < dc->link_count; i++) {
  60                 if (NULL != dc->links[i])
  61                         link_destroy(&dc->links[i]);
  62         }
  63 }
  64
  65 static bool create_links(
  66                 struct core_dc *dc,
  67                 uint32_t num_virtual_links)
  68 {
  69         int i;
  70         int connectors_num;
  71         struct dc_bios *bios = dc->ctx->dc_bios;
  72
  73         dc->link_count = 0;
  74
  75         connectors_num = bios->funcs->get_connectors_number(bios);
  76
  77         if (connectors_num > ENUM_ID_COUNT) {
  78                 dm_error(
  79                         "DC: Number of connectors %d exceeds maximum of %d!\n",
  80                         connectors_num,
  81                         ENUM_ID_COUNT);
  82                 return false;
  83         }
  84
  85         if (connectors_num == 0 && num_virtual_links == 0) {
  86                 dm_error("DC: Number of connectors is zero!\n");
  87         }
  88
  89         dm_output_to_console(
  90                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
  91                 __func__,
  92                 connectors_num,
  93                 num_virtual_links);
  94
  95         for (i = 0; i < connectors_num; i++) {
  96                 struct link_init_data link_init_params = {0};
  97                 struct core_link *link;
  98
  99                 link_init_params.ctx = dc->ctx;
 100                 /* next BIOS object table connector */
 101                 link_init_params.connector_index = i;
 102                 link_init_params.link_index = dc->link_count;
 103                 link_init_params.dc = dc;
 104                 link = link_create(&link_init_params);
 105
 106                 if (link) {
 107                         dc->links[dc->link_count] = link;
 108                         link->dc = dc;
 109                         ++dc->link_count;
 110                 }
 111         }
 112
 113         for (i = 0; i < num_virtual_links; i++) {
 114                 struct core_link *link = dm_alloc(sizeof(*link));
 115                 struct encoder_init_data enc_init = {0};
 116
 117                 if (link == NULL) {
 118                         BREAK_TO_DEBUGGER();
 119                         goto failed_alloc;
 120                 }
 121
 122                 link->ctx = dc->ctx;
 123                 link->dc = dc;
 124                 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
 125                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 126                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 127                 link->link_id.enum_id = ENUM_ID_1;
 128                 link->link_enc = dm_alloc(sizeof(*link->link_enc));
 129
 130                 enc_init.ctx = dc->ctx;
 131                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 132                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 133                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 134                 enc_init.connector = link->link_id;
 135                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 136                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 137                 enc_init.encoder.enum_id = ENUM_ID_1;
 138                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 139
 140                 link->public.link_index = dc->link_count;
 141                 dc->links[dc->link_count] = link;
 142                 dc->link_count++;
 143         }
 144
 145         return true;
 146
 147 failed_alloc:
 148         return false;
 149 }
 150
 151 static bool stream_adjust_vmin_vmax(struct dc *dc,
 152                 const struct dc_stream **stream, int num_streams,
 153                 int vmin, int vmax)
 154 {
 155         /* TODO: Support multiple streams */
 156         struct core_dc *core_dc = DC_TO_CORE(dc);
 157         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
 158         int i = 0;
 159         bool ret = false;
 160
 161         for (i = 0; i < MAX_PIPES; i++) {
 162                 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
 163
 164                 if (pipe->stream == core_stream && pipe->stream_enc) {
 165                         core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
 166
 167                         /* build and update the info frame */
 168                         resource_build_info_frame(pipe);
 169                         core_dc->hwss.update_info_frame(pipe);
 170
 171                         ret = true;
 172                 }
 173         }
 174         return ret;
 175 }
 176
 177 static bool stream_get_crtc_position(struct dc *dc,
 178                 const struct dc_stream **stream, int num_streams,
 179                 unsigned int *v_pos, unsigned int *nom_v_pos)
 180 {
 181         /* TODO: Support multiple streams */
 182         struct core_dc *core_dc = DC_TO_CORE(dc);
 183         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
 184         int i = 0;
 185         bool ret = false;
 186         struct crtc_position position;
 187
 188         for (i = 0; i < MAX_PIPES; i++) {
 189                 struct pipe_ctx *pipe =
 190                                 &core_dc->current_context->res_ctx.pipe_ctx[i];
 191
 192                 if (pipe->stream == core_stream && pipe->stream_enc) {
 193                         core_dc->hwss.get_position(&pipe, 1, &position);
 194
 195                         *v_pos = position.vertical_count;
 196                         *nom_v_pos = position.nominal_vcount;
 197                         ret = true;
 198                 }
 199         }
 200         return ret;
 201 }
 202
 203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
 204 {
 205         struct core_dc *core_dc = DC_TO_CORE(dc);
 206         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
 207         int i = 0;
 208         bool ret = false;
 209         struct pipe_ctx *pipes;
 210
 211         for (i = 0; i < MAX_PIPES; i++) {
 212                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
 213                                 == core_stream) {
 214
 215                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
 216                         core_dc->hwss.program_gamut_remap(pipes);
 217                         ret = true;
 218                 }
 219         }
 220
 221         return ret;
 222 }
 223
 224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
 225 {
 226         struct core_dc *core_dc = DC_TO_CORE(dc);
 227         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
 228         int i = 0;
 229         bool ret = false;
 230         struct pipe_ctx *pipes;
 231
 232         for (i = 0; i < MAX_PIPES; i++) {
 233                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
 234                                 == core_stream) {
 235
 236                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
 237                         core_dc->hwss.program_csc_matrix(pipes,
 238                         core_stream->public.output_color_space,
 239                         core_stream->public.csc_color_matrix.matrix);
 240                         ret = true;
 241                 }
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void set_static_screen_events(struct dc *dc,
 248                 const struct dc_stream **stream,
 249                 int num_streams,
 250                 const struct dc_static_screen_events *events)
 251 {
 252         struct core_dc *core_dc = DC_TO_CORE(dc);
 253         int i = 0;
 254         int j = 0;
 255         struct pipe_ctx *pipes_affected[MAX_PIPES];
 256         int num_pipes_affected = 0;
 257
 258         for (i = 0; i < num_streams; i++) {
 259                 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
 260
 261                 for (j = 0; j < MAX_PIPES; j++) {
 262                         if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
 263                                         == core_stream) {
 264                                 pipes_affected[num_pipes_affected++] =
 265                                                 &core_dc->current_context->res_ctx.pipe_ctx[j];
 266                         }
 267                 }
 268         }
 269
 270         core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 271 }
 272
 273 static void set_drive_settings(struct dc *dc,
 274                 struct link_training_settings *lt_settings,
 275                 const struct dc_link *link)
 276 {
 277         struct core_dc *core_dc = DC_TO_CORE(dc);
 278         int i;
 279
 280         for (i = 0; i < core_dc->link_count; i++) {
 281                 if (&core_dc->links[i]->public == link)
 282                         break;
 283         }
 284
 285         if (i >= core_dc->link_count)
 286                 ASSERT_CRITICAL(false);
 287
 288         dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
 289 }
 290
 291 static void perform_link_training(struct dc *dc,
 292                 struct dc_link_settings *link_setting,
 293                 bool skip_video_pattern)
 294 {
 295         struct core_dc *core_dc = DC_TO_CORE(dc);
 296         int i;
 297
 298         for (i = 0; i < core_dc->link_count; i++)
 299                 dc_link_dp_perform_link_training(
 300                         &core_dc->links[i]->public,
 301                         link_setting,
 302                         skip_video_pattern);
 303 }
 304
 305 static void set_preferred_link_settings(struct dc *dc,
 306                 struct dc_link_settings *link_setting,
 307                 const struct dc_link *link)
 308 {
 309         struct core_link *core_link = DC_LINK_TO_CORE(link);
 310
 311         core_link->public.verified_link_cap.lane_count =
 312                                 link_setting->lane_count;
 313         core_link->public.verified_link_cap.link_rate =
 314                                 link_setting->link_rate;
 315         dp_retrain_link_dp_test(core_link, link_setting, false);
 316 }
 317
 318 static void enable_hpd(const struct dc_link *link)
 319 {
 320         dc_link_dp_enable_hpd(link);
 321 }
 322
 323 static void disable_hpd(const struct dc_link *link)
 324 {
 325         dc_link_dp_disable_hpd(link);
 326 }
 327
 328
 329 static void set_test_pattern(
 330                 const struct dc_link *link,
 331                 enum dp_test_pattern test_pattern,
 332                 const struct link_training_settings *p_link_settings,
 333                 const unsigned char *p_custom_pattern,
 334                 unsigned int cust_pattern_size)
 335 {
 336         if (link != NULL)
 337                 dc_link_dp_set_test_pattern(
 338                         link,
 339                         test_pattern,
 340                         p_link_settings,
 341                         p_custom_pattern,
 342                         cust_pattern_size);
 343 }
 344
 345 void set_dither_option(const struct dc_stream *dc_stream,
 346                 enum dc_dither_option option)
 347 {
 348         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
 349         struct bit_depth_reduction_params params;
 350         struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
 351         struct pipe_ctx *pipes =
 352                         core_link->dc->current_context->res_ctx.pipe_ctx;
 353
 354         memset(&params, 0, sizeof(params));
 355         if (!stream)
 356                 return;
 357         if (option > DITHER_OPTION_MAX)
 358                 return;
 359         if (option == DITHER_OPTION_DEFAULT) {
 360                 switch (stream->public.timing.display_color_depth) {
 361                 case COLOR_DEPTH_666:
 362                         stream->public.dither_option = DITHER_OPTION_SPATIAL6;
 363                         break;
 364                 case COLOR_DEPTH_888:
 365                         stream->public.dither_option = DITHER_OPTION_SPATIAL8;
 366                         break;
 367                 case COLOR_DEPTH_101010:
 368                         stream->public.dither_option = DITHER_OPTION_SPATIAL10;
 369                         break;
 370                 default:
 371                         option = DITHER_OPTION_DISABLE;
 372                 }
 373         } else {
 374                 stream->public.dither_option = option;
 375         }
 376         resource_build_bit_depth_reduction_params(stream,
 377                                 &params);
 378         stream->bit_depth_params = params;
 379         pipes->opp->funcs->
 380                 opp_program_bit_depth_reduction(pipes->opp, &params);
 381 }
 382
 383 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
 384 {
 385         if (core_dc->hwss.set_drr != NULL) {
 386                 core_dc->public.stream_funcs.adjust_vmin_vmax =
 387                                 stream_adjust_vmin_vmax;
 388         }
 389
 390         core_dc->public.stream_funcs.set_static_screen_events =
 391                         set_static_screen_events;
 392
 393         core_dc->public.stream_funcs.get_crtc_position =
 394                         stream_get_crtc_position;
 395
 396         core_dc->public.stream_funcs.set_gamut_remap =
 397                         set_gamut_remap;
 398
 399         core_dc->public.stream_funcs.program_csc_matrix =
 400                         program_csc_matrix;
 401
 402         core_dc->public.stream_funcs.set_dither_option =
 403                         set_dither_option;
 404
 405         core_dc->public.link_funcs.set_drive_settings =
 406                         set_drive_settings;
 407
 408         core_dc->public.link_funcs.perform_link_training =
 409                         perform_link_training;
 410
 411         core_dc->public.link_funcs.set_preferred_link_settings =
 412                         set_preferred_link_settings;
 413
 414         core_dc->public.link_funcs.enable_hpd =
 415                         enable_hpd;
 416
 417         core_dc->public.link_funcs.disable_hpd =
 418                         disable_hpd;
 419
 420         core_dc->public.link_funcs.set_test_pattern =
 421                         set_test_pattern;
 422 }
 423
 424 static void destruct(struct core_dc *dc)
 425 {
 426         dc_resource_validate_ctx_destruct(dc->current_context);
 427
 428         destroy_links(dc);
 429
 430         dc_destroy_resource_pool(dc);
 431
 432         if (dc->ctx->gpio_service)
 433                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 434
 435         if (dc->ctx->i2caux)
 436                 dal_i2caux_destroy(&dc->ctx->i2caux);
 437
 438         if (dc->ctx->created_bios)
 439                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 440
 441         if (dc->ctx->logger)
 442                 dal_logger_destroy(&dc->ctx->logger);
 443
 444         dm_free(dc->current_context);
 445         dc->current_context = NULL;
 446
 447         dm_free(dc->ctx);
 448         dc->ctx = NULL;
 449 }
 450
 451 static bool construct(struct core_dc *dc,
 452                 const struct dc_init_data *init_params)
 453 {
 454         struct dal_logger *logger;
 455         struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
 456         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 457
 458         if (!dc_ctx) {
 459                 dm_error("%s: failed to create ctx\n", __func__);
 460                 goto ctx_fail;
 461         }
 462
 463         dc->current_context = dm_alloc(sizeof(*dc->current_context));
 464
 465         if (!dc->current_context) {
 466                 dm_error("%s: failed to create validate ctx\n", __func__);
 467                 goto val_ctx_fail;
 468         }
 469
 470         dc_ctx->cgs_device = init_params->cgs_device;
 471         dc_ctx->driver_context = init_params->driver;
 472         dc_ctx->dc = &dc->public;
 473         dc_ctx->asic_id = init_params->asic_id;
 474
 475         /* Create logger */
 476         logger = dal_logger_create(dc_ctx);
 477
 478         if (!logger) {
 479                 /* can *not* call logger. call base driver 'print error' */
 480                 dm_error("%s: failed to create Logger!\n", __func__);
 481                 goto logger_fail;
 482         }
 483         dc_ctx->logger = logger;
 484         dc->ctx = dc_ctx;
 485         dc->ctx->dce_environment = init_params->dce_environment;
 486
 487         dc_version = resource_parse_asic_id(init_params->asic_id);
 488         dc->ctx->dce_version = dc_version;
 489
 490         /* Resource should construct all asic specific resources.
 491          * This should be the only place where we need to parse the asic id
 492          */
 493         if (init_params->vbios_override)
 494                 dc_ctx->dc_bios = init_params->vbios_override;
 495         else {
 496                 /* Create BIOS parser */
 497                 struct bp_init_data bp_init_data;
 498
 499                 bp_init_data.ctx = dc_ctx;
 500                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 501
 502                 dc_ctx->dc_bios = dal_bios_parser_create(
 503                                 &bp_init_data, dc_version);
 504
 505                 if (!dc_ctx->dc_bios) {
 506                         ASSERT_CRITICAL(false);
 507                         goto bios_fail;
 508                 }
 509
 510                 dc_ctx->created_bios = true;
 511                 }
 512
 513         /* Create I2C AUX */
 514         dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
 515
 516         if (!dc_ctx->i2caux) {
 517                 ASSERT_CRITICAL(false);
 518                 goto failed_to_create_i2caux;
 519         }
 520
 521         /* Create GPIO service */
 522         dc_ctx->gpio_service = dal_gpio_service_create(
 523                         dc_version,
 524                         dc_ctx->dce_environment,
 525                         dc_ctx);
 526
 527         if (!dc_ctx->gpio_service) {
 528                 ASSERT_CRITICAL(false);
 529                 goto gpio_fail;
 530         }
 531
 532         dc->res_pool = dc_create_resource_pool(
 533                         dc,
 534                         init_params->num_virtual_links,
 535                         dc_version,
 536                         init_params->asic_id);
 537         if (!dc->res_pool)
 538                 goto create_resource_fail;
 539
 540         if (!create_links(dc, init_params->num_virtual_links))
 541                 goto create_links_fail;
 542
 543         allocate_dc_stream_funcs(dc);
 544
 545         return true;
 546
 547         /**** error handling here ****/
 548 create_links_fail:
 549 create_resource_fail:
 550 gpio_fail:
 551 failed_to_create_i2caux:
 552 bios_fail:
 553 logger_fail:
 554 val_ctx_fail:
 555 ctx_fail:
 556         destruct(dc);
 557         return false;
 558 }
 559
 560 /*
 561 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
 562 {
 563         fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
 564         unsigned int pixDurationInPico = round(pixel_duration);
 565
 566         DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
 567
 568         arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
 569         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
 570         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
 571
 572         arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
 573         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
 574         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
 575
 576         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
 577         WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
 578
 579         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
 580         WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
 581 }
 582 */
 583
 584 /*******************************************************************************
 585  * Public functions
 586  ******************************************************************************/
 587
 588 struct dc *dc_create(const struct dc_init_data *init_params)
 589  {
 590         struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
 591         unsigned int full_pipe_count;
 592
 593         if (NULL == core_dc)
 594                 goto alloc_fail;
 595
 596         if (false == construct(core_dc, init_params))
 597                 goto construct_fail;
 598
 599         /*TODO: separate HW and SW initialization*/
 600         core_dc->hwss.init_hw(core_dc);
 601
 602         full_pipe_count = core_dc->res_pool->pipe_count;
 603         if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 604                 full_pipe_count--;
 605         core_dc->public.caps.max_streams = min(
 606                         full_pipe_count,
 607                         core_dc->res_pool->stream_enc_count);
 608
 609         core_dc->public.caps.max_links = core_dc->link_count;
 610         core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
 611
 612         core_dc->public.config = init_params->flags;
 613
 614         dm_logger_write(core_dc->ctx->logger, LOG_DC,
 615                         "Display Core initialized\n");
 616
 617
 618         /* TODO: missing feature to be enabled */
 619         core_dc->public.debug.disable_dfs_bypass = true;
 620
 621         return &core_dc->public;
 622
 623 construct_fail:
 624         dm_free(core_dc);
 625
 626 alloc_fail:
 627         return NULL;
 628 }
 629
 630 void dc_destroy(struct dc **dc)
 631 {
 632         struct core_dc *core_dc = DC_TO_CORE(*dc);
 633         destruct(core_dc);
 634         dm_free(core_dc);
 635         *dc = NULL;
 636 }
 637
 638 static bool is_validation_required(
 639                 const struct core_dc *dc,
 640                 const struct dc_validation_set set[],
 641                 int set_count)
 642 {
 643         const struct validate_context *context = dc->current_context;
 644         int i, j;
 645
 646         if (context->stream_count != set_count)
 647                 return true;
 648
 649         for (i = 0; i < set_count; i++) {
 650
 651                 if (set[i].surface_count != context->stream_status[i].surface_count)
 652                         return true;
 653                 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
 654                         return true;
 655
 656                 for (j = 0; j < set[i].surface_count; j++) {
 657                         struct dc_surface temp_surf;
 658                         memset(&temp_surf, 0, sizeof(temp_surf));
 659
 660                         temp_surf = *context->stream_status[i].surfaces[j];
 661                         temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
 662                         temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
 663                         temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
 664
 665                         if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
 666                                 return true;
 667                 }
 668         }
 669
 670         return false;
 671 }
 672
 673 struct validate_context *dc_get_validate_context(
 674                 const struct dc *dc,
 675                 const struct dc_validation_set set[],
 676                 uint8_t set_count)
 677 {
 678         struct core_dc *core_dc = DC_TO_CORE(dc);
 679         enum dc_status result = DC_ERROR_UNEXPECTED;
 680         struct validate_context *context;
 681
 682         context = dm_alloc(sizeof(struct validate_context));
 683         if (context == NULL)
 684                 goto context_alloc_fail;
 685
 686         if (!is_validation_required(core_dc, set, set_count)) {
 687                 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
 688                 return context;
 689         }
 690
 691         result = core_dc->res_pool->funcs->validate_with_context(
 692                         core_dc, set, set_count, context, core_dc->current_context);
 693
 694 context_alloc_fail:
 695         if (result != DC_OK) {
 696                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 697                                 "%s:resource validation failed, dc_status:%d\n",
 698                                 __func__,
 699                                 result);
 700
 701                 dc_resource_validate_ctx_destruct(context);
 702                 dm_free(context);
 703                 context = NULL;
 704         }
 705
 706         return context;
 707
 708 }
 709
 710 bool dc_validate_resources(
 711                 const struct dc *dc,
 712                 const struct dc_validation_set set[],
 713                 uint8_t set_count)
 714 {
 715         struct core_dc *core_dc = DC_TO_CORE(dc);
 716         enum dc_status result = DC_ERROR_UNEXPECTED;
 717         struct validate_context *context;
 718
 719         context = dm_alloc(sizeof(struct validate_context));
 720         if (context == NULL)
 721                 goto context_alloc_fail;
 722
 723         result = core_dc->res_pool->funcs->validate_with_context(
 724                                 core_dc, set, set_count, context, NULL);
 725
 726 context_alloc_fail:
 727         if (result != DC_OK) {
 728                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 729                                 "%s:resource validation failed, dc_status:%d\n",
 730                                 __func__,
 731                                 result);
 732         }
 733
 734         dc_resource_validate_ctx_destruct(context);
 735         dm_free(context);
 736         context = NULL;
 737
 738         return result == DC_OK;
 739 }
 740
 741 bool dc_validate_guaranteed(
 742                 const struct dc *dc,
 743                 const struct dc_stream *stream)
 744 {
 745         struct core_dc *core_dc = DC_TO_CORE(dc);
 746         enum dc_status result = DC_ERROR_UNEXPECTED;
 747         struct validate_context *context;
 748
 749         context = dm_alloc(sizeof(struct validate_context));
 750         if (context == NULL)
 751                 goto context_alloc_fail;
 752
 753         result = core_dc->res_pool->funcs->validate_guaranteed(
 754                                         core_dc, stream, context);
 755
 756         dc_resource_validate_ctx_destruct(context);
 757         dm_free(context);
 758
 759 context_alloc_fail:
 760         if (result != DC_OK) {
 761                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 762                         "%s:guaranteed validation failed, dc_status:%d\n",
 763                         __func__,
 764                         result);
 765                 }
 766
 767         return (result == DC_OK);
 768 }
 769
 770 static void program_timing_sync(
 771                 struct core_dc *core_dc,
 772                 struct validate_context *ctx)
 773 {
 774         int i, j;
 775         int group_index = 0;
 776         int pipe_count = core_dc->res_pool->pipe_count;
 777         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 778
 779         for (i = 0; i < pipe_count; i++) {
 780                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 781                         continue;
 782
 783                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 784         }
 785
 786         for (i = 0; i < pipe_count; i++) {
 787                 int group_size = 1;
 788                 struct pipe_ctx *pipe_set[MAX_PIPES];
 789
 790                 if (!unsynced_pipes[i])
 791                         continue;
 792
 793                 pipe_set[0] = unsynced_pipes[i];
 794                 unsynced_pipes[i] = NULL;
 795
 796                 /* Add tg to the set, search rest of the tg's for ones with
 797                  * same timing, add all tgs with same timing to the group
 798                  */
 799                 for (j = i + 1; j < pipe_count; j++) {
 800                         if (!unsynced_pipes[j])
 801                                 continue;
 802
 803                         if (resource_are_streams_timing_synchronizable(
 804                                         unsynced_pipes[j]->stream,
 805                                         pipe_set[0]->stream)) {
 806                                 pipe_set[group_size] = unsynced_pipes[j];
 807                                 unsynced_pipes[j] = NULL;
 808                                 group_size++;
 809                         }
 810                 }
 811
 812                 /* set first unblanked pipe as master */
 813                 for (j = 0; j < group_size; j++) {
 814                         struct pipe_ctx *temp;
 815
 816                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
 817                                 if (j == 0)
 818                                         break;
 819
 820                                 temp = pipe_set[0];
 821                                 pipe_set[0] = pipe_set[j];
 822                                 pipe_set[j] = temp;
 823                                 break;
 824                         }
 825                 }
 826
 827                 /* remove any other unblanked pipes as they have already been synced */
 828                 for (j = j + 1; j < group_size; j++) {
 829                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
 830                                 group_size--;
 831                                 pipe_set[j] = pipe_set[group_size];
 832                                 j--;
 833                         }
 834                 }
 835
 836                 if (group_size > 1) {
 837                         core_dc->hwss.enable_timing_synchronization(
 838                                 core_dc, group_index, group_size, pipe_set);
 839                         group_index++;
 840                 }
 841         }
 842 }
 843
 844 static bool context_changed(
 845                 struct core_dc *dc,
 846                 struct validate_context *context)
 847 {
 848         uint8_t i;
 849
 850         if (context->stream_count != dc->current_context->stream_count)
 851                 return true;
 852
 853         for (i = 0; i < dc->current_context->stream_count; i++) {
 854                 if (&dc->current_context->streams[i]->public != &context->streams[i]->public)
 855                         return true;
 856         }
 857
 858         return false;
 859 }
 860
 861 static bool streams_changed(
 862                 struct core_dc *dc,
 863                 const struct dc_stream *streams[],
 864                 uint8_t stream_count)
 865 {
 866         uint8_t i;
 867
 868         if (stream_count != dc->current_context->stream_count)
 869                 return true;
 870
 871         for (i = 0; i < dc->current_context->stream_count; i++) {
 872                 if (&dc->current_context->streams[i]->public != streams[i])
 873                         return true;
 874         }
 875
 876         return false;
 877 }
 878
 879 bool dc_enable_stereo(
 880         struct dc *dc,
 881         struct validate_context *context,
 882         const struct dc_stream *streams[],
 883         uint8_t stream_count)
 884 {
 885         bool ret = true;
 886         int i, j;
 887         struct pipe_ctx *pipe;
 888         struct core_dc *core_dc = DC_TO_CORE(dc);
 889
 890 #ifdef ENABLE_FBC
 891         struct compressor *fbc_compressor = core_dc->fbc_compressor;
 892 #endif
 893
 894         for (i = 0; i < MAX_PIPES; i++) {
 895                 if (context != NULL)
 896                         pipe = &context->res_ctx.pipe_ctx[i];
 897                 else
 898                         pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
 899                 for (j = 0 ; pipe && j < stream_count; j++)  {
 900                         if (streams[j] && streams[j] == &pipe->stream->public &&
 901                                 core_dc->hwss.setup_stereo)
 902                                 core_dc->hwss.setup_stereo(pipe, core_dc);
 903                 }
 904         }
 905
 906 #ifdef ENABLE_FBC
 907         if (fbc_compressor != NULL &&
 908             fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
 909                                                         &pipe->tg->inst))
 910                 fbc_compressor->funcs->disable_fbc(fbc_compressor);
 911
 912 #endif
 913         return ret;
 914 }
 915
 916
 917 /*
 918  * Applies given context to HW and copy it into current context.
 919  * It's up to the user to release the src context afterwards.
 920  */
 921 static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context)
 922 {
 923         struct core_dc *core_dc = DC_TO_CORE(dc);
 924         struct dc_bios *dcb = core_dc->ctx->dc_bios;
 925         enum dc_status result = DC_ERROR_UNEXPECTED;
 926         struct pipe_ctx *pipe;
 927         int i, j, k, l;
 928         const struct dc_stream *dc_streams[MAX_STREAMS] = {0};
 929
 930         for (i = 0; i < context->stream_count; i++)
 931                 dc_streams[i] =  &context->streams[i]->public;
 932
 933         if (!dcb->funcs->is_accelerated_mode(dcb))
 934                 core_dc->hwss.enable_accelerated_mode(core_dc);
 935
 936         result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
 937
 938         program_timing_sync(core_dc, context);
 939
 940         for (i = 0; i < context->stream_count; i++) {
 941                 const struct core_sink *sink = context->streams[i]->sink;
 942
 943                 for (j = 0; j < context->stream_status[i].surface_count; j++) {
 944                         struct core_surface *surface =
 945                                         DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
 946
 947                         core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
 948
 949                         /*
 950                          * enable stereo
 951                          * TODO rework dc_enable_stereo call to work with validation sets?
 952                          */
 953                         for (k = 0; k < MAX_PIPES; k++) {
 954                                 pipe = &context->res_ctx.pipe_ctx[k];
 955
 956                                 for (l = 0 ; pipe && l < context->stream_count; l++)  {
 957                                         if (context->streams[l] &&
 958                                             context->streams[l] == pipe->stream &&
 959                                             core_dc->hwss.setup_stereo)
 960                                                 core_dc->hwss.setup_stereo(pipe, core_dc);
 961                                 }
 962                         }
 963                 }
 964
 965                 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
 966                                 context->streams[i]->public.timing.h_addressable,
 967                                 context->streams[i]->public.timing.v_addressable,
 968                                 context->streams[i]->public.timing.h_total,
 969                                 context->streams[i]->public.timing.v_total,
 970                                 context->streams[i]->public.timing.pix_clk_khz);
 971         }
 972
 973         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 974
 975         dc_resource_validate_ctx_copy_construct(context, core_dc->current_context);
 976
 977         return (result == DC_OK);
 978 }
 979
 980 bool dc_commit_context(struct dc *dc, struct validate_context *context)
 981 {
 982         enum dc_status result = DC_ERROR_UNEXPECTED;
 983         struct core_dc *core_dc = DC_TO_CORE(dc);
 984         int i;
 985
 986         if (false == context_changed(core_dc, context))
 987                 return DC_OK;
 988
 989         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
 990                                 __func__, context->stream_count);
 991
 992         for (i = 0; i < context->stream_count; i++) {
 993                 const struct dc_stream *stream = &context->streams[i]->public;
 994
 995                 dc_stream_log(stream,
 996                                 core_dc->ctx->logger,
 997                                 LOG_DC);
 998         }
 999
1000         result = dc_commit_context_no_check(dc, context);
1001
1002         return (result == DC_OK);
1003 }
1004
1005
1006 bool dc_commit_streams(
1007         struct dc *dc,
1008         const struct dc_stream *streams[],
1009         uint8_t stream_count)
1010 {
1011         struct core_dc *core_dc = DC_TO_CORE(dc);
1012         enum dc_status result = DC_ERROR_UNEXPECTED;
1013         struct validate_context *context;
1014         struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
1015         int i;
1016
1017         if (false == streams_changed(core_dc, streams, stream_count))
1018                 return DC_OK;
1019
1020         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
1021                                 __func__, stream_count);
1022
1023         for (i = 0; i < stream_count; i++) {
1024                 const struct dc_stream *stream = streams[i];
1025                 const struct dc_stream_status *status = dc_stream_get_status(stream);
1026                 int j;
1027
1028                 dc_stream_log(stream,
1029                                 core_dc->ctx->logger,
1030                                 LOG_DC);
1031
1032                 set[i].stream = stream;
1033
1034                 if (status) {
1035                         set[i].surface_count = status->surface_count;
1036                         for (j = 0; j < status->surface_count; j++)
1037                                 set[i].surfaces[j] = status->surfaces[j];
1038                 }
1039
1040         }
1041
1042         context = dm_alloc(sizeof(struct validate_context));
1043         if (context == NULL)
1044                 goto context_alloc_fail;
1045
1046         result = core_dc->res_pool->funcs->validate_with_context(
1047                         core_dc, set, stream_count, context, core_dc->current_context);
1048         if (result != DC_OK){
1049                 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
1050                                         "%s: Context validation failed! dc_status:%d\n",
1051                                         __func__,
1052                                         result);
1053                 BREAK_TO_DEBUGGER();
1054                 dc_resource_validate_ctx_destruct(context);
1055                 goto fail;
1056         }
1057
1058         result = dc_commit_context_no_check(dc, context);
1059
1060         dc_resource_validate_ctx_destruct(context);
1061         dm_free(context);
1062
1063         return (result == DC_OK);
1064
1065 fail:
1066         dm_free(context);
1067
1068 context_alloc_fail:
1069         return (result == DC_OK);
1070 }
1071
1072 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1073 {
1074         int i;
1075         struct core_dc *core_dc = DC_TO_CORE(dc);
1076         struct validate_context *context = core_dc->current_context;
1077
1078         post_surface_trace(dc);
1079
1080         for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1081                 if (context->res_ctx.pipe_ctx[i].stream == NULL
1082                                 || context->res_ctx.pipe_ctx[i].surface == NULL)
1083                         core_dc->hwss.power_down_front_end(core_dc, i);
1084
1085         /* 3rd param should be true, temp w/a for RV*/
1086 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1087         core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1088 #else
1089         core_dc->hwss.set_bandwidth(core_dc, context, true);
1090 #endif
1091         return true;
1092 }
1093
1094 bool dc_commit_surfaces_to_stream(
1095                 struct dc *dc,
1096                 const struct dc_surface **new_surfaces,
1097                 uint8_t new_surface_count,
1098                 const struct dc_stream *dc_stream)
1099 {
1100         struct dc_surface_update updates[MAX_SURFACES];
1101         struct dc_flip_addrs flip_addr[MAX_SURFACES];
1102         struct dc_plane_info plane_info[MAX_SURFACES];
1103         struct dc_scaling_info scaling_info[MAX_SURFACES];
1104         int i;
1105         struct dc_stream_update *stream_update =
1106                         dm_alloc(sizeof(struct dc_stream_update));
1107
1108         if (!stream_update) {
1109                 BREAK_TO_DEBUGGER();
1110                 return false;
1111         }
1112
1113         memset(updates, 0, sizeof(updates));
1114         memset(flip_addr, 0, sizeof(flip_addr));
1115         memset(plane_info, 0, sizeof(plane_info));
1116         memset(scaling_info, 0, sizeof(scaling_info));
1117
1118         stream_update->src = dc_stream->src;
1119         stream_update->dst = dc_stream->dst;
1120
1121         for (i = 0; i < new_surface_count; i++) {
1122                 updates[i].surface = new_surfaces[i];
1123                 updates[i].gamma =
1124                         (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1125                 flip_addr[i].address = new_surfaces[i]->address;
1126                 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1127                 plane_info[i].color_space = new_surfaces[i]->color_space;
1128                 plane_info[i].format = new_surfaces[i]->format;
1129                 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1130                 plane_info[i].rotation = new_surfaces[i]->rotation;
1131                 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1132                 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1133                 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1134                 plane_info[i].visible = new_surfaces[i]->visible;
1135                 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1136                 plane_info[i].dcc = new_surfaces[i]->dcc;
1137                 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1138                 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1139                 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1140                 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1141
1142                 updates[i].flip_addr = &flip_addr[i];
1143                 updates[i].plane_info = &plane_info[i];
1144                 updates[i].scaling_info = &scaling_info[i];
1145         }
1146
1147         dc_update_surfaces_and_stream(
1148                         dc,
1149                         updates,
1150                         new_surface_count,
1151                         dc_stream, stream_update);
1152
1153         dc_post_update_surfaces_to_stream(dc);
1154
1155         dm_free(stream_update);
1156         return true;
1157 }
1158
1159 static bool is_surface_in_context(
1160                 const struct validate_context *context,
1161                 const struct dc_surface *surface)
1162 {
1163         int j;
1164
1165         for (j = 0; j < MAX_PIPES; j++) {
1166                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1167
1168                 if (surface == &pipe_ctx->surface->public) {
1169                         return true;
1170                 }
1171         }
1172
1173         return false;
1174 }
1175
1176 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1177 {
1178         switch (format) {
1179         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1180         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1181                 return 12;
1182         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1183         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1184         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1185         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1186                 return 16;
1187         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1188         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1189         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1190         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1191                 return 32;
1192         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1193         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1194         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1195                 return 64;
1196         default:
1197                 ASSERT_CRITICAL(false);
1198                 return -1;
1199         }
1200 }
1201
1202 static enum surface_update_type get_plane_info_update_type(
1203                 const struct dc_surface_update *u,
1204                 int surface_index)
1205 {
1206         struct dc_plane_info temp_plane_info;
1207         memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1208
1209         if (!u->plane_info)
1210                 return UPDATE_TYPE_FAST;
1211
1212         temp_plane_info = *u->plane_info;
1213
1214         /* Copy all parameters that will cause a full update
1215          * from current surface, the rest of the parameters
1216          * from provided plane configuration.
1217          * Perform memory compare and special validation
1218          * for those that can cause fast/medium updates
1219          */
1220
1221         /* Full update parameters */
1222         temp_plane_info.color_space = u->surface->color_space;
1223         temp_plane_info.dcc = u->surface->dcc;
1224         temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1225         temp_plane_info.plane_size = u->surface->plane_size;
1226         temp_plane_info.rotation = u->surface->rotation;
1227         temp_plane_info.stereo_format = u->surface->stereo_format;
1228         temp_plane_info.tiling_info = u->surface->tiling_info;
1229
1230         if (surface_index == 0)
1231                 temp_plane_info.visible = u->plane_info->visible;
1232         else
1233                 temp_plane_info.visible = u->surface->visible;
1234
1235         if (memcmp(u->plane_info, &temp_plane_info,
1236                         sizeof(struct dc_plane_info)) != 0)
1237                 return UPDATE_TYPE_FULL;
1238
1239         if (pixel_format_to_bpp(u->plane_info->format) !=
1240                         pixel_format_to_bpp(u->surface->format)) {
1241                 return UPDATE_TYPE_FULL;
1242         } else {
1243                 return UPDATE_TYPE_MED;
1244         }
1245 }
1246
1247 static enum surface_update_type  get_scaling_info_update_type(
1248                 const struct dc_surface_update *u)
1249 {
1250         if (!u->scaling_info)
1251                 return UPDATE_TYPE_FAST;
1252
1253         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1254                         || u->scaling_info->src_rect.height != u->surface->src_rect.height
1255                         || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1256                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1257                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1258                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1259                 return UPDATE_TYPE_FULL;
1260
1261         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1262                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1263                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1264                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1265                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1266                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1267                 return UPDATE_TYPE_MED;
1268
1269         return UPDATE_TYPE_FAST;
1270 }
1271
1272 static enum surface_update_type det_surface_update(
1273                 const struct core_dc *dc,
1274                 const struct dc_surface_update *u,
1275                 int surface_index)
1276 {
1277         const struct validate_context *context = dc->current_context;
1278         enum surface_update_type type = UPDATE_TYPE_FAST;
1279         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1280
1281         if (!is_surface_in_context(context, u->surface))
1282                 return UPDATE_TYPE_FULL;
1283
1284         type = get_plane_info_update_type(u, surface_index);
1285         if (overall_type < type)
1286                 overall_type = type;
1287
1288         type = get_scaling_info_update_type(u);
1289         if (overall_type < type)
1290                 overall_type = type;
1291
1292         if (u->in_transfer_func ||
1293                 u->hdr_static_metadata) {
1294                 if (overall_type < UPDATE_TYPE_MED)
1295                         overall_type = UPDATE_TYPE_MED;
1296         }
1297
1298         return overall_type;
1299 }
1300
1301 enum surface_update_type dc_check_update_surfaces_for_stream(
1302                 struct dc *dc,
1303                 struct dc_surface_update *updates,
1304                 int surface_count,
1305                 struct dc_stream_update *stream_update,
1306                 const struct dc_stream_status *stream_status)
1307 {
1308         struct core_dc *core_dc = DC_TO_CORE(dc);
1309         int i;
1310         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1311
1312         if (stream_status == NULL || stream_status->surface_count != surface_count)
1313                 return UPDATE_TYPE_FULL;
1314
1315         if (stream_update)
1316                 return UPDATE_TYPE_FULL;
1317
1318         for (i = 0 ; i < surface_count; i++) {
1319                 enum surface_update_type type =
1320                                 det_surface_update(core_dc, &updates[i], i);
1321
1322                 if (type == UPDATE_TYPE_FULL)
1323                         return type;
1324
1325                 if (overall_type < type)
1326                         overall_type = type;
1327         }
1328
1329         return overall_type;
1330 }
1331
1332 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1333
1334 void dc_update_surfaces_and_stream(struct dc *dc,
1335                 struct dc_surface_update *srf_updates, int surface_count,
1336                 const struct dc_stream *dc_stream,
1337                 struct dc_stream_update *stream_update)
1338 {
1339         struct core_dc *core_dc = DC_TO_CORE(dc);
1340         struct validate_context *context;
1341         int i, j;
1342         enum surface_update_type update_type;
1343         const struct dc_stream_status *stream_status;
1344         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1345
1346         stream_status = dc_stream_get_status(dc_stream);
1347         ASSERT(stream_status);
1348         if (!stream_status)
1349                 return; /* Cannot commit surface to stream that is not committed */
1350
1351 #ifdef ENABLE_FBC
1352         if (srf_updates->flip_addr) {
1353                 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1354                         ASSERT(0);
1355         }
1356 #endif
1357         context = core_dc->current_context;
1358
1359         /* update current stream with the new updates */
1360         if (stream_update) {
1361                 if ((stream_update->src.height != 0) &&
1362                                 (stream_update->src.width != 0))
1363                         stream->public.src = stream_update->src;
1364
1365                 if ((stream_update->dst.height != 0) &&
1366                                 (stream_update->dst.width != 0))
1367                         stream->public.dst = stream_update->dst;
1368
1369                 if (stream_update->out_transfer_func &&
1370                                 stream_update->out_transfer_func !=
1371                                                 dc_stream->out_transfer_func) {
1372                         if (dc_stream->out_transfer_func != NULL)
1373                                 dc_transfer_func_release(dc_stream->out_transfer_func);
1374                         dc_transfer_func_retain(stream_update->out_transfer_func);
1375                         stream->public.out_transfer_func =
1376                                 stream_update->out_transfer_func;
1377                 }
1378         }
1379
1380         /* do not perform surface update if surface has invalid dimensions
1381          * (all zero) and no scaling_info is provided
1382          */
1383         if (surface_count > 0 &&
1384                         srf_updates->surface->src_rect.width == 0 &&
1385                         srf_updates->surface->src_rect.height == 0 &&
1386                         srf_updates->surface->dst_rect.width == 0 &&
1387                         srf_updates->surface->dst_rect.height == 0 &&
1388                         !srf_updates->scaling_info) {
1389                 ASSERT(false);
1390                 return;
1391         }
1392
1393         update_type = dc_check_update_surfaces_for_stream(
1394                         dc, srf_updates, surface_count, stream_update, stream_status);
1395
1396         if (update_type >= update_surface_trace_level)
1397                 update_surface_trace(dc, srf_updates, surface_count);
1398
1399         if (update_type >= UPDATE_TYPE_FULL) {
1400                 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1401
1402                 for (i = 0; i < surface_count; i++)
1403                         new_surfaces[i] = srf_updates[i].surface;
1404
1405                 /* initialize scratch memory for building context */
1406                 context = dm_alloc(sizeof(*context));
1407                 dc_resource_validate_ctx_copy_construct(
1408                                 core_dc->current_context, context);
1409
1410                 /* add surface to context */
1411                 if (!resource_attach_surfaces_to_context(
1412                                 new_surfaces, surface_count, dc_stream,
1413                                 context, core_dc->res_pool)) {
1414                         BREAK_TO_DEBUGGER();
1415                         goto fail;
1416                 }
1417         }
1418
1419         /* save update parameters into surface */
1420         for (i = 0; i < surface_count; i++) {
1421                 struct core_surface *surface =
1422                                 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1423
1424                 if (srf_updates[i].flip_addr) {
1425                         surface->public.address = srf_updates[i].flip_addr->address;
1426                         surface->public.flip_immediate =
1427                                         srf_updates[i].flip_addr->flip_immediate;
1428                 }
1429
1430                 if (srf_updates[i].scaling_info) {
1431                         surface->public.scaling_quality =
1432                                         srf_updates[i].scaling_info->scaling_quality;
1433                         surface->public.dst_rect =
1434                                         srf_updates[i].scaling_info->dst_rect;
1435                         surface->public.src_rect =
1436                                         srf_updates[i].scaling_info->src_rect;
1437                         surface->public.clip_rect =
1438                                         srf_updates[i].scaling_info->clip_rect;
1439                 }
1440
1441                 if (srf_updates[i].plane_info) {
1442                         surface->public.color_space =
1443                                         srf_updates[i].plane_info->color_space;
1444                         surface->public.format =
1445                                         srf_updates[i].plane_info->format;
1446                         surface->public.plane_size =
1447                                         srf_updates[i].plane_info->plane_size;
1448                         surface->public.rotation =
1449                                         srf_updates[i].plane_info->rotation;
1450                         surface->public.horizontal_mirror =
1451                                         srf_updates[i].plane_info->horizontal_mirror;
1452                         surface->public.stereo_format =
1453                                         srf_updates[i].plane_info->stereo_format;
1454                         surface->public.tiling_info =
1455                                         srf_updates[i].plane_info->tiling_info;
1456                         surface->public.visible =
1457                                         srf_updates[i].plane_info->visible;
1458                         surface->public.per_pixel_alpha =
1459                                         srf_updates[i].plane_info->per_pixel_alpha;
1460                         surface->public.dcc =
1461                                         srf_updates[i].plane_info->dcc;
1462                 }
1463
1464                 if (update_type >= UPDATE_TYPE_MED) {
1465                         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1466                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1467
1468                                 if (pipe_ctx->surface != surface)
1469                                         continue;
1470
1471                                 resource_build_scaling_params(pipe_ctx);
1472                         }
1473                 }
1474
1475                 if (srf_updates[i].gamma &&
1476                         srf_updates[i].gamma != surface->public.gamma_correction) {
1477                         if (surface->public.gamma_correction != NULL)
1478                                 dc_gamma_release(&surface->public.
1479                                                 gamma_correction);
1480
1481                         dc_gamma_retain(srf_updates[i].gamma);
1482                         surface->public.gamma_correction =
1483                                                 srf_updates[i].gamma;
1484                 }
1485
1486                 if (srf_updates[i].in_transfer_func &&
1487                         srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1488                         if (surface->public.in_transfer_func != NULL)
1489                                 dc_transfer_func_release(
1490                                                 surface->public.
1491                                                 in_transfer_func);
1492
1493                         dc_transfer_func_retain(
1494                                         srf_updates[i].in_transfer_func);
1495                         surface->public.in_transfer_func =
1496                                         srf_updates[i].in_transfer_func;
1497                 }
1498
1499                 if (srf_updates[i].hdr_static_metadata)
1500                         surface->public.hdr_static_ctx =
1501                                 *(srf_updates[i].hdr_static_metadata);
1502         }
1503
1504         if (update_type == UPDATE_TYPE_FULL) {
1505                 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1506                         BREAK_TO_DEBUGGER();
1507                         goto fail;
1508                 } else {
1509                         core_dc->hwss.set_bandwidth(core_dc, context, false);
1510                         context_clock_trace(dc, context);
1511                 }
1512         }
1513
1514         if (surface_count == 0)
1515                 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1516
1517         /* Lock pipes for provided surfaces, or all active if full update*/
1518         for (i = 0; i < surface_count; i++) {
1519                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1520
1521                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1522                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1523
1524                         if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1525                                 continue;
1526                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1527                                 continue;
1528
1529                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1530                                 core_dc->hwss.pipe_control_lock(
1531                                                 core_dc,
1532                                                 pipe_ctx,
1533                                                 true);
1534                         }
1535                 }
1536                 if (update_type == UPDATE_TYPE_FULL)
1537                         break;
1538         }
1539
1540         /* Full fe update*/
1541         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1542                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1543                 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1544                 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1545                 struct dc_cursor_position position = { 0 };
1546
1547                 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1548                         continue;
1549
1550                 if (!pipe_ctx->top_pipe)
1551                         core_dc->hwss.apply_ctx_for_surface(
1552                                         core_dc, pipe_ctx->surface, context);
1553
1554                 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1555                 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1556
1557                 if (is_new_pipe_surface) {
1558                         core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1559                         core_dc->hwss.set_input_transfer_func(
1560                                         pipe_ctx, pipe_ctx->surface);
1561                         core_dc->hwss.set_output_transfer_func(
1562                                         pipe_ctx, pipe_ctx->stream);
1563                 }
1564         }
1565
1566         if (update_type > UPDATE_TYPE_FAST)
1567                 context_timing_trace(dc, &context->res_ctx);
1568
1569         /* Perform requested Updates */
1570         for (i = 0; i < surface_count; i++) {
1571                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1572
1573                 if (update_type == UPDATE_TYPE_MED)
1574                         core_dc->hwss.apply_ctx_for_surface(
1575                                         core_dc, surface, context);
1576
1577                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1578                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1579
1580                         if (pipe_ctx->surface != surface)
1581                                 continue;
1582
1583                         if (srf_updates[i].flip_addr)
1584                                 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1585
1586                         if (update_type == UPDATE_TYPE_FAST)
1587                                 continue;
1588
1589                         if (srf_updates[i].in_transfer_func)
1590                                 core_dc->hwss.set_input_transfer_func(
1591                                                 pipe_ctx, pipe_ctx->surface);
1592
1593                         if (stream_update != NULL &&
1594                                         stream_update->out_transfer_func != NULL) {
1595                                 core_dc->hwss.set_output_transfer_func(
1596                                                 pipe_ctx, pipe_ctx->stream);
1597                         }
1598
1599                         if (srf_updates[i].hdr_static_metadata) {
1600                                 resource_build_info_frame(pipe_ctx);
1601                                 core_dc->hwss.update_info_frame(pipe_ctx);
1602                         }
1603                 }
1604         }
1605
1606         /* Unlock pipes */
1607         for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1608                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1609
1610                 for (j = 0; j < surface_count; j++) {
1611                         if (update_type != UPDATE_TYPE_FULL &&
1612                                         srf_updates[j].surface != &pipe_ctx->surface->public)
1613                                 continue;
1614                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1615                                 continue;
1616
1617                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1618                                 core_dc->hwss.pipe_control_lock(
1619                                                 core_dc,
1620                                                 pipe_ctx,
1621                                                 false);
1622                         }
1623                         break;
1624                 }
1625         }
1626
1627         if (core_dc->current_context != context) {
1628                 dc_resource_validate_ctx_destruct(core_dc->current_context);
1629                 dm_free(core_dc->current_context);
1630
1631                 core_dc->current_context = context;
1632         }
1633         return;
1634
1635 fail:
1636         dc_resource_validate_ctx_destruct(context);
1637         dm_free(context);
1638 }
1639
1640 uint8_t dc_get_current_stream_count(const struct dc *dc)
1641 {
1642         struct core_dc *core_dc = DC_TO_CORE(dc);
1643         return core_dc->current_context->stream_count;
1644 }
1645
1646 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1647 {
1648         struct core_dc *core_dc = DC_TO_CORE(dc);
1649         if (i < core_dc->current_context->stream_count)
1650                 return &(core_dc->current_context->streams[i]->public);
1651         return NULL;
1652 }
1653
1654 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1655 {
1656         struct core_dc *core_dc = DC_TO_CORE(dc);
1657         return &core_dc->links[link_index]->public;
1658 }
1659
1660 const struct graphics_object_id dc_get_link_id_at_index(
1661         struct dc *dc, uint32_t link_index)
1662 {
1663         struct core_dc *core_dc = DC_TO_CORE(dc);
1664         return core_dc->links[link_index]->link_id;
1665 }
1666
1667 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1668         struct dc *dc, uint32_t link_index)
1669 {
1670         struct core_dc *core_dc = DC_TO_CORE(dc);
1671         return core_dc->links[link_index]->public.irq_source_hpd;
1672 }
1673
1674 const struct audio **dc_get_audios(struct dc *dc)
1675 {
1676         struct core_dc *core_dc = DC_TO_CORE(dc);
1677         return (const struct audio **)core_dc->res_pool->audios;
1678 }
1679
1680 enum dc_irq_source dc_interrupt_to_irq_source(
1681                 struct dc *dc,
1682                 uint32_t src_id,
1683                 uint32_t ext_id)
1684 {
1685         struct core_dc *core_dc = DC_TO_CORE(dc);
1686         return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1687 }
1688
1689 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1690 {
1691         struct core_dc *core_dc;
1692
1693         if (dc == NULL)
1694                 return;
1695         core_dc = DC_TO_CORE(dc);
1696
1697         dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1698 }
1699
1700 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1701 {
1702         struct core_dc *core_dc = DC_TO_CORE(dc);
1703         dal_irq_service_ack(core_dc->res_pool->irqs, src);
1704 }
1705
1706 void dc_set_power_state(
1707         struct dc *dc,
1708         enum dc_acpi_cm_power_state power_state)
1709 {
1710         struct core_dc *core_dc = DC_TO_CORE(dc);
1711
1712         switch (power_state) {
1713         case DC_ACPI_CM_POWER_STATE_D0:
1714                 core_dc->hwss.init_hw(core_dc);
1715                 break;
1716         default:
1717
1718                 core_dc->hwss.power_down(core_dc);
1719
1720                 /* Zero out the current context so that on resume we start with
1721                  * clean state, and dc hw programming optimizations will not
1722                  * cause any trouble.
1723                  */
1724                 memset(core_dc->current_context, 0,
1725                                 sizeof(*core_dc->current_context));
1726
1727                 break;
1728         }
1729
1730 }
1731
1732 void dc_resume(const struct dc *dc)
1733 {
1734         struct core_dc *core_dc = DC_TO_CORE(dc);
1735
1736         uint32_t i;
1737
1738         for (i = 0; i < core_dc->link_count; i++)
1739                 core_link_resume(core_dc->links[i]);
1740 }
1741
1742 bool dc_read_aux_dpcd(
1743                 struct dc *dc,
1744                 uint32_t link_index,
1745                 uint32_t address,
1746                 uint8_t *data,
1747                 uint32_t size)
1748 {
1749         struct core_dc *core_dc = DC_TO_CORE(dc);
1750
1751         struct core_link *link = core_dc->links[link_index];
1752         enum ddc_result r = dal_ddc_service_read_dpcd_data(
1753                         link->public.ddc,
1754                         false,
1755                         I2C_MOT_UNDEF,
1756                         address,
1757                         data,
1758                         size);
1759         return r == DDC_RESULT_SUCESSFULL;
1760 }
1761
1762 bool dc_write_aux_dpcd(
1763                 struct dc *dc,
1764                 uint32_t link_index,
1765                 uint32_t address,
1766                 const uint8_t *data,
1767                 uint32_t size)
1768 {
1769         struct core_dc *core_dc = DC_TO_CORE(dc);
1770         struct core_link *link = core_dc->links[link_index];
1771
1772         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1773                         link->public.ddc,
1774                         false,
1775                         I2C_MOT_UNDEF,
1776                         address,
1777                         data,
1778                         size);
1779         return r == DDC_RESULT_SUCESSFULL;
1780 }
1781
1782 bool dc_read_aux_i2c(
1783                 struct dc *dc,
1784                 uint32_t link_index,
1785                 enum i2c_mot_mode mot,
1786                 uint32_t address,
1787                 uint8_t *data,
1788                 uint32_t size)
1789 {
1790         struct core_dc *core_dc = DC_TO_CORE(dc);
1791
1792                 struct core_link *link = core_dc->links[link_index];
1793                 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1794                         link->public.ddc,
1795                         true,
1796                         mot,
1797                         address,
1798                         data,
1799                         size);
1800                 return r == DDC_RESULT_SUCESSFULL;
1801 }
1802
1803 bool dc_write_aux_i2c(
1804                 struct dc *dc,
1805                 uint32_t link_index,
1806                 enum i2c_mot_mode mot,
1807                 uint32_t address,
1808                 const uint8_t *data,
1809                 uint32_t size)
1810 {
1811         struct core_dc *core_dc = DC_TO_CORE(dc);
1812         struct core_link *link = core_dc->links[link_index];
1813
1814         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1815                         link->public.ddc,
1816                         true,
1817                         mot,
1818                         address,
1819                         data,
1820                         size);
1821         return r == DDC_RESULT_SUCESSFULL;
1822 }
1823
1824 bool dc_query_ddc_data(
1825                 struct dc *dc,
1826                 uint32_t link_index,
1827                 uint32_t address,
1828                 uint8_t *write_buf,
1829                 uint32_t write_size,
1830                 uint8_t *read_buf,
1831                 uint32_t read_size) {
1832
1833         struct core_dc *core_dc = DC_TO_CORE(dc);
1834
1835         struct core_link *link = core_dc->links[link_index];
1836
1837         bool result = dal_ddc_service_query_ddc_data(
1838                         link->public.ddc,
1839                         address,
1840                         write_buf,
1841                         write_size,
1842                         read_buf,
1843                         read_size);
1844
1845         return result;
1846 }
1847
1848 bool dc_submit_i2c(
1849                 struct dc *dc,
1850                 uint32_t link_index,
1851                 struct i2c_command *cmd)
1852 {
1853         struct core_dc *core_dc = DC_TO_CORE(dc);
1854
1855         struct core_link *link = core_dc->links[link_index];
1856         struct ddc_service *ddc = link->public.ddc;
1857
1858         return dal_i2caux_submit_i2c_command(
1859                 ddc->ctx->i2caux,
1860                 ddc->ddc_pin,
1861                 cmd);
1862 }
1863
1864 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1865 {
1866         struct dc_link *dc_link = &core_link->public;
1867
1868         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1869                 BREAK_TO_DEBUGGER();
1870                 return false;
1871         }
1872
1873         dc_sink_retain(sink);
1874
1875         dc_link->remote_sinks[dc_link->sink_count] = sink;
1876         dc_link->sink_count++;
1877
1878         return true;
1879 }
1880
1881 struct dc_sink *dc_link_add_remote_sink(
1882                 const struct dc_link *link,
1883                 const uint8_t *edid,
1884                 int len,
1885                 struct dc_sink_init_data *init_data)
1886 {
1887         struct dc_sink *dc_sink;
1888         enum dc_edid_status edid_status;
1889         struct core_link *core_link = DC_LINK_TO_LINK(link);
1890
1891         if (len > MAX_EDID_BUFFER_SIZE) {
1892                 dm_error("Max EDID buffer size breached!\n");
1893                 return NULL;
1894         }
1895
1896         if (!init_data) {
1897                 BREAK_TO_DEBUGGER();
1898                 return NULL;
1899         }
1900
1901         if (!init_data->link) {
1902                 BREAK_TO_DEBUGGER();
1903                 return NULL;
1904         }
1905
1906         dc_sink = dc_sink_create(init_data);
1907
1908         if (!dc_sink)
1909                 return NULL;
1910
1911         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1912         dc_sink->dc_edid.length = len;
1913
1914         if (!link_add_remote_sink_helper(
1915                         core_link,
1916                         dc_sink))
1917                 goto fail_add_sink;
1918
1919         edid_status = dm_helpers_parse_edid_caps(
1920                         core_link->ctx,
1921                         &dc_sink->dc_edid,
1922                         &dc_sink->edid_caps);
1923
1924         if (edid_status != EDID_OK)
1925                 goto fail;
1926
1927         return dc_sink;
1928 fail:
1929         dc_link_remove_remote_sink(link, dc_sink);
1930 fail_add_sink:
1931         dc_sink_release(dc_sink);
1932         return NULL;
1933 }
1934
1935 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1936 {
1937         struct core_link *core_link = DC_LINK_TO_LINK(link);
1938         struct dc_link *dc_link = &core_link->public;
1939
1940         dc_link->local_sink = sink;
1941
1942         if (sink == NULL) {
1943                 dc_link->type = dc_connection_none;
1944         } else {
1945                 dc_link->type = dc_connection_single;
1946         }
1947 }
1948
1949 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1950 {
1951         int i;
1952         struct core_link *core_link = DC_LINK_TO_LINK(link);
1953         struct dc_link *dc_link = &core_link->public;
1954
1955         if (!link->sink_count) {
1956                 BREAK_TO_DEBUGGER();
1957                 return;
1958         }
1959
1960         for (i = 0; i < dc_link->sink_count; i++) {
1961                 if (dc_link->remote_sinks[i] == sink) {
1962                         dc_sink_release(sink);
1963                         dc_link->remote_sinks[i] = NULL;
1964
1965                         /* shrink array to remove empty place */
1966                         while (i < dc_link->sink_count - 1) {
1967                                 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1968                                 i++;
1969                         }
1970                         dc_link->remote_sinks[i] = NULL;
1971                         dc_link->sink_count--;
1972                         return;
1973                 }
1974         }
1975 }
1976
1977 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1978 {
1979         int i;
1980         struct core_dc *core_dc = DC_TO_CORE(dc);
1981         struct mem_input *mi = NULL;
1982
1983         for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1984                 if (core_dc->res_pool->mis[i] != NULL) {
1985                         mi = core_dc->res_pool->mis[i];
1986                         break;
1987                 }
1988         }
1989         if (mi == NULL) {
1990                 dm_error("no mem_input!\n");
1991                 return false;
1992         }
1993
1994         if (mi->funcs->mem_input_update_dchub)
1995                 mi->funcs->mem_input_update_dchub(mi, dh_data);
1996         else
1997                 ASSERT(mi->funcs->mem_input_update_dchub);
1998
1999
2000         return true;
2001
2002 }
2003