drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32
  33 #include "resource.h"
  34
  35 #include "clock_source.h"
  36 #include "dc_bios_types.h"
  37
  38 #include "dce_calcs.h"
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "timing_generator.h"
  43 #include "virtual/virtual_link_encoder.h"
  44
  45 #include "link_hwss.h"
  46 #include "link_encoder.h"
  47
  48 #include "dc_link_ddc.h"
  49 #include "dm_helpers.h"
  50 #include "mem_input.h"
  51
  52 /*******************************************************************************
  53  * Private functions
  54  ******************************************************************************/
  55 static void destroy_links(struct core_dc *dc)
  56 {
  57         uint32_t i;
  58
  59         for (i = 0; i < dc->link_count; i++) {
  60                 if (NULL != dc->links[i])
  61                         link_destroy(&dc->links[i]);
  62         }
  63 }
  64
  65 static bool create_links(
  66                 struct core_dc *dc,
  67                 uint32_t num_virtual_links)
  68 {
  69         int i;
  70         int connectors_num;
  71         struct dc_bios *bios = dc->ctx->dc_bios;
  72
  73         dc->link_count = 0;
  74
  75         connectors_num = bios->funcs->get_connectors_number(bios);
  76
  77         if (connectors_num > ENUM_ID_COUNT) {
  78                 dm_error(
  79                         "DC: Number of connectors %d exceeds maximum of %d!\n",
  80                         connectors_num,
  81                         ENUM_ID_COUNT);
  82                 return false;
  83         }
  84
  85         if (connectors_num == 0 && num_virtual_links == 0) {
  86                 dm_error("DC: Number of connectors is zero!\n");
  87         }
  88
  89         dm_output_to_console(
  90                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
  91                 __func__,
  92                 connectors_num,
  93                 num_virtual_links);
  94
  95         for (i = 0; i < connectors_num; i++) {
  96                 struct link_init_data link_init_params = {0};
  97                 struct core_link *link;
  98
  99                 link_init_params.ctx = dc->ctx;
 100                 /* next BIOS object table connector */
 101                 link_init_params.connector_index = i;
 102                 link_init_params.link_index = dc->link_count;
 103                 link_init_params.dc = dc;
 104                 link = link_create(&link_init_params);
 105
 106                 if (link) {
 107                         dc->links[dc->link_count] = link;
 108                         link->dc = dc;
 109                         ++dc->link_count;
 110                 }
 111         }
 112
 113         for (i = 0; i < num_virtual_links; i++) {
 114                 struct core_link *link = dm_alloc(sizeof(*link));
 115                 struct encoder_init_data enc_init = {0};
 116
 117                 if (link == NULL) {
 118                         BREAK_TO_DEBUGGER();
 119                         goto failed_alloc;
 120                 }
 121
 122                 link->ctx = dc->ctx;
 123                 link->dc = dc;
 124                 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
 125                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 126                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 127                 link->link_id.enum_id = ENUM_ID_1;
 128                 link->link_enc = dm_alloc(sizeof(*link->link_enc));
 129
 130                 enc_init.ctx = dc->ctx;
 131                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 132                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 133                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 134                 enc_init.connector = link->link_id;
 135                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 136                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 137                 enc_init.encoder.enum_id = ENUM_ID_1;
 138                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 139
 140                 link->public.link_index = dc->link_count;
 141                 dc->links[dc->link_count] = link;
 142                 dc->link_count++;
 143         }
 144
 145         return true;
 146
 147 failed_alloc:
 148         return false;
 149 }
 150
 151 static bool stream_adjust_vmin_vmax(struct dc *dc,
 152                 const struct dc_stream **stream, int num_streams,
 153                 int vmin, int vmax)
 154 {
 155         /* TODO: Support multiple streams */
 156         struct core_dc *core_dc = DC_TO_CORE(dc);
 157         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
 158         int i = 0;
 159         bool ret = false;
 160
 161         for (i = 0; i < MAX_PIPES; i++) {
 162                 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
 163
 164                 if (pipe->stream == core_stream && pipe->stream_enc) {
 165                         core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
 166
 167                         /* build and update the info frame */
 168                         resource_build_info_frame(pipe);
 169                         core_dc->hwss.update_info_frame(pipe);
 170
 171                         ret = true;
 172                 }
 173         }
 174         return ret;
 175 }
 176
 177 static bool stream_get_crtc_position(struct dc *dc,
 178                 const struct dc_stream **stream, int num_streams,
 179                 unsigned int *v_pos, unsigned int *nom_v_pos)
 180 {
 181         /* TODO: Support multiple streams */
 182         struct core_dc *core_dc = DC_TO_CORE(dc);
 183         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
 184         int i = 0;
 185         bool ret = false;
 186         struct crtc_position position;
 187
 188         for (i = 0; i < MAX_PIPES; i++) {
 189                 struct pipe_ctx *pipe =
 190                                 &core_dc->current_context->res_ctx.pipe_ctx[i];
 191
 192                 if (pipe->stream == core_stream && pipe->stream_enc) {
 193                         core_dc->hwss.get_position(&pipe, 1, &position);
 194
 195                         *v_pos = position.vertical_count;
 196                         *nom_v_pos = position.nominal_vcount;
 197                         ret = true;
 198                 }
 199         }
 200         return ret;
 201 }
 202
 203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
 204 {
 205         struct core_dc *core_dc = DC_TO_CORE(dc);
 206         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
 207         int i = 0;
 208         bool ret = false;
 209         struct pipe_ctx *pipes;
 210
 211         for (i = 0; i < MAX_PIPES; i++) {
 212                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
 213                                 == core_stream) {
 214
 215                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
 216                         core_dc->hwss.program_gamut_remap(pipes);
 217                         ret = true;
 218                 }
 219         }
 220
 221         return ret;
 222 }
 223
 224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
 225 {
 226         struct core_dc *core_dc = DC_TO_CORE(dc);
 227         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
 228         int i = 0;
 229         bool ret = false;
 230         struct pipe_ctx *pipes;
 231
 232         for (i = 0; i < MAX_PIPES; i++) {
 233                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
 234                                 == core_stream) {
 235
 236                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
 237                         core_dc->hwss.program_csc_matrix(pipes,
 238                         core_stream->public.output_color_space,
 239                         core_stream->public.csc_color_matrix.matrix);
 240                         ret = true;
 241                 }
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void set_static_screen_events(struct dc *dc,
 248                 const struct dc_stream **stream,
 249                 int num_streams,
 250                 const struct dc_static_screen_events *events)
 251 {
 252         struct core_dc *core_dc = DC_TO_CORE(dc);
 253         int i = 0;
 254         int j = 0;
 255         struct pipe_ctx *pipes_affected[MAX_PIPES];
 256         int num_pipes_affected = 0;
 257
 258         for (i = 0; i < num_streams; i++) {
 259                 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
 260
 261                 for (j = 0; j < MAX_PIPES; j++) {
 262                         if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
 263                                         == core_stream) {
 264                                 pipes_affected[num_pipes_affected++] =
 265                                                 &core_dc->current_context->res_ctx.pipe_ctx[j];
 266                         }
 267                 }
 268         }
 269
 270         core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 271 }
 272
 273 static void set_drive_settings(struct dc *dc,
 274                 struct link_training_settings *lt_settings,
 275                 const struct dc_link *link)
 276 {
 277         struct core_dc *core_dc = DC_TO_CORE(dc);
 278         int i;
 279
 280         for (i = 0; i < core_dc->link_count; i++) {
 281                 if (&core_dc->links[i]->public == link)
 282                         break;
 283         }
 284
 285         if (i >= core_dc->link_count)
 286                 ASSERT_CRITICAL(false);
 287
 288         dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
 289 }
 290
 291 static void perform_link_training(struct dc *dc,
 292                 struct dc_link_settings *link_setting,
 293                 bool skip_video_pattern)
 294 {
 295         struct core_dc *core_dc = DC_TO_CORE(dc);
 296         int i;
 297
 298         for (i = 0; i < core_dc->link_count; i++)
 299                 dc_link_dp_perform_link_training(
 300                         &core_dc->links[i]->public,
 301                         link_setting,
 302                         skip_video_pattern);
 303 }
 304
 305 static void set_preferred_link_settings(struct dc *dc,
 306                 struct dc_link_settings *link_setting,
 307                 const struct dc_link *link)
 308 {
 309         struct core_link *core_link = DC_LINK_TO_CORE(link);
 310
 311         core_link->public.preferred_link_setting =
 312                                 *link_setting;
 313         dp_retrain_link_dp_test(core_link, link_setting, false);
 314 }
 315
 316 static void enable_hpd(const struct dc_link *link)
 317 {
 318         dc_link_dp_enable_hpd(link);
 319 }
 320
 321 static void disable_hpd(const struct dc_link *link)
 322 {
 323         dc_link_dp_disable_hpd(link);
 324 }
 325
 326
 327 static void set_test_pattern(
 328                 const struct dc_link *link,
 329                 enum dp_test_pattern test_pattern,
 330                 const struct link_training_settings *p_link_settings,
 331                 const unsigned char *p_custom_pattern,
 332                 unsigned int cust_pattern_size)
 333 {
 334         if (link != NULL)
 335                 dc_link_dp_set_test_pattern(
 336                         link,
 337                         test_pattern,
 338                         p_link_settings,
 339                         p_custom_pattern,
 340                         cust_pattern_size);
 341 }
 342
 343 void set_dither_option(const struct dc_stream *dc_stream,
 344                 enum dc_dither_option option)
 345 {
 346         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
 347         struct bit_depth_reduction_params params;
 348         struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
 349         struct pipe_ctx *pipes =
 350                         core_link->dc->current_context->res_ctx.pipe_ctx;
 351
 352         memset(&params, 0, sizeof(params));
 353         if (!stream)
 354                 return;
 355         if (option > DITHER_OPTION_MAX)
 356                 return;
 357         if (option == DITHER_OPTION_DEFAULT) {
 358                 switch (stream->public.timing.display_color_depth) {
 359                 case COLOR_DEPTH_666:
 360                         stream->public.dither_option = DITHER_OPTION_SPATIAL6;
 361                         break;
 362                 case COLOR_DEPTH_888:
 363                         stream->public.dither_option = DITHER_OPTION_SPATIAL8;
 364                         break;
 365                 case COLOR_DEPTH_101010:
 366                         stream->public.dither_option = DITHER_OPTION_SPATIAL10;
 367                         break;
 368                 default:
 369                         option = DITHER_OPTION_DISABLE;
 370                 }
 371         } else {
 372                 stream->public.dither_option = option;
 373         }
 374         resource_build_bit_depth_reduction_params(stream,
 375                                 &params);
 376         stream->bit_depth_params = params;
 377         pipes->opp->funcs->
 378                 opp_program_bit_depth_reduction(pipes->opp, &params);
 379 }
 380
 381 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
 382 {
 383         if (core_dc->hwss.set_drr != NULL) {
 384                 core_dc->public.stream_funcs.adjust_vmin_vmax =
 385                                 stream_adjust_vmin_vmax;
 386         }
 387
 388         core_dc->public.stream_funcs.set_static_screen_events =
 389                         set_static_screen_events;
 390
 391         core_dc->public.stream_funcs.get_crtc_position =
 392                         stream_get_crtc_position;
 393
 394         core_dc->public.stream_funcs.set_gamut_remap =
 395                         set_gamut_remap;
 396
 397         core_dc->public.stream_funcs.program_csc_matrix =
 398                         program_csc_matrix;
 399
 400         core_dc->public.stream_funcs.set_dither_option =
 401                         set_dither_option;
 402
 403         core_dc->public.link_funcs.set_drive_settings =
 404                         set_drive_settings;
 405
 406         core_dc->public.link_funcs.perform_link_training =
 407                         perform_link_training;
 408
 409         core_dc->public.link_funcs.set_preferred_link_settings =
 410                         set_preferred_link_settings;
 411
 412         core_dc->public.link_funcs.enable_hpd =
 413                         enable_hpd;
 414
 415         core_dc->public.link_funcs.disable_hpd =
 416                         disable_hpd;
 417
 418         core_dc->public.link_funcs.set_test_pattern =
 419                         set_test_pattern;
 420 }
 421
 422 static void destruct(struct core_dc *dc)
 423 {
 424         dc_release_validate_context(dc->current_context);
 425         dc->current_context = NULL;
 426
 427         destroy_links(dc);
 428
 429         dc_destroy_resource_pool(dc);
 430
 431         if (dc->ctx->gpio_service)
 432                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 433
 434         if (dc->ctx->i2caux)
 435                 dal_i2caux_destroy(&dc->ctx->i2caux);
 436
 437         if (dc->ctx->created_bios)
 438                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 439
 440         if (dc->ctx->logger)
 441                 dal_logger_destroy(&dc->ctx->logger);
 442
 443         dm_free(dc->ctx);
 444         dc->ctx = NULL;
 445 }
 446
 447 static bool construct(struct core_dc *dc,
 448                 const struct dc_init_data *init_params)
 449 {
 450         struct dal_logger *logger;
 451         struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
 452         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 453
 454         if (!dc_ctx) {
 455                 dm_error("%s: failed to create ctx\n", __func__);
 456                 goto ctx_fail;
 457         }
 458
 459         dc->current_context = dm_alloc(sizeof(*dc->current_context));
 460
 461         if (!dc->current_context) {
 462                 dm_error("%s: failed to create validate ctx\n", __func__);
 463                 goto val_ctx_fail;
 464         }
 465
 466         dc->current_context->ref_count++;
 467
 468         dc_ctx->cgs_device = init_params->cgs_device;
 469         dc_ctx->driver_context = init_params->driver;
 470         dc_ctx->dc = &dc->public;
 471         dc_ctx->asic_id = init_params->asic_id;
 472
 473         /* Create logger */
 474         logger = dal_logger_create(dc_ctx);
 475
 476         if (!logger) {
 477                 /* can *not* call logger. call base driver 'print error' */
 478                 dm_error("%s: failed to create Logger!\n", __func__);
 479                 goto logger_fail;
 480         }
 481         dc_ctx->logger = logger;
 482         dc->ctx = dc_ctx;
 483         dc->ctx->dce_environment = init_params->dce_environment;
 484
 485         dc_version = resource_parse_asic_id(init_params->asic_id);
 486         dc->ctx->dce_version = dc_version;
 487
 488         /* Resource should construct all asic specific resources.
 489          * This should be the only place where we need to parse the asic id
 490          */
 491         if (init_params->vbios_override)
 492                 dc_ctx->dc_bios = init_params->vbios_override;
 493         else {
 494                 /* Create BIOS parser */
 495                 struct bp_init_data bp_init_data;
 496
 497                 bp_init_data.ctx = dc_ctx;
 498                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 499
 500                 dc_ctx->dc_bios = dal_bios_parser_create(
 501                                 &bp_init_data, dc_version);
 502
 503                 if (!dc_ctx->dc_bios) {
 504                         ASSERT_CRITICAL(false);
 505                         goto bios_fail;
 506                 }
 507
 508                 dc_ctx->created_bios = true;
 509                 }
 510
 511         /* Create I2C AUX */
 512         dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
 513
 514         if (!dc_ctx->i2caux) {
 515                 ASSERT_CRITICAL(false);
 516                 goto failed_to_create_i2caux;
 517         }
 518
 519         /* Create GPIO service */
 520         dc_ctx->gpio_service = dal_gpio_service_create(
 521                         dc_version,
 522                         dc_ctx->dce_environment,
 523                         dc_ctx);
 524
 525         if (!dc_ctx->gpio_service) {
 526                 ASSERT_CRITICAL(false);
 527                 goto gpio_fail;
 528         }
 529
 530         dc->res_pool = dc_create_resource_pool(
 531                         dc,
 532                         init_params->num_virtual_links,
 533                         dc_version,
 534                         init_params->asic_id);
 535         if (!dc->res_pool)
 536                 goto create_resource_fail;
 537
 538         if (!create_links(dc, init_params->num_virtual_links))
 539                 goto create_links_fail;
 540
 541         allocate_dc_stream_funcs(dc);
 542
 543         return true;
 544
 545         /**** error handling here ****/
 546 create_links_fail:
 547 create_resource_fail:
 548 gpio_fail:
 549 failed_to_create_i2caux:
 550 bios_fail:
 551 logger_fail:
 552 val_ctx_fail:
 553 ctx_fail:
 554         destruct(dc);
 555         return false;
 556 }
 557
 558 /*
 559 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
 560 {
 561         fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
 562         unsigned int pixDurationInPico = round(pixel_duration);
 563
 564         DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
 565
 566         arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
 567         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
 568         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
 569
 570         arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
 571         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
 572         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
 573
 574         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
 575         WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
 576
 577         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
 578         WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
 579 }
 580 */
 581
 582 /*******************************************************************************
 583  * Public functions
 584  ******************************************************************************/
 585
 586 struct dc *dc_create(const struct dc_init_data *init_params)
 587  {
 588         struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
 589         unsigned int full_pipe_count;
 590
 591         if (NULL == core_dc)
 592                 goto alloc_fail;
 593
 594         if (false == construct(core_dc, init_params))
 595                 goto construct_fail;
 596
 597         /*TODO: separate HW and SW initialization*/
 598         core_dc->hwss.init_hw(core_dc);
 599
 600         full_pipe_count = core_dc->res_pool->pipe_count;
 601         if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 602                 full_pipe_count--;
 603         core_dc->public.caps.max_streams = min(
 604                         full_pipe_count,
 605                         core_dc->res_pool->stream_enc_count);
 606
 607         core_dc->public.caps.max_links = core_dc->link_count;
 608         core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
 609
 610         core_dc->public.config = init_params->flags;
 611
 612         dm_logger_write(core_dc->ctx->logger, LOG_DC,
 613                         "Display Core initialized\n");
 614
 615
 616         /* TODO: missing feature to be enabled */
 617         core_dc->public.debug.disable_dfs_bypass = true;
 618
 619         return &core_dc->public;
 620
 621 construct_fail:
 622         dm_free(core_dc);
 623
 624 alloc_fail:
 625         return NULL;
 626 }
 627
 628 void dc_destroy(struct dc **dc)
 629 {
 630         struct core_dc *core_dc = DC_TO_CORE(*dc);
 631         destruct(core_dc);
 632         dm_free(core_dc);
 633         *dc = NULL;
 634 }
 635
 636 static bool is_validation_required(
 637                 const struct core_dc *dc,
 638                 const struct dc_validation_set set[],
 639                 int set_count)
 640 {
 641         const struct validate_context *context = dc->current_context;
 642         int i, j;
 643
 644         if (context->stream_count != set_count)
 645                 return true;
 646
 647         for (i = 0; i < set_count; i++) {
 648
 649                 if (set[i].surface_count != context->stream_status[i].surface_count)
 650                         return true;
 651                 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
 652                         return true;
 653
 654                 for (j = 0; j < set[i].surface_count; j++) {
 655                         struct dc_surface temp_surf;
 656                         memset(&temp_surf, 0, sizeof(temp_surf));
 657
 658                         temp_surf = *context->stream_status[i].surfaces[j];
 659                         temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
 660                         temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
 661                         temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
 662
 663                         if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
 664                                 return true;
 665                 }
 666         }
 667
 668         return false;
 669 }
 670
 671 struct validate_context *dc_get_validate_context(
 672                 const struct dc *dc,
 673                 const struct dc_validation_set set[],
 674                 uint8_t set_count)
 675 {
 676         struct core_dc *core_dc = DC_TO_CORE(dc);
 677         enum dc_status result = DC_ERROR_UNEXPECTED;
 678         struct validate_context *context;
 679
 680         context = dm_alloc(sizeof(struct validate_context));
 681         if (context == NULL)
 682                 goto context_alloc_fail;
 683
 684         ++context->ref_count;
 685
 686         if (!is_validation_required(core_dc, set, set_count)) {
 687                 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
 688                 return context;
 689         }
 690
 691         result = core_dc->res_pool->funcs->validate_with_context(
 692                         core_dc, set, set_count, context, core_dc->current_context);
 693
 694 context_alloc_fail:
 695         if (result != DC_OK) {
 696                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 697                                 "%s:resource validation failed, dc_status:%d\n",
 698                                 __func__,
 699                                 result);
 700
 701                 dc_release_validate_context(context);
 702                 context = NULL;
 703         }
 704
 705         return context;
 706
 707 }
 708
 709 bool dc_validate_resources(
 710                 const struct dc *dc,
 711                 const struct dc_validation_set set[],
 712                 uint8_t set_count)
 713 {
 714         struct core_dc *core_dc = DC_TO_CORE(dc);
 715         enum dc_status result = DC_ERROR_UNEXPECTED;
 716         struct validate_context *context;
 717
 718         context = dm_alloc(sizeof(struct validate_context));
 719         if (context == NULL)
 720                 goto context_alloc_fail;
 721
 722         ++context->ref_count;
 723
 724         result = core_dc->res_pool->funcs->validate_with_context(
 725                                 core_dc, set, set_count, context, NULL);
 726
 727 context_alloc_fail:
 728         if (result != DC_OK) {
 729                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 730                                 "%s:resource validation failed, dc_status:%d\n",
 731                                 __func__,
 732                                 result);
 733         }
 734
 735         dc_release_validate_context(context);
 736         context = NULL;
 737
 738         return result == DC_OK;
 739 }
 740
 741 bool dc_validate_guaranteed(
 742                 const struct dc *dc,
 743                 const struct dc_stream *stream)
 744 {
 745         struct core_dc *core_dc = DC_TO_CORE(dc);
 746         enum dc_status result = DC_ERROR_UNEXPECTED;
 747         struct validate_context *context;
 748
 749         context = dm_alloc(sizeof(struct validate_context));
 750         if (context == NULL)
 751                 goto context_alloc_fail;
 752
 753         ++context->ref_count;
 754
 755         result = core_dc->res_pool->funcs->validate_guaranteed(
 756                                         core_dc, stream, context);
 757
 758         dc_release_validate_context(context);
 759
 760 context_alloc_fail:
 761         if (result != DC_OK) {
 762                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 763                         "%s:guaranteed validation failed, dc_status:%d\n",
 764                         __func__,
 765                         result);
 766                 }
 767
 768         return (result == DC_OK);
 769 }
 770
 771 static void program_timing_sync(
 772                 struct core_dc *core_dc,
 773                 struct validate_context *ctx)
 774 {
 775         int i, j;
 776         int group_index = 0;
 777         int pipe_count = core_dc->res_pool->pipe_count;
 778         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 779
 780         for (i = 0; i < pipe_count; i++) {
 781                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 782                         continue;
 783
 784                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 785         }
 786
 787         for (i = 0; i < pipe_count; i++) {
 788                 int group_size = 1;
 789                 struct pipe_ctx *pipe_set[MAX_PIPES];
 790
 791                 if (!unsynced_pipes[i])
 792                         continue;
 793
 794                 pipe_set[0] = unsynced_pipes[i];
 795                 unsynced_pipes[i] = NULL;
 796
 797                 /* Add tg to the set, search rest of the tg's for ones with
 798                  * same timing, add all tgs with same timing to the group
 799                  */
 800                 for (j = i + 1; j < pipe_count; j++) {
 801                         if (!unsynced_pipes[j])
 802                                 continue;
 803
 804                         if (resource_are_streams_timing_synchronizable(
 805                                         unsynced_pipes[j]->stream,
 806                                         pipe_set[0]->stream)) {
 807                                 pipe_set[group_size] = unsynced_pipes[j];
 808                                 unsynced_pipes[j] = NULL;
 809                                 group_size++;
 810                         }
 811                 }
 812
 813                 /* set first unblanked pipe as master */
 814                 for (j = 0; j < group_size; j++) {
 815                         struct pipe_ctx *temp;
 816
 817                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
 818                                 if (j == 0)
 819                                         break;
 820
 821                                 temp = pipe_set[0];
 822                                 pipe_set[0] = pipe_set[j];
 823                                 pipe_set[j] = temp;
 824                                 break;
 825                         }
 826                 }
 827
 828                 /* remove any other unblanked pipes as they have already been synced */
 829                 for (j = j + 1; j < group_size; j++) {
 830                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
 831                                 group_size--;
 832                                 pipe_set[j] = pipe_set[group_size];
 833                                 j--;
 834                         }
 835                 }
 836
 837                 if (group_size > 1) {
 838                         core_dc->hwss.enable_timing_synchronization(
 839                                 core_dc, group_index, group_size, pipe_set);
 840                         group_index++;
 841                 }
 842         }
 843 }
 844
 845 static bool context_changed(
 846                 struct core_dc *dc,
 847                 struct validate_context *context)
 848 {
 849         uint8_t i;
 850
 851         if (context->stream_count != dc->current_context->stream_count)
 852                 return true;
 853
 854         for (i = 0; i < dc->current_context->stream_count; i++) {
 855                 if (&dc->current_context->streams[i]->public != &context->streams[i]->public)
 856                         return true;
 857         }
 858
 859         return false;
 860 }
 861
 862 static bool streams_changed(
 863                 struct core_dc *dc,
 864                 const struct dc_stream *streams[],
 865                 uint8_t stream_count)
 866 {
 867         uint8_t i;
 868
 869         if (stream_count != dc->current_context->stream_count)
 870                 return true;
 871
 872         for (i = 0; i < dc->current_context->stream_count; i++) {
 873                 if (&dc->current_context->streams[i]->public != streams[i])
 874                         return true;
 875         }
 876
 877         return false;
 878 }
 879
 880 bool dc_enable_stereo(
 881         struct dc *dc,
 882         struct validate_context *context,
 883         const struct dc_stream *streams[],
 884         uint8_t stream_count)
 885 {
 886         bool ret = true;
 887         int i, j;
 888         struct pipe_ctx *pipe;
 889         struct core_dc *core_dc = DC_TO_CORE(dc);
 890
 891 #ifdef ENABLE_FBC
 892         struct compressor *fbc_compressor = core_dc->fbc_compressor;
 893 #endif
 894
 895         for (i = 0; i < MAX_PIPES; i++) {
 896                 if (context != NULL)
 897                         pipe = &context->res_ctx.pipe_ctx[i];
 898                 else
 899                         pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
 900                 for (j = 0 ; pipe && j < stream_count; j++)  {
 901                         if (streams[j] && streams[j] == &pipe->stream->public &&
 902                                 core_dc->hwss.setup_stereo)
 903                                 core_dc->hwss.setup_stereo(pipe, core_dc);
 904                 }
 905         }
 906
 907 #ifdef ENABLE_FBC
 908         if (fbc_compressor != NULL &&
 909             fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
 910                                                         &pipe->tg->inst))
 911                 fbc_compressor->funcs->disable_fbc(fbc_compressor);
 912
 913 #endif
 914         return ret;
 915 }
 916
 917
 918 /*
 919  * Applies given context to HW and copy it into current context.
 920  * It's up to the user to release the src context afterwards.
 921  */
 922 static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context)
 923 {
 924         struct core_dc *core_dc = DC_TO_CORE(dc);
 925         struct dc_bios *dcb = core_dc->ctx->dc_bios;
 926         enum dc_status result = DC_ERROR_UNEXPECTED;
 927         struct pipe_ctx *pipe;
 928         int i, j, k, l;
 929         const struct dc_stream *dc_streams[MAX_STREAMS] = {0};
 930
 931         for (i = 0; i < context->stream_count; i++)
 932                 dc_streams[i] =  &context->streams[i]->public;
 933
 934         if (!dcb->funcs->is_accelerated_mode(dcb))
 935                 core_dc->hwss.enable_accelerated_mode(core_dc);
 936
 937         for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
 938                 pipe = &context->res_ctx.pipe_ctx[i];
 939                 core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe);
 940         }
 941         result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
 942
 943         program_timing_sync(core_dc, context);
 944
 945         for (i = 0; i < context->stream_count; i++) {
 946                 const struct core_sink *sink = context->streams[i]->sink;
 947
 948                 for (j = 0; j < context->stream_status[i].surface_count; j++) {
 949                         const struct dc_surface *surface =
 950                                         context->stream_status[i].surfaces[j];
 951
 952                         core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
 953
 954                         /*
 955                          * enable stereo
 956                          * TODO rework dc_enable_stereo call to work with validation sets?
 957                          */
 958                         for (k = 0; k < MAX_PIPES; k++) {
 959                                 pipe = &context->res_ctx.pipe_ctx[k];
 960
 961                                 for (l = 0 ; pipe && l < context->stream_count; l++)  {
 962                                         if (context->streams[l] &&
 963                                             context->streams[l] == pipe->stream &&
 964                                             core_dc->hwss.setup_stereo)
 965                                                 core_dc->hwss.setup_stereo(pipe, core_dc);
 966                                 }
 967                         }
 968                 }
 969
 970                 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
 971                                 context->streams[i]->public.timing.h_addressable,
 972                                 context->streams[i]->public.timing.v_addressable,
 973                                 context->streams[i]->public.timing.h_total,
 974                                 context->streams[i]->public.timing.v_total,
 975                                 context->streams[i]->public.timing.pix_clk_khz);
 976         }
 977
 978         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 979
 980         dc_release_validate_context(core_dc->current_context);
 981
 982         core_dc->current_context = context;
 983
 984         dc_retain_validate_context(core_dc->current_context);
 985
 986         return (result == DC_OK);
 987 }
 988
 989 bool dc_commit_context(struct dc *dc, struct validate_context *context)
 990 {
 991         enum dc_status result = DC_ERROR_UNEXPECTED;
 992         struct core_dc *core_dc = DC_TO_CORE(dc);
 993         int i;
 994
 995         if (false == context_changed(core_dc, context))
 996                 return DC_OK;
 997
 998         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
 999                                 __func__, context->stream_count);
1000
1001         for (i = 0; i < context->stream_count; i++) {
1002                 const struct dc_stream *stream = &context->streams[i]->public;
1003
1004                 dc_stream_log(stream,
1005                                 core_dc->ctx->logger,
1006                                 LOG_DC);
1007         }
1008
1009         result = dc_commit_context_no_check(dc, context);
1010
1011         return (result == DC_OK);
1012 }
1013
1014
1015 bool dc_commit_streams(
1016         struct dc *dc,
1017         const struct dc_stream *streams[],
1018         uint8_t stream_count)
1019 {
1020         struct core_dc *core_dc = DC_TO_CORE(dc);
1021         enum dc_status result = DC_ERROR_UNEXPECTED;
1022         struct validate_context *context;
1023         struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
1024         int i;
1025
1026         if (false == streams_changed(core_dc, streams, stream_count))
1027                 return DC_OK;
1028
1029         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
1030                                 __func__, stream_count);
1031
1032         for (i = 0; i < stream_count; i++) {
1033                 const struct dc_stream *stream = streams[i];
1034                 const struct dc_stream_status *status = dc_stream_get_status(stream);
1035                 int j;
1036
1037                 dc_stream_log(stream,
1038                                 core_dc->ctx->logger,
1039                                 LOG_DC);
1040
1041                 set[i].stream = stream;
1042
1043                 if (status) {
1044                         set[i].surface_count = status->surface_count;
1045                         for (j = 0; j < status->surface_count; j++)
1046                                 set[i].surfaces[j] = status->surfaces[j];
1047                 }
1048
1049         }
1050
1051         context = dm_alloc(sizeof(struct validate_context));
1052         if (context == NULL)
1053                 goto context_alloc_fail;
1054
1055         ++context->ref_count;
1056
1057         result = core_dc->res_pool->funcs->validate_with_context(
1058                         core_dc, set, stream_count, context, core_dc->current_context);
1059         if (result != DC_OK){
1060                 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
1061                                         "%s: Context validation failed! dc_status:%d\n",
1062                                         __func__,
1063                                         result);
1064                 BREAK_TO_DEBUGGER();
1065                 goto fail;
1066         }
1067
1068         result = dc_commit_context_no_check(dc, context);
1069
1070 fail:
1071         dc_release_validate_context(context);
1072
1073 context_alloc_fail:
1074         return (result == DC_OK);
1075 }
1076
1077 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1078 {
1079         int i;
1080         struct core_dc *core_dc = DC_TO_CORE(dc);
1081         struct validate_context *context = core_dc->current_context;
1082
1083         post_surface_trace(dc);
1084
1085         for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1086                 if (context->res_ctx.pipe_ctx[i].stream == NULL
1087                                 || context->res_ctx.pipe_ctx[i].surface == NULL)
1088                         core_dc->hwss.power_down_front_end(core_dc, i);
1089
1090         /* 3rd param should be true, temp w/a for RV*/
1091 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1092         core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1093 #else
1094         core_dc->hwss.set_bandwidth(core_dc, context, true);
1095 #endif
1096         return true;
1097 }
1098
1099 bool dc_commit_surfaces_to_stream(
1100                 struct dc *dc,
1101                 struct dc_surface **new_surfaces,
1102                 uint8_t new_surface_count,
1103                 const struct dc_stream *dc_stream)
1104 {
1105         struct dc_surface_update updates[MAX_SURFACES];
1106         struct dc_flip_addrs flip_addr[MAX_SURFACES];
1107         struct dc_plane_info plane_info[MAX_SURFACES];
1108         struct dc_scaling_info scaling_info[MAX_SURFACES];
1109         int i;
1110         struct dc_stream_update *stream_update =
1111                         dm_alloc(sizeof(struct dc_stream_update));
1112
1113         if (!stream_update) {
1114                 BREAK_TO_DEBUGGER();
1115                 return false;
1116         }
1117
1118         memset(updates, 0, sizeof(updates));
1119         memset(flip_addr, 0, sizeof(flip_addr));
1120         memset(plane_info, 0, sizeof(plane_info));
1121         memset(scaling_info, 0, sizeof(scaling_info));
1122
1123         stream_update->src = dc_stream->src;
1124         stream_update->dst = dc_stream->dst;
1125         stream_update->out_transfer_func = dc_stream->out_transfer_func;
1126
1127         for (i = 0; i < new_surface_count; i++) {
1128                 updates[i].surface = new_surfaces[i];
1129                 updates[i].gamma =
1130                         (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1131                 updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func;
1132                 flip_addr[i].address = new_surfaces[i]->address;
1133                 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1134                 plane_info[i].color_space = new_surfaces[i]->color_space;
1135                 plane_info[i].format = new_surfaces[i]->format;
1136                 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1137                 plane_info[i].rotation = new_surfaces[i]->rotation;
1138                 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1139                 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1140                 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1141                 plane_info[i].visible = new_surfaces[i]->visible;
1142                 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1143                 plane_info[i].dcc = new_surfaces[i]->dcc;
1144                 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1145                 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1146                 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1147                 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1148
1149                 updates[i].flip_addr = &flip_addr[i];
1150                 updates[i].plane_info = &plane_info[i];
1151                 updates[i].scaling_info = &scaling_info[i];
1152         }
1153
1154         dc_update_surfaces_and_stream(
1155                         dc,
1156                         updates,
1157                         new_surface_count,
1158                         dc_stream, stream_update);
1159
1160         dc_post_update_surfaces_to_stream(dc);
1161
1162         dm_free(stream_update);
1163         return true;
1164 }
1165
1166 void dc_retain_validate_context(struct validate_context *context)
1167 {
1168         ASSERT(context->ref_count > 0);
1169         ++context->ref_count;
1170 }
1171
1172 void dc_release_validate_context(struct validate_context *context)
1173 {
1174         ASSERT(context->ref_count > 0);
1175         --context->ref_count;
1176
1177         if (context->ref_count == 0) {
1178                 dc_resource_validate_ctx_destruct(context);
1179                 dm_free(context);
1180         }
1181 }
1182
1183 static bool is_surface_in_context(
1184                 const struct validate_context *context,
1185                 const struct dc_surface *surface)
1186 {
1187         int j;
1188
1189         for (j = 0; j < MAX_PIPES; j++) {
1190                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1191
1192                 if (surface == pipe_ctx->surface) {
1193                         return true;
1194                 }
1195         }
1196
1197         return false;
1198 }
1199
1200 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1201 {
1202         switch (format) {
1203         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1204         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1205                 return 12;
1206         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1207         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1208         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1209         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1210                 return 16;
1211         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1212         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1213         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1214         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1215                 return 32;
1216         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1217         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1218         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1219                 return 64;
1220         default:
1221                 ASSERT_CRITICAL(false);
1222                 return -1;
1223         }
1224 }
1225
1226 static enum surface_update_type get_plane_info_update_type(
1227                 const struct dc_surface_update *u,
1228                 int surface_index)
1229 {
1230         struct dc_plane_info temp_plane_info;
1231         memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1232
1233         if (!u->plane_info)
1234                 return UPDATE_TYPE_FAST;
1235
1236         temp_plane_info = *u->plane_info;
1237
1238         /* Copy all parameters that will cause a full update
1239          * from current surface, the rest of the parameters
1240          * from provided plane configuration.
1241          * Perform memory compare and special validation
1242          * for those that can cause fast/medium updates
1243          */
1244
1245         /* Full update parameters */
1246         temp_plane_info.color_space = u->surface->color_space;
1247         temp_plane_info.dcc = u->surface->dcc;
1248         temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1249         temp_plane_info.plane_size = u->surface->plane_size;
1250         temp_plane_info.rotation = u->surface->rotation;
1251         temp_plane_info.stereo_format = u->surface->stereo_format;
1252         temp_plane_info.tiling_info = u->surface->tiling_info;
1253
1254         if (surface_index == 0)
1255                 temp_plane_info.visible = u->plane_info->visible;
1256         else
1257                 temp_plane_info.visible = u->surface->visible;
1258
1259         if (memcmp(u->plane_info, &temp_plane_info,
1260                         sizeof(struct dc_plane_info)) != 0)
1261                 return UPDATE_TYPE_FULL;
1262
1263         if (pixel_format_to_bpp(u->plane_info->format) !=
1264                         pixel_format_to_bpp(u->surface->format)) {
1265                 return UPDATE_TYPE_FULL;
1266         } else {
1267                 return UPDATE_TYPE_MED;
1268         }
1269 }
1270
1271 static enum surface_update_type  get_scaling_info_update_type(
1272                 const struct dc_surface_update *u)
1273 {
1274         if (!u->scaling_info)
1275                 return UPDATE_TYPE_FAST;
1276
1277         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1278                         || u->scaling_info->src_rect.height != u->surface->src_rect.height
1279                         || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1280                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1281                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1282                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1283                 return UPDATE_TYPE_FULL;
1284
1285         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1286                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1287                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1288                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1289                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1290                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1291                 return UPDATE_TYPE_MED;
1292
1293         return UPDATE_TYPE_FAST;
1294 }
1295
1296 static enum surface_update_type det_surface_update(
1297                 const struct core_dc *dc,
1298                 const struct dc_surface_update *u,
1299                 int surface_index)
1300 {
1301         const struct validate_context *context = dc->current_context;
1302         enum surface_update_type type = UPDATE_TYPE_FAST;
1303         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1304
1305         if (!is_surface_in_context(context, u->surface))
1306                 return UPDATE_TYPE_FULL;
1307
1308         type = get_plane_info_update_type(u, surface_index);
1309         if (overall_type < type)
1310                 overall_type = type;
1311
1312         type = get_scaling_info_update_type(u);
1313         if (overall_type < type)
1314                 overall_type = type;
1315
1316         if (u->in_transfer_func ||
1317                 u->hdr_static_metadata) {
1318                 if (overall_type < UPDATE_TYPE_MED)
1319                         overall_type = UPDATE_TYPE_MED;
1320         }
1321
1322         return overall_type;
1323 }
1324
1325 enum surface_update_type dc_check_update_surfaces_for_stream(
1326                 struct dc *dc,
1327                 struct dc_surface_update *updates,
1328                 int surface_count,
1329                 struct dc_stream_update *stream_update,
1330                 const struct dc_stream_status *stream_status)
1331 {
1332         struct core_dc *core_dc = DC_TO_CORE(dc);
1333         int i;
1334         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1335
1336         if (stream_status == NULL || stream_status->surface_count != surface_count)
1337                 return UPDATE_TYPE_FULL;
1338
1339         if (stream_update)
1340                 return UPDATE_TYPE_FULL;
1341
1342         for (i = 0 ; i < surface_count; i++) {
1343                 enum surface_update_type type =
1344                                 det_surface_update(core_dc, &updates[i], i);
1345
1346                 if (type == UPDATE_TYPE_FULL)
1347                         return type;
1348
1349                 if (overall_type < type)
1350                         overall_type = type;
1351         }
1352
1353         return overall_type;
1354 }
1355
1356 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1357
1358 void dc_update_surfaces_and_stream(struct dc *dc,
1359                 struct dc_surface_update *srf_updates, int surface_count,
1360                 const struct dc_stream *dc_stream,
1361                 struct dc_stream_update *stream_update)
1362 {
1363         struct core_dc *core_dc = DC_TO_CORE(dc);
1364         struct validate_context *context;
1365         int i, j;
1366         enum surface_update_type update_type;
1367         const struct dc_stream_status *stream_status;
1368         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1369         struct dc_context *dc_ctx = core_dc->ctx;
1370
1371         stream_status = dc_stream_get_status(dc_stream);
1372         ASSERT(stream_status);
1373         if (!stream_status)
1374                 return; /* Cannot commit surface to stream that is not committed */
1375
1376 #ifdef ENABLE_FBC
1377         if (srf_updates->flip_addr) {
1378                 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1379                         ASSERT(0);
1380         }
1381 #endif
1382         context = core_dc->current_context;
1383
1384         /* update current stream with the new updates */
1385         if (stream_update) {
1386                 if ((stream_update->src.height != 0) &&
1387                                 (stream_update->src.width != 0))
1388                         stream->public.src = stream_update->src;
1389
1390                 if ((stream_update->dst.height != 0) &&
1391                                 (stream_update->dst.width != 0))
1392                         stream->public.dst = stream_update->dst;
1393
1394                 if (stream_update->out_transfer_func &&
1395                                 stream_update->out_transfer_func !=
1396                                                 dc_stream->out_transfer_func) {
1397                         if (dc_stream->out_transfer_func != NULL)
1398                                 dc_transfer_func_release(dc_stream->out_transfer_func);
1399                         dc_transfer_func_retain(stream_update->out_transfer_func);
1400                         stream->public.out_transfer_func =
1401                                 stream_update->out_transfer_func;
1402                 }
1403         }
1404
1405         /* do not perform surface update if surface has invalid dimensions
1406          * (all zero) and no scaling_info is provided
1407          */
1408         if (surface_count > 0 &&
1409                         srf_updates->surface->src_rect.width == 0 &&
1410                         srf_updates->surface->src_rect.height == 0 &&
1411                         srf_updates->surface->dst_rect.width == 0 &&
1412                         srf_updates->surface->dst_rect.height == 0 &&
1413                         !srf_updates->scaling_info) {
1414                 ASSERT(false);
1415                 return;
1416         }
1417
1418         update_type = dc_check_update_surfaces_for_stream(
1419                         dc, srf_updates, surface_count, stream_update, stream_status);
1420
1421         if (update_type >= update_surface_trace_level)
1422                 update_surface_trace(dc, srf_updates, surface_count);
1423
1424         if (update_type >= UPDATE_TYPE_FULL) {
1425                 struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1426
1427                 for (i = 0; i < surface_count; i++)
1428                         new_surfaces[i] = srf_updates[i].surface;
1429
1430                 /* initialize scratch memory for building context */
1431                 context = dm_alloc(sizeof(*context));
1432                 if (context == NULL)
1433                                 goto context_alloc_fail;
1434
1435                 ++context->ref_count;
1436
1437                 dc_resource_validate_ctx_copy_construct(
1438                                 core_dc->current_context, context);
1439
1440                 /* add surface to context */
1441                 if (!resource_attach_surfaces_to_context(
1442                                 new_surfaces, surface_count, dc_stream,
1443                                 context, core_dc->res_pool)) {
1444                         BREAK_TO_DEBUGGER();
1445                         goto fail;
1446                 }
1447         }
1448
1449         /* save update parameters into surface */
1450         for (i = 0; i < surface_count; i++) {
1451                 struct dc_surface *surface = srf_updates[i].surface;
1452
1453                 if (srf_updates[i].flip_addr) {
1454                         surface->address = srf_updates[i].flip_addr->address;
1455                         surface->flip_immediate =
1456                                         srf_updates[i].flip_addr->flip_immediate;
1457                 }
1458
1459                 if (srf_updates[i].scaling_info) {
1460                         surface->scaling_quality =
1461                                         srf_updates[i].scaling_info->scaling_quality;
1462                         surface->dst_rect =
1463                                         srf_updates[i].scaling_info->dst_rect;
1464                         surface->src_rect =
1465                                         srf_updates[i].scaling_info->src_rect;
1466                         surface->clip_rect =
1467                                         srf_updates[i].scaling_info->clip_rect;
1468                 }
1469
1470                 if (srf_updates[i].plane_info) {
1471                         surface->color_space =
1472                                         srf_updates[i].plane_info->color_space;
1473                         surface->format =
1474                                         srf_updates[i].plane_info->format;
1475                         surface->plane_size =
1476                                         srf_updates[i].plane_info->plane_size;
1477                         surface->rotation =
1478                                         srf_updates[i].plane_info->rotation;
1479                         surface->horizontal_mirror =
1480                                         srf_updates[i].plane_info->horizontal_mirror;
1481                         surface->stereo_format =
1482                                         srf_updates[i].plane_info->stereo_format;
1483                         surface->tiling_info =
1484                                         srf_updates[i].plane_info->tiling_info;
1485                         surface->visible =
1486                                         srf_updates[i].plane_info->visible;
1487                         surface->per_pixel_alpha =
1488                                         srf_updates[i].plane_info->per_pixel_alpha;
1489                         surface->dcc =
1490                                         srf_updates[i].plane_info->dcc;
1491                 }
1492
1493                 if (update_type >= UPDATE_TYPE_MED) {
1494                         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1495                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1496
1497                                 if (pipe_ctx->surface != surface)
1498                                         continue;
1499
1500                                 resource_build_scaling_params(pipe_ctx);
1501                         }
1502                 }
1503
1504                 if (srf_updates[i].gamma &&
1505                         srf_updates[i].gamma != surface->gamma_correction) {
1506                         if (surface->gamma_correction != NULL)
1507                                 dc_gamma_release(&surface->
1508                                                 gamma_correction);
1509
1510                         dc_gamma_retain(srf_updates[i].gamma);
1511                         surface->gamma_correction =
1512                                                 srf_updates[i].gamma;
1513                 }
1514
1515                 if (srf_updates[i].in_transfer_func &&
1516                         srf_updates[i].in_transfer_func != surface->in_transfer_func) {
1517                         if (surface->in_transfer_func != NULL)
1518                                 dc_transfer_func_release(
1519                                                 surface->
1520                                                 in_transfer_func);
1521
1522                         dc_transfer_func_retain(
1523                                         srf_updates[i].in_transfer_func);
1524                         surface->in_transfer_func =
1525                                         srf_updates[i].in_transfer_func;
1526                 }
1527
1528                 if (srf_updates[i].hdr_static_metadata)
1529                         surface->hdr_static_ctx =
1530                                 *(srf_updates[i].hdr_static_metadata);
1531         }
1532
1533         if (update_type == UPDATE_TYPE_FULL) {
1534                 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1535                         BREAK_TO_DEBUGGER();
1536                         goto fail;
1537                 } else {
1538                         core_dc->hwss.set_bandwidth(core_dc, context, false);
1539                         context_clock_trace(dc, context);
1540                 }
1541         }
1542
1543         if (update_type > UPDATE_TYPE_FAST) {
1544                 for (i = 0; i < surface_count; i++) {
1545                         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1546                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1547
1548                                 if (pipe_ctx->surface != srf_updates[i].surface)
1549                                         continue;
1550
1551                                 core_dc->hwss.wait_for_mpcc_disconnect(core_dc->res_pool, pipe_ctx);
1552                         }
1553                 }
1554         }
1555
1556         if (surface_count == 0)
1557                 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1558
1559         /* Lock pipes for provided surfaces, or all active if full update*/
1560         for (i = 0; i < surface_count; i++) {
1561                 struct dc_surface *surface = srf_updates[i].surface;
1562
1563                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1564                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1565
1566                         if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1567                                 continue;
1568                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1569                                 continue;
1570
1571                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1572                                 core_dc->hwss.pipe_control_lock(
1573                                                 core_dc,
1574                                                 pipe_ctx,
1575                                                 true);
1576                         }
1577                 }
1578                 if (update_type == UPDATE_TYPE_FULL)
1579                         break;
1580         }
1581
1582         /* Full fe update*/
1583         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1584                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1585                 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1586                 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1587                 struct dc_cursor_position position = { 0 };
1588
1589                 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1590                         continue;
1591
1592                 if (!pipe_ctx->top_pipe)
1593                         core_dc->hwss.apply_ctx_for_surface(
1594                                         core_dc, pipe_ctx->surface, context);
1595
1596                 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1597                 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1598
1599                 if (is_new_pipe_surface) {
1600                         core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1601                         core_dc->hwss.set_input_transfer_func(
1602                                         pipe_ctx, pipe_ctx->surface);
1603                         core_dc->hwss.set_output_transfer_func(
1604                                         pipe_ctx, pipe_ctx->stream);
1605                 }
1606         }
1607
1608         if (update_type > UPDATE_TYPE_FAST)
1609                 context_timing_trace(dc, &context->res_ctx);
1610
1611         /* Perform requested Updates */
1612         for (i = 0; i < surface_count; i++) {
1613                 struct dc_surface *surface = srf_updates[i].surface;
1614
1615                 if (update_type == UPDATE_TYPE_MED)
1616                         core_dc->hwss.apply_ctx_for_surface(
1617                                         core_dc, surface, context);
1618
1619                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1620                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1621
1622                         if (pipe_ctx->surface != surface)
1623                                 continue;
1624
1625                         if (srf_updates[i].flip_addr)
1626                                 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1627
1628                         if (update_type == UPDATE_TYPE_FAST)
1629                                 continue;
1630
1631                         if (srf_updates[i].in_transfer_func)
1632                                 core_dc->hwss.set_input_transfer_func(
1633                                                 pipe_ctx, pipe_ctx->surface);
1634
1635                         if (stream_update != NULL &&
1636                                         stream_update->out_transfer_func != NULL) {
1637                                 core_dc->hwss.set_output_transfer_func(
1638                                                 pipe_ctx, pipe_ctx->stream);
1639                         }
1640
1641                         if (srf_updates[i].hdr_static_metadata) {
1642                                 resource_build_info_frame(pipe_ctx);
1643                                 core_dc->hwss.update_info_frame(pipe_ctx);
1644                         }
1645                 }
1646         }
1647
1648         /* Unlock pipes */
1649         for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1650                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1651
1652                 for (j = 0; j < surface_count; j++) {
1653                         if (update_type != UPDATE_TYPE_FULL &&
1654                             srf_updates[j].surface != pipe_ctx->surface)
1655                                 continue;
1656                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1657                                 continue;
1658
1659                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1660                                 core_dc->hwss.pipe_control_lock(
1661                                                 core_dc,
1662                                                 pipe_ctx,
1663                                                 false);
1664                         }
1665                         break;
1666                 }
1667         }
1668
1669         if (core_dc->current_context != context) {
1670                 dc_release_validate_context(core_dc->current_context);
1671                 core_dc->current_context = context;
1672         }
1673         return;
1674
1675 fail:
1676         dc_release_validate_context(context);
1677
1678 context_alloc_fail:
1679         DC_ERROR("Failed to allocate new validate context!\n");
1680 }
1681
1682 uint8_t dc_get_current_stream_count(const struct dc *dc)
1683 {
1684         struct core_dc *core_dc = DC_TO_CORE(dc);
1685         return core_dc->current_context->stream_count;
1686 }
1687
1688 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1689 {
1690         struct core_dc *core_dc = DC_TO_CORE(dc);
1691         if (i < core_dc->current_context->stream_count)
1692                 return &(core_dc->current_context->streams[i]->public);
1693         return NULL;
1694 }
1695
1696 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1697 {
1698         struct core_dc *core_dc = DC_TO_CORE(dc);
1699         return &core_dc->links[link_index]->public;
1700 }
1701
1702 const struct graphics_object_id dc_get_link_id_at_index(
1703         struct dc *dc, uint32_t link_index)
1704 {
1705         struct core_dc *core_dc = DC_TO_CORE(dc);
1706         return core_dc->links[link_index]->link_id;
1707 }
1708
1709 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1710         struct dc *dc, uint32_t link_index)
1711 {
1712         struct core_dc *core_dc = DC_TO_CORE(dc);
1713         return core_dc->links[link_index]->public.irq_source_hpd;
1714 }
1715
1716 const struct audio **dc_get_audios(struct dc *dc)
1717 {
1718         struct core_dc *core_dc = DC_TO_CORE(dc);
1719         return (const struct audio **)core_dc->res_pool->audios;
1720 }
1721
1722 enum dc_irq_source dc_interrupt_to_irq_source(
1723                 struct dc *dc,
1724                 uint32_t src_id,
1725                 uint32_t ext_id)
1726 {
1727         struct core_dc *core_dc = DC_TO_CORE(dc);
1728         return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1729 }
1730
1731 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1732 {
1733         struct core_dc *core_dc;
1734
1735         if (dc == NULL)
1736                 return;
1737         core_dc = DC_TO_CORE(dc);
1738
1739         dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1740 }
1741
1742 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1743 {
1744         struct core_dc *core_dc = DC_TO_CORE(dc);
1745         dal_irq_service_ack(core_dc->res_pool->irqs, src);
1746 }
1747
1748 void dc_set_power_state(
1749         struct dc *dc,
1750         enum dc_acpi_cm_power_state power_state)
1751 {
1752         struct core_dc *core_dc = DC_TO_CORE(dc);
1753         int ref_count;
1754
1755         switch (power_state) {
1756         case DC_ACPI_CM_POWER_STATE_D0:
1757                 core_dc->hwss.init_hw(core_dc);
1758                 break;
1759         default:
1760
1761                 core_dc->hwss.power_down(core_dc);
1762
1763                 /* Zero out the current context so that on resume we start with
1764                  * clean state, and dc hw programming optimizations will not
1765                  * cause any trouble.
1766                  */
1767
1768                 /* Preserve refcount */
1769                 ref_count = core_dc->current_context->ref_count;
1770                 dc_resource_validate_ctx_destruct(core_dc->current_context);
1771                 memset(core_dc->current_context, 0,
1772                                 sizeof(*core_dc->current_context));
1773                 core_dc->current_context->ref_count = ref_count;
1774
1775                 break;
1776         }
1777
1778 }
1779
1780 void dc_resume(const struct dc *dc)
1781 {
1782         struct core_dc *core_dc = DC_TO_CORE(dc);
1783
1784         uint32_t i;
1785
1786         for (i = 0; i < core_dc->link_count; i++)
1787                 core_link_resume(core_dc->links[i]);
1788 }
1789
1790 bool dc_read_aux_dpcd(
1791                 struct dc *dc,
1792                 uint32_t link_index,
1793                 uint32_t address,
1794                 uint8_t *data,
1795                 uint32_t size)
1796 {
1797         struct core_dc *core_dc = DC_TO_CORE(dc);
1798
1799         struct core_link *link = core_dc->links[link_index];
1800         enum ddc_result r = dal_ddc_service_read_dpcd_data(
1801                         link->public.ddc,
1802                         false,
1803                         I2C_MOT_UNDEF,
1804                         address,
1805                         data,
1806                         size);
1807         return r == DDC_RESULT_SUCESSFULL;
1808 }
1809
1810 bool dc_write_aux_dpcd(
1811                 struct dc *dc,
1812                 uint32_t link_index,
1813                 uint32_t address,
1814                 const uint8_t *data,
1815                 uint32_t size)
1816 {
1817         struct core_dc *core_dc = DC_TO_CORE(dc);
1818         struct core_link *link = core_dc->links[link_index];
1819
1820         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1821                         link->public.ddc,
1822                         false,
1823                         I2C_MOT_UNDEF,
1824                         address,
1825                         data,
1826                         size);
1827         return r == DDC_RESULT_SUCESSFULL;
1828 }
1829
1830 bool dc_read_aux_i2c(
1831                 struct dc *dc,
1832                 uint32_t link_index,
1833                 enum i2c_mot_mode mot,
1834                 uint32_t address,
1835                 uint8_t *data,
1836                 uint32_t size)
1837 {
1838         struct core_dc *core_dc = DC_TO_CORE(dc);
1839
1840                 struct core_link *link = core_dc->links[link_index];
1841                 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1842                         link->public.ddc,
1843                         true,
1844                         mot,
1845                         address,
1846                         data,
1847                         size);
1848                 return r == DDC_RESULT_SUCESSFULL;
1849 }
1850
1851 bool dc_write_aux_i2c(
1852                 struct dc *dc,
1853                 uint32_t link_index,
1854                 enum i2c_mot_mode mot,
1855                 uint32_t address,
1856                 const uint8_t *data,
1857                 uint32_t size)
1858 {
1859         struct core_dc *core_dc = DC_TO_CORE(dc);
1860         struct core_link *link = core_dc->links[link_index];
1861
1862         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1863                         link->public.ddc,
1864                         true,
1865                         mot,
1866                         address,
1867                         data,
1868                         size);
1869         return r == DDC_RESULT_SUCESSFULL;
1870 }
1871
1872 bool dc_query_ddc_data(
1873                 struct dc *dc,
1874                 uint32_t link_index,
1875                 uint32_t address,
1876                 uint8_t *write_buf,
1877                 uint32_t write_size,
1878                 uint8_t *read_buf,
1879                 uint32_t read_size) {
1880
1881         struct core_dc *core_dc = DC_TO_CORE(dc);
1882
1883         struct core_link *link = core_dc->links[link_index];
1884
1885         bool result = dal_ddc_service_query_ddc_data(
1886                         link->public.ddc,
1887                         address,
1888                         write_buf,
1889                         write_size,
1890                         read_buf,
1891                         read_size);
1892
1893         return result;
1894 }
1895
1896 bool dc_submit_i2c(
1897                 struct dc *dc,
1898                 uint32_t link_index,
1899                 struct i2c_command *cmd)
1900 {
1901         struct core_dc *core_dc = DC_TO_CORE(dc);
1902
1903         struct core_link *link = core_dc->links[link_index];
1904         struct ddc_service *ddc = link->public.ddc;
1905
1906         return dal_i2caux_submit_i2c_command(
1907                 ddc->ctx->i2caux,
1908                 ddc->ddc_pin,
1909                 cmd);
1910 }
1911
1912 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1913 {
1914         struct dc_link *dc_link = &core_link->public;
1915
1916         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1917                 BREAK_TO_DEBUGGER();
1918                 return false;
1919         }
1920
1921         dc_sink_retain(sink);
1922
1923         dc_link->remote_sinks[dc_link->sink_count] = sink;
1924         dc_link->sink_count++;
1925
1926         return true;
1927 }
1928
1929 struct dc_sink *dc_link_add_remote_sink(
1930                 const struct dc_link *link,
1931                 const uint8_t *edid,
1932                 int len,
1933                 struct dc_sink_init_data *init_data)
1934 {
1935         struct dc_sink *dc_sink;
1936         enum dc_edid_status edid_status;
1937         struct core_link *core_link = DC_LINK_TO_LINK(link);
1938
1939         if (len > MAX_EDID_BUFFER_SIZE) {
1940                 dm_error("Max EDID buffer size breached!\n");
1941                 return NULL;
1942         }
1943
1944         if (!init_data) {
1945                 BREAK_TO_DEBUGGER();
1946                 return NULL;
1947         }
1948
1949         if (!init_data->link) {
1950                 BREAK_TO_DEBUGGER();
1951                 return NULL;
1952         }
1953
1954         dc_sink = dc_sink_create(init_data);
1955
1956         if (!dc_sink)
1957                 return NULL;
1958
1959         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1960         dc_sink->dc_edid.length = len;
1961
1962         if (!link_add_remote_sink_helper(
1963                         core_link,
1964                         dc_sink))
1965                 goto fail_add_sink;
1966
1967         edid_status = dm_helpers_parse_edid_caps(
1968                         core_link->ctx,
1969                         &dc_sink->dc_edid,
1970                         &dc_sink->edid_caps);
1971
1972         if (edid_status != EDID_OK)
1973                 goto fail;
1974
1975         return dc_sink;
1976 fail:
1977         dc_link_remove_remote_sink(link, dc_sink);
1978 fail_add_sink:
1979         dc_sink_release(dc_sink);
1980         return NULL;
1981 }
1982
1983 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1984 {
1985         struct core_link *core_link = DC_LINK_TO_LINK(link);
1986         struct dc_link *dc_link = &core_link->public;
1987
1988         dc_link->local_sink = sink;
1989
1990         if (sink == NULL) {
1991                 dc_link->type = dc_connection_none;
1992         } else {
1993                 dc_link->type = dc_connection_single;
1994         }
1995 }
1996
1997 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1998 {
1999         int i;
2000         struct core_link *core_link = DC_LINK_TO_LINK(link);
2001         struct dc_link *dc_link = &core_link->public;
2002
2003         if (!link->sink_count) {
2004                 BREAK_TO_DEBUGGER();
2005                 return;
2006         }
2007
2008         for (i = 0; i < dc_link->sink_count; i++) {
2009                 if (dc_link->remote_sinks[i] == sink) {
2010                         dc_sink_release(sink);
2011                         dc_link->remote_sinks[i] = NULL;
2012
2013                         /* shrink array to remove empty place */
2014                         while (i < dc_link->sink_count - 1) {
2015                                 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
2016                                 i++;
2017                         }
2018                         dc_link->remote_sinks[i] = NULL;
2019                         dc_link->sink_count--;
2020                         return;
2021                 }
2022         }
2023 }
2024
2025 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
2026 {
2027         int i;
2028         struct core_dc *core_dc = DC_TO_CORE(dc);
2029         struct mem_input *mi = NULL;
2030
2031         for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
2032                 if (core_dc->res_pool->mis[i] != NULL) {
2033                         mi = core_dc->res_pool->mis[i];
2034                         break;
2035                 }
2036         }
2037         if (mi == NULL) {
2038                 dm_error("no mem_input!\n");
2039                 return false;
2040         }
2041
2042         if (core_dc->hwss.update_dchub)
2043                 core_dc->hwss.update_dchub(core_dc->hwseq, dh_data);
2044         else
2045                 ASSERT(core_dc->hwss.update_dchub);
2046
2047
2048         return true;
2049
2050 }
2051
2052 void dc_log_hw_state(struct dc *dc)
2053 {
2054         struct core_dc *core_dc = DC_TO_CORE(dc);
2055
2056         if (core_dc->hwss.log_hw_state)
2057                 core_dc->hwss.log_hw_state(core_dc);
2058 }