2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
45 #include "link_hwss.h"
46 #include "link_encoder.h"
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
52 /*******************************************************************************
54 ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
59 for (i = 0; i < dc->link_count; i++) {
60 if (NULL != dc->links[i])
61 link_destroy(&dc->links[i]);
65 static bool create_links(
67 uint32_t num_virtual_links)
71 struct dc_bios *bios = dc->ctx->dc_bios;
75 connectors_num = bios->funcs->get_connectors_number(bios);
77 if (connectors_num > ENUM_ID_COUNT) {
79 "DC: Number of connectors %d exceeds maximum of %d!\n",
85 if (connectors_num == 0 && num_virtual_links == 0) {
86 dm_error("DC: Number of connectors is zero!\n");
90 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
95 for (i = 0; i < connectors_num; i++) {
96 struct link_init_data link_init_params = {0};
97 struct core_link *link;
99 link_init_params.ctx = dc->ctx;
100 /* next BIOS object table connector */
101 link_init_params.connector_index = i;
102 link_init_params.link_index = dc->link_count;
103 link_init_params.dc = dc;
104 link = link_create(&link_init_params);
107 dc->links[dc->link_count] = link;
113 for (i = 0; i < num_virtual_links; i++) {
114 struct core_link *link = dm_alloc(sizeof(*link));
115 struct encoder_init_data enc_init = {0};
124 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127 link->link_id.enum_id = ENUM_ID_1;
128 link->link_enc = dm_alloc(sizeof(*link->link_enc));
130 enc_init.ctx = dc->ctx;
131 enc_init.channel = CHANNEL_ID_UNKNOWN;
132 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134 enc_init.connector = link->link_id;
135 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137 enc_init.encoder.enum_id = ENUM_ID_1;
138 virtual_link_encoder_construct(link->link_enc, &enc_init);
140 link->public.link_index = dc->link_count;
141 dc->links[dc->link_count] = link;
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152 const struct dc_stream **stream, int num_streams,
155 /* TODO: Support multiple streams */
156 struct core_dc *core_dc = DC_TO_CORE(dc);
157 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
161 for (i = 0; i < MAX_PIPES; i++) {
162 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
164 if (pipe->stream == core_stream && pipe->stream_enc) {
165 core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
167 /* build and update the info frame */
168 resource_build_info_frame(pipe);
169 core_dc->hwss.update_info_frame(pipe);
177 static bool stream_get_crtc_position(struct dc *dc,
178 const struct dc_stream **stream, int num_streams,
179 unsigned int *v_pos, unsigned int *nom_v_pos)
181 /* TODO: Support multiple streams */
182 struct core_dc *core_dc = DC_TO_CORE(dc);
183 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
186 struct crtc_position position;
188 for (i = 0; i < MAX_PIPES; i++) {
189 struct pipe_ctx *pipe =
190 &core_dc->current_context->res_ctx.pipe_ctx[i];
192 if (pipe->stream == core_stream && pipe->stream_enc) {
193 core_dc->hwss.get_position(&pipe, 1, &position);
195 *v_pos = position.vertical_count;
196 *nom_v_pos = position.nominal_vcount;
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
205 struct core_dc *core_dc = DC_TO_CORE(dc);
206 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
209 struct pipe_ctx *pipes;
211 for (i = 0; i < MAX_PIPES; i++) {
212 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
215 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216 core_dc->hwss.program_gamut_remap(pipes);
224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
226 struct core_dc *core_dc = DC_TO_CORE(dc);
227 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
230 struct pipe_ctx *pipes;
232 for (i = 0; i < MAX_PIPES; i++) {
233 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
236 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
237 core_dc->hwss.program_csc_matrix(pipes,
238 core_stream->public.output_color_space,
239 core_stream->public.csc_color_matrix.matrix);
247 static void set_static_screen_events(struct dc *dc,
248 const struct dc_stream **stream,
250 const struct dc_static_screen_events *events)
252 struct core_dc *core_dc = DC_TO_CORE(dc);
255 struct pipe_ctx *pipes_affected[MAX_PIPES];
256 int num_pipes_affected = 0;
258 for (i = 0; i < num_streams; i++) {
259 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
261 for (j = 0; j < MAX_PIPES; j++) {
262 if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
264 pipes_affected[num_pipes_affected++] =
265 &core_dc->current_context->res_ctx.pipe_ctx[j];
270 core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
273 static void set_drive_settings(struct dc *dc,
274 struct link_training_settings *lt_settings,
275 const struct dc_link *link)
277 struct core_dc *core_dc = DC_TO_CORE(dc);
280 for (i = 0; i < core_dc->link_count; i++) {
281 if (&core_dc->links[i]->public == link)
285 if (i >= core_dc->link_count)
286 ASSERT_CRITICAL(false);
288 dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
291 static void perform_link_training(struct dc *dc,
292 struct dc_link_settings *link_setting,
293 bool skip_video_pattern)
295 struct core_dc *core_dc = DC_TO_CORE(dc);
298 for (i = 0; i < core_dc->link_count; i++)
299 dc_link_dp_perform_link_training(
300 &core_dc->links[i]->public,
305 static void set_preferred_link_settings(struct dc *dc,
306 struct dc_link_settings *link_setting,
307 const struct dc_link *link)
309 struct core_link *core_link = DC_LINK_TO_CORE(link);
311 core_link->public.verified_link_cap.lane_count =
312 link_setting->lane_count;
313 core_link->public.verified_link_cap.link_rate =
314 link_setting->link_rate;
315 dp_retrain_link_dp_test(core_link, link_setting, false);
318 static void enable_hpd(const struct dc_link *link)
320 dc_link_dp_enable_hpd(link);
323 static void disable_hpd(const struct dc_link *link)
325 dc_link_dp_disable_hpd(link);
329 static void set_test_pattern(
330 const struct dc_link *link,
331 enum dp_test_pattern test_pattern,
332 const struct link_training_settings *p_link_settings,
333 const unsigned char *p_custom_pattern,
334 unsigned int cust_pattern_size)
337 dc_link_dp_set_test_pattern(
345 void set_dither_option(const struct dc_stream *dc_stream,
346 enum dc_dither_option option)
348 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
349 struct bit_depth_reduction_params params;
350 struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
351 struct pipe_ctx *pipes =
352 core_link->dc->current_context->res_ctx.pipe_ctx;
354 memset(¶ms, 0, sizeof(params));
357 if (option > DITHER_OPTION_MAX)
359 if (option == DITHER_OPTION_DEFAULT) {
360 switch (stream->public.timing.display_color_depth) {
361 case COLOR_DEPTH_666:
362 stream->public.dither_option = DITHER_OPTION_SPATIAL6;
364 case COLOR_DEPTH_888:
365 stream->public.dither_option = DITHER_OPTION_SPATIAL8;
367 case COLOR_DEPTH_101010:
368 stream->public.dither_option = DITHER_OPTION_SPATIAL10;
371 option = DITHER_OPTION_DISABLE;
374 stream->public.dither_option = option;
376 resource_build_bit_depth_reduction_params(stream,
378 stream->bit_depth_params = params;
380 opp_program_bit_depth_reduction(pipes->opp, ¶ms);
383 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
385 if (core_dc->hwss.set_drr != NULL) {
386 core_dc->public.stream_funcs.adjust_vmin_vmax =
387 stream_adjust_vmin_vmax;
390 core_dc->public.stream_funcs.set_static_screen_events =
391 set_static_screen_events;
393 core_dc->public.stream_funcs.get_crtc_position =
394 stream_get_crtc_position;
396 core_dc->public.stream_funcs.set_gamut_remap =
399 core_dc->public.stream_funcs.program_csc_matrix =
402 core_dc->public.stream_funcs.set_dither_option =
405 core_dc->public.link_funcs.set_drive_settings =
408 core_dc->public.link_funcs.perform_link_training =
409 perform_link_training;
411 core_dc->public.link_funcs.set_preferred_link_settings =
412 set_preferred_link_settings;
414 core_dc->public.link_funcs.enable_hpd =
417 core_dc->public.link_funcs.disable_hpd =
420 core_dc->public.link_funcs.set_test_pattern =
424 static void destruct(struct core_dc *dc)
426 dc_resource_validate_ctx_destruct(dc->current_context);
430 dc_destroy_resource_pool(dc);
432 if (dc->ctx->gpio_service)
433 dal_gpio_service_destroy(&dc->ctx->gpio_service);
436 dal_i2caux_destroy(&dc->ctx->i2caux);
438 if (dc->ctx->created_bios)
439 dal_bios_parser_destroy(&dc->ctx->dc_bios);
442 dal_logger_destroy(&dc->ctx->logger);
444 dm_free(dc->current_context);
445 dc->current_context = NULL;
451 static bool construct(struct core_dc *dc,
452 const struct dc_init_data *init_params)
454 struct dal_logger *logger;
455 struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
456 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
459 dm_error("%s: failed to create ctx\n", __func__);
463 dc->current_context = dm_alloc(sizeof(*dc->current_context));
465 if (!dc->current_context) {
466 dm_error("%s: failed to create validate ctx\n", __func__);
470 dc_ctx->cgs_device = init_params->cgs_device;
471 dc_ctx->driver_context = init_params->driver;
472 dc_ctx->dc = &dc->public;
473 dc_ctx->asic_id = init_params->asic_id;
476 logger = dal_logger_create(dc_ctx);
479 /* can *not* call logger. call base driver 'print error' */
480 dm_error("%s: failed to create Logger!\n", __func__);
483 dc_ctx->logger = logger;
485 dc->ctx->dce_environment = init_params->dce_environment;
487 dc_version = resource_parse_asic_id(init_params->asic_id);
488 dc->ctx->dce_version = dc_version;
490 /* Resource should construct all asic specific resources.
491 * This should be the only place where we need to parse the asic id
493 if (init_params->vbios_override)
494 dc_ctx->dc_bios = init_params->vbios_override;
496 /* Create BIOS parser */
497 struct bp_init_data bp_init_data;
499 bp_init_data.ctx = dc_ctx;
500 bp_init_data.bios = init_params->asic_id.atombios_base_address;
502 dc_ctx->dc_bios = dal_bios_parser_create(
503 &bp_init_data, dc_version);
505 if (!dc_ctx->dc_bios) {
506 ASSERT_CRITICAL(false);
510 dc_ctx->created_bios = true;
514 dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
516 if (!dc_ctx->i2caux) {
517 ASSERT_CRITICAL(false);
518 goto failed_to_create_i2caux;
521 /* Create GPIO service */
522 dc_ctx->gpio_service = dal_gpio_service_create(
524 dc_ctx->dce_environment,
527 if (!dc_ctx->gpio_service) {
528 ASSERT_CRITICAL(false);
532 dc->res_pool = dc_create_resource_pool(
534 init_params->num_virtual_links,
536 init_params->asic_id);
538 goto create_resource_fail;
540 if (!create_links(dc, init_params->num_virtual_links))
541 goto create_links_fail;
543 allocate_dc_stream_funcs(dc);
547 /**** error handling here ****/
549 create_resource_fail:
551 failed_to_create_i2caux:
561 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
563 fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
564 unsigned int pixDurationInPico = round(pixel_duration);
566 DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
568 arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
569 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
570 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
572 arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
573 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
574 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
576 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
577 WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
579 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
580 WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
584 /*******************************************************************************
586 ******************************************************************************/
588 struct dc *dc_create(const struct dc_init_data *init_params)
590 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
591 unsigned int full_pipe_count;
596 if (false == construct(core_dc, init_params))
599 /*TODO: separate HW and SW initialization*/
600 core_dc->hwss.init_hw(core_dc);
602 full_pipe_count = core_dc->res_pool->pipe_count;
603 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
605 core_dc->public.caps.max_streams = min(
607 core_dc->res_pool->stream_enc_count);
609 core_dc->public.caps.max_links = core_dc->link_count;
610 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
612 core_dc->public.config = init_params->flags;
614 dm_logger_write(core_dc->ctx->logger, LOG_DC,
615 "Display Core initialized\n");
618 /* TODO: missing feature to be enabled */
619 core_dc->public.debug.disable_dfs_bypass = true;
621 return &core_dc->public;
630 void dc_destroy(struct dc **dc)
632 struct core_dc *core_dc = DC_TO_CORE(*dc);
638 static bool is_validation_required(
639 const struct core_dc *dc,
640 const struct dc_validation_set set[],
643 const struct validate_context *context = dc->current_context;
646 if (context->stream_count != set_count)
649 for (i = 0; i < set_count; i++) {
651 if (set[i].surface_count != context->stream_status[i].surface_count)
653 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
656 for (j = 0; j < set[i].surface_count; j++) {
657 struct dc_surface temp_surf;
658 memset(&temp_surf, 0, sizeof(temp_surf));
660 temp_surf = *context->stream_status[i].surfaces[j];
661 temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
662 temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
663 temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
665 if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
673 struct validate_context *dc_get_validate_context(
675 const struct dc_validation_set set[],
678 struct core_dc *core_dc = DC_TO_CORE(dc);
679 enum dc_status result = DC_ERROR_UNEXPECTED;
680 struct validate_context *context;
682 context = dm_alloc(sizeof(struct validate_context));
684 goto context_alloc_fail;
686 if (!is_validation_required(core_dc, set, set_count)) {
687 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
691 result = core_dc->res_pool->funcs->validate_with_context(
692 core_dc, set, set_count, context, core_dc->current_context);
695 if (result != DC_OK) {
696 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
697 "%s:resource validation failed, dc_status:%d\n",
701 dc_resource_validate_ctx_destruct(context);
710 bool dc_validate_resources(
712 const struct dc_validation_set set[],
715 struct core_dc *core_dc = DC_TO_CORE(dc);
716 enum dc_status result = DC_ERROR_UNEXPECTED;
717 struct validate_context *context;
719 context = dm_alloc(sizeof(struct validate_context));
721 goto context_alloc_fail;
723 result = core_dc->res_pool->funcs->validate_with_context(
724 core_dc, set, set_count, context, NULL);
727 if (result != DC_OK) {
728 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
729 "%s:resource validation failed, dc_status:%d\n",
734 dc_resource_validate_ctx_destruct(context);
738 return result == DC_OK;
741 bool dc_validate_guaranteed(
743 const struct dc_stream *stream)
745 struct core_dc *core_dc = DC_TO_CORE(dc);
746 enum dc_status result = DC_ERROR_UNEXPECTED;
747 struct validate_context *context;
749 context = dm_alloc(sizeof(struct validate_context));
751 goto context_alloc_fail;
753 result = core_dc->res_pool->funcs->validate_guaranteed(
754 core_dc, stream, context);
756 dc_resource_validate_ctx_destruct(context);
760 if (result != DC_OK) {
761 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
762 "%s:guaranteed validation failed, dc_status:%d\n",
767 return (result == DC_OK);
770 static void program_timing_sync(
771 struct core_dc *core_dc,
772 struct validate_context *ctx)
776 int pipe_count = core_dc->res_pool->pipe_count;
777 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
779 for (i = 0; i < pipe_count; i++) {
780 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
783 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
786 for (i = 0; i < pipe_count; i++) {
788 struct pipe_ctx *pipe_set[MAX_PIPES];
790 if (!unsynced_pipes[i])
793 pipe_set[0] = unsynced_pipes[i];
794 unsynced_pipes[i] = NULL;
796 /* Add tg to the set, search rest of the tg's for ones with
797 * same timing, add all tgs with same timing to the group
799 for (j = i + 1; j < pipe_count; j++) {
800 if (!unsynced_pipes[j])
803 if (resource_are_streams_timing_synchronizable(
804 unsynced_pipes[j]->stream,
805 pipe_set[0]->stream)) {
806 pipe_set[group_size] = unsynced_pipes[j];
807 unsynced_pipes[j] = NULL;
812 /* set first unblanked pipe as master */
813 for (j = 0; j < group_size; j++) {
814 struct pipe_ctx *temp;
816 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
821 pipe_set[0] = pipe_set[j];
827 /* remove any other unblanked pipes as they have already been synced */
828 for (j = j + 1; j < group_size; j++) {
829 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
831 pipe_set[j] = pipe_set[group_size];
836 if (group_size > 1) {
837 core_dc->hwss.enable_timing_synchronization(
838 core_dc, group_index, group_size, pipe_set);
844 static bool streams_changed(
846 const struct dc_stream *streams[],
847 uint8_t stream_count)
851 if (stream_count != dc->current_context->stream_count)
854 for (i = 0; i < dc->current_context->stream_count; i++) {
855 if (&dc->current_context->streams[i]->public != streams[i])
862 bool dc_enable_stereo(
864 struct validate_context *context,
865 const struct dc_stream *streams[],
866 uint8_t stream_count)
870 struct pipe_ctx *pipe;
871 struct core_dc *core_dc = DC_TO_CORE(dc);
874 struct compressor *fbc_compressor = core_dc->fbc_compressor;
877 for (i = 0; i < MAX_PIPES; i++) {
879 pipe = &context->res_ctx.pipe_ctx[i];
881 pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
882 for (j = 0 ; pipe && j < stream_count; j++) {
883 if (streams[j] && streams[j] == &pipe->stream->public &&
884 core_dc->hwss.setup_stereo)
885 core_dc->hwss.setup_stereo(pipe, core_dc);
890 if (fbc_compressor != NULL &&
891 fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
893 fbc_compressor->funcs->disable_fbc(fbc_compressor);
899 bool dc_commit_streams(
901 const struct dc_stream *streams[],
902 uint8_t stream_count)
904 struct core_dc *core_dc = DC_TO_CORE(dc);
905 struct dc_bios *dcb = core_dc->ctx->dc_bios;
906 enum dc_status result = DC_ERROR_UNEXPECTED;
907 struct validate_context *context;
908 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
911 if (false == streams_changed(core_dc, streams, stream_count))
914 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
915 __func__, stream_count);
917 for (i = 0; i < stream_count; i++) {
918 const struct dc_stream *stream = streams[i];
919 const struct dc_stream_status *status = dc_stream_get_status(stream);
922 dc_stream_log(stream,
923 core_dc->ctx->logger,
926 set[i].stream = stream;
929 set[i].surface_count = status->surface_count;
930 for (j = 0; j < status->surface_count; j++)
931 set[i].surfaces[j] = status->surfaces[j];
936 context = dm_alloc(sizeof(struct validate_context));
938 goto context_alloc_fail;
940 result = core_dc->res_pool->funcs->validate_with_context(
941 core_dc, set, stream_count, context, core_dc->current_context);
942 if (result != DC_OK){
943 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
944 "%s: Context validation failed! dc_status:%d\n",
948 dc_resource_validate_ctx_destruct(context);
952 if (!dcb->funcs->is_accelerated_mode(dcb)) {
953 core_dc->hwss.enable_accelerated_mode(core_dc);
956 if (result == DC_OK) {
957 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
960 program_timing_sync(core_dc, context);
962 for (i = 0; i < context->stream_count; i++) {
963 const struct core_sink *sink = context->streams[i]->sink;
965 for (j = 0; j < context->stream_status[i].surface_count; j++) {
966 struct core_surface *surface =
967 DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
969 core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
972 CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}",
973 context->streams[i]->public.src.width,
974 context->streams[i]->public.src.height,
975 context->streams[i]->public.timing.h_addressable,
976 context->streams[i]->public.timing.v_addressable,
977 context->streams[i]->public.timing.pix_clk_khz * 1000 /
978 context->streams[i]->public.timing.h_total /
979 context->streams[i]->public.timing.v_total, // Refresh rate
980 context->streams[i]->public.timing.h_total,
981 context->streams[i]->public.timing.v_total,
982 context->streams[i]->public.timing.pix_clk_khz);
984 dc_enable_stereo(dc, context, streams, stream_count);
985 dc_resource_validate_ctx_destruct(core_dc->current_context);
986 dm_free(core_dc->current_context);
988 core_dc->current_context = context;
990 return (result == DC_OK);
996 return (result == DC_OK);
999 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1002 struct core_dc *core_dc = DC_TO_CORE(dc);
1003 struct validate_context *context = core_dc->current_context;
1005 post_surface_trace(dc);
1007 for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1008 if (context->res_ctx.pipe_ctx[i].stream == NULL
1009 || context->res_ctx.pipe_ctx[i].surface == NULL)
1010 core_dc->hwss.power_down_front_end(core_dc, i);
1012 /* 3rd param should be true, temp w/a for RV*/
1013 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1014 core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1016 core_dc->hwss.set_bandwidth(core_dc, context, true);
1021 bool dc_commit_surfaces_to_stream(
1023 const struct dc_surface **new_surfaces,
1024 uint8_t new_surface_count,
1025 const struct dc_stream *dc_stream)
1027 struct dc_surface_update updates[MAX_SURFACES];
1028 struct dc_flip_addrs flip_addr[MAX_SURFACES];
1029 struct dc_plane_info plane_info[MAX_SURFACES];
1030 struct dc_scaling_info scaling_info[MAX_SURFACES];
1032 struct dc_stream_update *stream_update =
1033 dm_alloc(sizeof(struct dc_stream_update));
1035 if (!stream_update) {
1036 BREAK_TO_DEBUGGER();
1040 memset(updates, 0, sizeof(updates));
1041 memset(flip_addr, 0, sizeof(flip_addr));
1042 memset(plane_info, 0, sizeof(plane_info));
1043 memset(scaling_info, 0, sizeof(scaling_info));
1045 stream_update->src = dc_stream->src;
1046 stream_update->dst = dc_stream->dst;
1048 for (i = 0; i < new_surface_count; i++) {
1049 updates[i].surface = new_surfaces[i];
1051 (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1052 flip_addr[i].address = new_surfaces[i]->address;
1053 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1054 plane_info[i].color_space = new_surfaces[i]->color_space;
1055 plane_info[i].format = new_surfaces[i]->format;
1056 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1057 plane_info[i].rotation = new_surfaces[i]->rotation;
1058 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1059 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1060 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1061 plane_info[i].visible = new_surfaces[i]->visible;
1062 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1063 plane_info[i].dcc = new_surfaces[i]->dcc;
1064 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1065 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1066 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1067 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1069 updates[i].flip_addr = &flip_addr[i];
1070 updates[i].plane_info = &plane_info[i];
1071 updates[i].scaling_info = &scaling_info[i];
1074 dc_update_surfaces_and_stream(
1078 dc_stream, stream_update);
1080 dc_post_update_surfaces_to_stream(dc);
1082 dm_free(stream_update);
1086 static bool is_surface_in_context(
1087 const struct validate_context *context,
1088 const struct dc_surface *surface)
1092 for (j = 0; j < MAX_PIPES; j++) {
1093 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1095 if (surface == &pipe_ctx->surface->public) {
1103 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1106 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1107 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1109 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1110 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1111 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1112 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1114 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1115 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1116 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1117 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1119 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1120 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1121 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1124 ASSERT_CRITICAL(false);
1129 static enum surface_update_type get_plane_info_update_type(
1130 const struct dc_surface_update *u,
1133 struct dc_plane_info temp_plane_info;
1134 memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1137 return UPDATE_TYPE_FAST;
1139 temp_plane_info = *u->plane_info;
1141 /* Copy all parameters that will cause a full update
1142 * from current surface, the rest of the parameters
1143 * from provided plane configuration.
1144 * Perform memory compare and special validation
1145 * for those that can cause fast/medium updates
1148 /* Full update parameters */
1149 temp_plane_info.color_space = u->surface->color_space;
1150 temp_plane_info.dcc = u->surface->dcc;
1151 temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1152 temp_plane_info.plane_size = u->surface->plane_size;
1153 temp_plane_info.rotation = u->surface->rotation;
1154 temp_plane_info.stereo_format = u->surface->stereo_format;
1155 temp_plane_info.tiling_info = u->surface->tiling_info;
1157 if (surface_index == 0)
1158 temp_plane_info.visible = u->plane_info->visible;
1160 temp_plane_info.visible = u->surface->visible;
1162 if (memcmp(u->plane_info, &temp_plane_info,
1163 sizeof(struct dc_plane_info)) != 0)
1164 return UPDATE_TYPE_FULL;
1166 if (pixel_format_to_bpp(u->plane_info->format) !=
1167 pixel_format_to_bpp(u->surface->format)) {
1168 return UPDATE_TYPE_FULL;
1170 return UPDATE_TYPE_MED;
1174 static enum surface_update_type get_scaling_info_update_type(
1175 const struct dc_surface_update *u)
1177 if (!u->scaling_info)
1178 return UPDATE_TYPE_FAST;
1180 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1181 || u->scaling_info->src_rect.height != u->surface->src_rect.height
1182 || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1183 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1184 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1185 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1186 return UPDATE_TYPE_FULL;
1188 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1189 || u->scaling_info->src_rect.y != u->surface->src_rect.y
1190 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1191 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1192 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1193 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1194 return UPDATE_TYPE_MED;
1196 return UPDATE_TYPE_FAST;
1199 static enum surface_update_type det_surface_update(
1200 const struct core_dc *dc,
1201 const struct dc_surface_update *u,
1204 const struct validate_context *context = dc->current_context;
1205 enum surface_update_type type = UPDATE_TYPE_FAST;
1206 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1208 if (!is_surface_in_context(context, u->surface))
1209 return UPDATE_TYPE_FULL;
1211 type = get_plane_info_update_type(u, surface_index);
1212 if (overall_type < type)
1213 overall_type = type;
1215 type = get_scaling_info_update_type(u);
1216 if (overall_type < type)
1217 overall_type = type;
1219 if (u->in_transfer_func ||
1220 u->hdr_static_metadata) {
1221 if (overall_type < UPDATE_TYPE_MED)
1222 overall_type = UPDATE_TYPE_MED;
1225 return overall_type;
1228 enum surface_update_type dc_check_update_surfaces_for_stream(
1230 struct dc_surface_update *updates,
1232 struct dc_stream_update *stream_update,
1233 const struct dc_stream_status *stream_status)
1235 struct core_dc *core_dc = DC_TO_CORE(dc);
1237 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1239 if (stream_status == NULL || stream_status->surface_count != surface_count)
1240 return UPDATE_TYPE_FULL;
1243 return UPDATE_TYPE_FULL;
1245 for (i = 0 ; i < surface_count; i++) {
1246 enum surface_update_type type =
1247 det_surface_update(core_dc, &updates[i], i);
1249 if (type == UPDATE_TYPE_FULL)
1252 if (overall_type < type)
1253 overall_type = type;
1256 return overall_type;
1259 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1261 void dc_update_surfaces_and_stream(struct dc *dc,
1262 struct dc_surface_update *srf_updates, int surface_count,
1263 const struct dc_stream *dc_stream,
1264 struct dc_stream_update *stream_update)
1266 struct core_dc *core_dc = DC_TO_CORE(dc);
1267 struct validate_context *context;
1269 enum surface_update_type update_type;
1270 const struct dc_stream_status *stream_status;
1271 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1273 stream_status = dc_stream_get_status(dc_stream);
1274 ASSERT(stream_status);
1276 return; /* Cannot commit surface to stream that is not committed */
1279 if (srf_updates->flip_addr) {
1280 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1284 context = core_dc->current_context;
1286 /* update current stream with the new updates */
1287 if (stream_update) {
1288 if ((stream_update->src.height != 0) &&
1289 (stream_update->src.width != 0))
1290 stream->public.src = stream_update->src;
1292 if ((stream_update->dst.height != 0) &&
1293 (stream_update->dst.width != 0))
1294 stream->public.dst = stream_update->dst;
1296 if (stream_update->out_transfer_func &&
1297 stream_update->out_transfer_func !=
1298 dc_stream->out_transfer_func) {
1299 if (dc_stream->out_transfer_func != NULL)
1300 dc_transfer_func_release(dc_stream->out_transfer_func);
1301 dc_transfer_func_retain(stream_update->out_transfer_func);
1302 stream->public.out_transfer_func =
1303 stream_update->out_transfer_func;
1307 /* do not perform surface update if surface has invalid dimensions
1308 * (all zero) and no scaling_info is provided
1310 if (surface_count > 0 &&
1311 srf_updates->surface->src_rect.width == 0 &&
1312 srf_updates->surface->src_rect.height == 0 &&
1313 srf_updates->surface->dst_rect.width == 0 &&
1314 srf_updates->surface->dst_rect.height == 0 &&
1315 !srf_updates->scaling_info) {
1320 update_type = dc_check_update_surfaces_for_stream(
1321 dc, srf_updates, surface_count, stream_update, stream_status);
1323 if (update_type >= update_surface_trace_level)
1324 update_surface_trace(dc, srf_updates, surface_count);
1326 if (update_type >= UPDATE_TYPE_FULL) {
1327 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1329 for (i = 0; i < surface_count; i++)
1330 new_surfaces[i] = srf_updates[i].surface;
1332 /* initialize scratch memory for building context */
1333 context = dm_alloc(sizeof(*context));
1334 dc_resource_validate_ctx_copy_construct(
1335 core_dc->current_context, context);
1337 /* add surface to context */
1338 if (!resource_attach_surfaces_to_context(
1339 new_surfaces, surface_count, dc_stream,
1340 context, core_dc->res_pool)) {
1341 BREAK_TO_DEBUGGER();
1346 /* save update parameters into surface */
1347 for (i = 0; i < surface_count; i++) {
1348 struct core_surface *surface =
1349 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1351 if (srf_updates[i].flip_addr) {
1352 surface->public.address = srf_updates[i].flip_addr->address;
1353 surface->public.flip_immediate =
1354 srf_updates[i].flip_addr->flip_immediate;
1357 if (srf_updates[i].scaling_info) {
1358 surface->public.scaling_quality =
1359 srf_updates[i].scaling_info->scaling_quality;
1360 surface->public.dst_rect =
1361 srf_updates[i].scaling_info->dst_rect;
1362 surface->public.src_rect =
1363 srf_updates[i].scaling_info->src_rect;
1364 surface->public.clip_rect =
1365 srf_updates[i].scaling_info->clip_rect;
1368 if (srf_updates[i].plane_info) {
1369 surface->public.color_space =
1370 srf_updates[i].plane_info->color_space;
1371 surface->public.format =
1372 srf_updates[i].plane_info->format;
1373 surface->public.plane_size =
1374 srf_updates[i].plane_info->plane_size;
1375 surface->public.rotation =
1376 srf_updates[i].plane_info->rotation;
1377 surface->public.horizontal_mirror =
1378 srf_updates[i].plane_info->horizontal_mirror;
1379 surface->public.stereo_format =
1380 srf_updates[i].plane_info->stereo_format;
1381 surface->public.tiling_info =
1382 srf_updates[i].plane_info->tiling_info;
1383 surface->public.visible =
1384 srf_updates[i].plane_info->visible;
1385 surface->public.per_pixel_alpha =
1386 srf_updates[i].plane_info->per_pixel_alpha;
1387 surface->public.dcc =
1388 srf_updates[i].plane_info->dcc;
1391 if (update_type >= UPDATE_TYPE_MED) {
1392 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1393 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1395 if (pipe_ctx->surface != surface)
1398 resource_build_scaling_params(pipe_ctx);
1402 if (srf_updates[i].gamma &&
1403 srf_updates[i].gamma != surface->public.gamma_correction) {
1404 if (surface->public.gamma_correction != NULL)
1405 dc_gamma_release(&surface->public.
1408 dc_gamma_retain(srf_updates[i].gamma);
1409 surface->public.gamma_correction =
1410 srf_updates[i].gamma;
1413 if (srf_updates[i].in_transfer_func &&
1414 srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1415 if (surface->public.in_transfer_func != NULL)
1416 dc_transfer_func_release(
1420 dc_transfer_func_retain(
1421 srf_updates[i].in_transfer_func);
1422 surface->public.in_transfer_func =
1423 srf_updates[i].in_transfer_func;
1426 if (srf_updates[i].hdr_static_metadata)
1427 surface->public.hdr_static_ctx =
1428 *(srf_updates[i].hdr_static_metadata);
1431 if (update_type == UPDATE_TYPE_FULL) {
1432 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1433 BREAK_TO_DEBUGGER();
1436 core_dc->hwss.set_bandwidth(core_dc, context, false);
1437 context_clock_trace(dc, context);
1441 if (surface_count == 0)
1442 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1444 /* Lock pipes for provided surfaces, or all active if full update*/
1445 for (i = 0; i < surface_count; i++) {
1446 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1448 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1449 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1451 if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1453 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1456 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1457 core_dc->hwss.pipe_control_lock(
1463 if (update_type == UPDATE_TYPE_FULL)
1468 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1469 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1470 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1471 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1472 struct dc_cursor_position position = { 0 };
1474 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1477 if (!pipe_ctx->top_pipe)
1478 core_dc->hwss.apply_ctx_for_surface(
1479 core_dc, pipe_ctx->surface, context);
1481 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1482 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1484 if (is_new_pipe_surface) {
1485 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1486 core_dc->hwss.set_input_transfer_func(
1487 pipe_ctx, pipe_ctx->surface);
1488 core_dc->hwss.set_output_transfer_func(
1489 pipe_ctx, pipe_ctx->stream);
1493 if (update_type > UPDATE_TYPE_FAST)
1494 context_timing_trace(dc, &context->res_ctx);
1496 /* Perform requested Updates */
1497 for (i = 0; i < surface_count; i++) {
1498 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1500 if (update_type == UPDATE_TYPE_MED)
1501 core_dc->hwss.apply_ctx_for_surface(
1502 core_dc, surface, context);
1504 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1505 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1507 if (pipe_ctx->surface != surface)
1510 if (srf_updates[i].flip_addr)
1511 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1513 if (update_type == UPDATE_TYPE_FAST)
1516 if (srf_updates[i].in_transfer_func)
1517 core_dc->hwss.set_input_transfer_func(
1518 pipe_ctx, pipe_ctx->surface);
1520 if (stream_update != NULL &&
1521 stream_update->out_transfer_func != NULL) {
1522 core_dc->hwss.set_output_transfer_func(
1523 pipe_ctx, pipe_ctx->stream);
1526 if (srf_updates[i].hdr_static_metadata) {
1527 resource_build_info_frame(pipe_ctx);
1528 core_dc->hwss.update_info_frame(pipe_ctx);
1534 for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1535 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1537 for (j = 0; j < surface_count; j++) {
1538 if (update_type != UPDATE_TYPE_FULL &&
1539 srf_updates[j].surface != &pipe_ctx->surface->public)
1541 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1544 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1545 core_dc->hwss.pipe_control_lock(
1554 if (core_dc->current_context != context) {
1555 dc_resource_validate_ctx_destruct(core_dc->current_context);
1556 dm_free(core_dc->current_context);
1558 core_dc->current_context = context;
1563 dc_resource_validate_ctx_destruct(context);
1567 uint8_t dc_get_current_stream_count(const struct dc *dc)
1569 struct core_dc *core_dc = DC_TO_CORE(dc);
1570 return core_dc->current_context->stream_count;
1573 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1575 struct core_dc *core_dc = DC_TO_CORE(dc);
1576 if (i < core_dc->current_context->stream_count)
1577 return &(core_dc->current_context->streams[i]->public);
1581 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1583 struct core_dc *core_dc = DC_TO_CORE(dc);
1584 return &core_dc->links[link_index]->public;
1587 const struct graphics_object_id dc_get_link_id_at_index(
1588 struct dc *dc, uint32_t link_index)
1590 struct core_dc *core_dc = DC_TO_CORE(dc);
1591 return core_dc->links[link_index]->link_id;
1594 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1595 struct dc *dc, uint32_t link_index)
1597 struct core_dc *core_dc = DC_TO_CORE(dc);
1598 return core_dc->links[link_index]->public.irq_source_hpd;
1601 const struct audio **dc_get_audios(struct dc *dc)
1603 struct core_dc *core_dc = DC_TO_CORE(dc);
1604 return (const struct audio **)core_dc->res_pool->audios;
1607 enum dc_irq_source dc_interrupt_to_irq_source(
1612 struct core_dc *core_dc = DC_TO_CORE(dc);
1613 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1616 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1618 struct core_dc *core_dc;
1622 core_dc = DC_TO_CORE(dc);
1624 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1627 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1629 struct core_dc *core_dc = DC_TO_CORE(dc);
1630 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1633 void dc_set_power_state(
1635 enum dc_acpi_cm_power_state power_state)
1637 struct core_dc *core_dc = DC_TO_CORE(dc);
1639 switch (power_state) {
1640 case DC_ACPI_CM_POWER_STATE_D0:
1641 core_dc->hwss.init_hw(core_dc);
1645 core_dc->hwss.power_down(core_dc);
1647 /* Zero out the current context so that on resume we start with
1648 * clean state, and dc hw programming optimizations will not
1649 * cause any trouble.
1651 memset(core_dc->current_context, 0,
1652 sizeof(*core_dc->current_context));
1659 void dc_resume(const struct dc *dc)
1661 struct core_dc *core_dc = DC_TO_CORE(dc);
1665 for (i = 0; i < core_dc->link_count; i++)
1666 core_link_resume(core_dc->links[i]);
1669 bool dc_read_aux_dpcd(
1671 uint32_t link_index,
1676 struct core_dc *core_dc = DC_TO_CORE(dc);
1678 struct core_link *link = core_dc->links[link_index];
1679 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1686 return r == DDC_RESULT_SUCESSFULL;
1689 bool dc_write_aux_dpcd(
1691 uint32_t link_index,
1693 const uint8_t *data,
1696 struct core_dc *core_dc = DC_TO_CORE(dc);
1697 struct core_link *link = core_dc->links[link_index];
1699 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1706 return r == DDC_RESULT_SUCESSFULL;
1709 bool dc_read_aux_i2c(
1711 uint32_t link_index,
1712 enum i2c_mot_mode mot,
1717 struct core_dc *core_dc = DC_TO_CORE(dc);
1719 struct core_link *link = core_dc->links[link_index];
1720 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1727 return r == DDC_RESULT_SUCESSFULL;
1730 bool dc_write_aux_i2c(
1732 uint32_t link_index,
1733 enum i2c_mot_mode mot,
1735 const uint8_t *data,
1738 struct core_dc *core_dc = DC_TO_CORE(dc);
1739 struct core_link *link = core_dc->links[link_index];
1741 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1748 return r == DDC_RESULT_SUCESSFULL;
1751 bool dc_query_ddc_data(
1753 uint32_t link_index,
1756 uint32_t write_size,
1758 uint32_t read_size) {
1760 struct core_dc *core_dc = DC_TO_CORE(dc);
1762 struct core_link *link = core_dc->links[link_index];
1764 bool result = dal_ddc_service_query_ddc_data(
1777 uint32_t link_index,
1778 struct i2c_command *cmd)
1780 struct core_dc *core_dc = DC_TO_CORE(dc);
1782 struct core_link *link = core_dc->links[link_index];
1783 struct ddc_service *ddc = link->public.ddc;
1785 return dal_i2caux_submit_i2c_command(
1791 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1793 struct dc_link *dc_link = &core_link->public;
1795 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1796 BREAK_TO_DEBUGGER();
1800 dc_sink_retain(sink);
1802 dc_link->remote_sinks[dc_link->sink_count] = sink;
1803 dc_link->sink_count++;
1808 struct dc_sink *dc_link_add_remote_sink(
1809 const struct dc_link *link,
1810 const uint8_t *edid,
1812 struct dc_sink_init_data *init_data)
1814 struct dc_sink *dc_sink;
1815 enum dc_edid_status edid_status;
1816 struct core_link *core_link = DC_LINK_TO_LINK(link);
1818 if (len > MAX_EDID_BUFFER_SIZE) {
1819 dm_error("Max EDID buffer size breached!\n");
1824 BREAK_TO_DEBUGGER();
1828 if (!init_data->link) {
1829 BREAK_TO_DEBUGGER();
1833 dc_sink = dc_sink_create(init_data);
1838 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1839 dc_sink->dc_edid.length = len;
1841 if (!link_add_remote_sink_helper(
1846 edid_status = dm_helpers_parse_edid_caps(
1849 &dc_sink->edid_caps);
1851 if (edid_status != EDID_OK)
1856 dc_link_remove_remote_sink(link, dc_sink);
1858 dc_sink_release(dc_sink);
1862 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1864 struct core_link *core_link = DC_LINK_TO_LINK(link);
1865 struct dc_link *dc_link = &core_link->public;
1867 dc_link->local_sink = sink;
1870 dc_link->type = dc_connection_none;
1872 dc_link->type = dc_connection_single;
1876 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1879 struct core_link *core_link = DC_LINK_TO_LINK(link);
1880 struct dc_link *dc_link = &core_link->public;
1882 if (!link->sink_count) {
1883 BREAK_TO_DEBUGGER();
1887 for (i = 0; i < dc_link->sink_count; i++) {
1888 if (dc_link->remote_sinks[i] == sink) {
1889 dc_sink_release(sink);
1890 dc_link->remote_sinks[i] = NULL;
1892 /* shrink array to remove empty place */
1893 while (i < dc_link->sink_count - 1) {
1894 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1897 dc_link->remote_sinks[i] = NULL;
1898 dc_link->sink_count--;
1904 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1907 struct core_dc *core_dc = DC_TO_CORE(dc);
1908 struct mem_input *mi = NULL;
1910 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1911 if (core_dc->res_pool->mis[i] != NULL) {
1912 mi = core_dc->res_pool->mis[i];
1917 dm_error("no mem_input!\n");
1921 if (mi->funcs->mem_input_update_dchub)
1922 mi->funcs->mem_input_update_dchub(mi, dh_data);
1924 ASSERT(mi->funcs->mem_input_update_dchub);