drm/amd/display: Fix for hdmi frame pack stereo
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / core / dc.c
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  */
24
25 #include "dm_services.h"
26
27 #include "dc.h"
28
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
32
33 #include "resource.h"
34
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
37
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
44
45 #include "link_hwss.h"
46 #include "link_encoder.h"
47
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
51
52 /*******************************************************************************
53  * Private functions
54  ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
56 {
57         uint32_t i;
58
59         for (i = 0; i < dc->link_count; i++) {
60                 if (NULL != dc->links[i])
61                         link_destroy(&dc->links[i]);
62         }
63 }
64
65 static bool create_links(
66                 struct core_dc *dc,
67                 uint32_t num_virtual_links)
68 {
69         int i;
70         int connectors_num;
71         struct dc_bios *bios = dc->ctx->dc_bios;
72
73         dc->link_count = 0;
74
75         connectors_num = bios->funcs->get_connectors_number(bios);
76
77         if (connectors_num > ENUM_ID_COUNT) {
78                 dm_error(
79                         "DC: Number of connectors %d exceeds maximum of %d!\n",
80                         connectors_num,
81                         ENUM_ID_COUNT);
82                 return false;
83         }
84
85         if (connectors_num == 0 && num_virtual_links == 0) {
86                 dm_error("DC: Number of connectors is zero!\n");
87         }
88
89         dm_output_to_console(
90                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
91                 __func__,
92                 connectors_num,
93                 num_virtual_links);
94
95         for (i = 0; i < connectors_num; i++) {
96                 struct link_init_data link_init_params = {0};
97                 struct core_link *link;
98
99                 link_init_params.ctx = dc->ctx;
100                 /* next BIOS object table connector */
101                 link_init_params.connector_index = i;
102                 link_init_params.link_index = dc->link_count;
103                 link_init_params.dc = dc;
104                 link = link_create(&link_init_params);
105
106                 if (link) {
107                         dc->links[dc->link_count] = link;
108                         link->dc = dc;
109                         ++dc->link_count;
110                 }
111         }
112
113         for (i = 0; i < num_virtual_links; i++) {
114                 struct core_link *link = dm_alloc(sizeof(*link));
115                 struct encoder_init_data enc_init = {0};
116
117                 if (link == NULL) {
118                         BREAK_TO_DEBUGGER();
119                         goto failed_alloc;
120                 }
121
122                 link->ctx = dc->ctx;
123                 link->dc = dc;
124                 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127                 link->link_id.enum_id = ENUM_ID_1;
128                 link->link_enc = dm_alloc(sizeof(*link->link_enc));
129
130                 enc_init.ctx = dc->ctx;
131                 enc_init.channel = CHANNEL_ID_UNKNOWN;
132                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134                 enc_init.connector = link->link_id;
135                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137                 enc_init.encoder.enum_id = ENUM_ID_1;
138                 virtual_link_encoder_construct(link->link_enc, &enc_init);
139
140                 link->public.link_index = dc->link_count;
141                 dc->links[dc->link_count] = link;
142                 dc->link_count++;
143         }
144
145         return true;
146
147 failed_alloc:
148         return false;
149 }
150
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152                 const struct dc_stream **stream, int num_streams,
153                 int vmin, int vmax)
154 {
155         /* TODO: Support multiple streams */
156         struct core_dc *core_dc = DC_TO_CORE(dc);
157         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
158         int i = 0;
159         bool ret = false;
160
161         for (i = 0; i < MAX_PIPES; i++) {
162                 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
163
164                 if (pipe->stream == core_stream && pipe->stream_enc) {
165                         core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
166
167                         /* build and update the info frame */
168                         resource_build_info_frame(pipe);
169                         core_dc->hwss.update_info_frame(pipe);
170
171                         ret = true;
172                 }
173         }
174         return ret;
175 }
176
177 static bool stream_get_crtc_position(struct dc *dc,
178                 const struct dc_stream **stream, int num_streams,
179                 unsigned int *v_pos, unsigned int *nom_v_pos)
180 {
181         /* TODO: Support multiple streams */
182         struct core_dc *core_dc = DC_TO_CORE(dc);
183         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
184         int i = 0;
185         bool ret = false;
186         struct crtc_position position;
187
188         for (i = 0; i < MAX_PIPES; i++) {
189                 struct pipe_ctx *pipe =
190                                 &core_dc->current_context->res_ctx.pipe_ctx[i];
191
192                 if (pipe->stream == core_stream && pipe->stream_enc) {
193                         core_dc->hwss.get_position(&pipe, 1, &position);
194
195                         *v_pos = position.vertical_count;
196                         *nom_v_pos = position.nominal_vcount;
197                         ret = true;
198                 }
199         }
200         return ret;
201 }
202
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
204 {
205         struct core_dc *core_dc = DC_TO_CORE(dc);
206         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
207         int i = 0;
208         bool ret = false;
209         struct pipe_ctx *pipes;
210
211         for (i = 0; i < MAX_PIPES; i++) {
212                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
213                                 == core_stream) {
214
215                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216                         core_dc->hwss.program_gamut_remap(pipes);
217                         ret = true;
218                 }
219         }
220
221         return ret;
222 }
223
224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
225 {
226         struct core_dc *core_dc = DC_TO_CORE(dc);
227         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
228         int i = 0;
229         bool ret = false;
230         struct pipe_ctx *pipes;
231
232         for (i = 0; i < MAX_PIPES; i++) {
233                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
234                                 == core_stream) {
235
236                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
237                         core_dc->hwss.program_csc_matrix(pipes,
238                         core_stream->public.output_color_space,
239                         core_stream->public.csc_color_matrix.matrix);
240                         ret = true;
241                 }
242         }
243
244         return ret;
245 }
246
247 static void set_static_screen_events(struct dc *dc,
248                 const struct dc_stream **stream,
249                 int num_streams,
250                 const struct dc_static_screen_events *events)
251 {
252         struct core_dc *core_dc = DC_TO_CORE(dc);
253         int i = 0;
254         int j = 0;
255         struct pipe_ctx *pipes_affected[MAX_PIPES];
256         int num_pipes_affected = 0;
257
258         for (i = 0; i < num_streams; i++) {
259                 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
260
261                 for (j = 0; j < MAX_PIPES; j++) {
262                         if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
263                                         == core_stream) {
264                                 pipes_affected[num_pipes_affected++] =
265                                                 &core_dc->current_context->res_ctx.pipe_ctx[j];
266                         }
267                 }
268         }
269
270         core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
271 }
272
273 static void set_drive_settings(struct dc *dc,
274                 struct link_training_settings *lt_settings,
275                 const struct dc_link *link)
276 {
277         struct core_dc *core_dc = DC_TO_CORE(dc);
278         int i;
279
280         for (i = 0; i < core_dc->link_count; i++) {
281                 if (&core_dc->links[i]->public == link)
282                         break;
283         }
284
285         if (i >= core_dc->link_count)
286                 ASSERT_CRITICAL(false);
287
288         dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
289 }
290
291 static void perform_link_training(struct dc *dc,
292                 struct dc_link_settings *link_setting,
293                 bool skip_video_pattern)
294 {
295         struct core_dc *core_dc = DC_TO_CORE(dc);
296         int i;
297
298         for (i = 0; i < core_dc->link_count; i++)
299                 dc_link_dp_perform_link_training(
300                         &core_dc->links[i]->public,
301                         link_setting,
302                         skip_video_pattern);
303 }
304
305 static void set_preferred_link_settings(struct dc *dc,
306                 struct dc_link_settings *link_setting,
307                 const struct dc_link *link)
308 {
309         struct core_link *core_link = DC_LINK_TO_CORE(link);
310
311         core_link->public.verified_link_cap.lane_count =
312                                 link_setting->lane_count;
313         core_link->public.verified_link_cap.link_rate =
314                                 link_setting->link_rate;
315         dp_retrain_link_dp_test(core_link, link_setting, false);
316 }
317
318 static void enable_hpd(const struct dc_link *link)
319 {
320         dc_link_dp_enable_hpd(link);
321 }
322
323 static void disable_hpd(const struct dc_link *link)
324 {
325         dc_link_dp_disable_hpd(link);
326 }
327
328
329 static void set_test_pattern(
330                 const struct dc_link *link,
331                 enum dp_test_pattern test_pattern,
332                 const struct link_training_settings *p_link_settings,
333                 const unsigned char *p_custom_pattern,
334                 unsigned int cust_pattern_size)
335 {
336         if (link != NULL)
337                 dc_link_dp_set_test_pattern(
338                         link,
339                         test_pattern,
340                         p_link_settings,
341                         p_custom_pattern,
342                         cust_pattern_size);
343 }
344
345 void set_dither_option(const struct dc_stream *dc_stream,
346                 enum dc_dither_option option)
347 {
348         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
349         struct bit_depth_reduction_params params;
350         struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
351         struct pipe_ctx *pipes =
352                         core_link->dc->current_context->res_ctx.pipe_ctx;
353
354         memset(&params, 0, sizeof(params));
355         if (!stream)
356                 return;
357         if (option > DITHER_OPTION_MAX)
358                 return;
359         if (option == DITHER_OPTION_DEFAULT) {
360                 switch (stream->public.timing.display_color_depth) {
361                 case COLOR_DEPTH_666:
362                         stream->public.dither_option = DITHER_OPTION_SPATIAL6;
363                         break;
364                 case COLOR_DEPTH_888:
365                         stream->public.dither_option = DITHER_OPTION_SPATIAL8;
366                         break;
367                 case COLOR_DEPTH_101010:
368                         stream->public.dither_option = DITHER_OPTION_SPATIAL10;
369                         break;
370                 default:
371                         option = DITHER_OPTION_DISABLE;
372                 }
373         } else {
374                 stream->public.dither_option = option;
375         }
376         resource_build_bit_depth_reduction_params(stream,
377                                 &params);
378         stream->bit_depth_params = params;
379         pipes->opp->funcs->
380                 opp_program_bit_depth_reduction(pipes->opp, &params);
381 }
382
383 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
384 {
385         if (core_dc->hwss.set_drr != NULL) {
386                 core_dc->public.stream_funcs.adjust_vmin_vmax =
387                                 stream_adjust_vmin_vmax;
388         }
389
390         core_dc->public.stream_funcs.set_static_screen_events =
391                         set_static_screen_events;
392
393         core_dc->public.stream_funcs.get_crtc_position =
394                         stream_get_crtc_position;
395
396         core_dc->public.stream_funcs.set_gamut_remap =
397                         set_gamut_remap;
398
399         core_dc->public.stream_funcs.program_csc_matrix =
400                         program_csc_matrix;
401
402         core_dc->public.stream_funcs.set_dither_option =
403                         set_dither_option;
404
405         core_dc->public.link_funcs.set_drive_settings =
406                         set_drive_settings;
407
408         core_dc->public.link_funcs.perform_link_training =
409                         perform_link_training;
410
411         core_dc->public.link_funcs.set_preferred_link_settings =
412                         set_preferred_link_settings;
413
414         core_dc->public.link_funcs.enable_hpd =
415                         enable_hpd;
416
417         core_dc->public.link_funcs.disable_hpd =
418                         disable_hpd;
419
420         core_dc->public.link_funcs.set_test_pattern =
421                         set_test_pattern;
422 }
423
424 static void destruct(struct core_dc *dc)
425 {
426         dc_resource_validate_ctx_destruct(dc->current_context);
427
428         destroy_links(dc);
429
430         dc_destroy_resource_pool(dc);
431
432         if (dc->ctx->gpio_service)
433                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
434
435         if (dc->ctx->i2caux)
436                 dal_i2caux_destroy(&dc->ctx->i2caux);
437
438         if (dc->ctx->created_bios)
439                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
440
441         if (dc->ctx->logger)
442                 dal_logger_destroy(&dc->ctx->logger);
443
444         dm_free(dc->current_context);
445         dc->current_context = NULL;
446
447         dm_free(dc->ctx);
448         dc->ctx = NULL;
449 }
450
451 static bool construct(struct core_dc *dc,
452                 const struct dc_init_data *init_params)
453 {
454         struct dal_logger *logger;
455         struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
456         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
457
458         if (!dc_ctx) {
459                 dm_error("%s: failed to create ctx\n", __func__);
460                 goto ctx_fail;
461         }
462
463         dc->current_context = dm_alloc(sizeof(*dc->current_context));
464
465         if (!dc->current_context) {
466                 dm_error("%s: failed to create validate ctx\n", __func__);
467                 goto val_ctx_fail;
468         }
469
470         dc_ctx->cgs_device = init_params->cgs_device;
471         dc_ctx->driver_context = init_params->driver;
472         dc_ctx->dc = &dc->public;
473         dc_ctx->asic_id = init_params->asic_id;
474
475         /* Create logger */
476         logger = dal_logger_create(dc_ctx);
477
478         if (!logger) {
479                 /* can *not* call logger. call base driver 'print error' */
480                 dm_error("%s: failed to create Logger!\n", __func__);
481                 goto logger_fail;
482         }
483         dc_ctx->logger = logger;
484         dc->ctx = dc_ctx;
485         dc->ctx->dce_environment = init_params->dce_environment;
486
487         dc_version = resource_parse_asic_id(init_params->asic_id);
488         dc->ctx->dce_version = dc_version;
489
490         /* Resource should construct all asic specific resources.
491          * This should be the only place where we need to parse the asic id
492          */
493         if (init_params->vbios_override)
494                 dc_ctx->dc_bios = init_params->vbios_override;
495         else {
496                 /* Create BIOS parser */
497                 struct bp_init_data bp_init_data;
498
499                 bp_init_data.ctx = dc_ctx;
500                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
501
502                 dc_ctx->dc_bios = dal_bios_parser_create(
503                                 &bp_init_data, dc_version);
504
505                 if (!dc_ctx->dc_bios) {
506                         ASSERT_CRITICAL(false);
507                         goto bios_fail;
508                 }
509
510                 dc_ctx->created_bios = true;
511                 }
512
513         /* Create I2C AUX */
514         dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
515
516         if (!dc_ctx->i2caux) {
517                 ASSERT_CRITICAL(false);
518                 goto failed_to_create_i2caux;
519         }
520
521         /* Create GPIO service */
522         dc_ctx->gpio_service = dal_gpio_service_create(
523                         dc_version,
524                         dc_ctx->dce_environment,
525                         dc_ctx);
526
527         if (!dc_ctx->gpio_service) {
528                 ASSERT_CRITICAL(false);
529                 goto gpio_fail;
530         }
531
532         dc->res_pool = dc_create_resource_pool(
533                         dc,
534                         init_params->num_virtual_links,
535                         dc_version,
536                         init_params->asic_id);
537         if (!dc->res_pool)
538                 goto create_resource_fail;
539
540         if (!create_links(dc, init_params->num_virtual_links))
541                 goto create_links_fail;
542
543         allocate_dc_stream_funcs(dc);
544
545         return true;
546
547         /**** error handling here ****/
548 create_links_fail:
549 create_resource_fail:
550 gpio_fail:
551 failed_to_create_i2caux:
552 bios_fail:
553 logger_fail:
554 val_ctx_fail:
555 ctx_fail:
556         destruct(dc);
557         return false;
558 }
559
560 /*
561 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
562 {
563         fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
564         unsigned int pixDurationInPico = round(pixel_duration);
565
566         DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
567
568         arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
569         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
570         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
571
572         arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
573         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
574         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
575
576         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
577         WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
578
579         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
580         WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
581 }
582 */
583
584 /*******************************************************************************
585  * Public functions
586  ******************************************************************************/
587
588 struct dc *dc_create(const struct dc_init_data *init_params)
589  {
590         struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
591         unsigned int full_pipe_count;
592
593         if (NULL == core_dc)
594                 goto alloc_fail;
595
596         if (false == construct(core_dc, init_params))
597                 goto construct_fail;
598
599         /*TODO: separate HW and SW initialization*/
600         core_dc->hwss.init_hw(core_dc);
601
602         full_pipe_count = core_dc->res_pool->pipe_count;
603         if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
604                 full_pipe_count--;
605         core_dc->public.caps.max_streams = min(
606                         full_pipe_count,
607                         core_dc->res_pool->stream_enc_count);
608
609         core_dc->public.caps.max_links = core_dc->link_count;
610         core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
611
612         core_dc->public.config = init_params->flags;
613
614         dm_logger_write(core_dc->ctx->logger, LOG_DC,
615                         "Display Core initialized\n");
616
617
618         /* TODO: missing feature to be enabled */
619         core_dc->public.debug.disable_dfs_bypass = true;
620
621         return &core_dc->public;
622
623 construct_fail:
624         dm_free(core_dc);
625
626 alloc_fail:
627         return NULL;
628 }
629
630 void dc_destroy(struct dc **dc)
631 {
632         struct core_dc *core_dc = DC_TO_CORE(*dc);
633         destruct(core_dc);
634         dm_free(core_dc);
635         *dc = NULL;
636 }
637
638 static bool is_validation_required(
639                 const struct core_dc *dc,
640                 const struct dc_validation_set set[],
641                 int set_count)
642 {
643         const struct validate_context *context = dc->current_context;
644         int i, j;
645
646         if (context->stream_count != set_count)
647                 return true;
648
649         for (i = 0; i < set_count; i++) {
650
651                 if (set[i].surface_count != context->stream_status[i].surface_count)
652                         return true;
653                 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
654                         return true;
655
656                 for (j = 0; j < set[i].surface_count; j++) {
657                         struct dc_surface temp_surf;
658                         memset(&temp_surf, 0, sizeof(temp_surf));
659
660                         temp_surf = *context->stream_status[i].surfaces[j];
661                         temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
662                         temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
663                         temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
664
665                         if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
666                                 return true;
667                 }
668         }
669
670         return false;
671 }
672
673 struct validate_context *dc_get_validate_context(
674                 const struct dc *dc,
675                 const struct dc_validation_set set[],
676                 uint8_t set_count)
677 {
678         struct core_dc *core_dc = DC_TO_CORE(dc);
679         enum dc_status result = DC_ERROR_UNEXPECTED;
680         struct validate_context *context;
681
682         context = dm_alloc(sizeof(struct validate_context));
683         if (context == NULL)
684                 goto context_alloc_fail;
685
686         if (!is_validation_required(core_dc, set, set_count)) {
687                 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
688                 return context;
689         }
690
691         result = core_dc->res_pool->funcs->validate_with_context(
692                         core_dc, set, set_count, context, core_dc->current_context);
693
694 context_alloc_fail:
695         if (result != DC_OK) {
696                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
697                                 "%s:resource validation failed, dc_status:%d\n",
698                                 __func__,
699                                 result);
700
701                 dc_resource_validate_ctx_destruct(context);
702                 dm_free(context);
703                 context = NULL;
704         }
705
706         return context;
707
708 }
709
710 bool dc_validate_resources(
711                 const struct dc *dc,
712                 const struct dc_validation_set set[],
713                 uint8_t set_count)
714 {
715         struct core_dc *core_dc = DC_TO_CORE(dc);
716         enum dc_status result = DC_ERROR_UNEXPECTED;
717         struct validate_context *context;
718
719         context = dm_alloc(sizeof(struct validate_context));
720         if (context == NULL)
721                 goto context_alloc_fail;
722
723         result = core_dc->res_pool->funcs->validate_with_context(
724                                 core_dc, set, set_count, context, NULL);
725
726 context_alloc_fail:
727         if (result != DC_OK) {
728                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
729                                 "%s:resource validation failed, dc_status:%d\n",
730                                 __func__,
731                                 result);
732         }
733
734         dc_resource_validate_ctx_destruct(context);
735         dm_free(context);
736         context = NULL;
737
738         return result == DC_OK;
739 }
740
741 bool dc_validate_guaranteed(
742                 const struct dc *dc,
743                 const struct dc_stream *stream)
744 {
745         struct core_dc *core_dc = DC_TO_CORE(dc);
746         enum dc_status result = DC_ERROR_UNEXPECTED;
747         struct validate_context *context;
748
749         context = dm_alloc(sizeof(struct validate_context));
750         if (context == NULL)
751                 goto context_alloc_fail;
752
753         result = core_dc->res_pool->funcs->validate_guaranteed(
754                                         core_dc, stream, context);
755
756         dc_resource_validate_ctx_destruct(context);
757         dm_free(context);
758
759 context_alloc_fail:
760         if (result != DC_OK) {
761                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
762                         "%s:guaranteed validation failed, dc_status:%d\n",
763                         __func__,
764                         result);
765                 }
766
767         return (result == DC_OK);
768 }
769
770 static void program_timing_sync(
771                 struct core_dc *core_dc,
772                 struct validate_context *ctx)
773 {
774         int i, j;
775         int group_index = 0;
776         int pipe_count = core_dc->res_pool->pipe_count;
777         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
778
779         for (i = 0; i < pipe_count; i++) {
780                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
781                         continue;
782
783                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
784         }
785
786         for (i = 0; i < pipe_count; i++) {
787                 int group_size = 1;
788                 struct pipe_ctx *pipe_set[MAX_PIPES];
789
790                 if (!unsynced_pipes[i])
791                         continue;
792
793                 pipe_set[0] = unsynced_pipes[i];
794                 unsynced_pipes[i] = NULL;
795
796                 /* Add tg to the set, search rest of the tg's for ones with
797                  * same timing, add all tgs with same timing to the group
798                  */
799                 for (j = i + 1; j < pipe_count; j++) {
800                         if (!unsynced_pipes[j])
801                                 continue;
802
803                         if (resource_are_streams_timing_synchronizable(
804                                         unsynced_pipes[j]->stream,
805                                         pipe_set[0]->stream)) {
806                                 pipe_set[group_size] = unsynced_pipes[j];
807                                 unsynced_pipes[j] = NULL;
808                                 group_size++;
809                         }
810                 }
811
812                 /* set first unblanked pipe as master */
813                 for (j = 0; j < group_size; j++) {
814                         struct pipe_ctx *temp;
815
816                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
817                                 if (j == 0)
818                                         break;
819
820                                 temp = pipe_set[0];
821                                 pipe_set[0] = pipe_set[j];
822                                 pipe_set[j] = temp;
823                                 break;
824                         }
825                 }
826
827                 /* remove any other unblanked pipes as they have already been synced */
828                 for (j = j + 1; j < group_size; j++) {
829                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
830                                 group_size--;
831                                 pipe_set[j] = pipe_set[group_size];
832                                 j--;
833                         }
834                 }
835
836                 if (group_size > 1) {
837                         core_dc->hwss.enable_timing_synchronization(
838                                 core_dc, group_index, group_size, pipe_set);
839                         group_index++;
840                 }
841         }
842 }
843
844 static bool streams_changed(
845                 struct core_dc *dc,
846                 const struct dc_stream *streams[],
847                 uint8_t stream_count)
848 {
849         uint8_t i;
850
851         if (stream_count != dc->current_context->stream_count)
852                 return true;
853
854         for (i = 0; i < dc->current_context->stream_count; i++) {
855                 if (&dc->current_context->streams[i]->public != streams[i])
856                         return true;
857         }
858
859         return false;
860 }
861
862 bool dc_enable_stereo(
863         struct dc *dc,
864         struct validate_context *context,
865         const struct dc_stream *streams[],
866         uint8_t stream_count)
867 {
868         bool ret = true;
869         int i, j;
870         struct pipe_ctx *pipe;
871         struct core_dc *core_dc = DC_TO_CORE(dc);
872
873 #ifdef ENABLE_FBC
874         struct compressor *fbc_compressor = core_dc->fbc_compressor;
875 #endif
876
877         for (i = 0; i < MAX_PIPES; i++) {
878                 if (context != NULL)
879                         pipe = &context->res_ctx.pipe_ctx[i];
880                 else
881                         pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
882                 for (j = 0 ; pipe && j < stream_count; j++)  {
883                         if (streams[j] && streams[j] == &pipe->stream->public &&
884                                 core_dc->hwss.setup_stereo)
885                                 core_dc->hwss.setup_stereo(pipe, core_dc);
886                 }
887         }
888
889 #ifdef ENABLE_FBC
890         if (fbc_compressor != NULL &&
891             fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
892                                                         &pipe->tg->inst))
893                 fbc_compressor->funcs->disable_fbc(fbc_compressor);
894
895 #endif
896         return ret;
897 }
898
899 bool dc_commit_streams(
900         struct dc *dc,
901         const struct dc_stream *streams[],
902         uint8_t stream_count)
903 {
904         struct core_dc *core_dc = DC_TO_CORE(dc);
905         struct dc_bios *dcb = core_dc->ctx->dc_bios;
906         enum dc_status result = DC_ERROR_UNEXPECTED;
907         struct validate_context *context;
908         struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
909         int i, j;
910
911         if (false == streams_changed(core_dc, streams, stream_count))
912                 return DC_OK;
913
914         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
915                                 __func__, stream_count);
916
917         for (i = 0; i < stream_count; i++) {
918                 const struct dc_stream *stream = streams[i];
919                 const struct dc_stream_status *status = dc_stream_get_status(stream);
920                 int j;
921
922                 dc_stream_log(stream,
923                                 core_dc->ctx->logger,
924                                 LOG_DC);
925
926                 set[i].stream = stream;
927
928                 if (status) {
929                         set[i].surface_count = status->surface_count;
930                         for (j = 0; j < status->surface_count; j++)
931                                 set[i].surfaces[j] = status->surfaces[j];
932                 }
933
934         }
935
936         context = dm_alloc(sizeof(struct validate_context));
937         if (context == NULL)
938                 goto context_alloc_fail;
939
940         result = core_dc->res_pool->funcs->validate_with_context(
941                         core_dc, set, stream_count, context, core_dc->current_context);
942         if (result != DC_OK){
943                 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
944                                         "%s: Context validation failed! dc_status:%d\n",
945                                         __func__,
946                                         result);
947                 BREAK_TO_DEBUGGER();
948                 dc_resource_validate_ctx_destruct(context);
949                 goto fail;
950         }
951
952         if (!dcb->funcs->is_accelerated_mode(dcb)) {
953                 core_dc->hwss.enable_accelerated_mode(core_dc);
954         }
955
956         if (result == DC_OK) {
957                 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
958         }
959
960         program_timing_sync(core_dc, context);
961
962         for (i = 0; i < context->stream_count; i++) {
963                 const struct core_sink *sink = context->streams[i]->sink;
964
965                 for (j = 0; j < context->stream_status[i].surface_count; j++) {
966                         struct core_surface *surface =
967                                         DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
968
969                         core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
970                 }
971
972                 CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}",
973                                 context->streams[i]->public.src.width,
974                                 context->streams[i]->public.src.height,
975                                 context->streams[i]->public.timing.h_addressable,
976                                 context->streams[i]->public.timing.v_addressable,
977                                 context->streams[i]->public.timing.pix_clk_khz * 1000 /
978                                         context->streams[i]->public.timing.h_total /
979                                         context->streams[i]->public.timing.v_total, // Refresh rate
980                                 context->streams[i]->public.timing.h_total,
981                                 context->streams[i]->public.timing.v_total,
982                                 context->streams[i]->public.timing.pix_clk_khz);
983         }
984         dc_enable_stereo(dc, context, streams, stream_count);
985         dc_resource_validate_ctx_destruct(core_dc->current_context);
986         dm_free(core_dc->current_context);
987
988         core_dc->current_context = context;
989
990         return (result == DC_OK);
991
992 fail:
993         dm_free(context);
994
995 context_alloc_fail:
996         return (result == DC_OK);
997 }
998
999 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1000 {
1001         int i;
1002         struct core_dc *core_dc = DC_TO_CORE(dc);
1003         struct validate_context *context = core_dc->current_context;
1004
1005         post_surface_trace(dc);
1006
1007         for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1008                 if (context->res_ctx.pipe_ctx[i].stream == NULL
1009                                 || context->res_ctx.pipe_ctx[i].surface == NULL)
1010                         core_dc->hwss.power_down_front_end(core_dc, i);
1011
1012         /* 3rd param should be true, temp w/a for RV*/
1013 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1014         core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1015 #else
1016         core_dc->hwss.set_bandwidth(core_dc, context, true);
1017 #endif
1018         return true;
1019 }
1020
1021 bool dc_commit_surfaces_to_stream(
1022                 struct dc *dc,
1023                 const struct dc_surface **new_surfaces,
1024                 uint8_t new_surface_count,
1025                 const struct dc_stream *dc_stream)
1026 {
1027         struct dc_surface_update updates[MAX_SURFACES];
1028         struct dc_flip_addrs flip_addr[MAX_SURFACES];
1029         struct dc_plane_info plane_info[MAX_SURFACES];
1030         struct dc_scaling_info scaling_info[MAX_SURFACES];
1031         int i;
1032         struct dc_stream_update *stream_update =
1033                         dm_alloc(sizeof(struct dc_stream_update));
1034
1035         if (!stream_update) {
1036                 BREAK_TO_DEBUGGER();
1037                 return false;
1038         }
1039
1040         memset(updates, 0, sizeof(updates));
1041         memset(flip_addr, 0, sizeof(flip_addr));
1042         memset(plane_info, 0, sizeof(plane_info));
1043         memset(scaling_info, 0, sizeof(scaling_info));
1044
1045         stream_update->src = dc_stream->src;
1046         stream_update->dst = dc_stream->dst;
1047
1048         for (i = 0; i < new_surface_count; i++) {
1049                 updates[i].surface = new_surfaces[i];
1050                 updates[i].gamma =
1051                         (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1052                 flip_addr[i].address = new_surfaces[i]->address;
1053                 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1054                 plane_info[i].color_space = new_surfaces[i]->color_space;
1055                 plane_info[i].format = new_surfaces[i]->format;
1056                 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1057                 plane_info[i].rotation = new_surfaces[i]->rotation;
1058                 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1059                 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1060                 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1061                 plane_info[i].visible = new_surfaces[i]->visible;
1062                 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1063                 plane_info[i].dcc = new_surfaces[i]->dcc;
1064                 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1065                 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1066                 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1067                 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1068
1069                 updates[i].flip_addr = &flip_addr[i];
1070                 updates[i].plane_info = &plane_info[i];
1071                 updates[i].scaling_info = &scaling_info[i];
1072         }
1073
1074         dc_update_surfaces_and_stream(
1075                         dc,
1076                         updates,
1077                         new_surface_count,
1078                         dc_stream, stream_update);
1079
1080         dc_post_update_surfaces_to_stream(dc);
1081
1082         dm_free(stream_update);
1083         return true;
1084 }
1085
1086 static bool is_surface_in_context(
1087                 const struct validate_context *context,
1088                 const struct dc_surface *surface)
1089 {
1090         int j;
1091
1092         for (j = 0; j < MAX_PIPES; j++) {
1093                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1094
1095                 if (surface == &pipe_ctx->surface->public) {
1096                         return true;
1097                 }
1098         }
1099
1100         return false;
1101 }
1102
1103 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1104 {
1105         switch (format) {
1106         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1107         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1108                 return 12;
1109         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1110         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1111         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1112         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1113                 return 16;
1114         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1115         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1116         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1117         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1118                 return 32;
1119         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1120         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1121         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1122                 return 64;
1123         default:
1124                 ASSERT_CRITICAL(false);
1125                 return -1;
1126         }
1127 }
1128
1129 static enum surface_update_type get_plane_info_update_type(
1130                 const struct dc_surface_update *u,
1131                 int surface_index)
1132 {
1133         struct dc_plane_info temp_plane_info;
1134         memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1135
1136         if (!u->plane_info)
1137                 return UPDATE_TYPE_FAST;
1138
1139         temp_plane_info = *u->plane_info;
1140
1141         /* Copy all parameters that will cause a full update
1142          * from current surface, the rest of the parameters
1143          * from provided plane configuration.
1144          * Perform memory compare and special validation
1145          * for those that can cause fast/medium updates
1146          */
1147
1148         /* Full update parameters */
1149         temp_plane_info.color_space = u->surface->color_space;
1150         temp_plane_info.dcc = u->surface->dcc;
1151         temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1152         temp_plane_info.plane_size = u->surface->plane_size;
1153         temp_plane_info.rotation = u->surface->rotation;
1154         temp_plane_info.stereo_format = u->surface->stereo_format;
1155         temp_plane_info.tiling_info = u->surface->tiling_info;
1156
1157         if (surface_index == 0)
1158                 temp_plane_info.visible = u->plane_info->visible;
1159         else
1160                 temp_plane_info.visible = u->surface->visible;
1161
1162         if (memcmp(u->plane_info, &temp_plane_info,
1163                         sizeof(struct dc_plane_info)) != 0)
1164                 return UPDATE_TYPE_FULL;
1165
1166         if (pixel_format_to_bpp(u->plane_info->format) !=
1167                         pixel_format_to_bpp(u->surface->format)) {
1168                 return UPDATE_TYPE_FULL;
1169         } else {
1170                 return UPDATE_TYPE_MED;
1171         }
1172 }
1173
1174 static enum surface_update_type  get_scaling_info_update_type(
1175                 const struct dc_surface_update *u)
1176 {
1177         if (!u->scaling_info)
1178                 return UPDATE_TYPE_FAST;
1179
1180         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1181                         || u->scaling_info->src_rect.height != u->surface->src_rect.height
1182                         || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1183                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1184                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1185                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1186                 return UPDATE_TYPE_FULL;
1187
1188         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1189                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1190                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1191                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1192                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1193                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1194                 return UPDATE_TYPE_MED;
1195
1196         return UPDATE_TYPE_FAST;
1197 }
1198
1199 static enum surface_update_type det_surface_update(
1200                 const struct core_dc *dc,
1201                 const struct dc_surface_update *u,
1202                 int surface_index)
1203 {
1204         const struct validate_context *context = dc->current_context;
1205         enum surface_update_type type = UPDATE_TYPE_FAST;
1206         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1207
1208         if (!is_surface_in_context(context, u->surface))
1209                 return UPDATE_TYPE_FULL;
1210
1211         type = get_plane_info_update_type(u, surface_index);
1212         if (overall_type < type)
1213                 overall_type = type;
1214
1215         type = get_scaling_info_update_type(u);
1216         if (overall_type < type)
1217                 overall_type = type;
1218
1219         if (u->in_transfer_func ||
1220                 u->hdr_static_metadata) {
1221                 if (overall_type < UPDATE_TYPE_MED)
1222                         overall_type = UPDATE_TYPE_MED;
1223         }
1224
1225         return overall_type;
1226 }
1227
1228 enum surface_update_type dc_check_update_surfaces_for_stream(
1229                 struct dc *dc,
1230                 struct dc_surface_update *updates,
1231                 int surface_count,
1232                 struct dc_stream_update *stream_update,
1233                 const struct dc_stream_status *stream_status)
1234 {
1235         struct core_dc *core_dc = DC_TO_CORE(dc);
1236         int i;
1237         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1238
1239         if (stream_status == NULL || stream_status->surface_count != surface_count)
1240                 return UPDATE_TYPE_FULL;
1241
1242         if (stream_update)
1243                 return UPDATE_TYPE_FULL;
1244
1245         for (i = 0 ; i < surface_count; i++) {
1246                 enum surface_update_type type =
1247                                 det_surface_update(core_dc, &updates[i], i);
1248
1249                 if (type == UPDATE_TYPE_FULL)
1250                         return type;
1251
1252                 if (overall_type < type)
1253                         overall_type = type;
1254         }
1255
1256         return overall_type;
1257 }
1258
1259 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1260
1261 void dc_update_surfaces_and_stream(struct dc *dc,
1262                 struct dc_surface_update *srf_updates, int surface_count,
1263                 const struct dc_stream *dc_stream,
1264                 struct dc_stream_update *stream_update)
1265 {
1266         struct core_dc *core_dc = DC_TO_CORE(dc);
1267         struct validate_context *context;
1268         int i, j;
1269         enum surface_update_type update_type;
1270         const struct dc_stream_status *stream_status;
1271         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1272
1273         stream_status = dc_stream_get_status(dc_stream);
1274         ASSERT(stream_status);
1275         if (!stream_status)
1276                 return; /* Cannot commit surface to stream that is not committed */
1277
1278 #ifdef ENABLE_FBC
1279         if (srf_updates->flip_addr) {
1280                 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1281                         ASSERT(0);
1282         }
1283 #endif
1284         context = core_dc->current_context;
1285
1286         /* update current stream with the new updates */
1287         if (stream_update) {
1288                 if ((stream_update->src.height != 0) &&
1289                                 (stream_update->src.width != 0))
1290                         stream->public.src = stream_update->src;
1291
1292                 if ((stream_update->dst.height != 0) &&
1293                                 (stream_update->dst.width != 0))
1294                         stream->public.dst = stream_update->dst;
1295
1296                 if (stream_update->out_transfer_func &&
1297                                 stream_update->out_transfer_func !=
1298                                                 dc_stream->out_transfer_func) {
1299                         if (dc_stream->out_transfer_func != NULL)
1300                                 dc_transfer_func_release(dc_stream->out_transfer_func);
1301                         dc_transfer_func_retain(stream_update->out_transfer_func);
1302                         stream->public.out_transfer_func =
1303                                 stream_update->out_transfer_func;
1304                 }
1305         }
1306
1307         /* do not perform surface update if surface has invalid dimensions
1308          * (all zero) and no scaling_info is provided
1309          */
1310         if (surface_count > 0 &&
1311                         srf_updates->surface->src_rect.width == 0 &&
1312                         srf_updates->surface->src_rect.height == 0 &&
1313                         srf_updates->surface->dst_rect.width == 0 &&
1314                         srf_updates->surface->dst_rect.height == 0 &&
1315                         !srf_updates->scaling_info) {
1316                 ASSERT(false);
1317                 return;
1318         }
1319
1320         update_type = dc_check_update_surfaces_for_stream(
1321                         dc, srf_updates, surface_count, stream_update, stream_status);
1322
1323         if (update_type >= update_surface_trace_level)
1324                 update_surface_trace(dc, srf_updates, surface_count);
1325
1326         if (update_type >= UPDATE_TYPE_FULL) {
1327                 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1328
1329                 for (i = 0; i < surface_count; i++)
1330                         new_surfaces[i] = srf_updates[i].surface;
1331
1332                 /* initialize scratch memory for building context */
1333                 context = dm_alloc(sizeof(*context));
1334                 dc_resource_validate_ctx_copy_construct(
1335                                 core_dc->current_context, context);
1336
1337                 /* add surface to context */
1338                 if (!resource_attach_surfaces_to_context(
1339                                 new_surfaces, surface_count, dc_stream,
1340                                 context, core_dc->res_pool)) {
1341                         BREAK_TO_DEBUGGER();
1342                         goto fail;
1343                 }
1344         }
1345
1346         /* save update parameters into surface */
1347         for (i = 0; i < surface_count; i++) {
1348                 struct core_surface *surface =
1349                                 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1350
1351                 if (srf_updates[i].flip_addr) {
1352                         surface->public.address = srf_updates[i].flip_addr->address;
1353                         surface->public.flip_immediate =
1354                                         srf_updates[i].flip_addr->flip_immediate;
1355                 }
1356
1357                 if (srf_updates[i].scaling_info) {
1358                         surface->public.scaling_quality =
1359                                         srf_updates[i].scaling_info->scaling_quality;
1360                         surface->public.dst_rect =
1361                                         srf_updates[i].scaling_info->dst_rect;
1362                         surface->public.src_rect =
1363                                         srf_updates[i].scaling_info->src_rect;
1364                         surface->public.clip_rect =
1365                                         srf_updates[i].scaling_info->clip_rect;
1366                 }
1367
1368                 if (srf_updates[i].plane_info) {
1369                         surface->public.color_space =
1370                                         srf_updates[i].plane_info->color_space;
1371                         surface->public.format =
1372                                         srf_updates[i].plane_info->format;
1373                         surface->public.plane_size =
1374                                         srf_updates[i].plane_info->plane_size;
1375                         surface->public.rotation =
1376                                         srf_updates[i].plane_info->rotation;
1377                         surface->public.horizontal_mirror =
1378                                         srf_updates[i].plane_info->horizontal_mirror;
1379                         surface->public.stereo_format =
1380                                         srf_updates[i].plane_info->stereo_format;
1381                         surface->public.tiling_info =
1382                                         srf_updates[i].plane_info->tiling_info;
1383                         surface->public.visible =
1384                                         srf_updates[i].plane_info->visible;
1385                         surface->public.per_pixel_alpha =
1386                                         srf_updates[i].plane_info->per_pixel_alpha;
1387                         surface->public.dcc =
1388                                         srf_updates[i].plane_info->dcc;
1389                 }
1390
1391                 if (update_type >= UPDATE_TYPE_MED) {
1392                         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1393                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1394
1395                                 if (pipe_ctx->surface != surface)
1396                                         continue;
1397
1398                                 resource_build_scaling_params(pipe_ctx);
1399                         }
1400                 }
1401
1402                 if (srf_updates[i].gamma &&
1403                         srf_updates[i].gamma != surface->public.gamma_correction) {
1404                         if (surface->public.gamma_correction != NULL)
1405                                 dc_gamma_release(&surface->public.
1406                                                 gamma_correction);
1407
1408                         dc_gamma_retain(srf_updates[i].gamma);
1409                         surface->public.gamma_correction =
1410                                                 srf_updates[i].gamma;
1411                 }
1412
1413                 if (srf_updates[i].in_transfer_func &&
1414                         srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1415                         if (surface->public.in_transfer_func != NULL)
1416                                 dc_transfer_func_release(
1417                                                 surface->public.
1418                                                 in_transfer_func);
1419
1420                         dc_transfer_func_retain(
1421                                         srf_updates[i].in_transfer_func);
1422                         surface->public.in_transfer_func =
1423                                         srf_updates[i].in_transfer_func;
1424                 }
1425
1426                 if (srf_updates[i].hdr_static_metadata)
1427                         surface->public.hdr_static_ctx =
1428                                 *(srf_updates[i].hdr_static_metadata);
1429         }
1430
1431         if (update_type == UPDATE_TYPE_FULL) {
1432                 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1433                         BREAK_TO_DEBUGGER();
1434                         goto fail;
1435                 } else {
1436                         core_dc->hwss.set_bandwidth(core_dc, context, false);
1437                         context_clock_trace(dc, context);
1438                 }
1439         }
1440
1441         if (surface_count == 0)
1442                 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1443
1444         /* Lock pipes for provided surfaces, or all active if full update*/
1445         for (i = 0; i < surface_count; i++) {
1446                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1447
1448                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1449                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1450
1451                         if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1452                                 continue;
1453                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1454                                 continue;
1455
1456                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1457                                 core_dc->hwss.pipe_control_lock(
1458                                                 core_dc,
1459                                                 pipe_ctx,
1460                                                 true);
1461                         }
1462                 }
1463                 if (update_type == UPDATE_TYPE_FULL)
1464                         break;
1465         }
1466
1467         /* Full fe update*/
1468         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1469                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1470                 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1471                 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1472                 struct dc_cursor_position position = { 0 };
1473
1474                 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1475                         continue;
1476
1477                 if (!pipe_ctx->top_pipe)
1478                         core_dc->hwss.apply_ctx_for_surface(
1479                                         core_dc, pipe_ctx->surface, context);
1480
1481                 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1482                 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1483
1484                 if (is_new_pipe_surface) {
1485                         core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1486                         core_dc->hwss.set_input_transfer_func(
1487                                         pipe_ctx, pipe_ctx->surface);
1488                         core_dc->hwss.set_output_transfer_func(
1489                                         pipe_ctx, pipe_ctx->stream);
1490                 }
1491         }
1492
1493         if (update_type > UPDATE_TYPE_FAST)
1494                 context_timing_trace(dc, &context->res_ctx);
1495
1496         /* Perform requested Updates */
1497         for (i = 0; i < surface_count; i++) {
1498                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1499
1500                 if (update_type == UPDATE_TYPE_MED)
1501                         core_dc->hwss.apply_ctx_for_surface(
1502                                         core_dc, surface, context);
1503
1504                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1505                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1506
1507                         if (pipe_ctx->surface != surface)
1508                                 continue;
1509
1510                         if (srf_updates[i].flip_addr)
1511                                 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1512
1513                         if (update_type == UPDATE_TYPE_FAST)
1514                                 continue;
1515
1516                         if (srf_updates[i].in_transfer_func)
1517                                 core_dc->hwss.set_input_transfer_func(
1518                                                 pipe_ctx, pipe_ctx->surface);
1519
1520                         if (stream_update != NULL &&
1521                                         stream_update->out_transfer_func != NULL) {
1522                                 core_dc->hwss.set_output_transfer_func(
1523                                                 pipe_ctx, pipe_ctx->stream);
1524                         }
1525
1526                         if (srf_updates[i].hdr_static_metadata) {
1527                                 resource_build_info_frame(pipe_ctx);
1528                                 core_dc->hwss.update_info_frame(pipe_ctx);
1529                         }
1530                 }
1531         }
1532
1533         /* Unlock pipes */
1534         for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1535                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1536
1537                 for (j = 0; j < surface_count; j++) {
1538                         if (update_type != UPDATE_TYPE_FULL &&
1539                                         srf_updates[j].surface != &pipe_ctx->surface->public)
1540                                 continue;
1541                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1542                                 continue;
1543
1544                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1545                                 core_dc->hwss.pipe_control_lock(
1546                                                 core_dc,
1547                                                 pipe_ctx,
1548                                                 false);
1549                         }
1550                         break;
1551                 }
1552         }
1553
1554         if (core_dc->current_context != context) {
1555                 dc_resource_validate_ctx_destruct(core_dc->current_context);
1556                 dm_free(core_dc->current_context);
1557
1558                 core_dc->current_context = context;
1559         }
1560         return;
1561
1562 fail:
1563         dc_resource_validate_ctx_destruct(context);
1564         dm_free(context);
1565 }
1566
1567 uint8_t dc_get_current_stream_count(const struct dc *dc)
1568 {
1569         struct core_dc *core_dc = DC_TO_CORE(dc);
1570         return core_dc->current_context->stream_count;
1571 }
1572
1573 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1574 {
1575         struct core_dc *core_dc = DC_TO_CORE(dc);
1576         if (i < core_dc->current_context->stream_count)
1577                 return &(core_dc->current_context->streams[i]->public);
1578         return NULL;
1579 }
1580
1581 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1582 {
1583         struct core_dc *core_dc = DC_TO_CORE(dc);
1584         return &core_dc->links[link_index]->public;
1585 }
1586
1587 const struct graphics_object_id dc_get_link_id_at_index(
1588         struct dc *dc, uint32_t link_index)
1589 {
1590         struct core_dc *core_dc = DC_TO_CORE(dc);
1591         return core_dc->links[link_index]->link_id;
1592 }
1593
1594 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1595         struct dc *dc, uint32_t link_index)
1596 {
1597         struct core_dc *core_dc = DC_TO_CORE(dc);
1598         return core_dc->links[link_index]->public.irq_source_hpd;
1599 }
1600
1601 const struct audio **dc_get_audios(struct dc *dc)
1602 {
1603         struct core_dc *core_dc = DC_TO_CORE(dc);
1604         return (const struct audio **)core_dc->res_pool->audios;
1605 }
1606
1607 enum dc_irq_source dc_interrupt_to_irq_source(
1608                 struct dc *dc,
1609                 uint32_t src_id,
1610                 uint32_t ext_id)
1611 {
1612         struct core_dc *core_dc = DC_TO_CORE(dc);
1613         return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1614 }
1615
1616 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1617 {
1618         struct core_dc *core_dc;
1619
1620         if (dc == NULL)
1621                 return;
1622         core_dc = DC_TO_CORE(dc);
1623
1624         dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1625 }
1626
1627 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1628 {
1629         struct core_dc *core_dc = DC_TO_CORE(dc);
1630         dal_irq_service_ack(core_dc->res_pool->irqs, src);
1631 }
1632
1633 void dc_set_power_state(
1634         struct dc *dc,
1635         enum dc_acpi_cm_power_state power_state)
1636 {
1637         struct core_dc *core_dc = DC_TO_CORE(dc);
1638
1639         switch (power_state) {
1640         case DC_ACPI_CM_POWER_STATE_D0:
1641                 core_dc->hwss.init_hw(core_dc);
1642                 break;
1643         default:
1644
1645                 core_dc->hwss.power_down(core_dc);
1646
1647                 /* Zero out the current context so that on resume we start with
1648                  * clean state, and dc hw programming optimizations will not
1649                  * cause any trouble.
1650                  */
1651                 memset(core_dc->current_context, 0,
1652                                 sizeof(*core_dc->current_context));
1653
1654                 break;
1655         }
1656
1657 }
1658
1659 void dc_resume(const struct dc *dc)
1660 {
1661         struct core_dc *core_dc = DC_TO_CORE(dc);
1662
1663         uint32_t i;
1664
1665         for (i = 0; i < core_dc->link_count; i++)
1666                 core_link_resume(core_dc->links[i]);
1667 }
1668
1669 bool dc_read_aux_dpcd(
1670                 struct dc *dc,
1671                 uint32_t link_index,
1672                 uint32_t address,
1673                 uint8_t *data,
1674                 uint32_t size)
1675 {
1676         struct core_dc *core_dc = DC_TO_CORE(dc);
1677
1678         struct core_link *link = core_dc->links[link_index];
1679         enum ddc_result r = dal_ddc_service_read_dpcd_data(
1680                         link->public.ddc,
1681                         false,
1682                         I2C_MOT_UNDEF,
1683                         address,
1684                         data,
1685                         size);
1686         return r == DDC_RESULT_SUCESSFULL;
1687 }
1688
1689 bool dc_write_aux_dpcd(
1690                 struct dc *dc,
1691                 uint32_t link_index,
1692                 uint32_t address,
1693                 const uint8_t *data,
1694                 uint32_t size)
1695 {
1696         struct core_dc *core_dc = DC_TO_CORE(dc);
1697         struct core_link *link = core_dc->links[link_index];
1698
1699         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1700                         link->public.ddc,
1701                         false,
1702                         I2C_MOT_UNDEF,
1703                         address,
1704                         data,
1705                         size);
1706         return r == DDC_RESULT_SUCESSFULL;
1707 }
1708
1709 bool dc_read_aux_i2c(
1710                 struct dc *dc,
1711                 uint32_t link_index,
1712                 enum i2c_mot_mode mot,
1713                 uint32_t address,
1714                 uint8_t *data,
1715                 uint32_t size)
1716 {
1717         struct core_dc *core_dc = DC_TO_CORE(dc);
1718
1719                 struct core_link *link = core_dc->links[link_index];
1720                 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1721                         link->public.ddc,
1722                         true,
1723                         mot,
1724                         address,
1725                         data,
1726                         size);
1727                 return r == DDC_RESULT_SUCESSFULL;
1728 }
1729
1730 bool dc_write_aux_i2c(
1731                 struct dc *dc,
1732                 uint32_t link_index,
1733                 enum i2c_mot_mode mot,
1734                 uint32_t address,
1735                 const uint8_t *data,
1736                 uint32_t size)
1737 {
1738         struct core_dc *core_dc = DC_TO_CORE(dc);
1739         struct core_link *link = core_dc->links[link_index];
1740
1741         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1742                         link->public.ddc,
1743                         true,
1744                         mot,
1745                         address,
1746                         data,
1747                         size);
1748         return r == DDC_RESULT_SUCESSFULL;
1749 }
1750
1751 bool dc_query_ddc_data(
1752                 struct dc *dc,
1753                 uint32_t link_index,
1754                 uint32_t address,
1755                 uint8_t *write_buf,
1756                 uint32_t write_size,
1757                 uint8_t *read_buf,
1758                 uint32_t read_size) {
1759
1760         struct core_dc *core_dc = DC_TO_CORE(dc);
1761
1762         struct core_link *link = core_dc->links[link_index];
1763
1764         bool result = dal_ddc_service_query_ddc_data(
1765                         link->public.ddc,
1766                         address,
1767                         write_buf,
1768                         write_size,
1769                         read_buf,
1770                         read_size);
1771
1772         return result;
1773 }
1774
1775 bool dc_submit_i2c(
1776                 struct dc *dc,
1777                 uint32_t link_index,
1778                 struct i2c_command *cmd)
1779 {
1780         struct core_dc *core_dc = DC_TO_CORE(dc);
1781
1782         struct core_link *link = core_dc->links[link_index];
1783         struct ddc_service *ddc = link->public.ddc;
1784
1785         return dal_i2caux_submit_i2c_command(
1786                 ddc->ctx->i2caux,
1787                 ddc->ddc_pin,
1788                 cmd);
1789 }
1790
1791 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1792 {
1793         struct dc_link *dc_link = &core_link->public;
1794
1795         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1796                 BREAK_TO_DEBUGGER();
1797                 return false;
1798         }
1799
1800         dc_sink_retain(sink);
1801
1802         dc_link->remote_sinks[dc_link->sink_count] = sink;
1803         dc_link->sink_count++;
1804
1805         return true;
1806 }
1807
1808 struct dc_sink *dc_link_add_remote_sink(
1809                 const struct dc_link *link,
1810                 const uint8_t *edid,
1811                 int len,
1812                 struct dc_sink_init_data *init_data)
1813 {
1814         struct dc_sink *dc_sink;
1815         enum dc_edid_status edid_status;
1816         struct core_link *core_link = DC_LINK_TO_LINK(link);
1817
1818         if (len > MAX_EDID_BUFFER_SIZE) {
1819                 dm_error("Max EDID buffer size breached!\n");
1820                 return NULL;
1821         }
1822
1823         if (!init_data) {
1824                 BREAK_TO_DEBUGGER();
1825                 return NULL;
1826         }
1827
1828         if (!init_data->link) {
1829                 BREAK_TO_DEBUGGER();
1830                 return NULL;
1831         }
1832
1833         dc_sink = dc_sink_create(init_data);
1834
1835         if (!dc_sink)
1836                 return NULL;
1837
1838         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1839         dc_sink->dc_edid.length = len;
1840
1841         if (!link_add_remote_sink_helper(
1842                         core_link,
1843                         dc_sink))
1844                 goto fail_add_sink;
1845
1846         edid_status = dm_helpers_parse_edid_caps(
1847                         core_link->ctx,
1848                         &dc_sink->dc_edid,
1849                         &dc_sink->edid_caps);
1850
1851         if (edid_status != EDID_OK)
1852                 goto fail;
1853
1854         return dc_sink;
1855 fail:
1856         dc_link_remove_remote_sink(link, dc_sink);
1857 fail_add_sink:
1858         dc_sink_release(dc_sink);
1859         return NULL;
1860 }
1861
1862 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1863 {
1864         struct core_link *core_link = DC_LINK_TO_LINK(link);
1865         struct dc_link *dc_link = &core_link->public;
1866
1867         dc_link->local_sink = sink;
1868
1869         if (sink == NULL) {
1870                 dc_link->type = dc_connection_none;
1871         } else {
1872                 dc_link->type = dc_connection_single;
1873         }
1874 }
1875
1876 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1877 {
1878         int i;
1879         struct core_link *core_link = DC_LINK_TO_LINK(link);
1880         struct dc_link *dc_link = &core_link->public;
1881
1882         if (!link->sink_count) {
1883                 BREAK_TO_DEBUGGER();
1884                 return;
1885         }
1886
1887         for (i = 0; i < dc_link->sink_count; i++) {
1888                 if (dc_link->remote_sinks[i] == sink) {
1889                         dc_sink_release(sink);
1890                         dc_link->remote_sinks[i] = NULL;
1891
1892                         /* shrink array to remove empty place */
1893                         while (i < dc_link->sink_count - 1) {
1894                                 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1895                                 i++;
1896                         }
1897                         dc_link->remote_sinks[i] = NULL;
1898                         dc_link->sink_count--;
1899                         return;
1900                 }
1901         }
1902 }
1903
1904 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1905 {
1906         int i;
1907         struct core_dc *core_dc = DC_TO_CORE(dc);
1908         struct mem_input *mi = NULL;
1909
1910         for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1911                 if (core_dc->res_pool->mis[i] != NULL) {
1912                         mi = core_dc->res_pool->mis[i];
1913                         break;
1914                 }
1915         }
1916         if (mi == NULL) {
1917                 dm_error("no mem_input!\n");
1918                 return false;
1919         }
1920
1921         if (mi->funcs->mem_input_update_dchub)
1922                 mi->funcs->mem_input_update_dchub(mi, dh_data);
1923         else
1924                 ASSERT(mi->funcs->mem_input_update_dchub);
1925
1926
1927         return true;
1928
1929 }
1930