2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
45 #include "link_hwss.h"
46 #include "link_encoder.h"
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
52 /*******************************************************************************
54 ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
59 for (i = 0; i < dc->link_count; i++) {
60 if (NULL != dc->links[i])
61 link_destroy(&dc->links[i]);
65 static bool create_links(
67 uint32_t num_virtual_links)
71 struct dc_bios *bios = dc->ctx->dc_bios;
75 connectors_num = bios->funcs->get_connectors_number(bios);
77 if (connectors_num > ENUM_ID_COUNT) {
79 "DC: Number of connectors %d exceeds maximum of %d!\n",
85 if (connectors_num == 0 && num_virtual_links == 0) {
86 dm_error("DC: Number of connectors is zero!\n");
90 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
95 for (i = 0; i < connectors_num; i++) {
96 struct link_init_data link_init_params = {0};
97 struct core_link *link;
99 link_init_params.ctx = dc->ctx;
100 /* next BIOS object table connector */
101 link_init_params.connector_index = i;
102 link_init_params.link_index = dc->link_count;
103 link_init_params.dc = dc;
104 link = link_create(&link_init_params);
107 dc->links[dc->link_count] = link;
113 for (i = 0; i < num_virtual_links; i++) {
114 struct core_link *link = dm_alloc(sizeof(*link));
115 struct encoder_init_data enc_init = {0};
124 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127 link->link_id.enum_id = ENUM_ID_1;
128 link->link_enc = dm_alloc(sizeof(*link->link_enc));
130 enc_init.ctx = dc->ctx;
131 enc_init.channel = CHANNEL_ID_UNKNOWN;
132 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134 enc_init.connector = link->link_id;
135 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137 enc_init.encoder.enum_id = ENUM_ID_1;
138 virtual_link_encoder_construct(link->link_enc, &enc_init);
140 link->public.link_index = dc->link_count;
141 dc->links[dc->link_count] = link;
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152 const struct dc_stream **stream, int num_streams,
155 /* TODO: Support multiple streams */
156 struct core_dc *core_dc = DC_TO_CORE(dc);
157 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
161 for (i = 0; i < MAX_PIPES; i++) {
162 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
164 if (pipe->stream == core_stream && pipe->stream_enc) {
165 core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
167 /* build and update the info frame */
168 resource_build_info_frame(pipe);
169 core_dc->hwss.update_info_frame(pipe);
177 static bool stream_get_crtc_position(struct dc *dc,
178 const struct dc_stream **stream, int num_streams,
179 unsigned int *v_pos, unsigned int *nom_v_pos)
181 /* TODO: Support multiple streams */
182 struct core_dc *core_dc = DC_TO_CORE(dc);
183 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
186 struct crtc_position position;
188 for (i = 0; i < MAX_PIPES; i++) {
189 struct pipe_ctx *pipe =
190 &core_dc->current_context->res_ctx.pipe_ctx[i];
192 if (pipe->stream == core_stream && pipe->stream_enc) {
193 core_dc->hwss.get_position(&pipe, 1, &position);
195 *v_pos = position.vertical_count;
196 *nom_v_pos = position.nominal_vcount;
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
205 struct core_dc *core_dc = DC_TO_CORE(dc);
206 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
209 struct pipe_ctx *pipes;
211 for (i = 0; i < MAX_PIPES; i++) {
212 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
215 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216 core_dc->hwss.program_gamut_remap(pipes);
224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
226 struct core_dc *core_dc = DC_TO_CORE(dc);
227 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
230 struct pipe_ctx *pipes;
232 for (i = 0; i < MAX_PIPES; i++) {
233 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
236 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
237 core_dc->hwss.program_csc_matrix(pipes,
238 core_stream->public.output_color_space,
239 core_stream->public.csc_color_matrix.matrix);
247 static void set_static_screen_events(struct dc *dc,
248 const struct dc_stream **stream,
250 const struct dc_static_screen_events *events)
252 struct core_dc *core_dc = DC_TO_CORE(dc);
255 struct pipe_ctx *pipes_affected[MAX_PIPES];
256 int num_pipes_affected = 0;
258 for (i = 0; i < num_streams; i++) {
259 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
261 for (j = 0; j < MAX_PIPES; j++) {
262 if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
264 pipes_affected[num_pipes_affected++] =
265 &core_dc->current_context->res_ctx.pipe_ctx[j];
270 core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
273 static void set_drive_settings(struct dc *dc,
274 struct link_training_settings *lt_settings,
275 const struct dc_link *link)
277 struct core_dc *core_dc = DC_TO_CORE(dc);
280 for (i = 0; i < core_dc->link_count; i++) {
281 if (&core_dc->links[i]->public == link)
285 if (i >= core_dc->link_count)
286 ASSERT_CRITICAL(false);
288 dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
291 static void perform_link_training(struct dc *dc,
292 struct dc_link_settings *link_setting,
293 bool skip_video_pattern)
295 struct core_dc *core_dc = DC_TO_CORE(dc);
298 for (i = 0; i < core_dc->link_count; i++)
299 dc_link_dp_perform_link_training(
300 &core_dc->links[i]->public,
305 static void set_preferred_link_settings(struct dc *dc,
306 struct dc_link_settings *link_setting,
307 const struct dc_link *link)
309 struct core_link *core_link = DC_LINK_TO_CORE(link);
311 core_link->public.preferred_link_setting =
313 dp_retrain_link_dp_test(core_link, link_setting, false);
316 static void enable_hpd(const struct dc_link *link)
318 dc_link_dp_enable_hpd(link);
321 static void disable_hpd(const struct dc_link *link)
323 dc_link_dp_disable_hpd(link);
327 static void set_test_pattern(
328 const struct dc_link *link,
329 enum dp_test_pattern test_pattern,
330 const struct link_training_settings *p_link_settings,
331 const unsigned char *p_custom_pattern,
332 unsigned int cust_pattern_size)
335 dc_link_dp_set_test_pattern(
343 void set_dither_option(const struct dc_stream *dc_stream,
344 enum dc_dither_option option)
346 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
347 struct bit_depth_reduction_params params;
348 struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
349 struct pipe_ctx *pipes =
350 core_link->dc->current_context->res_ctx.pipe_ctx;
352 memset(¶ms, 0, sizeof(params));
355 if (option > DITHER_OPTION_MAX)
357 if (option == DITHER_OPTION_DEFAULT) {
358 switch (stream->public.timing.display_color_depth) {
359 case COLOR_DEPTH_666:
360 stream->public.dither_option = DITHER_OPTION_SPATIAL6;
362 case COLOR_DEPTH_888:
363 stream->public.dither_option = DITHER_OPTION_SPATIAL8;
365 case COLOR_DEPTH_101010:
366 stream->public.dither_option = DITHER_OPTION_SPATIAL10;
369 option = DITHER_OPTION_DISABLE;
372 stream->public.dither_option = option;
374 resource_build_bit_depth_reduction_params(stream,
376 stream->bit_depth_params = params;
378 opp_program_bit_depth_reduction(pipes->opp, ¶ms);
381 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
383 if (core_dc->hwss.set_drr != NULL) {
384 core_dc->public.stream_funcs.adjust_vmin_vmax =
385 stream_adjust_vmin_vmax;
388 core_dc->public.stream_funcs.set_static_screen_events =
389 set_static_screen_events;
391 core_dc->public.stream_funcs.get_crtc_position =
392 stream_get_crtc_position;
394 core_dc->public.stream_funcs.set_gamut_remap =
397 core_dc->public.stream_funcs.program_csc_matrix =
400 core_dc->public.stream_funcs.set_dither_option =
403 core_dc->public.link_funcs.set_drive_settings =
406 core_dc->public.link_funcs.perform_link_training =
407 perform_link_training;
409 core_dc->public.link_funcs.set_preferred_link_settings =
410 set_preferred_link_settings;
412 core_dc->public.link_funcs.enable_hpd =
415 core_dc->public.link_funcs.disable_hpd =
418 core_dc->public.link_funcs.set_test_pattern =
422 static void destruct(struct core_dc *dc)
424 dc_release_validate_context(dc->current_context);
425 dc->current_context = NULL;
429 dc_destroy_resource_pool(dc);
431 if (dc->ctx->gpio_service)
432 dal_gpio_service_destroy(&dc->ctx->gpio_service);
435 dal_i2caux_destroy(&dc->ctx->i2caux);
437 if (dc->ctx->created_bios)
438 dal_bios_parser_destroy(&dc->ctx->dc_bios);
441 dal_logger_destroy(&dc->ctx->logger);
447 static bool construct(struct core_dc *dc,
448 const struct dc_init_data *init_params)
450 struct dal_logger *logger;
451 struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
452 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
455 dm_error("%s: failed to create ctx\n", __func__);
459 dc->current_context = dm_alloc(sizeof(*dc->current_context));
461 if (!dc->current_context) {
462 dm_error("%s: failed to create validate ctx\n", __func__);
466 dc->current_context->ref_count++;
468 dc_ctx->cgs_device = init_params->cgs_device;
469 dc_ctx->driver_context = init_params->driver;
470 dc_ctx->dc = &dc->public;
471 dc_ctx->asic_id = init_params->asic_id;
474 logger = dal_logger_create(dc_ctx);
477 /* can *not* call logger. call base driver 'print error' */
478 dm_error("%s: failed to create Logger!\n", __func__);
481 dc_ctx->logger = logger;
483 dc->ctx->dce_environment = init_params->dce_environment;
485 dc_version = resource_parse_asic_id(init_params->asic_id);
486 dc->ctx->dce_version = dc_version;
488 /* Resource should construct all asic specific resources.
489 * This should be the only place where we need to parse the asic id
491 if (init_params->vbios_override)
492 dc_ctx->dc_bios = init_params->vbios_override;
494 /* Create BIOS parser */
495 struct bp_init_data bp_init_data;
497 bp_init_data.ctx = dc_ctx;
498 bp_init_data.bios = init_params->asic_id.atombios_base_address;
500 dc_ctx->dc_bios = dal_bios_parser_create(
501 &bp_init_data, dc_version);
503 if (!dc_ctx->dc_bios) {
504 ASSERT_CRITICAL(false);
508 dc_ctx->created_bios = true;
512 dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
514 if (!dc_ctx->i2caux) {
515 ASSERT_CRITICAL(false);
516 goto failed_to_create_i2caux;
519 /* Create GPIO service */
520 dc_ctx->gpio_service = dal_gpio_service_create(
522 dc_ctx->dce_environment,
525 if (!dc_ctx->gpio_service) {
526 ASSERT_CRITICAL(false);
530 dc->res_pool = dc_create_resource_pool(
532 init_params->num_virtual_links,
534 init_params->asic_id);
536 goto create_resource_fail;
538 if (!create_links(dc, init_params->num_virtual_links))
539 goto create_links_fail;
541 allocate_dc_stream_funcs(dc);
545 /**** error handling here ****/
547 create_resource_fail:
549 failed_to_create_i2caux:
559 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
561 fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
562 unsigned int pixDurationInPico = round(pixel_duration);
564 DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
566 arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
567 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
568 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
570 arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
571 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
572 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
574 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
575 WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
577 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
578 WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
582 /*******************************************************************************
584 ******************************************************************************/
586 struct dc *dc_create(const struct dc_init_data *init_params)
588 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
589 unsigned int full_pipe_count;
594 if (false == construct(core_dc, init_params))
597 /*TODO: separate HW and SW initialization*/
598 core_dc->hwss.init_hw(core_dc);
600 full_pipe_count = core_dc->res_pool->pipe_count;
601 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
603 core_dc->public.caps.max_streams = min(
605 core_dc->res_pool->stream_enc_count);
607 core_dc->public.caps.max_links = core_dc->link_count;
608 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
610 core_dc->public.config = init_params->flags;
612 dm_logger_write(core_dc->ctx->logger, LOG_DC,
613 "Display Core initialized\n");
616 /* TODO: missing feature to be enabled */
617 core_dc->public.debug.disable_dfs_bypass = true;
619 return &core_dc->public;
628 void dc_destroy(struct dc **dc)
630 struct core_dc *core_dc = DC_TO_CORE(*dc);
636 static bool is_validation_required(
637 const struct core_dc *dc,
638 const struct dc_validation_set set[],
641 const struct validate_context *context = dc->current_context;
644 if (context->stream_count != set_count)
647 for (i = 0; i < set_count; i++) {
649 if (set[i].surface_count != context->stream_status[i].surface_count)
651 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
654 for (j = 0; j < set[i].surface_count; j++) {
655 struct dc_surface temp_surf;
656 memset(&temp_surf, 0, sizeof(temp_surf));
658 temp_surf = *context->stream_status[i].surfaces[j];
659 temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
660 temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
661 temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
663 if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
671 struct validate_context *dc_get_validate_context(
673 const struct dc_validation_set set[],
676 struct core_dc *core_dc = DC_TO_CORE(dc);
677 enum dc_status result = DC_ERROR_UNEXPECTED;
678 struct validate_context *context;
680 context = dm_alloc(sizeof(struct validate_context));
682 goto context_alloc_fail;
684 ++context->ref_count;
686 if (!is_validation_required(core_dc, set, set_count)) {
687 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
691 result = core_dc->res_pool->funcs->validate_with_context(
692 core_dc, set, set_count, context, core_dc->current_context);
695 if (result != DC_OK) {
696 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
697 "%s:resource validation failed, dc_status:%d\n",
701 dc_release_validate_context(context);
709 bool dc_validate_resources(
711 const struct dc_validation_set set[],
714 struct core_dc *core_dc = DC_TO_CORE(dc);
715 enum dc_status result = DC_ERROR_UNEXPECTED;
716 struct validate_context *context;
718 context = dm_alloc(sizeof(struct validate_context));
720 goto context_alloc_fail;
722 ++context->ref_count;
724 result = core_dc->res_pool->funcs->validate_with_context(
725 core_dc, set, set_count, context, NULL);
728 if (result != DC_OK) {
729 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
730 "%s:resource validation failed, dc_status:%d\n",
735 dc_release_validate_context(context);
738 return result == DC_OK;
741 bool dc_validate_guaranteed(
743 const struct dc_stream *stream)
745 struct core_dc *core_dc = DC_TO_CORE(dc);
746 enum dc_status result = DC_ERROR_UNEXPECTED;
747 struct validate_context *context;
749 context = dm_alloc(sizeof(struct validate_context));
751 goto context_alloc_fail;
753 ++context->ref_count;
755 result = core_dc->res_pool->funcs->validate_guaranteed(
756 core_dc, stream, context);
758 dc_release_validate_context(context);
761 if (result != DC_OK) {
762 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
763 "%s:guaranteed validation failed, dc_status:%d\n",
768 return (result == DC_OK);
771 static void program_timing_sync(
772 struct core_dc *core_dc,
773 struct validate_context *ctx)
777 int pipe_count = core_dc->res_pool->pipe_count;
778 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
780 for (i = 0; i < pipe_count; i++) {
781 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
784 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
787 for (i = 0; i < pipe_count; i++) {
789 struct pipe_ctx *pipe_set[MAX_PIPES];
791 if (!unsynced_pipes[i])
794 pipe_set[0] = unsynced_pipes[i];
795 unsynced_pipes[i] = NULL;
797 /* Add tg to the set, search rest of the tg's for ones with
798 * same timing, add all tgs with same timing to the group
800 for (j = i + 1; j < pipe_count; j++) {
801 if (!unsynced_pipes[j])
804 if (resource_are_streams_timing_synchronizable(
805 unsynced_pipes[j]->stream,
806 pipe_set[0]->stream)) {
807 pipe_set[group_size] = unsynced_pipes[j];
808 unsynced_pipes[j] = NULL;
813 /* set first unblanked pipe as master */
814 for (j = 0; j < group_size; j++) {
815 struct pipe_ctx *temp;
817 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
822 pipe_set[0] = pipe_set[j];
828 /* remove any other unblanked pipes as they have already been synced */
829 for (j = j + 1; j < group_size; j++) {
830 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
832 pipe_set[j] = pipe_set[group_size];
837 if (group_size > 1) {
838 core_dc->hwss.enable_timing_synchronization(
839 core_dc, group_index, group_size, pipe_set);
845 static bool context_changed(
847 struct validate_context *context)
851 if (context->stream_count != dc->current_context->stream_count)
854 for (i = 0; i < dc->current_context->stream_count; i++) {
855 if (&dc->current_context->streams[i]->public != &context->streams[i]->public)
862 static bool streams_changed(
864 const struct dc_stream *streams[],
865 uint8_t stream_count)
869 if (stream_count != dc->current_context->stream_count)
872 for (i = 0; i < dc->current_context->stream_count; i++) {
873 if (&dc->current_context->streams[i]->public != streams[i])
880 bool dc_enable_stereo(
882 struct validate_context *context,
883 const struct dc_stream *streams[],
884 uint8_t stream_count)
888 struct pipe_ctx *pipe;
889 struct core_dc *core_dc = DC_TO_CORE(dc);
892 struct compressor *fbc_compressor = core_dc->fbc_compressor;
895 for (i = 0; i < MAX_PIPES; i++) {
897 pipe = &context->res_ctx.pipe_ctx[i];
899 pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
900 for (j = 0 ; pipe && j < stream_count; j++) {
901 if (streams[j] && streams[j] == &pipe->stream->public &&
902 core_dc->hwss.setup_stereo)
903 core_dc->hwss.setup_stereo(pipe, core_dc);
908 if (fbc_compressor != NULL &&
909 fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
911 fbc_compressor->funcs->disable_fbc(fbc_compressor);
919 * Applies given context to HW and copy it into current context.
920 * It's up to the user to release the src context afterwards.
922 static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context)
924 struct core_dc *core_dc = DC_TO_CORE(dc);
925 struct dc_bios *dcb = core_dc->ctx->dc_bios;
926 enum dc_status result = DC_ERROR_UNEXPECTED;
927 struct pipe_ctx *pipe;
929 const struct dc_stream *dc_streams[MAX_STREAMS] = {0};
931 for (i = 0; i < context->stream_count; i++)
932 dc_streams[i] = &context->streams[i]->public;
934 if (!dcb->funcs->is_accelerated_mode(dcb))
935 core_dc->hwss.enable_accelerated_mode(core_dc);
937 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
939 program_timing_sync(core_dc, context);
941 for (i = 0; i < context->stream_count; i++) {
942 const struct core_sink *sink = context->streams[i]->sink;
944 for (j = 0; j < context->stream_status[i].surface_count; j++) {
945 struct core_surface *surface =
946 DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
948 core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
952 * TODO rework dc_enable_stereo call to work with validation sets?
954 for (k = 0; k < MAX_PIPES; k++) {
955 pipe = &context->res_ctx.pipe_ctx[k];
957 for (l = 0 ; pipe && l < context->stream_count; l++) {
958 if (context->streams[l] &&
959 context->streams[l] == pipe->stream &&
960 core_dc->hwss.setup_stereo)
961 core_dc->hwss.setup_stereo(pipe, core_dc);
966 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
967 context->streams[i]->public.timing.h_addressable,
968 context->streams[i]->public.timing.v_addressable,
969 context->streams[i]->public.timing.h_total,
970 context->streams[i]->public.timing.v_total,
971 context->streams[i]->public.timing.pix_clk_khz);
974 dc_enable_stereo(dc, context, dc_streams, context->stream_count);
976 dc_release_validate_context(core_dc->current_context);
978 core_dc->current_context = context;
980 dc_retain_validate_context(core_dc->current_context);
982 return (result == DC_OK);
985 bool dc_commit_context(struct dc *dc, struct validate_context *context)
987 enum dc_status result = DC_ERROR_UNEXPECTED;
988 struct core_dc *core_dc = DC_TO_CORE(dc);
991 if (false == context_changed(core_dc, context))
994 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
995 __func__, context->stream_count);
997 for (i = 0; i < context->stream_count; i++) {
998 const struct dc_stream *stream = &context->streams[i]->public;
1000 dc_stream_log(stream,
1001 core_dc->ctx->logger,
1005 result = dc_commit_context_no_check(dc, context);
1007 return (result == DC_OK);
1011 bool dc_commit_streams(
1013 const struct dc_stream *streams[],
1014 uint8_t stream_count)
1016 struct core_dc *core_dc = DC_TO_CORE(dc);
1017 enum dc_status result = DC_ERROR_UNEXPECTED;
1018 struct validate_context *context;
1019 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
1022 if (false == streams_changed(core_dc, streams, stream_count))
1025 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
1026 __func__, stream_count);
1028 for (i = 0; i < stream_count; i++) {
1029 const struct dc_stream *stream = streams[i];
1030 const struct dc_stream_status *status = dc_stream_get_status(stream);
1033 dc_stream_log(stream,
1034 core_dc->ctx->logger,
1037 set[i].stream = stream;
1040 set[i].surface_count = status->surface_count;
1041 for (j = 0; j < status->surface_count; j++)
1042 set[i].surfaces[j] = status->surfaces[j];
1047 context = dm_alloc(sizeof(struct validate_context));
1048 if (context == NULL)
1049 goto context_alloc_fail;
1051 ++context->ref_count;
1053 result = core_dc->res_pool->funcs->validate_with_context(
1054 core_dc, set, stream_count, context, core_dc->current_context);
1055 if (result != DC_OK){
1056 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
1057 "%s: Context validation failed! dc_status:%d\n",
1060 BREAK_TO_DEBUGGER();
1064 result = dc_commit_context_no_check(dc, context);
1067 dc_release_validate_context(context);
1070 return (result == DC_OK);
1073 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1076 struct core_dc *core_dc = DC_TO_CORE(dc);
1077 struct validate_context *context = core_dc->current_context;
1079 post_surface_trace(dc);
1081 for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1082 if (context->res_ctx.pipe_ctx[i].stream == NULL
1083 || context->res_ctx.pipe_ctx[i].surface == NULL)
1084 core_dc->hwss.power_down_front_end(core_dc, i);
1086 /* 3rd param should be true, temp w/a for RV*/
1087 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1088 core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1090 core_dc->hwss.set_bandwidth(core_dc, context, true);
1095 bool dc_commit_surfaces_to_stream(
1097 const struct dc_surface **new_surfaces,
1098 uint8_t new_surface_count,
1099 const struct dc_stream *dc_stream)
1101 struct dc_surface_update updates[MAX_SURFACES];
1102 struct dc_flip_addrs flip_addr[MAX_SURFACES];
1103 struct dc_plane_info plane_info[MAX_SURFACES];
1104 struct dc_scaling_info scaling_info[MAX_SURFACES];
1106 struct dc_stream_update *stream_update =
1107 dm_alloc(sizeof(struct dc_stream_update));
1109 if (!stream_update) {
1110 BREAK_TO_DEBUGGER();
1114 memset(updates, 0, sizeof(updates));
1115 memset(flip_addr, 0, sizeof(flip_addr));
1116 memset(plane_info, 0, sizeof(plane_info));
1117 memset(scaling_info, 0, sizeof(scaling_info));
1119 stream_update->src = dc_stream->src;
1120 stream_update->dst = dc_stream->dst;
1121 stream_update->out_transfer_func = dc_stream->out_transfer_func;
1123 for (i = 0; i < new_surface_count; i++) {
1124 updates[i].surface = new_surfaces[i];
1126 (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1127 updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func;
1128 flip_addr[i].address = new_surfaces[i]->address;
1129 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1130 plane_info[i].color_space = new_surfaces[i]->color_space;
1131 plane_info[i].format = new_surfaces[i]->format;
1132 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1133 plane_info[i].rotation = new_surfaces[i]->rotation;
1134 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1135 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1136 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1137 plane_info[i].visible = new_surfaces[i]->visible;
1138 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1139 plane_info[i].dcc = new_surfaces[i]->dcc;
1140 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1141 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1142 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1143 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1145 updates[i].flip_addr = &flip_addr[i];
1146 updates[i].plane_info = &plane_info[i];
1147 updates[i].scaling_info = &scaling_info[i];
1150 dc_update_surfaces_and_stream(
1154 dc_stream, stream_update);
1156 dc_post_update_surfaces_to_stream(dc);
1158 dm_free(stream_update);
1162 void dc_retain_validate_context(struct validate_context *context)
1164 ASSERT(context->ref_count > 0);
1165 ++context->ref_count;
1168 void dc_release_validate_context(struct validate_context *context)
1170 ASSERT(context->ref_count > 0);
1171 --context->ref_count;
1173 if (context->ref_count == 0) {
1174 dc_resource_validate_ctx_destruct(context);
1179 static bool is_surface_in_context(
1180 const struct validate_context *context,
1181 const struct dc_surface *surface)
1185 for (j = 0; j < MAX_PIPES; j++) {
1186 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1188 if (surface == &pipe_ctx->surface->public) {
1196 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1199 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1200 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1202 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1203 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1204 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1205 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1207 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1208 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1209 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1210 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1212 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1213 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1214 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1217 ASSERT_CRITICAL(false);
1222 static enum surface_update_type get_plane_info_update_type(
1223 const struct dc_surface_update *u,
1226 struct dc_plane_info temp_plane_info;
1227 memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1230 return UPDATE_TYPE_FAST;
1232 temp_plane_info = *u->plane_info;
1234 /* Copy all parameters that will cause a full update
1235 * from current surface, the rest of the parameters
1236 * from provided plane configuration.
1237 * Perform memory compare and special validation
1238 * for those that can cause fast/medium updates
1241 /* Full update parameters */
1242 temp_plane_info.color_space = u->surface->color_space;
1243 temp_plane_info.dcc = u->surface->dcc;
1244 temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1245 temp_plane_info.plane_size = u->surface->plane_size;
1246 temp_plane_info.rotation = u->surface->rotation;
1247 temp_plane_info.stereo_format = u->surface->stereo_format;
1248 temp_plane_info.tiling_info = u->surface->tiling_info;
1250 if (surface_index == 0)
1251 temp_plane_info.visible = u->plane_info->visible;
1253 temp_plane_info.visible = u->surface->visible;
1255 if (memcmp(u->plane_info, &temp_plane_info,
1256 sizeof(struct dc_plane_info)) != 0)
1257 return UPDATE_TYPE_FULL;
1259 if (pixel_format_to_bpp(u->plane_info->format) !=
1260 pixel_format_to_bpp(u->surface->format)) {
1261 return UPDATE_TYPE_FULL;
1263 return UPDATE_TYPE_MED;
1267 static enum surface_update_type get_scaling_info_update_type(
1268 const struct dc_surface_update *u)
1270 if (!u->scaling_info)
1271 return UPDATE_TYPE_FAST;
1273 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1274 || u->scaling_info->src_rect.height != u->surface->src_rect.height
1275 || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1276 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1277 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1278 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1279 return UPDATE_TYPE_FULL;
1281 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1282 || u->scaling_info->src_rect.y != u->surface->src_rect.y
1283 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1284 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1285 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1286 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1287 return UPDATE_TYPE_MED;
1289 return UPDATE_TYPE_FAST;
1292 static enum surface_update_type det_surface_update(
1293 const struct core_dc *dc,
1294 const struct dc_surface_update *u,
1297 const struct validate_context *context = dc->current_context;
1298 enum surface_update_type type = UPDATE_TYPE_FAST;
1299 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1301 if (!is_surface_in_context(context, u->surface))
1302 return UPDATE_TYPE_FULL;
1304 type = get_plane_info_update_type(u, surface_index);
1305 if (overall_type < type)
1306 overall_type = type;
1308 type = get_scaling_info_update_type(u);
1309 if (overall_type < type)
1310 overall_type = type;
1312 if (u->in_transfer_func ||
1313 u->hdr_static_metadata) {
1314 if (overall_type < UPDATE_TYPE_MED)
1315 overall_type = UPDATE_TYPE_MED;
1318 return overall_type;
1321 enum surface_update_type dc_check_update_surfaces_for_stream(
1323 struct dc_surface_update *updates,
1325 struct dc_stream_update *stream_update,
1326 const struct dc_stream_status *stream_status)
1328 struct core_dc *core_dc = DC_TO_CORE(dc);
1330 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1332 if (stream_status == NULL || stream_status->surface_count != surface_count)
1333 return UPDATE_TYPE_FULL;
1336 return UPDATE_TYPE_FULL;
1338 for (i = 0 ; i < surface_count; i++) {
1339 enum surface_update_type type =
1340 det_surface_update(core_dc, &updates[i], i);
1342 if (type == UPDATE_TYPE_FULL)
1345 if (overall_type < type)
1346 overall_type = type;
1349 return overall_type;
1352 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1354 void dc_update_surfaces_and_stream(struct dc *dc,
1355 struct dc_surface_update *srf_updates, int surface_count,
1356 const struct dc_stream *dc_stream,
1357 struct dc_stream_update *stream_update)
1359 struct core_dc *core_dc = DC_TO_CORE(dc);
1360 struct validate_context *context;
1362 enum surface_update_type update_type;
1363 const struct dc_stream_status *stream_status;
1364 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1365 struct dc_context *dc_ctx = core_dc->ctx;
1367 stream_status = dc_stream_get_status(dc_stream);
1368 ASSERT(stream_status);
1370 return; /* Cannot commit surface to stream that is not committed */
1373 if (srf_updates->flip_addr) {
1374 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1378 context = core_dc->current_context;
1380 /* update current stream with the new updates */
1381 if (stream_update) {
1382 if ((stream_update->src.height != 0) &&
1383 (stream_update->src.width != 0))
1384 stream->public.src = stream_update->src;
1386 if ((stream_update->dst.height != 0) &&
1387 (stream_update->dst.width != 0))
1388 stream->public.dst = stream_update->dst;
1390 if (stream_update->out_transfer_func &&
1391 stream_update->out_transfer_func !=
1392 dc_stream->out_transfer_func) {
1393 if (dc_stream->out_transfer_func != NULL)
1394 dc_transfer_func_release(dc_stream->out_transfer_func);
1395 dc_transfer_func_retain(stream_update->out_transfer_func);
1396 stream->public.out_transfer_func =
1397 stream_update->out_transfer_func;
1401 /* do not perform surface update if surface has invalid dimensions
1402 * (all zero) and no scaling_info is provided
1404 if (surface_count > 0 &&
1405 srf_updates->surface->src_rect.width == 0 &&
1406 srf_updates->surface->src_rect.height == 0 &&
1407 srf_updates->surface->dst_rect.width == 0 &&
1408 srf_updates->surface->dst_rect.height == 0 &&
1409 !srf_updates->scaling_info) {
1414 update_type = dc_check_update_surfaces_for_stream(
1415 dc, srf_updates, surface_count, stream_update, stream_status);
1417 if (update_type >= update_surface_trace_level)
1418 update_surface_trace(dc, srf_updates, surface_count);
1420 if (update_type >= UPDATE_TYPE_FULL) {
1421 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1423 for (i = 0; i < surface_count; i++)
1424 new_surfaces[i] = srf_updates[i].surface;
1426 /* initialize scratch memory for building context */
1427 context = dm_alloc(sizeof(*context));
1428 if (context == NULL)
1429 goto context_alloc_fail;
1431 ++context->ref_count;
1433 dc_resource_validate_ctx_copy_construct(
1434 core_dc->current_context, context);
1436 /* add surface to context */
1437 if (!resource_attach_surfaces_to_context(
1438 new_surfaces, surface_count, dc_stream,
1439 context, core_dc->res_pool)) {
1440 BREAK_TO_DEBUGGER();
1445 /* save update parameters into surface */
1446 for (i = 0; i < surface_count; i++) {
1447 struct core_surface *surface =
1448 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1450 if (srf_updates[i].flip_addr) {
1451 surface->public.address = srf_updates[i].flip_addr->address;
1452 surface->public.flip_immediate =
1453 srf_updates[i].flip_addr->flip_immediate;
1456 if (srf_updates[i].scaling_info) {
1457 surface->public.scaling_quality =
1458 srf_updates[i].scaling_info->scaling_quality;
1459 surface->public.dst_rect =
1460 srf_updates[i].scaling_info->dst_rect;
1461 surface->public.src_rect =
1462 srf_updates[i].scaling_info->src_rect;
1463 surface->public.clip_rect =
1464 srf_updates[i].scaling_info->clip_rect;
1467 if (srf_updates[i].plane_info) {
1468 surface->public.color_space =
1469 srf_updates[i].plane_info->color_space;
1470 surface->public.format =
1471 srf_updates[i].plane_info->format;
1472 surface->public.plane_size =
1473 srf_updates[i].plane_info->plane_size;
1474 surface->public.rotation =
1475 srf_updates[i].plane_info->rotation;
1476 surface->public.horizontal_mirror =
1477 srf_updates[i].plane_info->horizontal_mirror;
1478 surface->public.stereo_format =
1479 srf_updates[i].plane_info->stereo_format;
1480 surface->public.tiling_info =
1481 srf_updates[i].plane_info->tiling_info;
1482 surface->public.visible =
1483 srf_updates[i].plane_info->visible;
1484 surface->public.per_pixel_alpha =
1485 srf_updates[i].plane_info->per_pixel_alpha;
1486 surface->public.dcc =
1487 srf_updates[i].plane_info->dcc;
1490 if (update_type >= UPDATE_TYPE_MED) {
1491 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1492 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1494 if (pipe_ctx->surface != surface)
1497 resource_build_scaling_params(pipe_ctx);
1501 if (srf_updates[i].gamma &&
1502 srf_updates[i].gamma != surface->public.gamma_correction) {
1503 if (surface->public.gamma_correction != NULL)
1504 dc_gamma_release(&surface->public.
1507 dc_gamma_retain(srf_updates[i].gamma);
1508 surface->public.gamma_correction =
1509 srf_updates[i].gamma;
1512 if (srf_updates[i].in_transfer_func &&
1513 srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1514 if (surface->public.in_transfer_func != NULL)
1515 dc_transfer_func_release(
1519 dc_transfer_func_retain(
1520 srf_updates[i].in_transfer_func);
1521 surface->public.in_transfer_func =
1522 srf_updates[i].in_transfer_func;
1525 if (srf_updates[i].hdr_static_metadata)
1526 surface->public.hdr_static_ctx =
1527 *(srf_updates[i].hdr_static_metadata);
1530 if (update_type == UPDATE_TYPE_FULL) {
1531 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1532 BREAK_TO_DEBUGGER();
1535 core_dc->hwss.set_bandwidth(core_dc, context, false);
1536 context_clock_trace(dc, context);
1540 if (surface_count == 0)
1541 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1543 /* Lock pipes for provided surfaces, or all active if full update*/
1544 for (i = 0; i < surface_count; i++) {
1545 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1547 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1548 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1550 if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1552 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1555 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1556 core_dc->hwss.pipe_control_lock(
1562 if (update_type == UPDATE_TYPE_FULL)
1567 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1568 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1569 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1570 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1571 struct dc_cursor_position position = { 0 };
1573 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1576 if (!pipe_ctx->top_pipe)
1577 core_dc->hwss.apply_ctx_for_surface(
1578 core_dc, pipe_ctx->surface, context);
1580 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1581 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1583 if (is_new_pipe_surface) {
1584 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1585 core_dc->hwss.set_input_transfer_func(
1586 pipe_ctx, pipe_ctx->surface);
1587 core_dc->hwss.set_output_transfer_func(
1588 pipe_ctx, pipe_ctx->stream);
1592 if (update_type > UPDATE_TYPE_FAST)
1593 context_timing_trace(dc, &context->res_ctx);
1595 /* Perform requested Updates */
1596 for (i = 0; i < surface_count; i++) {
1597 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1599 if (update_type == UPDATE_TYPE_MED)
1600 core_dc->hwss.apply_ctx_for_surface(
1601 core_dc, surface, context);
1603 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1604 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1606 if (pipe_ctx->surface != surface)
1609 if (srf_updates[i].flip_addr)
1610 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1612 if (update_type == UPDATE_TYPE_FAST)
1615 if (srf_updates[i].in_transfer_func)
1616 core_dc->hwss.set_input_transfer_func(
1617 pipe_ctx, pipe_ctx->surface);
1619 if (stream_update != NULL &&
1620 stream_update->out_transfer_func != NULL) {
1621 core_dc->hwss.set_output_transfer_func(
1622 pipe_ctx, pipe_ctx->stream);
1625 if (srf_updates[i].hdr_static_metadata) {
1626 resource_build_info_frame(pipe_ctx);
1627 core_dc->hwss.update_info_frame(pipe_ctx);
1633 for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1634 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1636 for (j = 0; j < surface_count; j++) {
1637 if (update_type != UPDATE_TYPE_FULL &&
1638 srf_updates[j].surface != &pipe_ctx->surface->public)
1640 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1643 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1644 core_dc->hwss.pipe_control_lock(
1653 if (core_dc->current_context != context) {
1654 dc_release_validate_context(core_dc->current_context);
1655 core_dc->current_context = context;
1660 dc_release_validate_context(context);
1663 DC_ERROR("Failed to allocate new validate context!\n");
1666 uint8_t dc_get_current_stream_count(const struct dc *dc)
1668 struct core_dc *core_dc = DC_TO_CORE(dc);
1669 return core_dc->current_context->stream_count;
1672 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1674 struct core_dc *core_dc = DC_TO_CORE(dc);
1675 if (i < core_dc->current_context->stream_count)
1676 return &(core_dc->current_context->streams[i]->public);
1680 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1682 struct core_dc *core_dc = DC_TO_CORE(dc);
1683 return &core_dc->links[link_index]->public;
1686 const struct graphics_object_id dc_get_link_id_at_index(
1687 struct dc *dc, uint32_t link_index)
1689 struct core_dc *core_dc = DC_TO_CORE(dc);
1690 return core_dc->links[link_index]->link_id;
1693 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1694 struct dc *dc, uint32_t link_index)
1696 struct core_dc *core_dc = DC_TO_CORE(dc);
1697 return core_dc->links[link_index]->public.irq_source_hpd;
1700 const struct audio **dc_get_audios(struct dc *dc)
1702 struct core_dc *core_dc = DC_TO_CORE(dc);
1703 return (const struct audio **)core_dc->res_pool->audios;
1706 enum dc_irq_source dc_interrupt_to_irq_source(
1711 struct core_dc *core_dc = DC_TO_CORE(dc);
1712 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1715 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1717 struct core_dc *core_dc;
1721 core_dc = DC_TO_CORE(dc);
1723 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1726 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1728 struct core_dc *core_dc = DC_TO_CORE(dc);
1729 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1732 void dc_set_power_state(
1734 enum dc_acpi_cm_power_state power_state)
1736 struct core_dc *core_dc = DC_TO_CORE(dc);
1739 switch (power_state) {
1740 case DC_ACPI_CM_POWER_STATE_D0:
1741 core_dc->hwss.init_hw(core_dc);
1745 core_dc->hwss.power_down(core_dc);
1747 /* Zero out the current context so that on resume we start with
1748 * clean state, and dc hw programming optimizations will not
1749 * cause any trouble.
1752 /* Preserve refcount */
1753 ref_count = core_dc->current_context->ref_count;
1754 dc_resource_validate_ctx_destruct(core_dc->current_context);
1755 memset(core_dc->current_context, 0,
1756 sizeof(*core_dc->current_context));
1757 core_dc->current_context->ref_count = ref_count;
1764 void dc_resume(const struct dc *dc)
1766 struct core_dc *core_dc = DC_TO_CORE(dc);
1770 for (i = 0; i < core_dc->link_count; i++)
1771 core_link_resume(core_dc->links[i]);
1774 bool dc_read_aux_dpcd(
1776 uint32_t link_index,
1781 struct core_dc *core_dc = DC_TO_CORE(dc);
1783 struct core_link *link = core_dc->links[link_index];
1784 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1791 return r == DDC_RESULT_SUCESSFULL;
1794 bool dc_write_aux_dpcd(
1796 uint32_t link_index,
1798 const uint8_t *data,
1801 struct core_dc *core_dc = DC_TO_CORE(dc);
1802 struct core_link *link = core_dc->links[link_index];
1804 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1811 return r == DDC_RESULT_SUCESSFULL;
1814 bool dc_read_aux_i2c(
1816 uint32_t link_index,
1817 enum i2c_mot_mode mot,
1822 struct core_dc *core_dc = DC_TO_CORE(dc);
1824 struct core_link *link = core_dc->links[link_index];
1825 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1832 return r == DDC_RESULT_SUCESSFULL;
1835 bool dc_write_aux_i2c(
1837 uint32_t link_index,
1838 enum i2c_mot_mode mot,
1840 const uint8_t *data,
1843 struct core_dc *core_dc = DC_TO_CORE(dc);
1844 struct core_link *link = core_dc->links[link_index];
1846 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1853 return r == DDC_RESULT_SUCESSFULL;
1856 bool dc_query_ddc_data(
1858 uint32_t link_index,
1861 uint32_t write_size,
1863 uint32_t read_size) {
1865 struct core_dc *core_dc = DC_TO_CORE(dc);
1867 struct core_link *link = core_dc->links[link_index];
1869 bool result = dal_ddc_service_query_ddc_data(
1882 uint32_t link_index,
1883 struct i2c_command *cmd)
1885 struct core_dc *core_dc = DC_TO_CORE(dc);
1887 struct core_link *link = core_dc->links[link_index];
1888 struct ddc_service *ddc = link->public.ddc;
1890 return dal_i2caux_submit_i2c_command(
1896 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1898 struct dc_link *dc_link = &core_link->public;
1900 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1901 BREAK_TO_DEBUGGER();
1905 dc_sink_retain(sink);
1907 dc_link->remote_sinks[dc_link->sink_count] = sink;
1908 dc_link->sink_count++;
1913 struct dc_sink *dc_link_add_remote_sink(
1914 const struct dc_link *link,
1915 const uint8_t *edid,
1917 struct dc_sink_init_data *init_data)
1919 struct dc_sink *dc_sink;
1920 enum dc_edid_status edid_status;
1921 struct core_link *core_link = DC_LINK_TO_LINK(link);
1923 if (len > MAX_EDID_BUFFER_SIZE) {
1924 dm_error("Max EDID buffer size breached!\n");
1929 BREAK_TO_DEBUGGER();
1933 if (!init_data->link) {
1934 BREAK_TO_DEBUGGER();
1938 dc_sink = dc_sink_create(init_data);
1943 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1944 dc_sink->dc_edid.length = len;
1946 if (!link_add_remote_sink_helper(
1951 edid_status = dm_helpers_parse_edid_caps(
1954 &dc_sink->edid_caps);
1956 if (edid_status != EDID_OK)
1961 dc_link_remove_remote_sink(link, dc_sink);
1963 dc_sink_release(dc_sink);
1967 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1969 struct core_link *core_link = DC_LINK_TO_LINK(link);
1970 struct dc_link *dc_link = &core_link->public;
1972 dc_link->local_sink = sink;
1975 dc_link->type = dc_connection_none;
1977 dc_link->type = dc_connection_single;
1981 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1984 struct core_link *core_link = DC_LINK_TO_LINK(link);
1985 struct dc_link *dc_link = &core_link->public;
1987 if (!link->sink_count) {
1988 BREAK_TO_DEBUGGER();
1992 for (i = 0; i < dc_link->sink_count; i++) {
1993 if (dc_link->remote_sinks[i] == sink) {
1994 dc_sink_release(sink);
1995 dc_link->remote_sinks[i] = NULL;
1997 /* shrink array to remove empty place */
1998 while (i < dc_link->sink_count - 1) {
1999 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
2002 dc_link->remote_sinks[i] = NULL;
2003 dc_link->sink_count--;
2009 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
2012 struct core_dc *core_dc = DC_TO_CORE(dc);
2013 struct mem_input *mi = NULL;
2015 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
2016 if (core_dc->res_pool->mis[i] != NULL) {
2017 mi = core_dc->res_pool->mis[i];
2022 dm_error("no mem_input!\n");
2026 if (mi->funcs->mem_input_update_dchub)
2027 mi->funcs->mem_input_update_dchub(mi, dh_data);
2029 ASSERT(mi->funcs->mem_input_update_dchub);
2036 void dc_log_hw_state(struct dc *dc)
2038 struct core_dc *core_dc = DC_TO_CORE(dc);
2040 if (core_dc->hwss.log_hw_state)
2041 core_dc->hwss.log_hw_state(core_dc);