drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #include "dmub/dmub_srv.h"
  70
  71 #include "dce/dmub_hw_lock_mgr.h"
  72
  73 #include "dc_trace.h"
  74
  75 #define CTX \
  76         dc->ctx
  77
  78 #define DC_LOGGER \
  79         dc->ctx->logger
  80
  81 static const char DC_BUILD_ID[] = "production-build";
  82
  83 /**
  84  * DOC: Overview
  85  *
  86  * DC is the OS-agnostic component of the amdgpu DC driver.
  87  *
  88  * DC maintains and validates a set of structs representing the state of the
  89  * driver and writes that state to AMD hardware
  90  *
  91  * Main DC HW structs:
  92  *
  93  * struct dc - The central struct.  One per driver.  Created on driver load,
  94  * destroyed on driver unload.
  95  *
  96  * struct dc_context - One per driver.
  97  * Used as a backpointer by most other structs in dc.
  98  *
  99  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 100  * plugpoints).  Created on driver load, destroyed on driver unload.
 101  *
 102  * struct dc_sink - One per display.  Created on boot or hotplug.
 103  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 104  * (the display directly attached).  It may also have one or more remote
 105  * sinks (in the Multi-Stream Transport case)
 106  *
 107  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 108  * main pipeline.  Not directly accessible by dm.
 109  *
 110  * Main dc state structs:
 111  *
 112  * These structs can be created and destroyed as needed.  There is a full set of
 113  * these structs in dc->current_state representing the currently programmed state.
 114  *
 115  * struct dc_state - The global DC state to track global state information,
 116  * such as bandwidth values.
 117  *
 118  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 119  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 120  *
 121  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 122  * and may have more in the Multi-Plane Overlay case.
 123  *
 124  * struct resource_context - Represents the programmable state of everything in
 125  * the resource_pool.  Not directly accessible by dm.
 126  *
 127  * struct pipe_ctx - A member of struct resource_context.  Represents the
 128  * internal hardware pipeline components.  Each dc_plane_state has either
 129  * one or two (in the pipe-split case).
 130  */
 131
 132 /*******************************************************************************
 133  * Private functions
 134  ******************************************************************************/
 135
 136 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 137 {
 138         if (new > *original)
 139                 *original = new;
 140 }
 141
 142 static void destroy_links(struct dc *dc)
 143 {
 144         uint32_t i;
 145
 146         for (i = 0; i < dc->link_count; i++) {
 147                 if (NULL != dc->links[i])
 148                         link_destroy(&dc->links[i]);
 149         }
 150 }
 151
 152 static bool create_links(
 153                 struct dc *dc,
 154                 uint32_t num_virtual_links)
 155 {
 156         int i;
 157         int connectors_num;
 158         struct dc_bios *bios = dc->ctx->dc_bios;
 159
 160         dc->link_count = 0;
 161
 162         connectors_num = bios->funcs->get_connectors_number(bios);
 163
 164         if (connectors_num > ENUM_ID_COUNT) {
 165                 dm_error(
 166                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 167                         connectors_num,
 168                         ENUM_ID_COUNT);
 169                 return false;
 170         }
 171
 172         dm_output_to_console(
 173                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 174                 __func__,
 175                 connectors_num,
 176                 num_virtual_links);
 177
 178         for (i = 0; i < connectors_num; i++) {
 179                 struct link_init_data link_init_params = {0};
 180                 struct dc_link *link;
 181
 182                 link_init_params.ctx = dc->ctx;
 183                 /* next BIOS object table connector */
 184                 link_init_params.connector_index = i;
 185                 link_init_params.link_index = dc->link_count;
 186                 link_init_params.dc = dc;
 187                 link = link_create(&link_init_params);
 188
 189                 if (link) {
 190                         bool should_destory_link = false;
 191
 192                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 193                                 if (dc->config.edp_not_connected) {
 194                                         if (!IS_DIAG_DC(dc->ctx->dce_environment))
 195                                                 should_destory_link = true;
 196                                 } else {
 197                                         enum dc_connection_type type;
 198                                         dc_link_detect_sink(link, &type);
 199                                         if (type == dc_connection_none)
 200                                                 should_destory_link = true;
 201                                 }
 202                         }
 203
 204                         if (dc->config.force_enum_edp || !should_destory_link) {
 205                                 dc->links[dc->link_count] = link;
 206                                 link->dc = dc;
 207                                 ++dc->link_count;
 208                         } else {
 209                                 link_destroy(&link);
 210                         }
 211                 }
 212         }
 213
 214         for (i = 0; i < num_virtual_links; i++) {
 215                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 216                 struct encoder_init_data enc_init = {0};
 217
 218                 if (link == NULL) {
 219                         BREAK_TO_DEBUGGER();
 220                         goto failed_alloc;
 221                 }
 222
 223                 link->link_index = dc->link_count;
 224                 dc->links[dc->link_count] = link;
 225                 dc->link_count++;
 226
 227                 link->ctx = dc->ctx;
 228                 link->dc = dc;
 229                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 230                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 231                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 232                 link->link_id.enum_id = ENUM_ID_1;
 233                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 234
 235                 if (!link->link_enc) {
 236                         BREAK_TO_DEBUGGER();
 237                         goto failed_alloc;
 238                 }
 239
 240                 link->link_status.dpcd_caps = &link->dpcd_caps;
 241
 242                 enc_init.ctx = dc->ctx;
 243                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 244                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 245                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 246                 enc_init.connector = link->link_id;
 247                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 248                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 249                 enc_init.encoder.enum_id = ENUM_ID_1;
 250                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 251         }
 252
 253         return true;
 254
 255 failed_alloc:
 256         return false;
 257 }
 258
 259 static struct dc_perf_trace *dc_perf_trace_create(void)
 260 {
 261         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 262 }
 263
 264 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 265 {
 266         kfree(*perf_trace);
 267         *perf_trace = NULL;
 268 }
 269
 270 /**
 271  *****************************************************************************
 272  *  Function: dc_stream_adjust_vmin_vmax
 273  *
 274  *  @brief
 275  *     Looks up the pipe context of dc_stream_state and updates the
 276  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 277  *     Rate, which is a power-saving feature that targets reducing panel
 278  *     refresh rate while the screen is static
 279  *
 280  *  @param [in] dc: dc reference
 281  *  @param [in] stream: Initial dc stream state
 282  *  @param [in] adjust: Updated parameters for vertical_total_min and
 283  *  vertical_total_max
 284  *****************************************************************************
 285  */
 286 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 287                 struct dc_stream_state *stream,
 288                 struct dc_crtc_timing_adjust *adjust)
 289 {
 290         int i = 0;
 291         bool ret = false;
 292
 293         stream->adjust = *adjust;
 294
 295         for (i = 0; i < MAX_PIPES; i++) {
 296                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 297
 298                 if (pipe->stream == stream && pipe->stream_res.tg) {
 299                         dc->hwss.set_drr(&pipe,
 300                                         1,
 301                                         adjust->v_total_min,
 302                                         adjust->v_total_max,
 303                                         adjust->v_total_mid,
 304                                         adjust->v_total_mid_frame_num);
 305
 306                         ret = true;
 307                 }
 308         }
 309         return ret;
 310 }
 311
 312 bool dc_stream_get_crtc_position(struct dc *dc,
 313                 struct dc_stream_state **streams, int num_streams,
 314                 unsigned int *v_pos, unsigned int *nom_v_pos)
 315 {
 316         /* TODO: Support multiple streams */
 317         const struct dc_stream_state *stream = streams[0];
 318         int i = 0;
 319         bool ret = false;
 320         struct crtc_position position;
 321
 322         for (i = 0; i < MAX_PIPES; i++) {
 323                 struct pipe_ctx *pipe =
 324                                 &dc->current_state->res_ctx.pipe_ctx[i];
 325
 326                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 327                         dc->hwss.get_position(&pipe, 1, &position);
 328
 329                         *v_pos = position.vertical_count;
 330                         *nom_v_pos = position.nominal_vcount;
 331                         ret = true;
 332                 }
 333         }
 334         return ret;
 335 }
 336
 337 /**
 338  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 339  * @dc: DC Object
 340  * @stream: The stream to configure CRC on.
 341  * @enable: Enable CRC if true, disable otherwise.
 342  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 343  *              once.
 344  *
 345  * By default, only CRC0 is configured, and the entire frame is used to
 346  * calculate the crc.
 347  */
 348 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 349                              bool enable, bool continuous)
 350 {
 351         int i;
 352         struct pipe_ctx *pipe;
 353         struct crc_params param;
 354         struct timing_generator *tg;
 355
 356         for (i = 0; i < MAX_PIPES; i++) {
 357                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 358                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 359                         break;
 360         }
 361         /* Stream not found */
 362         if (i == MAX_PIPES)
 363                 return false;
 364
 365         /* Always capture the full frame */
 366         param.windowa_x_start = 0;
 367         param.windowa_y_start = 0;
 368         param.windowa_x_end = pipe->stream->timing.h_addressable;
 369         param.windowa_y_end = pipe->stream->timing.v_addressable;
 370         param.windowb_x_start = 0;
 371         param.windowb_y_start = 0;
 372         param.windowb_x_end = pipe->stream->timing.h_addressable;
 373         param.windowb_y_end = pipe->stream->timing.v_addressable;
 374
 375         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 376         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 377
 378         /* Default to the union of both windows */
 379         param.selection = UNION_WINDOW_A_B;
 380         param.continuous_mode = continuous;
 381         param.enable = enable;
 382
 383         tg = pipe->stream_res.tg;
 384
 385         /* Only call if supported */
 386         if (tg->funcs->configure_crc)
 387                 return tg->funcs->configure_crc(tg, &param);
 388         DC_LOG_WARNING("CRC capture not supported.");
 389         return false;
 390 }
 391
 392 /**
 393  * dc_stream_get_crc() - Get CRC values for the given stream.
 394  * @dc: DC object
 395  * @stream: The DC stream state of the stream to get CRCs from.
 396  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 397  *
 398  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 399  * Return false if stream is not found, or if CRCs are not enabled.
 400  */
 401 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 402                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 403 {
 404         int i;
 405         struct pipe_ctx *pipe;
 406         struct timing_generator *tg;
 407
 408         for (i = 0; i < MAX_PIPES; i++) {
 409                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 410                 if (pipe->stream == stream)
 411                         break;
 412         }
 413         /* Stream not found */
 414         if (i == MAX_PIPES)
 415                 return false;
 416
 417         tg = pipe->stream_res.tg;
 418
 419         if (tg->funcs->get_crc)
 420                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 421         DC_LOG_WARNING("CRC capture not supported.");
 422         return false;
 423 }
 424
 425 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 426                 enum dc_dynamic_expansion option)
 427 {
 428         /* OPP FMT dyn expansion updates*/
 429         int i = 0;
 430         struct pipe_ctx *pipe_ctx;
 431
 432         for (i = 0; i < MAX_PIPES; i++) {
 433                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 434                                 == stream) {
 435                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 436                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 437                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 438                                         pipe_ctx->stream_res.opp,
 439                                         COLOR_SPACE_YCBCR601,
 440                                         stream->timing.display_color_depth,
 441                                         stream->signal);
 442                 }
 443         }
 444 }
 445
 446 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 447                 enum dc_dither_option option)
 448 {
 449         struct bit_depth_reduction_params params;
 450         struct dc_link *link = stream->link;
 451         struct pipe_ctx *pipes = NULL;
 452         int i;
 453
 454         for (i = 0; i < MAX_PIPES; i++) {
 455                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 456                                 stream) {
 457                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 458                         break;
 459                 }
 460         }
 461
 462         if (!pipes)
 463                 return;
 464         if (option > DITHER_OPTION_MAX)
 465                 return;
 466
 467         stream->dither_option = option;
 468
 469         memset(&params, 0, sizeof(params));
 470         resource_build_bit_depth_reduction_params(stream, &params);
 471         stream->bit_depth_params = params;
 472
 473         if (pipes->plane_res.xfm &&
 474             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 475                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 476                         pipes->plane_res.xfm,
 477                         pipes->plane_res.scl_data.lb_params.depth,
 478                         &stream->bit_depth_params);
 479         }
 480
 481         pipes->stream_res.opp->funcs->
 482                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 483 }
 484
 485 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 486 {
 487         int i = 0;
 488         bool ret = false;
 489         struct pipe_ctx *pipes;
 490
 491         for (i = 0; i < MAX_PIPES; i++) {
 492                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 493                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 494                         dc->hwss.program_gamut_remap(pipes);
 495                         ret = true;
 496                 }
 497         }
 498
 499         return ret;
 500 }
 501
 502 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 503 {
 504         int i = 0;
 505         bool ret = false;
 506         struct pipe_ctx *pipes;
 507
 508         for (i = 0; i < MAX_PIPES; i++) {
 509                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 510                                 == stream) {
 511
 512                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 513                         dc->hwss.program_output_csc(dc,
 514                                         pipes,
 515                                         stream->output_color_space,
 516                                         stream->csc_color_matrix.matrix,
 517                                         pipes->stream_res.opp->inst);
 518                         ret = true;
 519                 }
 520         }
 521
 522         return ret;
 523 }
 524
 525 void dc_stream_set_static_screen_params(struct dc *dc,
 526                 struct dc_stream_state **streams,
 527                 int num_streams,
 528                 const struct dc_static_screen_params *params)
 529 {
 530         int i = 0;
 531         int j = 0;
 532         struct pipe_ctx *pipes_affected[MAX_PIPES];
 533         int num_pipes_affected = 0;
 534
 535         for (i = 0; i < num_streams; i++) {
 536                 struct dc_stream_state *stream = streams[i];
 537
 538                 for (j = 0; j < MAX_PIPES; j++) {
 539                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 540                                         == stream) {
 541                                 pipes_affected[num_pipes_affected++] =
 542                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 543                         }
 544                 }
 545         }
 546
 547         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 548 }
 549
 550 static void dc_destruct(struct dc *dc)
 551 {
 552         if (dc->current_state) {
 553                 dc_release_state(dc->current_state);
 554                 dc->current_state = NULL;
 555         }
 556
 557         destroy_links(dc);
 558
 559         if (dc->clk_mgr) {
 560                 dc_destroy_clk_mgr(dc->clk_mgr);
 561                 dc->clk_mgr = NULL;
 562         }
 563
 564         dc_destroy_resource_pool(dc);
 565
 566         if (dc->ctx->gpio_service)
 567                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 568
 569         if (dc->ctx->created_bios)
 570                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 571
 572         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 573
 574         kfree(dc->ctx);
 575         dc->ctx = NULL;
 576
 577         kfree(dc->bw_vbios);
 578         dc->bw_vbios = NULL;
 579
 580         kfree(dc->bw_dceip);
 581         dc->bw_dceip = NULL;
 582
 583 #ifdef CONFIG_DRM_AMD_DC_DCN
 584         kfree(dc->dcn_soc);
 585         dc->dcn_soc = NULL;
 586
 587         kfree(dc->dcn_ip);
 588         dc->dcn_ip = NULL;
 589
 590 #endif
 591         kfree(dc->vm_helper);
 592         dc->vm_helper = NULL;
 593
 594 }
 595
 596 static bool dc_construct_ctx(struct dc *dc,
 597                 const struct dc_init_data *init_params)
 598 {
 599         struct dc_context *dc_ctx;
 600         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 601
 602         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 603         if (!dc_ctx)
 604                 return false;
 605
 606         dc_ctx->cgs_device = init_params->cgs_device;
 607         dc_ctx->driver_context = init_params->driver;
 608         dc_ctx->dc = dc;
 609         dc_ctx->asic_id = init_params->asic_id;
 610         dc_ctx->dc_sink_id_count = 0;
 611         dc_ctx->dc_stream_id_count = 0;
 612         dc_ctx->dce_environment = init_params->dce_environment;
 613
 614         /* Create logger */
 615
 616         dc_version = resource_parse_asic_id(init_params->asic_id);
 617         dc_ctx->dce_version = dc_version;
 618
 619         dc_ctx->perf_trace = dc_perf_trace_create();
 620         if (!dc_ctx->perf_trace) {
 621                 ASSERT_CRITICAL(false);
 622                 return false;
 623         }
 624
 625         dc->ctx = dc_ctx;
 626
 627         return true;
 628 }
 629
 630 static bool dc_construct(struct dc *dc,
 631                 const struct dc_init_data *init_params)
 632 {
 633         struct dc_context *dc_ctx;
 634         struct bw_calcs_dceip *dc_dceip;
 635         struct bw_calcs_vbios *dc_vbios;
 636 #ifdef CONFIG_DRM_AMD_DC_DCN
 637         struct dcn_soc_bounding_box *dcn_soc;
 638         struct dcn_ip_params *dcn_ip;
 639 #endif
 640
 641         dc->config = init_params->flags;
 642
 643         // Allocate memory for the vm_helper
 644         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 645         if (!dc->vm_helper) {
 646                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 647                 goto fail;
 648         }
 649
 650         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 651
 652         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 653         if (!dc_dceip) {
 654                 dm_error("%s: failed to create dceip\n", __func__);
 655                 goto fail;
 656         }
 657
 658         dc->bw_dceip = dc_dceip;
 659
 660         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 661         if (!dc_vbios) {
 662                 dm_error("%s: failed to create vbios\n", __func__);
 663                 goto fail;
 664         }
 665
 666         dc->bw_vbios = dc_vbios;
 667 #ifdef CONFIG_DRM_AMD_DC_DCN
 668         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 669         if (!dcn_soc) {
 670                 dm_error("%s: failed to create dcn_soc\n", __func__);
 671                 goto fail;
 672         }
 673
 674         dc->dcn_soc = dcn_soc;
 675
 676         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 677         if (!dcn_ip) {
 678                 dm_error("%s: failed to create dcn_ip\n", __func__);
 679                 goto fail;
 680         }
 681
 682         dc->dcn_ip = dcn_ip;
 683         dc->soc_bounding_box = init_params->soc_bounding_box;
 684 #endif
 685
 686         if (!dc_construct_ctx(dc, init_params)) {
 687                 dm_error("%s: failed to create ctx\n", __func__);
 688                 goto fail;
 689         }
 690
 691         dc_ctx = dc->ctx;
 692
 693         /* Resource should construct all asic specific resources.
 694          * This should be the only place where we need to parse the asic id
 695          */
 696         if (init_params->vbios_override)
 697                 dc_ctx->dc_bios = init_params->vbios_override;
 698         else {
 699                 /* Create BIOS parser */
 700                 struct bp_init_data bp_init_data;
 701
 702                 bp_init_data.ctx = dc_ctx;
 703                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 704
 705                 dc_ctx->dc_bios = dal_bios_parser_create(
 706                                 &bp_init_data, dc_ctx->dce_version);
 707
 708                 if (!dc_ctx->dc_bios) {
 709                         ASSERT_CRITICAL(false);
 710                         goto fail;
 711                 }
 712
 713                 dc_ctx->created_bios = true;
 714         }
 715
 716         dc->vendor_signature = init_params->vendor_signature;
 717
 718         /* Create GPIO service */
 719         dc_ctx->gpio_service = dal_gpio_service_create(
 720                         dc_ctx->dce_version,
 721                         dc_ctx->dce_environment,
 722                         dc_ctx);
 723
 724         if (!dc_ctx->gpio_service) {
 725                 ASSERT_CRITICAL(false);
 726                 goto fail;
 727         }
 728
 729         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 730         if (!dc->res_pool)
 731                 goto fail;
 732
 733         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 734         if (!dc->clk_mgr)
 735                 goto fail;
 736 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
 737         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 738 #endif
 739
 740         dc->debug.force_ignore_link_settings = init_params->force_ignore_link_settings;
 741
 742         if (dc->res_pool->funcs->update_bw_bounding_box)
 743                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 744
 745         /* Creation of current_state must occur after dc->dml
 746          * is initialized in dc_create_resource_pool because
 747          * on creation it copies the contents of dc->dml
 748          */
 749
 750         dc->current_state = dc_create_state(dc);
 751
 752         if (!dc->current_state) {
 753                 dm_error("%s: failed to create validate ctx\n", __func__);
 754                 goto fail;
 755         }
 756
 757         dc_resource_state_construct(dc, dc->current_state);
 758
 759         if (!create_links(dc, init_params->num_virtual_links))
 760                 goto fail;
 761
 762         return true;
 763
 764 fail:
 765         return false;
 766 }
 767
 768 static void disable_all_writeback_pipes_for_stream(
 769                 const struct dc *dc,
 770                 struct dc_stream_state *stream,
 771                 struct dc_state *context)
 772 {
 773         int i;
 774
 775         for (i = 0; i < stream->num_wb_info; i++)
 776                 stream->writeback_info[i].wb_enabled = false;
 777 }
 778
 779 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 780 {
 781         int i = 0;
 782
 783         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 784         if (dc->hwss.interdependent_update_lock)
 785                 dc->hwss.interdependent_update_lock(dc, context, lock);
 786         else {
 787                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 788                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 789                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 790
 791                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 792                         if (stream == pipe_ctx->stream) {
 793                                 if (!pipe_ctx->top_pipe &&
 794                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 795                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 796                         }
 797                 }
 798         }
 799 }
 800
 801 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 802 {
 803         int i, j;
 804         struct dc_state *dangling_context = dc_create_state(dc);
 805         struct dc_state *current_ctx;
 806
 807         if (dangling_context == NULL)
 808                 return;
 809
 810         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 811
 812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 813                 struct dc_stream_state *old_stream =
 814                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 815                 bool should_disable = true;
 816
 817                 for (j = 0; j < context->stream_count; j++) {
 818                         if (old_stream == context->streams[j]) {
 819                                 should_disable = false;
 820                                 break;
 821                         }
 822                 }
 823                 if (should_disable && old_stream) {
 824                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 825                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 826
 827                         if (dc->hwss.apply_ctx_for_surface) {
 828                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 829                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 830                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 831                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 832                         }
 833                         if (dc->hwss.program_front_end_for_ctx) {
 834                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 835                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 836                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 837                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 838                         }
 839                 }
 840         }
 841
 842         current_ctx = dc->current_state;
 843         dc->current_state = dangling_context;
 844         dc_release_state(current_ctx);
 845 }
 846
 847 static void disable_vbios_mode_if_required(
 848                 struct dc *dc,
 849                 struct dc_state *context)
 850 {
 851         unsigned int i, j;
 852
 853         /* check if timing_changed, disable stream*/
 854         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 855                 struct dc_stream_state *stream = NULL;
 856                 struct dc_link *link = NULL;
 857                 struct pipe_ctx *pipe = NULL;
 858
 859                 pipe = &context->res_ctx.pipe_ctx[i];
 860                 stream = pipe->stream;
 861                 if (stream == NULL)
 862                         continue;
 863
 864                 // only looking for first odm pipe
 865                 if (pipe->prev_odm_pipe)
 866                         continue;
 867
 868                 if (stream->link->local_sink &&
 869                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 870                         link = stream->link;
 871                 }
 872
 873                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 874                         unsigned int enc_inst, tg_inst = 0;
 875                         unsigned int pix_clk_100hz;
 876
 877                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 878                         if (enc_inst != ENGINE_ID_UNKNOWN) {
 879                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 880                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
 881                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
 882                                                         dc->res_pool->stream_enc[j]);
 883                                                 break;
 884                                         }
 885                                 }
 886
 887                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
 888                                         dc->res_pool->dp_clock_source,
 889                                         tg_inst, &pix_clk_100hz);
 890
 891                                 if (link->link_status.link_active) {
 892                                         uint32_t requested_pix_clk_100hz =
 893                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
 894
 895                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
 896                                                 core_link_disable_stream(pipe);
 897                                                 pipe->stream->dpms_off = false;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903 }
 904
 905 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 906 {
 907         int i;
 908         PERF_TRACE();
 909         for (i = 0; i < MAX_PIPES; i++) {
 910                 int count = 0;
 911                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 912
 913                 if (!pipe->plane_state)
 914                         continue;
 915
 916                 /* Timeout 100 ms */
 917                 while (count < 100000) {
 918                         /* Must set to false to start with, due to OR in update function */
 919                         pipe->plane_state->status.is_flip_pending = false;
 920                         dc->hwss.update_pending_status(pipe);
 921                         if (!pipe->plane_state->status.is_flip_pending)
 922                                 break;
 923                         udelay(1);
 924                         count++;
 925                 }
 926                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 927         }
 928         PERF_TRACE();
 929 }
 930
 931 /*******************************************************************************
 932  * Public functions
 933  ******************************************************************************/
 934
 935 struct dc *dc_create(const struct dc_init_data *init_params)
 936 {
 937         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 938         unsigned int full_pipe_count;
 939
 940         if (NULL == dc)
 941                 goto alloc_fail;
 942
 943         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 944                 if (false == dc_construct_ctx(dc, init_params)) {
 945                         dc_destruct(dc);
 946                         goto construct_fail;
 947                 }
 948         } else {
 949                 if (false == dc_construct(dc, init_params)) {
 950                         dc_destruct(dc);
 951                         goto construct_fail;
 952                 }
 953
 954                 full_pipe_count = dc->res_pool->pipe_count;
 955                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 956                         full_pipe_count--;
 957                 dc->caps.max_streams = min(
 958                                 full_pipe_count,
 959                                 dc->res_pool->stream_enc_count);
 960
 961                 dc->optimize_seamless_boot_streams = 0;
 962                 dc->caps.max_links = dc->link_count;
 963                 dc->caps.max_audios = dc->res_pool->audio_count;
 964                 dc->caps.linear_pitch_alignment = 64;
 965
 966                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 967
 968                 if (dc->res_pool->dmcu != NULL)
 969                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 970         }
 971
 972         /* Populate versioning information */
 973         dc->versions.dc_ver = DC_VER;
 974
 975         dc->build_id = DC_BUILD_ID;
 976
 977         DC_LOG_DC("Display Core initialized\n");
 978
 979
 980
 981         return dc;
 982
 983 construct_fail:
 984         kfree(dc);
 985
 986 alloc_fail:
 987         return NULL;
 988 }
 989
 990 void dc_hardware_init(struct dc *dc)
 991 {
 992         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
 993                 dc->hwss.init_hw(dc);
 994 }
 995
 996 void dc_init_callbacks(struct dc *dc,
 997                 const struct dc_callback_init *init_params)
 998 {
 999 #ifdef CONFIG_DRM_AMD_DC_HDCP
1000         dc->ctx->cp_psp = init_params->cp_psp;
1001 #endif
1002 }
1003
1004 void dc_deinit_callbacks(struct dc *dc)
1005 {
1006 #ifdef CONFIG_DRM_AMD_DC_HDCP
1007         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1008 #endif
1009 }
1010
1011 void dc_destroy(struct dc **dc)
1012 {
1013         dc_destruct(*dc);
1014         kfree(*dc);
1015         *dc = NULL;
1016 }
1017
1018 static void enable_timing_multisync(
1019                 struct dc *dc,
1020                 struct dc_state *ctx)
1021 {
1022         int i = 0, multisync_count = 0;
1023         int pipe_count = dc->res_pool->pipe_count;
1024         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1025
1026         for (i = 0; i < pipe_count; i++) {
1027                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1028                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1029                         continue;
1030                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1031                         continue;
1032                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1033                 multisync_count++;
1034         }
1035
1036         if (multisync_count > 0) {
1037                 dc->hwss.enable_per_frame_crtc_position_reset(
1038                         dc, multisync_count, multisync_pipes);
1039         }
1040 }
1041
1042 static void program_timing_sync(
1043                 struct dc *dc,
1044                 struct dc_state *ctx)
1045 {
1046         int i, j, k;
1047         int group_index = 0;
1048         int num_group = 0;
1049         int pipe_count = dc->res_pool->pipe_count;
1050         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1051
1052         for (i = 0; i < pipe_count; i++) {
1053                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1054                         continue;
1055
1056                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1057         }
1058
1059         for (i = 0; i < pipe_count; i++) {
1060                 int group_size = 1;
1061                 struct pipe_ctx *pipe_set[MAX_PIPES];
1062
1063                 if (!unsynced_pipes[i])
1064                         continue;
1065
1066                 pipe_set[0] = unsynced_pipes[i];
1067                 unsynced_pipes[i] = NULL;
1068
1069                 /* Add tg to the set, search rest of the tg's for ones with
1070                  * same timing, add all tgs with same timing to the group
1071                  */
1072                 for (j = i + 1; j < pipe_count; j++) {
1073                         if (!unsynced_pipes[j])
1074                                 continue;
1075
1076                         if (resource_are_streams_timing_synchronizable(
1077                                         unsynced_pipes[j]->stream,
1078                                         pipe_set[0]->stream)) {
1079                                 pipe_set[group_size] = unsynced_pipes[j];
1080                                 unsynced_pipes[j] = NULL;
1081                                 group_size++;
1082                         }
1083                 }
1084
1085                 /* set first unblanked pipe as master */
1086                 for (j = 0; j < group_size; j++) {
1087                         bool is_blanked;
1088
1089                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1090                                 is_blanked =
1091                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1092                         else
1093                                 is_blanked =
1094                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1095                         if (!is_blanked) {
1096                                 if (j == 0)
1097                                         break;
1098
1099                                 swap(pipe_set[0], pipe_set[j]);
1100                                 break;
1101                         }
1102                 }
1103
1104
1105                 for (k = 0; k < group_size; k++) {
1106                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1107
1108                         status->timing_sync_info.group_id = num_group;
1109                         status->timing_sync_info.group_size = group_size;
1110                         if (k == 0)
1111                                 status->timing_sync_info.master = true;
1112                         else
1113                                 status->timing_sync_info.master = false;
1114
1115                 }
1116                 /* remove any other unblanked pipes as they have already been synced */
1117                 for (j = j + 1; j < group_size; j++) {
1118                         bool is_blanked;
1119
1120                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1121                                 is_blanked =
1122                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1123                         else
1124                                 is_blanked =
1125                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1126                         if (!is_blanked) {
1127                                 group_size--;
1128                                 pipe_set[j] = pipe_set[group_size];
1129                                 j--;
1130                         }
1131                 }
1132
1133                 if (group_size > 1) {
1134                         dc->hwss.enable_timing_synchronization(
1135                                 dc, group_index, group_size, pipe_set);
1136                         group_index++;
1137                 }
1138                 num_group++;
1139         }
1140 }
1141
1142 static bool context_changed(
1143                 struct dc *dc,
1144                 struct dc_state *context)
1145 {
1146         uint8_t i;
1147
1148         if (context->stream_count != dc->current_state->stream_count)
1149                 return true;
1150
1151         for (i = 0; i < dc->current_state->stream_count; i++) {
1152                 if (dc->current_state->streams[i] != context->streams[i])
1153                         return true;
1154         }
1155
1156         return false;
1157 }
1158
1159 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1160                                 const struct dc_sink *sink,
1161                                 struct dc_crtc_timing *crtc_timing)
1162 {
1163         struct timing_generator *tg;
1164         struct stream_encoder *se = NULL;
1165
1166         struct dc_crtc_timing hw_crtc_timing = {0};
1167
1168         struct dc_link *link = sink->link;
1169         unsigned int i, enc_inst, tg_inst = 0;
1170
1171         // Seamless port only support single DP and EDP so far
1172         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1173                 sink->sink_signal != SIGNAL_TYPE_EDP)
1174                 return false;
1175
1176         /* Check for enabled DIG to identify enabled display */
1177         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1178                 return false;
1179
1180         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1181
1182         if (enc_inst == ENGINE_ID_UNKNOWN)
1183                 return false;
1184
1185         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1186                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1187
1188                         se = dc->res_pool->stream_enc[i];
1189
1190                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1191                                 dc->res_pool->stream_enc[i]);
1192                         break;
1193                 }
1194         }
1195
1196         // tg_inst not found
1197         if (i == dc->res_pool->stream_enc_count)
1198                 return false;
1199
1200         if (tg_inst >= dc->res_pool->timing_generator_count)
1201                 return false;
1202
1203         tg = dc->res_pool->timing_generators[tg_inst];
1204
1205         if (!tg->funcs->get_hw_timing)
1206                 return false;
1207
1208         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1209                 return false;
1210
1211         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1212                 return false;
1213
1214         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1215                 return false;
1216
1217         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1218                 return false;
1219
1220         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1221                 return false;
1222
1223         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1224                 return false;
1225
1226         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1227                 return false;
1228
1229         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1230                 return false;
1231
1232         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1233                 return false;
1234
1235         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1236                 return false;
1237
1238         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1239                 return false;
1240
1241         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1242                 return false;
1243
1244         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1245                 return false;
1246
1247         if (dc_is_dp_signal(link->connector_signal)) {
1248                 unsigned int pix_clk_100hz;
1249
1250                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1251                         dc->res_pool->dp_clock_source,
1252                         tg_inst, &pix_clk_100hz);
1253
1254                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1255                         return false;
1256
1257                 if (!se->funcs->dp_get_pixel_format)
1258                         return false;
1259
1260                 if (!se->funcs->dp_get_pixel_format(
1261                         se,
1262                         &hw_crtc_timing.pixel_encoding,
1263                         &hw_crtc_timing.display_color_depth))
1264                         return false;
1265
1266                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1267                         return false;
1268
1269                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1270                         return false;
1271         }
1272
1273         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1274                 return false;
1275         }
1276
1277         return true;
1278 }
1279
1280 void dc_enable_stereo(
1281         struct dc *dc,
1282         struct dc_state *context,
1283         struct dc_stream_state *streams[],
1284         uint8_t stream_count)
1285 {
1286         int i, j;
1287         struct pipe_ctx *pipe;
1288
1289         for (i = 0; i < MAX_PIPES; i++) {
1290                 if (context != NULL)
1291                         pipe = &context->res_ctx.pipe_ctx[i];
1292                 else
1293                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1294                 for (j = 0 ; pipe && j < stream_count; j++)  {
1295                         if (streams[j] && streams[j] == pipe->stream &&
1296                                 dc->hwss.setup_stereo)
1297                                 dc->hwss.setup_stereo(pipe, dc);
1298                 }
1299         }
1300 }
1301
1302 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1303 {
1304         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1305                 enable_timing_multisync(dc, context);
1306                 program_timing_sync(dc, context);
1307         }
1308 }
1309
1310 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1311 {
1312         int i;
1313         unsigned int stream_mask = 0;
1314
1315         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1316                 if (context->res_ctx.pipe_ctx[i].stream)
1317                         stream_mask |= 1 << i;
1318         }
1319
1320         return stream_mask;
1321 }
1322
1323 /*
1324  * Applies given context to HW and copy it into current context.
1325  * It's up to the user to release the src context afterwards.
1326  */
1327 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1328 {
1329         struct dc_bios *dcb = dc->ctx->dc_bios;
1330         enum dc_status result = DC_ERROR_UNEXPECTED;
1331         struct pipe_ctx *pipe;
1332         int i, k, l;
1333         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1334
1335 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1336         dc_allow_idle_optimizations(dc, false);
1337 #endif
1338
1339         for (i = 0; i < context->stream_count; i++)
1340                 dc_streams[i] =  context->streams[i];
1341
1342         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1343                 disable_vbios_mode_if_required(dc, context);
1344                 dc->hwss.enable_accelerated_mode(dc, context);
1345         }
1346
1347         for (i = 0; i < context->stream_count; i++)
1348                 if (context->streams[i]->apply_seamless_boot_optimization)
1349                         dc->optimize_seamless_boot_streams++;
1350
1351         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1352                 context->stream_count == 0)
1353                 dc->hwss.prepare_bandwidth(dc, context);
1354
1355         disable_dangling_plane(dc, context);
1356         /* re-program planes for existing stream, in case we need to
1357          * free up plane resource for later use
1358          */
1359         if (dc->hwss.apply_ctx_for_surface) {
1360                 for (i = 0; i < context->stream_count; i++) {
1361                         if (context->streams[i]->mode_changed)
1362                                 continue;
1363                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1364                         dc->hwss.apply_ctx_for_surface(
1365                                 dc, context->streams[i],
1366                                 context->stream_status[i].plane_count,
1367                                 context); /* use new pipe config in new context */
1368                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1369                         dc->hwss.post_unlock_program_front_end(dc, context);
1370                 }
1371         }
1372
1373         /* Program hardware */
1374         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1375                 pipe = &context->res_ctx.pipe_ctx[i];
1376                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1377         }
1378
1379         result = dc->hwss.apply_ctx_to_hw(dc, context);
1380
1381         if (result != DC_OK)
1382                 return result;
1383
1384         dc_trigger_sync(dc, context);
1385
1386         /* Program all planes within new context*/
1387         if (dc->hwss.program_front_end_for_ctx) {
1388                 dc->hwss.interdependent_update_lock(dc, context, true);
1389                 dc->hwss.program_front_end_for_ctx(dc, context);
1390                 dc->hwss.interdependent_update_lock(dc, context, false);
1391                 dc->hwss.post_unlock_program_front_end(dc, context);
1392         }
1393         for (i = 0; i < context->stream_count; i++) {
1394                 const struct dc_link *link = context->streams[i]->link;
1395
1396                 if (!context->streams[i]->mode_changed)
1397                         continue;
1398
1399                 if (dc->hwss.apply_ctx_for_surface) {
1400                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1401                         dc->hwss.apply_ctx_for_surface(
1402                                         dc, context->streams[i],
1403                                         context->stream_status[i].plane_count,
1404                                         context);
1405                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1406                         dc->hwss.post_unlock_program_front_end(dc, context);
1407                 }
1408
1409                 /*
1410                  * enable stereo
1411                  * TODO rework dc_enable_stereo call to work with validation sets?
1412                  */
1413                 for (k = 0; k < MAX_PIPES; k++) {
1414                         pipe = &context->res_ctx.pipe_ctx[k];
1415
1416                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1417                                 if (context->streams[l] &&
1418                                         context->streams[l] == pipe->stream &&
1419                                         dc->hwss.setup_stereo)
1420                                         dc->hwss.setup_stereo(pipe, dc);
1421                         }
1422                 }
1423
1424                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1425                                 context->streams[i]->timing.h_addressable,
1426                                 context->streams[i]->timing.v_addressable,
1427                                 context->streams[i]->timing.h_total,
1428                                 context->streams[i]->timing.v_total,
1429                                 context->streams[i]->timing.pix_clk_100hz / 10);
1430         }
1431
1432         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1433
1434         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1435                 context->stream_count == 0) {
1436                 /* Must wait for no flips to be pending before doing optimize bw */
1437                 wait_for_no_pipes_pending(dc, context);
1438                 /* pplib is notified if disp_num changed */
1439                 dc->hwss.optimize_bandwidth(dc, context);
1440         }
1441
1442         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1443                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1444         else
1445                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1446
1447         context->stream_mask = get_stream_mask(dc, context);
1448
1449         if (context->stream_mask != dc->current_state->stream_mask)
1450                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1451
1452         for (i = 0; i < context->stream_count; i++)
1453                 context->streams[i]->mode_changed = false;
1454
1455         dc_release_state(dc->current_state);
1456
1457         dc->current_state = context;
1458
1459         dc_retain_state(dc->current_state);
1460
1461         return result;
1462 }
1463
1464 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1465 {
1466         enum dc_status result = DC_ERROR_UNEXPECTED;
1467         int i;
1468
1469         if (false == context_changed(dc, context))
1470                 return DC_OK;
1471
1472         DC_LOG_DC("%s: %d streams\n",
1473                                 __func__, context->stream_count);
1474
1475         for (i = 0; i < context->stream_count; i++) {
1476                 struct dc_stream_state *stream = context->streams[i];
1477
1478                 dc_stream_log(dc, stream);
1479         }
1480
1481         result = dc_commit_state_no_check(dc, context);
1482
1483         return (result == DC_OK);
1484 }
1485
1486 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1487 bool dc_acquire_release_mpc_3dlut(
1488                 struct dc *dc, bool acquire,
1489                 struct dc_stream_state *stream,
1490                 struct dc_3dlut **lut,
1491                 struct dc_transfer_func **shaper)
1492 {
1493         int pipe_idx;
1494         bool ret = false;
1495         bool found_pipe_idx = false;
1496         const struct resource_pool *pool = dc->res_pool;
1497         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1498         int mpcc_id = 0;
1499
1500         if (pool && res_ctx) {
1501                 if (acquire) {
1502                         /*find pipe idx for the given stream*/
1503                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1504                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1505                                         found_pipe_idx = true;
1506                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1507                                         break;
1508                                 }
1509                         }
1510                 } else
1511                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1512
1513                 if (found_pipe_idx) {
1514                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1515                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1516                         else if (acquire == false && pool->funcs->release_post_bldn_3dlut)
1517                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1518                 }
1519         }
1520         return ret;
1521 }
1522 #endif
1523 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1524 {
1525         int i;
1526         struct pipe_ctx *pipe;
1527
1528         for (i = 0; i < MAX_PIPES; i++) {
1529                 pipe = &context->res_ctx.pipe_ctx[i];
1530
1531                 if (!pipe->plane_state)
1532                         continue;
1533
1534                 /* Must set to false to start with, due to OR in update function */
1535                 pipe->plane_state->status.is_flip_pending = false;
1536                 dc->hwss.update_pending_status(pipe);
1537                 if (pipe->plane_state->status.is_flip_pending)
1538                         return true;
1539         }
1540         return false;
1541 }
1542
1543 void dc_post_update_surfaces_to_stream(struct dc *dc)
1544 {
1545         int i;
1546         struct dc_state *context = dc->current_state;
1547
1548         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1549                 return;
1550
1551         post_surface_trace(dc);
1552
1553         if (is_flip_pending_in_pipes(dc, context))
1554                 return;
1555
1556         for (i = 0; i < dc->res_pool->pipe_count; i++)
1557                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1558                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1559                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1560                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1561                 }
1562
1563         dc->hwss.optimize_bandwidth(dc, context);
1564
1565         dc->optimized_required = false;
1566         dc->wm_optimized_required = false;
1567 }
1568
1569 static void init_state(struct dc *dc, struct dc_state *context)
1570 {
1571         /* Each context must have their own instance of VBA and in order to
1572          * initialize and obtain IP and SOC the base DML instance from DC is
1573          * initially copied into every context
1574          */
1575 #ifdef CONFIG_DRM_AMD_DC_DCN
1576         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1577 #endif
1578 }
1579
1580 struct dc_state *dc_create_state(struct dc *dc)
1581 {
1582         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1583                                             GFP_KERNEL);
1584
1585         if (!context)
1586                 return NULL;
1587
1588         init_state(dc, context);
1589
1590         kref_init(&context->refcount);
1591
1592         return context;
1593 }
1594
1595 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1596 {
1597         int i, j;
1598         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1599
1600         if (!new_ctx)
1601                 return NULL;
1602         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1603
1604         for (i = 0; i < MAX_PIPES; i++) {
1605                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1606
1607                         if (cur_pipe->top_pipe)
1608                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1609
1610                         if (cur_pipe->bottom_pipe)
1611                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1612
1613                         if (cur_pipe->prev_odm_pipe)
1614                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1615
1616                         if (cur_pipe->next_odm_pipe)
1617                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1618
1619         }
1620
1621         for (i = 0; i < new_ctx->stream_count; i++) {
1622                         dc_stream_retain(new_ctx->streams[i]);
1623                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1624                                 dc_plane_state_retain(
1625                                         new_ctx->stream_status[i].plane_states[j]);
1626         }
1627
1628         kref_init(&new_ctx->refcount);
1629
1630         return new_ctx;
1631 }
1632
1633 void dc_retain_state(struct dc_state *context)
1634 {
1635         kref_get(&context->refcount);
1636 }
1637
1638 static void dc_state_free(struct kref *kref)
1639 {
1640         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1641         dc_resource_state_destruct(context);
1642         kvfree(context);
1643 }
1644
1645 void dc_release_state(struct dc_state *context)
1646 {
1647         kref_put(&context->refcount, dc_state_free);
1648 }
1649
1650 bool dc_set_generic_gpio_for_stereo(bool enable,
1651                 struct gpio_service *gpio_service)
1652 {
1653         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1654         struct gpio_pin_info pin_info;
1655         struct gpio *generic;
1656         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1657                            GFP_KERNEL);
1658
1659         if (!config)
1660                 return false;
1661         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1662
1663         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1664                 kfree(config);
1665                 return false;
1666         } else {
1667                 generic = dal_gpio_service_create_generic_mux(
1668                         gpio_service,
1669                         pin_info.offset,
1670                         pin_info.mask);
1671         }
1672
1673         if (!generic) {
1674                 kfree(config);
1675                 return false;
1676         }
1677
1678         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1679
1680         config->enable_output_from_mux = enable;
1681         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1682
1683         if (gpio_result == GPIO_RESULT_OK)
1684                 gpio_result = dal_mux_setup_config(generic, config);
1685
1686         if (gpio_result == GPIO_RESULT_OK) {
1687                 dal_gpio_close(generic);
1688                 dal_gpio_destroy_generic_mux(&generic);
1689                 kfree(config);
1690                 return true;
1691         } else {
1692                 dal_gpio_close(generic);
1693                 dal_gpio_destroy_generic_mux(&generic);
1694                 kfree(config);
1695                 return false;
1696         }
1697 }
1698
1699 static bool is_surface_in_context(
1700                 const struct dc_state *context,
1701                 const struct dc_plane_state *plane_state)
1702 {
1703         int j;
1704
1705         for (j = 0; j < MAX_PIPES; j++) {
1706                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1707
1708                 if (plane_state == pipe_ctx->plane_state) {
1709                         return true;
1710                 }
1711         }
1712
1713         return false;
1714 }
1715
1716 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1717 {
1718         union surface_update_flags *update_flags = &u->surface->update_flags;
1719         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1720
1721         if (!u->plane_info)
1722                 return UPDATE_TYPE_FAST;
1723
1724         if (u->plane_info->color_space != u->surface->color_space) {
1725                 update_flags->bits.color_space_change = 1;
1726                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1727         }
1728
1729         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1730                 update_flags->bits.horizontal_mirror_change = 1;
1731                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1732         }
1733
1734         if (u->plane_info->rotation != u->surface->rotation) {
1735                 update_flags->bits.rotation_change = 1;
1736                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1737         }
1738
1739         if (u->plane_info->format != u->surface->format) {
1740                 update_flags->bits.pixel_format_change = 1;
1741                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1742         }
1743
1744         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1745                 update_flags->bits.stereo_format_change = 1;
1746                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1747         }
1748
1749         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1750                 update_flags->bits.per_pixel_alpha_change = 1;
1751                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1752         }
1753
1754         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1755                 update_flags->bits.global_alpha_change = 1;
1756                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1757         }
1758
1759         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1760                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1761                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1762                 update_flags->bits.dcc_change = 1;
1763                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1764         }
1765
1766         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1767                         resource_pixel_format_to_bpp(u->surface->format)) {
1768                 /* different bytes per element will require full bandwidth
1769                  * and DML calculation
1770                  */
1771                 update_flags->bits.bpp_change = 1;
1772                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1773         }
1774
1775         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1776                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1777                 update_flags->bits.plane_size_change = 1;
1778                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1779         }
1780
1781
1782         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1783                         sizeof(union dc_tiling_info)) != 0) {
1784                 update_flags->bits.swizzle_change = 1;
1785                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1786
1787                 /* todo: below are HW dependent, we should add a hook to
1788                  * DCE/N resource and validated there.
1789                  */
1790                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1791                         /* swizzled mode requires RQ to be setup properly,
1792                          * thus need to run DML to calculate RQ settings
1793                          */
1794                         update_flags->bits.bandwidth_change = 1;
1795                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1796                 }
1797         }
1798
1799         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1800         return update_type;
1801 }
1802
1803 static enum surface_update_type get_scaling_info_update_type(
1804                 const struct dc_surface_update *u)
1805 {
1806         union surface_update_flags *update_flags = &u->surface->update_flags;
1807
1808         if (!u->scaling_info)
1809                 return UPDATE_TYPE_FAST;
1810
1811         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1812                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1813                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1814                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1815                         || u->scaling_info->scaling_quality.integer_scaling !=
1816                                 u->surface->scaling_quality.integer_scaling
1817                         ) {
1818                 update_flags->bits.scaling_change = 1;
1819
1820                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1821                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1822                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1823                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1824                         /* Making dst rect smaller requires a bandwidth change */
1825                         update_flags->bits.bandwidth_change = 1;
1826         }
1827
1828         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1829                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1830
1831                 update_flags->bits.scaling_change = 1;
1832                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1833                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1834                         /* Making src rect bigger requires a bandwidth change */
1835                         update_flags->bits.clock_change = 1;
1836         }
1837
1838         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1839                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1840                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1841                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1842                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1843                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1844                 update_flags->bits.position_change = 1;
1845
1846         if (update_flags->bits.clock_change
1847                         || update_flags->bits.bandwidth_change
1848                         || update_flags->bits.scaling_change)
1849                 return UPDATE_TYPE_FULL;
1850
1851         if (update_flags->bits.position_change)
1852                 return UPDATE_TYPE_MED;
1853
1854         return UPDATE_TYPE_FAST;
1855 }
1856
1857 static enum surface_update_type det_surface_update(const struct dc *dc,
1858                 const struct dc_surface_update *u)
1859 {
1860         const struct dc_state *context = dc->current_state;
1861         enum surface_update_type type;
1862         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1863         union surface_update_flags *update_flags = &u->surface->update_flags;
1864
1865         if (u->flip_addr)
1866                 update_flags->bits.addr_update = 1;
1867
1868         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1869                 update_flags->raw = 0xFFFFFFFF;
1870                 return UPDATE_TYPE_FULL;
1871         }
1872
1873         update_flags->raw = 0; // Reset all flags
1874
1875         type = get_plane_info_update_type(u);
1876         elevate_update_type(&overall_type, type);
1877
1878         type = get_scaling_info_update_type(u);
1879         elevate_update_type(&overall_type, type);
1880
1881         if (u->flip_addr)
1882                 update_flags->bits.addr_update = 1;
1883
1884         if (u->in_transfer_func)
1885                 update_flags->bits.in_transfer_func_change = 1;
1886
1887         if (u->input_csc_color_matrix)
1888                 update_flags->bits.input_csc_change = 1;
1889
1890         if (u->coeff_reduction_factor)
1891                 update_flags->bits.coeff_reduction_change = 1;
1892
1893         if (u->gamut_remap_matrix)
1894                 update_flags->bits.gamut_remap_change = 1;
1895
1896         if (u->gamma) {
1897                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1898
1899                 if (u->plane_info)
1900                         format = u->plane_info->format;
1901                 else if (u->surface)
1902                         format = u->surface->format;
1903
1904                 if (dce_use_lut(format))
1905                         update_flags->bits.gamma_change = 1;
1906         }
1907
1908         if (u->hdr_mult.value)
1909                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1910                         update_flags->bits.hdr_mult = 1;
1911                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1912                 }
1913
1914         if (update_flags->bits.in_transfer_func_change) {
1915                 type = UPDATE_TYPE_MED;
1916                 elevate_update_type(&overall_type, type);
1917         }
1918
1919         if (update_flags->bits.input_csc_change
1920                         || update_flags->bits.coeff_reduction_change
1921                         || update_flags->bits.gamma_change
1922                         || update_flags->bits.gamut_remap_change) {
1923                 type = UPDATE_TYPE_FULL;
1924                 elevate_update_type(&overall_type, type);
1925         }
1926
1927         return overall_type;
1928 }
1929
1930 static enum surface_update_type check_update_surfaces_for_stream(
1931                 struct dc *dc,
1932                 struct dc_surface_update *updates,
1933                 int surface_count,
1934                 struct dc_stream_update *stream_update,
1935                 const struct dc_stream_status *stream_status)
1936 {
1937         int i;
1938         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1939
1940 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1941         if (dc->idle_optimizations_allowed)
1942                 overall_type = UPDATE_TYPE_FULL;
1943
1944 #endif
1945         if (stream_status == NULL || stream_status->plane_count != surface_count)
1946                 overall_type = UPDATE_TYPE_FULL;
1947
1948         /* some stream updates require passive update */
1949         if (stream_update) {
1950                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1951
1952                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1953                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1954                         stream_update->integer_scaling_update)
1955                         su_flags->bits.scaling = 1;
1956
1957                 if (stream_update->out_transfer_func)
1958                         su_flags->bits.out_tf = 1;
1959
1960                 if (stream_update->abm_level)
1961                         su_flags->bits.abm_level = 1;
1962
1963                 if (stream_update->dpms_off)
1964                         su_flags->bits.dpms_off = 1;
1965
1966                 if (stream_update->gamut_remap)
1967                         su_flags->bits.gamut_remap = 1;
1968
1969                 if (stream_update->wb_update)
1970                         su_flags->bits.wb_update = 1;
1971
1972                 if (stream_update->dsc_config)
1973                         su_flags->bits.dsc_changed = 1;
1974
1975                 if (su_flags->raw != 0)
1976                         overall_type = UPDATE_TYPE_FULL;
1977
1978                 if (stream_update->output_csc_transform || stream_update->output_color_space)
1979                         su_flags->bits.out_csc = 1;
1980         }
1981
1982         for (i = 0 ; i < surface_count; i++) {
1983                 enum surface_update_type type =
1984                                 det_surface_update(dc, &updates[i]);
1985
1986                 elevate_update_type(&overall_type, type);
1987         }
1988
1989         return overall_type;
1990 }
1991
1992 /**
1993  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1994  *
1995  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1996  */
1997 enum surface_update_type dc_check_update_surfaces_for_stream(
1998                 struct dc *dc,
1999                 struct dc_surface_update *updates,
2000                 int surface_count,
2001                 struct dc_stream_update *stream_update,
2002                 const struct dc_stream_status *stream_status)
2003 {
2004         int i;
2005         enum surface_update_type type;
2006
2007         if (stream_update)
2008                 stream_update->stream->update_flags.raw = 0;
2009         for (i = 0; i < surface_count; i++)
2010                 updates[i].surface->update_flags.raw = 0;
2011
2012         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2013         if (type == UPDATE_TYPE_FULL) {
2014                 if (stream_update) {
2015                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2016                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2017                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2018                 }
2019                 for (i = 0; i < surface_count; i++)
2020                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2021         }
2022
2023         if (type == UPDATE_TYPE_FAST) {
2024                 // If there's an available clock comparator, we use that.
2025                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2026                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2027                                 dc->optimized_required = true;
2028                 // Else we fallback to mem compare.
2029                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2030                         dc->optimized_required = true;
2031                 }
2032
2033                 dc->optimized_required |= dc->wm_optimized_required;
2034         }
2035
2036         return type;
2037 }
2038
2039 static struct dc_stream_status *stream_get_status(
2040         struct dc_state *ctx,
2041         struct dc_stream_state *stream)
2042 {
2043         uint8_t i;
2044
2045         for (i = 0; i < ctx->stream_count; i++) {
2046                 if (stream == ctx->streams[i]) {
2047                         return &ctx->stream_status[i];
2048                 }
2049         }
2050
2051         return NULL;
2052 }
2053
2054 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2055
2056 static void copy_surface_update_to_plane(
2057                 struct dc_plane_state *surface,
2058                 struct dc_surface_update *srf_update)
2059 {
2060         if (srf_update->flip_addr) {
2061                 surface->address = srf_update->flip_addr->address;
2062                 surface->flip_immediate =
2063                         srf_update->flip_addr->flip_immediate;
2064                 surface->time.time_elapsed_in_us[surface->time.index] =
2065                         srf_update->flip_addr->flip_timestamp_in_us -
2066                                 surface->time.prev_update_time_in_us;
2067                 surface->time.prev_update_time_in_us =
2068                         srf_update->flip_addr->flip_timestamp_in_us;
2069                 surface->time.index++;
2070                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2071                         surface->time.index = 0;
2072
2073                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2074         }
2075
2076         if (srf_update->scaling_info) {
2077                 surface->scaling_quality =
2078                                 srf_update->scaling_info->scaling_quality;
2079                 surface->dst_rect =
2080                                 srf_update->scaling_info->dst_rect;
2081                 surface->src_rect =
2082                                 srf_update->scaling_info->src_rect;
2083                 surface->clip_rect =
2084                                 srf_update->scaling_info->clip_rect;
2085         }
2086
2087         if (srf_update->plane_info) {
2088                 surface->color_space =
2089                                 srf_update->plane_info->color_space;
2090                 surface->format =
2091                                 srf_update->plane_info->format;
2092                 surface->plane_size =
2093                                 srf_update->plane_info->plane_size;
2094                 surface->rotation =
2095                                 srf_update->plane_info->rotation;
2096                 surface->horizontal_mirror =
2097                                 srf_update->plane_info->horizontal_mirror;
2098                 surface->stereo_format =
2099                                 srf_update->plane_info->stereo_format;
2100                 surface->tiling_info =
2101                                 srf_update->plane_info->tiling_info;
2102                 surface->visible =
2103                                 srf_update->plane_info->visible;
2104                 surface->per_pixel_alpha =
2105                                 srf_update->plane_info->per_pixel_alpha;
2106                 surface->global_alpha =
2107                                 srf_update->plane_info->global_alpha;
2108                 surface->global_alpha_value =
2109                                 srf_update->plane_info->global_alpha_value;
2110                 surface->dcc =
2111                                 srf_update->plane_info->dcc;
2112                 surface->layer_index =
2113                                 srf_update->plane_info->layer_index;
2114         }
2115
2116         if (srf_update->gamma &&
2117                         (surface->gamma_correction !=
2118                                         srf_update->gamma)) {
2119                 memcpy(&surface->gamma_correction->entries,
2120                         &srf_update->gamma->entries,
2121                         sizeof(struct dc_gamma_entries));
2122                 surface->gamma_correction->is_identity =
2123                         srf_update->gamma->is_identity;
2124                 surface->gamma_correction->num_entries =
2125                         srf_update->gamma->num_entries;
2126                 surface->gamma_correction->type =
2127                         srf_update->gamma->type;
2128         }
2129
2130         if (srf_update->in_transfer_func &&
2131                         (surface->in_transfer_func !=
2132                                 srf_update->in_transfer_func)) {
2133                 surface->in_transfer_func->sdr_ref_white_level =
2134                         srf_update->in_transfer_func->sdr_ref_white_level;
2135                 surface->in_transfer_func->tf =
2136                         srf_update->in_transfer_func->tf;
2137                 surface->in_transfer_func->type =
2138                         srf_update->in_transfer_func->type;
2139                 memcpy(&surface->in_transfer_func->tf_pts,
2140                         &srf_update->in_transfer_func->tf_pts,
2141                         sizeof(struct dc_transfer_func_distributed_points));
2142         }
2143
2144         if (srf_update->func_shaper &&
2145                         (surface->in_shaper_func !=
2146                         srf_update->func_shaper))
2147                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2148                 sizeof(*surface->in_shaper_func));
2149
2150         if (srf_update->lut3d_func &&
2151                         (surface->lut3d_func !=
2152                         srf_update->lut3d_func))
2153                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2154                 sizeof(*surface->lut3d_func));
2155
2156         if (srf_update->hdr_mult.value)
2157                 surface->hdr_mult =
2158                                 srf_update->hdr_mult;
2159
2160         if (srf_update->blend_tf &&
2161                         (surface->blend_tf !=
2162                         srf_update->blend_tf))
2163                 memcpy(surface->blend_tf, srf_update->blend_tf,
2164                 sizeof(*surface->blend_tf));
2165
2166         if (srf_update->input_csc_color_matrix)
2167                 surface->input_csc_color_matrix =
2168                         *srf_update->input_csc_color_matrix;
2169
2170         if (srf_update->coeff_reduction_factor)
2171                 surface->coeff_reduction_factor =
2172                         *srf_update->coeff_reduction_factor;
2173
2174         if (srf_update->gamut_remap_matrix)
2175                 surface->gamut_remap_matrix =
2176                         *srf_update->gamut_remap_matrix;
2177 }
2178
2179 static void copy_stream_update_to_stream(struct dc *dc,
2180                                          struct dc_state *context,
2181                                          struct dc_stream_state *stream,
2182                                          struct dc_stream_update *update)
2183 {
2184         struct dc_context *dc_ctx = dc->ctx;
2185
2186         if (update == NULL || stream == NULL)
2187                 return;
2188
2189         if (update->src.height && update->src.width)
2190                 stream->src = update->src;
2191
2192         if (update->dst.height && update->dst.width)
2193                 stream->dst = update->dst;
2194
2195         if (update->out_transfer_func &&
2196             stream->out_transfer_func != update->out_transfer_func) {
2197                 stream->out_transfer_func->sdr_ref_white_level =
2198                         update->out_transfer_func->sdr_ref_white_level;
2199                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2200                 stream->out_transfer_func->type =
2201                         update->out_transfer_func->type;
2202                 memcpy(&stream->out_transfer_func->tf_pts,
2203                        &update->out_transfer_func->tf_pts,
2204                        sizeof(struct dc_transfer_func_distributed_points));
2205         }
2206
2207         if (update->hdr_static_metadata)
2208                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2209
2210         if (update->abm_level)
2211                 stream->abm_level = *update->abm_level;
2212
2213         if (update->periodic_interrupt0)
2214                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2215
2216         if (update->periodic_interrupt1)
2217                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2218
2219         if (update->gamut_remap)
2220                 stream->gamut_remap_matrix = *update->gamut_remap;
2221
2222         /* Note: this being updated after mode set is currently not a use case
2223          * however if it arises OCSC would need to be reprogrammed at the
2224          * minimum
2225          */
2226         if (update->output_color_space)
2227                 stream->output_color_space = *update->output_color_space;
2228
2229         if (update->output_csc_transform)
2230                 stream->csc_color_matrix = *update->output_csc_transform;
2231
2232         if (update->vrr_infopacket)
2233                 stream->vrr_infopacket = *update->vrr_infopacket;
2234
2235         if (update->dpms_off)
2236                 stream->dpms_off = *update->dpms_off;
2237
2238         if (update->vsc_infopacket)
2239                 stream->vsc_infopacket = *update->vsc_infopacket;
2240
2241         if (update->vsp_infopacket)
2242                 stream->vsp_infopacket = *update->vsp_infopacket;
2243
2244         if (update->dither_option)
2245                 stream->dither_option = *update->dither_option;
2246         /* update current stream with writeback info */
2247         if (update->wb_update) {
2248                 int i;
2249
2250                 stream->num_wb_info = update->wb_update->num_wb_info;
2251                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2252                 for (i = 0; i < stream->num_wb_info; i++)
2253                         stream->writeback_info[i] =
2254                                 update->wb_update->writeback_info[i];
2255         }
2256         if (update->dsc_config) {
2257                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2258                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2259                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2260                                        update->dsc_config->num_slices_v != 0);
2261
2262                 /* Use temporarry context for validating new DSC config */
2263                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2264
2265                 if (dsc_validate_context) {
2266                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2267
2268                         stream->timing.dsc_cfg = *update->dsc_config;
2269                         stream->timing.flags.DSC = enable_dsc;
2270                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2271                                 stream->timing.dsc_cfg = old_dsc_cfg;
2272                                 stream->timing.flags.DSC = old_dsc_enabled;
2273                                 update->dsc_config = NULL;
2274                         }
2275
2276                         dc_release_state(dsc_validate_context);
2277                 } else {
2278                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2279                         update->dsc_config = NULL;
2280                 }
2281         }
2282 }
2283
2284 static void commit_planes_do_stream_update(struct dc *dc,
2285                 struct dc_stream_state *stream,
2286                 struct dc_stream_update *stream_update,
2287                 enum surface_update_type update_type,
2288                 struct dc_state *context)
2289 {
2290         int j;
2291         bool should_program_abm;
2292
2293         // Stream updates
2294         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2295                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2296
2297                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2298
2299                         if (stream_update->periodic_interrupt0 &&
2300                                         dc->hwss.setup_periodic_interrupt)
2301                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2302
2303                         if (stream_update->periodic_interrupt1 &&
2304                                         dc->hwss.setup_periodic_interrupt)
2305                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2306
2307                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2308                                         stream_update->vrr_infopacket ||
2309                                         stream_update->vsc_infopacket ||
2310                                         stream_update->vsp_infopacket) {
2311                                 resource_build_info_frame(pipe_ctx);
2312                                 dc->hwss.update_info_frame(pipe_ctx);
2313                         }
2314
2315                         if (stream_update->hdr_static_metadata &&
2316                                         stream->use_dynamic_meta &&
2317                                         dc->hwss.set_dmdata_attributes &&
2318                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2319                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2320
2321                         if (stream_update->gamut_remap)
2322                                 dc_stream_set_gamut_remap(dc, stream);
2323
2324                         if (stream_update->output_csc_transform)
2325                                 dc_stream_program_csc_matrix(dc, stream);
2326
2327                         if (stream_update->dither_option) {
2328                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2329                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2330                                                                         &pipe_ctx->stream->bit_depth_params);
2331                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2332                                                 &stream->bit_depth_params,
2333                                                 &stream->clamping);
2334                                 while (odm_pipe) {
2335                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2336                                                         &stream->bit_depth_params,
2337                                                         &stream->clamping);
2338                                         odm_pipe = odm_pipe->next_odm_pipe;
2339                                 }
2340                         }
2341
2342                         /* Full fe update*/
2343                         if (update_type == UPDATE_TYPE_FAST)
2344                                 continue;
2345
2346                         if (stream_update->dsc_config)
2347                                 dp_update_dsc_config(pipe_ctx);
2348
2349                         if (stream_update->dpms_off) {
2350                                 if (*stream_update->dpms_off) {
2351                                         core_link_disable_stream(pipe_ctx);
2352                                         /* for dpms, keep acquired resources*/
2353                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2354                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2355
2356                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2357                                 } else {
2358                                         if (dc->optimize_seamless_boot_streams == 0)
2359                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2360
2361                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2362                                 }
2363                         }
2364
2365                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2366                                 should_program_abm = true;
2367
2368                                 // if otg funcs defined check if blanked before programming
2369                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2370                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2371                                                 should_program_abm = false;
2372
2373                                 if (should_program_abm) {
2374                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2375                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2376                                         } else {
2377                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2378                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2379                                         }
2380                                 }
2381                         }
2382                 }
2383         }
2384 }
2385
2386 static void commit_planes_for_stream(struct dc *dc,
2387                 struct dc_surface_update *srf_updates,
2388                 int surface_count,
2389                 struct dc_stream_state *stream,
2390                 struct dc_stream_update *stream_update,
2391                 enum surface_update_type update_type,
2392                 struct dc_state *context)
2393 {
2394         int i, j;
2395         struct pipe_ctx *top_pipe_to_program = NULL;
2396
2397         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2398                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2399                  * first flip. After first flip, optimization is required to lower
2400                  * bandwidth. Important to note that it is expected UEFI will
2401                  * only light up a single display on POST, therefore we only expect
2402                  * one stream with seamless boot flag set.
2403                  */
2404                 if (stream->apply_seamless_boot_optimization) {
2405                         stream->apply_seamless_boot_optimization = false;
2406                         dc->optimize_seamless_boot_streams--;
2407
2408                         if (dc->optimize_seamless_boot_streams == 0)
2409                                 dc->optimized_required = true;
2410                 }
2411         }
2412
2413         if (update_type == UPDATE_TYPE_FULL) {
2414 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2415                 dc_allow_idle_optimizations(dc, false);
2416
2417 #endif
2418                 if (dc->optimize_seamless_boot_streams == 0)
2419                         dc->hwss.prepare_bandwidth(dc, context);
2420
2421                 context_clock_trace(dc, context);
2422         }
2423
2424         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2425                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2426
2427                 if (!pipe_ctx->top_pipe &&
2428                         !pipe_ctx->prev_odm_pipe &&
2429                         pipe_ctx->stream &&
2430                         pipe_ctx->stream == stream) {
2431                         top_pipe_to_program = pipe_ctx;
2432                 }
2433         }
2434
2435         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2436                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2437                         if (should_use_dmub_lock(stream->link)) {
2438                                 union dmub_hw_lock_flags hw_locks = { 0 };
2439                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2440
2441                                 hw_locks.bits.lock_dig = 1;
2442                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2443
2444                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2445                                                         true,
2446                                                         &hw_locks,
2447                                                         &inst_flags);
2448                         } else
2449                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2450                                                 top_pipe_to_program->stream_res.tg);
2451                 }
2452
2453         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2454                 dc->hwss.interdependent_update_lock(dc, context, true);
2455         else
2456                 /* Lock the top pipe while updating plane addrs, since freesync requires
2457                  *  plane addr update event triggers to be synchronized.
2458                  *  top_pipe_to_program is expected to never be NULL
2459                  */
2460                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2461
2462         // Stream updates
2463         if (stream_update)
2464                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2465
2466         if (surface_count == 0) {
2467                 /*
2468                  * In case of turning off screen, no need to program front end a second time.
2469                  * just return after program blank.
2470                  */
2471                 if (dc->hwss.apply_ctx_for_surface)
2472                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2473                 if (dc->hwss.program_front_end_for_ctx)
2474                         dc->hwss.program_front_end_for_ctx(dc, context);
2475
2476                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2477                         dc->hwss.interdependent_update_lock(dc, context, false);
2478                 else
2479                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2480
2481                 dc->hwss.post_unlock_program_front_end(dc, context);
2482                 return;
2483         }
2484
2485         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2486                 for (i = 0; i < surface_count; i++) {
2487                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2488                         /*set logical flag for lock/unlock use*/
2489                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2490                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2491                                 if (!pipe_ctx->plane_state)
2492                                         continue;
2493                                 if (pipe_ctx->plane_state != plane_state)
2494                                         continue;
2495                                 plane_state->triplebuffer_flips = false;
2496                                 if (update_type == UPDATE_TYPE_FAST &&
2497                                         dc->hwss.program_triplebuffer != NULL &&
2498                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2499                                                 /*triple buffer for VUpdate  only*/
2500                                                 plane_state->triplebuffer_flips = true;
2501                                 }
2502                         }
2503                 }
2504         }
2505
2506         // Update Type FULL, Surface updates
2507         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2508                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2509
2510                 if (!pipe_ctx->top_pipe &&
2511                         !pipe_ctx->prev_odm_pipe &&
2512                         pipe_ctx->stream &&
2513                         pipe_ctx->stream == stream) {
2514                         struct dc_stream_status *stream_status = NULL;
2515
2516                         if (!pipe_ctx->plane_state)
2517                                 continue;
2518
2519                         /* Full fe update*/
2520                         if (update_type == UPDATE_TYPE_FAST)
2521                                 continue;
2522
2523                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2524
2525                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2526                                 /*turn off triple buffer for full update*/
2527                                 dc->hwss.program_triplebuffer(
2528                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2529                         }
2530                         stream_status =
2531                                 stream_get_status(context, pipe_ctx->stream);
2532
2533                         if (dc->hwss.apply_ctx_for_surface)
2534                                 dc->hwss.apply_ctx_for_surface(
2535                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2536                 }
2537         }
2538         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2539                 dc->hwss.program_front_end_for_ctx(dc, context);
2540 #ifdef CONFIG_DRM_AMD_DC_DCN
2541                 if (dc->debug.validate_dml_output) {
2542                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2543                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2544                                 if (cur_pipe.stream == NULL)
2545                                         continue;
2546
2547                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2548                                                 cur_pipe.plane_res.hubp, dc->ctx,
2549                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2550                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2551                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2552                         }
2553                 }
2554 #endif
2555         }
2556
2557         // Update Type FAST, Surface updates
2558         if (update_type == UPDATE_TYPE_FAST) {
2559                 if (dc->hwss.set_flip_control_gsl)
2560                         for (i = 0; i < surface_count; i++) {
2561                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2562
2563                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2564                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2565
2566                                         if (pipe_ctx->stream != stream)
2567                                                 continue;
2568
2569                                         if (pipe_ctx->plane_state != plane_state)
2570                                                 continue;
2571
2572                                         // GSL has to be used for flip immediate
2573                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2574                                                         plane_state->flip_immediate);
2575                                 }
2576                         }
2577                 /* Perform requested Updates */
2578                 for (i = 0; i < surface_count; i++) {
2579                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2580
2581                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2582                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2583
2584                                 if (pipe_ctx->stream != stream)
2585                                         continue;
2586
2587                                 if (pipe_ctx->plane_state != plane_state)
2588                                         continue;
2589                                 /*program triple buffer after lock based on flip type*/
2590                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2591                                         /*only enable triplebuffer for  fast_update*/
2592                                         dc->hwss.program_triplebuffer(
2593                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2594                                 }
2595                                 if (srf_updates[i].flip_addr)
2596                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2597                         }
2598                 }
2599         }
2600
2601         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2602                 dc->hwss.interdependent_update_lock(dc, context, false);
2603         else
2604                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2605
2606         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2607                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2608                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2609                                         top_pipe_to_program->stream_res.tg,
2610                                         CRTC_STATE_VACTIVE);
2611                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2612                                         top_pipe_to_program->stream_res.tg,
2613                                         CRTC_STATE_VBLANK);
2614                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2615                                         top_pipe_to_program->stream_res.tg,
2616                                         CRTC_STATE_VACTIVE);
2617
2618                         if (stream && should_use_dmub_lock(stream->link)) {
2619                                 union dmub_hw_lock_flags hw_locks = { 0 };
2620                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2621
2622                                 hw_locks.bits.lock_dig = 1;
2623                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2624
2625                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2626                                                         false,
2627                                                         &hw_locks,
2628                                                         &inst_flags);
2629                         } else
2630                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2631                                         top_pipe_to_program->stream_res.tg);
2632                 }
2633
2634         if (update_type != UPDATE_TYPE_FAST)
2635                 dc->hwss.post_unlock_program_front_end(dc, context);
2636
2637         // Fire manual trigger only when bottom plane is flipped
2638         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2639                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2640
2641                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2642                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2643                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2644                         continue;
2645
2646                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2647                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2648         }
2649 }
2650
2651 void dc_commit_updates_for_stream(struct dc *dc,
2652                 struct dc_surface_update *srf_updates,
2653                 int surface_count,
2654                 struct dc_stream_state *stream,
2655                 struct dc_stream_update *stream_update,
2656                 struct dc_state *state)
2657 {
2658         const struct dc_stream_status *stream_status;
2659         enum surface_update_type update_type;
2660         struct dc_state *context;
2661         struct dc_context *dc_ctx = dc->ctx;
2662         int i, j;
2663
2664         stream_status = dc_stream_get_status(stream);
2665         context = dc->current_state;
2666
2667         update_type = dc_check_update_surfaces_for_stream(
2668                                 dc, srf_updates, surface_count, stream_update, stream_status);
2669
2670         if (update_type >= update_surface_trace_level)
2671                 update_surface_trace(dc, srf_updates, surface_count);
2672
2673
2674         if (update_type >= UPDATE_TYPE_FULL) {
2675
2676                 /* initialize scratch memory for building context */
2677                 context = dc_create_state(dc);
2678                 if (context == NULL) {
2679                         DC_ERROR("Failed to allocate new validate context!\n");
2680                         return;
2681                 }
2682
2683                 dc_resource_state_copy_construct(state, context);
2684
2685                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2686                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2687                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2688
2689                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2690                                 new_pipe->plane_state->force_full_update = true;
2691                 }
2692         }
2693
2694
2695         for (i = 0; i < surface_count; i++) {
2696                 struct dc_plane_state *surface = srf_updates[i].surface;
2697
2698                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2699
2700                 if (update_type >= UPDATE_TYPE_MED) {
2701                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2702                                 struct pipe_ctx *pipe_ctx =
2703                                         &context->res_ctx.pipe_ctx[j];
2704
2705                                 if (pipe_ctx->plane_state != surface)
2706                                         continue;
2707
2708                                 resource_build_scaling_params(pipe_ctx);
2709                         }
2710                 }
2711         }
2712
2713         copy_stream_update_to_stream(dc, context, stream, stream_update);
2714
2715         if (update_type >= UPDATE_TYPE_FULL) {
2716                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2717                         DC_ERROR("Mode validation failed for stream update!\n");
2718                         dc_release_state(context);
2719                         return;
2720                 }
2721         }
2722
2723         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2724
2725         commit_planes_for_stream(
2726                                 dc,
2727                                 srf_updates,
2728                                 surface_count,
2729                                 stream,
2730                                 stream_update,
2731                                 update_type,
2732                                 context);
2733         /*update current_State*/
2734         if (dc->current_state != context) {
2735
2736                 struct dc_state *old = dc->current_state;
2737
2738                 dc->current_state = context;
2739                 dc_release_state(old);
2740
2741                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2742                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2743
2744                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2745                                 pipe_ctx->plane_state->force_full_update = false;
2746                 }
2747         }
2748         /*let's use current_state to update watermark etc*/
2749         if (update_type >= UPDATE_TYPE_FULL) {
2750                 dc_post_update_surfaces_to_stream(dc);
2751
2752                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
2753                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2754                 else
2755                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2756         }
2757
2758         return;
2759
2760 }
2761
2762 uint8_t dc_get_current_stream_count(struct dc *dc)
2763 {
2764         return dc->current_state->stream_count;
2765 }
2766
2767 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2768 {
2769         if (i < dc->current_state->stream_count)
2770                 return dc->current_state->streams[i];
2771         return NULL;
2772 }
2773
2774 enum dc_irq_source dc_interrupt_to_irq_source(
2775                 struct dc *dc,
2776                 uint32_t src_id,
2777                 uint32_t ext_id)
2778 {
2779         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2780 }
2781
2782 /**
2783  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2784  */
2785 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2786 {
2787
2788         if (dc == NULL)
2789                 return false;
2790
2791         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2792 }
2793
2794 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2795 {
2796         dal_irq_service_ack(dc->res_pool->irqs, src);
2797 }
2798
2799 void dc_power_down_on_boot(struct dc *dc)
2800 {
2801         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
2802                         dc->hwss.power_down_on_boot)
2803                 dc->hwss.power_down_on_boot(dc);
2804 }
2805
2806 void dc_set_power_state(
2807         struct dc *dc,
2808         enum dc_acpi_cm_power_state power_state)
2809 {
2810         struct kref refcount;
2811         struct display_mode_lib *dml;
2812
2813         switch (power_state) {
2814         case DC_ACPI_CM_POWER_STATE_D0:
2815                 dc_resource_state_construct(dc, dc->current_state);
2816
2817                 if (dc->ctx->dmub_srv)
2818                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2819
2820                 dc->hwss.init_hw(dc);
2821
2822                 if (dc->hwss.init_sys_ctx != NULL &&
2823                         dc->vm_pa_config.valid) {
2824                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2825                 }
2826
2827                 break;
2828         default:
2829                 ASSERT(dc->current_state->stream_count == 0);
2830                 /* Zero out the current context so that on resume we start with
2831                  * clean state, and dc hw programming optimizations will not
2832                  * cause any trouble.
2833                  */
2834                 dml = kzalloc(sizeof(struct display_mode_lib),
2835                                 GFP_KERNEL);
2836
2837                 ASSERT(dml);
2838                 if (!dml)
2839                         return;
2840
2841                 /* Preserve refcount */
2842                 refcount = dc->current_state->refcount;
2843                 /* Preserve display mode lib */
2844                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2845
2846                 dc_resource_state_destruct(dc->current_state);
2847                 memset(dc->current_state, 0,
2848                                 sizeof(*dc->current_state));
2849
2850                 dc->current_state->refcount = refcount;
2851                 dc->current_state->bw_ctx.dml = *dml;
2852
2853                 kfree(dml);
2854
2855                 break;
2856         }
2857 }
2858
2859 void dc_resume(struct dc *dc)
2860 {
2861         uint32_t i;
2862
2863         for (i = 0; i < dc->link_count; i++)
2864                 core_link_resume(dc->links[i]);
2865 }
2866
2867 bool dc_is_dmcu_initialized(struct dc *dc)
2868 {
2869         struct dmcu *dmcu = dc->res_pool->dmcu;
2870
2871         if (dmcu)
2872                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2873         return false;
2874 }
2875
2876 bool dc_submit_i2c(
2877                 struct dc *dc,
2878                 uint32_t link_index,
2879                 struct i2c_command *cmd)
2880 {
2881
2882         struct dc_link *link = dc->links[link_index];
2883         struct ddc_service *ddc = link->ddc;
2884         return dce_i2c_submit_command(
2885                 dc->res_pool,
2886                 ddc->ddc_pin,
2887                 cmd);
2888 }
2889
2890 bool dc_submit_i2c_oem(
2891                 struct dc *dc,
2892                 struct i2c_command *cmd)
2893 {
2894         struct ddc_service *ddc = dc->res_pool->oem_device;
2895         return dce_i2c_submit_command(
2896                 dc->res_pool,
2897                 ddc->ddc_pin,
2898                 cmd);
2899 }
2900
2901 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2902 {
2903         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2904                 BREAK_TO_DEBUGGER();
2905                 return false;
2906         }
2907
2908         dc_sink_retain(sink);
2909
2910         dc_link->remote_sinks[dc_link->sink_count] = sink;
2911         dc_link->sink_count++;
2912
2913         return true;
2914 }
2915
2916 /**
2917  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2918  *
2919  * EDID length is in bytes
2920  */
2921 struct dc_sink *dc_link_add_remote_sink(
2922                 struct dc_link *link,
2923                 const uint8_t *edid,
2924                 int len,
2925                 struct dc_sink_init_data *init_data)
2926 {
2927         struct dc_sink *dc_sink;
2928         enum dc_edid_status edid_status;
2929
2930         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2931                 dm_error("Max EDID buffer size breached!\n");
2932                 return NULL;
2933         }
2934
2935         if (!init_data) {
2936                 BREAK_TO_DEBUGGER();
2937                 return NULL;
2938         }
2939
2940         if (!init_data->link) {
2941                 BREAK_TO_DEBUGGER();
2942                 return NULL;
2943         }
2944
2945         dc_sink = dc_sink_create(init_data);
2946
2947         if (!dc_sink)
2948                 return NULL;
2949
2950         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2951         dc_sink->dc_edid.length = len;
2952
2953         if (!link_add_remote_sink_helper(
2954                         link,
2955                         dc_sink))
2956                 goto fail_add_sink;
2957
2958         edid_status = dm_helpers_parse_edid_caps(
2959                         link->ctx,
2960                         &dc_sink->dc_edid,
2961                         &dc_sink->edid_caps);
2962
2963         /*
2964          * Treat device as no EDID device if EDID
2965          * parsing fails
2966          */
2967         if (edid_status != EDID_OK) {
2968                 dc_sink->dc_edid.length = 0;
2969                 dm_error("Bad EDID, status%d!\n", edid_status);
2970         }
2971
2972         return dc_sink;
2973
2974 fail_add_sink:
2975         dc_sink_release(dc_sink);
2976         return NULL;
2977 }
2978
2979 /**
2980  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2981  *
2982  * Note that this just removes the struct dc_sink - it doesn't
2983  * program hardware or alter other members of dc_link
2984  */
2985 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2986 {
2987         int i;
2988
2989         if (!link->sink_count) {
2990                 BREAK_TO_DEBUGGER();
2991                 return;
2992         }
2993
2994         for (i = 0; i < link->sink_count; i++) {
2995                 if (link->remote_sinks[i] == sink) {
2996                         dc_sink_release(sink);
2997                         link->remote_sinks[i] = NULL;
2998
2999                         /* shrink array to remove empty place */
3000                         while (i < link->sink_count - 1) {
3001                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3002                                 i++;
3003                         }
3004                         link->remote_sinks[i] = NULL;
3005                         link->sink_count--;
3006                         return;
3007                 }
3008         }
3009 }
3010
3011 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3012 {
3013         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3014         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3015         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3016         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3017         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3018         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3019         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3020         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3021         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3022 }
3023 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3024 {
3025         if (dc->hwss.set_clock)
3026                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3027         return DC_ERROR_UNEXPECTED;
3028 }
3029 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3030 {
3031         if (dc->hwss.get_clock)
3032                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3033 }
3034
3035 /* enable/disable eDP PSR without specify stream for eDP */
3036 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3037 {
3038         int i;
3039
3040         for (i = 0; i < dc->current_state->stream_count ; i++) {
3041                 struct dc_link *link;
3042                 struct dc_stream_state *stream = dc->current_state->streams[i];
3043
3044                 link = stream->link;
3045                 if (!link)
3046                         continue;
3047
3048                 if (link->psr_settings.psr_feature_enabled) {
3049                         if (enable && !link->psr_settings.psr_allow_active)
3050                                 return dc_link_set_psr_allow_active(link, true, false);
3051                         else if (!enable && link->psr_settings.psr_allow_active)
3052                                 return dc_link_set_psr_allow_active(link, false, true);
3053                 }
3054         }
3055
3056         return true;
3057 }
3058
3059 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
3060
3061 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3062 {
3063         if (dc->debug.disable_idle_power_optimizations)
3064                 return;
3065
3066         if (allow == dc->idle_optimizations_allowed)
3067                 return;
3068
3069         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3070                 dc->idle_optimizations_allowed = allow;
3071 }
3072
3073 /*
3074  * blank all streams, and set min and max memory clock to
3075  * lowest and highest DPM level, respectively
3076  */
3077 void dc_unlock_memory_clock_frequency(struct dc *dc)
3078 {
3079         unsigned int i;
3080
3081         for (i = 0; i < MAX_PIPES; i++)
3082                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3083                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3084
3085         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3086         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3087 }
3088
3089 /*
3090  * set min memory clock to the min required for current mode,
3091  * max to maxDPM, and unblank streams
3092  */
3093 void dc_lock_memory_clock_frequency(struct dc *dc)
3094 {
3095         unsigned int i;
3096
3097         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3098         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3099         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3100
3101         for (i = 0; i < MAX_PIPES; i++)
3102                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3103                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3104 }
3105
3106 bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,
3107                                                  struct dc_plane_state *plane)
3108 {
3109         return false;
3110 }
3111
3112 /* cleanup on driver unload */
3113 void dc_hardware_release(struct dc *dc)
3114 {
3115         if (dc->hwss.hardware_release)
3116                 dc->hwss.hardware_release(dc);
3117 }
3118 #endif