drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32
  33 #include "resource.h"
  34
  35 #include "clock_source.h"
  36 #include "dc_bios_types.h"
  37
  38 #include "dce_calcs.h"
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "timing_generator.h"
  43 #include "virtual/virtual_link_encoder.h"
  44
  45 #include "link_hwss.h"
  46 #include "link_encoder.h"
  47
  48 #include "dc_link_ddc.h"
  49 #include "dm_helpers.h"
  50 #include "mem_input.h"
  51
  52 /*******************************************************************************
  53  * Private functions
  54  ******************************************************************************/
  55 static void destroy_links(struct core_dc *dc)
  56 {
  57         uint32_t i;
  58
  59         for (i = 0; i < dc->link_count; i++) {
  60                 if (NULL != dc->links[i])
  61                         link_destroy(&dc->links[i]);
  62         }
  63 }
  64
  65 static bool create_links(
  66                 struct core_dc *dc,
  67                 uint32_t num_virtual_links)
  68 {
  69         int i;
  70         int connectors_num;
  71         struct dc_bios *bios = dc->ctx->dc_bios;
  72
  73         dc->link_count = 0;
  74
  75         connectors_num = bios->funcs->get_connectors_number(bios);
  76
  77         if (connectors_num > ENUM_ID_COUNT) {
  78                 dm_error(
  79                         "DC: Number of connectors %d exceeds maximum of %d!\n",
  80                         connectors_num,
  81                         ENUM_ID_COUNT);
  82                 return false;
  83         }
  84
  85         if (connectors_num == 0 && num_virtual_links == 0) {
  86                 dm_error("DC: Number of connectors is zero!\n");
  87         }
  88
  89         dm_output_to_console(
  90                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
  91                 __func__,
  92                 connectors_num,
  93                 num_virtual_links);
  94
  95         for (i = 0; i < connectors_num; i++) {
  96                 struct link_init_data link_init_params = {0};
  97                 struct core_link *link;
  98
  99                 link_init_params.ctx = dc->ctx;
 100                 /* next BIOS object table connector */
 101                 link_init_params.connector_index = i;
 102                 link_init_params.link_index = dc->link_count;
 103                 link_init_params.dc = dc;
 104                 link = link_create(&link_init_params);
 105
 106                 if (link) {
 107                         dc->links[dc->link_count] = link;
 108                         link->dc = dc;
 109                         ++dc->link_count;
 110                 }
 111         }
 112
 113         for (i = 0; i < num_virtual_links; i++) {
 114                 struct core_link *link = dm_alloc(sizeof(*link));
 115                 struct encoder_init_data enc_init = {0};
 116
 117                 if (link == NULL) {
 118                         BREAK_TO_DEBUGGER();
 119                         goto failed_alloc;
 120                 }
 121
 122                 link->ctx = dc->ctx;
 123                 link->dc = dc;
 124                 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
 125                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 126                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 127                 link->link_id.enum_id = ENUM_ID_1;
 128                 link->link_enc = dm_alloc(sizeof(*link->link_enc));
 129
 130                 enc_init.ctx = dc->ctx;
 131                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 132                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 133                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 134                 enc_init.connector = link->link_id;
 135                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 136                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 137                 enc_init.encoder.enum_id = ENUM_ID_1;
 138                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 139
 140                 link->public.link_index = dc->link_count;
 141                 dc->links[dc->link_count] = link;
 142                 dc->link_count++;
 143         }
 144
 145         return true;
 146
 147 failed_alloc:
 148         return false;
 149 }
 150
 151 static bool stream_adjust_vmin_vmax(struct dc *dc,
 152                 const struct dc_stream **stream, int num_streams,
 153                 int vmin, int vmax)
 154 {
 155         /* TODO: Support multiple streams */
 156         struct core_dc *core_dc = DC_TO_CORE(dc);
 157         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
 158         int i = 0;
 159         bool ret = false;
 160
 161         for (i = 0; i < MAX_PIPES; i++) {
 162                 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
 163
 164                 if (pipe->stream == core_stream && pipe->stream_enc) {
 165                         core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
 166
 167                         /* build and update the info frame */
 168                         resource_build_info_frame(pipe);
 169                         core_dc->hwss.update_info_frame(pipe);
 170
 171                         ret = true;
 172                 }
 173         }
 174         return ret;
 175 }
 176
 177 static bool stream_get_crtc_position(struct dc *dc,
 178                 const struct dc_stream **stream, int num_streams,
 179                 unsigned int *v_pos, unsigned int *nom_v_pos)
 180 {
 181         /* TODO: Support multiple streams */
 182         struct core_dc *core_dc = DC_TO_CORE(dc);
 183         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
 184         int i = 0;
 185         bool ret = false;
 186         struct crtc_position position;
 187
 188         for (i = 0; i < MAX_PIPES; i++) {
 189                 struct pipe_ctx *pipe =
 190                                 &core_dc->current_context->res_ctx.pipe_ctx[i];
 191
 192                 if (pipe->stream == core_stream && pipe->stream_enc) {
 193                         core_dc->hwss.get_position(&pipe, 1, &position);
 194
 195                         *v_pos = position.vertical_count;
 196                         *nom_v_pos = position.nominal_vcount;
 197                         ret = true;
 198                 }
 199         }
 200         return ret;
 201 }
 202
 203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
 204 {
 205         struct core_dc *core_dc = DC_TO_CORE(dc);
 206         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
 207         int i = 0;
 208         bool ret = false;
 209         struct pipe_ctx *pipes;
 210
 211         for (i = 0; i < MAX_PIPES; i++) {
 212                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
 213                                 == core_stream) {
 214
 215                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
 216                         core_dc->hwss.program_gamut_remap(pipes);
 217                         ret = true;
 218                 }
 219         }
 220
 221         return ret;
 222 }
 223
 224 static void set_static_screen_events(struct dc *dc,
 225                 const struct dc_stream **stream,
 226                 int num_streams,
 227                 const struct dc_static_screen_events *events)
 228 {
 229         struct core_dc *core_dc = DC_TO_CORE(dc);
 230         int i = 0;
 231         int j = 0;
 232         struct pipe_ctx *pipes_affected[MAX_PIPES];
 233         int num_pipes_affected = 0;
 234
 235         for (i = 0; i < num_streams; i++) {
 236                 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
 237
 238                 for (j = 0; j < MAX_PIPES; j++) {
 239                         if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
 240                                         == core_stream) {
 241                                 pipes_affected[num_pipes_affected++] =
 242                                                 &core_dc->current_context->res_ctx.pipe_ctx[j];
 243                         }
 244                 }
 245         }
 246
 247         core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 248 }
 249
 250 static void set_drive_settings(struct dc *dc,
 251                 struct link_training_settings *lt_settings,
 252                 const struct dc_link *link)
 253 {
 254         struct core_dc *core_dc = DC_TO_CORE(dc);
 255         int i;
 256
 257         for (i = 0; i < core_dc->link_count; i++) {
 258                 if (&core_dc->links[i]->public == link)
 259                         break;
 260         }
 261
 262         if (i >= core_dc->link_count)
 263                 ASSERT_CRITICAL(false);
 264
 265         dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
 266 }
 267
 268 static void perform_link_training(struct dc *dc,
 269                 struct dc_link_settings *link_setting,
 270                 bool skip_video_pattern)
 271 {
 272         struct core_dc *core_dc = DC_TO_CORE(dc);
 273         int i;
 274
 275         for (i = 0; i < core_dc->link_count; i++)
 276                 dc_link_dp_perform_link_training(
 277                         &core_dc->links[i]->public,
 278                         link_setting,
 279                         skip_video_pattern);
 280 }
 281
 282 static void set_preferred_link_settings(struct dc *dc,
 283                 struct dc_link_settings *link_setting,
 284                 const struct dc_link *link)
 285 {
 286         struct core_link *core_link = DC_LINK_TO_CORE(link);
 287
 288         core_link->public.verified_link_cap.lane_count =
 289                                 link_setting->lane_count;
 290         core_link->public.verified_link_cap.link_rate =
 291                                 link_setting->link_rate;
 292         dp_retrain_link_dp_test(core_link, link_setting, false);
 293 }
 294
 295 static void enable_hpd(const struct dc_link *link)
 296 {
 297         dc_link_dp_enable_hpd(link);
 298 }
 299
 300 static void disable_hpd(const struct dc_link *link)
 301 {
 302         dc_link_dp_disable_hpd(link);
 303 }
 304
 305
 306 static void set_test_pattern(
 307                 const struct dc_link *link,
 308                 enum dp_test_pattern test_pattern,
 309                 const struct link_training_settings *p_link_settings,
 310                 const unsigned char *p_custom_pattern,
 311                 unsigned int cust_pattern_size)
 312 {
 313         if (link != NULL)
 314                 dc_link_dp_set_test_pattern(
 315                         link,
 316                         test_pattern,
 317                         p_link_settings,
 318                         p_custom_pattern,
 319                         cust_pattern_size);
 320 }
 321
 322 void set_dither_option(const struct dc_stream *dc_stream,
 323                 enum dc_dither_option option)
 324 {
 325         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
 326         struct bit_depth_reduction_params params;
 327         struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
 328         struct pipe_ctx *pipes =
 329                         core_link->dc->current_context->res_ctx.pipe_ctx;
 330
 331         memset(&params, 0, sizeof(params));
 332         if (!stream)
 333                 return;
 334         if (option > DITHER_OPTION_MAX)
 335                 return;
 336         if (option == DITHER_OPTION_DEFAULT) {
 337                 switch (stream->public.timing.display_color_depth) {
 338                 case COLOR_DEPTH_666:
 339                         stream->public.dither_option = DITHER_OPTION_SPATIAL6;
 340                         break;
 341                 case COLOR_DEPTH_888:
 342                         stream->public.dither_option = DITHER_OPTION_SPATIAL8;
 343                         break;
 344                 case COLOR_DEPTH_101010:
 345                         stream->public.dither_option = DITHER_OPTION_SPATIAL10;
 346                         break;
 347                 default:
 348                         option = DITHER_OPTION_DISABLE;
 349                 }
 350         } else {
 351                 stream->public.dither_option = option;
 352         }
 353         resource_build_bit_depth_reduction_params(stream,
 354                                 &params);
 355         stream->bit_depth_params = params;
 356         pipes->opp->funcs->
 357                 opp_program_bit_depth_reduction(pipes->opp, &params);
 358 }
 359
 360 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
 361 {
 362         if (core_dc->hwss.set_drr != NULL) {
 363                 core_dc->public.stream_funcs.adjust_vmin_vmax =
 364                                 stream_adjust_vmin_vmax;
 365         }
 366
 367         core_dc->public.stream_funcs.set_static_screen_events =
 368                         set_static_screen_events;
 369
 370         core_dc->public.stream_funcs.get_crtc_position =
 371                         stream_get_crtc_position;
 372
 373         core_dc->public.stream_funcs.set_gamut_remap =
 374                         set_gamut_remap;
 375
 376         core_dc->public.stream_funcs.set_dither_option =
 377                         set_dither_option;
 378
 379         core_dc->public.link_funcs.set_drive_settings =
 380                         set_drive_settings;
 381
 382         core_dc->public.link_funcs.perform_link_training =
 383                         perform_link_training;
 384
 385         core_dc->public.link_funcs.set_preferred_link_settings =
 386                         set_preferred_link_settings;
 387
 388         core_dc->public.link_funcs.enable_hpd =
 389                         enable_hpd;
 390
 391         core_dc->public.link_funcs.disable_hpd =
 392                         disable_hpd;
 393
 394         core_dc->public.link_funcs.set_test_pattern =
 395                         set_test_pattern;
 396 }
 397
 398 static void destruct(struct core_dc *dc)
 399 {
 400         dc_resource_validate_ctx_destruct(dc->current_context);
 401
 402         destroy_links(dc);
 403
 404         dc_destroy_resource_pool(dc);
 405
 406         if (dc->ctx->gpio_service)
 407                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 408
 409         if (dc->ctx->i2caux)
 410                 dal_i2caux_destroy(&dc->ctx->i2caux);
 411
 412         if (dc->ctx->created_bios)
 413                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 414
 415         if (dc->ctx->logger)
 416                 dal_logger_destroy(&dc->ctx->logger);
 417
 418         dm_free(dc->current_context);
 419         dc->current_context = NULL;
 420
 421         dm_free(dc->ctx);
 422         dc->ctx = NULL;
 423 }
 424
 425 static bool construct(struct core_dc *dc,
 426                 const struct dc_init_data *init_params)
 427 {
 428         struct dal_logger *logger;
 429         struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
 430         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 431
 432         if (!dc_ctx) {
 433                 dm_error("%s: failed to create ctx\n", __func__);
 434                 goto ctx_fail;
 435         }
 436
 437         dc->current_context = dm_alloc(sizeof(*dc->current_context));
 438
 439         if (!dc->current_context) {
 440                 dm_error("%s: failed to create validate ctx\n", __func__);
 441                 goto val_ctx_fail;
 442         }
 443
 444         dc_ctx->cgs_device = init_params->cgs_device;
 445         dc_ctx->driver_context = init_params->driver;
 446         dc_ctx->dc = &dc->public;
 447         dc_ctx->asic_id = init_params->asic_id;
 448
 449         /* Create logger */
 450         logger = dal_logger_create(dc_ctx);
 451
 452         if (!logger) {
 453                 /* can *not* call logger. call base driver 'print error' */
 454                 dm_error("%s: failed to create Logger!\n", __func__);
 455                 goto logger_fail;
 456         }
 457         dc_ctx->logger = logger;
 458         dc->ctx = dc_ctx;
 459         dc->ctx->dce_environment = init_params->dce_environment;
 460
 461         dc_version = resource_parse_asic_id(init_params->asic_id);
 462         dc->ctx->dce_version = dc_version;
 463
 464         /* Resource should construct all asic specific resources.
 465          * This should be the only place where we need to parse the asic id
 466          */
 467         if (init_params->vbios_override)
 468                 dc_ctx->dc_bios = init_params->vbios_override;
 469         else {
 470                 /* Create BIOS parser */
 471                 struct bp_init_data bp_init_data;
 472
 473                 bp_init_data.ctx = dc_ctx;
 474                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 475
 476                 dc_ctx->dc_bios = dal_bios_parser_create(
 477                                 &bp_init_data, dc_version);
 478
 479                 if (!dc_ctx->dc_bios) {
 480                         ASSERT_CRITICAL(false);
 481                         goto bios_fail;
 482                 }
 483
 484                 dc_ctx->created_bios = true;
 485                 }
 486
 487         /* Create I2C AUX */
 488         dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
 489
 490         if (!dc_ctx->i2caux) {
 491                 ASSERT_CRITICAL(false);
 492                 goto failed_to_create_i2caux;
 493         }
 494
 495         /* Create GPIO service */
 496         dc_ctx->gpio_service = dal_gpio_service_create(
 497                         dc_version,
 498                         dc_ctx->dce_environment,
 499                         dc_ctx);
 500
 501         if (!dc_ctx->gpio_service) {
 502                 ASSERT_CRITICAL(false);
 503                 goto gpio_fail;
 504         }
 505
 506         dc->res_pool = dc_create_resource_pool(
 507                         dc,
 508                         init_params->num_virtual_links,
 509                         dc_version,
 510                         init_params->asic_id);
 511         if (!dc->res_pool)
 512                 goto create_resource_fail;
 513
 514         if (!create_links(dc, init_params->num_virtual_links))
 515                 goto create_links_fail;
 516
 517         allocate_dc_stream_funcs(dc);
 518
 519         return true;
 520
 521         /**** error handling here ****/
 522 create_links_fail:
 523 create_resource_fail:
 524 gpio_fail:
 525 failed_to_create_i2caux:
 526 bios_fail:
 527 logger_fail:
 528 val_ctx_fail:
 529 ctx_fail:
 530         destruct(dc);
 531         return false;
 532 }
 533
 534 /*
 535 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
 536 {
 537         fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
 538         unsigned int pixDurationInPico = round(pixel_duration);
 539
 540         DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
 541
 542         arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
 543         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
 544         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
 545
 546         arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
 547         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
 548         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
 549
 550         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
 551         WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
 552
 553         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
 554         WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
 555 }
 556 */
 557
 558 /*******************************************************************************
 559  * Public functions
 560  ******************************************************************************/
 561
 562 struct dc *dc_create(const struct dc_init_data *init_params)
 563  {
 564         struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
 565         unsigned int full_pipe_count;
 566
 567         if (NULL == core_dc)
 568                 goto alloc_fail;
 569
 570         if (false == construct(core_dc, init_params))
 571                 goto construct_fail;
 572
 573         /*TODO: separate HW and SW initialization*/
 574         core_dc->hwss.init_hw(core_dc);
 575
 576         full_pipe_count = core_dc->res_pool->pipe_count;
 577         if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 578                 full_pipe_count--;
 579         core_dc->public.caps.max_streams = min(
 580                         full_pipe_count,
 581                         core_dc->res_pool->stream_enc_count);
 582
 583         core_dc->public.caps.max_links = core_dc->link_count;
 584         core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
 585
 586         core_dc->public.config = init_params->flags;
 587
 588         dm_logger_write(core_dc->ctx->logger, LOG_DC,
 589                         "Display Core initialized\n");
 590
 591
 592         /* TODO: missing feature to be enabled */
 593         core_dc->public.debug.disable_dfs_bypass = true;
 594
 595         return &core_dc->public;
 596
 597 construct_fail:
 598         dm_free(core_dc);
 599
 600 alloc_fail:
 601         return NULL;
 602 }
 603
 604 void dc_destroy(struct dc **dc)
 605 {
 606         struct core_dc *core_dc = DC_TO_CORE(*dc);
 607         destruct(core_dc);
 608         dm_free(core_dc);
 609         *dc = NULL;
 610 }
 611
 612 static bool is_validation_required(
 613                 const struct core_dc *dc,
 614                 const struct dc_validation_set set[],
 615                 int set_count)
 616 {
 617         const struct validate_context *context = dc->current_context;
 618         int i, j;
 619
 620         if (context->stream_count != set_count)
 621                 return true;
 622
 623         for (i = 0; i < set_count; i++) {
 624
 625                 if (set[i].surface_count != context->stream_status[i].surface_count)
 626                         return true;
 627                 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
 628                         return true;
 629
 630                 for (j = 0; j < set[i].surface_count; j++) {
 631                         struct dc_surface temp_surf;
 632                         memset(&temp_surf, 0, sizeof(temp_surf));
 633
 634                         temp_surf = *context->stream_status[i].surfaces[j];
 635                         temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
 636                         temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
 637                         temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
 638
 639                         if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
 640                                 return true;
 641                 }
 642         }
 643
 644         return false;
 645 }
 646
 647 struct validate_context *dc_get_validate_context(
 648                 const struct dc *dc,
 649                 const struct dc_validation_set set[],
 650                 uint8_t set_count)
 651 {
 652         struct core_dc *core_dc = DC_TO_CORE(dc);
 653         enum dc_status result = DC_ERROR_UNEXPECTED;
 654         struct validate_context *context;
 655
 656         context = dm_alloc(sizeof(struct validate_context));
 657         if (context == NULL)
 658                 goto context_alloc_fail;
 659
 660         if (!is_validation_required(core_dc, set, set_count)) {
 661                 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
 662                 return context;
 663         }
 664
 665         result = core_dc->res_pool->funcs->validate_with_context(
 666                         core_dc, set, set_count, context, core_dc->current_context);
 667
 668 context_alloc_fail:
 669         if (result != DC_OK) {
 670                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 671                                 "%s:resource validation failed, dc_status:%d\n",
 672                                 __func__,
 673                                 result);
 674
 675                 dc_resource_validate_ctx_destruct(context);
 676                 dm_free(context);
 677                 context = NULL;
 678         }
 679
 680         return context;
 681
 682 }
 683
 684 bool dc_validate_resources(
 685                 const struct dc *dc,
 686                 const struct dc_validation_set set[],
 687                 uint8_t set_count)
 688 {
 689         struct core_dc *core_dc = DC_TO_CORE(dc);
 690         enum dc_status result = DC_ERROR_UNEXPECTED;
 691         struct validate_context *context;
 692
 693         context = dm_alloc(sizeof(struct validate_context));
 694         if (context == NULL)
 695                 goto context_alloc_fail;
 696
 697         result = core_dc->res_pool->funcs->validate_with_context(
 698                                 core_dc, set, set_count, context, NULL);
 699
 700 context_alloc_fail:
 701         if (result != DC_OK) {
 702                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 703                                 "%s:resource validation failed, dc_status:%d\n",
 704                                 __func__,
 705                                 result);
 706         }
 707
 708         dc_resource_validate_ctx_destruct(context);
 709         dm_free(context);
 710         context = NULL;
 711
 712         return result == DC_OK;
 713 }
 714
 715 bool dc_validate_guaranteed(
 716                 const struct dc *dc,
 717                 const struct dc_stream *stream)
 718 {
 719         struct core_dc *core_dc = DC_TO_CORE(dc);
 720         enum dc_status result = DC_ERROR_UNEXPECTED;
 721         struct validate_context *context;
 722
 723         context = dm_alloc(sizeof(struct validate_context));
 724         if (context == NULL)
 725                 goto context_alloc_fail;
 726
 727         result = core_dc->res_pool->funcs->validate_guaranteed(
 728                                         core_dc, stream, context);
 729
 730         dc_resource_validate_ctx_destruct(context);
 731         dm_free(context);
 732
 733 context_alloc_fail:
 734         if (result != DC_OK) {
 735                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
 736                         "%s:guaranteed validation failed, dc_status:%d\n",
 737                         __func__,
 738                         result);
 739                 }
 740
 741         return (result == DC_OK);
 742 }
 743
 744 static void program_timing_sync(
 745                 struct core_dc *core_dc,
 746                 struct validate_context *ctx)
 747 {
 748         int i, j;
 749         int group_index = 0;
 750         int pipe_count = core_dc->res_pool->pipe_count;
 751         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 752
 753         for (i = 0; i < pipe_count; i++) {
 754                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 755                         continue;
 756
 757                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 758         }
 759
 760         for (i = 0; i < pipe_count; i++) {
 761                 int group_size = 1;
 762                 struct pipe_ctx *pipe_set[MAX_PIPES];
 763
 764                 if (!unsynced_pipes[i])
 765                         continue;
 766
 767                 pipe_set[0] = unsynced_pipes[i];
 768                 unsynced_pipes[i] = NULL;
 769
 770                 /* Add tg to the set, search rest of the tg's for ones with
 771                  * same timing, add all tgs with same timing to the group
 772                  */
 773                 for (j = i + 1; j < pipe_count; j++) {
 774                         if (!unsynced_pipes[j])
 775                                 continue;
 776
 777                         if (resource_are_streams_timing_synchronizable(
 778                                         unsynced_pipes[j]->stream,
 779                                         pipe_set[0]->stream)) {
 780                                 pipe_set[group_size] = unsynced_pipes[j];
 781                                 unsynced_pipes[j] = NULL;
 782                                 group_size++;
 783                         }
 784                 }
 785
 786                 /* set first unblanked pipe as master */
 787                 for (j = 0; j < group_size; j++) {
 788                         struct pipe_ctx *temp;
 789
 790                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
 791                                 if (j == 0)
 792                                         break;
 793
 794                                 temp = pipe_set[0];
 795                                 pipe_set[0] = pipe_set[j];
 796                                 pipe_set[j] = temp;
 797                                 break;
 798                         }
 799                 }
 800
 801                 /* remove any other unblanked pipes as they have already been synced */
 802                 for (j = j + 1; j < group_size; j++) {
 803                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
 804                                 group_size--;
 805                                 pipe_set[j] = pipe_set[group_size];
 806                                 j--;
 807                         }
 808                 }
 809
 810                 if (group_size > 1) {
 811                         core_dc->hwss.enable_timing_synchronization(
 812                                 core_dc, group_index, group_size, pipe_set);
 813                         group_index++;
 814                 }
 815         }
 816 }
 817
 818 static bool streams_changed(
 819                 struct core_dc *dc,
 820                 const struct dc_stream *streams[],
 821                 uint8_t stream_count)
 822 {
 823         uint8_t i;
 824
 825         if (stream_count != dc->current_context->stream_count)
 826                 return true;
 827
 828         for (i = 0; i < dc->current_context->stream_count; i++) {
 829                 if (&dc->current_context->streams[i]->public != streams[i])
 830                         return true;
 831         }
 832
 833         return false;
 834 }
 835
 836 bool dc_enable_stereo(
 837         struct dc *dc,
 838         struct validate_context *context,
 839         const struct dc_stream *streams[],
 840         uint8_t stream_count)
 841 {
 842         bool ret = true;
 843         int i, j;
 844         struct pipe_ctx *pipe;
 845         struct core_dc *core_dc = DC_TO_CORE(dc);
 846         for (i = 0; i < MAX_PIPES; i++) {
 847                 if (context != NULL)
 848                         pipe = &context->res_ctx.pipe_ctx[i];
 849                 else
 850                         pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
 851                 for (j = 0 ; pipe && j < stream_count; j++)  {
 852                         if (streams[j] && streams[j] == &pipe->stream->public &&
 853                                 core_dc->hwss.setup_stereo)
 854                                 core_dc->hwss.setup_stereo(pipe, core_dc);
 855                 }
 856         }
 857         return ret;
 858 }
 859
 860 bool dc_commit_streams(
 861         struct dc *dc,
 862         const struct dc_stream *streams[],
 863         uint8_t stream_count)
 864 {
 865         struct core_dc *core_dc = DC_TO_CORE(dc);
 866         struct dc_bios *dcb = core_dc->ctx->dc_bios;
 867         enum dc_status result = DC_ERROR_UNEXPECTED;
 868         struct validate_context *context;
 869         struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
 870         int i, j;
 871
 872         if (false == streams_changed(core_dc, streams, stream_count))
 873                 return DC_OK;
 874
 875         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
 876                                 __func__, stream_count);
 877
 878         for (i = 0; i < stream_count; i++) {
 879                 const struct dc_stream *stream = streams[i];
 880                 const struct dc_stream_status *status = dc_stream_get_status(stream);
 881                 int j;
 882
 883                 dc_stream_log(stream,
 884                                 core_dc->ctx->logger,
 885                                 LOG_DC);
 886
 887                 set[i].stream = stream;
 888
 889                 if (status) {
 890                         set[i].surface_count = status->surface_count;
 891                         for (j = 0; j < status->surface_count; j++)
 892                                 set[i].surfaces[j] = status->surfaces[j];
 893                 }
 894
 895         }
 896
 897         context = dm_alloc(sizeof(struct validate_context));
 898         if (context == NULL)
 899                 goto context_alloc_fail;
 900
 901         result = core_dc->res_pool->funcs->validate_with_context(
 902                         core_dc, set, stream_count, context, core_dc->current_context);
 903         if (result != DC_OK){
 904                 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
 905                                         "%s: Context validation failed! dc_status:%d\n",
 906                                         __func__,
 907                                         result);
 908                 BREAK_TO_DEBUGGER();
 909                 dc_resource_validate_ctx_destruct(context);
 910                 goto fail;
 911         }
 912
 913         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 914                 core_dc->hwss.enable_accelerated_mode(core_dc);
 915         }
 916
 917         if (result == DC_OK) {
 918                 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
 919         }
 920
 921         program_timing_sync(core_dc, context);
 922
 923         for (i = 0; i < context->stream_count; i++) {
 924                 const struct core_sink *sink = context->streams[i]->sink;
 925
 926                 for (j = 0; j < context->stream_status[i].surface_count; j++) {
 927                         struct core_surface *surface =
 928                                         DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
 929
 930                         core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
 931                         dc_enable_stereo(dc, context, streams, stream_count);
 932                 }
 933
 934                 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
 935                                 context->streams[i]->public.timing.h_addressable,
 936                                 context->streams[i]->public.timing.v_addressable,
 937                                 context->streams[i]->public.timing.h_total,
 938                                 context->streams[i]->public.timing.v_total,
 939                                 context->streams[i]->public.timing.pix_clk_khz);
 940         }
 941
 942         dc_resource_validate_ctx_destruct(core_dc->current_context);
 943         dm_free(core_dc->current_context);
 944
 945         core_dc->current_context = context;
 946
 947         return (result == DC_OK);
 948
 949 fail:
 950         dm_free(context);
 951
 952 context_alloc_fail:
 953         return (result == DC_OK);
 954 }
 955
 956 bool dc_post_update_surfaces_to_stream(struct dc *dc)
 957 {
 958         int i;
 959         struct core_dc *core_dc = DC_TO_CORE(dc);
 960         struct validate_context *context = core_dc->current_context;
 961
 962         post_surface_trace(dc);
 963
 964         for (i = 0; i < core_dc->res_pool->pipe_count; i++)
 965                 if (context->res_ctx.pipe_ctx[i].stream == NULL
 966                                 || context->res_ctx.pipe_ctx[i].surface == NULL) {
 967                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
 968                         core_dc->hwss.power_down_front_end(
 969                                         core_dc, &context->res_ctx.pipe_ctx[i]);
 970                 }
 971
 972         /* 3rd param should be true, temp w/a for RV*/
 973 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 974         core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
 975 #else
 976         core_dc->hwss.set_bandwidth(core_dc, context, true);
 977 #endif
 978         return true;
 979 }
 980
 981 bool dc_commit_surfaces_to_stream(
 982                 struct dc *dc,
 983                 const struct dc_surface **new_surfaces,
 984                 uint8_t new_surface_count,
 985                 const struct dc_stream *dc_stream)
 986 {
 987         struct dc_surface_update updates[MAX_SURFACES];
 988         struct dc_flip_addrs flip_addr[MAX_SURFACES];
 989         struct dc_plane_info plane_info[MAX_SURFACES];
 990         struct dc_scaling_info scaling_info[MAX_SURFACES];
 991         int i;
 992         bool ret;
 993         struct dc_stream_update *stream_update =
 994                         dm_alloc(sizeof(struct dc_stream_update));
 995
 996         if (!stream_update) {
 997                 BREAK_TO_DEBUGGER();
 998                 return false;
 999         }
1000
1001         memset(updates, 0, sizeof(updates));
1002         memset(flip_addr, 0, sizeof(flip_addr));
1003         memset(plane_info, 0, sizeof(plane_info));
1004         memset(scaling_info, 0, sizeof(scaling_info));
1005
1006         stream_update->src = dc_stream->src;
1007         stream_update->dst = dc_stream->dst;
1008
1009         for (i = 0; i < new_surface_count; i++) {
1010                 updates[i].surface = new_surfaces[i];
1011                 updates[i].gamma =
1012                         (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1013                 flip_addr[i].address = new_surfaces[i]->address;
1014                 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1015                 plane_info[i].color_space = new_surfaces[i]->color_space;
1016                 plane_info[i].format = new_surfaces[i]->format;
1017                 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1018                 plane_info[i].rotation = new_surfaces[i]->rotation;
1019                 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1020                 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1021                 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1022                 plane_info[i].visible = new_surfaces[i]->visible;
1023                 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1024                 plane_info[i].dcc = new_surfaces[i]->dcc;
1025                 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1026                 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1027                 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1028                 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1029
1030                 updates[i].flip_addr = &flip_addr[i];
1031                 updates[i].plane_info = &plane_info[i];
1032                 updates[i].scaling_info = &scaling_info[i];
1033         }
1034
1035         dc_update_surfaces_and_stream(
1036                         dc,
1037                         updates,
1038                         new_surface_count,
1039                         dc_stream, stream_update);
1040
1041         ret = dc_post_update_surfaces_to_stream(dc);
1042
1043         dm_free(stream_update);
1044         return ret;
1045 }
1046
1047 static bool is_surface_in_context(
1048                 const struct validate_context *context,
1049                 const struct dc_surface *surface)
1050 {
1051         int j;
1052
1053         for (j = 0; j < MAX_PIPES; j++) {
1054                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1055
1056                 if (surface == &pipe_ctx->surface->public) {
1057                         return true;
1058                 }
1059         }
1060
1061         return false;
1062 }
1063
1064 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1065 {
1066         switch (format) {
1067         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1068         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1069                 return 12;
1070         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1071         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1072         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1073         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1074                 return 16;
1075         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1076         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1077         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1078         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1079                 return 32;
1080         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1081         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1082         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1083                 return 64;
1084         default:
1085                 ASSERT_CRITICAL(false);
1086                 return -1;
1087         }
1088 }
1089
1090 static enum surface_update_type get_plane_info_update_type(
1091                 const struct dc_surface_update *u,
1092                 int surface_index)
1093 {
1094         struct dc_plane_info temp_plane_info;
1095         memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1096
1097         if (!u->plane_info)
1098                 return UPDATE_TYPE_FAST;
1099
1100         temp_plane_info = *u->plane_info;
1101
1102         /* Copy all parameters that will cause a full update
1103          * from current surface, the rest of the parameters
1104          * from provided plane configuration.
1105          * Perform memory compare and special validation
1106          * for those that can cause fast/medium updates
1107          */
1108
1109         /* Full update parameters */
1110         temp_plane_info.color_space = u->surface->color_space;
1111         temp_plane_info.dcc = u->surface->dcc;
1112         temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1113         temp_plane_info.plane_size = u->surface->plane_size;
1114         temp_plane_info.rotation = u->surface->rotation;
1115         temp_plane_info.stereo_format = u->surface->stereo_format;
1116         temp_plane_info.tiling_info = u->surface->tiling_info;
1117
1118         if (surface_index == 0)
1119                 temp_plane_info.visible = u->plane_info->visible;
1120         else
1121                 temp_plane_info.visible = u->surface->visible;
1122
1123         if (memcmp(u->plane_info, &temp_plane_info,
1124                         sizeof(struct dc_plane_info)) != 0)
1125                 return UPDATE_TYPE_FULL;
1126
1127         if (pixel_format_to_bpp(u->plane_info->format) !=
1128                         pixel_format_to_bpp(u->surface->format)) {
1129                 return UPDATE_TYPE_FULL;
1130         } else {
1131                 return UPDATE_TYPE_MED;
1132         }
1133 }
1134
1135 static enum surface_update_type  get_scaling_info_update_type(
1136                 const struct dc_surface_update *u)
1137 {
1138         if (!u->scaling_info)
1139                 return UPDATE_TYPE_FAST;
1140
1141         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1142                         || u->scaling_info->src_rect.height != u->surface->src_rect.height
1143                         || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1144                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1145                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1146                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1147                 return UPDATE_TYPE_FULL;
1148
1149         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1150                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1151                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1152                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1153                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1154                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1155                 return UPDATE_TYPE_MED;
1156
1157         return UPDATE_TYPE_FAST;
1158 }
1159
1160 static enum surface_update_type det_surface_update(
1161                 const struct core_dc *dc,
1162                 const struct dc_surface_update *u,
1163                 int surface_index)
1164 {
1165         const struct validate_context *context = dc->current_context;
1166         enum surface_update_type type = UPDATE_TYPE_FAST;
1167         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1168
1169         if (!is_surface_in_context(context, u->surface))
1170                 return UPDATE_TYPE_FULL;
1171
1172         type = get_plane_info_update_type(u, surface_index);
1173         if (overall_type < type)
1174                 overall_type = type;
1175
1176         type = get_scaling_info_update_type(u);
1177         if (overall_type < type)
1178                 overall_type = type;
1179
1180         if (u->in_transfer_func ||
1181                 u->hdr_static_metadata) {
1182                 if (overall_type < UPDATE_TYPE_MED)
1183                         overall_type = UPDATE_TYPE_MED;
1184         }
1185
1186         return overall_type;
1187 }
1188
1189 enum surface_update_type dc_check_update_surfaces_for_stream(
1190                 struct dc *dc,
1191                 struct dc_surface_update *updates,
1192                 int surface_count,
1193                 struct dc_stream_update *stream_update,
1194                 const struct dc_stream_status *stream_status)
1195 {
1196         struct core_dc *core_dc = DC_TO_CORE(dc);
1197         int i;
1198         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1199
1200         if (stream_status == NULL || stream_status->surface_count != surface_count)
1201                 return UPDATE_TYPE_FULL;
1202
1203         if (stream_update)
1204                 return UPDATE_TYPE_FULL;
1205
1206         for (i = 0 ; i < surface_count; i++) {
1207                 enum surface_update_type type =
1208                                 det_surface_update(core_dc, &updates[i], i);
1209
1210                 if (type == UPDATE_TYPE_FULL)
1211                         return type;
1212
1213                 if (overall_type < type)
1214                         overall_type = type;
1215         }
1216
1217         return overall_type;
1218 }
1219
1220 void dc_update_surfaces_for_stream(struct dc *dc,
1221                 struct dc_surface_update *surface_updates, int surface_count,
1222                 const struct dc_stream *dc_stream)
1223 {
1224         dc_update_surfaces_and_stream(dc, surface_updates, surface_count,
1225                         dc_stream, NULL);
1226 }
1227
1228 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1229
1230 void dc_update_surfaces_and_stream(struct dc *dc,
1231                 struct dc_surface_update *srf_updates, int surface_count,
1232                 const struct dc_stream *dc_stream,
1233                 struct dc_stream_update *stream_update)
1234 {
1235         struct core_dc *core_dc = DC_TO_CORE(dc);
1236         struct validate_context *context;
1237         int i, j;
1238         enum surface_update_type update_type;
1239         const struct dc_stream_status *stream_status;
1240         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1241
1242         stream_status = dc_stream_get_status(dc_stream);
1243         ASSERT(stream_status);
1244         if (!stream_status)
1245                 return; /* Cannot commit surface to stream that is not committed */
1246
1247         context = core_dc->current_context;
1248
1249         /* update current stream with the new updates */
1250         if (stream_update) {
1251                 if ((stream_update->src.height != 0) &&
1252                                 (stream_update->src.width != 0))
1253                         stream->public.src = stream_update->src;
1254
1255                 if ((stream_update->dst.height != 0) &&
1256                                 (stream_update->dst.width != 0))
1257                         stream->public.dst = stream_update->dst;
1258
1259                 if (stream_update->out_transfer_func &&
1260                                 stream_update->out_transfer_func !=
1261                                                 dc_stream->out_transfer_func) {
1262                         if (dc_stream->out_transfer_func != NULL)
1263                                 dc_transfer_func_release(dc_stream->out_transfer_func);
1264                         dc_transfer_func_retain(stream_update->out_transfer_func);
1265                         stream->public.out_transfer_func =
1266                                 stream_update->out_transfer_func;
1267                 }
1268         }
1269
1270         /* do not perform surface update if surface has invalid dimensions
1271          * (all zero) and no scaling_info is provided
1272          */
1273         if (surface_count > 0 &&
1274                         srf_updates->surface->src_rect.width == 0 &&
1275                         srf_updates->surface->src_rect.height == 0 &&
1276                         srf_updates->surface->dst_rect.width == 0 &&
1277                         srf_updates->surface->dst_rect.height == 0 &&
1278                         !srf_updates->scaling_info) {
1279                 ASSERT(false);
1280                 return;
1281         }
1282
1283         update_type = dc_check_update_surfaces_for_stream(
1284                         dc, srf_updates, surface_count, stream_update, stream_status);
1285
1286         if (update_type >= update_surface_trace_level)
1287                 update_surface_trace(dc, srf_updates, surface_count);
1288
1289         if (update_type >= UPDATE_TYPE_FULL) {
1290                 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1291
1292                 for (i = 0; i < surface_count; i++)
1293                         new_surfaces[i] = srf_updates[i].surface;
1294
1295                 /* initialize scratch memory for building context */
1296                 context = dm_alloc(sizeof(*context));
1297                 dc_resource_validate_ctx_copy_construct(
1298                                 core_dc->current_context, context);
1299
1300                 /* add surface to context */
1301                 if (!resource_attach_surfaces_to_context(
1302                                 new_surfaces, surface_count, dc_stream,
1303                                 context, core_dc->res_pool)) {
1304                         BREAK_TO_DEBUGGER();
1305                         goto fail;
1306                 }
1307         }
1308
1309         /* save update parameters into surface */
1310         for (i = 0; i < surface_count; i++) {
1311                 struct core_surface *surface =
1312                                 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1313
1314                 if (srf_updates[i].flip_addr) {
1315                         surface->public.address = srf_updates[i].flip_addr->address;
1316                         surface->public.flip_immediate =
1317                                         srf_updates[i].flip_addr->flip_immediate;
1318                 }
1319
1320                 if (srf_updates[i].scaling_info) {
1321                         surface->public.scaling_quality =
1322                                         srf_updates[i].scaling_info->scaling_quality;
1323                         surface->public.dst_rect =
1324                                         srf_updates[i].scaling_info->dst_rect;
1325                         surface->public.src_rect =
1326                                         srf_updates[i].scaling_info->src_rect;
1327                         surface->public.clip_rect =
1328                                         srf_updates[i].scaling_info->clip_rect;
1329                 }
1330
1331                 if (srf_updates[i].plane_info) {
1332                         surface->public.color_space =
1333                                         srf_updates[i].plane_info->color_space;
1334                         surface->public.format =
1335                                         srf_updates[i].plane_info->format;
1336                         surface->public.plane_size =
1337                                         srf_updates[i].plane_info->plane_size;
1338                         surface->public.rotation =
1339                                         srf_updates[i].plane_info->rotation;
1340                         surface->public.horizontal_mirror =
1341                                         srf_updates[i].plane_info->horizontal_mirror;
1342                         surface->public.stereo_format =
1343                                         srf_updates[i].plane_info->stereo_format;
1344                         surface->public.tiling_info =
1345                                         srf_updates[i].plane_info->tiling_info;
1346                         surface->public.visible =
1347                                         srf_updates[i].plane_info->visible;
1348                         surface->public.per_pixel_alpha =
1349                                         srf_updates[i].plane_info->per_pixel_alpha;
1350                         surface->public.dcc =
1351                                         srf_updates[i].plane_info->dcc;
1352                 }
1353
1354                 if (update_type >= UPDATE_TYPE_MED) {
1355                         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1356                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1357
1358                                 if (pipe_ctx->surface != surface)
1359                                         continue;
1360
1361                                 resource_build_scaling_params(pipe_ctx);
1362                         }
1363                 }
1364
1365                 if (srf_updates[i].gamma &&
1366                         srf_updates[i].gamma != surface->public.gamma_correction) {
1367                         if (surface->public.gamma_correction != NULL)
1368                                 dc_gamma_release(&surface->public.
1369                                                 gamma_correction);
1370
1371                         dc_gamma_retain(srf_updates[i].gamma);
1372                         surface->public.gamma_correction =
1373                                                 srf_updates[i].gamma;
1374                 }
1375
1376                 if (srf_updates[i].in_transfer_func &&
1377                         srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1378                         if (surface->public.in_transfer_func != NULL)
1379                                 dc_transfer_func_release(
1380                                                 surface->public.
1381                                                 in_transfer_func);
1382
1383                         dc_transfer_func_retain(
1384                                         srf_updates[i].in_transfer_func);
1385                         surface->public.in_transfer_func =
1386                                         srf_updates[i].in_transfer_func;
1387                 }
1388
1389                 if (srf_updates[i].hdr_static_metadata)
1390                         surface->public.hdr_static_ctx =
1391                                 *(srf_updates[i].hdr_static_metadata);
1392         }
1393
1394         if (update_type == UPDATE_TYPE_FULL) {
1395                 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1396                         BREAK_TO_DEBUGGER();
1397                         goto fail;
1398                 } else {
1399                         core_dc->hwss.set_bandwidth(core_dc, context, false);
1400                         context_clock_trace(dc, context);
1401                 }
1402         }
1403
1404         if (!surface_count)  /* reset */
1405                 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1406
1407         /* Lock pipes for provided surfaces */
1408         for (i = 0; i < surface_count; i++) {
1409                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1410
1411                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1412                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1413
1414                         if (pipe_ctx->surface != surface)
1415                                 continue;
1416                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1417                                 core_dc->hwss.pipe_control_lock(
1418                                                 core_dc,
1419                                                 pipe_ctx,
1420                                                 true);
1421                         }
1422                 }
1423         }
1424
1425         /* Perform requested Updates */
1426         for (i = 0; i < surface_count; i++) {
1427                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1428
1429                 if (update_type >= UPDATE_TYPE_MED) {
1430                                 core_dc->hwss.apply_ctx_for_surface(
1431                                                 core_dc, surface, context);
1432                                 context_timing_trace(dc, &context->res_ctx);
1433                 }
1434
1435                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1436                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1437                         struct pipe_ctx *cur_pipe_ctx;
1438                         bool is_new_pipe_surface = true;
1439
1440                         if (pipe_ctx->surface != surface)
1441                                 continue;
1442
1443                         if (srf_updates[i].flip_addr)
1444                                 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1445
1446                         if (update_type == UPDATE_TYPE_FAST)
1447                                 continue;
1448
1449                         cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1450                         if (cur_pipe_ctx->surface == pipe_ctx->surface)
1451                                 is_new_pipe_surface = false;
1452
1453                         if (is_new_pipe_surface ||
1454                                         srf_updates[i].in_transfer_func)
1455                                 core_dc->hwss.set_input_transfer_func(
1456                                                 pipe_ctx, pipe_ctx->surface);
1457
1458                         if (is_new_pipe_surface ||
1459                                 (stream_update != NULL &&
1460                                         stream_update->out_transfer_func !=
1461                                                         NULL)) {
1462                                 core_dc->hwss.set_output_transfer_func(
1463                                                 pipe_ctx, pipe_ctx->stream);
1464                         }
1465
1466                         if (srf_updates[i].hdr_static_metadata) {
1467                                 resource_build_info_frame(pipe_ctx);
1468                                 core_dc->hwss.update_info_frame(pipe_ctx);
1469                         }
1470                 }
1471         }
1472
1473         /* Unlock pipes */
1474         for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1475                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1476
1477                 for (j = 0; j < surface_count; j++) {
1478                         if (srf_updates[j].surface == &pipe_ctx->surface->public) {
1479                                 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1480                                         core_dc->hwss.pipe_control_lock(
1481                                                         core_dc,
1482                                                         pipe_ctx,
1483                                                         false);
1484                                 }
1485                                 break;
1486                         }
1487                 }
1488         }
1489
1490         if (core_dc->current_context != context) {
1491                 dc_resource_validate_ctx_destruct(core_dc->current_context);
1492                 dm_free(core_dc->current_context);
1493
1494                 core_dc->current_context = context;
1495         }
1496         return;
1497
1498 fail:
1499         dc_resource_validate_ctx_destruct(context);
1500         dm_free(context);
1501 }
1502
1503 uint8_t dc_get_current_stream_count(const struct dc *dc)
1504 {
1505         struct core_dc *core_dc = DC_TO_CORE(dc);
1506         return core_dc->current_context->stream_count;
1507 }
1508
1509 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1510 {
1511         struct core_dc *core_dc = DC_TO_CORE(dc);
1512         if (i < core_dc->current_context->stream_count)
1513                 return &(core_dc->current_context->streams[i]->public);
1514         return NULL;
1515 }
1516
1517 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1518 {
1519         struct core_dc *core_dc = DC_TO_CORE(dc);
1520         return &core_dc->links[link_index]->public;
1521 }
1522
1523 const struct graphics_object_id dc_get_link_id_at_index(
1524         struct dc *dc, uint32_t link_index)
1525 {
1526         struct core_dc *core_dc = DC_TO_CORE(dc);
1527         return core_dc->links[link_index]->link_id;
1528 }
1529
1530 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1531         struct dc *dc, uint32_t link_index)
1532 {
1533         struct core_dc *core_dc = DC_TO_CORE(dc);
1534         return core_dc->links[link_index]->public.irq_source_hpd;
1535 }
1536
1537 const struct audio **dc_get_audios(struct dc *dc)
1538 {
1539         struct core_dc *core_dc = DC_TO_CORE(dc);
1540         return (const struct audio **)core_dc->res_pool->audios;
1541 }
1542
1543 enum dc_irq_source dc_interrupt_to_irq_source(
1544                 struct dc *dc,
1545                 uint32_t src_id,
1546                 uint32_t ext_id)
1547 {
1548         struct core_dc *core_dc = DC_TO_CORE(dc);
1549         return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1550 }
1551
1552 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1553 {
1554         struct core_dc *core_dc;
1555
1556         if (dc == NULL)
1557                 return;
1558         core_dc = DC_TO_CORE(dc);
1559
1560         dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1561 }
1562
1563 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1564 {
1565         struct core_dc *core_dc = DC_TO_CORE(dc);
1566         dal_irq_service_ack(core_dc->res_pool->irqs, src);
1567 }
1568
1569 void dc_set_power_state(
1570         struct dc *dc,
1571         enum dc_acpi_cm_power_state power_state)
1572 {
1573         struct core_dc *core_dc = DC_TO_CORE(dc);
1574
1575         switch (power_state) {
1576         case DC_ACPI_CM_POWER_STATE_D0:
1577                 core_dc->hwss.init_hw(core_dc);
1578                 break;
1579         default:
1580
1581                 core_dc->hwss.power_down(core_dc);
1582
1583                 /* Zero out the current context so that on resume we start with
1584                  * clean state, and dc hw programming optimizations will not
1585                  * cause any trouble.
1586                  */
1587                 memset(core_dc->current_context, 0,
1588                                 sizeof(*core_dc->current_context));
1589
1590                 break;
1591         }
1592
1593 }
1594
1595 void dc_resume(const struct dc *dc)
1596 {
1597         struct core_dc *core_dc = DC_TO_CORE(dc);
1598
1599         uint32_t i;
1600
1601         for (i = 0; i < core_dc->link_count; i++)
1602                 core_link_resume(core_dc->links[i]);
1603 }
1604
1605 bool dc_read_aux_dpcd(
1606                 struct dc *dc,
1607                 uint32_t link_index,
1608                 uint32_t address,
1609                 uint8_t *data,
1610                 uint32_t size)
1611 {
1612         struct core_dc *core_dc = DC_TO_CORE(dc);
1613
1614         struct core_link *link = core_dc->links[link_index];
1615         enum ddc_result r = dal_ddc_service_read_dpcd_data(
1616                         link->public.ddc,
1617                         false,
1618                         I2C_MOT_UNDEF,
1619                         address,
1620                         data,
1621                         size);
1622         return r == DDC_RESULT_SUCESSFULL;
1623 }
1624
1625 bool dc_write_aux_dpcd(
1626                 struct dc *dc,
1627                 uint32_t link_index,
1628                 uint32_t address,
1629                 const uint8_t *data,
1630                 uint32_t size)
1631 {
1632         struct core_dc *core_dc = DC_TO_CORE(dc);
1633         struct core_link *link = core_dc->links[link_index];
1634
1635         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1636                         link->public.ddc,
1637                         false,
1638                         I2C_MOT_UNDEF,
1639                         address,
1640                         data,
1641                         size);
1642         return r == DDC_RESULT_SUCESSFULL;
1643 }
1644
1645 bool dc_read_aux_i2c(
1646                 struct dc *dc,
1647                 uint32_t link_index,
1648                 enum i2c_mot_mode mot,
1649                 uint32_t address,
1650                 uint8_t *data,
1651                 uint32_t size)
1652 {
1653         struct core_dc *core_dc = DC_TO_CORE(dc);
1654
1655                 struct core_link *link = core_dc->links[link_index];
1656                 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1657                         link->public.ddc,
1658                         true,
1659                         mot,
1660                         address,
1661                         data,
1662                         size);
1663                 return r == DDC_RESULT_SUCESSFULL;
1664 }
1665
1666 bool dc_write_aux_i2c(
1667                 struct dc *dc,
1668                 uint32_t link_index,
1669                 enum i2c_mot_mode mot,
1670                 uint32_t address,
1671                 const uint8_t *data,
1672                 uint32_t size)
1673 {
1674         struct core_dc *core_dc = DC_TO_CORE(dc);
1675         struct core_link *link = core_dc->links[link_index];
1676
1677         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1678                         link->public.ddc,
1679                         true,
1680                         mot,
1681                         address,
1682                         data,
1683                         size);
1684         return r == DDC_RESULT_SUCESSFULL;
1685 }
1686
1687 bool dc_query_ddc_data(
1688                 struct dc *dc,
1689                 uint32_t link_index,
1690                 uint32_t address,
1691                 uint8_t *write_buf,
1692                 uint32_t write_size,
1693                 uint8_t *read_buf,
1694                 uint32_t read_size) {
1695
1696         struct core_dc *core_dc = DC_TO_CORE(dc);
1697
1698         struct core_link *link = core_dc->links[link_index];
1699
1700         bool result = dal_ddc_service_query_ddc_data(
1701                         link->public.ddc,
1702                         address,
1703                         write_buf,
1704                         write_size,
1705                         read_buf,
1706                         read_size);
1707
1708         return result;
1709 }
1710
1711 bool dc_submit_i2c(
1712                 struct dc *dc,
1713                 uint32_t link_index,
1714                 struct i2c_command *cmd)
1715 {
1716         struct core_dc *core_dc = DC_TO_CORE(dc);
1717
1718         struct core_link *link = core_dc->links[link_index];
1719         struct ddc_service *ddc = link->public.ddc;
1720
1721         return dal_i2caux_submit_i2c_command(
1722                 ddc->ctx->i2caux,
1723                 ddc->ddc_pin,
1724                 cmd);
1725 }
1726
1727 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1728 {
1729         struct dc_link *dc_link = &core_link->public;
1730
1731         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1732                 BREAK_TO_DEBUGGER();
1733                 return false;
1734         }
1735
1736         dc_sink_retain(sink);
1737
1738         dc_link->remote_sinks[dc_link->sink_count] = sink;
1739         dc_link->sink_count++;
1740
1741         return true;
1742 }
1743
1744 struct dc_sink *dc_link_add_remote_sink(
1745                 const struct dc_link *link,
1746                 const uint8_t *edid,
1747                 int len,
1748                 struct dc_sink_init_data *init_data)
1749 {
1750         struct dc_sink *dc_sink;
1751         enum dc_edid_status edid_status;
1752         struct core_link *core_link = DC_LINK_TO_LINK(link);
1753
1754         if (len > MAX_EDID_BUFFER_SIZE) {
1755                 dm_error("Max EDID buffer size breached!\n");
1756                 return NULL;
1757         }
1758
1759         if (!init_data) {
1760                 BREAK_TO_DEBUGGER();
1761                 return NULL;
1762         }
1763
1764         if (!init_data->link) {
1765                 BREAK_TO_DEBUGGER();
1766                 return NULL;
1767         }
1768
1769         dc_sink = dc_sink_create(init_data);
1770
1771         if (!dc_sink)
1772                 return NULL;
1773
1774         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1775         dc_sink->dc_edid.length = len;
1776
1777         if (!link_add_remote_sink_helper(
1778                         core_link,
1779                         dc_sink))
1780                 goto fail_add_sink;
1781
1782         edid_status = dm_helpers_parse_edid_caps(
1783                         core_link->ctx,
1784                         &dc_sink->dc_edid,
1785                         &dc_sink->edid_caps);
1786
1787         if (edid_status != EDID_OK)
1788                 goto fail;
1789
1790         return dc_sink;
1791 fail:
1792         dc_link_remove_remote_sink(link, dc_sink);
1793 fail_add_sink:
1794         dc_sink_release(dc_sink);
1795         return NULL;
1796 }
1797
1798 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1799 {
1800         struct core_link *core_link = DC_LINK_TO_LINK(link);
1801         struct dc_link *dc_link = &core_link->public;
1802
1803         dc_link->local_sink = sink;
1804
1805         if (sink == NULL) {
1806                 dc_link->type = dc_connection_none;
1807         } else {
1808                 dc_link->type = dc_connection_single;
1809         }
1810 }
1811
1812 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1813 {
1814         int i;
1815         struct core_link *core_link = DC_LINK_TO_LINK(link);
1816         struct dc_link *dc_link = &core_link->public;
1817
1818         if (!link->sink_count) {
1819                 BREAK_TO_DEBUGGER();
1820                 return;
1821         }
1822
1823         for (i = 0; i < dc_link->sink_count; i++) {
1824                 if (dc_link->remote_sinks[i] == sink) {
1825                         dc_sink_release(sink);
1826                         dc_link->remote_sinks[i] = NULL;
1827
1828                         /* shrink array to remove empty place */
1829                         while (i < dc_link->sink_count - 1) {
1830                                 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1831                                 i++;
1832                         }
1833                         dc_link->remote_sinks[i] = NULL;
1834                         dc_link->sink_count--;
1835                         return;
1836                 }
1837         }
1838 }
1839
1840 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1841 {
1842         int i;
1843         struct core_dc *core_dc = DC_TO_CORE(dc);
1844         struct mem_input *mi = NULL;
1845
1846         for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1847                 if (core_dc->res_pool->mis[i] != NULL) {
1848                         mi = core_dc->res_pool->mis[i];
1849                         break;
1850                 }
1851         }
1852         if (mi == NULL) {
1853                 dm_error("no mem_input!\n");
1854                 return false;
1855         }
1856
1857         if (mi->funcs->mem_input_update_dchub)
1858                 mi->funcs->mem_input_update_dchub(mi, dh_data);
1859         else
1860                 ASSERT(mi->funcs->mem_input_update_dchub);
1861
1862
1863         return true;
1864
1865 }
1866