2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
45 #include "link_hwss.h"
46 #include "link_encoder.h"
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
52 /*******************************************************************************
54 ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
59 for (i = 0; i < dc->link_count; i++) {
60 if (NULL != dc->links[i])
61 link_destroy(&dc->links[i]);
65 static bool create_links(
67 uint32_t num_virtual_links)
71 struct dc_bios *bios = dc->ctx->dc_bios;
75 connectors_num = bios->funcs->get_connectors_number(bios);
77 if (connectors_num > ENUM_ID_COUNT) {
79 "DC: Number of connectors %d exceeds maximum of %d!\n",
85 if (connectors_num == 0 && num_virtual_links == 0) {
86 dm_error("DC: Number of connectors is zero!\n");
90 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
95 for (i = 0; i < connectors_num; i++) {
96 struct link_init_data link_init_params = {0};
97 struct core_link *link;
99 link_init_params.ctx = dc->ctx;
100 /* next BIOS object table connector */
101 link_init_params.connector_index = i;
102 link_init_params.link_index = dc->link_count;
103 link_init_params.dc = dc;
104 link = link_create(&link_init_params);
107 dc->links[dc->link_count] = link;
113 for (i = 0; i < num_virtual_links; i++) {
114 struct core_link *link = dm_alloc(sizeof(*link));
115 struct encoder_init_data enc_init = {0};
124 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127 link->link_id.enum_id = ENUM_ID_1;
128 link->link_enc = dm_alloc(sizeof(*link->link_enc));
130 enc_init.ctx = dc->ctx;
131 enc_init.channel = CHANNEL_ID_UNKNOWN;
132 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134 enc_init.connector = link->link_id;
135 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137 enc_init.encoder.enum_id = ENUM_ID_1;
138 virtual_link_encoder_construct(link->link_enc, &enc_init);
140 link->public.link_index = dc->link_count;
141 dc->links[dc->link_count] = link;
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152 const struct dc_stream **stream, int num_streams,
155 /* TODO: Support multiple streams */
156 struct core_dc *core_dc = DC_TO_CORE(dc);
157 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
161 for (i = 0; i < MAX_PIPES; i++) {
162 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
164 if (pipe->stream == core_stream && pipe->stream_enc) {
165 core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
167 /* build and update the info frame */
168 resource_build_info_frame(pipe);
169 core_dc->hwss.update_info_frame(pipe);
177 static bool stream_get_crtc_position(struct dc *dc,
178 const struct dc_stream **stream, int num_streams,
179 unsigned int *v_pos, unsigned int *nom_v_pos)
181 /* TODO: Support multiple streams */
182 struct core_dc *core_dc = DC_TO_CORE(dc);
183 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
186 struct crtc_position position;
188 for (i = 0; i < MAX_PIPES; i++) {
189 struct pipe_ctx *pipe =
190 &core_dc->current_context->res_ctx.pipe_ctx[i];
192 if (pipe->stream == core_stream && pipe->stream_enc) {
193 core_dc->hwss.get_position(&pipe, 1, &position);
195 *v_pos = position.vertical_count;
196 *nom_v_pos = position.nominal_vcount;
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
205 struct core_dc *core_dc = DC_TO_CORE(dc);
206 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
209 struct pipe_ctx *pipes;
211 for (i = 0; i < MAX_PIPES; i++) {
212 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
215 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216 core_dc->hwss.program_gamut_remap(pipes);
224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
226 struct core_dc *core_dc = DC_TO_CORE(dc);
227 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
230 struct pipe_ctx *pipes;
232 for (i = 0; i < MAX_PIPES; i++) {
233 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
236 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
237 core_dc->hwss.program_csc_matrix(pipes,
238 core_stream->public.output_color_space,
239 core_stream->public.csc_color_matrix.matrix);
247 static void set_static_screen_events(struct dc *dc,
248 const struct dc_stream **stream,
250 const struct dc_static_screen_events *events)
252 struct core_dc *core_dc = DC_TO_CORE(dc);
255 struct pipe_ctx *pipes_affected[MAX_PIPES];
256 int num_pipes_affected = 0;
258 for (i = 0; i < num_streams; i++) {
259 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
261 for (j = 0; j < MAX_PIPES; j++) {
262 if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
264 pipes_affected[num_pipes_affected++] =
265 &core_dc->current_context->res_ctx.pipe_ctx[j];
270 core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
273 static void set_drive_settings(struct dc *dc,
274 struct link_training_settings *lt_settings,
275 const struct dc_link *link)
277 struct core_dc *core_dc = DC_TO_CORE(dc);
280 for (i = 0; i < core_dc->link_count; i++) {
281 if (&core_dc->links[i]->public == link)
285 if (i >= core_dc->link_count)
286 ASSERT_CRITICAL(false);
288 dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
291 static void perform_link_training(struct dc *dc,
292 struct dc_link_settings *link_setting,
293 bool skip_video_pattern)
295 struct core_dc *core_dc = DC_TO_CORE(dc);
298 for (i = 0; i < core_dc->link_count; i++)
299 dc_link_dp_perform_link_training(
300 &core_dc->links[i]->public,
305 static void set_preferred_link_settings(struct dc *dc,
306 struct dc_link_settings *link_setting,
307 const struct dc_link *link)
309 struct core_link *core_link = DC_LINK_TO_CORE(link);
311 core_link->public.verified_link_cap.lane_count =
312 link_setting->lane_count;
313 core_link->public.verified_link_cap.link_rate =
314 link_setting->link_rate;
315 dp_retrain_link_dp_test(core_link, link_setting, false);
318 static void enable_hpd(const struct dc_link *link)
320 dc_link_dp_enable_hpd(link);
323 static void disable_hpd(const struct dc_link *link)
325 dc_link_dp_disable_hpd(link);
329 static void set_test_pattern(
330 const struct dc_link *link,
331 enum dp_test_pattern test_pattern,
332 const struct link_training_settings *p_link_settings,
333 const unsigned char *p_custom_pattern,
334 unsigned int cust_pattern_size)
337 dc_link_dp_set_test_pattern(
345 void set_dither_option(const struct dc_stream *dc_stream,
346 enum dc_dither_option option)
348 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
349 struct bit_depth_reduction_params params;
350 struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
351 struct pipe_ctx *pipes =
352 core_link->dc->current_context->res_ctx.pipe_ctx;
354 memset(¶ms, 0, sizeof(params));
357 if (option > DITHER_OPTION_MAX)
359 if (option == DITHER_OPTION_DEFAULT) {
360 switch (stream->public.timing.display_color_depth) {
361 case COLOR_DEPTH_666:
362 stream->public.dither_option = DITHER_OPTION_SPATIAL6;
364 case COLOR_DEPTH_888:
365 stream->public.dither_option = DITHER_OPTION_SPATIAL8;
367 case COLOR_DEPTH_101010:
368 stream->public.dither_option = DITHER_OPTION_SPATIAL10;
371 option = DITHER_OPTION_DISABLE;
374 stream->public.dither_option = option;
376 resource_build_bit_depth_reduction_params(stream,
378 stream->bit_depth_params = params;
380 opp_program_bit_depth_reduction(pipes->opp, ¶ms);
383 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
385 if (core_dc->hwss.set_drr != NULL) {
386 core_dc->public.stream_funcs.adjust_vmin_vmax =
387 stream_adjust_vmin_vmax;
390 core_dc->public.stream_funcs.set_static_screen_events =
391 set_static_screen_events;
393 core_dc->public.stream_funcs.get_crtc_position =
394 stream_get_crtc_position;
396 core_dc->public.stream_funcs.set_gamut_remap =
399 core_dc->public.stream_funcs.program_csc_matrix =
402 core_dc->public.stream_funcs.set_dither_option =
405 core_dc->public.link_funcs.set_drive_settings =
408 core_dc->public.link_funcs.perform_link_training =
409 perform_link_training;
411 core_dc->public.link_funcs.set_preferred_link_settings =
412 set_preferred_link_settings;
414 core_dc->public.link_funcs.enable_hpd =
417 core_dc->public.link_funcs.disable_hpd =
420 core_dc->public.link_funcs.set_test_pattern =
424 static void destruct(struct core_dc *dc)
426 dc_release_validate_context(dc->current_context);
427 dc->current_context = NULL;
431 dc_destroy_resource_pool(dc);
433 if (dc->ctx->gpio_service)
434 dal_gpio_service_destroy(&dc->ctx->gpio_service);
437 dal_i2caux_destroy(&dc->ctx->i2caux);
439 if (dc->ctx->created_bios)
440 dal_bios_parser_destroy(&dc->ctx->dc_bios);
443 dal_logger_destroy(&dc->ctx->logger);
449 static bool construct(struct core_dc *dc,
450 const struct dc_init_data *init_params)
452 struct dal_logger *logger;
453 struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
454 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
457 dm_error("%s: failed to create ctx\n", __func__);
461 dc->current_context = dm_alloc(sizeof(*dc->current_context));
463 if (!dc->current_context) {
464 dm_error("%s: failed to create validate ctx\n", __func__);
468 dc->current_context->ref_count++;
470 dc_ctx->cgs_device = init_params->cgs_device;
471 dc_ctx->driver_context = init_params->driver;
472 dc_ctx->dc = &dc->public;
473 dc_ctx->asic_id = init_params->asic_id;
476 logger = dal_logger_create(dc_ctx);
479 /* can *not* call logger. call base driver 'print error' */
480 dm_error("%s: failed to create Logger!\n", __func__);
483 dc_ctx->logger = logger;
485 dc->ctx->dce_environment = init_params->dce_environment;
487 dc_version = resource_parse_asic_id(init_params->asic_id);
488 dc->ctx->dce_version = dc_version;
490 /* Resource should construct all asic specific resources.
491 * This should be the only place where we need to parse the asic id
493 if (init_params->vbios_override)
494 dc_ctx->dc_bios = init_params->vbios_override;
496 /* Create BIOS parser */
497 struct bp_init_data bp_init_data;
499 bp_init_data.ctx = dc_ctx;
500 bp_init_data.bios = init_params->asic_id.atombios_base_address;
502 dc_ctx->dc_bios = dal_bios_parser_create(
503 &bp_init_data, dc_version);
505 if (!dc_ctx->dc_bios) {
506 ASSERT_CRITICAL(false);
510 dc_ctx->created_bios = true;
514 dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
516 if (!dc_ctx->i2caux) {
517 ASSERT_CRITICAL(false);
518 goto failed_to_create_i2caux;
521 /* Create GPIO service */
522 dc_ctx->gpio_service = dal_gpio_service_create(
524 dc_ctx->dce_environment,
527 if (!dc_ctx->gpio_service) {
528 ASSERT_CRITICAL(false);
532 dc->res_pool = dc_create_resource_pool(
534 init_params->num_virtual_links,
536 init_params->asic_id);
538 goto create_resource_fail;
540 if (!create_links(dc, init_params->num_virtual_links))
541 goto create_links_fail;
543 allocate_dc_stream_funcs(dc);
547 /**** error handling here ****/
549 create_resource_fail:
551 failed_to_create_i2caux:
561 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
563 fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
564 unsigned int pixDurationInPico = round(pixel_duration);
566 DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
568 arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
569 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
570 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
572 arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
573 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
574 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
576 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
577 WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
579 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
580 WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
584 /*******************************************************************************
586 ******************************************************************************/
588 struct dc *dc_create(const struct dc_init_data *init_params)
590 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
591 unsigned int full_pipe_count;
596 if (false == construct(core_dc, init_params))
599 /*TODO: separate HW and SW initialization*/
600 core_dc->hwss.init_hw(core_dc);
602 full_pipe_count = core_dc->res_pool->pipe_count;
603 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
605 core_dc->public.caps.max_streams = min(
607 core_dc->res_pool->stream_enc_count);
609 core_dc->public.caps.max_links = core_dc->link_count;
610 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
612 core_dc->public.config = init_params->flags;
614 dm_logger_write(core_dc->ctx->logger, LOG_DC,
615 "Display Core initialized\n");
618 /* TODO: missing feature to be enabled */
619 core_dc->public.debug.disable_dfs_bypass = true;
621 return &core_dc->public;
630 void dc_destroy(struct dc **dc)
632 struct core_dc *core_dc = DC_TO_CORE(*dc);
638 static bool is_validation_required(
639 const struct core_dc *dc,
640 const struct dc_validation_set set[],
643 const struct validate_context *context = dc->current_context;
646 if (context->stream_count != set_count)
649 for (i = 0; i < set_count; i++) {
651 if (set[i].surface_count != context->stream_status[i].surface_count)
653 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
656 for (j = 0; j < set[i].surface_count; j++) {
657 struct dc_surface temp_surf;
658 memset(&temp_surf, 0, sizeof(temp_surf));
660 temp_surf = *context->stream_status[i].surfaces[j];
661 temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
662 temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
663 temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
665 if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
673 struct validate_context *dc_get_validate_context(
675 const struct dc_validation_set set[],
678 struct core_dc *core_dc = DC_TO_CORE(dc);
679 enum dc_status result = DC_ERROR_UNEXPECTED;
680 struct validate_context *context;
682 context = dm_alloc(sizeof(struct validate_context));
684 goto context_alloc_fail;
686 ++context->ref_count;
688 if (!is_validation_required(core_dc, set, set_count)) {
689 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
693 result = core_dc->res_pool->funcs->validate_with_context(
694 core_dc, set, set_count, context, core_dc->current_context);
697 if (result != DC_OK) {
698 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
699 "%s:resource validation failed, dc_status:%d\n",
703 dc_release_validate_context(context);
711 bool dc_validate_resources(
713 const struct dc_validation_set set[],
716 struct core_dc *core_dc = DC_TO_CORE(dc);
717 enum dc_status result = DC_ERROR_UNEXPECTED;
718 struct validate_context *context;
720 context = dm_alloc(sizeof(struct validate_context));
722 goto context_alloc_fail;
724 ++context->ref_count;
726 result = core_dc->res_pool->funcs->validate_with_context(
727 core_dc, set, set_count, context, NULL);
730 if (result != DC_OK) {
731 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
732 "%s:resource validation failed, dc_status:%d\n",
737 dc_release_validate_context(context);
740 return result == DC_OK;
743 bool dc_validate_guaranteed(
745 const struct dc_stream *stream)
747 struct core_dc *core_dc = DC_TO_CORE(dc);
748 enum dc_status result = DC_ERROR_UNEXPECTED;
749 struct validate_context *context;
751 context = dm_alloc(sizeof(struct validate_context));
753 goto context_alloc_fail;
755 ++context->ref_count;
757 result = core_dc->res_pool->funcs->validate_guaranteed(
758 core_dc, stream, context);
760 dc_release_validate_context(context);
763 if (result != DC_OK) {
764 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
765 "%s:guaranteed validation failed, dc_status:%d\n",
770 return (result == DC_OK);
773 static void program_timing_sync(
774 struct core_dc *core_dc,
775 struct validate_context *ctx)
779 int pipe_count = core_dc->res_pool->pipe_count;
780 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
782 for (i = 0; i < pipe_count; i++) {
783 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
786 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
789 for (i = 0; i < pipe_count; i++) {
791 struct pipe_ctx *pipe_set[MAX_PIPES];
793 if (!unsynced_pipes[i])
796 pipe_set[0] = unsynced_pipes[i];
797 unsynced_pipes[i] = NULL;
799 /* Add tg to the set, search rest of the tg's for ones with
800 * same timing, add all tgs with same timing to the group
802 for (j = i + 1; j < pipe_count; j++) {
803 if (!unsynced_pipes[j])
806 if (resource_are_streams_timing_synchronizable(
807 unsynced_pipes[j]->stream,
808 pipe_set[0]->stream)) {
809 pipe_set[group_size] = unsynced_pipes[j];
810 unsynced_pipes[j] = NULL;
815 /* set first unblanked pipe as master */
816 for (j = 0; j < group_size; j++) {
817 struct pipe_ctx *temp;
819 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
824 pipe_set[0] = pipe_set[j];
830 /* remove any other unblanked pipes as they have already been synced */
831 for (j = j + 1; j < group_size; j++) {
832 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
834 pipe_set[j] = pipe_set[group_size];
839 if (group_size > 1) {
840 core_dc->hwss.enable_timing_synchronization(
841 core_dc, group_index, group_size, pipe_set);
847 static bool context_changed(
849 struct validate_context *context)
853 if (context->stream_count != dc->current_context->stream_count)
856 for (i = 0; i < dc->current_context->stream_count; i++) {
857 if (&dc->current_context->streams[i]->public != &context->streams[i]->public)
864 static bool streams_changed(
866 const struct dc_stream *streams[],
867 uint8_t stream_count)
871 if (stream_count != dc->current_context->stream_count)
874 for (i = 0; i < dc->current_context->stream_count; i++) {
875 if (&dc->current_context->streams[i]->public != streams[i])
882 bool dc_enable_stereo(
884 struct validate_context *context,
885 const struct dc_stream *streams[],
886 uint8_t stream_count)
890 struct pipe_ctx *pipe;
891 struct core_dc *core_dc = DC_TO_CORE(dc);
894 struct compressor *fbc_compressor = core_dc->fbc_compressor;
897 for (i = 0; i < MAX_PIPES; i++) {
899 pipe = &context->res_ctx.pipe_ctx[i];
901 pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
902 for (j = 0 ; pipe && j < stream_count; j++) {
903 if (streams[j] && streams[j] == &pipe->stream->public &&
904 core_dc->hwss.setup_stereo)
905 core_dc->hwss.setup_stereo(pipe, core_dc);
910 if (fbc_compressor != NULL &&
911 fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
913 fbc_compressor->funcs->disable_fbc(fbc_compressor);
921 * Applies given context to HW and copy it into current context.
922 * It's up to the user to release the src context afterwards.
924 static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context)
926 struct core_dc *core_dc = DC_TO_CORE(dc);
927 struct dc_bios *dcb = core_dc->ctx->dc_bios;
928 enum dc_status result = DC_ERROR_UNEXPECTED;
929 struct pipe_ctx *pipe;
931 const struct dc_stream *dc_streams[MAX_STREAMS] = {0};
933 for (i = 0; i < context->stream_count; i++)
934 dc_streams[i] = &context->streams[i]->public;
936 if (!dcb->funcs->is_accelerated_mode(dcb))
937 core_dc->hwss.enable_accelerated_mode(core_dc);
939 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
941 program_timing_sync(core_dc, context);
943 for (i = 0; i < context->stream_count; i++) {
944 const struct core_sink *sink = context->streams[i]->sink;
946 for (j = 0; j < context->stream_status[i].surface_count; j++) {
947 struct core_surface *surface =
948 DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
950 core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
954 * TODO rework dc_enable_stereo call to work with validation sets?
956 for (k = 0; k < MAX_PIPES; k++) {
957 pipe = &context->res_ctx.pipe_ctx[k];
959 for (l = 0 ; pipe && l < context->stream_count; l++) {
960 if (context->streams[l] &&
961 context->streams[l] == pipe->stream &&
962 core_dc->hwss.setup_stereo)
963 core_dc->hwss.setup_stereo(pipe, core_dc);
968 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
969 context->streams[i]->public.timing.h_addressable,
970 context->streams[i]->public.timing.v_addressable,
971 context->streams[i]->public.timing.h_total,
972 context->streams[i]->public.timing.v_total,
973 context->streams[i]->public.timing.pix_clk_khz);
976 dc_enable_stereo(dc, context, dc_streams, context->stream_count);
978 dc_release_validate_context(core_dc->current_context);
980 core_dc->current_context = context;
982 dc_retain_validate_context(core_dc->current_context);
984 return (result == DC_OK);
987 bool dc_commit_context(struct dc *dc, struct validate_context *context)
989 enum dc_status result = DC_ERROR_UNEXPECTED;
990 struct core_dc *core_dc = DC_TO_CORE(dc);
993 if (false == context_changed(core_dc, context))
996 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
997 __func__, context->stream_count);
999 for (i = 0; i < context->stream_count; i++) {
1000 const struct dc_stream *stream = &context->streams[i]->public;
1002 dc_stream_log(stream,
1003 core_dc->ctx->logger,
1007 result = dc_commit_context_no_check(dc, context);
1009 return (result == DC_OK);
1013 bool dc_commit_streams(
1015 const struct dc_stream *streams[],
1016 uint8_t stream_count)
1018 struct core_dc *core_dc = DC_TO_CORE(dc);
1019 enum dc_status result = DC_ERROR_UNEXPECTED;
1020 struct validate_context *context;
1021 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
1024 if (false == streams_changed(core_dc, streams, stream_count))
1027 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
1028 __func__, stream_count);
1030 for (i = 0; i < stream_count; i++) {
1031 const struct dc_stream *stream = streams[i];
1032 const struct dc_stream_status *status = dc_stream_get_status(stream);
1035 dc_stream_log(stream,
1036 core_dc->ctx->logger,
1039 set[i].stream = stream;
1042 set[i].surface_count = status->surface_count;
1043 for (j = 0; j < status->surface_count; j++)
1044 set[i].surfaces[j] = status->surfaces[j];
1049 context = dm_alloc(sizeof(struct validate_context));
1050 if (context == NULL)
1051 goto context_alloc_fail;
1053 ++context->ref_count;
1055 result = core_dc->res_pool->funcs->validate_with_context(
1056 core_dc, set, stream_count, context, core_dc->current_context);
1057 if (result != DC_OK){
1058 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
1059 "%s: Context validation failed! dc_status:%d\n",
1062 BREAK_TO_DEBUGGER();
1066 result = dc_commit_context_no_check(dc, context);
1069 dc_release_validate_context(context);
1072 return (result == DC_OK);
1075 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1078 struct core_dc *core_dc = DC_TO_CORE(dc);
1079 struct validate_context *context = core_dc->current_context;
1081 post_surface_trace(dc);
1083 for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1084 if (context->res_ctx.pipe_ctx[i].stream == NULL
1085 || context->res_ctx.pipe_ctx[i].surface == NULL)
1086 core_dc->hwss.power_down_front_end(core_dc, i);
1088 /* 3rd param should be true, temp w/a for RV*/
1089 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1090 core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1092 core_dc->hwss.set_bandwidth(core_dc, context, true);
1097 bool dc_commit_surfaces_to_stream(
1099 const struct dc_surface **new_surfaces,
1100 uint8_t new_surface_count,
1101 const struct dc_stream *dc_stream)
1103 struct dc_surface_update updates[MAX_SURFACES];
1104 struct dc_flip_addrs flip_addr[MAX_SURFACES];
1105 struct dc_plane_info plane_info[MAX_SURFACES];
1106 struct dc_scaling_info scaling_info[MAX_SURFACES];
1108 struct dc_stream_update *stream_update =
1109 dm_alloc(sizeof(struct dc_stream_update));
1111 if (!stream_update) {
1112 BREAK_TO_DEBUGGER();
1116 memset(updates, 0, sizeof(updates));
1117 memset(flip_addr, 0, sizeof(flip_addr));
1118 memset(plane_info, 0, sizeof(plane_info));
1119 memset(scaling_info, 0, sizeof(scaling_info));
1121 stream_update->src = dc_stream->src;
1122 stream_update->dst = dc_stream->dst;
1123 stream_update->out_transfer_func = dc_stream->out_transfer_func;
1125 for (i = 0; i < new_surface_count; i++) {
1126 updates[i].surface = new_surfaces[i];
1128 (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1129 updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func;
1130 flip_addr[i].address = new_surfaces[i]->address;
1131 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1132 plane_info[i].color_space = new_surfaces[i]->color_space;
1133 plane_info[i].format = new_surfaces[i]->format;
1134 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1135 plane_info[i].rotation = new_surfaces[i]->rotation;
1136 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1137 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1138 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1139 plane_info[i].visible = new_surfaces[i]->visible;
1140 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1141 plane_info[i].dcc = new_surfaces[i]->dcc;
1142 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1143 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1144 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1145 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1147 updates[i].flip_addr = &flip_addr[i];
1148 updates[i].plane_info = &plane_info[i];
1149 updates[i].scaling_info = &scaling_info[i];
1152 dc_update_surfaces_and_stream(
1156 dc_stream, stream_update);
1158 dc_post_update_surfaces_to_stream(dc);
1160 dm_free(stream_update);
1164 void dc_retain_validate_context(struct validate_context *context)
1166 ASSERT(context->ref_count > 0);
1167 ++context->ref_count;
1170 void dc_release_validate_context(struct validate_context *context)
1172 ASSERT(context->ref_count > 0);
1173 --context->ref_count;
1175 if (context->ref_count == 0) {
1176 dc_resource_validate_ctx_destruct(context);
1181 static bool is_surface_in_context(
1182 const struct validate_context *context,
1183 const struct dc_surface *surface)
1187 for (j = 0; j < MAX_PIPES; j++) {
1188 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1190 if (surface == &pipe_ctx->surface->public) {
1198 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1201 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1202 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1204 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1205 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1206 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1207 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1209 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1210 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1211 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1212 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1214 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1215 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1216 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1219 ASSERT_CRITICAL(false);
1224 static enum surface_update_type get_plane_info_update_type(
1225 const struct dc_surface_update *u,
1228 struct dc_plane_info temp_plane_info;
1229 memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1232 return UPDATE_TYPE_FAST;
1234 temp_plane_info = *u->plane_info;
1236 /* Copy all parameters that will cause a full update
1237 * from current surface, the rest of the parameters
1238 * from provided plane configuration.
1239 * Perform memory compare and special validation
1240 * for those that can cause fast/medium updates
1243 /* Full update parameters */
1244 temp_plane_info.color_space = u->surface->color_space;
1245 temp_plane_info.dcc = u->surface->dcc;
1246 temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1247 temp_plane_info.plane_size = u->surface->plane_size;
1248 temp_plane_info.rotation = u->surface->rotation;
1249 temp_plane_info.stereo_format = u->surface->stereo_format;
1250 temp_plane_info.tiling_info = u->surface->tiling_info;
1252 if (surface_index == 0)
1253 temp_plane_info.visible = u->plane_info->visible;
1255 temp_plane_info.visible = u->surface->visible;
1257 if (memcmp(u->plane_info, &temp_plane_info,
1258 sizeof(struct dc_plane_info)) != 0)
1259 return UPDATE_TYPE_FULL;
1261 if (pixel_format_to_bpp(u->plane_info->format) !=
1262 pixel_format_to_bpp(u->surface->format)) {
1263 return UPDATE_TYPE_FULL;
1265 return UPDATE_TYPE_MED;
1269 static enum surface_update_type get_scaling_info_update_type(
1270 const struct dc_surface_update *u)
1272 if (!u->scaling_info)
1273 return UPDATE_TYPE_FAST;
1275 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1276 || u->scaling_info->src_rect.height != u->surface->src_rect.height
1277 || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1278 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1279 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1280 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1281 return UPDATE_TYPE_FULL;
1283 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1284 || u->scaling_info->src_rect.y != u->surface->src_rect.y
1285 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1286 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1287 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1288 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1289 return UPDATE_TYPE_MED;
1291 return UPDATE_TYPE_FAST;
1294 static enum surface_update_type det_surface_update(
1295 const struct core_dc *dc,
1296 const struct dc_surface_update *u,
1299 const struct validate_context *context = dc->current_context;
1300 enum surface_update_type type = UPDATE_TYPE_FAST;
1301 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1303 if (!is_surface_in_context(context, u->surface))
1304 return UPDATE_TYPE_FULL;
1306 type = get_plane_info_update_type(u, surface_index);
1307 if (overall_type < type)
1308 overall_type = type;
1310 type = get_scaling_info_update_type(u);
1311 if (overall_type < type)
1312 overall_type = type;
1314 if (u->in_transfer_func ||
1315 u->hdr_static_metadata) {
1316 if (overall_type < UPDATE_TYPE_MED)
1317 overall_type = UPDATE_TYPE_MED;
1320 return overall_type;
1323 enum surface_update_type dc_check_update_surfaces_for_stream(
1325 struct dc_surface_update *updates,
1327 struct dc_stream_update *stream_update,
1328 const struct dc_stream_status *stream_status)
1330 struct core_dc *core_dc = DC_TO_CORE(dc);
1332 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1334 if (stream_status == NULL || stream_status->surface_count != surface_count)
1335 return UPDATE_TYPE_FULL;
1338 return UPDATE_TYPE_FULL;
1340 for (i = 0 ; i < surface_count; i++) {
1341 enum surface_update_type type =
1342 det_surface_update(core_dc, &updates[i], i);
1344 if (type == UPDATE_TYPE_FULL)
1347 if (overall_type < type)
1348 overall_type = type;
1351 return overall_type;
1354 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1356 void dc_update_surfaces_and_stream(struct dc *dc,
1357 struct dc_surface_update *srf_updates, int surface_count,
1358 const struct dc_stream *dc_stream,
1359 struct dc_stream_update *stream_update)
1361 struct core_dc *core_dc = DC_TO_CORE(dc);
1362 struct validate_context *context;
1364 enum surface_update_type update_type;
1365 const struct dc_stream_status *stream_status;
1366 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1367 struct dc_context *dc_ctx = core_dc->ctx;
1369 stream_status = dc_stream_get_status(dc_stream);
1370 ASSERT(stream_status);
1372 return; /* Cannot commit surface to stream that is not committed */
1375 if (srf_updates->flip_addr) {
1376 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1380 context = core_dc->current_context;
1382 /* update current stream with the new updates */
1383 if (stream_update) {
1384 if ((stream_update->src.height != 0) &&
1385 (stream_update->src.width != 0))
1386 stream->public.src = stream_update->src;
1388 if ((stream_update->dst.height != 0) &&
1389 (stream_update->dst.width != 0))
1390 stream->public.dst = stream_update->dst;
1392 if (stream_update->out_transfer_func &&
1393 stream_update->out_transfer_func !=
1394 dc_stream->out_transfer_func) {
1395 if (dc_stream->out_transfer_func != NULL)
1396 dc_transfer_func_release(dc_stream->out_transfer_func);
1397 dc_transfer_func_retain(stream_update->out_transfer_func);
1398 stream->public.out_transfer_func =
1399 stream_update->out_transfer_func;
1403 /* do not perform surface update if surface has invalid dimensions
1404 * (all zero) and no scaling_info is provided
1406 if (surface_count > 0 &&
1407 srf_updates->surface->src_rect.width == 0 &&
1408 srf_updates->surface->src_rect.height == 0 &&
1409 srf_updates->surface->dst_rect.width == 0 &&
1410 srf_updates->surface->dst_rect.height == 0 &&
1411 !srf_updates->scaling_info) {
1416 update_type = dc_check_update_surfaces_for_stream(
1417 dc, srf_updates, surface_count, stream_update, stream_status);
1419 if (update_type >= update_surface_trace_level)
1420 update_surface_trace(dc, srf_updates, surface_count);
1422 if (update_type >= UPDATE_TYPE_FULL) {
1423 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1425 for (i = 0; i < surface_count; i++)
1426 new_surfaces[i] = srf_updates[i].surface;
1428 /* initialize scratch memory for building context */
1429 context = dm_alloc(sizeof(*context));
1430 if (context == NULL)
1431 goto context_alloc_fail;
1433 ++context->ref_count;
1435 dc_resource_validate_ctx_copy_construct(
1436 core_dc->current_context, context);
1438 /* add surface to context */
1439 if (!resource_attach_surfaces_to_context(
1440 new_surfaces, surface_count, dc_stream,
1441 context, core_dc->res_pool)) {
1442 BREAK_TO_DEBUGGER();
1447 /* save update parameters into surface */
1448 for (i = 0; i < surface_count; i++) {
1449 struct core_surface *surface =
1450 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1452 if (srf_updates[i].flip_addr) {
1453 surface->public.address = srf_updates[i].flip_addr->address;
1454 surface->public.flip_immediate =
1455 srf_updates[i].flip_addr->flip_immediate;
1458 if (srf_updates[i].scaling_info) {
1459 surface->public.scaling_quality =
1460 srf_updates[i].scaling_info->scaling_quality;
1461 surface->public.dst_rect =
1462 srf_updates[i].scaling_info->dst_rect;
1463 surface->public.src_rect =
1464 srf_updates[i].scaling_info->src_rect;
1465 surface->public.clip_rect =
1466 srf_updates[i].scaling_info->clip_rect;
1469 if (srf_updates[i].plane_info) {
1470 surface->public.color_space =
1471 srf_updates[i].plane_info->color_space;
1472 surface->public.format =
1473 srf_updates[i].plane_info->format;
1474 surface->public.plane_size =
1475 srf_updates[i].plane_info->plane_size;
1476 surface->public.rotation =
1477 srf_updates[i].plane_info->rotation;
1478 surface->public.horizontal_mirror =
1479 srf_updates[i].plane_info->horizontal_mirror;
1480 surface->public.stereo_format =
1481 srf_updates[i].plane_info->stereo_format;
1482 surface->public.tiling_info =
1483 srf_updates[i].plane_info->tiling_info;
1484 surface->public.visible =
1485 srf_updates[i].plane_info->visible;
1486 surface->public.per_pixel_alpha =
1487 srf_updates[i].plane_info->per_pixel_alpha;
1488 surface->public.dcc =
1489 srf_updates[i].plane_info->dcc;
1492 if (update_type >= UPDATE_TYPE_MED) {
1493 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1494 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1496 if (pipe_ctx->surface != surface)
1499 resource_build_scaling_params(pipe_ctx);
1503 if (srf_updates[i].gamma &&
1504 srf_updates[i].gamma != surface->public.gamma_correction) {
1505 if (surface->public.gamma_correction != NULL)
1506 dc_gamma_release(&surface->public.
1509 dc_gamma_retain(srf_updates[i].gamma);
1510 surface->public.gamma_correction =
1511 srf_updates[i].gamma;
1514 if (srf_updates[i].in_transfer_func &&
1515 srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1516 if (surface->public.in_transfer_func != NULL)
1517 dc_transfer_func_release(
1521 dc_transfer_func_retain(
1522 srf_updates[i].in_transfer_func);
1523 surface->public.in_transfer_func =
1524 srf_updates[i].in_transfer_func;
1527 if (srf_updates[i].hdr_static_metadata)
1528 surface->public.hdr_static_ctx =
1529 *(srf_updates[i].hdr_static_metadata);
1532 if (update_type == UPDATE_TYPE_FULL) {
1533 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1534 BREAK_TO_DEBUGGER();
1537 core_dc->hwss.set_bandwidth(core_dc, context, false);
1538 context_clock_trace(dc, context);
1542 if (surface_count == 0)
1543 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1545 /* Lock pipes for provided surfaces, or all active if full update*/
1546 for (i = 0; i < surface_count; i++) {
1547 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1549 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1550 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1552 if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1554 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1557 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1558 core_dc->hwss.pipe_control_lock(
1564 if (update_type == UPDATE_TYPE_FULL)
1569 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1570 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1571 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1572 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1573 struct dc_cursor_position position = { 0 };
1575 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1578 if (!pipe_ctx->top_pipe)
1579 core_dc->hwss.apply_ctx_for_surface(
1580 core_dc, pipe_ctx->surface, context);
1582 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1583 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1585 if (is_new_pipe_surface) {
1586 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1587 core_dc->hwss.set_input_transfer_func(
1588 pipe_ctx, pipe_ctx->surface);
1589 core_dc->hwss.set_output_transfer_func(
1590 pipe_ctx, pipe_ctx->stream);
1594 if (update_type > UPDATE_TYPE_FAST)
1595 context_timing_trace(dc, &context->res_ctx);
1597 /* Perform requested Updates */
1598 for (i = 0; i < surface_count; i++) {
1599 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1601 if (update_type == UPDATE_TYPE_MED)
1602 core_dc->hwss.apply_ctx_for_surface(
1603 core_dc, surface, context);
1605 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1606 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1608 if (pipe_ctx->surface != surface)
1611 if (srf_updates[i].flip_addr)
1612 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1614 if (update_type == UPDATE_TYPE_FAST)
1617 if (srf_updates[i].in_transfer_func)
1618 core_dc->hwss.set_input_transfer_func(
1619 pipe_ctx, pipe_ctx->surface);
1621 if (stream_update != NULL &&
1622 stream_update->out_transfer_func != NULL) {
1623 core_dc->hwss.set_output_transfer_func(
1624 pipe_ctx, pipe_ctx->stream);
1627 if (srf_updates[i].hdr_static_metadata) {
1628 resource_build_info_frame(pipe_ctx);
1629 core_dc->hwss.update_info_frame(pipe_ctx);
1635 for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1636 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1638 for (j = 0; j < surface_count; j++) {
1639 if (update_type != UPDATE_TYPE_FULL &&
1640 srf_updates[j].surface != &pipe_ctx->surface->public)
1642 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1645 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1646 core_dc->hwss.pipe_control_lock(
1655 if (core_dc->current_context != context) {
1656 dc_release_validate_context(core_dc->current_context);
1657 core_dc->current_context = context;
1662 dc_release_validate_context(context);
1665 DC_ERROR("Failed to allocate new validate context!\n");
1668 uint8_t dc_get_current_stream_count(const struct dc *dc)
1670 struct core_dc *core_dc = DC_TO_CORE(dc);
1671 return core_dc->current_context->stream_count;
1674 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1676 struct core_dc *core_dc = DC_TO_CORE(dc);
1677 if (i < core_dc->current_context->stream_count)
1678 return &(core_dc->current_context->streams[i]->public);
1682 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1684 struct core_dc *core_dc = DC_TO_CORE(dc);
1685 return &core_dc->links[link_index]->public;
1688 const struct graphics_object_id dc_get_link_id_at_index(
1689 struct dc *dc, uint32_t link_index)
1691 struct core_dc *core_dc = DC_TO_CORE(dc);
1692 return core_dc->links[link_index]->link_id;
1695 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1696 struct dc *dc, uint32_t link_index)
1698 struct core_dc *core_dc = DC_TO_CORE(dc);
1699 return core_dc->links[link_index]->public.irq_source_hpd;
1702 const struct audio **dc_get_audios(struct dc *dc)
1704 struct core_dc *core_dc = DC_TO_CORE(dc);
1705 return (const struct audio **)core_dc->res_pool->audios;
1708 enum dc_irq_source dc_interrupt_to_irq_source(
1713 struct core_dc *core_dc = DC_TO_CORE(dc);
1714 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1717 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1719 struct core_dc *core_dc;
1723 core_dc = DC_TO_CORE(dc);
1725 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1728 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1730 struct core_dc *core_dc = DC_TO_CORE(dc);
1731 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1734 void dc_set_power_state(
1736 enum dc_acpi_cm_power_state power_state)
1738 struct core_dc *core_dc = DC_TO_CORE(dc);
1741 switch (power_state) {
1742 case DC_ACPI_CM_POWER_STATE_D0:
1743 core_dc->hwss.init_hw(core_dc);
1747 core_dc->hwss.power_down(core_dc);
1749 /* Zero out the current context so that on resume we start with
1750 * clean state, and dc hw programming optimizations will not
1751 * cause any trouble.
1754 /* Preserve refcount */
1755 ref_count = core_dc->current_context->ref_count;
1756 dc_resource_validate_ctx_destruct(core_dc->current_context);
1757 memset(core_dc->current_context, 0,
1758 sizeof(*core_dc->current_context));
1759 core_dc->current_context->ref_count = ref_count;
1766 void dc_resume(const struct dc *dc)
1768 struct core_dc *core_dc = DC_TO_CORE(dc);
1772 for (i = 0; i < core_dc->link_count; i++)
1773 core_link_resume(core_dc->links[i]);
1776 bool dc_read_aux_dpcd(
1778 uint32_t link_index,
1783 struct core_dc *core_dc = DC_TO_CORE(dc);
1785 struct core_link *link = core_dc->links[link_index];
1786 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1793 return r == DDC_RESULT_SUCESSFULL;
1796 bool dc_write_aux_dpcd(
1798 uint32_t link_index,
1800 const uint8_t *data,
1803 struct core_dc *core_dc = DC_TO_CORE(dc);
1804 struct core_link *link = core_dc->links[link_index];
1806 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1813 return r == DDC_RESULT_SUCESSFULL;
1816 bool dc_read_aux_i2c(
1818 uint32_t link_index,
1819 enum i2c_mot_mode mot,
1824 struct core_dc *core_dc = DC_TO_CORE(dc);
1826 struct core_link *link = core_dc->links[link_index];
1827 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1834 return r == DDC_RESULT_SUCESSFULL;
1837 bool dc_write_aux_i2c(
1839 uint32_t link_index,
1840 enum i2c_mot_mode mot,
1842 const uint8_t *data,
1845 struct core_dc *core_dc = DC_TO_CORE(dc);
1846 struct core_link *link = core_dc->links[link_index];
1848 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1855 return r == DDC_RESULT_SUCESSFULL;
1858 bool dc_query_ddc_data(
1860 uint32_t link_index,
1863 uint32_t write_size,
1865 uint32_t read_size) {
1867 struct core_dc *core_dc = DC_TO_CORE(dc);
1869 struct core_link *link = core_dc->links[link_index];
1871 bool result = dal_ddc_service_query_ddc_data(
1884 uint32_t link_index,
1885 struct i2c_command *cmd)
1887 struct core_dc *core_dc = DC_TO_CORE(dc);
1889 struct core_link *link = core_dc->links[link_index];
1890 struct ddc_service *ddc = link->public.ddc;
1892 return dal_i2caux_submit_i2c_command(
1898 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1900 struct dc_link *dc_link = &core_link->public;
1902 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1903 BREAK_TO_DEBUGGER();
1907 dc_sink_retain(sink);
1909 dc_link->remote_sinks[dc_link->sink_count] = sink;
1910 dc_link->sink_count++;
1915 struct dc_sink *dc_link_add_remote_sink(
1916 const struct dc_link *link,
1917 const uint8_t *edid,
1919 struct dc_sink_init_data *init_data)
1921 struct dc_sink *dc_sink;
1922 enum dc_edid_status edid_status;
1923 struct core_link *core_link = DC_LINK_TO_LINK(link);
1925 if (len > MAX_EDID_BUFFER_SIZE) {
1926 dm_error("Max EDID buffer size breached!\n");
1931 BREAK_TO_DEBUGGER();
1935 if (!init_data->link) {
1936 BREAK_TO_DEBUGGER();
1940 dc_sink = dc_sink_create(init_data);
1945 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1946 dc_sink->dc_edid.length = len;
1948 if (!link_add_remote_sink_helper(
1953 edid_status = dm_helpers_parse_edid_caps(
1956 &dc_sink->edid_caps);
1958 if (edid_status != EDID_OK)
1963 dc_link_remove_remote_sink(link, dc_sink);
1965 dc_sink_release(dc_sink);
1969 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1971 struct core_link *core_link = DC_LINK_TO_LINK(link);
1972 struct dc_link *dc_link = &core_link->public;
1974 dc_link->local_sink = sink;
1977 dc_link->type = dc_connection_none;
1979 dc_link->type = dc_connection_single;
1983 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1986 struct core_link *core_link = DC_LINK_TO_LINK(link);
1987 struct dc_link *dc_link = &core_link->public;
1989 if (!link->sink_count) {
1990 BREAK_TO_DEBUGGER();
1994 for (i = 0; i < dc_link->sink_count; i++) {
1995 if (dc_link->remote_sinks[i] == sink) {
1996 dc_sink_release(sink);
1997 dc_link->remote_sinks[i] = NULL;
1999 /* shrink array to remove empty place */
2000 while (i < dc_link->sink_count - 1) {
2001 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
2004 dc_link->remote_sinks[i] = NULL;
2005 dc_link->sink_count--;
2011 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
2014 struct core_dc *core_dc = DC_TO_CORE(dc);
2015 struct mem_input *mi = NULL;
2017 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
2018 if (core_dc->res_pool->mis[i] != NULL) {
2019 mi = core_dc->res_pool->mis[i];
2024 dm_error("no mem_input!\n");
2028 if (mi->funcs->mem_input_update_dchub)
2029 mi->funcs->mem_input_update_dchub(mi, dh_data);
2031 ASSERT(mi->funcs->mem_input_update_dchub);
2038 void dc_log_hw_state(struct dc *dc)
2040 struct core_dc *core_dc = DC_TO_CORE(dc);
2042 if (core_dc->hwss.log_hw_state)
2043 core_dc->hwss.log_hw_state(core_dc);