drm/amd/display: plumbing to allow easy print of HW state for DTN
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / display / dc / core / dc.c
1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  */
24
25 #include "dm_services.h"
26
27 #include "dc.h"
28
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
32
33 #include "resource.h"
34
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
37
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
44
45 #include "link_hwss.h"
46 #include "link_encoder.h"
47
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
51
52 /*******************************************************************************
53  * Private functions
54  ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
56 {
57         uint32_t i;
58
59         for (i = 0; i < dc->link_count; i++) {
60                 if (NULL != dc->links[i])
61                         link_destroy(&dc->links[i]);
62         }
63 }
64
65 static bool create_links(
66                 struct core_dc *dc,
67                 uint32_t num_virtual_links)
68 {
69         int i;
70         int connectors_num;
71         struct dc_bios *bios = dc->ctx->dc_bios;
72
73         dc->link_count = 0;
74
75         connectors_num = bios->funcs->get_connectors_number(bios);
76
77         if (connectors_num > ENUM_ID_COUNT) {
78                 dm_error(
79                         "DC: Number of connectors %d exceeds maximum of %d!\n",
80                         connectors_num,
81                         ENUM_ID_COUNT);
82                 return false;
83         }
84
85         if (connectors_num == 0 && num_virtual_links == 0) {
86                 dm_error("DC: Number of connectors is zero!\n");
87         }
88
89         dm_output_to_console(
90                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
91                 __func__,
92                 connectors_num,
93                 num_virtual_links);
94
95         for (i = 0; i < connectors_num; i++) {
96                 struct link_init_data link_init_params = {0};
97                 struct core_link *link;
98
99                 link_init_params.ctx = dc->ctx;
100                 /* next BIOS object table connector */
101                 link_init_params.connector_index = i;
102                 link_init_params.link_index = dc->link_count;
103                 link_init_params.dc = dc;
104                 link = link_create(&link_init_params);
105
106                 if (link) {
107                         dc->links[dc->link_count] = link;
108                         link->dc = dc;
109                         ++dc->link_count;
110                 }
111         }
112
113         for (i = 0; i < num_virtual_links; i++) {
114                 struct core_link *link = dm_alloc(sizeof(*link));
115                 struct encoder_init_data enc_init = {0};
116
117                 if (link == NULL) {
118                         BREAK_TO_DEBUGGER();
119                         goto failed_alloc;
120                 }
121
122                 link->ctx = dc->ctx;
123                 link->dc = dc;
124                 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127                 link->link_id.enum_id = ENUM_ID_1;
128                 link->link_enc = dm_alloc(sizeof(*link->link_enc));
129
130                 enc_init.ctx = dc->ctx;
131                 enc_init.channel = CHANNEL_ID_UNKNOWN;
132                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134                 enc_init.connector = link->link_id;
135                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137                 enc_init.encoder.enum_id = ENUM_ID_1;
138                 virtual_link_encoder_construct(link->link_enc, &enc_init);
139
140                 link->public.link_index = dc->link_count;
141                 dc->links[dc->link_count] = link;
142                 dc->link_count++;
143         }
144
145         return true;
146
147 failed_alloc:
148         return false;
149 }
150
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152                 const struct dc_stream **stream, int num_streams,
153                 int vmin, int vmax)
154 {
155         /* TODO: Support multiple streams */
156         struct core_dc *core_dc = DC_TO_CORE(dc);
157         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
158         int i = 0;
159         bool ret = false;
160
161         for (i = 0; i < MAX_PIPES; i++) {
162                 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
163
164                 if (pipe->stream == core_stream && pipe->stream_enc) {
165                         core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
166
167                         /* build and update the info frame */
168                         resource_build_info_frame(pipe);
169                         core_dc->hwss.update_info_frame(pipe);
170
171                         ret = true;
172                 }
173         }
174         return ret;
175 }
176
177 static bool stream_get_crtc_position(struct dc *dc,
178                 const struct dc_stream **stream, int num_streams,
179                 unsigned int *v_pos, unsigned int *nom_v_pos)
180 {
181         /* TODO: Support multiple streams */
182         struct core_dc *core_dc = DC_TO_CORE(dc);
183         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
184         int i = 0;
185         bool ret = false;
186         struct crtc_position position;
187
188         for (i = 0; i < MAX_PIPES; i++) {
189                 struct pipe_ctx *pipe =
190                                 &core_dc->current_context->res_ctx.pipe_ctx[i];
191
192                 if (pipe->stream == core_stream && pipe->stream_enc) {
193                         core_dc->hwss.get_position(&pipe, 1, &position);
194
195                         *v_pos = position.vertical_count;
196                         *nom_v_pos = position.nominal_vcount;
197                         ret = true;
198                 }
199         }
200         return ret;
201 }
202
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
204 {
205         struct core_dc *core_dc = DC_TO_CORE(dc);
206         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
207         int i = 0;
208         bool ret = false;
209         struct pipe_ctx *pipes;
210
211         for (i = 0; i < MAX_PIPES; i++) {
212                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
213                                 == core_stream) {
214
215                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216                         core_dc->hwss.program_gamut_remap(pipes);
217                         ret = true;
218                 }
219         }
220
221         return ret;
222 }
223
224 static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
225 {
226         struct core_dc *core_dc = DC_TO_CORE(dc);
227         struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
228         int i = 0;
229         bool ret = false;
230         struct pipe_ctx *pipes;
231
232         for (i = 0; i < MAX_PIPES; i++) {
233                 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
234                                 == core_stream) {
235
236                         pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
237                         core_dc->hwss.program_csc_matrix(pipes,
238                         core_stream->public.output_color_space,
239                         core_stream->public.csc_color_matrix.matrix);
240                         ret = true;
241                 }
242         }
243
244         return ret;
245 }
246
247 static void set_static_screen_events(struct dc *dc,
248                 const struct dc_stream **stream,
249                 int num_streams,
250                 const struct dc_static_screen_events *events)
251 {
252         struct core_dc *core_dc = DC_TO_CORE(dc);
253         int i = 0;
254         int j = 0;
255         struct pipe_ctx *pipes_affected[MAX_PIPES];
256         int num_pipes_affected = 0;
257
258         for (i = 0; i < num_streams; i++) {
259                 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
260
261                 for (j = 0; j < MAX_PIPES; j++) {
262                         if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
263                                         == core_stream) {
264                                 pipes_affected[num_pipes_affected++] =
265                                                 &core_dc->current_context->res_ctx.pipe_ctx[j];
266                         }
267                 }
268         }
269
270         core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
271 }
272
273 static void set_drive_settings(struct dc *dc,
274                 struct link_training_settings *lt_settings,
275                 const struct dc_link *link)
276 {
277         struct core_dc *core_dc = DC_TO_CORE(dc);
278         int i;
279
280         for (i = 0; i < core_dc->link_count; i++) {
281                 if (&core_dc->links[i]->public == link)
282                         break;
283         }
284
285         if (i >= core_dc->link_count)
286                 ASSERT_CRITICAL(false);
287
288         dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
289 }
290
291 static void perform_link_training(struct dc *dc,
292                 struct dc_link_settings *link_setting,
293                 bool skip_video_pattern)
294 {
295         struct core_dc *core_dc = DC_TO_CORE(dc);
296         int i;
297
298         for (i = 0; i < core_dc->link_count; i++)
299                 dc_link_dp_perform_link_training(
300                         &core_dc->links[i]->public,
301                         link_setting,
302                         skip_video_pattern);
303 }
304
305 static void set_preferred_link_settings(struct dc *dc,
306                 struct dc_link_settings *link_setting,
307                 const struct dc_link *link)
308 {
309         struct core_link *core_link = DC_LINK_TO_CORE(link);
310
311         core_link->public.verified_link_cap.lane_count =
312                                 link_setting->lane_count;
313         core_link->public.verified_link_cap.link_rate =
314                                 link_setting->link_rate;
315         dp_retrain_link_dp_test(core_link, link_setting, false);
316 }
317
318 static void enable_hpd(const struct dc_link *link)
319 {
320         dc_link_dp_enable_hpd(link);
321 }
322
323 static void disable_hpd(const struct dc_link *link)
324 {
325         dc_link_dp_disable_hpd(link);
326 }
327
328
329 static void set_test_pattern(
330                 const struct dc_link *link,
331                 enum dp_test_pattern test_pattern,
332                 const struct link_training_settings *p_link_settings,
333                 const unsigned char *p_custom_pattern,
334                 unsigned int cust_pattern_size)
335 {
336         if (link != NULL)
337                 dc_link_dp_set_test_pattern(
338                         link,
339                         test_pattern,
340                         p_link_settings,
341                         p_custom_pattern,
342                         cust_pattern_size);
343 }
344
345 void set_dither_option(const struct dc_stream *dc_stream,
346                 enum dc_dither_option option)
347 {
348         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
349         struct bit_depth_reduction_params params;
350         struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
351         struct pipe_ctx *pipes =
352                         core_link->dc->current_context->res_ctx.pipe_ctx;
353
354         memset(&params, 0, sizeof(params));
355         if (!stream)
356                 return;
357         if (option > DITHER_OPTION_MAX)
358                 return;
359         if (option == DITHER_OPTION_DEFAULT) {
360                 switch (stream->public.timing.display_color_depth) {
361                 case COLOR_DEPTH_666:
362                         stream->public.dither_option = DITHER_OPTION_SPATIAL6;
363                         break;
364                 case COLOR_DEPTH_888:
365                         stream->public.dither_option = DITHER_OPTION_SPATIAL8;
366                         break;
367                 case COLOR_DEPTH_101010:
368                         stream->public.dither_option = DITHER_OPTION_SPATIAL10;
369                         break;
370                 default:
371                         option = DITHER_OPTION_DISABLE;
372                 }
373         } else {
374                 stream->public.dither_option = option;
375         }
376         resource_build_bit_depth_reduction_params(stream,
377                                 &params);
378         stream->bit_depth_params = params;
379         pipes->opp->funcs->
380                 opp_program_bit_depth_reduction(pipes->opp, &params);
381 }
382
383 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
384 {
385         if (core_dc->hwss.set_drr != NULL) {
386                 core_dc->public.stream_funcs.adjust_vmin_vmax =
387                                 stream_adjust_vmin_vmax;
388         }
389
390         core_dc->public.stream_funcs.set_static_screen_events =
391                         set_static_screen_events;
392
393         core_dc->public.stream_funcs.get_crtc_position =
394                         stream_get_crtc_position;
395
396         core_dc->public.stream_funcs.set_gamut_remap =
397                         set_gamut_remap;
398
399         core_dc->public.stream_funcs.program_csc_matrix =
400                         program_csc_matrix;
401
402         core_dc->public.stream_funcs.set_dither_option =
403                         set_dither_option;
404
405         core_dc->public.link_funcs.set_drive_settings =
406                         set_drive_settings;
407
408         core_dc->public.link_funcs.perform_link_training =
409                         perform_link_training;
410
411         core_dc->public.link_funcs.set_preferred_link_settings =
412                         set_preferred_link_settings;
413
414         core_dc->public.link_funcs.enable_hpd =
415                         enable_hpd;
416
417         core_dc->public.link_funcs.disable_hpd =
418                         disable_hpd;
419
420         core_dc->public.link_funcs.set_test_pattern =
421                         set_test_pattern;
422 }
423
424 static void destruct(struct core_dc *dc)
425 {
426         dc_release_validate_context(dc->current_context);
427         dc->current_context = NULL;
428
429         destroy_links(dc);
430
431         dc_destroy_resource_pool(dc);
432
433         if (dc->ctx->gpio_service)
434                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
435
436         if (dc->ctx->i2caux)
437                 dal_i2caux_destroy(&dc->ctx->i2caux);
438
439         if (dc->ctx->created_bios)
440                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
441
442         if (dc->ctx->logger)
443                 dal_logger_destroy(&dc->ctx->logger);
444
445         dm_free(dc->ctx);
446         dc->ctx = NULL;
447 }
448
449 static bool construct(struct core_dc *dc,
450                 const struct dc_init_data *init_params)
451 {
452         struct dal_logger *logger;
453         struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
454         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
455
456         if (!dc_ctx) {
457                 dm_error("%s: failed to create ctx\n", __func__);
458                 goto ctx_fail;
459         }
460
461         dc->current_context = dm_alloc(sizeof(*dc->current_context));
462
463         if (!dc->current_context) {
464                 dm_error("%s: failed to create validate ctx\n", __func__);
465                 goto val_ctx_fail;
466         }
467
468         dc->current_context->ref_count++;
469
470         dc_ctx->cgs_device = init_params->cgs_device;
471         dc_ctx->driver_context = init_params->driver;
472         dc_ctx->dc = &dc->public;
473         dc_ctx->asic_id = init_params->asic_id;
474
475         /* Create logger */
476         logger = dal_logger_create(dc_ctx);
477
478         if (!logger) {
479                 /* can *not* call logger. call base driver 'print error' */
480                 dm_error("%s: failed to create Logger!\n", __func__);
481                 goto logger_fail;
482         }
483         dc_ctx->logger = logger;
484         dc->ctx = dc_ctx;
485         dc->ctx->dce_environment = init_params->dce_environment;
486
487         dc_version = resource_parse_asic_id(init_params->asic_id);
488         dc->ctx->dce_version = dc_version;
489
490         /* Resource should construct all asic specific resources.
491          * This should be the only place where we need to parse the asic id
492          */
493         if (init_params->vbios_override)
494                 dc_ctx->dc_bios = init_params->vbios_override;
495         else {
496                 /* Create BIOS parser */
497                 struct bp_init_data bp_init_data;
498
499                 bp_init_data.ctx = dc_ctx;
500                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
501
502                 dc_ctx->dc_bios = dal_bios_parser_create(
503                                 &bp_init_data, dc_version);
504
505                 if (!dc_ctx->dc_bios) {
506                         ASSERT_CRITICAL(false);
507                         goto bios_fail;
508                 }
509
510                 dc_ctx->created_bios = true;
511                 }
512
513         /* Create I2C AUX */
514         dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
515
516         if (!dc_ctx->i2caux) {
517                 ASSERT_CRITICAL(false);
518                 goto failed_to_create_i2caux;
519         }
520
521         /* Create GPIO service */
522         dc_ctx->gpio_service = dal_gpio_service_create(
523                         dc_version,
524                         dc_ctx->dce_environment,
525                         dc_ctx);
526
527         if (!dc_ctx->gpio_service) {
528                 ASSERT_CRITICAL(false);
529                 goto gpio_fail;
530         }
531
532         dc->res_pool = dc_create_resource_pool(
533                         dc,
534                         init_params->num_virtual_links,
535                         dc_version,
536                         init_params->asic_id);
537         if (!dc->res_pool)
538                 goto create_resource_fail;
539
540         if (!create_links(dc, init_params->num_virtual_links))
541                 goto create_links_fail;
542
543         allocate_dc_stream_funcs(dc);
544
545         return true;
546
547         /**** error handling here ****/
548 create_links_fail:
549 create_resource_fail:
550 gpio_fail:
551 failed_to_create_i2caux:
552 bios_fail:
553 logger_fail:
554 val_ctx_fail:
555 ctx_fail:
556         destruct(dc);
557         return false;
558 }
559
560 /*
561 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
562 {
563         fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
564         unsigned int pixDurationInPico = round(pixel_duration);
565
566         DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
567
568         arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
569         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
570         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
571
572         arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
573         arb_control.bits.PIXEL_DURATION = pixDurationInPico;
574         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
575
576         WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
577         WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
578
579         WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
580         WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
581 }
582 */
583
584 /*******************************************************************************
585  * Public functions
586  ******************************************************************************/
587
588 struct dc *dc_create(const struct dc_init_data *init_params)
589  {
590         struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
591         unsigned int full_pipe_count;
592
593         if (NULL == core_dc)
594                 goto alloc_fail;
595
596         if (false == construct(core_dc, init_params))
597                 goto construct_fail;
598
599         /*TODO: separate HW and SW initialization*/
600         core_dc->hwss.init_hw(core_dc);
601
602         full_pipe_count = core_dc->res_pool->pipe_count;
603         if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
604                 full_pipe_count--;
605         core_dc->public.caps.max_streams = min(
606                         full_pipe_count,
607                         core_dc->res_pool->stream_enc_count);
608
609         core_dc->public.caps.max_links = core_dc->link_count;
610         core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
611
612         core_dc->public.config = init_params->flags;
613
614         dm_logger_write(core_dc->ctx->logger, LOG_DC,
615                         "Display Core initialized\n");
616
617
618         /* TODO: missing feature to be enabled */
619         core_dc->public.debug.disable_dfs_bypass = true;
620
621         return &core_dc->public;
622
623 construct_fail:
624         dm_free(core_dc);
625
626 alloc_fail:
627         return NULL;
628 }
629
630 void dc_destroy(struct dc **dc)
631 {
632         struct core_dc *core_dc = DC_TO_CORE(*dc);
633         destruct(core_dc);
634         dm_free(core_dc);
635         *dc = NULL;
636 }
637
638 static bool is_validation_required(
639                 const struct core_dc *dc,
640                 const struct dc_validation_set set[],
641                 int set_count)
642 {
643         const struct validate_context *context = dc->current_context;
644         int i, j;
645
646         if (context->stream_count != set_count)
647                 return true;
648
649         for (i = 0; i < set_count; i++) {
650
651                 if (set[i].surface_count != context->stream_status[i].surface_count)
652                         return true;
653                 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
654                         return true;
655
656                 for (j = 0; j < set[i].surface_count; j++) {
657                         struct dc_surface temp_surf;
658                         memset(&temp_surf, 0, sizeof(temp_surf));
659
660                         temp_surf = *context->stream_status[i].surfaces[j];
661                         temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
662                         temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
663                         temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
664
665                         if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
666                                 return true;
667                 }
668         }
669
670         return false;
671 }
672
673 struct validate_context *dc_get_validate_context(
674                 const struct dc *dc,
675                 const struct dc_validation_set set[],
676                 uint8_t set_count)
677 {
678         struct core_dc *core_dc = DC_TO_CORE(dc);
679         enum dc_status result = DC_ERROR_UNEXPECTED;
680         struct validate_context *context;
681
682         context = dm_alloc(sizeof(struct validate_context));
683         if (context == NULL)
684                 goto context_alloc_fail;
685
686         ++context->ref_count;
687
688         if (!is_validation_required(core_dc, set, set_count)) {
689                 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
690                 return context;
691         }
692
693         result = core_dc->res_pool->funcs->validate_with_context(
694                         core_dc, set, set_count, context, core_dc->current_context);
695
696 context_alloc_fail:
697         if (result != DC_OK) {
698                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
699                                 "%s:resource validation failed, dc_status:%d\n",
700                                 __func__,
701                                 result);
702
703                 dc_release_validate_context(context);
704                 context = NULL;
705         }
706
707         return context;
708
709 }
710
711 bool dc_validate_resources(
712                 const struct dc *dc,
713                 const struct dc_validation_set set[],
714                 uint8_t set_count)
715 {
716         struct core_dc *core_dc = DC_TO_CORE(dc);
717         enum dc_status result = DC_ERROR_UNEXPECTED;
718         struct validate_context *context;
719
720         context = dm_alloc(sizeof(struct validate_context));
721         if (context == NULL)
722                 goto context_alloc_fail;
723
724         ++context->ref_count;
725
726         result = core_dc->res_pool->funcs->validate_with_context(
727                                 core_dc, set, set_count, context, NULL);
728
729 context_alloc_fail:
730         if (result != DC_OK) {
731                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
732                                 "%s:resource validation failed, dc_status:%d\n",
733                                 __func__,
734                                 result);
735         }
736
737         dc_release_validate_context(context);
738         context = NULL;
739
740         return result == DC_OK;
741 }
742
743 bool dc_validate_guaranteed(
744                 const struct dc *dc,
745                 const struct dc_stream *stream)
746 {
747         struct core_dc *core_dc = DC_TO_CORE(dc);
748         enum dc_status result = DC_ERROR_UNEXPECTED;
749         struct validate_context *context;
750
751         context = dm_alloc(sizeof(struct validate_context));
752         if (context == NULL)
753                 goto context_alloc_fail;
754
755         ++context->ref_count;
756
757         result = core_dc->res_pool->funcs->validate_guaranteed(
758                                         core_dc, stream, context);
759
760         dc_release_validate_context(context);
761
762 context_alloc_fail:
763         if (result != DC_OK) {
764                 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
765                         "%s:guaranteed validation failed, dc_status:%d\n",
766                         __func__,
767                         result);
768                 }
769
770         return (result == DC_OK);
771 }
772
773 static void program_timing_sync(
774                 struct core_dc *core_dc,
775                 struct validate_context *ctx)
776 {
777         int i, j;
778         int group_index = 0;
779         int pipe_count = core_dc->res_pool->pipe_count;
780         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
781
782         for (i = 0; i < pipe_count; i++) {
783                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
784                         continue;
785
786                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
787         }
788
789         for (i = 0; i < pipe_count; i++) {
790                 int group_size = 1;
791                 struct pipe_ctx *pipe_set[MAX_PIPES];
792
793                 if (!unsynced_pipes[i])
794                         continue;
795
796                 pipe_set[0] = unsynced_pipes[i];
797                 unsynced_pipes[i] = NULL;
798
799                 /* Add tg to the set, search rest of the tg's for ones with
800                  * same timing, add all tgs with same timing to the group
801                  */
802                 for (j = i + 1; j < pipe_count; j++) {
803                         if (!unsynced_pipes[j])
804                                 continue;
805
806                         if (resource_are_streams_timing_synchronizable(
807                                         unsynced_pipes[j]->stream,
808                                         pipe_set[0]->stream)) {
809                                 pipe_set[group_size] = unsynced_pipes[j];
810                                 unsynced_pipes[j] = NULL;
811                                 group_size++;
812                         }
813                 }
814
815                 /* set first unblanked pipe as master */
816                 for (j = 0; j < group_size; j++) {
817                         struct pipe_ctx *temp;
818
819                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
820                                 if (j == 0)
821                                         break;
822
823                                 temp = pipe_set[0];
824                                 pipe_set[0] = pipe_set[j];
825                                 pipe_set[j] = temp;
826                                 break;
827                         }
828                 }
829
830                 /* remove any other unblanked pipes as they have already been synced */
831                 for (j = j + 1; j < group_size; j++) {
832                         if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
833                                 group_size--;
834                                 pipe_set[j] = pipe_set[group_size];
835                                 j--;
836                         }
837                 }
838
839                 if (group_size > 1) {
840                         core_dc->hwss.enable_timing_synchronization(
841                                 core_dc, group_index, group_size, pipe_set);
842                         group_index++;
843                 }
844         }
845 }
846
847 static bool context_changed(
848                 struct core_dc *dc,
849                 struct validate_context *context)
850 {
851         uint8_t i;
852
853         if (context->stream_count != dc->current_context->stream_count)
854                 return true;
855
856         for (i = 0; i < dc->current_context->stream_count; i++) {
857                 if (&dc->current_context->streams[i]->public != &context->streams[i]->public)
858                         return true;
859         }
860
861         return false;
862 }
863
864 static bool streams_changed(
865                 struct core_dc *dc,
866                 const struct dc_stream *streams[],
867                 uint8_t stream_count)
868 {
869         uint8_t i;
870
871         if (stream_count != dc->current_context->stream_count)
872                 return true;
873
874         for (i = 0; i < dc->current_context->stream_count; i++) {
875                 if (&dc->current_context->streams[i]->public != streams[i])
876                         return true;
877         }
878
879         return false;
880 }
881
882 bool dc_enable_stereo(
883         struct dc *dc,
884         struct validate_context *context,
885         const struct dc_stream *streams[],
886         uint8_t stream_count)
887 {
888         bool ret = true;
889         int i, j;
890         struct pipe_ctx *pipe;
891         struct core_dc *core_dc = DC_TO_CORE(dc);
892
893 #ifdef ENABLE_FBC
894         struct compressor *fbc_compressor = core_dc->fbc_compressor;
895 #endif
896
897         for (i = 0; i < MAX_PIPES; i++) {
898                 if (context != NULL)
899                         pipe = &context->res_ctx.pipe_ctx[i];
900                 else
901                         pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
902                 for (j = 0 ; pipe && j < stream_count; j++)  {
903                         if (streams[j] && streams[j] == &pipe->stream->public &&
904                                 core_dc->hwss.setup_stereo)
905                                 core_dc->hwss.setup_stereo(pipe, core_dc);
906                 }
907         }
908
909 #ifdef ENABLE_FBC
910         if (fbc_compressor != NULL &&
911             fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
912                                                         &pipe->tg->inst))
913                 fbc_compressor->funcs->disable_fbc(fbc_compressor);
914
915 #endif
916         return ret;
917 }
918
919
920 /*
921  * Applies given context to HW and copy it into current context.
922  * It's up to the user to release the src context afterwards.
923  */
924 static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context)
925 {
926         struct core_dc *core_dc = DC_TO_CORE(dc);
927         struct dc_bios *dcb = core_dc->ctx->dc_bios;
928         enum dc_status result = DC_ERROR_UNEXPECTED;
929         struct pipe_ctx *pipe;
930         int i, j, k, l;
931         const struct dc_stream *dc_streams[MAX_STREAMS] = {0};
932
933         for (i = 0; i < context->stream_count; i++)
934                 dc_streams[i] =  &context->streams[i]->public;
935
936         if (!dcb->funcs->is_accelerated_mode(dcb))
937                 core_dc->hwss.enable_accelerated_mode(core_dc);
938
939         result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
940
941         program_timing_sync(core_dc, context);
942
943         for (i = 0; i < context->stream_count; i++) {
944                 const struct core_sink *sink = context->streams[i]->sink;
945
946                 for (j = 0; j < context->stream_status[i].surface_count; j++) {
947                         struct core_surface *surface =
948                                         DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
949
950                         core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
951
952                         /*
953                          * enable stereo
954                          * TODO rework dc_enable_stereo call to work with validation sets?
955                          */
956                         for (k = 0; k < MAX_PIPES; k++) {
957                                 pipe = &context->res_ctx.pipe_ctx[k];
958
959                                 for (l = 0 ; pipe && l < context->stream_count; l++)  {
960                                         if (context->streams[l] &&
961                                             context->streams[l] == pipe->stream &&
962                                             core_dc->hwss.setup_stereo)
963                                                 core_dc->hwss.setup_stereo(pipe, core_dc);
964                                 }
965                         }
966                 }
967
968                 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
969                                 context->streams[i]->public.timing.h_addressable,
970                                 context->streams[i]->public.timing.v_addressable,
971                                 context->streams[i]->public.timing.h_total,
972                                 context->streams[i]->public.timing.v_total,
973                                 context->streams[i]->public.timing.pix_clk_khz);
974         }
975
976         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
977
978         dc_release_validate_context(core_dc->current_context);
979
980         core_dc->current_context = context;
981
982         dc_retain_validate_context(core_dc->current_context);
983
984         return (result == DC_OK);
985 }
986
987 bool dc_commit_context(struct dc *dc, struct validate_context *context)
988 {
989         enum dc_status result = DC_ERROR_UNEXPECTED;
990         struct core_dc *core_dc = DC_TO_CORE(dc);
991         int i;
992
993         if (false == context_changed(core_dc, context))
994                 return DC_OK;
995
996         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
997                                 __func__, context->stream_count);
998
999         for (i = 0; i < context->stream_count; i++) {
1000                 const struct dc_stream *stream = &context->streams[i]->public;
1001
1002                 dc_stream_log(stream,
1003                                 core_dc->ctx->logger,
1004                                 LOG_DC);
1005         }
1006
1007         result = dc_commit_context_no_check(dc, context);
1008
1009         return (result == DC_OK);
1010 }
1011
1012
1013 bool dc_commit_streams(
1014         struct dc *dc,
1015         const struct dc_stream *streams[],
1016         uint8_t stream_count)
1017 {
1018         struct core_dc *core_dc = DC_TO_CORE(dc);
1019         enum dc_status result = DC_ERROR_UNEXPECTED;
1020         struct validate_context *context;
1021         struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
1022         int i;
1023
1024         if (false == streams_changed(core_dc, streams, stream_count))
1025                 return DC_OK;
1026
1027         dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
1028                                 __func__, stream_count);
1029
1030         for (i = 0; i < stream_count; i++) {
1031                 const struct dc_stream *stream = streams[i];
1032                 const struct dc_stream_status *status = dc_stream_get_status(stream);
1033                 int j;
1034
1035                 dc_stream_log(stream,
1036                                 core_dc->ctx->logger,
1037                                 LOG_DC);
1038
1039                 set[i].stream = stream;
1040
1041                 if (status) {
1042                         set[i].surface_count = status->surface_count;
1043                         for (j = 0; j < status->surface_count; j++)
1044                                 set[i].surfaces[j] = status->surfaces[j];
1045                 }
1046
1047         }
1048
1049         context = dm_alloc(sizeof(struct validate_context));
1050         if (context == NULL)
1051                 goto context_alloc_fail;
1052
1053         ++context->ref_count;
1054
1055         result = core_dc->res_pool->funcs->validate_with_context(
1056                         core_dc, set, stream_count, context, core_dc->current_context);
1057         if (result != DC_OK){
1058                 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
1059                                         "%s: Context validation failed! dc_status:%d\n",
1060                                         __func__,
1061                                         result);
1062                 BREAK_TO_DEBUGGER();
1063                 goto fail;
1064         }
1065
1066         result = dc_commit_context_no_check(dc, context);
1067
1068 fail:
1069         dc_release_validate_context(context);
1070
1071 context_alloc_fail:
1072         return (result == DC_OK);
1073 }
1074
1075 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1076 {
1077         int i;
1078         struct core_dc *core_dc = DC_TO_CORE(dc);
1079         struct validate_context *context = core_dc->current_context;
1080
1081         post_surface_trace(dc);
1082
1083         for (i = 0; i < core_dc->res_pool->pipe_count; i++)
1084                 if (context->res_ctx.pipe_ctx[i].stream == NULL
1085                                 || context->res_ctx.pipe_ctx[i].surface == NULL)
1086                         core_dc->hwss.power_down_front_end(core_dc, i);
1087
1088         /* 3rd param should be true, temp w/a for RV*/
1089 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1090         core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
1091 #else
1092         core_dc->hwss.set_bandwidth(core_dc, context, true);
1093 #endif
1094         return true;
1095 }
1096
1097 bool dc_commit_surfaces_to_stream(
1098                 struct dc *dc,
1099                 const struct dc_surface **new_surfaces,
1100                 uint8_t new_surface_count,
1101                 const struct dc_stream *dc_stream)
1102 {
1103         struct dc_surface_update updates[MAX_SURFACES];
1104         struct dc_flip_addrs flip_addr[MAX_SURFACES];
1105         struct dc_plane_info plane_info[MAX_SURFACES];
1106         struct dc_scaling_info scaling_info[MAX_SURFACES];
1107         int i;
1108         struct dc_stream_update *stream_update =
1109                         dm_alloc(sizeof(struct dc_stream_update));
1110
1111         if (!stream_update) {
1112                 BREAK_TO_DEBUGGER();
1113                 return false;
1114         }
1115
1116         memset(updates, 0, sizeof(updates));
1117         memset(flip_addr, 0, sizeof(flip_addr));
1118         memset(plane_info, 0, sizeof(plane_info));
1119         memset(scaling_info, 0, sizeof(scaling_info));
1120
1121         stream_update->src = dc_stream->src;
1122         stream_update->dst = dc_stream->dst;
1123         stream_update->out_transfer_func = dc_stream->out_transfer_func;
1124
1125         for (i = 0; i < new_surface_count; i++) {
1126                 updates[i].surface = new_surfaces[i];
1127                 updates[i].gamma =
1128                         (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1129                 updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func;
1130                 flip_addr[i].address = new_surfaces[i]->address;
1131                 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1132                 plane_info[i].color_space = new_surfaces[i]->color_space;
1133                 plane_info[i].format = new_surfaces[i]->format;
1134                 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1135                 plane_info[i].rotation = new_surfaces[i]->rotation;
1136                 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1137                 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1138                 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1139                 plane_info[i].visible = new_surfaces[i]->visible;
1140                 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1141                 plane_info[i].dcc = new_surfaces[i]->dcc;
1142                 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1143                 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1144                 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1145                 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1146
1147                 updates[i].flip_addr = &flip_addr[i];
1148                 updates[i].plane_info = &plane_info[i];
1149                 updates[i].scaling_info = &scaling_info[i];
1150         }
1151
1152         dc_update_surfaces_and_stream(
1153                         dc,
1154                         updates,
1155                         new_surface_count,
1156                         dc_stream, stream_update);
1157
1158         dc_post_update_surfaces_to_stream(dc);
1159
1160         dm_free(stream_update);
1161         return true;
1162 }
1163
1164 void dc_retain_validate_context(struct validate_context *context)
1165 {
1166         ASSERT(context->ref_count > 0);
1167         ++context->ref_count;
1168 }
1169
1170 void dc_release_validate_context(struct validate_context *context)
1171 {
1172         ASSERT(context->ref_count > 0);
1173         --context->ref_count;
1174
1175         if (context->ref_count == 0) {
1176                 dc_resource_validate_ctx_destruct(context);
1177                 dm_free(context);
1178         }
1179 }
1180
1181 static bool is_surface_in_context(
1182                 const struct validate_context *context,
1183                 const struct dc_surface *surface)
1184 {
1185         int j;
1186
1187         for (j = 0; j < MAX_PIPES; j++) {
1188                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1189
1190                 if (surface == &pipe_ctx->surface->public) {
1191                         return true;
1192                 }
1193         }
1194
1195         return false;
1196 }
1197
1198 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1199 {
1200         switch (format) {
1201         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1202         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1203                 return 12;
1204         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1205         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1206         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1207         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1208                 return 16;
1209         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1210         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1211         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1212         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1213                 return 32;
1214         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1215         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1216         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1217                 return 64;
1218         default:
1219                 ASSERT_CRITICAL(false);
1220                 return -1;
1221         }
1222 }
1223
1224 static enum surface_update_type get_plane_info_update_type(
1225                 const struct dc_surface_update *u,
1226                 int surface_index)
1227 {
1228         struct dc_plane_info temp_plane_info;
1229         memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1230
1231         if (!u->plane_info)
1232                 return UPDATE_TYPE_FAST;
1233
1234         temp_plane_info = *u->plane_info;
1235
1236         /* Copy all parameters that will cause a full update
1237          * from current surface, the rest of the parameters
1238          * from provided plane configuration.
1239          * Perform memory compare and special validation
1240          * for those that can cause fast/medium updates
1241          */
1242
1243         /* Full update parameters */
1244         temp_plane_info.color_space = u->surface->color_space;
1245         temp_plane_info.dcc = u->surface->dcc;
1246         temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1247         temp_plane_info.plane_size = u->surface->plane_size;
1248         temp_plane_info.rotation = u->surface->rotation;
1249         temp_plane_info.stereo_format = u->surface->stereo_format;
1250         temp_plane_info.tiling_info = u->surface->tiling_info;
1251
1252         if (surface_index == 0)
1253                 temp_plane_info.visible = u->plane_info->visible;
1254         else
1255                 temp_plane_info.visible = u->surface->visible;
1256
1257         if (memcmp(u->plane_info, &temp_plane_info,
1258                         sizeof(struct dc_plane_info)) != 0)
1259                 return UPDATE_TYPE_FULL;
1260
1261         if (pixel_format_to_bpp(u->plane_info->format) !=
1262                         pixel_format_to_bpp(u->surface->format)) {
1263                 return UPDATE_TYPE_FULL;
1264         } else {
1265                 return UPDATE_TYPE_MED;
1266         }
1267 }
1268
1269 static enum surface_update_type  get_scaling_info_update_type(
1270                 const struct dc_surface_update *u)
1271 {
1272         if (!u->scaling_info)
1273                 return UPDATE_TYPE_FAST;
1274
1275         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1276                         || u->scaling_info->src_rect.height != u->surface->src_rect.height
1277                         || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1278                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1279                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1280                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1281                 return UPDATE_TYPE_FULL;
1282
1283         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1284                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1285                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1286                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1287                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1288                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1289                 return UPDATE_TYPE_MED;
1290
1291         return UPDATE_TYPE_FAST;
1292 }
1293
1294 static enum surface_update_type det_surface_update(
1295                 const struct core_dc *dc,
1296                 const struct dc_surface_update *u,
1297                 int surface_index)
1298 {
1299         const struct validate_context *context = dc->current_context;
1300         enum surface_update_type type = UPDATE_TYPE_FAST;
1301         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1302
1303         if (!is_surface_in_context(context, u->surface))
1304                 return UPDATE_TYPE_FULL;
1305
1306         type = get_plane_info_update_type(u, surface_index);
1307         if (overall_type < type)
1308                 overall_type = type;
1309
1310         type = get_scaling_info_update_type(u);
1311         if (overall_type < type)
1312                 overall_type = type;
1313
1314         if (u->in_transfer_func ||
1315                 u->hdr_static_metadata) {
1316                 if (overall_type < UPDATE_TYPE_MED)
1317                         overall_type = UPDATE_TYPE_MED;
1318         }
1319
1320         return overall_type;
1321 }
1322
1323 enum surface_update_type dc_check_update_surfaces_for_stream(
1324                 struct dc *dc,
1325                 struct dc_surface_update *updates,
1326                 int surface_count,
1327                 struct dc_stream_update *stream_update,
1328                 const struct dc_stream_status *stream_status)
1329 {
1330         struct core_dc *core_dc = DC_TO_CORE(dc);
1331         int i;
1332         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1333
1334         if (stream_status == NULL || stream_status->surface_count != surface_count)
1335                 return UPDATE_TYPE_FULL;
1336
1337         if (stream_update)
1338                 return UPDATE_TYPE_FULL;
1339
1340         for (i = 0 ; i < surface_count; i++) {
1341                 enum surface_update_type type =
1342                                 det_surface_update(core_dc, &updates[i], i);
1343
1344                 if (type == UPDATE_TYPE_FULL)
1345                         return type;
1346
1347                 if (overall_type < type)
1348                         overall_type = type;
1349         }
1350
1351         return overall_type;
1352 }
1353
1354 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1355
1356 void dc_update_surfaces_and_stream(struct dc *dc,
1357                 struct dc_surface_update *srf_updates, int surface_count,
1358                 const struct dc_stream *dc_stream,
1359                 struct dc_stream_update *stream_update)
1360 {
1361         struct core_dc *core_dc = DC_TO_CORE(dc);
1362         struct validate_context *context;
1363         int i, j;
1364         enum surface_update_type update_type;
1365         const struct dc_stream_status *stream_status;
1366         struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1367         struct dc_context *dc_ctx = core_dc->ctx;
1368
1369         stream_status = dc_stream_get_status(dc_stream);
1370         ASSERT(stream_status);
1371         if (!stream_status)
1372                 return; /* Cannot commit surface to stream that is not committed */
1373
1374 #ifdef ENABLE_FBC
1375         if (srf_updates->flip_addr) {
1376                 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1377                         ASSERT(0);
1378         }
1379 #endif
1380         context = core_dc->current_context;
1381
1382         /* update current stream with the new updates */
1383         if (stream_update) {
1384                 if ((stream_update->src.height != 0) &&
1385                                 (stream_update->src.width != 0))
1386                         stream->public.src = stream_update->src;
1387
1388                 if ((stream_update->dst.height != 0) &&
1389                                 (stream_update->dst.width != 0))
1390                         stream->public.dst = stream_update->dst;
1391
1392                 if (stream_update->out_transfer_func &&
1393                                 stream_update->out_transfer_func !=
1394                                                 dc_stream->out_transfer_func) {
1395                         if (dc_stream->out_transfer_func != NULL)
1396                                 dc_transfer_func_release(dc_stream->out_transfer_func);
1397                         dc_transfer_func_retain(stream_update->out_transfer_func);
1398                         stream->public.out_transfer_func =
1399                                 stream_update->out_transfer_func;
1400                 }
1401         }
1402
1403         /* do not perform surface update if surface has invalid dimensions
1404          * (all zero) and no scaling_info is provided
1405          */
1406         if (surface_count > 0 &&
1407                         srf_updates->surface->src_rect.width == 0 &&
1408                         srf_updates->surface->src_rect.height == 0 &&
1409                         srf_updates->surface->dst_rect.width == 0 &&
1410                         srf_updates->surface->dst_rect.height == 0 &&
1411                         !srf_updates->scaling_info) {
1412                 ASSERT(false);
1413                 return;
1414         }
1415
1416         update_type = dc_check_update_surfaces_for_stream(
1417                         dc, srf_updates, surface_count, stream_update, stream_status);
1418
1419         if (update_type >= update_surface_trace_level)
1420                 update_surface_trace(dc, srf_updates, surface_count);
1421
1422         if (update_type >= UPDATE_TYPE_FULL) {
1423                 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1424
1425                 for (i = 0; i < surface_count; i++)
1426                         new_surfaces[i] = srf_updates[i].surface;
1427
1428                 /* initialize scratch memory for building context */
1429                 context = dm_alloc(sizeof(*context));
1430                 if (context == NULL)
1431                                 goto context_alloc_fail;
1432
1433                 ++context->ref_count;
1434
1435                 dc_resource_validate_ctx_copy_construct(
1436                                 core_dc->current_context, context);
1437
1438                 /* add surface to context */
1439                 if (!resource_attach_surfaces_to_context(
1440                                 new_surfaces, surface_count, dc_stream,
1441                                 context, core_dc->res_pool)) {
1442                         BREAK_TO_DEBUGGER();
1443                         goto fail;
1444                 }
1445         }
1446
1447         /* save update parameters into surface */
1448         for (i = 0; i < surface_count; i++) {
1449                 struct core_surface *surface =
1450                                 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1451
1452                 if (srf_updates[i].flip_addr) {
1453                         surface->public.address = srf_updates[i].flip_addr->address;
1454                         surface->public.flip_immediate =
1455                                         srf_updates[i].flip_addr->flip_immediate;
1456                 }
1457
1458                 if (srf_updates[i].scaling_info) {
1459                         surface->public.scaling_quality =
1460                                         srf_updates[i].scaling_info->scaling_quality;
1461                         surface->public.dst_rect =
1462                                         srf_updates[i].scaling_info->dst_rect;
1463                         surface->public.src_rect =
1464                                         srf_updates[i].scaling_info->src_rect;
1465                         surface->public.clip_rect =
1466                                         srf_updates[i].scaling_info->clip_rect;
1467                 }
1468
1469                 if (srf_updates[i].plane_info) {
1470                         surface->public.color_space =
1471                                         srf_updates[i].plane_info->color_space;
1472                         surface->public.format =
1473                                         srf_updates[i].plane_info->format;
1474                         surface->public.plane_size =
1475                                         srf_updates[i].plane_info->plane_size;
1476                         surface->public.rotation =
1477                                         srf_updates[i].plane_info->rotation;
1478                         surface->public.horizontal_mirror =
1479                                         srf_updates[i].plane_info->horizontal_mirror;
1480                         surface->public.stereo_format =
1481                                         srf_updates[i].plane_info->stereo_format;
1482                         surface->public.tiling_info =
1483                                         srf_updates[i].plane_info->tiling_info;
1484                         surface->public.visible =
1485                                         srf_updates[i].plane_info->visible;
1486                         surface->public.per_pixel_alpha =
1487                                         srf_updates[i].plane_info->per_pixel_alpha;
1488                         surface->public.dcc =
1489                                         srf_updates[i].plane_info->dcc;
1490                 }
1491
1492                 if (update_type >= UPDATE_TYPE_MED) {
1493                         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1494                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1495
1496                                 if (pipe_ctx->surface != surface)
1497                                         continue;
1498
1499                                 resource_build_scaling_params(pipe_ctx);
1500                         }
1501                 }
1502
1503                 if (srf_updates[i].gamma &&
1504                         srf_updates[i].gamma != surface->public.gamma_correction) {
1505                         if (surface->public.gamma_correction != NULL)
1506                                 dc_gamma_release(&surface->public.
1507                                                 gamma_correction);
1508
1509                         dc_gamma_retain(srf_updates[i].gamma);
1510                         surface->public.gamma_correction =
1511                                                 srf_updates[i].gamma;
1512                 }
1513
1514                 if (srf_updates[i].in_transfer_func &&
1515                         srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1516                         if (surface->public.in_transfer_func != NULL)
1517                                 dc_transfer_func_release(
1518                                                 surface->public.
1519                                                 in_transfer_func);
1520
1521                         dc_transfer_func_retain(
1522                                         srf_updates[i].in_transfer_func);
1523                         surface->public.in_transfer_func =
1524                                         srf_updates[i].in_transfer_func;
1525                 }
1526
1527                 if (srf_updates[i].hdr_static_metadata)
1528                         surface->public.hdr_static_ctx =
1529                                 *(srf_updates[i].hdr_static_metadata);
1530         }
1531
1532         if (update_type == UPDATE_TYPE_FULL) {
1533                 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1534                         BREAK_TO_DEBUGGER();
1535                         goto fail;
1536                 } else {
1537                         core_dc->hwss.set_bandwidth(core_dc, context, false);
1538                         context_clock_trace(dc, context);
1539                 }
1540         }
1541
1542         if (surface_count == 0)
1543                 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1544
1545         /* Lock pipes for provided surfaces, or all active if full update*/
1546         for (i = 0; i < surface_count; i++) {
1547                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1548
1549                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1550                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1551
1552                         if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1553                                 continue;
1554                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1555                                 continue;
1556
1557                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1558                                 core_dc->hwss.pipe_control_lock(
1559                                                 core_dc,
1560                                                 pipe_ctx,
1561                                                 true);
1562                         }
1563                 }
1564                 if (update_type == UPDATE_TYPE_FULL)
1565                         break;
1566         }
1567
1568         /* Full fe update*/
1569         for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1570                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1571                 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1572                 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1573                 struct dc_cursor_position position = { 0 };
1574
1575                 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1576                         continue;
1577
1578                 if (!pipe_ctx->top_pipe)
1579                         core_dc->hwss.apply_ctx_for_surface(
1580                                         core_dc, pipe_ctx->surface, context);
1581
1582                 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1583                 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1584
1585                 if (is_new_pipe_surface) {
1586                         core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1587                         core_dc->hwss.set_input_transfer_func(
1588                                         pipe_ctx, pipe_ctx->surface);
1589                         core_dc->hwss.set_output_transfer_func(
1590                                         pipe_ctx, pipe_ctx->stream);
1591                 }
1592         }
1593
1594         if (update_type > UPDATE_TYPE_FAST)
1595                 context_timing_trace(dc, &context->res_ctx);
1596
1597         /* Perform requested Updates */
1598         for (i = 0; i < surface_count; i++) {
1599                 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1600
1601                 if (update_type == UPDATE_TYPE_MED)
1602                         core_dc->hwss.apply_ctx_for_surface(
1603                                         core_dc, surface, context);
1604
1605                 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1606                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1607
1608                         if (pipe_ctx->surface != surface)
1609                                 continue;
1610
1611                         if (srf_updates[i].flip_addr)
1612                                 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1613
1614                         if (update_type == UPDATE_TYPE_FAST)
1615                                 continue;
1616
1617                         if (srf_updates[i].in_transfer_func)
1618                                 core_dc->hwss.set_input_transfer_func(
1619                                                 pipe_ctx, pipe_ctx->surface);
1620
1621                         if (stream_update != NULL &&
1622                                         stream_update->out_transfer_func != NULL) {
1623                                 core_dc->hwss.set_output_transfer_func(
1624                                                 pipe_ctx, pipe_ctx->stream);
1625                         }
1626
1627                         if (srf_updates[i].hdr_static_metadata) {
1628                                 resource_build_info_frame(pipe_ctx);
1629                                 core_dc->hwss.update_info_frame(pipe_ctx);
1630                         }
1631                 }
1632         }
1633
1634         /* Unlock pipes */
1635         for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1636                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1637
1638                 for (j = 0; j < surface_count; j++) {
1639                         if (update_type != UPDATE_TYPE_FULL &&
1640                                         srf_updates[j].surface != &pipe_ctx->surface->public)
1641                                 continue;
1642                         if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1643                                 continue;
1644
1645                         if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1646                                 core_dc->hwss.pipe_control_lock(
1647                                                 core_dc,
1648                                                 pipe_ctx,
1649                                                 false);
1650                         }
1651                         break;
1652                 }
1653         }
1654
1655         if (core_dc->current_context != context) {
1656                 dc_release_validate_context(core_dc->current_context);
1657                 core_dc->current_context = context;
1658         }
1659         return;
1660
1661 fail:
1662         dc_release_validate_context(context);
1663
1664 context_alloc_fail:
1665         DC_ERROR("Failed to allocate new validate context!\n");
1666 }
1667
1668 uint8_t dc_get_current_stream_count(const struct dc *dc)
1669 {
1670         struct core_dc *core_dc = DC_TO_CORE(dc);
1671         return core_dc->current_context->stream_count;
1672 }
1673
1674 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1675 {
1676         struct core_dc *core_dc = DC_TO_CORE(dc);
1677         if (i < core_dc->current_context->stream_count)
1678                 return &(core_dc->current_context->streams[i]->public);
1679         return NULL;
1680 }
1681
1682 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1683 {
1684         struct core_dc *core_dc = DC_TO_CORE(dc);
1685         return &core_dc->links[link_index]->public;
1686 }
1687
1688 const struct graphics_object_id dc_get_link_id_at_index(
1689         struct dc *dc, uint32_t link_index)
1690 {
1691         struct core_dc *core_dc = DC_TO_CORE(dc);
1692         return core_dc->links[link_index]->link_id;
1693 }
1694
1695 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1696         struct dc *dc, uint32_t link_index)
1697 {
1698         struct core_dc *core_dc = DC_TO_CORE(dc);
1699         return core_dc->links[link_index]->public.irq_source_hpd;
1700 }
1701
1702 const struct audio **dc_get_audios(struct dc *dc)
1703 {
1704         struct core_dc *core_dc = DC_TO_CORE(dc);
1705         return (const struct audio **)core_dc->res_pool->audios;
1706 }
1707
1708 enum dc_irq_source dc_interrupt_to_irq_source(
1709                 struct dc *dc,
1710                 uint32_t src_id,
1711                 uint32_t ext_id)
1712 {
1713         struct core_dc *core_dc = DC_TO_CORE(dc);
1714         return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1715 }
1716
1717 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1718 {
1719         struct core_dc *core_dc;
1720
1721         if (dc == NULL)
1722                 return;
1723         core_dc = DC_TO_CORE(dc);
1724
1725         dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1726 }
1727
1728 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1729 {
1730         struct core_dc *core_dc = DC_TO_CORE(dc);
1731         dal_irq_service_ack(core_dc->res_pool->irqs, src);
1732 }
1733
1734 void dc_set_power_state(
1735         struct dc *dc,
1736         enum dc_acpi_cm_power_state power_state)
1737 {
1738         struct core_dc *core_dc = DC_TO_CORE(dc);
1739         int ref_count;
1740
1741         switch (power_state) {
1742         case DC_ACPI_CM_POWER_STATE_D0:
1743                 core_dc->hwss.init_hw(core_dc);
1744                 break;
1745         default:
1746
1747                 core_dc->hwss.power_down(core_dc);
1748
1749                 /* Zero out the current context so that on resume we start with
1750                  * clean state, and dc hw programming optimizations will not
1751                  * cause any trouble.
1752                  */
1753
1754                 /* Preserve refcount */
1755                 ref_count = core_dc->current_context->ref_count;
1756                 dc_resource_validate_ctx_destruct(core_dc->current_context);
1757                 memset(core_dc->current_context, 0,
1758                                 sizeof(*core_dc->current_context));
1759                 core_dc->current_context->ref_count = ref_count;
1760
1761                 break;
1762         }
1763
1764 }
1765
1766 void dc_resume(const struct dc *dc)
1767 {
1768         struct core_dc *core_dc = DC_TO_CORE(dc);
1769
1770         uint32_t i;
1771
1772         for (i = 0; i < core_dc->link_count; i++)
1773                 core_link_resume(core_dc->links[i]);
1774 }
1775
1776 bool dc_read_aux_dpcd(
1777                 struct dc *dc,
1778                 uint32_t link_index,
1779                 uint32_t address,
1780                 uint8_t *data,
1781                 uint32_t size)
1782 {
1783         struct core_dc *core_dc = DC_TO_CORE(dc);
1784
1785         struct core_link *link = core_dc->links[link_index];
1786         enum ddc_result r = dal_ddc_service_read_dpcd_data(
1787                         link->public.ddc,
1788                         false,
1789                         I2C_MOT_UNDEF,
1790                         address,
1791                         data,
1792                         size);
1793         return r == DDC_RESULT_SUCESSFULL;
1794 }
1795
1796 bool dc_write_aux_dpcd(
1797                 struct dc *dc,
1798                 uint32_t link_index,
1799                 uint32_t address,
1800                 const uint8_t *data,
1801                 uint32_t size)
1802 {
1803         struct core_dc *core_dc = DC_TO_CORE(dc);
1804         struct core_link *link = core_dc->links[link_index];
1805
1806         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1807                         link->public.ddc,
1808                         false,
1809                         I2C_MOT_UNDEF,
1810                         address,
1811                         data,
1812                         size);
1813         return r == DDC_RESULT_SUCESSFULL;
1814 }
1815
1816 bool dc_read_aux_i2c(
1817                 struct dc *dc,
1818                 uint32_t link_index,
1819                 enum i2c_mot_mode mot,
1820                 uint32_t address,
1821                 uint8_t *data,
1822                 uint32_t size)
1823 {
1824         struct core_dc *core_dc = DC_TO_CORE(dc);
1825
1826                 struct core_link *link = core_dc->links[link_index];
1827                 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1828                         link->public.ddc,
1829                         true,
1830                         mot,
1831                         address,
1832                         data,
1833                         size);
1834                 return r == DDC_RESULT_SUCESSFULL;
1835 }
1836
1837 bool dc_write_aux_i2c(
1838                 struct dc *dc,
1839                 uint32_t link_index,
1840                 enum i2c_mot_mode mot,
1841                 uint32_t address,
1842                 const uint8_t *data,
1843                 uint32_t size)
1844 {
1845         struct core_dc *core_dc = DC_TO_CORE(dc);
1846         struct core_link *link = core_dc->links[link_index];
1847
1848         enum ddc_result r = dal_ddc_service_write_dpcd_data(
1849                         link->public.ddc,
1850                         true,
1851                         mot,
1852                         address,
1853                         data,
1854                         size);
1855         return r == DDC_RESULT_SUCESSFULL;
1856 }
1857
1858 bool dc_query_ddc_data(
1859                 struct dc *dc,
1860                 uint32_t link_index,
1861                 uint32_t address,
1862                 uint8_t *write_buf,
1863                 uint32_t write_size,
1864                 uint8_t *read_buf,
1865                 uint32_t read_size) {
1866
1867         struct core_dc *core_dc = DC_TO_CORE(dc);
1868
1869         struct core_link *link = core_dc->links[link_index];
1870
1871         bool result = dal_ddc_service_query_ddc_data(
1872                         link->public.ddc,
1873                         address,
1874                         write_buf,
1875                         write_size,
1876                         read_buf,
1877                         read_size);
1878
1879         return result;
1880 }
1881
1882 bool dc_submit_i2c(
1883                 struct dc *dc,
1884                 uint32_t link_index,
1885                 struct i2c_command *cmd)
1886 {
1887         struct core_dc *core_dc = DC_TO_CORE(dc);
1888
1889         struct core_link *link = core_dc->links[link_index];
1890         struct ddc_service *ddc = link->public.ddc;
1891
1892         return dal_i2caux_submit_i2c_command(
1893                 ddc->ctx->i2caux,
1894                 ddc->ddc_pin,
1895                 cmd);
1896 }
1897
1898 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1899 {
1900         struct dc_link *dc_link = &core_link->public;
1901
1902         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1903                 BREAK_TO_DEBUGGER();
1904                 return false;
1905         }
1906
1907         dc_sink_retain(sink);
1908
1909         dc_link->remote_sinks[dc_link->sink_count] = sink;
1910         dc_link->sink_count++;
1911
1912         return true;
1913 }
1914
1915 struct dc_sink *dc_link_add_remote_sink(
1916                 const struct dc_link *link,
1917                 const uint8_t *edid,
1918                 int len,
1919                 struct dc_sink_init_data *init_data)
1920 {
1921         struct dc_sink *dc_sink;
1922         enum dc_edid_status edid_status;
1923         struct core_link *core_link = DC_LINK_TO_LINK(link);
1924
1925         if (len > MAX_EDID_BUFFER_SIZE) {
1926                 dm_error("Max EDID buffer size breached!\n");
1927                 return NULL;
1928         }
1929
1930         if (!init_data) {
1931                 BREAK_TO_DEBUGGER();
1932                 return NULL;
1933         }
1934
1935         if (!init_data->link) {
1936                 BREAK_TO_DEBUGGER();
1937                 return NULL;
1938         }
1939
1940         dc_sink = dc_sink_create(init_data);
1941
1942         if (!dc_sink)
1943                 return NULL;
1944
1945         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1946         dc_sink->dc_edid.length = len;
1947
1948         if (!link_add_remote_sink_helper(
1949                         core_link,
1950                         dc_sink))
1951                 goto fail_add_sink;
1952
1953         edid_status = dm_helpers_parse_edid_caps(
1954                         core_link->ctx,
1955                         &dc_sink->dc_edid,
1956                         &dc_sink->edid_caps);
1957
1958         if (edid_status != EDID_OK)
1959                 goto fail;
1960
1961         return dc_sink;
1962 fail:
1963         dc_link_remove_remote_sink(link, dc_sink);
1964 fail_add_sink:
1965         dc_sink_release(dc_sink);
1966         return NULL;
1967 }
1968
1969 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1970 {
1971         struct core_link *core_link = DC_LINK_TO_LINK(link);
1972         struct dc_link *dc_link = &core_link->public;
1973
1974         dc_link->local_sink = sink;
1975
1976         if (sink == NULL) {
1977                 dc_link->type = dc_connection_none;
1978         } else {
1979                 dc_link->type = dc_connection_single;
1980         }
1981 }
1982
1983 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1984 {
1985         int i;
1986         struct core_link *core_link = DC_LINK_TO_LINK(link);
1987         struct dc_link *dc_link = &core_link->public;
1988
1989         if (!link->sink_count) {
1990                 BREAK_TO_DEBUGGER();
1991                 return;
1992         }
1993
1994         for (i = 0; i < dc_link->sink_count; i++) {
1995                 if (dc_link->remote_sinks[i] == sink) {
1996                         dc_sink_release(sink);
1997                         dc_link->remote_sinks[i] = NULL;
1998
1999                         /* shrink array to remove empty place */
2000                         while (i < dc_link->sink_count - 1) {
2001                                 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
2002                                 i++;
2003                         }
2004                         dc_link->remote_sinks[i] = NULL;
2005                         dc_link->sink_count--;
2006                         return;
2007                 }
2008         }
2009 }
2010
2011 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
2012 {
2013         int i;
2014         struct core_dc *core_dc = DC_TO_CORE(dc);
2015         struct mem_input *mi = NULL;
2016
2017         for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
2018                 if (core_dc->res_pool->mis[i] != NULL) {
2019                         mi = core_dc->res_pool->mis[i];
2020                         break;
2021                 }
2022         }
2023         if (mi == NULL) {
2024                 dm_error("no mem_input!\n");
2025                 return false;
2026         }
2027
2028         if (mi->funcs->mem_input_update_dchub)
2029                 mi->funcs->mem_input_update_dchub(mi, dh_data);
2030         else
2031                 ASSERT(mi->funcs->mem_input_update_dchub);
2032
2033
2034         return true;
2035
2036 }
2037
2038 void dc_log_hw_state(struct dc *dc)
2039 {
2040         struct core_dc *core_dc = DC_TO_CORE(dc);
2041
2042         if (core_dc->hwss.log_hw_state)
2043                 core_dc->hwss.log_hw_state(core_dc);
2044 }