drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #include "dmub/dmub_srv.h"
  70
  71 #include "dce/dmub_hw_lock_mgr.h"
  72
  73 #include "dc_trace.h"
  74
  75 #define CTX \
  76         dc->ctx
  77
  78 #define DC_LOGGER \
  79         dc->ctx->logger
  80
  81 static const char DC_BUILD_ID[] = "production-build";
  82
  83 /**
  84  * DOC: Overview
  85  *
  86  * DC is the OS-agnostic component of the amdgpu DC driver.
  87  *
  88  * DC maintains and validates a set of structs representing the state of the
  89  * driver and writes that state to AMD hardware
  90  *
  91  * Main DC HW structs:
  92  *
  93  * struct dc - The central struct.  One per driver.  Created on driver load,
  94  * destroyed on driver unload.
  95  *
  96  * struct dc_context - One per driver.
  97  * Used as a backpointer by most other structs in dc.
  98  *
  99  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 100  * plugpoints).  Created on driver load, destroyed on driver unload.
 101  *
 102  * struct dc_sink - One per display.  Created on boot or hotplug.
 103  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 104  * (the display directly attached).  It may also have one or more remote
 105  * sinks (in the Multi-Stream Transport case)
 106  *
 107  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 108  * main pipeline.  Not directly accessible by dm.
 109  *
 110  * Main dc state structs:
 111  *
 112  * These structs can be created and destroyed as needed.  There is a full set of
 113  * these structs in dc->current_state representing the currently programmed state.
 114  *
 115  * struct dc_state - The global DC state to track global state information,
 116  * such as bandwidth values.
 117  *
 118  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 119  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 120  *
 121  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 122  * and may have more in the Multi-Plane Overlay case.
 123  *
 124  * struct resource_context - Represents the programmable state of everything in
 125  * the resource_pool.  Not directly accessible by dm.
 126  *
 127  * struct pipe_ctx - A member of struct resource_context.  Represents the
 128  * internal hardware pipeline components.  Each dc_plane_state has either
 129  * one or two (in the pipe-split case).
 130  */
 131
 132 /*******************************************************************************
 133  * Private functions
 134  ******************************************************************************/
 135
 136 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 137 {
 138         if (new > *original)
 139                 *original = new;
 140 }
 141
 142 static void destroy_links(struct dc *dc)
 143 {
 144         uint32_t i;
 145
 146         for (i = 0; i < dc->link_count; i++) {
 147                 if (NULL != dc->links[i])
 148                         link_destroy(&dc->links[i]);
 149         }
 150 }
 151
 152 static bool create_links(
 153                 struct dc *dc,
 154                 uint32_t num_virtual_links)
 155 {
 156         int i;
 157         int connectors_num;
 158         struct dc_bios *bios = dc->ctx->dc_bios;
 159
 160         dc->link_count = 0;
 161
 162         connectors_num = bios->funcs->get_connectors_number(bios);
 163
 164         if (connectors_num > ENUM_ID_COUNT) {
 165                 dm_error(
 166                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 167                         connectors_num,
 168                         ENUM_ID_COUNT);
 169                 return false;
 170         }
 171
 172         dm_output_to_console(
 173                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 174                 __func__,
 175                 connectors_num,
 176                 num_virtual_links);
 177
 178         for (i = 0; i < connectors_num; i++) {
 179                 struct link_init_data link_init_params = {0};
 180                 struct dc_link *link;
 181
 182                 link_init_params.ctx = dc->ctx;
 183                 /* next BIOS object table connector */
 184                 link_init_params.connector_index = i;
 185                 link_init_params.link_index = dc->link_count;
 186                 link_init_params.dc = dc;
 187                 link = link_create(&link_init_params);
 188
 189                 if (link) {
 190                         bool should_destory_link = false;
 191
 192                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 193                                 if (dc->config.edp_not_connected) {
 194                                         if (!IS_DIAG_DC(dc->ctx->dce_environment))
 195                                                 should_destory_link = true;
 196                                 } else {
 197                                         enum dc_connection_type type;
 198                                         dc_link_detect_sink(link, &type);
 199                                         if (type == dc_connection_none)
 200                                                 should_destory_link = true;
 201                                 }
 202                         }
 203
 204                         if (dc->config.force_enum_edp || !should_destory_link) {
 205                                 dc->links[dc->link_count] = link;
 206                                 link->dc = dc;
 207                                 ++dc->link_count;
 208                         } else {
 209                                 link_destroy(&link);
 210                         }
 211                 }
 212         }
 213
 214         for (i = 0; i < num_virtual_links; i++) {
 215                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 216                 struct encoder_init_data enc_init = {0};
 217
 218                 if (link == NULL) {
 219                         BREAK_TO_DEBUGGER();
 220                         goto failed_alloc;
 221                 }
 222
 223                 link->link_index = dc->link_count;
 224                 dc->links[dc->link_count] = link;
 225                 dc->link_count++;
 226
 227                 link->ctx = dc->ctx;
 228                 link->dc = dc;
 229                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 230                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 231                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 232                 link->link_id.enum_id = ENUM_ID_1;
 233                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 234
 235                 if (!link->link_enc) {
 236                         BREAK_TO_DEBUGGER();
 237                         goto failed_alloc;
 238                 }
 239
 240                 link->link_status.dpcd_caps = &link->dpcd_caps;
 241
 242                 enc_init.ctx = dc->ctx;
 243                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 244                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 245                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 246                 enc_init.connector = link->link_id;
 247                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 248                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 249                 enc_init.encoder.enum_id = ENUM_ID_1;
 250                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 251         }
 252
 253         return true;
 254
 255 failed_alloc:
 256         return false;
 257 }
 258
 259 static struct dc_perf_trace *dc_perf_trace_create(void)
 260 {
 261         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 262 }
 263
 264 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 265 {
 266         kfree(*perf_trace);
 267         *perf_trace = NULL;
 268 }
 269
 270 /**
 271  *****************************************************************************
 272  *  Function: dc_stream_adjust_vmin_vmax
 273  *
 274  *  @brief
 275  *     Looks up the pipe context of dc_stream_state and updates the
 276  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 277  *     Rate, which is a power-saving feature that targets reducing panel
 278  *     refresh rate while the screen is static
 279  *
 280  *  @param [in] dc: dc reference
 281  *  @param [in] stream: Initial dc stream state
 282  *  @param [in] adjust: Updated parameters for vertical_total_min and
 283  *  vertical_total_max
 284  *****************************************************************************
 285  */
 286 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 287                 struct dc_stream_state *stream,
 288                 struct dc_crtc_timing_adjust *adjust)
 289 {
 290         int i = 0;
 291         bool ret = false;
 292
 293         stream->adjust = *adjust;
 294
 295         for (i = 0; i < MAX_PIPES; i++) {
 296                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 297
 298                 if (pipe->stream == stream && pipe->stream_res.tg) {
 299                         dc->hwss.set_drr(&pipe,
 300                                         1,
 301                                         adjust->v_total_min,
 302                                         adjust->v_total_max,
 303                                         adjust->v_total_mid,
 304                                         adjust->v_total_mid_frame_num);
 305
 306                         ret = true;
 307                 }
 308         }
 309         return ret;
 310 }
 311
 312 bool dc_stream_get_crtc_position(struct dc *dc,
 313                 struct dc_stream_state **streams, int num_streams,
 314                 unsigned int *v_pos, unsigned int *nom_v_pos)
 315 {
 316         /* TODO: Support multiple streams */
 317         const struct dc_stream_state *stream = streams[0];
 318         int i = 0;
 319         bool ret = false;
 320         struct crtc_position position;
 321
 322         for (i = 0; i < MAX_PIPES; i++) {
 323                 struct pipe_ctx *pipe =
 324                                 &dc->current_state->res_ctx.pipe_ctx[i];
 325
 326                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 327                         dc->hwss.get_position(&pipe, 1, &position);
 328
 329                         *v_pos = position.vertical_count;
 330                         *nom_v_pos = position.nominal_vcount;
 331                         ret = true;
 332                 }
 333         }
 334         return ret;
 335 }
 336
 337 /**
 338  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 339  * @dc: DC Object
 340  * @stream: The stream to configure CRC on.
 341  * @enable: Enable CRC if true, disable otherwise.
 342  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 343  *              once.
 344  *
 345  * By default, only CRC0 is configured, and the entire frame is used to
 346  * calculate the crc.
 347  */
 348 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 349                              struct crc_params *crc_window, bool enable, bool continuous)
 350 {
 351         int i;
 352         struct pipe_ctx *pipe;
 353         struct crc_params param;
 354         struct timing_generator *tg;
 355
 356         for (i = 0; i < MAX_PIPES; i++) {
 357                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 358                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 359                         break;
 360         }
 361         /* Stream not found */
 362         if (i == MAX_PIPES)
 363                 return false;
 364
 365         /* By default, capture the full frame */
 366         param.windowa_x_start = 0;
 367         param.windowa_y_start = 0;
 368         param.windowa_x_end = pipe->stream->timing.h_addressable;
 369         param.windowa_y_end = pipe->stream->timing.v_addressable;
 370         param.windowb_x_start = 0;
 371         param.windowb_y_start = 0;
 372         param.windowb_x_end = pipe->stream->timing.h_addressable;
 373         param.windowb_y_end = pipe->stream->timing.v_addressable;
 374
 375         if (crc_window) {
 376                 param.windowa_x_start = crc_window->windowa_x_start;
 377                 param.windowa_y_start = crc_window->windowa_y_start;
 378                 param.windowa_x_end = crc_window->windowa_x_end;
 379                 param.windowa_y_end = crc_window->windowa_y_end;
 380                 param.windowb_x_start = crc_window->windowb_x_start;
 381                 param.windowb_y_start = crc_window->windowb_y_start;
 382                 param.windowb_x_end = crc_window->windowb_x_end;
 383                 param.windowb_y_end = crc_window->windowb_y_end;
 384         }
 385
 386         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 387         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 388
 389         /* Default to the union of both windows */
 390         param.selection = UNION_WINDOW_A_B;
 391         param.continuous_mode = continuous;
 392         param.enable = enable;
 393
 394         tg = pipe->stream_res.tg;
 395
 396         /* Only call if supported */
 397         if (tg->funcs->configure_crc)
 398                 return tg->funcs->configure_crc(tg, &param);
 399         DC_LOG_WARNING("CRC capture not supported.");
 400         return false;
 401 }
 402
 403 /**
 404  * dc_stream_get_crc() - Get CRC values for the given stream.
 405  * @dc: DC object
 406  * @stream: The DC stream state of the stream to get CRCs from.
 407  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 408  *
 409  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 410  * Return false if stream is not found, or if CRCs are not enabled.
 411  */
 412 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 413                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 414 {
 415         int i;
 416         struct pipe_ctx *pipe;
 417         struct timing_generator *tg;
 418
 419         for (i = 0; i < MAX_PIPES; i++) {
 420                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 421                 if (pipe->stream == stream)
 422                         break;
 423         }
 424         /* Stream not found */
 425         if (i == MAX_PIPES)
 426                 return false;
 427
 428         tg = pipe->stream_res.tg;
 429
 430         if (tg->funcs->get_crc)
 431                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 432         DC_LOG_WARNING("CRC capture not supported.");
 433         return false;
 434 }
 435
 436 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 437                 enum dc_dynamic_expansion option)
 438 {
 439         /* OPP FMT dyn expansion updates*/
 440         int i = 0;
 441         struct pipe_ctx *pipe_ctx;
 442
 443         for (i = 0; i < MAX_PIPES; i++) {
 444                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 445                                 == stream) {
 446                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 447                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 448                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 449                                         pipe_ctx->stream_res.opp,
 450                                         COLOR_SPACE_YCBCR601,
 451                                         stream->timing.display_color_depth,
 452                                         stream->signal);
 453                 }
 454         }
 455 }
 456
 457 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 458                 enum dc_dither_option option)
 459 {
 460         struct bit_depth_reduction_params params;
 461         struct dc_link *link = stream->link;
 462         struct pipe_ctx *pipes = NULL;
 463         int i;
 464
 465         for (i = 0; i < MAX_PIPES; i++) {
 466                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 467                                 stream) {
 468                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 469                         break;
 470                 }
 471         }
 472
 473         if (!pipes)
 474                 return;
 475         if (option > DITHER_OPTION_MAX)
 476                 return;
 477
 478         stream->dither_option = option;
 479
 480         memset(&params, 0, sizeof(params));
 481         resource_build_bit_depth_reduction_params(stream, &params);
 482         stream->bit_depth_params = params;
 483
 484         if (pipes->plane_res.xfm &&
 485             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 486                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 487                         pipes->plane_res.xfm,
 488                         pipes->plane_res.scl_data.lb_params.depth,
 489                         &stream->bit_depth_params);
 490         }
 491
 492         pipes->stream_res.opp->funcs->
 493                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 494 }
 495
 496 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 497 {
 498         int i = 0;
 499         bool ret = false;
 500         struct pipe_ctx *pipes;
 501
 502         for (i = 0; i < MAX_PIPES; i++) {
 503                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 504                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 505                         dc->hwss.program_gamut_remap(pipes);
 506                         ret = true;
 507                 }
 508         }
 509
 510         return ret;
 511 }
 512
 513 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 514 {
 515         int i = 0;
 516         bool ret = false;
 517         struct pipe_ctx *pipes;
 518
 519         for (i = 0; i < MAX_PIPES; i++) {
 520                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 521                                 == stream) {
 522
 523                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 524                         dc->hwss.program_output_csc(dc,
 525                                         pipes,
 526                                         stream->output_color_space,
 527                                         stream->csc_color_matrix.matrix,
 528                                         pipes->stream_res.opp->inst);
 529                         ret = true;
 530                 }
 531         }
 532
 533         return ret;
 534 }
 535
 536 void dc_stream_set_static_screen_params(struct dc *dc,
 537                 struct dc_stream_state **streams,
 538                 int num_streams,
 539                 const struct dc_static_screen_params *params)
 540 {
 541         int i = 0;
 542         int j = 0;
 543         struct pipe_ctx *pipes_affected[MAX_PIPES];
 544         int num_pipes_affected = 0;
 545
 546         for (i = 0; i < num_streams; i++) {
 547                 struct dc_stream_state *stream = streams[i];
 548
 549                 for (j = 0; j < MAX_PIPES; j++) {
 550                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 551                                         == stream) {
 552                                 pipes_affected[num_pipes_affected++] =
 553                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 554                         }
 555                 }
 556         }
 557
 558         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 559 }
 560
 561 static void dc_destruct(struct dc *dc)
 562 {
 563         if (dc->current_state) {
 564                 dc_release_state(dc->current_state);
 565                 dc->current_state = NULL;
 566         }
 567
 568         destroy_links(dc);
 569
 570         if (dc->clk_mgr) {
 571                 dc_destroy_clk_mgr(dc->clk_mgr);
 572                 dc->clk_mgr = NULL;
 573         }
 574
 575         dc_destroy_resource_pool(dc);
 576
 577         if (dc->ctx->gpio_service)
 578                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 579
 580         if (dc->ctx->created_bios)
 581                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 582
 583         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 584
 585         kfree(dc->ctx);
 586         dc->ctx = NULL;
 587
 588         kfree(dc->bw_vbios);
 589         dc->bw_vbios = NULL;
 590
 591         kfree(dc->bw_dceip);
 592         dc->bw_dceip = NULL;
 593
 594 #ifdef CONFIG_DRM_AMD_DC_DCN
 595         kfree(dc->dcn_soc);
 596         dc->dcn_soc = NULL;
 597
 598         kfree(dc->dcn_ip);
 599         dc->dcn_ip = NULL;
 600
 601 #endif
 602         kfree(dc->vm_helper);
 603         dc->vm_helper = NULL;
 604
 605 }
 606
 607 static bool dc_construct_ctx(struct dc *dc,
 608                 const struct dc_init_data *init_params)
 609 {
 610         struct dc_context *dc_ctx;
 611         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 612
 613         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 614         if (!dc_ctx)
 615                 return false;
 616
 617         dc_ctx->cgs_device = init_params->cgs_device;
 618         dc_ctx->driver_context = init_params->driver;
 619         dc_ctx->dc = dc;
 620         dc_ctx->asic_id = init_params->asic_id;
 621         dc_ctx->dc_sink_id_count = 0;
 622         dc_ctx->dc_stream_id_count = 0;
 623         dc_ctx->dce_environment = init_params->dce_environment;
 624
 625         /* Create logger */
 626
 627         dc_version = resource_parse_asic_id(init_params->asic_id);
 628         dc_ctx->dce_version = dc_version;
 629
 630         dc_ctx->perf_trace = dc_perf_trace_create();
 631         if (!dc_ctx->perf_trace) {
 632                 ASSERT_CRITICAL(false);
 633                 return false;
 634         }
 635
 636         dc->ctx = dc_ctx;
 637
 638         return true;
 639 }
 640
 641 static bool dc_construct(struct dc *dc,
 642                 const struct dc_init_data *init_params)
 643 {
 644         struct dc_context *dc_ctx;
 645         struct bw_calcs_dceip *dc_dceip;
 646         struct bw_calcs_vbios *dc_vbios;
 647 #ifdef CONFIG_DRM_AMD_DC_DCN
 648         struct dcn_soc_bounding_box *dcn_soc;
 649         struct dcn_ip_params *dcn_ip;
 650 #endif
 651
 652         dc->config = init_params->flags;
 653
 654         // Allocate memory for the vm_helper
 655         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 656         if (!dc->vm_helper) {
 657                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 658                 goto fail;
 659         }
 660
 661         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 662
 663         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 664         if (!dc_dceip) {
 665                 dm_error("%s: failed to create dceip\n", __func__);
 666                 goto fail;
 667         }
 668
 669         dc->bw_dceip = dc_dceip;
 670
 671         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 672         if (!dc_vbios) {
 673                 dm_error("%s: failed to create vbios\n", __func__);
 674                 goto fail;
 675         }
 676
 677         dc->bw_vbios = dc_vbios;
 678 #ifdef CONFIG_DRM_AMD_DC_DCN
 679         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 680         if (!dcn_soc) {
 681                 dm_error("%s: failed to create dcn_soc\n", __func__);
 682                 goto fail;
 683         }
 684
 685         dc->dcn_soc = dcn_soc;
 686
 687         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 688         if (!dcn_ip) {
 689                 dm_error("%s: failed to create dcn_ip\n", __func__);
 690                 goto fail;
 691         }
 692
 693         dc->dcn_ip = dcn_ip;
 694         dc->soc_bounding_box = init_params->soc_bounding_box;
 695 #endif
 696
 697         if (!dc_construct_ctx(dc, init_params)) {
 698                 dm_error("%s: failed to create ctx\n", __func__);
 699                 goto fail;
 700         }
 701
 702         dc_ctx = dc->ctx;
 703
 704         /* Resource should construct all asic specific resources.
 705          * This should be the only place where we need to parse the asic id
 706          */
 707         if (init_params->vbios_override)
 708                 dc_ctx->dc_bios = init_params->vbios_override;
 709         else {
 710                 /* Create BIOS parser */
 711                 struct bp_init_data bp_init_data;
 712
 713                 bp_init_data.ctx = dc_ctx;
 714                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 715
 716                 dc_ctx->dc_bios = dal_bios_parser_create(
 717                                 &bp_init_data, dc_ctx->dce_version);
 718
 719                 if (!dc_ctx->dc_bios) {
 720                         ASSERT_CRITICAL(false);
 721                         goto fail;
 722                 }
 723
 724                 dc_ctx->created_bios = true;
 725         }
 726
 727         dc->vendor_signature = init_params->vendor_signature;
 728
 729         /* Create GPIO service */
 730         dc_ctx->gpio_service = dal_gpio_service_create(
 731                         dc_ctx->dce_version,
 732                         dc_ctx->dce_environment,
 733                         dc_ctx);
 734
 735         if (!dc_ctx->gpio_service) {
 736                 ASSERT_CRITICAL(false);
 737                 goto fail;
 738         }
 739
 740         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 741         if (!dc->res_pool)
 742                 goto fail;
 743
 744         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 745         if (!dc->clk_mgr)
 746                 goto fail;
 747 #ifdef CONFIG_DRM_AMD_DC_DCN
 748         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 749 #endif
 750
 751         dc->debug.force_ignore_link_settings = init_params->force_ignore_link_settings;
 752
 753         if (dc->res_pool->funcs->update_bw_bounding_box)
 754                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 755
 756         /* Creation of current_state must occur after dc->dml
 757          * is initialized in dc_create_resource_pool because
 758          * on creation it copies the contents of dc->dml
 759          */
 760
 761         dc->current_state = dc_create_state(dc);
 762
 763         if (!dc->current_state) {
 764                 dm_error("%s: failed to create validate ctx\n", __func__);
 765                 goto fail;
 766         }
 767
 768         dc_resource_state_construct(dc, dc->current_state);
 769
 770         if (!create_links(dc, init_params->num_virtual_links))
 771                 goto fail;
 772
 773         return true;
 774
 775 fail:
 776         return false;
 777 }
 778
 779 static void disable_all_writeback_pipes_for_stream(
 780                 const struct dc *dc,
 781                 struct dc_stream_state *stream,
 782                 struct dc_state *context)
 783 {
 784         int i;
 785
 786         for (i = 0; i < stream->num_wb_info; i++)
 787                 stream->writeback_info[i].wb_enabled = false;
 788 }
 789
 790 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 791 {
 792         int i = 0;
 793
 794         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 795         if (dc->hwss.interdependent_update_lock)
 796                 dc->hwss.interdependent_update_lock(dc, context, lock);
 797         else {
 798                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 799                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 800                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 801
 802                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 803                         if (stream == pipe_ctx->stream) {
 804                                 if (!pipe_ctx->top_pipe &&
 805                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 806                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 807                         }
 808                 }
 809         }
 810 }
 811
 812 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 813 {
 814         int i, j;
 815         struct dc_state *dangling_context = dc_create_state(dc);
 816         struct dc_state *current_ctx;
 817
 818         if (dangling_context == NULL)
 819                 return;
 820
 821         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 822
 823         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 824                 struct dc_stream_state *old_stream =
 825                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 826                 bool should_disable = true;
 827
 828                 for (j = 0; j < context->stream_count; j++) {
 829                         if (old_stream == context->streams[j]) {
 830                                 should_disable = false;
 831                                 break;
 832                         }
 833                 }
 834                 if (should_disable && old_stream) {
 835                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 836                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 837
 838                         if (dc->hwss.apply_ctx_for_surface) {
 839                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 840                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 841                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 842                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 843                         }
 844                         if (dc->hwss.program_front_end_for_ctx) {
 845                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 846                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 847                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 848                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 849                         }
 850                 }
 851         }
 852
 853         current_ctx = dc->current_state;
 854         dc->current_state = dangling_context;
 855         dc_release_state(current_ctx);
 856 }
 857
 858 static void disable_vbios_mode_if_required(
 859                 struct dc *dc,
 860                 struct dc_state *context)
 861 {
 862         unsigned int i, j;
 863
 864         /* check if timing_changed, disable stream*/
 865         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 866                 struct dc_stream_state *stream = NULL;
 867                 struct dc_link *link = NULL;
 868                 struct pipe_ctx *pipe = NULL;
 869
 870                 pipe = &context->res_ctx.pipe_ctx[i];
 871                 stream = pipe->stream;
 872                 if (stream == NULL)
 873                         continue;
 874
 875                 // only looking for first odm pipe
 876                 if (pipe->prev_odm_pipe)
 877                         continue;
 878
 879                 if (stream->link->local_sink &&
 880                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 881                         link = stream->link;
 882                 }
 883
 884                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 885                         unsigned int enc_inst, tg_inst = 0;
 886                         unsigned int pix_clk_100hz;
 887
 888                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 889                         if (enc_inst != ENGINE_ID_UNKNOWN) {
 890                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 891                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
 892                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
 893                                                         dc->res_pool->stream_enc[j]);
 894                                                 break;
 895                                         }
 896                                 }
 897
 898                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
 899                                         dc->res_pool->dp_clock_source,
 900                                         tg_inst, &pix_clk_100hz);
 901
 902                                 if (link->link_status.link_active) {
 903                                         uint32_t requested_pix_clk_100hz =
 904                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
 905
 906                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
 907                                                 core_link_disable_stream(pipe);
 908                                                 pipe->stream->dpms_off = false;
 909                                         }
 910                                 }
 911                         }
 912                 }
 913         }
 914 }
 915
 916 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 917 {
 918         int i;
 919         PERF_TRACE();
 920         for (i = 0; i < MAX_PIPES; i++) {
 921                 int count = 0;
 922                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 923
 924                 if (!pipe->plane_state)
 925                         continue;
 926
 927                 /* Timeout 100 ms */
 928                 while (count < 100000) {
 929                         /* Must set to false to start with, due to OR in update function */
 930                         pipe->plane_state->status.is_flip_pending = false;
 931                         dc->hwss.update_pending_status(pipe);
 932                         if (!pipe->plane_state->status.is_flip_pending)
 933                                 break;
 934                         udelay(1);
 935                         count++;
 936                 }
 937                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 938         }
 939         PERF_TRACE();
 940 }
 941
 942 /*******************************************************************************
 943  * Public functions
 944  ******************************************************************************/
 945
 946 struct dc *dc_create(const struct dc_init_data *init_params)
 947 {
 948         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 949         unsigned int full_pipe_count;
 950
 951         if (NULL == dc)
 952                 goto alloc_fail;
 953
 954         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 955                 if (false == dc_construct_ctx(dc, init_params)) {
 956                         dc_destruct(dc);
 957                         goto construct_fail;
 958                 }
 959         } else {
 960                 if (false == dc_construct(dc, init_params)) {
 961                         dc_destruct(dc);
 962                         goto construct_fail;
 963                 }
 964
 965                 full_pipe_count = dc->res_pool->pipe_count;
 966                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 967                         full_pipe_count--;
 968                 dc->caps.max_streams = min(
 969                                 full_pipe_count,
 970                                 dc->res_pool->stream_enc_count);
 971
 972                 dc->optimize_seamless_boot_streams = 0;
 973                 dc->caps.max_links = dc->link_count;
 974                 dc->caps.max_audios = dc->res_pool->audio_count;
 975                 dc->caps.linear_pitch_alignment = 64;
 976
 977                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 978
 979                 if (dc->res_pool->dmcu != NULL)
 980                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 981         }
 982
 983         /* Populate versioning information */
 984         dc->versions.dc_ver = DC_VER;
 985
 986         dc->build_id = DC_BUILD_ID;
 987
 988         DC_LOG_DC("Display Core initialized\n");
 989
 990
 991
 992         return dc;
 993
 994 construct_fail:
 995         kfree(dc);
 996
 997 alloc_fail:
 998         return NULL;
 999 }
1000
1001 void dc_hardware_init(struct dc *dc)
1002 {
1003         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1004                 dc->hwss.init_hw(dc);
1005 }
1006
1007 void dc_init_callbacks(struct dc *dc,
1008                 const struct dc_callback_init *init_params)
1009 {
1010 #ifdef CONFIG_DRM_AMD_DC_HDCP
1011         dc->ctx->cp_psp = init_params->cp_psp;
1012 #endif
1013 }
1014
1015 void dc_deinit_callbacks(struct dc *dc)
1016 {
1017 #ifdef CONFIG_DRM_AMD_DC_HDCP
1018         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1019 #endif
1020 }
1021
1022 void dc_destroy(struct dc **dc)
1023 {
1024         dc_destruct(*dc);
1025         kfree(*dc);
1026         *dc = NULL;
1027 }
1028
1029 static void enable_timing_multisync(
1030                 struct dc *dc,
1031                 struct dc_state *ctx)
1032 {
1033         int i = 0, multisync_count = 0;
1034         int pipe_count = dc->res_pool->pipe_count;
1035         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1036
1037         for (i = 0; i < pipe_count; i++) {
1038                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1039                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1040                         continue;
1041                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1042                         continue;
1043                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1044                 multisync_count++;
1045         }
1046
1047         if (multisync_count > 0) {
1048                 dc->hwss.enable_per_frame_crtc_position_reset(
1049                         dc, multisync_count, multisync_pipes);
1050         }
1051 }
1052
1053 static void program_timing_sync(
1054                 struct dc *dc,
1055                 struct dc_state *ctx)
1056 {
1057         int i, j, k;
1058         int group_index = 0;
1059         int num_group = 0;
1060         int pipe_count = dc->res_pool->pipe_count;
1061         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1062
1063         for (i = 0; i < pipe_count; i++) {
1064                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1065                         continue;
1066
1067                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1068         }
1069
1070         for (i = 0; i < pipe_count; i++) {
1071                 int group_size = 1;
1072                 struct pipe_ctx *pipe_set[MAX_PIPES];
1073
1074                 if (!unsynced_pipes[i])
1075                         continue;
1076
1077                 pipe_set[0] = unsynced_pipes[i];
1078                 unsynced_pipes[i] = NULL;
1079
1080                 /* Add tg to the set, search rest of the tg's for ones with
1081                  * same timing, add all tgs with same timing to the group
1082                  */
1083                 for (j = i + 1; j < pipe_count; j++) {
1084                         if (!unsynced_pipes[j])
1085                                 continue;
1086
1087                         if (resource_are_streams_timing_synchronizable(
1088                                         unsynced_pipes[j]->stream,
1089                                         pipe_set[0]->stream)) {
1090                                 pipe_set[group_size] = unsynced_pipes[j];
1091                                 unsynced_pipes[j] = NULL;
1092                                 group_size++;
1093                         }
1094                 }
1095
1096                 /* set first unblanked pipe as master */
1097                 for (j = 0; j < group_size; j++) {
1098                         bool is_blanked;
1099
1100                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1101                                 is_blanked =
1102                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1103                         else
1104                                 is_blanked =
1105                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1106                         if (!is_blanked) {
1107                                 if (j == 0)
1108                                         break;
1109
1110                                 swap(pipe_set[0], pipe_set[j]);
1111                                 break;
1112                         }
1113                 }
1114
1115
1116                 for (k = 0; k < group_size; k++) {
1117                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1118
1119                         status->timing_sync_info.group_id = num_group;
1120                         status->timing_sync_info.group_size = group_size;
1121                         if (k == 0)
1122                                 status->timing_sync_info.master = true;
1123                         else
1124                                 status->timing_sync_info.master = false;
1125
1126                 }
1127                 /* remove any other unblanked pipes as they have already been synced */
1128                 for (j = j + 1; j < group_size; j++) {
1129                         bool is_blanked;
1130
1131                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1132                                 is_blanked =
1133                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1134                         else
1135                                 is_blanked =
1136                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1137                         if (!is_blanked) {
1138                                 group_size--;
1139                                 pipe_set[j] = pipe_set[group_size];
1140                                 j--;
1141                         }
1142                 }
1143
1144                 if (group_size > 1) {
1145                         dc->hwss.enable_timing_synchronization(
1146                                 dc, group_index, group_size, pipe_set);
1147                         group_index++;
1148                 }
1149                 num_group++;
1150         }
1151 }
1152
1153 static bool context_changed(
1154                 struct dc *dc,
1155                 struct dc_state *context)
1156 {
1157         uint8_t i;
1158
1159         if (context->stream_count != dc->current_state->stream_count)
1160                 return true;
1161
1162         for (i = 0; i < dc->current_state->stream_count; i++) {
1163                 if (dc->current_state->streams[i] != context->streams[i])
1164                         return true;
1165         }
1166
1167         return false;
1168 }
1169
1170 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1171                                 const struct dc_sink *sink,
1172                                 struct dc_crtc_timing *crtc_timing)
1173 {
1174         struct timing_generator *tg;
1175         struct stream_encoder *se = NULL;
1176
1177         struct dc_crtc_timing hw_crtc_timing = {0};
1178
1179         struct dc_link *link = sink->link;
1180         unsigned int i, enc_inst, tg_inst = 0;
1181
1182         // Seamless port only support single DP and EDP so far
1183         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1184                 sink->sink_signal != SIGNAL_TYPE_EDP)
1185                 return false;
1186
1187         /* Check for enabled DIG to identify enabled display */
1188         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1189                 return false;
1190
1191         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1192
1193         if (enc_inst == ENGINE_ID_UNKNOWN)
1194                 return false;
1195
1196         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1197                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1198
1199                         se = dc->res_pool->stream_enc[i];
1200
1201                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1202                                 dc->res_pool->stream_enc[i]);
1203                         break;
1204                 }
1205         }
1206
1207         // tg_inst not found
1208         if (i == dc->res_pool->stream_enc_count)
1209                 return false;
1210
1211         if (tg_inst >= dc->res_pool->timing_generator_count)
1212                 return false;
1213
1214         tg = dc->res_pool->timing_generators[tg_inst];
1215
1216         if (!tg->funcs->get_hw_timing)
1217                 return false;
1218
1219         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1220                 return false;
1221
1222         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1223                 return false;
1224
1225         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1226                 return false;
1227
1228         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1229                 return false;
1230
1231         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1232                 return false;
1233
1234         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1235                 return false;
1236
1237         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1238                 return false;
1239
1240         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1241                 return false;
1242
1243         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1244                 return false;
1245
1246         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1247                 return false;
1248
1249         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1250                 return false;
1251
1252         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1253                 return false;
1254
1255         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1256                 return false;
1257
1258         if (dc_is_dp_signal(link->connector_signal)) {
1259                 unsigned int pix_clk_100hz;
1260
1261                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1262                         dc->res_pool->dp_clock_source,
1263                         tg_inst, &pix_clk_100hz);
1264
1265                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1266                         return false;
1267
1268                 if (!se->funcs->dp_get_pixel_format)
1269                         return false;
1270
1271                 if (!se->funcs->dp_get_pixel_format(
1272                         se,
1273                         &hw_crtc_timing.pixel_encoding,
1274                         &hw_crtc_timing.display_color_depth))
1275                         return false;
1276
1277                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1278                         return false;
1279
1280                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1281                         return false;
1282         }
1283
1284         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1285                 return false;
1286         }
1287
1288         return true;
1289 }
1290
1291 void dc_enable_stereo(
1292         struct dc *dc,
1293         struct dc_state *context,
1294         struct dc_stream_state *streams[],
1295         uint8_t stream_count)
1296 {
1297         int i, j;
1298         struct pipe_ctx *pipe;
1299
1300         for (i = 0; i < MAX_PIPES; i++) {
1301                 if (context != NULL)
1302                         pipe = &context->res_ctx.pipe_ctx[i];
1303                 else
1304                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1305                 for (j = 0 ; pipe && j < stream_count; j++)  {
1306                         if (streams[j] && streams[j] == pipe->stream &&
1307                                 dc->hwss.setup_stereo)
1308                                 dc->hwss.setup_stereo(pipe, dc);
1309                 }
1310         }
1311 }
1312
1313 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1314 {
1315         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1316                 enable_timing_multisync(dc, context);
1317                 program_timing_sync(dc, context);
1318         }
1319 }
1320
1321 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1322 {
1323         int i;
1324         unsigned int stream_mask = 0;
1325
1326         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1327                 if (context->res_ctx.pipe_ctx[i].stream)
1328                         stream_mask |= 1 << i;
1329         }
1330
1331         return stream_mask;
1332 }
1333
1334 /*
1335  * Applies given context to HW and copy it into current context.
1336  * It's up to the user to release the src context afterwards.
1337  */
1338 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1339 {
1340         struct dc_bios *dcb = dc->ctx->dc_bios;
1341         enum dc_status result = DC_ERROR_UNEXPECTED;
1342         struct pipe_ctx *pipe;
1343         int i, k, l;
1344         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1345
1346 #if defined(CONFIG_DRM_AMD_DC_DCN)
1347         dc_allow_idle_optimizations(dc, false);
1348 #endif
1349
1350         for (i = 0; i < context->stream_count; i++)
1351                 dc_streams[i] =  context->streams[i];
1352
1353         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1354                 disable_vbios_mode_if_required(dc, context);
1355                 dc->hwss.enable_accelerated_mode(dc, context);
1356         }
1357
1358         for (i = 0; i < context->stream_count; i++)
1359                 if (context->streams[i]->apply_seamless_boot_optimization)
1360                         dc->optimize_seamless_boot_streams++;
1361
1362         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1363                 context->stream_count == 0)
1364                 dc->hwss.prepare_bandwidth(dc, context);
1365
1366         disable_dangling_plane(dc, context);
1367         /* re-program planes for existing stream, in case we need to
1368          * free up plane resource for later use
1369          */
1370         if (dc->hwss.apply_ctx_for_surface) {
1371                 for (i = 0; i < context->stream_count; i++) {
1372                         if (context->streams[i]->mode_changed)
1373                                 continue;
1374                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1375                         dc->hwss.apply_ctx_for_surface(
1376                                 dc, context->streams[i],
1377                                 context->stream_status[i].plane_count,
1378                                 context); /* use new pipe config in new context */
1379                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1380                         dc->hwss.post_unlock_program_front_end(dc, context);
1381                 }
1382         }
1383
1384         /* Program hardware */
1385         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1386                 pipe = &context->res_ctx.pipe_ctx[i];
1387                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1388         }
1389
1390         result = dc->hwss.apply_ctx_to_hw(dc, context);
1391
1392         if (result != DC_OK)
1393                 return result;
1394
1395         dc_trigger_sync(dc, context);
1396
1397         /* Program all planes within new context*/
1398         if (dc->hwss.program_front_end_for_ctx) {
1399                 dc->hwss.interdependent_update_lock(dc, context, true);
1400                 dc->hwss.program_front_end_for_ctx(dc, context);
1401                 dc->hwss.interdependent_update_lock(dc, context, false);
1402                 dc->hwss.post_unlock_program_front_end(dc, context);
1403         }
1404         for (i = 0; i < context->stream_count; i++) {
1405                 const struct dc_link *link = context->streams[i]->link;
1406
1407                 if (!context->streams[i]->mode_changed)
1408                         continue;
1409
1410                 if (dc->hwss.apply_ctx_for_surface) {
1411                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1412                         dc->hwss.apply_ctx_for_surface(
1413                                         dc, context->streams[i],
1414                                         context->stream_status[i].plane_count,
1415                                         context);
1416                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1417                         dc->hwss.post_unlock_program_front_end(dc, context);
1418                 }
1419
1420                 /*
1421                  * enable stereo
1422                  * TODO rework dc_enable_stereo call to work with validation sets?
1423                  */
1424                 for (k = 0; k < MAX_PIPES; k++) {
1425                         pipe = &context->res_ctx.pipe_ctx[k];
1426
1427                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1428                                 if (context->streams[l] &&
1429                                         context->streams[l] == pipe->stream &&
1430                                         dc->hwss.setup_stereo)
1431                                         dc->hwss.setup_stereo(pipe, dc);
1432                         }
1433                 }
1434
1435                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1436                                 context->streams[i]->timing.h_addressable,
1437                                 context->streams[i]->timing.v_addressable,
1438                                 context->streams[i]->timing.h_total,
1439                                 context->streams[i]->timing.v_total,
1440                                 context->streams[i]->timing.pix_clk_100hz / 10);
1441         }
1442
1443         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1444
1445         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1446                 context->stream_count == 0) {
1447                 /* Must wait for no flips to be pending before doing optimize bw */
1448                 wait_for_no_pipes_pending(dc, context);
1449                 /* pplib is notified if disp_num changed */
1450                 dc->hwss.optimize_bandwidth(dc, context);
1451         }
1452
1453         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1454                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1455         else
1456                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1457
1458         context->stream_mask = get_stream_mask(dc, context);
1459
1460         if (context->stream_mask != dc->current_state->stream_mask)
1461                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1462
1463         for (i = 0; i < context->stream_count; i++)
1464                 context->streams[i]->mode_changed = false;
1465
1466         dc_release_state(dc->current_state);
1467
1468         dc->current_state = context;
1469
1470         dc_retain_state(dc->current_state);
1471
1472         return result;
1473 }
1474
1475 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1476 {
1477         enum dc_status result = DC_ERROR_UNEXPECTED;
1478         int i;
1479
1480         if (false == context_changed(dc, context))
1481                 return DC_OK;
1482
1483         DC_LOG_DC("%s: %d streams\n",
1484                                 __func__, context->stream_count);
1485
1486         for (i = 0; i < context->stream_count; i++) {
1487                 struct dc_stream_state *stream = context->streams[i];
1488
1489                 dc_stream_log(dc, stream);
1490         }
1491
1492         result = dc_commit_state_no_check(dc, context);
1493
1494         return (result == DC_OK);
1495 }
1496
1497 #if defined(CONFIG_DRM_AMD_DC_DCN)
1498 bool dc_acquire_release_mpc_3dlut(
1499                 struct dc *dc, bool acquire,
1500                 struct dc_stream_state *stream,
1501                 struct dc_3dlut **lut,
1502                 struct dc_transfer_func **shaper)
1503 {
1504         int pipe_idx;
1505         bool ret = false;
1506         bool found_pipe_idx = false;
1507         const struct resource_pool *pool = dc->res_pool;
1508         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1509         int mpcc_id = 0;
1510
1511         if (pool && res_ctx) {
1512                 if (acquire) {
1513                         /*find pipe idx for the given stream*/
1514                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1515                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1516                                         found_pipe_idx = true;
1517                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1518                                         break;
1519                                 }
1520                         }
1521                 } else
1522                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1523
1524                 if (found_pipe_idx) {
1525                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1526                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1527                         else if (acquire == false && pool->funcs->release_post_bldn_3dlut)
1528                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1529                 }
1530         }
1531         return ret;
1532 }
1533 #endif
1534 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1535 {
1536         int i;
1537         struct pipe_ctx *pipe;
1538
1539         for (i = 0; i < MAX_PIPES; i++) {
1540                 pipe = &context->res_ctx.pipe_ctx[i];
1541
1542                 if (!pipe->plane_state)
1543                         continue;
1544
1545                 /* Must set to false to start with, due to OR in update function */
1546                 pipe->plane_state->status.is_flip_pending = false;
1547                 dc->hwss.update_pending_status(pipe);
1548                 if (pipe->plane_state->status.is_flip_pending)
1549                         return true;
1550         }
1551         return false;
1552 }
1553
1554 void dc_post_update_surfaces_to_stream(struct dc *dc)
1555 {
1556         int i;
1557         struct dc_state *context = dc->current_state;
1558
1559         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1560                 return;
1561
1562         post_surface_trace(dc);
1563
1564         if (is_flip_pending_in_pipes(dc, context))
1565                 return;
1566
1567         for (i = 0; i < dc->res_pool->pipe_count; i++)
1568                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1569                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1570                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1571                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1572                 }
1573
1574         dc->hwss.optimize_bandwidth(dc, context);
1575
1576         dc->optimized_required = false;
1577         dc->wm_optimized_required = false;
1578 }
1579
1580 static void init_state(struct dc *dc, struct dc_state *context)
1581 {
1582         /* Each context must have their own instance of VBA and in order to
1583          * initialize and obtain IP and SOC the base DML instance from DC is
1584          * initially copied into every context
1585          */
1586 #ifdef CONFIG_DRM_AMD_DC_DCN
1587         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1588 #endif
1589 }
1590
1591 struct dc_state *dc_create_state(struct dc *dc)
1592 {
1593         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1594                                             GFP_KERNEL);
1595
1596         if (!context)
1597                 return NULL;
1598
1599         init_state(dc, context);
1600
1601         kref_init(&context->refcount);
1602
1603         return context;
1604 }
1605
1606 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1607 {
1608         int i, j;
1609         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1610
1611         if (!new_ctx)
1612                 return NULL;
1613         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1614
1615         for (i = 0; i < MAX_PIPES; i++) {
1616                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1617
1618                         if (cur_pipe->top_pipe)
1619                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1620
1621                         if (cur_pipe->bottom_pipe)
1622                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1623
1624                         if (cur_pipe->prev_odm_pipe)
1625                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1626
1627                         if (cur_pipe->next_odm_pipe)
1628                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1629
1630         }
1631
1632         for (i = 0; i < new_ctx->stream_count; i++) {
1633                         dc_stream_retain(new_ctx->streams[i]);
1634                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1635                                 dc_plane_state_retain(
1636                                         new_ctx->stream_status[i].plane_states[j]);
1637         }
1638
1639         kref_init(&new_ctx->refcount);
1640
1641         return new_ctx;
1642 }
1643
1644 void dc_retain_state(struct dc_state *context)
1645 {
1646         kref_get(&context->refcount);
1647 }
1648
1649 static void dc_state_free(struct kref *kref)
1650 {
1651         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1652         dc_resource_state_destruct(context);
1653         kvfree(context);
1654 }
1655
1656 void dc_release_state(struct dc_state *context)
1657 {
1658         kref_put(&context->refcount, dc_state_free);
1659 }
1660
1661 bool dc_set_generic_gpio_for_stereo(bool enable,
1662                 struct gpio_service *gpio_service)
1663 {
1664         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1665         struct gpio_pin_info pin_info;
1666         struct gpio *generic;
1667         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1668                            GFP_KERNEL);
1669
1670         if (!config)
1671                 return false;
1672         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1673
1674         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1675                 kfree(config);
1676                 return false;
1677         } else {
1678                 generic = dal_gpio_service_create_generic_mux(
1679                         gpio_service,
1680                         pin_info.offset,
1681                         pin_info.mask);
1682         }
1683
1684         if (!generic) {
1685                 kfree(config);
1686                 return false;
1687         }
1688
1689         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1690
1691         config->enable_output_from_mux = enable;
1692         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1693
1694         if (gpio_result == GPIO_RESULT_OK)
1695                 gpio_result = dal_mux_setup_config(generic, config);
1696
1697         if (gpio_result == GPIO_RESULT_OK) {
1698                 dal_gpio_close(generic);
1699                 dal_gpio_destroy_generic_mux(&generic);
1700                 kfree(config);
1701                 return true;
1702         } else {
1703                 dal_gpio_close(generic);
1704                 dal_gpio_destroy_generic_mux(&generic);
1705                 kfree(config);
1706                 return false;
1707         }
1708 }
1709
1710 static bool is_surface_in_context(
1711                 const struct dc_state *context,
1712                 const struct dc_plane_state *plane_state)
1713 {
1714         int j;
1715
1716         for (j = 0; j < MAX_PIPES; j++) {
1717                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1718
1719                 if (plane_state == pipe_ctx->plane_state) {
1720                         return true;
1721                 }
1722         }
1723
1724         return false;
1725 }
1726
1727 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1728 {
1729         union surface_update_flags *update_flags = &u->surface->update_flags;
1730         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1731
1732         if (!u->plane_info)
1733                 return UPDATE_TYPE_FAST;
1734
1735         if (u->plane_info->color_space != u->surface->color_space) {
1736                 update_flags->bits.color_space_change = 1;
1737                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1738         }
1739
1740         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1741                 update_flags->bits.horizontal_mirror_change = 1;
1742                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1743         }
1744
1745         if (u->plane_info->rotation != u->surface->rotation) {
1746                 update_flags->bits.rotation_change = 1;
1747                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1748         }
1749
1750         if (u->plane_info->format != u->surface->format) {
1751                 update_flags->bits.pixel_format_change = 1;
1752                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1753         }
1754
1755         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1756                 update_flags->bits.stereo_format_change = 1;
1757                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1758         }
1759
1760         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1761                 update_flags->bits.per_pixel_alpha_change = 1;
1762                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1763         }
1764
1765         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1766                 update_flags->bits.global_alpha_change = 1;
1767                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1768         }
1769
1770         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1771                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1772                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1773                 update_flags->bits.dcc_change = 1;
1774                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1775         }
1776
1777         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1778                         resource_pixel_format_to_bpp(u->surface->format)) {
1779                 /* different bytes per element will require full bandwidth
1780                  * and DML calculation
1781                  */
1782                 update_flags->bits.bpp_change = 1;
1783                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1784         }
1785
1786         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1787                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1788                 update_flags->bits.plane_size_change = 1;
1789                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1790         }
1791
1792
1793         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1794                         sizeof(union dc_tiling_info)) != 0) {
1795                 update_flags->bits.swizzle_change = 1;
1796                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1797
1798                 /* todo: below are HW dependent, we should add a hook to
1799                  * DCE/N resource and validated there.
1800                  */
1801                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1802                         /* swizzled mode requires RQ to be setup properly,
1803                          * thus need to run DML to calculate RQ settings
1804                          */
1805                         update_flags->bits.bandwidth_change = 1;
1806                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1807                 }
1808         }
1809
1810         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1811         return update_type;
1812 }
1813
1814 static enum surface_update_type get_scaling_info_update_type(
1815                 const struct dc_surface_update *u)
1816 {
1817         union surface_update_flags *update_flags = &u->surface->update_flags;
1818
1819         if (!u->scaling_info)
1820                 return UPDATE_TYPE_FAST;
1821
1822         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1823                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1824                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1825                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1826                         || u->scaling_info->scaling_quality.integer_scaling !=
1827                                 u->surface->scaling_quality.integer_scaling
1828                         ) {
1829                 update_flags->bits.scaling_change = 1;
1830
1831                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1832                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1833                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1834                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1835                         /* Making dst rect smaller requires a bandwidth change */
1836                         update_flags->bits.bandwidth_change = 1;
1837         }
1838
1839         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1840                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1841
1842                 update_flags->bits.scaling_change = 1;
1843                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1844                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1845                         /* Making src rect bigger requires a bandwidth change */
1846                         update_flags->bits.clock_change = 1;
1847         }
1848
1849         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1850                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1851                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1852                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1853                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1854                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1855                 update_flags->bits.position_change = 1;
1856
1857         if (update_flags->bits.clock_change
1858                         || update_flags->bits.bandwidth_change
1859                         || update_flags->bits.scaling_change)
1860                 return UPDATE_TYPE_FULL;
1861
1862         if (update_flags->bits.position_change)
1863                 return UPDATE_TYPE_MED;
1864
1865         return UPDATE_TYPE_FAST;
1866 }
1867
1868 static enum surface_update_type det_surface_update(const struct dc *dc,
1869                 const struct dc_surface_update *u)
1870 {
1871         const struct dc_state *context = dc->current_state;
1872         enum surface_update_type type;
1873         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1874         union surface_update_flags *update_flags = &u->surface->update_flags;
1875
1876         if (u->flip_addr)
1877                 update_flags->bits.addr_update = 1;
1878
1879         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1880                 update_flags->raw = 0xFFFFFFFF;
1881                 return UPDATE_TYPE_FULL;
1882         }
1883
1884         update_flags->raw = 0; // Reset all flags
1885
1886         type = get_plane_info_update_type(u);
1887         elevate_update_type(&overall_type, type);
1888
1889         type = get_scaling_info_update_type(u);
1890         elevate_update_type(&overall_type, type);
1891
1892         if (u->flip_addr)
1893                 update_flags->bits.addr_update = 1;
1894
1895         if (u->in_transfer_func)
1896                 update_flags->bits.in_transfer_func_change = 1;
1897
1898         if (u->input_csc_color_matrix)
1899                 update_flags->bits.input_csc_change = 1;
1900
1901         if (u->coeff_reduction_factor)
1902                 update_flags->bits.coeff_reduction_change = 1;
1903
1904         if (u->gamut_remap_matrix)
1905                 update_flags->bits.gamut_remap_change = 1;
1906
1907         if (u->gamma) {
1908                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1909
1910                 if (u->plane_info)
1911                         format = u->plane_info->format;
1912                 else if (u->surface)
1913                         format = u->surface->format;
1914
1915                 if (dce_use_lut(format))
1916                         update_flags->bits.gamma_change = 1;
1917         }
1918
1919         if (u->hdr_mult.value)
1920                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1921                         update_flags->bits.hdr_mult = 1;
1922                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1923                 }
1924
1925         if (update_flags->bits.in_transfer_func_change) {
1926                 type = UPDATE_TYPE_MED;
1927                 elevate_update_type(&overall_type, type);
1928         }
1929
1930         if (update_flags->bits.input_csc_change
1931                         || update_flags->bits.coeff_reduction_change
1932                         || update_flags->bits.gamma_change
1933                         || update_flags->bits.gamut_remap_change) {
1934                 type = UPDATE_TYPE_FULL;
1935                 elevate_update_type(&overall_type, type);
1936         }
1937
1938         return overall_type;
1939 }
1940
1941 static enum surface_update_type check_update_surfaces_for_stream(
1942                 struct dc *dc,
1943                 struct dc_surface_update *updates,
1944                 int surface_count,
1945                 struct dc_stream_update *stream_update,
1946                 const struct dc_stream_status *stream_status)
1947 {
1948         int i;
1949         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1950
1951 #if defined(CONFIG_DRM_AMD_DC_DCN)
1952         if (dc->idle_optimizations_allowed)
1953                 overall_type = UPDATE_TYPE_FULL;
1954
1955 #endif
1956         if (stream_status == NULL || stream_status->plane_count != surface_count)
1957                 overall_type = UPDATE_TYPE_FULL;
1958
1959         /* some stream updates require passive update */
1960         if (stream_update) {
1961                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1962
1963                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1964                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1965                         stream_update->integer_scaling_update)
1966                         su_flags->bits.scaling = 1;
1967
1968                 if (stream_update->out_transfer_func)
1969                         su_flags->bits.out_tf = 1;
1970
1971                 if (stream_update->abm_level)
1972                         su_flags->bits.abm_level = 1;
1973
1974                 if (stream_update->dpms_off)
1975                         su_flags->bits.dpms_off = 1;
1976
1977                 if (stream_update->gamut_remap)
1978                         su_flags->bits.gamut_remap = 1;
1979
1980                 if (stream_update->wb_update)
1981                         su_flags->bits.wb_update = 1;
1982
1983                 if (stream_update->dsc_config)
1984                         su_flags->bits.dsc_changed = 1;
1985
1986                 if (su_flags->raw != 0)
1987                         overall_type = UPDATE_TYPE_FULL;
1988
1989                 if (stream_update->output_csc_transform || stream_update->output_color_space)
1990                         su_flags->bits.out_csc = 1;
1991         }
1992
1993         for (i = 0 ; i < surface_count; i++) {
1994                 enum surface_update_type type =
1995                                 det_surface_update(dc, &updates[i]);
1996
1997                 elevate_update_type(&overall_type, type);
1998         }
1999
2000         return overall_type;
2001 }
2002
2003 /**
2004  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2005  *
2006  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2007  */
2008 enum surface_update_type dc_check_update_surfaces_for_stream(
2009                 struct dc *dc,
2010                 struct dc_surface_update *updates,
2011                 int surface_count,
2012                 struct dc_stream_update *stream_update,
2013                 const struct dc_stream_status *stream_status)
2014 {
2015         int i;
2016         enum surface_update_type type;
2017
2018         if (stream_update)
2019                 stream_update->stream->update_flags.raw = 0;
2020         for (i = 0; i < surface_count; i++)
2021                 updates[i].surface->update_flags.raw = 0;
2022
2023         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2024         if (type == UPDATE_TYPE_FULL) {
2025                 if (stream_update) {
2026                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2027                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2028                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2029                 }
2030                 for (i = 0; i < surface_count; i++)
2031                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2032         }
2033
2034         if (type == UPDATE_TYPE_FAST) {
2035                 // If there's an available clock comparator, we use that.
2036                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2037                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2038                                 dc->optimized_required = true;
2039                 // Else we fallback to mem compare.
2040                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2041                         dc->optimized_required = true;
2042                 }
2043
2044                 dc->optimized_required |= dc->wm_optimized_required;
2045         }
2046
2047         return type;
2048 }
2049
2050 static struct dc_stream_status *stream_get_status(
2051         struct dc_state *ctx,
2052         struct dc_stream_state *stream)
2053 {
2054         uint8_t i;
2055
2056         for (i = 0; i < ctx->stream_count; i++) {
2057                 if (stream == ctx->streams[i]) {
2058                         return &ctx->stream_status[i];
2059                 }
2060         }
2061
2062         return NULL;
2063 }
2064
2065 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2066
2067 static void copy_surface_update_to_plane(
2068                 struct dc_plane_state *surface,
2069                 struct dc_surface_update *srf_update)
2070 {
2071         if (srf_update->flip_addr) {
2072                 surface->address = srf_update->flip_addr->address;
2073                 surface->flip_immediate =
2074                         srf_update->flip_addr->flip_immediate;
2075                 surface->time.time_elapsed_in_us[surface->time.index] =
2076                         srf_update->flip_addr->flip_timestamp_in_us -
2077                                 surface->time.prev_update_time_in_us;
2078                 surface->time.prev_update_time_in_us =
2079                         srf_update->flip_addr->flip_timestamp_in_us;
2080                 surface->time.index++;
2081                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2082                         surface->time.index = 0;
2083
2084                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2085         }
2086
2087         if (srf_update->scaling_info) {
2088                 surface->scaling_quality =
2089                                 srf_update->scaling_info->scaling_quality;
2090                 surface->dst_rect =
2091                                 srf_update->scaling_info->dst_rect;
2092                 surface->src_rect =
2093                                 srf_update->scaling_info->src_rect;
2094                 surface->clip_rect =
2095                                 srf_update->scaling_info->clip_rect;
2096         }
2097
2098         if (srf_update->plane_info) {
2099                 surface->color_space =
2100                                 srf_update->plane_info->color_space;
2101                 surface->format =
2102                                 srf_update->plane_info->format;
2103                 surface->plane_size =
2104                                 srf_update->plane_info->plane_size;
2105                 surface->rotation =
2106                                 srf_update->plane_info->rotation;
2107                 surface->horizontal_mirror =
2108                                 srf_update->plane_info->horizontal_mirror;
2109                 surface->stereo_format =
2110                                 srf_update->plane_info->stereo_format;
2111                 surface->tiling_info =
2112                                 srf_update->plane_info->tiling_info;
2113                 surface->visible =
2114                                 srf_update->plane_info->visible;
2115                 surface->per_pixel_alpha =
2116                                 srf_update->plane_info->per_pixel_alpha;
2117                 surface->global_alpha =
2118                                 srf_update->plane_info->global_alpha;
2119                 surface->global_alpha_value =
2120                                 srf_update->plane_info->global_alpha_value;
2121                 surface->dcc =
2122                                 srf_update->plane_info->dcc;
2123                 surface->layer_index =
2124                                 srf_update->plane_info->layer_index;
2125         }
2126
2127         if (srf_update->gamma &&
2128                         (surface->gamma_correction !=
2129                                         srf_update->gamma)) {
2130                 memcpy(&surface->gamma_correction->entries,
2131                         &srf_update->gamma->entries,
2132                         sizeof(struct dc_gamma_entries));
2133                 surface->gamma_correction->is_identity =
2134                         srf_update->gamma->is_identity;
2135                 surface->gamma_correction->num_entries =
2136                         srf_update->gamma->num_entries;
2137                 surface->gamma_correction->type =
2138                         srf_update->gamma->type;
2139         }
2140
2141         if (srf_update->in_transfer_func &&
2142                         (surface->in_transfer_func !=
2143                                 srf_update->in_transfer_func)) {
2144                 surface->in_transfer_func->sdr_ref_white_level =
2145                         srf_update->in_transfer_func->sdr_ref_white_level;
2146                 surface->in_transfer_func->tf =
2147                         srf_update->in_transfer_func->tf;
2148                 surface->in_transfer_func->type =
2149                         srf_update->in_transfer_func->type;
2150                 memcpy(&surface->in_transfer_func->tf_pts,
2151                         &srf_update->in_transfer_func->tf_pts,
2152                         sizeof(struct dc_transfer_func_distributed_points));
2153         }
2154
2155         if (srf_update->func_shaper &&
2156                         (surface->in_shaper_func !=
2157                         srf_update->func_shaper))
2158                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2159                 sizeof(*surface->in_shaper_func));
2160
2161         if (srf_update->lut3d_func &&
2162                         (surface->lut3d_func !=
2163                         srf_update->lut3d_func))
2164                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2165                 sizeof(*surface->lut3d_func));
2166
2167         if (srf_update->hdr_mult.value)
2168                 surface->hdr_mult =
2169                                 srf_update->hdr_mult;
2170
2171         if (srf_update->blend_tf &&
2172                         (surface->blend_tf !=
2173                         srf_update->blend_tf))
2174                 memcpy(surface->blend_tf, srf_update->blend_tf,
2175                 sizeof(*surface->blend_tf));
2176
2177         if (srf_update->input_csc_color_matrix)
2178                 surface->input_csc_color_matrix =
2179                         *srf_update->input_csc_color_matrix;
2180
2181         if (srf_update->coeff_reduction_factor)
2182                 surface->coeff_reduction_factor =
2183                         *srf_update->coeff_reduction_factor;
2184
2185         if (srf_update->gamut_remap_matrix)
2186                 surface->gamut_remap_matrix =
2187                         *srf_update->gamut_remap_matrix;
2188 }
2189
2190 static void copy_stream_update_to_stream(struct dc *dc,
2191                                          struct dc_state *context,
2192                                          struct dc_stream_state *stream,
2193                                          struct dc_stream_update *update)
2194 {
2195         struct dc_context *dc_ctx = dc->ctx;
2196
2197         if (update == NULL || stream == NULL)
2198                 return;
2199
2200         if (update->src.height && update->src.width)
2201                 stream->src = update->src;
2202
2203         if (update->dst.height && update->dst.width)
2204                 stream->dst = update->dst;
2205
2206         if (update->out_transfer_func &&
2207             stream->out_transfer_func != update->out_transfer_func) {
2208                 stream->out_transfer_func->sdr_ref_white_level =
2209                         update->out_transfer_func->sdr_ref_white_level;
2210                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2211                 stream->out_transfer_func->type =
2212                         update->out_transfer_func->type;
2213                 memcpy(&stream->out_transfer_func->tf_pts,
2214                        &update->out_transfer_func->tf_pts,
2215                        sizeof(struct dc_transfer_func_distributed_points));
2216         }
2217
2218         if (update->hdr_static_metadata)
2219                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2220
2221         if (update->abm_level)
2222                 stream->abm_level = *update->abm_level;
2223
2224         if (update->periodic_interrupt0)
2225                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2226
2227         if (update->periodic_interrupt1)
2228                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2229
2230         if (update->gamut_remap)
2231                 stream->gamut_remap_matrix = *update->gamut_remap;
2232
2233         /* Note: this being updated after mode set is currently not a use case
2234          * however if it arises OCSC would need to be reprogrammed at the
2235          * minimum
2236          */
2237         if (update->output_color_space)
2238                 stream->output_color_space = *update->output_color_space;
2239
2240         if (update->output_csc_transform)
2241                 stream->csc_color_matrix = *update->output_csc_transform;
2242
2243         if (update->vrr_infopacket)
2244                 stream->vrr_infopacket = *update->vrr_infopacket;
2245
2246         if (update->dpms_off)
2247                 stream->dpms_off = *update->dpms_off;
2248
2249         if (update->vsc_infopacket)
2250                 stream->vsc_infopacket = *update->vsc_infopacket;
2251
2252         if (update->vsp_infopacket)
2253                 stream->vsp_infopacket = *update->vsp_infopacket;
2254
2255         if (update->dither_option)
2256                 stream->dither_option = *update->dither_option;
2257         /* update current stream with writeback info */
2258         if (update->wb_update) {
2259                 int i;
2260
2261                 stream->num_wb_info = update->wb_update->num_wb_info;
2262                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2263                 for (i = 0; i < stream->num_wb_info; i++)
2264                         stream->writeback_info[i] =
2265                                 update->wb_update->writeback_info[i];
2266         }
2267         if (update->dsc_config) {
2268                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2269                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2270                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2271                                        update->dsc_config->num_slices_v != 0);
2272
2273                 /* Use temporarry context for validating new DSC config */
2274                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2275
2276                 if (dsc_validate_context) {
2277                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2278
2279                         stream->timing.dsc_cfg = *update->dsc_config;
2280                         stream->timing.flags.DSC = enable_dsc;
2281                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2282                                 stream->timing.dsc_cfg = old_dsc_cfg;
2283                                 stream->timing.flags.DSC = old_dsc_enabled;
2284                                 update->dsc_config = NULL;
2285                         }
2286
2287                         dc_release_state(dsc_validate_context);
2288                 } else {
2289                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2290                         update->dsc_config = NULL;
2291                 }
2292         }
2293 }
2294
2295 static void commit_planes_do_stream_update(struct dc *dc,
2296                 struct dc_stream_state *stream,
2297                 struct dc_stream_update *stream_update,
2298                 enum surface_update_type update_type,
2299                 struct dc_state *context)
2300 {
2301         int j;
2302         bool should_program_abm;
2303
2304         // Stream updates
2305         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2306                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2307
2308                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2309
2310                         if (stream_update->periodic_interrupt0 &&
2311                                         dc->hwss.setup_periodic_interrupt)
2312                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2313
2314                         if (stream_update->periodic_interrupt1 &&
2315                                         dc->hwss.setup_periodic_interrupt)
2316                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2317
2318                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2319                                         stream_update->vrr_infopacket ||
2320                                         stream_update->vsc_infopacket ||
2321                                         stream_update->vsp_infopacket) {
2322                                 resource_build_info_frame(pipe_ctx);
2323                                 dc->hwss.update_info_frame(pipe_ctx);
2324                         }
2325
2326                         if (stream_update->hdr_static_metadata &&
2327                                         stream->use_dynamic_meta &&
2328                                         dc->hwss.set_dmdata_attributes &&
2329                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2330                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2331
2332                         if (stream_update->gamut_remap)
2333                                 dc_stream_set_gamut_remap(dc, stream);
2334
2335                         if (stream_update->output_csc_transform)
2336                                 dc_stream_program_csc_matrix(dc, stream);
2337
2338                         if (stream_update->dither_option) {
2339                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2340                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2341                                                                         &pipe_ctx->stream->bit_depth_params);
2342                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2343                                                 &stream->bit_depth_params,
2344                                                 &stream->clamping);
2345                                 while (odm_pipe) {
2346                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2347                                                         &stream->bit_depth_params,
2348                                                         &stream->clamping);
2349                                         odm_pipe = odm_pipe->next_odm_pipe;
2350                                 }
2351                         }
2352
2353                         /* Full fe update*/
2354                         if (update_type == UPDATE_TYPE_FAST)
2355                                 continue;
2356
2357                         if (stream_update->dsc_config)
2358                                 dp_update_dsc_config(pipe_ctx);
2359
2360                         if (stream_update->dpms_off) {
2361                                 if (*stream_update->dpms_off) {
2362                                         core_link_disable_stream(pipe_ctx);
2363                                         /* for dpms, keep acquired resources*/
2364                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2365                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2366
2367                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2368                                 } else {
2369                                         if (dc->optimize_seamless_boot_streams == 0)
2370                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2371
2372                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2373                                 }
2374                         }
2375
2376                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2377                                 should_program_abm = true;
2378
2379                                 // if otg funcs defined check if blanked before programming
2380                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2381                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2382                                                 should_program_abm = false;
2383
2384                                 if (should_program_abm) {
2385                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2386                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2387                                         } else {
2388                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2389                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2390                                         }
2391                                 }
2392                         }
2393                 }
2394         }
2395 }
2396
2397 static void commit_planes_for_stream(struct dc *dc,
2398                 struct dc_surface_update *srf_updates,
2399                 int surface_count,
2400                 struct dc_stream_state *stream,
2401                 struct dc_stream_update *stream_update,
2402                 enum surface_update_type update_type,
2403                 struct dc_state *context)
2404 {
2405         int i, j;
2406         struct pipe_ctx *top_pipe_to_program = NULL;
2407
2408         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2409                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2410                  * first flip. After first flip, optimization is required to lower
2411                  * bandwidth. Important to note that it is expected UEFI will
2412                  * only light up a single display on POST, therefore we only expect
2413                  * one stream with seamless boot flag set.
2414                  */
2415                 if (stream->apply_seamless_boot_optimization) {
2416                         stream->apply_seamless_boot_optimization = false;
2417                         dc->optimize_seamless_boot_streams--;
2418
2419                         if (dc->optimize_seamless_boot_streams == 0)
2420                                 dc->optimized_required = true;
2421                 }
2422         }
2423
2424         if (update_type == UPDATE_TYPE_FULL) {
2425 #if defined(CONFIG_DRM_AMD_DC_DCN)
2426                 dc_allow_idle_optimizations(dc, false);
2427
2428 #endif
2429                 if (dc->optimize_seamless_boot_streams == 0)
2430                         dc->hwss.prepare_bandwidth(dc, context);
2431
2432                 context_clock_trace(dc, context);
2433         }
2434
2435         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2436                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2437
2438                 if (!pipe_ctx->top_pipe &&
2439                         !pipe_ctx->prev_odm_pipe &&
2440                         pipe_ctx->stream &&
2441                         pipe_ctx->stream == stream) {
2442                         top_pipe_to_program = pipe_ctx;
2443                 }
2444         }
2445
2446         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2447                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2448                         if (should_use_dmub_lock(stream->link)) {
2449                                 union dmub_hw_lock_flags hw_locks = { 0 };
2450                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2451
2452                                 hw_locks.bits.lock_dig = 1;
2453                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2454
2455                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2456                                                         true,
2457                                                         &hw_locks,
2458                                                         &inst_flags);
2459                         } else
2460                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2461                                                 top_pipe_to_program->stream_res.tg);
2462                 }
2463
2464         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2465                 dc->hwss.interdependent_update_lock(dc, context, true);
2466         else
2467                 /* Lock the top pipe while updating plane addrs, since freesync requires
2468                  *  plane addr update event triggers to be synchronized.
2469                  *  top_pipe_to_program is expected to never be NULL
2470                  */
2471                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2472
2473         // Stream updates
2474         if (stream_update)
2475                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2476
2477         if (surface_count == 0) {
2478                 /*
2479                  * In case of turning off screen, no need to program front end a second time.
2480                  * just return after program blank.
2481                  */
2482                 if (dc->hwss.apply_ctx_for_surface)
2483                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2484                 if (dc->hwss.program_front_end_for_ctx)
2485                         dc->hwss.program_front_end_for_ctx(dc, context);
2486
2487                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2488                         dc->hwss.interdependent_update_lock(dc, context, false);
2489                 else
2490                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2491
2492                 dc->hwss.post_unlock_program_front_end(dc, context);
2493                 return;
2494         }
2495
2496         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2497                 for (i = 0; i < surface_count; i++) {
2498                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2499                         /*set logical flag for lock/unlock use*/
2500                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2501                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2502                                 if (!pipe_ctx->plane_state)
2503                                         continue;
2504                                 if (pipe_ctx->plane_state != plane_state)
2505                                         continue;
2506                                 plane_state->triplebuffer_flips = false;
2507                                 if (update_type == UPDATE_TYPE_FAST &&
2508                                         dc->hwss.program_triplebuffer != NULL &&
2509                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2510                                                 /*triple buffer for VUpdate  only*/
2511                                                 plane_state->triplebuffer_flips = true;
2512                                 }
2513                         }
2514                 }
2515         }
2516
2517         // Update Type FULL, Surface updates
2518         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2519                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2520
2521                 if (!pipe_ctx->top_pipe &&
2522                         !pipe_ctx->prev_odm_pipe &&
2523                         pipe_ctx->stream &&
2524                         pipe_ctx->stream == stream) {
2525                         struct dc_stream_status *stream_status = NULL;
2526
2527                         if (!pipe_ctx->plane_state)
2528                                 continue;
2529
2530                         /* Full fe update*/
2531                         if (update_type == UPDATE_TYPE_FAST)
2532                                 continue;
2533
2534                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2535
2536                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2537                                 /*turn off triple buffer for full update*/
2538                                 dc->hwss.program_triplebuffer(
2539                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2540                         }
2541                         stream_status =
2542                                 stream_get_status(context, pipe_ctx->stream);
2543
2544                         if (dc->hwss.apply_ctx_for_surface)
2545                                 dc->hwss.apply_ctx_for_surface(
2546                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2547                 }
2548         }
2549         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2550                 dc->hwss.program_front_end_for_ctx(dc, context);
2551 #ifdef CONFIG_DRM_AMD_DC_DCN
2552                 if (dc->debug.validate_dml_output) {
2553                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2554                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2555                                 if (cur_pipe.stream == NULL)
2556                                         continue;
2557
2558                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2559                                                 cur_pipe.plane_res.hubp, dc->ctx,
2560                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2561                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2562                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2563                         }
2564                 }
2565 #endif
2566         }
2567
2568         // Update Type FAST, Surface updates
2569         if (update_type == UPDATE_TYPE_FAST) {
2570                 if (dc->hwss.set_flip_control_gsl)
2571                         for (i = 0; i < surface_count; i++) {
2572                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2573
2574                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2575                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2576
2577                                         if (pipe_ctx->stream != stream)
2578                                                 continue;
2579
2580                                         if (pipe_ctx->plane_state != plane_state)
2581                                                 continue;
2582
2583                                         // GSL has to be used for flip immediate
2584                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2585                                                         plane_state->flip_immediate);
2586                                 }
2587                         }
2588                 /* Perform requested Updates */
2589                 for (i = 0; i < surface_count; i++) {
2590                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2591
2592                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2593                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2594
2595                                 if (pipe_ctx->stream != stream)
2596                                         continue;
2597
2598                                 if (pipe_ctx->plane_state != plane_state)
2599                                         continue;
2600                                 /*program triple buffer after lock based on flip type*/
2601                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2602                                         /*only enable triplebuffer for  fast_update*/
2603                                         dc->hwss.program_triplebuffer(
2604                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2605                                 }
2606                                 if (srf_updates[i].flip_addr)
2607                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2608                         }
2609                 }
2610         }
2611
2612         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2613                 dc->hwss.interdependent_update_lock(dc, context, false);
2614         else
2615                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2616
2617         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2618                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2619                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2620                                         top_pipe_to_program->stream_res.tg,
2621                                         CRTC_STATE_VACTIVE);
2622                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2623                                         top_pipe_to_program->stream_res.tg,
2624                                         CRTC_STATE_VBLANK);
2625                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2626                                         top_pipe_to_program->stream_res.tg,
2627                                         CRTC_STATE_VACTIVE);
2628
2629                         if (stream && should_use_dmub_lock(stream->link)) {
2630                                 union dmub_hw_lock_flags hw_locks = { 0 };
2631                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2632
2633                                 hw_locks.bits.lock_dig = 1;
2634                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2635
2636                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2637                                                         false,
2638                                                         &hw_locks,
2639                                                         &inst_flags);
2640                         } else
2641                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2642                                         top_pipe_to_program->stream_res.tg);
2643                 }
2644
2645         if (update_type != UPDATE_TYPE_FAST)
2646                 dc->hwss.post_unlock_program_front_end(dc, context);
2647
2648         // Fire manual trigger only when bottom plane is flipped
2649         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2650                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2651
2652                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2653                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2654                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2655                         continue;
2656
2657                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2658                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2659         }
2660 }
2661
2662 void dc_commit_updates_for_stream(struct dc *dc,
2663                 struct dc_surface_update *srf_updates,
2664                 int surface_count,
2665                 struct dc_stream_state *stream,
2666                 struct dc_stream_update *stream_update,
2667                 struct dc_state *state)
2668 {
2669         const struct dc_stream_status *stream_status;
2670         enum surface_update_type update_type;
2671         struct dc_state *context;
2672         struct dc_context *dc_ctx = dc->ctx;
2673         int i, j;
2674
2675         stream_status = dc_stream_get_status(stream);
2676         context = dc->current_state;
2677
2678         update_type = dc_check_update_surfaces_for_stream(
2679                                 dc, srf_updates, surface_count, stream_update, stream_status);
2680
2681         if (update_type >= update_surface_trace_level)
2682                 update_surface_trace(dc, srf_updates, surface_count);
2683
2684
2685         if (update_type >= UPDATE_TYPE_FULL) {
2686
2687                 /* initialize scratch memory for building context */
2688                 context = dc_create_state(dc);
2689                 if (context == NULL) {
2690                         DC_ERROR("Failed to allocate new validate context!\n");
2691                         return;
2692                 }
2693
2694                 dc_resource_state_copy_construct(state, context);
2695
2696                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2697                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2698                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2699
2700                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2701                                 new_pipe->plane_state->force_full_update = true;
2702                 }
2703         }
2704
2705
2706         for (i = 0; i < surface_count; i++) {
2707                 struct dc_plane_state *surface = srf_updates[i].surface;
2708
2709                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2710
2711                 if (update_type >= UPDATE_TYPE_MED) {
2712                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2713                                 struct pipe_ctx *pipe_ctx =
2714                                         &context->res_ctx.pipe_ctx[j];
2715
2716                                 if (pipe_ctx->plane_state != surface)
2717                                         continue;
2718
2719                                 resource_build_scaling_params(pipe_ctx);
2720                         }
2721                 }
2722         }
2723
2724         copy_stream_update_to_stream(dc, context, stream, stream_update);
2725
2726         if (update_type >= UPDATE_TYPE_FULL) {
2727                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2728                         DC_ERROR("Mode validation failed for stream update!\n");
2729                         dc_release_state(context);
2730                         return;
2731                 }
2732         }
2733
2734         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2735
2736         commit_planes_for_stream(
2737                                 dc,
2738                                 srf_updates,
2739                                 surface_count,
2740                                 stream,
2741                                 stream_update,
2742                                 update_type,
2743                                 context);
2744         /*update current_State*/
2745         if (dc->current_state != context) {
2746
2747                 struct dc_state *old = dc->current_state;
2748
2749                 dc->current_state = context;
2750                 dc_release_state(old);
2751
2752                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2753                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2754
2755                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2756                                 pipe_ctx->plane_state->force_full_update = false;
2757                 }
2758         }
2759         /*let's use current_state to update watermark etc*/
2760         if (update_type >= UPDATE_TYPE_FULL) {
2761                 dc_post_update_surfaces_to_stream(dc);
2762
2763                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
2764                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2765                 else
2766                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2767         }
2768
2769         return;
2770
2771 }
2772
2773 uint8_t dc_get_current_stream_count(struct dc *dc)
2774 {
2775         return dc->current_state->stream_count;
2776 }
2777
2778 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2779 {
2780         if (i < dc->current_state->stream_count)
2781                 return dc->current_state->streams[i];
2782         return NULL;
2783 }
2784
2785 enum dc_irq_source dc_interrupt_to_irq_source(
2786                 struct dc *dc,
2787                 uint32_t src_id,
2788                 uint32_t ext_id)
2789 {
2790         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2791 }
2792
2793 /**
2794  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2795  */
2796 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2797 {
2798
2799         if (dc == NULL)
2800                 return false;
2801
2802         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2803 }
2804
2805 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2806 {
2807         dal_irq_service_ack(dc->res_pool->irqs, src);
2808 }
2809
2810 void dc_power_down_on_boot(struct dc *dc)
2811 {
2812         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
2813                         dc->hwss.power_down_on_boot)
2814                 dc->hwss.power_down_on_boot(dc);
2815 }
2816
2817 void dc_set_power_state(
2818         struct dc *dc,
2819         enum dc_acpi_cm_power_state power_state)
2820 {
2821         struct kref refcount;
2822         struct display_mode_lib *dml;
2823
2824         switch (power_state) {
2825         case DC_ACPI_CM_POWER_STATE_D0:
2826                 dc_resource_state_construct(dc, dc->current_state);
2827
2828                 if (dc->ctx->dmub_srv)
2829                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2830
2831                 dc->hwss.init_hw(dc);
2832
2833                 if (dc->hwss.init_sys_ctx != NULL &&
2834                         dc->vm_pa_config.valid) {
2835                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2836                 }
2837
2838                 break;
2839         default:
2840                 ASSERT(dc->current_state->stream_count == 0);
2841                 /* Zero out the current context so that on resume we start with
2842                  * clean state, and dc hw programming optimizations will not
2843                  * cause any trouble.
2844                  */
2845                 dml = kzalloc(sizeof(struct display_mode_lib),
2846                                 GFP_KERNEL);
2847
2848                 ASSERT(dml);
2849                 if (!dml)
2850                         return;
2851
2852                 /* Preserve refcount */
2853                 refcount = dc->current_state->refcount;
2854                 /* Preserve display mode lib */
2855                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2856
2857                 dc_resource_state_destruct(dc->current_state);
2858                 memset(dc->current_state, 0,
2859                                 sizeof(*dc->current_state));
2860
2861                 dc->current_state->refcount = refcount;
2862                 dc->current_state->bw_ctx.dml = *dml;
2863
2864                 kfree(dml);
2865
2866                 break;
2867         }
2868 }
2869
2870 void dc_resume(struct dc *dc)
2871 {
2872         uint32_t i;
2873
2874         for (i = 0; i < dc->link_count; i++)
2875                 core_link_resume(dc->links[i]);
2876 }
2877
2878 bool dc_is_dmcu_initialized(struct dc *dc)
2879 {
2880         struct dmcu *dmcu = dc->res_pool->dmcu;
2881
2882         if (dmcu)
2883                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2884         return false;
2885 }
2886
2887 bool dc_submit_i2c(
2888                 struct dc *dc,
2889                 uint32_t link_index,
2890                 struct i2c_command *cmd)
2891 {
2892
2893         struct dc_link *link = dc->links[link_index];
2894         struct ddc_service *ddc = link->ddc;
2895         return dce_i2c_submit_command(
2896                 dc->res_pool,
2897                 ddc->ddc_pin,
2898                 cmd);
2899 }
2900
2901 bool dc_submit_i2c_oem(
2902                 struct dc *dc,
2903                 struct i2c_command *cmd)
2904 {
2905         struct ddc_service *ddc = dc->res_pool->oem_device;
2906         return dce_i2c_submit_command(
2907                 dc->res_pool,
2908                 ddc->ddc_pin,
2909                 cmd);
2910 }
2911
2912 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2913 {
2914         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2915                 BREAK_TO_DEBUGGER();
2916                 return false;
2917         }
2918
2919         dc_sink_retain(sink);
2920
2921         dc_link->remote_sinks[dc_link->sink_count] = sink;
2922         dc_link->sink_count++;
2923
2924         return true;
2925 }
2926
2927 /**
2928  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2929  *
2930  * EDID length is in bytes
2931  */
2932 struct dc_sink *dc_link_add_remote_sink(
2933                 struct dc_link *link,
2934                 const uint8_t *edid,
2935                 int len,
2936                 struct dc_sink_init_data *init_data)
2937 {
2938         struct dc_sink *dc_sink;
2939         enum dc_edid_status edid_status;
2940
2941         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2942                 dm_error("Max EDID buffer size breached!\n");
2943                 return NULL;
2944         }
2945
2946         if (!init_data) {
2947                 BREAK_TO_DEBUGGER();
2948                 return NULL;
2949         }
2950
2951         if (!init_data->link) {
2952                 BREAK_TO_DEBUGGER();
2953                 return NULL;
2954         }
2955
2956         dc_sink = dc_sink_create(init_data);
2957
2958         if (!dc_sink)
2959                 return NULL;
2960
2961         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2962         dc_sink->dc_edid.length = len;
2963
2964         if (!link_add_remote_sink_helper(
2965                         link,
2966                         dc_sink))
2967                 goto fail_add_sink;
2968
2969         edid_status = dm_helpers_parse_edid_caps(
2970                         link->ctx,
2971                         &dc_sink->dc_edid,
2972                         &dc_sink->edid_caps);
2973
2974         /*
2975          * Treat device as no EDID device if EDID
2976          * parsing fails
2977          */
2978         if (edid_status != EDID_OK) {
2979                 dc_sink->dc_edid.length = 0;
2980                 dm_error("Bad EDID, status%d!\n", edid_status);
2981         }
2982
2983         return dc_sink;
2984
2985 fail_add_sink:
2986         dc_sink_release(dc_sink);
2987         return NULL;
2988 }
2989
2990 /**
2991  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2992  *
2993  * Note that this just removes the struct dc_sink - it doesn't
2994  * program hardware or alter other members of dc_link
2995  */
2996 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2997 {
2998         int i;
2999
3000         if (!link->sink_count) {
3001                 BREAK_TO_DEBUGGER();
3002                 return;
3003         }
3004
3005         for (i = 0; i < link->sink_count; i++) {
3006                 if (link->remote_sinks[i] == sink) {
3007                         dc_sink_release(sink);
3008                         link->remote_sinks[i] = NULL;
3009
3010                         /* shrink array to remove empty place */
3011                         while (i < link->sink_count - 1) {
3012                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3013                                 i++;
3014                         }
3015                         link->remote_sinks[i] = NULL;
3016                         link->sink_count--;
3017                         return;
3018                 }
3019         }
3020 }
3021
3022 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3023 {
3024         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3025         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3026         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3027         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3028         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3029         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3030         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3031         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3032         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3033 }
3034 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3035 {
3036         if (dc->hwss.set_clock)
3037                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3038         return DC_ERROR_UNEXPECTED;
3039 }
3040 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3041 {
3042         if (dc->hwss.get_clock)
3043                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3044 }
3045
3046 /* enable/disable eDP PSR without specify stream for eDP */
3047 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3048 {
3049         int i;
3050
3051         for (i = 0; i < dc->current_state->stream_count ; i++) {
3052                 struct dc_link *link;
3053                 struct dc_stream_state *stream = dc->current_state->streams[i];
3054
3055                 link = stream->link;
3056                 if (!link)
3057                         continue;
3058
3059                 if (link->psr_settings.psr_feature_enabled) {
3060                         if (enable && !link->psr_settings.psr_allow_active)
3061                                 return dc_link_set_psr_allow_active(link, true, false);
3062                         else if (!enable && link->psr_settings.psr_allow_active)
3063                                 return dc_link_set_psr_allow_active(link, false, true);
3064                 }
3065         }
3066
3067         return true;
3068 }
3069
3070 #if defined(CONFIG_DRM_AMD_DC_DCN)
3071
3072 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3073 {
3074         if (dc->debug.disable_idle_power_optimizations)
3075                 return;
3076
3077         if (allow == dc->idle_optimizations_allowed)
3078                 return;
3079
3080         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3081                 dc->idle_optimizations_allowed = allow;
3082 }
3083
3084 /*
3085  * blank all streams, and set min and max memory clock to
3086  * lowest and highest DPM level, respectively
3087  */
3088 void dc_unlock_memory_clock_frequency(struct dc *dc)
3089 {
3090         unsigned int i;
3091
3092         for (i = 0; i < MAX_PIPES; i++)
3093                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3094                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3095
3096         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3097         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3098 }
3099
3100 /*
3101  * set min memory clock to the min required for current mode,
3102  * max to maxDPM, and unblank streams
3103  */
3104 void dc_lock_memory_clock_frequency(struct dc *dc)
3105 {
3106         unsigned int i;
3107
3108         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3109         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3110         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3111
3112         for (i = 0; i < MAX_PIPES; i++)
3113                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3114                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3115 }
3116
3117 bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,
3118                                                  struct dc_plane_state *plane)
3119 {
3120         return false;
3121 }
3122
3123 /* cleanup on driver unload */
3124 void dc_hardware_release(struct dc *dc)
3125 {
3126         if (dc->hwss.hardware_release)
3127                 dc->hwss.hardware_release(dc);
3128 }
3129 #endif