drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61
  62 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  63 #include "dsc.h"
  64 #endif
  65
  66 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
  67 #include "vm_helper.h"
  68 #endif
  69
  70 #include "dce/dce_i2c.h"
  71
  72 #define DC_LOGGER \
  73         dc->ctx->logger
  74
  75 const static char DC_BUILD_ID[] = "production-build";
  76
  77 /**
  78  * DOC: Overview
  79  *
  80  * DC is the OS-agnostic component of the amdgpu DC driver.
  81  *
  82  * DC maintains and validates a set of structs representing the state of the
  83  * driver and writes that state to AMD hardware
  84  *
  85  * Main DC HW structs:
  86  *
  87  * struct dc - The central struct.  One per driver.  Created on driver load,
  88  * destroyed on driver unload.
  89  *
  90  * struct dc_context - One per driver.
  91  * Used as a backpointer by most other structs in dc.
  92  *
  93  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  94  * plugpoints).  Created on driver load, destroyed on driver unload.
  95  *
  96  * struct dc_sink - One per display.  Created on boot or hotplug.
  97  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
  98  * (the display directly attached).  It may also have one or more remote
  99  * sinks (in the Multi-Stream Transport case)
 100  *
 101  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 102  * main pipeline.  Not directly accessible by dm.
 103  *
 104  * Main dc state structs:
 105  *
 106  * These structs can be created and destroyed as needed.  There is a full set of
 107  * these structs in dc->current_state representing the currently programmed state.
 108  *
 109  * struct dc_state - The global DC state to track global state information,
 110  * such as bandwidth values.
 111  *
 112  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 113  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 114  *
 115  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 116  * and may have more in the Multi-Plane Overlay case.
 117  *
 118  * struct resource_context - Represents the programmable state of everything in
 119  * the resource_pool.  Not directly accessible by dm.
 120  *
 121  * struct pipe_ctx - A member of struct resource_context.  Represents the
 122  * internal hardware pipeline components.  Each dc_plane_state has either
 123  * one or two (in the pipe-split case).
 124  */
 125
 126 /*******************************************************************************
 127  * Private functions
 128  ******************************************************************************/
 129
 130 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 131 {
 132         if (new > *original)
 133                 *original = new;
 134 }
 135
 136 static void destroy_links(struct dc *dc)
 137 {
 138         uint32_t i;
 139
 140         for (i = 0; i < dc->link_count; i++) {
 141                 if (NULL != dc->links[i])
 142                         link_destroy(&dc->links[i]);
 143         }
 144 }
 145
 146 static bool create_links(
 147                 struct dc *dc,
 148                 uint32_t num_virtual_links)
 149 {
 150         int i;
 151         int connectors_num;
 152         struct dc_bios *bios = dc->ctx->dc_bios;
 153
 154         dc->link_count = 0;
 155
 156         connectors_num = bios->funcs->get_connectors_number(bios);
 157
 158         if (connectors_num > ENUM_ID_COUNT) {
 159                 dm_error(
 160                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 161                         connectors_num,
 162                         ENUM_ID_COUNT);
 163                 return false;
 164         }
 165
 166         dm_output_to_console(
 167                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 168                 __func__,
 169                 connectors_num,
 170                 num_virtual_links);
 171
 172         for (i = 0; i < connectors_num; i++) {
 173                 struct link_init_data link_init_params = {0};
 174                 struct dc_link *link;
 175
 176                 link_init_params.ctx = dc->ctx;
 177                 /* next BIOS object table connector */
 178                 link_init_params.connector_index = i;
 179                 link_init_params.link_index = dc->link_count;
 180                 link_init_params.dc = dc;
 181                 link = link_create(&link_init_params);
 182
 183                 if (link) {
 184                         bool should_destory_link = false;
 185
 186                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 187                                 if (dc->config.edp_not_connected)
 188                                         should_destory_link = true;
 189                                 else if (dc->debug.remove_disconnect_edp) {
 190                                         enum dc_connection_type type;
 191                                         dc_link_detect_sink(link, &type);
 192                                         if (type == dc_connection_none)
 193                                                 should_destory_link = true;
 194                                 }
 195                         }
 196
 197                         if (!should_destory_link) {
 198                                 dc->links[dc->link_count] = link;
 199                                 link->dc = dc;
 200                                 ++dc->link_count;
 201                         } else {
 202                                 link_destroy(&link);
 203                         }
 204                 }
 205         }
 206
 207         for (i = 0; i < num_virtual_links; i++) {
 208                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 209                 struct encoder_init_data enc_init = {0};
 210
 211                 if (link == NULL) {
 212                         BREAK_TO_DEBUGGER();
 213                         goto failed_alloc;
 214                 }
 215
 216                 link->link_index = dc->link_count;
 217                 dc->links[dc->link_count] = link;
 218                 dc->link_count++;
 219
 220                 link->ctx = dc->ctx;
 221                 link->dc = dc;
 222                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 223                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 224                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 225                 link->link_id.enum_id = ENUM_ID_1;
 226                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 227
 228                 if (!link->link_enc) {
 229                         BREAK_TO_DEBUGGER();
 230                         goto failed_alloc;
 231                 }
 232
 233                 link->link_status.dpcd_caps = &link->dpcd_caps;
 234
 235                 enc_init.ctx = dc->ctx;
 236                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 237                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 238                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 239                 enc_init.connector = link->link_id;
 240                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 241                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 242                 enc_init.encoder.enum_id = ENUM_ID_1;
 243                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 244         }
 245
 246         return true;
 247
 248 failed_alloc:
 249         return false;
 250 }
 251
 252 static struct dc_perf_trace *dc_perf_trace_create(void)
 253 {
 254         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 255 }
 256
 257 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 258 {
 259         kfree(*perf_trace);
 260         *perf_trace = NULL;
 261 }
 262
 263 /**
 264  *****************************************************************************
 265  *  Function: dc_stream_adjust_vmin_vmax
 266  *
 267  *  @brief
 268  *     Looks up the pipe context of dc_stream_state and updates the
 269  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 270  *     Rate, which is a power-saving feature that targets reducing panel
 271  *     refresh rate while the screen is static
 272  *
 273  *  @param [in] dc: dc reference
 274  *  @param [in] stream: Initial dc stream state
 275  *  @param [in] adjust: Updated parameters for vertical_total_min and
 276  *  vertical_total_max
 277  *****************************************************************************
 278  */
 279 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 280                 struct dc_stream_state *stream,
 281                 struct dc_crtc_timing_adjust *adjust)
 282 {
 283         int i = 0;
 284         bool ret = false;
 285
 286         for (i = 0; i < MAX_PIPES; i++) {
 287                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 288
 289                 if (pipe->stream == stream && pipe->stream_res.tg) {
 290                         pipe->stream->adjust = *adjust;
 291                         dc->hwss.set_drr(&pipe,
 292                                         1,
 293                                         adjust->v_total_min,
 294                                         adjust->v_total_max,
 295                                         adjust->v_total_mid,
 296                                         adjust->v_total_mid_frame_num);
 297
 298                         ret = true;
 299                 }
 300         }
 301         return ret;
 302 }
 303
 304 bool dc_stream_get_crtc_position(struct dc *dc,
 305                 struct dc_stream_state **streams, int num_streams,
 306                 unsigned int *v_pos, unsigned int *nom_v_pos)
 307 {
 308         /* TODO: Support multiple streams */
 309         const struct dc_stream_state *stream = streams[0];
 310         int i = 0;
 311         bool ret = false;
 312         struct crtc_position position;
 313
 314         for (i = 0; i < MAX_PIPES; i++) {
 315                 struct pipe_ctx *pipe =
 316                                 &dc->current_state->res_ctx.pipe_ctx[i];
 317
 318                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 319                         dc->hwss.get_position(&pipe, 1, &position);
 320
 321                         *v_pos = position.vertical_count;
 322                         *nom_v_pos = position.nominal_vcount;
 323                         ret = true;
 324                 }
 325         }
 326         return ret;
 327 }
 328
 329 /**
 330  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 331  * @dc: DC Object
 332  * @stream: The stream to configure CRC on.
 333  * @enable: Enable CRC if true, disable otherwise.
 334  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 335  *              once.
 336  *
 337  * By default, only CRC0 is configured, and the entire frame is used to
 338  * calculate the crc.
 339  */
 340 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 341                              bool enable, bool continuous)
 342 {
 343         int i;
 344         struct pipe_ctx *pipe;
 345         struct crc_params param;
 346         struct timing_generator *tg;
 347
 348         for (i = 0; i < MAX_PIPES; i++) {
 349                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 350                 if (pipe->stream == stream)
 351                         break;
 352         }
 353         /* Stream not found */
 354         if (i == MAX_PIPES)
 355                 return false;
 356
 357         /* Always capture the full frame */
 358         param.windowa_x_start = 0;
 359         param.windowa_y_start = 0;
 360         param.windowa_x_end = pipe->stream->timing.h_addressable;
 361         param.windowa_y_end = pipe->stream->timing.v_addressable;
 362         param.windowb_x_start = 0;
 363         param.windowb_y_start = 0;
 364         param.windowb_x_end = pipe->stream->timing.h_addressable;
 365         param.windowb_y_end = pipe->stream->timing.v_addressable;
 366
 367         /* Default to the union of both windows */
 368         param.selection = UNION_WINDOW_A_B;
 369         param.continuous_mode = continuous;
 370         param.enable = enable;
 371
 372         tg = pipe->stream_res.tg;
 373
 374         /* Only call if supported */
 375         if (tg->funcs->configure_crc)
 376                 return tg->funcs->configure_crc(tg, &param);
 377         DC_LOG_WARNING("CRC capture not supported.");
 378         return false;
 379 }
 380
 381 /**
 382  * dc_stream_get_crc() - Get CRC values for the given stream.
 383  * @dc: DC object
 384  * @stream: The DC stream state of the stream to get CRCs from.
 385  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 386  *
 387  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 388  * Return false if stream is not found, or if CRCs are not enabled.
 389  */
 390 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 391                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 392 {
 393         int i;
 394         struct pipe_ctx *pipe;
 395         struct timing_generator *tg;
 396
 397         for (i = 0; i < MAX_PIPES; i++) {
 398                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 399                 if (pipe->stream == stream)
 400                         break;
 401         }
 402         /* Stream not found */
 403         if (i == MAX_PIPES)
 404                 return false;
 405
 406         tg = pipe->stream_res.tg;
 407
 408         if (tg->funcs->get_crc)
 409                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 410         DC_LOG_WARNING("CRC capture not supported.");
 411         return false;
 412 }
 413
 414 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 415                 enum dc_dither_option option)
 416 {
 417         struct bit_depth_reduction_params params;
 418         struct dc_link *link = stream->link;
 419         struct pipe_ctx *pipes = NULL;
 420         int i;
 421
 422         for (i = 0; i < MAX_PIPES; i++) {
 423                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 424                                 stream) {
 425                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 426                         break;
 427                 }
 428         }
 429
 430         if (!pipes)
 431                 return;
 432         if (option > DITHER_OPTION_MAX)
 433                 return;
 434
 435         stream->dither_option = option;
 436
 437         memset(&params, 0, sizeof(params));
 438         resource_build_bit_depth_reduction_params(stream, &params);
 439         stream->bit_depth_params = params;
 440
 441         if (pipes->plane_res.xfm &&
 442             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 443                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 444                         pipes->plane_res.xfm,
 445                         pipes->plane_res.scl_data.lb_params.depth,
 446                         &stream->bit_depth_params);
 447         }
 448
 449         pipes->stream_res.opp->funcs->
 450                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 451 }
 452
 453 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 454 {
 455         int i = 0;
 456         bool ret = false;
 457         struct pipe_ctx *pipes;
 458
 459         for (i = 0; i < MAX_PIPES; i++) {
 460                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 461                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 462                         dc->hwss.program_gamut_remap(pipes);
 463                         ret = true;
 464                 }
 465         }
 466
 467         return ret;
 468 }
 469
 470 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 471 {
 472         int i = 0;
 473         bool ret = false;
 474         struct pipe_ctx *pipes;
 475
 476         for (i = 0; i < MAX_PIPES; i++) {
 477                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 478                                 == stream) {
 479
 480                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 481                         dc->hwss.program_output_csc(dc,
 482                                         pipes,
 483                                         stream->output_color_space,
 484                                         stream->csc_color_matrix.matrix,
 485                                         pipes->stream_res.opp->inst);
 486                         ret = true;
 487                 }
 488         }
 489
 490         return ret;
 491 }
 492
 493 void dc_stream_set_static_screen_events(struct dc *dc,
 494                 struct dc_stream_state **streams,
 495                 int num_streams,
 496                 const struct dc_static_screen_events *events)
 497 {
 498         int i = 0;
 499         int j = 0;
 500         struct pipe_ctx *pipes_affected[MAX_PIPES];
 501         int num_pipes_affected = 0;
 502
 503         for (i = 0; i < num_streams; i++) {
 504                 struct dc_stream_state *stream = streams[i];
 505
 506                 for (j = 0; j < MAX_PIPES; j++) {
 507                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 508                                         == stream) {
 509                                 pipes_affected[num_pipes_affected++] =
 510                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 511                         }
 512                 }
 513         }
 514
 515         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 516 }
 517
 518 static void destruct(struct dc *dc)
 519 {
 520         if (dc->current_state) {
 521                 dc_release_state(dc->current_state);
 522                 dc->current_state = NULL;
 523         }
 524
 525         destroy_links(dc);
 526
 527         if (dc->clk_mgr) {
 528                 dc_destroy_clk_mgr(dc->clk_mgr);
 529                 dc->clk_mgr = NULL;
 530         }
 531
 532         dc_destroy_resource_pool(dc);
 533
 534         if (dc->ctx->gpio_service)
 535                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 536
 537         if (dc->ctx->created_bios)
 538                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 539
 540         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 541
 542         kfree(dc->ctx);
 543         dc->ctx = NULL;
 544
 545         kfree(dc->bw_vbios);
 546         dc->bw_vbios = NULL;
 547
 548         kfree(dc->bw_dceip);
 549         dc->bw_dceip = NULL;
 550
 551 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 552         kfree(dc->dcn_soc);
 553         dc->dcn_soc = NULL;
 554
 555         kfree(dc->dcn_ip);
 556         dc->dcn_ip = NULL;
 557
 558 #endif
 559 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 560         kfree(dc->vm_helper);
 561         dc->vm_helper = NULL;
 562
 563 #endif
 564 }
 565
 566 static bool construct(struct dc *dc,
 567                 const struct dc_init_data *init_params)
 568 {
 569         struct dc_context *dc_ctx;
 570         struct bw_calcs_dceip *dc_dceip;
 571         struct bw_calcs_vbios *dc_vbios;
 572 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 573         struct dcn_soc_bounding_box *dcn_soc;
 574         struct dcn_ip_params *dcn_ip;
 575 #endif
 576
 577         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 578         dc->config = init_params->flags;
 579
 580 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 581         // Allocate memory for the vm_helper
 582         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 583
 584 #endif
 585         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 586
 587         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 588         if (!dc_dceip) {
 589                 dm_error("%s: failed to create dceip\n", __func__);
 590                 goto fail;
 591         }
 592
 593         dc->bw_dceip = dc_dceip;
 594
 595         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 596         if (!dc_vbios) {
 597                 dm_error("%s: failed to create vbios\n", __func__);
 598                 goto fail;
 599         }
 600
 601         dc->bw_vbios = dc_vbios;
 602 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 603         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 604         if (!dcn_soc) {
 605                 dm_error("%s: failed to create dcn_soc\n", __func__);
 606                 goto fail;
 607         }
 608
 609         dc->dcn_soc = dcn_soc;
 610
 611         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 612         if (!dcn_ip) {
 613                 dm_error("%s: failed to create dcn_ip\n", __func__);
 614                 goto fail;
 615         }
 616
 617         dc->dcn_ip = dcn_ip;
 618 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 619         dc->soc_bounding_box = init_params->soc_bounding_box;
 620 #endif
 621 #endif
 622
 623         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 624         if (!dc_ctx) {
 625                 dm_error("%s: failed to create ctx\n", __func__);
 626                 goto fail;
 627         }
 628
 629         dc_ctx->cgs_device = init_params->cgs_device;
 630         dc_ctx->driver_context = init_params->driver;
 631         dc_ctx->dc = dc;
 632         dc_ctx->asic_id = init_params->asic_id;
 633         dc_ctx->dc_sink_id_count = 0;
 634         dc_ctx->dc_stream_id_count = 0;
 635         dc->ctx = dc_ctx;
 636
 637         /* Create logger */
 638
 639         dc_ctx->dce_environment = init_params->dce_environment;
 640
 641         dc_version = resource_parse_asic_id(init_params->asic_id);
 642         dc_ctx->dce_version = dc_version;
 643
 644         /* Resource should construct all asic specific resources.
 645          * This should be the only place where we need to parse the asic id
 646          */
 647         if (init_params->vbios_override)
 648                 dc_ctx->dc_bios = init_params->vbios_override;
 649         else {
 650                 /* Create BIOS parser */
 651                 struct bp_init_data bp_init_data;
 652
 653                 bp_init_data.ctx = dc_ctx;
 654                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 655
 656                 dc_ctx->dc_bios = dal_bios_parser_create(
 657                                 &bp_init_data, dc_version);
 658
 659                 if (!dc_ctx->dc_bios) {
 660                         ASSERT_CRITICAL(false);
 661                         goto fail;
 662                 }
 663
 664                 dc_ctx->created_bios = true;
 665                 }
 666
 667         dc_ctx->perf_trace = dc_perf_trace_create();
 668         if (!dc_ctx->perf_trace) {
 669                 ASSERT_CRITICAL(false);
 670                 goto fail;
 671         }
 672
 673         /* Create GPIO service */
 674         dc_ctx->gpio_service = dal_gpio_service_create(
 675                         dc_version,
 676                         dc_ctx->dce_environment,
 677                         dc_ctx);
 678
 679         if (!dc_ctx->gpio_service) {
 680                 ASSERT_CRITICAL(false);
 681                 goto fail;
 682         }
 683
 684         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
 685         if (!dc->res_pool)
 686                 goto fail;
 687
 688         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 689         if (!dc->clk_mgr)
 690                 goto fail;
 691
 692 #ifdef CONFIG_DRM_AMD_DC_DCN2_1
 693         if (dc->res_pool->funcs->update_bw_bounding_box)
 694                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 695 #endif
 696
 697         /* Creation of current_state must occur after dc->dml
 698          * is initialized in dc_create_resource_pool because
 699          * on creation it copies the contents of dc->dml
 700          */
 701
 702         dc->current_state = dc_create_state(dc);
 703
 704         if (!dc->current_state) {
 705                 dm_error("%s: failed to create validate ctx\n", __func__);
 706                 goto fail;
 707         }
 708
 709         dc_resource_state_construct(dc, dc->current_state);
 710
 711         if (!create_links(dc, init_params->num_virtual_links))
 712                 goto fail;
 713
 714         return true;
 715
 716 fail:
 717
 718         destruct(dc);
 719         return false;
 720 }
 721
 722 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 723 static bool disable_all_writeback_pipes_for_stream(
 724                 const struct dc *dc,
 725                 struct dc_stream_state *stream,
 726                 struct dc_state *context)
 727 {
 728         int i;
 729
 730         for (i = 0; i < stream->num_wb_info; i++)
 731                 stream->writeback_info[i].wb_enabled = false;
 732
 733         return true;
 734 }
 735 #endif
 736
 737 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 738 {
 739         int i, j;
 740         struct dc_state *dangling_context = dc_create_state(dc);
 741         struct dc_state *current_ctx;
 742
 743         if (dangling_context == NULL)
 744                 return;
 745
 746         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 747
 748         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 749                 struct dc_stream_state *old_stream =
 750                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 751                 bool should_disable = true;
 752
 753                 for (j = 0; j < context->stream_count; j++) {
 754                         if (old_stream == context->streams[j]) {
 755                                 should_disable = false;
 756                                 break;
 757                         }
 758                 }
 759                 if (should_disable && old_stream) {
 760                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 761 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 762                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 763 #endif
 764                         dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 765                 }
 766         }
 767
 768         current_ctx = dc->current_state;
 769         dc->current_state = dangling_context;
 770         dc_release_state(current_ctx);
 771 }
 772
 773 /*******************************************************************************
 774  * Public functions
 775  ******************************************************************************/
 776
 777 struct dc *dc_create(const struct dc_init_data *init_params)
 778 {
 779         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 780         unsigned int full_pipe_count;
 781
 782         if (NULL == dc)
 783                 goto alloc_fail;
 784
 785         if (false == construct(dc, init_params))
 786                 goto construct_fail;
 787
 788         /*TODO: separate HW and SW initialization*/
 789         dc->hwss.init_hw(dc);
 790
 791         full_pipe_count = dc->res_pool->pipe_count;
 792         if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 793                 full_pipe_count--;
 794         dc->caps.max_streams = min(
 795                         full_pipe_count,
 796                         dc->res_pool->stream_enc_count);
 797
 798         dc->caps.max_links = dc->link_count;
 799         dc->caps.max_audios = dc->res_pool->audio_count;
 800         dc->caps.linear_pitch_alignment = 64;
 801
 802         /* Populate versioning information */
 803         dc->versions.dc_ver = DC_VER;
 804
 805         if (dc->res_pool->dmcu != NULL)
 806                 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 807
 808         dc->build_id = DC_BUILD_ID;
 809
 810         DC_LOG_DC("Display Core initialized\n");
 811
 812
 813
 814         return dc;
 815
 816 construct_fail:
 817         kfree(dc);
 818
 819 alloc_fail:
 820         return NULL;
 821 }
 822
 823 void dc_init_callbacks(struct dc *dc,
 824                 const struct dc_callback_init *init_params)
 825 {
 826 }
 827
 828 void dc_destroy(struct dc **dc)
 829 {
 830         destruct(*dc);
 831         kfree(*dc);
 832         *dc = NULL;
 833 }
 834
 835 static void enable_timing_multisync(
 836                 struct dc *dc,
 837                 struct dc_state *ctx)
 838 {
 839         int i = 0, multisync_count = 0;
 840         int pipe_count = dc->res_pool->pipe_count;
 841         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 842
 843         for (i = 0; i < pipe_count; i++) {
 844                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 845                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 846                         continue;
 847                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 848                         continue;
 849                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 850                 multisync_count++;
 851         }
 852
 853         if (multisync_count > 0) {
 854                 dc->hwss.enable_per_frame_crtc_position_reset(
 855                         dc, multisync_count, multisync_pipes);
 856         }
 857 }
 858
 859 static void program_timing_sync(
 860                 struct dc *dc,
 861                 struct dc_state *ctx)
 862 {
 863         int i, j, k;
 864         int group_index = 0;
 865         int num_group = 0;
 866         int pipe_count = dc->res_pool->pipe_count;
 867         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 868
 869         for (i = 0; i < pipe_count; i++) {
 870                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 871                         continue;
 872
 873                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 874         }
 875
 876         for (i = 0; i < pipe_count; i++) {
 877                 int group_size = 1;
 878                 struct pipe_ctx *pipe_set[MAX_PIPES];
 879
 880                 if (!unsynced_pipes[i])
 881                         continue;
 882
 883                 pipe_set[0] = unsynced_pipes[i];
 884                 unsynced_pipes[i] = NULL;
 885
 886                 /* Add tg to the set, search rest of the tg's for ones with
 887                  * same timing, add all tgs with same timing to the group
 888                  */
 889                 for (j = i + 1; j < pipe_count; j++) {
 890                         if (!unsynced_pipes[j])
 891                                 continue;
 892
 893                         if (resource_are_streams_timing_synchronizable(
 894                                         unsynced_pipes[j]->stream,
 895                                         pipe_set[0]->stream)) {
 896                                 pipe_set[group_size] = unsynced_pipes[j];
 897                                 unsynced_pipes[j] = NULL;
 898                                 group_size++;
 899                         }
 900                 }
 901
 902                 /* set first pipe with plane as master */
 903                 for (j = 0; j < group_size; j++) {
 904                         struct pipe_ctx *temp;
 905
 906                         if (pipe_set[j]->plane_state) {
 907                                 if (j == 0)
 908                                         break;
 909
 910                                 temp = pipe_set[0];
 911                                 pipe_set[0] = pipe_set[j];
 912                                 pipe_set[j] = temp;
 913                                 break;
 914                         }
 915                 }
 916
 917
 918                 for (k = 0; k < group_size; k++) {
 919                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
 920
 921                         status->timing_sync_info.group_id = num_group;
 922                         status->timing_sync_info.group_size = group_size;
 923                         if (k == 0)
 924                                 status->timing_sync_info.master = true;
 925                         else
 926                                 status->timing_sync_info.master = false;
 927
 928                 }
 929                 /* remove any other pipes with plane as they have already been synced */
 930                 for (j = j + 1; j < group_size; j++) {
 931                         if (pipe_set[j]->plane_state) {
 932                                 group_size--;
 933                                 pipe_set[j] = pipe_set[group_size];
 934                                 j--;
 935                         }
 936                 }
 937
 938                 if (group_size > 1) {
 939                         dc->hwss.enable_timing_synchronization(
 940                                 dc, group_index, group_size, pipe_set);
 941                         group_index++;
 942                 }
 943                 num_group++;
 944         }
 945 }
 946
 947 static bool context_changed(
 948                 struct dc *dc,
 949                 struct dc_state *context)
 950 {
 951         uint8_t i;
 952
 953         if (context->stream_count != dc->current_state->stream_count)
 954                 return true;
 955
 956         for (i = 0; i < dc->current_state->stream_count; i++) {
 957                 if (dc->current_state->streams[i] != context->streams[i])
 958                         return true;
 959         }
 960
 961         return false;
 962 }
 963
 964 bool dc_validate_seamless_boot_timing(const struct dc *dc,
 965                                 const struct dc_sink *sink,
 966                                 struct dc_crtc_timing *crtc_timing)
 967 {
 968         struct timing_generator *tg;
 969         struct dc_link *link = sink->link;
 970         unsigned int enc_inst, tg_inst;
 971
 972         /* Check for enabled DIG to identify enabled display */
 973         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
 974                 return false;
 975
 976         /* Check for which front end is used by this encoder.
 977          * Note the inst is 1 indexed, where 0 is undefined.
 978          * Note that DIG_FE can source from different OTG but our
 979          * current implementation always map 1-to-1, so this code makes
 980          * the same assumption and doesn't check OTG source.
 981          */
 982         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 983
 984         /* Instance should be within the range of the pool */
 985         if (enc_inst >= dc->res_pool->pipe_count)
 986                 return false;
 987
 988         if (enc_inst >= dc->res_pool->stream_enc_count)
 989                 return false;
 990
 991         tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
 992                 dc->res_pool->stream_enc[enc_inst]);
 993
 994         if (tg_inst >= dc->res_pool->timing_generator_count)
 995                 return false;
 996
 997         tg = dc->res_pool->timing_generators[tg_inst];
 998
 999         if (!tg->funcs->is_matching_timing)
1000                 return false;
1001
1002         if (!tg->funcs->is_matching_timing(tg, crtc_timing))
1003                 return false;
1004
1005         if (dc_is_dp_signal(link->connector_signal)) {
1006                 unsigned int pix_clk_100hz;
1007
1008                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1009                         dc->res_pool->dp_clock_source,
1010                         tg_inst, &pix_clk_100hz);
1011
1012                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1013                         return false;
1014
1015         }
1016
1017         return true;
1018 }
1019
1020 bool dc_enable_stereo(
1021         struct dc *dc,
1022         struct dc_state *context,
1023         struct dc_stream_state *streams[],
1024         uint8_t stream_count)
1025 {
1026         bool ret = true;
1027         int i, j;
1028         struct pipe_ctx *pipe;
1029
1030         for (i = 0; i < MAX_PIPES; i++) {
1031                 if (context != NULL)
1032                         pipe = &context->res_ctx.pipe_ctx[i];
1033                 else
1034                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1035                 for (j = 0 ; pipe && j < stream_count; j++)  {
1036                         if (streams[j] && streams[j] == pipe->stream &&
1037                                 dc->hwss.setup_stereo)
1038                                 dc->hwss.setup_stereo(pipe, dc);
1039                 }
1040         }
1041
1042         return ret;
1043 }
1044
1045 /*
1046  * Applies given context to HW and copy it into current context.
1047  * It's up to the user to release the src context afterwards.
1048  */
1049 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1050 {
1051         struct dc_bios *dcb = dc->ctx->dc_bios;
1052         enum dc_status result = DC_ERROR_UNEXPECTED;
1053         struct pipe_ctx *pipe;
1054         int i, k, l;
1055         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1056
1057         disable_dangling_plane(dc, context);
1058
1059         for (i = 0; i < context->stream_count; i++)
1060                 dc_streams[i] =  context->streams[i];
1061
1062         if (!dcb->funcs->is_accelerated_mode(dcb))
1063                 dc->hwss.enable_accelerated_mode(dc, context);
1064
1065         for (i = 0; i < context->stream_count; i++) {
1066                 if (context->streams[i]->apply_seamless_boot_optimization)
1067                         dc->optimize_seamless_boot = true;
1068         }
1069
1070         if (!dc->optimize_seamless_boot)
1071                 dc->hwss.prepare_bandwidth(dc, context);
1072
1073         /* re-program planes for existing stream, in case we need to
1074          * free up plane resource for later use
1075          */
1076         for (i = 0; i < context->stream_count; i++) {
1077                 if (context->streams[i]->mode_changed)
1078                         continue;
1079
1080                 dc->hwss.apply_ctx_for_surface(
1081                         dc, context->streams[i],
1082                         context->stream_status[i].plane_count,
1083                         context); /* use new pipe config in new context */
1084         }
1085
1086         /* Program hardware */
1087         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1088                 pipe = &context->res_ctx.pipe_ctx[i];
1089                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1090         }
1091
1092         result = dc->hwss.apply_ctx_to_hw(dc, context);
1093
1094         if (result != DC_OK)
1095                 return result;
1096
1097         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1098                 enable_timing_multisync(dc, context);
1099                 program_timing_sync(dc, context);
1100         }
1101
1102         /* Program all planes within new context*/
1103         for (i = 0; i < context->stream_count; i++) {
1104                 const struct dc_link *link = context->streams[i]->link;
1105
1106                 if (!context->streams[i]->mode_changed)
1107                         continue;
1108
1109                 dc->hwss.apply_ctx_for_surface(
1110                                 dc, context->streams[i],
1111                                 context->stream_status[i].plane_count,
1112                                 context);
1113
1114                 /*
1115                  * enable stereo
1116                  * TODO rework dc_enable_stereo call to work with validation sets?
1117                  */
1118                 for (k = 0; k < MAX_PIPES; k++) {
1119                         pipe = &context->res_ctx.pipe_ctx[k];
1120
1121                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1122                                 if (context->streams[l] &&
1123                                         context->streams[l] == pipe->stream &&
1124                                         dc->hwss.setup_stereo)
1125                                         dc->hwss.setup_stereo(pipe, dc);
1126                         }
1127                 }
1128
1129                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1130                                 context->streams[i]->timing.h_addressable,
1131                                 context->streams[i]->timing.v_addressable,
1132                                 context->streams[i]->timing.h_total,
1133                                 context->streams[i]->timing.v_total,
1134                                 context->streams[i]->timing.pix_clk_100hz / 10);
1135         }
1136
1137         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1138
1139         if (!dc->optimize_seamless_boot)
1140                 /* pplib is notified if disp_num changed */
1141                 dc->hwss.optimize_bandwidth(dc, context);
1142
1143         for (i = 0; i < context->stream_count; i++)
1144                 context->streams[i]->mode_changed = false;
1145
1146         memset(&context->commit_hints, 0, sizeof(context->commit_hints));
1147
1148         dc_release_state(dc->current_state);
1149
1150         dc->current_state = context;
1151
1152         dc_retain_state(dc->current_state);
1153
1154         return result;
1155 }
1156
1157 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1158 {
1159         enum dc_status result = DC_ERROR_UNEXPECTED;
1160         int i;
1161
1162         if (false == context_changed(dc, context))
1163                 return DC_OK;
1164
1165         DC_LOG_DC("%s: %d streams\n",
1166                                 __func__, context->stream_count);
1167
1168         for (i = 0; i < context->stream_count; i++) {
1169                 struct dc_stream_state *stream = context->streams[i];
1170
1171                 dc_stream_log(dc, stream);
1172         }
1173
1174         result = dc_commit_state_no_check(dc, context);
1175
1176         return (result == DC_OK);
1177 }
1178
1179 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1180 {
1181         int i;
1182         struct dc_state *context = dc->current_state;
1183
1184         if (!dc->optimized_required || dc->optimize_seamless_boot)
1185                 return true;
1186
1187         post_surface_trace(dc);
1188
1189         for (i = 0; i < dc->res_pool->pipe_count; i++)
1190                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1191                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1192                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1193                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1194                 }
1195
1196         dc->optimized_required = false;
1197
1198         dc->hwss.optimize_bandwidth(dc, context);
1199         return true;
1200 }
1201
1202 struct dc_state *dc_create_state(struct dc *dc)
1203 {
1204         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1205                                             GFP_KERNEL);
1206
1207         if (!context)
1208                 return NULL;
1209         /* Each context must have their own instance of VBA and in order to
1210          * initialize and obtain IP and SOC the base DML instance from DC is
1211          * initially copied into every context
1212          */
1213 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
1214         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1215 #endif
1216
1217         kref_init(&context->refcount);
1218
1219         return context;
1220 }
1221
1222 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1223 {
1224         int i, j;
1225         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1226
1227         if (!new_ctx)
1228                 return NULL;
1229         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1230
1231         for (i = 0; i < MAX_PIPES; i++) {
1232                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1233
1234                         if (cur_pipe->top_pipe)
1235                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1236
1237                         if (cur_pipe->bottom_pipe)
1238                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1239
1240                         if (cur_pipe->prev_odm_pipe)
1241                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1242
1243                         if (cur_pipe->next_odm_pipe)
1244                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1245
1246         }
1247
1248         for (i = 0; i < new_ctx->stream_count; i++) {
1249                         dc_stream_retain(new_ctx->streams[i]);
1250                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1251                                 dc_plane_state_retain(
1252                                         new_ctx->stream_status[i].plane_states[j]);
1253         }
1254
1255         kref_init(&new_ctx->refcount);
1256
1257         return new_ctx;
1258 }
1259
1260 void dc_retain_state(struct dc_state *context)
1261 {
1262         kref_get(&context->refcount);
1263 }
1264
1265 static void dc_state_free(struct kref *kref)
1266 {
1267         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1268         dc_resource_state_destruct(context);
1269         kvfree(context);
1270 }
1271
1272 void dc_release_state(struct dc_state *context)
1273 {
1274         kref_put(&context->refcount, dc_state_free);
1275 }
1276
1277 bool dc_set_generic_gpio_for_stereo(bool enable,
1278                 struct gpio_service *gpio_service)
1279 {
1280         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1281         struct gpio_pin_info pin_info;
1282         struct gpio *generic;
1283         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1284                            GFP_KERNEL);
1285
1286         if (!config)
1287                 return false;
1288         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1289
1290         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1291                 kfree(config);
1292                 return false;
1293         } else {
1294                 generic = dal_gpio_service_create_generic_mux(
1295                         gpio_service,
1296                         pin_info.offset,
1297                         pin_info.mask);
1298         }
1299
1300         if (!generic) {
1301                 kfree(config);
1302                 return false;
1303         }
1304
1305         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1306
1307         config->enable_output_from_mux = enable;
1308         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1309
1310         if (gpio_result == GPIO_RESULT_OK)
1311                 gpio_result = dal_mux_setup_config(generic, config);
1312
1313         if (gpio_result == GPIO_RESULT_OK) {
1314                 dal_gpio_close(generic);
1315                 dal_gpio_destroy_generic_mux(&generic);
1316                 kfree(config);
1317                 return true;
1318         } else {
1319                 dal_gpio_close(generic);
1320                 dal_gpio_destroy_generic_mux(&generic);
1321                 kfree(config);
1322                 return false;
1323         }
1324 }
1325
1326 static bool is_surface_in_context(
1327                 const struct dc_state *context,
1328                 const struct dc_plane_state *plane_state)
1329 {
1330         int j;
1331
1332         for (j = 0; j < MAX_PIPES; j++) {
1333                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1334
1335                 if (plane_state == pipe_ctx->plane_state) {
1336                         return true;
1337                 }
1338         }
1339
1340         return false;
1341 }
1342
1343 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1344 {
1345         union surface_update_flags *update_flags = &u->surface->update_flags;
1346         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1347
1348         if (!u->plane_info)
1349                 return UPDATE_TYPE_FAST;
1350
1351         if (u->plane_info->color_space != u->surface->color_space) {
1352                 update_flags->bits.color_space_change = 1;
1353                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1354         }
1355
1356         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1357                 update_flags->bits.horizontal_mirror_change = 1;
1358                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1359         }
1360
1361         if (u->plane_info->rotation != u->surface->rotation) {
1362                 update_flags->bits.rotation_change = 1;
1363                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1364         }
1365
1366         if (u->plane_info->format != u->surface->format) {
1367                 update_flags->bits.pixel_format_change = 1;
1368                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1369         }
1370
1371         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1372                 update_flags->bits.stereo_format_change = 1;
1373                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1374         }
1375
1376         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1377                 update_flags->bits.per_pixel_alpha_change = 1;
1378                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1379         }
1380
1381         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1382                 update_flags->bits.global_alpha_change = 1;
1383                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1384         }
1385
1386         if (u->plane_info->sdr_white_level != u->surface->sdr_white_level) {
1387                 update_flags->bits.sdr_white_level = 1;
1388                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1389         }
1390
1391         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1392                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1393                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1394                 update_flags->bits.dcc_change = 1;
1395                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1396         }
1397
1398         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1399                         resource_pixel_format_to_bpp(u->surface->format)) {
1400                 /* different bytes per element will require full bandwidth
1401                  * and DML calculation
1402                  */
1403                 update_flags->bits.bpp_change = 1;
1404                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1405         }
1406
1407         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1408                         || u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1409                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1410                 update_flags->bits.plane_size_change = 1;
1411                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1412         }
1413
1414
1415         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1416                         sizeof(union dc_tiling_info)) != 0) {
1417                 update_flags->bits.swizzle_change = 1;
1418                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1419
1420                 /* todo: below are HW dependent, we should add a hook to
1421                  * DCE/N resource and validated there.
1422                  */
1423                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1424                         /* swizzled mode requires RQ to be setup properly,
1425                          * thus need to run DML to calculate RQ settings
1426                          */
1427                         update_flags->bits.bandwidth_change = 1;
1428                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1429                 }
1430         }
1431
1432         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1433         return update_type;
1434 }
1435
1436 static enum surface_update_type get_scaling_info_update_type(
1437                 const struct dc_surface_update *u)
1438 {
1439         union surface_update_flags *update_flags = &u->surface->update_flags;
1440
1441         if (!u->scaling_info)
1442                 return UPDATE_TYPE_FAST;
1443
1444         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1445                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1446                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1447                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
1448                 update_flags->bits.scaling_change = 1;
1449
1450                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1451                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1452                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1453                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1454                         /* Making dst rect smaller requires a bandwidth change */
1455                         update_flags->bits.bandwidth_change = 1;
1456         }
1457
1458         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1459                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1460
1461                 update_flags->bits.scaling_change = 1;
1462                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1463                                 && u->scaling_info->src_rect.height > u->surface->src_rect.height)
1464                         /* Making src rect bigger requires a bandwidth change */
1465                         update_flags->bits.clock_change = 1;
1466         }
1467
1468         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1469                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1470                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1471                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1472                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1473                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1474                 update_flags->bits.position_change = 1;
1475
1476         if (update_flags->bits.clock_change
1477                         || update_flags->bits.bandwidth_change)
1478                 return UPDATE_TYPE_FULL;
1479
1480         if (update_flags->bits.scaling_change
1481                         || update_flags->bits.position_change)
1482                 return UPDATE_TYPE_MED;
1483
1484         return UPDATE_TYPE_FAST;
1485 }
1486
1487 static enum surface_update_type det_surface_update(const struct dc *dc,
1488                 const struct dc_surface_update *u)
1489 {
1490         const struct dc_state *context = dc->current_state;
1491         enum surface_update_type type;
1492         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1493         union surface_update_flags *update_flags = &u->surface->update_flags;
1494
1495         update_flags->raw = 0; // Reset all flags
1496
1497         if (u->flip_addr)
1498                 update_flags->bits.addr_update = 1;
1499
1500         if (!is_surface_in_context(context, u->surface)) {
1501                 update_flags->bits.new_plane = 1;
1502                 return UPDATE_TYPE_FULL;
1503         }
1504
1505         if (u->surface->force_full_update) {
1506                 update_flags->bits.full_update = 1;
1507                 return UPDATE_TYPE_FULL;
1508         }
1509
1510         type = get_plane_info_update_type(u);
1511         elevate_update_type(&overall_type, type);
1512
1513         type = get_scaling_info_update_type(u);
1514         elevate_update_type(&overall_type, type);
1515
1516         if (u->flip_addr)
1517                 update_flags->bits.addr_update = 1;
1518
1519         if (u->in_transfer_func)
1520                 update_flags->bits.in_transfer_func_change = 1;
1521
1522         if (u->input_csc_color_matrix)
1523                 update_flags->bits.input_csc_change = 1;
1524
1525         if (u->coeff_reduction_factor)
1526                 update_flags->bits.coeff_reduction_change = 1;
1527
1528         if (u->gamma) {
1529                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1530
1531                 if (u->plane_info)
1532                         format = u->plane_info->format;
1533                 else if (u->surface)
1534                         format = u->surface->format;
1535
1536                 if (dce_use_lut(format))
1537                         update_flags->bits.gamma_change = 1;
1538         }
1539
1540         if (update_flags->bits.in_transfer_func_change) {
1541                 type = UPDATE_TYPE_MED;
1542                 elevate_update_type(&overall_type, type);
1543         }
1544
1545         if (update_flags->bits.input_csc_change
1546                         || update_flags->bits.coeff_reduction_change
1547                         || update_flags->bits.gamma_change) {
1548                 type = UPDATE_TYPE_FULL;
1549                 elevate_update_type(&overall_type, type);
1550         }
1551
1552         return overall_type;
1553 }
1554
1555 static enum surface_update_type check_update_surfaces_for_stream(
1556                 struct dc *dc,
1557                 struct dc_surface_update *updates,
1558                 int surface_count,
1559                 struct dc_stream_update *stream_update,
1560                 const struct dc_stream_status *stream_status)
1561 {
1562         int i;
1563         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1564
1565         if (stream_status == NULL || stream_status->plane_count != surface_count)
1566                 return UPDATE_TYPE_FULL;
1567
1568         /* some stream updates require passive update */
1569         if (stream_update) {
1570                 if ((stream_update->src.height != 0) &&
1571                                 (stream_update->src.width != 0))
1572                         return UPDATE_TYPE_FULL;
1573
1574                 if ((stream_update->dst.height != 0) &&
1575                                 (stream_update->dst.width != 0))
1576                         return UPDATE_TYPE_FULL;
1577
1578                 if (stream_update->out_transfer_func)
1579                         return UPDATE_TYPE_FULL;
1580
1581                 if (stream_update->abm_level)
1582                         return UPDATE_TYPE_FULL;
1583
1584                 if (stream_update->dpms_off)
1585                         return UPDATE_TYPE_FULL;
1586
1587 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1588                 if (stream_update->wb_update)
1589                         return UPDATE_TYPE_FULL;
1590 #endif
1591         }
1592
1593         for (i = 0 ; i < surface_count; i++) {
1594                 enum surface_update_type type =
1595                                 det_surface_update(dc, &updates[i]);
1596
1597                 if (type == UPDATE_TYPE_FULL)
1598                         return type;
1599
1600                 elevate_update_type(&overall_type, type);
1601         }
1602
1603         return overall_type;
1604 }
1605
1606 /**
1607  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1608  *
1609  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1610  */
1611 enum surface_update_type dc_check_update_surfaces_for_stream(
1612                 struct dc *dc,
1613                 struct dc_surface_update *updates,
1614                 int surface_count,
1615                 struct dc_stream_update *stream_update,
1616                 const struct dc_stream_status *stream_status)
1617 {
1618         int i;
1619         enum surface_update_type type;
1620
1621         for (i = 0; i < surface_count; i++)
1622                 updates[i].surface->update_flags.raw = 0;
1623
1624         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1625         if (type == UPDATE_TYPE_FULL)
1626                 for (i = 0; i < surface_count; i++)
1627                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1628
1629         if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
1630                 dc->optimized_required = true;
1631
1632         return type;
1633 }
1634
1635 static struct dc_stream_status *stream_get_status(
1636         struct dc_state *ctx,
1637         struct dc_stream_state *stream)
1638 {
1639         uint8_t i;
1640
1641         for (i = 0; i < ctx->stream_count; i++) {
1642                 if (stream == ctx->streams[i]) {
1643                         return &ctx->stream_status[i];
1644                 }
1645         }
1646
1647         return NULL;
1648 }
1649
1650 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1651
1652 static void copy_surface_update_to_plane(
1653                 struct dc_plane_state *surface,
1654                 struct dc_surface_update *srf_update)
1655 {
1656         if (srf_update->flip_addr) {
1657                 surface->address = srf_update->flip_addr->address;
1658                 surface->flip_immediate =
1659                         srf_update->flip_addr->flip_immediate;
1660                 surface->time.time_elapsed_in_us[surface->time.index] =
1661                         srf_update->flip_addr->flip_timestamp_in_us -
1662                                 surface->time.prev_update_time_in_us;
1663                 surface->time.prev_update_time_in_us =
1664                         srf_update->flip_addr->flip_timestamp_in_us;
1665                 surface->time.index++;
1666                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1667                         surface->time.index = 0;
1668         }
1669
1670         if (srf_update->scaling_info) {
1671                 surface->scaling_quality =
1672                                 srf_update->scaling_info->scaling_quality;
1673                 surface->dst_rect =
1674                                 srf_update->scaling_info->dst_rect;
1675                 surface->src_rect =
1676                                 srf_update->scaling_info->src_rect;
1677                 surface->clip_rect =
1678                                 srf_update->scaling_info->clip_rect;
1679         }
1680
1681         if (srf_update->plane_info) {
1682                 surface->color_space =
1683                                 srf_update->plane_info->color_space;
1684                 surface->format =
1685                                 srf_update->plane_info->format;
1686                 surface->plane_size =
1687                                 srf_update->plane_info->plane_size;
1688                 surface->rotation =
1689                                 srf_update->plane_info->rotation;
1690                 surface->horizontal_mirror =
1691                                 srf_update->plane_info->horizontal_mirror;
1692                 surface->stereo_format =
1693                                 srf_update->plane_info->stereo_format;
1694                 surface->tiling_info =
1695                                 srf_update->plane_info->tiling_info;
1696                 surface->visible =
1697                                 srf_update->plane_info->visible;
1698                 surface->per_pixel_alpha =
1699                                 srf_update->plane_info->per_pixel_alpha;
1700                 surface->global_alpha =
1701                                 srf_update->plane_info->global_alpha;
1702                 surface->global_alpha_value =
1703                                 srf_update->plane_info->global_alpha_value;
1704                 surface->dcc =
1705                                 srf_update->plane_info->dcc;
1706                 surface->sdr_white_level =
1707                                 srf_update->plane_info->sdr_white_level;
1708                 surface->layer_index =
1709                                 srf_update->plane_info->layer_index;
1710         }
1711
1712         if (srf_update->gamma &&
1713                         (surface->gamma_correction !=
1714                                         srf_update->gamma)) {
1715                 memcpy(&surface->gamma_correction->entries,
1716                         &srf_update->gamma->entries,
1717                         sizeof(struct dc_gamma_entries));
1718                 surface->gamma_correction->is_identity =
1719                         srf_update->gamma->is_identity;
1720                 surface->gamma_correction->num_entries =
1721                         srf_update->gamma->num_entries;
1722                 surface->gamma_correction->type =
1723                         srf_update->gamma->type;
1724         }
1725
1726         if (srf_update->in_transfer_func &&
1727                         (surface->in_transfer_func !=
1728                                 srf_update->in_transfer_func)) {
1729                 surface->in_transfer_func->sdr_ref_white_level =
1730                         srf_update->in_transfer_func->sdr_ref_white_level;
1731                 surface->in_transfer_func->tf =
1732                         srf_update->in_transfer_func->tf;
1733                 surface->in_transfer_func->type =
1734                         srf_update->in_transfer_func->type;
1735                 memcpy(&surface->in_transfer_func->tf_pts,
1736                         &srf_update->in_transfer_func->tf_pts,
1737                         sizeof(struct dc_transfer_func_distributed_points));
1738         }
1739
1740 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1741         if (srf_update->func_shaper &&
1742                         (surface->in_shaper_func !=
1743                         srf_update->func_shaper))
1744                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
1745                 sizeof(*surface->in_shaper_func));
1746
1747         if (srf_update->lut3d_func &&
1748                         (surface->lut3d_func !=
1749                         srf_update->lut3d_func))
1750                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
1751                 sizeof(*surface->lut3d_func));
1752
1753         if (srf_update->blend_tf &&
1754                         (surface->blend_tf !=
1755                         srf_update->blend_tf))
1756                 memcpy(surface->blend_tf, srf_update->blend_tf,
1757                 sizeof(*surface->blend_tf));
1758
1759 #endif
1760         if (srf_update->input_csc_color_matrix)
1761                 surface->input_csc_color_matrix =
1762                         *srf_update->input_csc_color_matrix;
1763
1764         if (srf_update->coeff_reduction_factor)
1765                 surface->coeff_reduction_factor =
1766                         *srf_update->coeff_reduction_factor;
1767 }
1768
1769 static void copy_stream_update_to_stream(struct dc *dc,
1770                                          struct dc_state *context,
1771                                          struct dc_stream_state *stream,
1772                                          const struct dc_stream_update *update)
1773 {
1774         if (update == NULL || stream == NULL)
1775                 return;
1776
1777         if (update->src.height && update->src.width)
1778                 stream->src = update->src;
1779
1780         if (update->dst.height && update->dst.width)
1781                 stream->dst = update->dst;
1782
1783         if (update->out_transfer_func &&
1784             stream->out_transfer_func != update->out_transfer_func) {
1785                 stream->out_transfer_func->sdr_ref_white_level =
1786                         update->out_transfer_func->sdr_ref_white_level;
1787                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
1788                 stream->out_transfer_func->type =
1789                         update->out_transfer_func->type;
1790                 memcpy(&stream->out_transfer_func->tf_pts,
1791                        &update->out_transfer_func->tf_pts,
1792                        sizeof(struct dc_transfer_func_distributed_points));
1793         }
1794
1795         if (update->hdr_static_metadata)
1796                 stream->hdr_static_metadata = *update->hdr_static_metadata;
1797
1798         if (update->abm_level)
1799                 stream->abm_level = *update->abm_level;
1800
1801         if (update->periodic_interrupt0)
1802                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
1803
1804         if (update->periodic_interrupt1)
1805                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
1806
1807         if (update->gamut_remap)
1808                 stream->gamut_remap_matrix = *update->gamut_remap;
1809
1810         /* Note: this being updated after mode set is currently not a use case
1811          * however if it arises OCSC would need to be reprogrammed at the
1812          * minimum
1813          */
1814         if (update->output_color_space)
1815                 stream->output_color_space = *update->output_color_space;
1816
1817         if (update->output_csc_transform)
1818                 stream->csc_color_matrix = *update->output_csc_transform;
1819
1820         if (update->vrr_infopacket)
1821                 stream->vrr_infopacket = *update->vrr_infopacket;
1822
1823         if (update->dpms_off)
1824                 stream->dpms_off = *update->dpms_off;
1825
1826         if (update->vsc_infopacket)
1827                 stream->vsc_infopacket = *update->vsc_infopacket;
1828
1829         if (update->vsp_infopacket)
1830                 stream->vsp_infopacket = *update->vsp_infopacket;
1831
1832         if (update->dither_option)
1833                 stream->dither_option = *update->dither_option;
1834 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1835         /* update current stream with writeback info */
1836         if (update->wb_update) {
1837                 int i;
1838
1839                 stream->num_wb_info = update->wb_update->num_wb_info;
1840                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
1841                 for (i = 0; i < stream->num_wb_info; i++)
1842                         stream->writeback_info[i] =
1843                                 update->wb_update->writeback_info[i];
1844         }
1845 #endif
1846 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
1847         if (update->dsc_config) {
1848                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
1849                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
1850                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
1851                                        update->dsc_config->num_slices_v != 0);
1852
1853                 stream->timing.dsc_cfg = *update->dsc_config;
1854                 stream->timing.flags.DSC = enable_dsc;
1855                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context,
1856                                                              true)) {
1857                         stream->timing.dsc_cfg = old_dsc_cfg;
1858                         stream->timing.flags.DSC = old_dsc_enabled;
1859                 }
1860         }
1861 #endif
1862 }
1863
1864 static void commit_planes_do_stream_update(struct dc *dc,
1865                 struct dc_stream_state *stream,
1866                 struct dc_stream_update *stream_update,
1867                 enum surface_update_type update_type,
1868                 struct dc_state *context)
1869 {
1870         int j;
1871
1872         // Stream updates
1873         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1874                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1875
1876                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
1877
1878                         if (stream_update->periodic_interrupt0 &&
1879                                         dc->hwss.setup_periodic_interrupt)
1880                                 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
1881
1882                         if (stream_update->periodic_interrupt1 &&
1883                                         dc->hwss.setup_periodic_interrupt)
1884                                 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
1885
1886                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
1887                                         stream_update->vrr_infopacket ||
1888                                         stream_update->vsc_infopacket ||
1889                                         stream_update->vsp_infopacket) {
1890                                 resource_build_info_frame(pipe_ctx);
1891                                 dc->hwss.update_info_frame(pipe_ctx);
1892                         }
1893
1894                         if (stream_update->gamut_remap)
1895                                 dc_stream_set_gamut_remap(dc, stream);
1896
1897                         if (stream_update->output_csc_transform)
1898                                 dc_stream_program_csc_matrix(dc, stream);
1899
1900                         if (stream_update->dither_option) {
1901 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1902                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1903 #endif
1904                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1905                                                                         &pipe_ctx->stream->bit_depth_params);
1906                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
1907                                                 &stream->bit_depth_params,
1908                                                 &stream->clamping);
1909 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
1910                                 while (odm_pipe) {
1911                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
1912                                                         &stream->bit_depth_params,
1913                                                         &stream->clamping);
1914                                         odm_pipe = odm_pipe->next_odm_pipe;
1915                                 }
1916 #endif
1917                         }
1918
1919 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
1920                         if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
1921                                 dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
1922                                 dp_update_dsc_config(pipe_ctx);
1923                                 dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
1924                         }
1925 #endif
1926                         /* Full fe update*/
1927                         if (update_type == UPDATE_TYPE_FAST)
1928                                 continue;
1929
1930                         if (stream_update->dpms_off) {
1931                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1932
1933                                 if (*stream_update->dpms_off) {
1934                                         core_link_disable_stream(pipe_ctx);
1935                                         /* for dpms, keep acquired resources*/
1936                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
1937                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1938
1939                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
1940                                 } else {
1941                                         if (!dc->optimize_seamless_boot)
1942                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
1943
1944                                         core_link_enable_stream(dc->current_state, pipe_ctx);
1945                                 }
1946
1947                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
1948                         }
1949
1950                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
1951                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
1952                                         // if otg funcs defined check if blanked before programming
1953                                         if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
1954                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
1955                                                         pipe_ctx->stream_res.abm, stream->abm_level);
1956                                 } else
1957                                         pipe_ctx->stream_res.abm->funcs->set_abm_level(
1958                                                 pipe_ctx->stream_res.abm, stream->abm_level);
1959                         }
1960                 }
1961         }
1962 }
1963
1964 static void commit_planes_for_stream(struct dc *dc,
1965                 struct dc_surface_update *srf_updates,
1966                 int surface_count,
1967                 struct dc_stream_state *stream,
1968                 struct dc_stream_update *stream_update,
1969                 enum surface_update_type update_type,
1970                 struct dc_state *context)
1971 {
1972         int i, j;
1973         struct pipe_ctx *top_pipe_to_program = NULL;
1974
1975         if (dc->optimize_seamless_boot && surface_count > 0) {
1976                 /* Optimize seamless boot flag keeps clocks and watermarks high until
1977                  * first flip. After first flip, optimization is required to lower
1978                  * bandwidth. Important to note that it is expected UEFI will
1979                  * only light up a single display on POST, therefore we only expect
1980                  * one stream with seamless boot flag set.
1981                  */
1982                 if (stream->apply_seamless_boot_optimization) {
1983                         stream->apply_seamless_boot_optimization = false;
1984                         dc->optimize_seamless_boot = false;
1985                         dc->optimized_required = true;
1986                 }
1987         }
1988
1989         if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) {
1990                 dc->hwss.prepare_bandwidth(dc, context);
1991                 context_clock_trace(dc, context);
1992         }
1993
1994         // Stream updates
1995         if (stream_update)
1996                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
1997
1998         if (surface_count == 0) {
1999                 /*
2000                  * In case of turning off screen, no need to program front end a second time.
2001                  * just return after program blank.
2002                  */
2003                 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2004                 return;
2005         }
2006
2007 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2008         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2009                 for (i = 0; i < surface_count; i++) {
2010                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2011                         /*set logical flag for lock/unlock use*/
2012                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2013                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2014                                 if (!pipe_ctx->plane_state)
2015                                         continue;
2016                                 if (pipe_ctx->plane_state != plane_state)
2017                                         continue;
2018                                 plane_state->triplebuffer_flips = false;
2019                                 if (update_type == UPDATE_TYPE_FAST &&
2020                                         dc->hwss.program_triplebuffer != NULL &&
2021                                         !plane_state->flip_immediate &&
2022                                         !dc->debug.disable_tri_buf) {
2023                                                 /*triple buffer for VUpdate  only*/
2024                                                 plane_state->triplebuffer_flips = true;
2025                                 }
2026                         }
2027                 }
2028         }
2029 #endif
2030
2031         // Update Type FULL, Surface updates
2032         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2033                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2034
2035                 if (!pipe_ctx->top_pipe &&
2036                         !pipe_ctx->prev_odm_pipe &&
2037                         pipe_ctx->stream &&
2038                         pipe_ctx->stream == stream) {
2039                         struct dc_stream_status *stream_status = NULL;
2040
2041                         top_pipe_to_program = pipe_ctx;
2042
2043                         if (!pipe_ctx->plane_state)
2044                                 continue;
2045
2046                         /* Full fe update*/
2047                         if (update_type == UPDATE_TYPE_FAST)
2048                                 continue;
2049
2050 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2051                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2052
2053                         if (dc->hwss.program_triplebuffer != NULL &&
2054                                 !dc->debug.disable_tri_buf) {
2055                                 /*turn off triple buffer for full update*/
2056                                 dc->hwss.program_triplebuffer(
2057                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2058                         }
2059 #endif
2060                         stream_status =
2061                                 stream_get_status(context, pipe_ctx->stream);
2062
2063                         dc->hwss.apply_ctx_for_surface(
2064                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2065                 }
2066         }
2067
2068         // Update Type FAST, Surface updates
2069         if (update_type == UPDATE_TYPE_FAST) {
2070                 /* Lock the top pipe while updating plane addrs, since freesync requires
2071                  *  plane addr update event triggers to be synchronized.
2072                  *  top_pipe_to_program is expected to never be NULL
2073                  */
2074                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2075
2076 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2077                 if (dc->hwss.set_flip_control_gsl)
2078                         for (i = 0; i < surface_count; i++) {
2079                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2080
2081                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2082                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2083
2084                                         if (pipe_ctx->stream != stream)
2085                                                 continue;
2086
2087                                         if (pipe_ctx->plane_state != plane_state)
2088                                                 continue;
2089
2090                                         // GSL has to be used for flip immediate
2091                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2092                                                         plane_state->flip_immediate);
2093                                 }
2094                         }
2095 #endif
2096                 /* Perform requested Updates */
2097                 for (i = 0; i < surface_count; i++) {
2098                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2099
2100                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2101                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2102
2103                                 if (pipe_ctx->stream != stream)
2104                                         continue;
2105
2106                                 if (pipe_ctx->plane_state != plane_state)
2107                                         continue;
2108 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2109                                 /*program triple buffer after lock based on flip type*/
2110                                 if (dc->hwss.program_triplebuffer != NULL &&
2111                                         !dc->debug.disable_tri_buf) {
2112                                         /*only enable triplebuffer for  fast_update*/
2113                                         dc->hwss.program_triplebuffer(
2114                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2115                                 }
2116 #endif
2117                                 if (srf_updates[i].flip_addr)
2118                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2119                         }
2120                 }
2121
2122                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2123         }
2124
2125         // Fire manual trigger only when bottom plane is flipped
2126         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2127                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2128
2129                 if (pipe_ctx->bottom_pipe ||
2130                                 !pipe_ctx->stream ||
2131                                 pipe_ctx->stream != stream ||
2132                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2133                         continue;
2134
2135                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2136                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2137         }
2138 }
2139
2140 void dc_commit_updates_for_stream(struct dc *dc,
2141                 struct dc_surface_update *srf_updates,
2142                 int surface_count,
2143                 struct dc_stream_state *stream,
2144                 struct dc_stream_update *stream_update,
2145                 struct dc_state *state)
2146 {
2147         const struct dc_stream_status *stream_status;
2148         enum surface_update_type update_type;
2149         struct dc_state *context;
2150         struct dc_context *dc_ctx = dc->ctx;
2151         int i;
2152
2153         stream_status = dc_stream_get_status(stream);
2154         context = dc->current_state;
2155
2156         update_type = dc_check_update_surfaces_for_stream(
2157                                 dc, srf_updates, surface_count, stream_update, stream_status);
2158
2159         if (update_type >= update_surface_trace_level)
2160                 update_surface_trace(dc, srf_updates, surface_count);
2161
2162
2163         if (update_type >= UPDATE_TYPE_FULL) {
2164
2165                 /* initialize scratch memory for building context */
2166                 context = dc_create_state(dc);
2167                 if (context == NULL) {
2168                         DC_ERROR("Failed to allocate new validate context!\n");
2169                         return;
2170                 }
2171
2172                 dc_resource_state_copy_construct(state, context);
2173
2174                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2175                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2176                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2177
2178                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2179                                 new_pipe->plane_state->force_full_update = true;
2180                 }
2181         }
2182
2183
2184         for (i = 0; i < surface_count; i++) {
2185                 struct dc_plane_state *surface = srf_updates[i].surface;
2186
2187                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2188
2189         }
2190
2191         copy_stream_update_to_stream(dc, context, stream, stream_update);
2192
2193         commit_planes_for_stream(
2194                                 dc,
2195                                 srf_updates,
2196                                 surface_count,
2197                                 stream,
2198                                 stream_update,
2199                                 update_type,
2200                                 context);
2201         /*update current_State*/
2202         if (dc->current_state != context) {
2203
2204                 struct dc_state *old = dc->current_state;
2205
2206                 dc->current_state = context;
2207                 dc_release_state(old);
2208
2209                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2210                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2211
2212                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2213                                 pipe_ctx->plane_state->force_full_update = false;
2214                 }
2215         }
2216         /*let's use current_state to update watermark etc*/
2217         if (update_type >= UPDATE_TYPE_FULL)
2218                 dc_post_update_surfaces_to_stream(dc);
2219
2220         return;
2221
2222 }
2223
2224 uint8_t dc_get_current_stream_count(struct dc *dc)
2225 {
2226         return dc->current_state->stream_count;
2227 }
2228
2229 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2230 {
2231         if (i < dc->current_state->stream_count)
2232                 return dc->current_state->streams[i];
2233         return NULL;
2234 }
2235
2236 enum dc_irq_source dc_interrupt_to_irq_source(
2237                 struct dc *dc,
2238                 uint32_t src_id,
2239                 uint32_t ext_id)
2240 {
2241         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2242 }
2243
2244 /**
2245  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2246  */
2247 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2248 {
2249
2250         if (dc == NULL)
2251                 return false;
2252
2253         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2254 }
2255
2256 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2257 {
2258         dal_irq_service_ack(dc->res_pool->irqs, src);
2259 }
2260
2261 void dc_set_power_state(
2262         struct dc *dc,
2263         enum dc_acpi_cm_power_state power_state)
2264 {
2265         struct kref refcount;
2266         struct display_mode_lib *dml = kzalloc(sizeof(struct display_mode_lib),
2267                                                 GFP_KERNEL);
2268
2269         ASSERT(dml);
2270         if (!dml)
2271                 return;
2272
2273         switch (power_state) {
2274         case DC_ACPI_CM_POWER_STATE_D0:
2275                 dc_resource_state_construct(dc, dc->current_state);
2276
2277                 dc->hwss.init_hw(dc);
2278
2279 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
2280                 if (dc->hwss.init_sys_ctx != NULL &&
2281                         dc->vm_pa_config.valid) {
2282                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2283                 }
2284 #endif
2285
2286                 break;
2287         default:
2288                 ASSERT(dc->current_state->stream_count == 0);
2289                 /* Zero out the current context so that on resume we start with
2290                  * clean state, and dc hw programming optimizations will not
2291                  * cause any trouble.
2292                  */
2293
2294                 /* Preserve refcount */
2295                 refcount = dc->current_state->refcount;
2296                 /* Preserve display mode lib */
2297                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2298
2299                 dc_resource_state_destruct(dc->current_state);
2300                 memset(dc->current_state, 0,
2301                                 sizeof(*dc->current_state));
2302
2303                 dc->current_state->refcount = refcount;
2304                 dc->current_state->bw_ctx.dml = *dml;
2305
2306                 break;
2307         }
2308
2309         kfree(dml);
2310 }
2311
2312 void dc_resume(struct dc *dc)
2313 {
2314
2315         uint32_t i;
2316
2317         for (i = 0; i < dc->link_count; i++)
2318                 core_link_resume(dc->links[i]);
2319 }
2320
2321 unsigned int dc_get_current_backlight_pwm(struct dc *dc)
2322 {
2323         struct abm *abm = dc->res_pool->abm;
2324
2325         if (abm)
2326                 return abm->funcs->get_current_backlight(abm);
2327
2328         return 0;
2329 }
2330
2331 unsigned int dc_get_target_backlight_pwm(struct dc *dc)
2332 {
2333         struct abm *abm = dc->res_pool->abm;
2334
2335         if (abm)
2336                 return abm->funcs->get_target_backlight(abm);
2337
2338         return 0;
2339 }
2340
2341 bool dc_is_dmcu_initialized(struct dc *dc)
2342 {
2343         struct dmcu *dmcu = dc->res_pool->dmcu;
2344
2345         if (dmcu)
2346                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2347         return false;
2348 }
2349
2350 bool dc_submit_i2c(
2351                 struct dc *dc,
2352                 uint32_t link_index,
2353                 struct i2c_command *cmd)
2354 {
2355
2356         struct dc_link *link = dc->links[link_index];
2357         struct ddc_service *ddc = link->ddc;
2358         return dce_i2c_submit_command(
2359                 dc->res_pool,
2360                 ddc->ddc_pin,
2361                 cmd);
2362 }
2363
2364 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2365 {
2366         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2367                 BREAK_TO_DEBUGGER();
2368                 return false;
2369         }
2370
2371         dc_sink_retain(sink);
2372
2373         dc_link->remote_sinks[dc_link->sink_count] = sink;
2374         dc_link->sink_count++;
2375
2376         return true;
2377 }
2378
2379 /**
2380  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2381  *
2382  * EDID length is in bytes
2383  */
2384 struct dc_sink *dc_link_add_remote_sink(
2385                 struct dc_link *link,
2386                 const uint8_t *edid,
2387                 int len,
2388                 struct dc_sink_init_data *init_data)
2389 {
2390         struct dc_sink *dc_sink;
2391         enum dc_edid_status edid_status;
2392
2393         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2394                 dm_error("Max EDID buffer size breached!\n");
2395                 return NULL;
2396         }
2397
2398         if (!init_data) {
2399                 BREAK_TO_DEBUGGER();
2400                 return NULL;
2401         }
2402
2403         if (!init_data->link) {
2404                 BREAK_TO_DEBUGGER();
2405                 return NULL;
2406         }
2407
2408         dc_sink = dc_sink_create(init_data);
2409
2410         if (!dc_sink)
2411                 return NULL;
2412
2413         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2414         dc_sink->dc_edid.length = len;
2415
2416         if (!link_add_remote_sink_helper(
2417                         link,
2418                         dc_sink))
2419                 goto fail_add_sink;
2420
2421         edid_status = dm_helpers_parse_edid_caps(
2422                         link->ctx,
2423                         &dc_sink->dc_edid,
2424                         &dc_sink->edid_caps);
2425
2426         /*
2427          * Treat device as no EDID device if EDID
2428          * parsing fails
2429          */
2430         if (edid_status != EDID_OK) {
2431                 dc_sink->dc_edid.length = 0;
2432                 dm_error("Bad EDID, status%d!\n", edid_status);
2433         }
2434
2435         return dc_sink;
2436
2437 fail_add_sink:
2438         dc_sink_release(dc_sink);
2439         return NULL;
2440 }
2441
2442 /**
2443  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2444  *
2445  * Note that this just removes the struct dc_sink - it doesn't
2446  * program hardware or alter other members of dc_link
2447  */
2448 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2449 {
2450         int i;
2451
2452         if (!link->sink_count) {
2453                 BREAK_TO_DEBUGGER();
2454                 return;
2455         }
2456
2457         for (i = 0; i < link->sink_count; i++) {
2458                 if (link->remote_sinks[i] == sink) {
2459                         dc_sink_release(sink);
2460                         link->remote_sinks[i] = NULL;
2461
2462                         /* shrink array to remove empty place */
2463                         while (i < link->sink_count - 1) {
2464                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2465                                 i++;
2466                         }
2467                         link->remote_sinks[i] = NULL;
2468                         link->sink_count--;
2469                         return;
2470                 }
2471         }
2472 }
2473
2474 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2475 {
2476         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2477         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2478         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2479         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2480         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
2481         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
2482         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
2483         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
2484         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
2485 }
2486 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
2487 {
2488         if (dc->hwss.set_clock)
2489                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
2490         return DC_ERROR_UNEXPECTED;
2491 }
2492 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
2493 {
2494         if (dc->hwss.get_clock)
2495                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
2496 }