2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
45 #include "link_hwss.h"
46 #include "link_encoder.h"
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
52 /*******************************************************************************
54 ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
59 for (i = 0; i < dc->link_count; i++) {
60 if (NULL != dc->links[i])
61 link_destroy(&dc->links[i]);
65 static bool create_links(
67 uint32_t num_virtual_links)
71 struct dc_bios *bios = dc->ctx->dc_bios;
75 connectors_num = bios->funcs->get_connectors_number(bios);
77 if (connectors_num > ENUM_ID_COUNT) {
79 "DC: Number of connectors %d exceeds maximum of %d!\n",
85 if (connectors_num == 0 && num_virtual_links == 0) {
86 dm_error("DC: Number of connectors is zero!\n");
90 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
95 for (i = 0; i < connectors_num; i++) {
96 struct link_init_data link_init_params = {0};
97 struct core_link *link;
99 link_init_params.ctx = dc->ctx;
100 /* next BIOS object table connector */
101 link_init_params.connector_index = i;
102 link_init_params.link_index = dc->link_count;
103 link_init_params.dc = dc;
104 link = link_create(&link_init_params);
107 dc->links[dc->link_count] = link;
113 for (i = 0; i < num_virtual_links; i++) {
114 struct core_link *link = dm_alloc(sizeof(*link));
115 struct encoder_init_data enc_init = {0};
124 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127 link->link_id.enum_id = ENUM_ID_1;
128 link->link_enc = dm_alloc(sizeof(*link->link_enc));
130 enc_init.ctx = dc->ctx;
131 enc_init.channel = CHANNEL_ID_UNKNOWN;
132 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134 enc_init.connector = link->link_id;
135 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137 enc_init.encoder.enum_id = ENUM_ID_1;
138 virtual_link_encoder_construct(link->link_enc, &enc_init);
140 link->public.link_index = dc->link_count;
141 dc->links[dc->link_count] = link;
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152 const struct dc_stream **stream, int num_streams,
155 /* TODO: Support multiple streams */
156 struct core_dc *core_dc = DC_TO_CORE(dc);
157 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
161 for (i = 0; i < MAX_PIPES; i++) {
162 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
164 if (pipe->stream == core_stream && pipe->stream_enc) {
165 core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
167 /* build and update the info frame */
168 resource_build_info_frame(pipe);
169 core_dc->hwss.update_info_frame(pipe);
177 static bool stream_get_crtc_position(struct dc *dc,
178 const struct dc_stream **stream, int num_streams,
179 unsigned int *v_pos, unsigned int *nom_v_pos)
181 /* TODO: Support multiple streams */
182 struct core_dc *core_dc = DC_TO_CORE(dc);
183 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
186 struct crtc_position position;
188 for (i = 0; i < MAX_PIPES; i++) {
189 struct pipe_ctx *pipe =
190 &core_dc->current_context->res_ctx.pipe_ctx[i];
192 if (pipe->stream == core_stream && pipe->stream_enc) {
193 core_dc->hwss.get_position(&pipe, 1, &position);
195 *v_pos = position.vertical_count;
196 *nom_v_pos = position.nominal_vcount;
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
205 struct core_dc *core_dc = DC_TO_CORE(dc);
206 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
209 struct pipe_ctx *pipes;
211 for (i = 0; i < MAX_PIPES; i++) {
212 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
215 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216 core_dc->hwss.program_gamut_remap(pipes);
224 static void set_static_screen_events(struct dc *dc,
225 const struct dc_stream **stream,
227 const struct dc_static_screen_events *events)
229 struct core_dc *core_dc = DC_TO_CORE(dc);
232 struct pipe_ctx *pipes_affected[MAX_PIPES];
233 int num_pipes_affected = 0;
235 for (i = 0; i < num_streams; i++) {
236 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
238 for (j = 0; j < MAX_PIPES; j++) {
239 if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
241 pipes_affected[num_pipes_affected++] =
242 &core_dc->current_context->res_ctx.pipe_ctx[j];
247 core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
250 static void set_drive_settings(struct dc *dc,
251 struct link_training_settings *lt_settings,
252 const struct dc_link *link)
254 struct core_dc *core_dc = DC_TO_CORE(dc);
257 for (i = 0; i < core_dc->link_count; i++) {
258 if (&core_dc->links[i]->public == link)
262 if (i >= core_dc->link_count)
263 ASSERT_CRITICAL(false);
265 dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
268 static void perform_link_training(struct dc *dc,
269 struct dc_link_settings *link_setting,
270 bool skip_video_pattern)
272 struct core_dc *core_dc = DC_TO_CORE(dc);
275 for (i = 0; i < core_dc->link_count; i++)
276 dc_link_dp_perform_link_training(
277 &core_dc->links[i]->public,
282 static void set_preferred_link_settings(struct dc *dc,
283 struct dc_link_settings *link_setting,
284 const struct dc_link *link)
286 struct core_link *core_link = DC_LINK_TO_CORE(link);
288 core_link->public.verified_link_cap.lane_count =
289 link_setting->lane_count;
290 core_link->public.verified_link_cap.link_rate =
291 link_setting->link_rate;
292 dp_retrain_link_dp_test(core_link, link_setting, false);
295 static void enable_hpd(const struct dc_link *link)
297 dc_link_dp_enable_hpd(link);
300 static void disable_hpd(const struct dc_link *link)
302 dc_link_dp_disable_hpd(link);
306 static void set_test_pattern(
307 const struct dc_link *link,
308 enum dp_test_pattern test_pattern,
309 const struct link_training_settings *p_link_settings,
310 const unsigned char *p_custom_pattern,
311 unsigned int cust_pattern_size)
314 dc_link_dp_set_test_pattern(
322 void set_dither_option(const struct dc_stream *dc_stream,
323 enum dc_dither_option option)
325 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
326 struct bit_depth_reduction_params params;
327 struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
328 struct pipe_ctx *pipes =
329 core_link->dc->current_context->res_ctx.pipe_ctx;
331 memset(¶ms, 0, sizeof(params));
334 if (option > DITHER_OPTION_MAX)
336 if (option == DITHER_OPTION_DEFAULT) {
337 switch (stream->public.timing.display_color_depth) {
338 case COLOR_DEPTH_666:
339 stream->public.dither_option = DITHER_OPTION_SPATIAL6;
341 case COLOR_DEPTH_888:
342 stream->public.dither_option = DITHER_OPTION_SPATIAL8;
344 case COLOR_DEPTH_101010:
345 stream->public.dither_option = DITHER_OPTION_SPATIAL10;
348 option = DITHER_OPTION_DISABLE;
351 stream->public.dither_option = option;
353 resource_build_bit_depth_reduction_params(stream,
355 stream->bit_depth_params = params;
357 opp_program_bit_depth_reduction(pipes->opp, ¶ms);
360 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
362 if (core_dc->hwss.set_drr != NULL) {
363 core_dc->public.stream_funcs.adjust_vmin_vmax =
364 stream_adjust_vmin_vmax;
367 core_dc->public.stream_funcs.set_static_screen_events =
368 set_static_screen_events;
370 core_dc->public.stream_funcs.get_crtc_position =
371 stream_get_crtc_position;
373 core_dc->public.stream_funcs.set_gamut_remap =
376 core_dc->public.stream_funcs.set_dither_option =
379 core_dc->public.link_funcs.set_drive_settings =
382 core_dc->public.link_funcs.perform_link_training =
383 perform_link_training;
385 core_dc->public.link_funcs.set_preferred_link_settings =
386 set_preferred_link_settings;
388 core_dc->public.link_funcs.enable_hpd =
391 core_dc->public.link_funcs.disable_hpd =
394 core_dc->public.link_funcs.set_test_pattern =
398 static void destruct(struct core_dc *dc)
400 dc_resource_validate_ctx_destruct(dc->current_context);
404 dc_destroy_resource_pool(dc);
406 if (dc->ctx->gpio_service)
407 dal_gpio_service_destroy(&dc->ctx->gpio_service);
410 dal_i2caux_destroy(&dc->ctx->i2caux);
412 if (dc->ctx->created_bios)
413 dal_bios_parser_destroy(&dc->ctx->dc_bios);
416 dal_logger_destroy(&dc->ctx->logger);
418 dm_free(dc->current_context);
419 dc->current_context = NULL;
425 static bool construct(struct core_dc *dc,
426 const struct dc_init_data *init_params)
428 struct dal_logger *logger;
429 struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
430 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
433 dm_error("%s: failed to create ctx\n", __func__);
437 dc->current_context = dm_alloc(sizeof(*dc->current_context));
439 if (!dc->current_context) {
440 dm_error("%s: failed to create validate ctx\n", __func__);
444 dc_ctx->cgs_device = init_params->cgs_device;
445 dc_ctx->driver_context = init_params->driver;
446 dc_ctx->dc = &dc->public;
447 dc_ctx->asic_id = init_params->asic_id;
450 logger = dal_logger_create(dc_ctx);
453 /* can *not* call logger. call base driver 'print error' */
454 dm_error("%s: failed to create Logger!\n", __func__);
457 dc_ctx->logger = logger;
459 dc->ctx->dce_environment = init_params->dce_environment;
461 dc_version = resource_parse_asic_id(init_params->asic_id);
462 dc->ctx->dce_version = dc_version;
464 /* Resource should construct all asic specific resources.
465 * This should be the only place where we need to parse the asic id
467 if (init_params->vbios_override)
468 dc_ctx->dc_bios = init_params->vbios_override;
470 /* Create BIOS parser */
471 struct bp_init_data bp_init_data;
473 bp_init_data.ctx = dc_ctx;
474 bp_init_data.bios = init_params->asic_id.atombios_base_address;
476 dc_ctx->dc_bios = dal_bios_parser_create(
477 &bp_init_data, dc_version);
479 if (!dc_ctx->dc_bios) {
480 ASSERT_CRITICAL(false);
484 dc_ctx->created_bios = true;
488 dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
490 if (!dc_ctx->i2caux) {
491 ASSERT_CRITICAL(false);
492 goto failed_to_create_i2caux;
495 /* Create GPIO service */
496 dc_ctx->gpio_service = dal_gpio_service_create(
498 dc_ctx->dce_environment,
501 if (!dc_ctx->gpio_service) {
502 ASSERT_CRITICAL(false);
506 dc->res_pool = dc_create_resource_pool(
508 init_params->num_virtual_links,
510 init_params->asic_id);
512 goto create_resource_fail;
514 if (!create_links(dc, init_params->num_virtual_links))
515 goto create_links_fail;
517 allocate_dc_stream_funcs(dc);
521 /**** error handling here ****/
523 create_resource_fail:
525 failed_to_create_i2caux:
535 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
537 fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
538 unsigned int pixDurationInPico = round(pixel_duration);
540 DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
542 arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
543 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
544 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
546 arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
547 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
548 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
550 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
551 WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
553 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
554 WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
558 /*******************************************************************************
560 ******************************************************************************/
562 struct dc *dc_create(const struct dc_init_data *init_params)
564 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
565 unsigned int full_pipe_count;
570 if (false == construct(core_dc, init_params))
573 /*TODO: separate HW and SW initialization*/
574 core_dc->hwss.init_hw(core_dc);
576 full_pipe_count = core_dc->res_pool->pipe_count;
577 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
579 core_dc->public.caps.max_streams = min(
581 core_dc->res_pool->stream_enc_count);
583 core_dc->public.caps.max_links = core_dc->link_count;
584 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
586 core_dc->public.config = init_params->flags;
588 dm_logger_write(core_dc->ctx->logger, LOG_DC,
589 "Display Core initialized\n");
592 /* TODO: missing feature to be enabled */
593 core_dc->public.debug.disable_dfs_bypass = true;
595 return &core_dc->public;
604 void dc_destroy(struct dc **dc)
606 struct core_dc *core_dc = DC_TO_CORE(*dc);
612 static bool is_validation_required(
613 const struct core_dc *dc,
614 const struct dc_validation_set set[],
617 const struct validate_context *context = dc->current_context;
620 if (context->stream_count != set_count)
623 for (i = 0; i < set_count; i++) {
625 if (set[i].surface_count != context->stream_status[i].surface_count)
627 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
630 for (j = 0; j < set[i].surface_count; j++) {
631 struct dc_surface temp_surf;
632 memset(&temp_surf, 0, sizeof(temp_surf));
634 temp_surf = *context->stream_status[i].surfaces[j];
635 temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
636 temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
637 temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
639 if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
647 struct validate_context *dc_get_validate_context(
649 const struct dc_validation_set set[],
652 struct core_dc *core_dc = DC_TO_CORE(dc);
653 enum dc_status result = DC_ERROR_UNEXPECTED;
654 struct validate_context *context;
656 context = dm_alloc(sizeof(struct validate_context));
658 goto context_alloc_fail;
660 if (!is_validation_required(core_dc, set, set_count)) {
661 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
665 result = core_dc->res_pool->funcs->validate_with_context(
666 core_dc, set, set_count, context, core_dc->current_context);
669 if (result != DC_OK) {
670 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
671 "%s:resource validation failed, dc_status:%d\n",
675 dc_resource_validate_ctx_destruct(context);
684 bool dc_validate_resources(
686 const struct dc_validation_set set[],
689 struct core_dc *core_dc = DC_TO_CORE(dc);
690 enum dc_status result = DC_ERROR_UNEXPECTED;
691 struct validate_context *context;
693 context = dm_alloc(sizeof(struct validate_context));
695 goto context_alloc_fail;
697 result = core_dc->res_pool->funcs->validate_with_context(
698 core_dc, set, set_count, context, NULL);
701 if (result != DC_OK) {
702 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
703 "%s:resource validation failed, dc_status:%d\n",
708 dc_resource_validate_ctx_destruct(context);
712 return result == DC_OK;
715 bool dc_validate_guaranteed(
717 const struct dc_stream *stream)
719 struct core_dc *core_dc = DC_TO_CORE(dc);
720 enum dc_status result = DC_ERROR_UNEXPECTED;
721 struct validate_context *context;
723 context = dm_alloc(sizeof(struct validate_context));
725 goto context_alloc_fail;
727 result = core_dc->res_pool->funcs->validate_guaranteed(
728 core_dc, stream, context);
730 dc_resource_validate_ctx_destruct(context);
734 if (result != DC_OK) {
735 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
736 "%s:guaranteed validation failed, dc_status:%d\n",
741 return (result == DC_OK);
744 static void program_timing_sync(
745 struct core_dc *core_dc,
746 struct validate_context *ctx)
750 int pipe_count = core_dc->res_pool->pipe_count;
751 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
753 for (i = 0; i < pipe_count; i++) {
754 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
757 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
760 for (i = 0; i < pipe_count; i++) {
762 struct pipe_ctx *pipe_set[MAX_PIPES];
764 if (!unsynced_pipes[i])
767 pipe_set[0] = unsynced_pipes[i];
768 unsynced_pipes[i] = NULL;
770 /* Add tg to the set, search rest of the tg's for ones with
771 * same timing, add all tgs with same timing to the group
773 for (j = i + 1; j < pipe_count; j++) {
774 if (!unsynced_pipes[j])
777 if (resource_are_streams_timing_synchronizable(
778 unsynced_pipes[j]->stream,
779 pipe_set[0]->stream)) {
780 pipe_set[group_size] = unsynced_pipes[j];
781 unsynced_pipes[j] = NULL;
786 /* set first unblanked pipe as master */
787 for (j = 0; j < group_size; j++) {
788 struct pipe_ctx *temp;
790 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
795 pipe_set[0] = pipe_set[j];
801 /* remove any other unblanked pipes as they have already been synced */
802 for (j = j + 1; j < group_size; j++) {
803 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
805 pipe_set[j] = pipe_set[group_size];
810 if (group_size > 1) {
811 core_dc->hwss.enable_timing_synchronization(
812 core_dc, group_index, group_size, pipe_set);
818 static bool streams_changed(
820 const struct dc_stream *streams[],
821 uint8_t stream_count)
825 if (stream_count != dc->current_context->stream_count)
828 for (i = 0; i < dc->current_context->stream_count; i++) {
829 if (&dc->current_context->streams[i]->public != streams[i])
836 bool dc_enable_stereo(
838 struct validate_context *context,
839 const struct dc_stream *streams[],
840 uint8_t stream_count)
844 struct pipe_ctx *pipe;
845 struct core_dc *core_dc = DC_TO_CORE(dc);
848 struct compressor *fbc_compressor = core_dc->fbc_compressor;
851 for (i = 0; i < MAX_PIPES; i++) {
853 pipe = &context->res_ctx.pipe_ctx[i];
855 pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
856 for (j = 0 ; pipe && j < stream_count; j++) {
857 if (streams[j] && streams[j] == &pipe->stream->public &&
858 core_dc->hwss.setup_stereo)
859 core_dc->hwss.setup_stereo(pipe, core_dc);
864 if (fbc_compressor != NULL &&
865 fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
867 fbc_compressor->funcs->disable_fbc(fbc_compressor);
873 bool dc_commit_streams(
875 const struct dc_stream *streams[],
876 uint8_t stream_count)
878 struct core_dc *core_dc = DC_TO_CORE(dc);
879 struct dc_bios *dcb = core_dc->ctx->dc_bios;
880 enum dc_status result = DC_ERROR_UNEXPECTED;
881 struct validate_context *context;
882 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
885 if (false == streams_changed(core_dc, streams, stream_count))
888 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
889 __func__, stream_count);
891 for (i = 0; i < stream_count; i++) {
892 const struct dc_stream *stream = streams[i];
893 const struct dc_stream_status *status = dc_stream_get_status(stream);
896 dc_stream_log(stream,
897 core_dc->ctx->logger,
900 set[i].stream = stream;
903 set[i].surface_count = status->surface_count;
904 for (j = 0; j < status->surface_count; j++)
905 set[i].surfaces[j] = status->surfaces[j];
910 context = dm_alloc(sizeof(struct validate_context));
912 goto context_alloc_fail;
914 result = core_dc->res_pool->funcs->validate_with_context(
915 core_dc, set, stream_count, context, core_dc->current_context);
916 if (result != DC_OK){
917 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
918 "%s: Context validation failed! dc_status:%d\n",
922 dc_resource_validate_ctx_destruct(context);
926 if (!dcb->funcs->is_accelerated_mode(dcb)) {
927 core_dc->hwss.enable_accelerated_mode(core_dc);
930 if (result == DC_OK) {
931 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
934 program_timing_sync(core_dc, context);
936 for (i = 0; i < context->stream_count; i++) {
937 const struct core_sink *sink = context->streams[i]->sink;
939 for (j = 0; j < context->stream_status[i].surface_count; j++) {
940 struct core_surface *surface =
941 DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
943 core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
944 dc_enable_stereo(dc, context, streams, stream_count);
947 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
948 context->streams[i]->public.timing.h_addressable,
949 context->streams[i]->public.timing.v_addressable,
950 context->streams[i]->public.timing.h_total,
951 context->streams[i]->public.timing.v_total,
952 context->streams[i]->public.timing.pix_clk_khz);
955 dc_resource_validate_ctx_destruct(core_dc->current_context);
956 dm_free(core_dc->current_context);
958 core_dc->current_context = context;
960 return (result == DC_OK);
966 return (result == DC_OK);
969 bool dc_post_update_surfaces_to_stream(struct dc *dc)
972 struct core_dc *core_dc = DC_TO_CORE(dc);
973 struct validate_context *context = core_dc->current_context;
975 post_surface_trace(dc);
977 for (i = 0; i < core_dc->res_pool->pipe_count; i++)
978 if (context->res_ctx.pipe_ctx[i].stream == NULL
979 || context->res_ctx.pipe_ctx[i].surface == NULL)
980 core_dc->hwss.power_down_front_end(core_dc, i);
982 /* 3rd param should be true, temp w/a for RV*/
983 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
984 core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
986 core_dc->hwss.set_bandwidth(core_dc, context, true);
991 bool dc_commit_surfaces_to_stream(
993 const struct dc_surface **new_surfaces,
994 uint8_t new_surface_count,
995 const struct dc_stream *dc_stream)
997 struct dc_surface_update updates[MAX_SURFACES];
998 struct dc_flip_addrs flip_addr[MAX_SURFACES];
999 struct dc_plane_info plane_info[MAX_SURFACES];
1000 struct dc_scaling_info scaling_info[MAX_SURFACES];
1002 struct dc_stream_update *stream_update =
1003 dm_alloc(sizeof(struct dc_stream_update));
1005 if (!stream_update) {
1006 BREAK_TO_DEBUGGER();
1010 memset(updates, 0, sizeof(updates));
1011 memset(flip_addr, 0, sizeof(flip_addr));
1012 memset(plane_info, 0, sizeof(plane_info));
1013 memset(scaling_info, 0, sizeof(scaling_info));
1015 stream_update->src = dc_stream->src;
1016 stream_update->dst = dc_stream->dst;
1018 for (i = 0; i < new_surface_count; i++) {
1019 updates[i].surface = new_surfaces[i];
1021 (struct dc_gamma *)new_surfaces[i]->gamma_correction;
1022 flip_addr[i].address = new_surfaces[i]->address;
1023 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
1024 plane_info[i].color_space = new_surfaces[i]->color_space;
1025 plane_info[i].format = new_surfaces[i]->format;
1026 plane_info[i].plane_size = new_surfaces[i]->plane_size;
1027 plane_info[i].rotation = new_surfaces[i]->rotation;
1028 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
1029 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
1030 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1031 plane_info[i].visible = new_surfaces[i]->visible;
1032 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1033 plane_info[i].dcc = new_surfaces[i]->dcc;
1034 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1035 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1036 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1037 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1039 updates[i].flip_addr = &flip_addr[i];
1040 updates[i].plane_info = &plane_info[i];
1041 updates[i].scaling_info = &scaling_info[i];
1044 dc_update_surfaces_and_stream(
1048 dc_stream, stream_update);
1050 dc_post_update_surfaces_to_stream(dc);
1052 dm_free(stream_update);
1056 static bool is_surface_in_context(
1057 const struct validate_context *context,
1058 const struct dc_surface *surface)
1062 for (j = 0; j < MAX_PIPES; j++) {
1063 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1065 if (surface == &pipe_ctx->surface->public) {
1073 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1076 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1077 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1079 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1080 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1081 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1082 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1084 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1085 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1086 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1087 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1089 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1090 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1091 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1094 ASSERT_CRITICAL(false);
1099 static enum surface_update_type get_plane_info_update_type(
1100 const struct dc_surface_update *u,
1103 struct dc_plane_info temp_plane_info;
1104 memset(&temp_plane_info, 0, sizeof(temp_plane_info));
1107 return UPDATE_TYPE_FAST;
1109 temp_plane_info = *u->plane_info;
1111 /* Copy all parameters that will cause a full update
1112 * from current surface, the rest of the parameters
1113 * from provided plane configuration.
1114 * Perform memory compare and special validation
1115 * for those that can cause fast/medium updates
1118 /* Full update parameters */
1119 temp_plane_info.color_space = u->surface->color_space;
1120 temp_plane_info.dcc = u->surface->dcc;
1121 temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1122 temp_plane_info.plane_size = u->surface->plane_size;
1123 temp_plane_info.rotation = u->surface->rotation;
1124 temp_plane_info.stereo_format = u->surface->stereo_format;
1125 temp_plane_info.tiling_info = u->surface->tiling_info;
1127 if (surface_index == 0)
1128 temp_plane_info.visible = u->plane_info->visible;
1130 temp_plane_info.visible = u->surface->visible;
1132 if (memcmp(u->plane_info, &temp_plane_info,
1133 sizeof(struct dc_plane_info)) != 0)
1134 return UPDATE_TYPE_FULL;
1136 if (pixel_format_to_bpp(u->plane_info->format) !=
1137 pixel_format_to_bpp(u->surface->format)) {
1138 return UPDATE_TYPE_FULL;
1140 return UPDATE_TYPE_MED;
1144 static enum surface_update_type get_scaling_info_update_type(
1145 const struct dc_surface_update *u)
1147 if (!u->scaling_info)
1148 return UPDATE_TYPE_FAST;
1150 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1151 || u->scaling_info->src_rect.height != u->surface->src_rect.height
1152 || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1153 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1154 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1155 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1156 return UPDATE_TYPE_FULL;
1158 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1159 || u->scaling_info->src_rect.y != u->surface->src_rect.y
1160 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1161 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1162 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1163 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1164 return UPDATE_TYPE_MED;
1166 return UPDATE_TYPE_FAST;
1169 static enum surface_update_type det_surface_update(
1170 const struct core_dc *dc,
1171 const struct dc_surface_update *u,
1174 const struct validate_context *context = dc->current_context;
1175 enum surface_update_type type = UPDATE_TYPE_FAST;
1176 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1178 if (!is_surface_in_context(context, u->surface))
1179 return UPDATE_TYPE_FULL;
1181 type = get_plane_info_update_type(u, surface_index);
1182 if (overall_type < type)
1183 overall_type = type;
1185 type = get_scaling_info_update_type(u);
1186 if (overall_type < type)
1187 overall_type = type;
1189 if (u->in_transfer_func ||
1190 u->hdr_static_metadata) {
1191 if (overall_type < UPDATE_TYPE_MED)
1192 overall_type = UPDATE_TYPE_MED;
1195 return overall_type;
1198 enum surface_update_type dc_check_update_surfaces_for_stream(
1200 struct dc_surface_update *updates,
1202 struct dc_stream_update *stream_update,
1203 const struct dc_stream_status *stream_status)
1205 struct core_dc *core_dc = DC_TO_CORE(dc);
1207 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1209 if (stream_status == NULL || stream_status->surface_count != surface_count)
1210 return UPDATE_TYPE_FULL;
1213 return UPDATE_TYPE_FULL;
1215 for (i = 0 ; i < surface_count; i++) {
1216 enum surface_update_type type =
1217 det_surface_update(core_dc, &updates[i], i);
1219 if (type == UPDATE_TYPE_FULL)
1222 if (overall_type < type)
1223 overall_type = type;
1226 return overall_type;
1229 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1231 void dc_update_surfaces_and_stream(struct dc *dc,
1232 struct dc_surface_update *srf_updates, int surface_count,
1233 const struct dc_stream *dc_stream,
1234 struct dc_stream_update *stream_update)
1236 struct core_dc *core_dc = DC_TO_CORE(dc);
1237 struct validate_context *context;
1239 enum surface_update_type update_type;
1240 const struct dc_stream_status *stream_status;
1241 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1243 stream_status = dc_stream_get_status(dc_stream);
1244 ASSERT(stream_status);
1246 return; /* Cannot commit surface to stream that is not committed */
1249 if (srf_updates->flip_addr) {
1250 if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
1254 context = core_dc->current_context;
1256 /* update current stream with the new updates */
1257 if (stream_update) {
1258 if ((stream_update->src.height != 0) &&
1259 (stream_update->src.width != 0))
1260 stream->public.src = stream_update->src;
1262 if ((stream_update->dst.height != 0) &&
1263 (stream_update->dst.width != 0))
1264 stream->public.dst = stream_update->dst;
1266 if (stream_update->out_transfer_func &&
1267 stream_update->out_transfer_func !=
1268 dc_stream->out_transfer_func) {
1269 if (dc_stream->out_transfer_func != NULL)
1270 dc_transfer_func_release(dc_stream->out_transfer_func);
1271 dc_transfer_func_retain(stream_update->out_transfer_func);
1272 stream->public.out_transfer_func =
1273 stream_update->out_transfer_func;
1277 /* do not perform surface update if surface has invalid dimensions
1278 * (all zero) and no scaling_info is provided
1280 if (surface_count > 0 &&
1281 srf_updates->surface->src_rect.width == 0 &&
1282 srf_updates->surface->src_rect.height == 0 &&
1283 srf_updates->surface->dst_rect.width == 0 &&
1284 srf_updates->surface->dst_rect.height == 0 &&
1285 !srf_updates->scaling_info) {
1290 update_type = dc_check_update_surfaces_for_stream(
1291 dc, srf_updates, surface_count, stream_update, stream_status);
1293 if (update_type >= update_surface_trace_level)
1294 update_surface_trace(dc, srf_updates, surface_count);
1296 if (update_type >= UPDATE_TYPE_FULL) {
1297 const struct dc_surface *new_surfaces[MAX_SURFACES] = {0};
1299 for (i = 0; i < surface_count; i++)
1300 new_surfaces[i] = srf_updates[i].surface;
1302 /* initialize scratch memory for building context */
1303 context = dm_alloc(sizeof(*context));
1304 dc_resource_validate_ctx_copy_construct(
1305 core_dc->current_context, context);
1307 /* add surface to context */
1308 if (!resource_attach_surfaces_to_context(
1309 new_surfaces, surface_count, dc_stream,
1310 context, core_dc->res_pool)) {
1311 BREAK_TO_DEBUGGER();
1316 /* save update parameters into surface */
1317 for (i = 0; i < surface_count; i++) {
1318 struct core_surface *surface =
1319 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1321 if (srf_updates[i].flip_addr) {
1322 surface->public.address = srf_updates[i].flip_addr->address;
1323 surface->public.flip_immediate =
1324 srf_updates[i].flip_addr->flip_immediate;
1327 if (srf_updates[i].scaling_info) {
1328 surface->public.scaling_quality =
1329 srf_updates[i].scaling_info->scaling_quality;
1330 surface->public.dst_rect =
1331 srf_updates[i].scaling_info->dst_rect;
1332 surface->public.src_rect =
1333 srf_updates[i].scaling_info->src_rect;
1334 surface->public.clip_rect =
1335 srf_updates[i].scaling_info->clip_rect;
1338 if (srf_updates[i].plane_info) {
1339 surface->public.color_space =
1340 srf_updates[i].plane_info->color_space;
1341 surface->public.format =
1342 srf_updates[i].plane_info->format;
1343 surface->public.plane_size =
1344 srf_updates[i].plane_info->plane_size;
1345 surface->public.rotation =
1346 srf_updates[i].plane_info->rotation;
1347 surface->public.horizontal_mirror =
1348 srf_updates[i].plane_info->horizontal_mirror;
1349 surface->public.stereo_format =
1350 srf_updates[i].plane_info->stereo_format;
1351 surface->public.tiling_info =
1352 srf_updates[i].plane_info->tiling_info;
1353 surface->public.visible =
1354 srf_updates[i].plane_info->visible;
1355 surface->public.per_pixel_alpha =
1356 srf_updates[i].plane_info->per_pixel_alpha;
1357 surface->public.dcc =
1358 srf_updates[i].plane_info->dcc;
1361 if (update_type >= UPDATE_TYPE_MED) {
1362 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1363 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1365 if (pipe_ctx->surface != surface)
1368 resource_build_scaling_params(pipe_ctx);
1372 if (srf_updates[i].gamma &&
1373 srf_updates[i].gamma != surface->public.gamma_correction) {
1374 if (surface->public.gamma_correction != NULL)
1375 dc_gamma_release(&surface->public.
1378 dc_gamma_retain(srf_updates[i].gamma);
1379 surface->public.gamma_correction =
1380 srf_updates[i].gamma;
1383 if (srf_updates[i].in_transfer_func &&
1384 srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1385 if (surface->public.in_transfer_func != NULL)
1386 dc_transfer_func_release(
1390 dc_transfer_func_retain(
1391 srf_updates[i].in_transfer_func);
1392 surface->public.in_transfer_func =
1393 srf_updates[i].in_transfer_func;
1396 if (srf_updates[i].hdr_static_metadata)
1397 surface->public.hdr_static_ctx =
1398 *(srf_updates[i].hdr_static_metadata);
1401 if (update_type == UPDATE_TYPE_FULL) {
1402 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1403 BREAK_TO_DEBUGGER();
1406 core_dc->hwss.set_bandwidth(core_dc, context, false);
1407 context_clock_trace(dc, context);
1411 if (surface_count == 0)
1412 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1414 /* Lock pipes for provided surfaces, or all active if full update*/
1415 for (i = 0; i < surface_count; i++) {
1416 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1418 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1419 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1421 if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface)
1423 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1426 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1427 core_dc->hwss.pipe_control_lock(
1433 if (update_type == UPDATE_TYPE_FULL)
1438 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1439 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1440 struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1441 bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface;
1442 struct dc_cursor_position position = { 0 };
1444 if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface)
1447 if (!pipe_ctx->top_pipe)
1448 core_dc->hwss.apply_ctx_for_surface(
1449 core_dc, pipe_ctx->surface, context);
1451 /* TODO: this is a hack w/a for switching from mpo to pipe split */
1452 dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position);
1454 if (is_new_pipe_surface) {
1455 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1456 core_dc->hwss.set_input_transfer_func(
1457 pipe_ctx, pipe_ctx->surface);
1458 core_dc->hwss.set_output_transfer_func(
1459 pipe_ctx, pipe_ctx->stream);
1463 if (update_type > UPDATE_TYPE_FAST)
1464 context_timing_trace(dc, &context->res_ctx);
1466 /* Perform requested Updates */
1467 for (i = 0; i < surface_count; i++) {
1468 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1470 if (update_type == UPDATE_TYPE_MED)
1471 core_dc->hwss.apply_ctx_for_surface(
1472 core_dc, surface, context);
1474 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1475 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1477 if (pipe_ctx->surface != surface)
1480 if (srf_updates[i].flip_addr)
1481 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1483 if (update_type == UPDATE_TYPE_FAST)
1486 if (srf_updates[i].in_transfer_func)
1487 core_dc->hwss.set_input_transfer_func(
1488 pipe_ctx, pipe_ctx->surface);
1490 if (stream_update != NULL &&
1491 stream_update->out_transfer_func != NULL) {
1492 core_dc->hwss.set_output_transfer_func(
1493 pipe_ctx, pipe_ctx->stream);
1496 if (srf_updates[i].hdr_static_metadata) {
1497 resource_build_info_frame(pipe_ctx);
1498 core_dc->hwss.update_info_frame(pipe_ctx);
1504 for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1505 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1507 for (j = 0; j < surface_count; j++) {
1508 if (update_type != UPDATE_TYPE_FULL &&
1509 srf_updates[j].surface != &pipe_ctx->surface->public)
1511 if (!pipe_ctx->surface || pipe_ctx->top_pipe)
1514 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1515 core_dc->hwss.pipe_control_lock(
1524 if (core_dc->current_context != context) {
1525 dc_resource_validate_ctx_destruct(core_dc->current_context);
1526 dm_free(core_dc->current_context);
1528 core_dc->current_context = context;
1533 dc_resource_validate_ctx_destruct(context);
1537 uint8_t dc_get_current_stream_count(const struct dc *dc)
1539 struct core_dc *core_dc = DC_TO_CORE(dc);
1540 return core_dc->current_context->stream_count;
1543 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1545 struct core_dc *core_dc = DC_TO_CORE(dc);
1546 if (i < core_dc->current_context->stream_count)
1547 return &(core_dc->current_context->streams[i]->public);
1551 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1553 struct core_dc *core_dc = DC_TO_CORE(dc);
1554 return &core_dc->links[link_index]->public;
1557 const struct graphics_object_id dc_get_link_id_at_index(
1558 struct dc *dc, uint32_t link_index)
1560 struct core_dc *core_dc = DC_TO_CORE(dc);
1561 return core_dc->links[link_index]->link_id;
1564 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1565 struct dc *dc, uint32_t link_index)
1567 struct core_dc *core_dc = DC_TO_CORE(dc);
1568 return core_dc->links[link_index]->public.irq_source_hpd;
1571 const struct audio **dc_get_audios(struct dc *dc)
1573 struct core_dc *core_dc = DC_TO_CORE(dc);
1574 return (const struct audio **)core_dc->res_pool->audios;
1577 enum dc_irq_source dc_interrupt_to_irq_source(
1582 struct core_dc *core_dc = DC_TO_CORE(dc);
1583 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1586 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1588 struct core_dc *core_dc;
1592 core_dc = DC_TO_CORE(dc);
1594 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1597 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1599 struct core_dc *core_dc = DC_TO_CORE(dc);
1600 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1603 void dc_set_power_state(
1605 enum dc_acpi_cm_power_state power_state)
1607 struct core_dc *core_dc = DC_TO_CORE(dc);
1609 switch (power_state) {
1610 case DC_ACPI_CM_POWER_STATE_D0:
1611 core_dc->hwss.init_hw(core_dc);
1615 core_dc->hwss.power_down(core_dc);
1617 /* Zero out the current context so that on resume we start with
1618 * clean state, and dc hw programming optimizations will not
1619 * cause any trouble.
1621 memset(core_dc->current_context, 0,
1622 sizeof(*core_dc->current_context));
1629 void dc_resume(const struct dc *dc)
1631 struct core_dc *core_dc = DC_TO_CORE(dc);
1635 for (i = 0; i < core_dc->link_count; i++)
1636 core_link_resume(core_dc->links[i]);
1639 bool dc_read_aux_dpcd(
1641 uint32_t link_index,
1646 struct core_dc *core_dc = DC_TO_CORE(dc);
1648 struct core_link *link = core_dc->links[link_index];
1649 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1656 return r == DDC_RESULT_SUCESSFULL;
1659 bool dc_write_aux_dpcd(
1661 uint32_t link_index,
1663 const uint8_t *data,
1666 struct core_dc *core_dc = DC_TO_CORE(dc);
1667 struct core_link *link = core_dc->links[link_index];
1669 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1676 return r == DDC_RESULT_SUCESSFULL;
1679 bool dc_read_aux_i2c(
1681 uint32_t link_index,
1682 enum i2c_mot_mode mot,
1687 struct core_dc *core_dc = DC_TO_CORE(dc);
1689 struct core_link *link = core_dc->links[link_index];
1690 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1697 return r == DDC_RESULT_SUCESSFULL;
1700 bool dc_write_aux_i2c(
1702 uint32_t link_index,
1703 enum i2c_mot_mode mot,
1705 const uint8_t *data,
1708 struct core_dc *core_dc = DC_TO_CORE(dc);
1709 struct core_link *link = core_dc->links[link_index];
1711 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1718 return r == DDC_RESULT_SUCESSFULL;
1721 bool dc_query_ddc_data(
1723 uint32_t link_index,
1726 uint32_t write_size,
1728 uint32_t read_size) {
1730 struct core_dc *core_dc = DC_TO_CORE(dc);
1732 struct core_link *link = core_dc->links[link_index];
1734 bool result = dal_ddc_service_query_ddc_data(
1747 uint32_t link_index,
1748 struct i2c_command *cmd)
1750 struct core_dc *core_dc = DC_TO_CORE(dc);
1752 struct core_link *link = core_dc->links[link_index];
1753 struct ddc_service *ddc = link->public.ddc;
1755 return dal_i2caux_submit_i2c_command(
1761 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1763 struct dc_link *dc_link = &core_link->public;
1765 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1766 BREAK_TO_DEBUGGER();
1770 dc_sink_retain(sink);
1772 dc_link->remote_sinks[dc_link->sink_count] = sink;
1773 dc_link->sink_count++;
1778 struct dc_sink *dc_link_add_remote_sink(
1779 const struct dc_link *link,
1780 const uint8_t *edid,
1782 struct dc_sink_init_data *init_data)
1784 struct dc_sink *dc_sink;
1785 enum dc_edid_status edid_status;
1786 struct core_link *core_link = DC_LINK_TO_LINK(link);
1788 if (len > MAX_EDID_BUFFER_SIZE) {
1789 dm_error("Max EDID buffer size breached!\n");
1794 BREAK_TO_DEBUGGER();
1798 if (!init_data->link) {
1799 BREAK_TO_DEBUGGER();
1803 dc_sink = dc_sink_create(init_data);
1808 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1809 dc_sink->dc_edid.length = len;
1811 if (!link_add_remote_sink_helper(
1816 edid_status = dm_helpers_parse_edid_caps(
1819 &dc_sink->edid_caps);
1821 if (edid_status != EDID_OK)
1826 dc_link_remove_remote_sink(link, dc_sink);
1828 dc_sink_release(dc_sink);
1832 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1834 struct core_link *core_link = DC_LINK_TO_LINK(link);
1835 struct dc_link *dc_link = &core_link->public;
1837 dc_link->local_sink = sink;
1840 dc_link->type = dc_connection_none;
1842 dc_link->type = dc_connection_single;
1846 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1849 struct core_link *core_link = DC_LINK_TO_LINK(link);
1850 struct dc_link *dc_link = &core_link->public;
1852 if (!link->sink_count) {
1853 BREAK_TO_DEBUGGER();
1857 for (i = 0; i < dc_link->sink_count; i++) {
1858 if (dc_link->remote_sinks[i] == sink) {
1859 dc_sink_release(sink);
1860 dc_link->remote_sinks[i] = NULL;
1862 /* shrink array to remove empty place */
1863 while (i < dc_link->sink_count - 1) {
1864 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1867 dc_link->remote_sinks[i] = NULL;
1868 dc_link->sink_count--;
1874 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1877 struct core_dc *core_dc = DC_TO_CORE(dc);
1878 struct mem_input *mi = NULL;
1880 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1881 if (core_dc->res_pool->mis[i] != NULL) {
1882 mi = core_dc->res_pool->mis[i];
1887 dm_error("no mem_input!\n");
1891 if (mi->funcs->mem_input_update_dchub)
1892 mi->funcs->mem_input_update_dchub(mi, dh_data);
1894 ASSERT(mi->funcs->mem_input_update_dchub);