drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #include "dmub/dmub_srv.h"
  70
  71 #include "dce/dmub_hw_lock_mgr.h"
  72
  73 #include "dc_trace.h"
  74
  75 #define CTX \
  76         dc->ctx
  77
  78 #define DC_LOGGER \
  79         dc->ctx->logger
  80
  81 static const char DC_BUILD_ID[] = "production-build";
  82
  83 /**
  84  * DOC: Overview
  85  *
  86  * DC is the OS-agnostic component of the amdgpu DC driver.
  87  *
  88  * DC maintains and validates a set of structs representing the state of the
  89  * driver and writes that state to AMD hardware
  90  *
  91  * Main DC HW structs:
  92  *
  93  * struct dc - The central struct.  One per driver.  Created on driver load,
  94  * destroyed on driver unload.
  95  *
  96  * struct dc_context - One per driver.
  97  * Used as a backpointer by most other structs in dc.
  98  *
  99  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 100  * plugpoints).  Created on driver load, destroyed on driver unload.
 101  *
 102  * struct dc_sink - One per display.  Created on boot or hotplug.
 103  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 104  * (the display directly attached).  It may also have one or more remote
 105  * sinks (in the Multi-Stream Transport case)
 106  *
 107  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 108  * main pipeline.  Not directly accessible by dm.
 109  *
 110  * Main dc state structs:
 111  *
 112  * These structs can be created and destroyed as needed.  There is a full set of
 113  * these structs in dc->current_state representing the currently programmed state.
 114  *
 115  * struct dc_state - The global DC state to track global state information,
 116  * such as bandwidth values.
 117  *
 118  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 119  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 120  *
 121  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 122  * and may have more in the Multi-Plane Overlay case.
 123  *
 124  * struct resource_context - Represents the programmable state of everything in
 125  * the resource_pool.  Not directly accessible by dm.
 126  *
 127  * struct pipe_ctx - A member of struct resource_context.  Represents the
 128  * internal hardware pipeline components.  Each dc_plane_state has either
 129  * one or two (in the pipe-split case).
 130  */
 131
 132 /*******************************************************************************
 133  * Private functions
 134  ******************************************************************************/
 135
 136 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 137 {
 138         if (new > *original)
 139                 *original = new;
 140 }
 141
 142 static void destroy_links(struct dc *dc)
 143 {
 144         uint32_t i;
 145
 146         for (i = 0; i < dc->link_count; i++) {
 147                 if (NULL != dc->links[i])
 148                         link_destroy(&dc->links[i]);
 149         }
 150 }
 151
 152 static bool create_links(
 153                 struct dc *dc,
 154                 uint32_t num_virtual_links)
 155 {
 156         int i;
 157         int connectors_num;
 158         struct dc_bios *bios = dc->ctx->dc_bios;
 159
 160         dc->link_count = 0;
 161
 162         connectors_num = bios->funcs->get_connectors_number(bios);
 163
 164         if (connectors_num > ENUM_ID_COUNT) {
 165                 dm_error(
 166                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 167                         connectors_num,
 168                         ENUM_ID_COUNT);
 169                 return false;
 170         }
 171
 172         dm_output_to_console(
 173                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 174                 __func__,
 175                 connectors_num,
 176                 num_virtual_links);
 177
 178         for (i = 0; i < connectors_num; i++) {
 179                 struct link_init_data link_init_params = {0};
 180                 struct dc_link *link;
 181
 182                 link_init_params.ctx = dc->ctx;
 183                 /* next BIOS object table connector */
 184                 link_init_params.connector_index = i;
 185                 link_init_params.link_index = dc->link_count;
 186                 link_init_params.dc = dc;
 187                 link = link_create(&link_init_params);
 188
 189                 if (link) {
 190                         bool should_destory_link = false;
 191
 192                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 193                                 if (dc->config.edp_not_connected) {
 194                                         if (!IS_DIAG_DC(dc->ctx->dce_environment))
 195                                                 should_destory_link = true;
 196                                 } else {
 197                                         enum dc_connection_type type;
 198                                         dc_link_detect_sink(link, &type);
 199                                         if (type == dc_connection_none)
 200                                                 should_destory_link = true;
 201                                 }
 202                         }
 203
 204                         if (dc->config.force_enum_edp || !should_destory_link) {
 205                                 dc->links[dc->link_count] = link;
 206                                 link->dc = dc;
 207                                 ++dc->link_count;
 208                         } else {
 209                                 link_destroy(&link);
 210                         }
 211                 }
 212         }
 213
 214         for (i = 0; i < num_virtual_links; i++) {
 215                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 216                 struct encoder_init_data enc_init = {0};
 217
 218                 if (link == NULL) {
 219                         BREAK_TO_DEBUGGER();
 220                         goto failed_alloc;
 221                 }
 222
 223                 link->link_index = dc->link_count;
 224                 dc->links[dc->link_count] = link;
 225                 dc->link_count++;
 226
 227                 link->ctx = dc->ctx;
 228                 link->dc = dc;
 229                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 230                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 231                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 232                 link->link_id.enum_id = ENUM_ID_1;
 233                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 234
 235                 if (!link->link_enc) {
 236                         BREAK_TO_DEBUGGER();
 237                         goto failed_alloc;
 238                 }
 239
 240                 link->link_status.dpcd_caps = &link->dpcd_caps;
 241
 242                 enc_init.ctx = dc->ctx;
 243                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 244                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 245                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 246                 enc_init.connector = link->link_id;
 247                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 248                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 249                 enc_init.encoder.enum_id = ENUM_ID_1;
 250                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 251         }
 252
 253         return true;
 254
 255 failed_alloc:
 256         return false;
 257 }
 258
 259 static struct dc_perf_trace *dc_perf_trace_create(void)
 260 {
 261         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 262 }
 263
 264 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 265 {
 266         kfree(*perf_trace);
 267         *perf_trace = NULL;
 268 }
 269
 270 /**
 271  *****************************************************************************
 272  *  Function: dc_stream_adjust_vmin_vmax
 273  *
 274  *  @brief
 275  *     Looks up the pipe context of dc_stream_state and updates the
 276  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 277  *     Rate, which is a power-saving feature that targets reducing panel
 278  *     refresh rate while the screen is static
 279  *
 280  *  @param [in] dc: dc reference
 281  *  @param [in] stream: Initial dc stream state
 282  *  @param [in] adjust: Updated parameters for vertical_total_min and
 283  *  vertical_total_max
 284  *****************************************************************************
 285  */
 286 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 287                 struct dc_stream_state *stream,
 288                 struct dc_crtc_timing_adjust *adjust)
 289 {
 290         int i = 0;
 291         bool ret = false;
 292
 293         stream->adjust = *adjust;
 294
 295         for (i = 0; i < MAX_PIPES; i++) {
 296                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 297
 298                 if (pipe->stream == stream && pipe->stream_res.tg) {
 299                         dc->hwss.set_drr(&pipe,
 300                                         1,
 301                                         adjust->v_total_min,
 302                                         adjust->v_total_max,
 303                                         adjust->v_total_mid,
 304                                         adjust->v_total_mid_frame_num);
 305
 306                         ret = true;
 307                 }
 308         }
 309         return ret;
 310 }
 311
 312 bool dc_stream_get_crtc_position(struct dc *dc,
 313                 struct dc_stream_state **streams, int num_streams,
 314                 unsigned int *v_pos, unsigned int *nom_v_pos)
 315 {
 316         /* TODO: Support multiple streams */
 317         const struct dc_stream_state *stream = streams[0];
 318         int i = 0;
 319         bool ret = false;
 320         struct crtc_position position;
 321
 322         for (i = 0; i < MAX_PIPES; i++) {
 323                 struct pipe_ctx *pipe =
 324                                 &dc->current_state->res_ctx.pipe_ctx[i];
 325
 326                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 327                         dc->hwss.get_position(&pipe, 1, &position);
 328
 329                         *v_pos = position.vertical_count;
 330                         *nom_v_pos = position.nominal_vcount;
 331                         ret = true;
 332                 }
 333         }
 334         return ret;
 335 }
 336
 337 /**
 338  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 339  * @dc: DC Object
 340  * @stream: The stream to configure CRC on.
 341  * @enable: Enable CRC if true, disable otherwise.
 342  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 343  *              once.
 344  *
 345  * By default, only CRC0 is configured, and the entire frame is used to
 346  * calculate the crc.
 347  */
 348 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 349                              bool enable, bool continuous)
 350 {
 351         int i;
 352         struct pipe_ctx *pipe;
 353         struct crc_params param;
 354         struct timing_generator *tg;
 355
 356         for (i = 0; i < MAX_PIPES; i++) {
 357                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 358                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 359                         break;
 360         }
 361         /* Stream not found */
 362         if (i == MAX_PIPES)
 363                 return false;
 364
 365         /* Always capture the full frame */
 366         param.windowa_x_start = 0;
 367         param.windowa_y_start = 0;
 368         param.windowa_x_end = pipe->stream->timing.h_addressable;
 369         param.windowa_y_end = pipe->stream->timing.v_addressable;
 370         param.windowb_x_start = 0;
 371         param.windowb_y_start = 0;
 372         param.windowb_x_end = pipe->stream->timing.h_addressable;
 373         param.windowb_y_end = pipe->stream->timing.v_addressable;
 374
 375         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 376         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 377
 378         /* Default to the union of both windows */
 379         param.selection = UNION_WINDOW_A_B;
 380         param.continuous_mode = continuous;
 381         param.enable = enable;
 382
 383         tg = pipe->stream_res.tg;
 384
 385         /* Only call if supported */
 386         if (tg->funcs->configure_crc)
 387                 return tg->funcs->configure_crc(tg, &param);
 388         DC_LOG_WARNING("CRC capture not supported.");
 389         return false;
 390 }
 391
 392 /**
 393  * dc_stream_get_crc() - Get CRC values for the given stream.
 394  * @dc: DC object
 395  * @stream: The DC stream state of the stream to get CRCs from.
 396  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 397  *
 398  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 399  * Return false if stream is not found, or if CRCs are not enabled.
 400  */
 401 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 402                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 403 {
 404         int i;
 405         struct pipe_ctx *pipe;
 406         struct timing_generator *tg;
 407
 408         for (i = 0; i < MAX_PIPES; i++) {
 409                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 410                 if (pipe->stream == stream)
 411                         break;
 412         }
 413         /* Stream not found */
 414         if (i == MAX_PIPES)
 415                 return false;
 416
 417         tg = pipe->stream_res.tg;
 418
 419         if (tg->funcs->get_crc)
 420                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 421         DC_LOG_WARNING("CRC capture not supported.");
 422         return false;
 423 }
 424
 425 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 426                 enum dc_dynamic_expansion option)
 427 {
 428         /* OPP FMT dyn expansion updates*/
 429         int i = 0;
 430         struct pipe_ctx *pipe_ctx;
 431
 432         for (i = 0; i < MAX_PIPES; i++) {
 433                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 434                                 == stream) {
 435                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 436                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 437                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 438                                         pipe_ctx->stream_res.opp,
 439                                         COLOR_SPACE_YCBCR601,
 440                                         stream->timing.display_color_depth,
 441                                         stream->signal);
 442                 }
 443         }
 444 }
 445
 446 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 447                 enum dc_dither_option option)
 448 {
 449         struct bit_depth_reduction_params params;
 450         struct dc_link *link = stream->link;
 451         struct pipe_ctx *pipes = NULL;
 452         int i;
 453
 454         for (i = 0; i < MAX_PIPES; i++) {
 455                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 456                                 stream) {
 457                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 458                         break;
 459                 }
 460         }
 461
 462         if (!pipes)
 463                 return;
 464         if (option > DITHER_OPTION_MAX)
 465                 return;
 466
 467         stream->dither_option = option;
 468
 469         memset(&params, 0, sizeof(params));
 470         resource_build_bit_depth_reduction_params(stream, &params);
 471         stream->bit_depth_params = params;
 472
 473         if (pipes->plane_res.xfm &&
 474             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 475                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 476                         pipes->plane_res.xfm,
 477                         pipes->plane_res.scl_data.lb_params.depth,
 478                         &stream->bit_depth_params);
 479         }
 480
 481         pipes->stream_res.opp->funcs->
 482                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 483 }
 484
 485 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 486 {
 487         int i = 0;
 488         bool ret = false;
 489         struct pipe_ctx *pipes;
 490
 491         for (i = 0; i < MAX_PIPES; i++) {
 492                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 493                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 494                         dc->hwss.program_gamut_remap(pipes);
 495                         ret = true;
 496                 }
 497         }
 498
 499         return ret;
 500 }
 501
 502 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 503 {
 504         int i = 0;
 505         bool ret = false;
 506         struct pipe_ctx *pipes;
 507
 508         for (i = 0; i < MAX_PIPES; i++) {
 509                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 510                                 == stream) {
 511
 512                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 513                         dc->hwss.program_output_csc(dc,
 514                                         pipes,
 515                                         stream->output_color_space,
 516                                         stream->csc_color_matrix.matrix,
 517                                         pipes->stream_res.opp->inst);
 518                         ret = true;
 519                 }
 520         }
 521
 522         return ret;
 523 }
 524
 525 void dc_stream_set_static_screen_params(struct dc *dc,
 526                 struct dc_stream_state **streams,
 527                 int num_streams,
 528                 const struct dc_static_screen_params *params)
 529 {
 530         int i = 0;
 531         int j = 0;
 532         struct pipe_ctx *pipes_affected[MAX_PIPES];
 533         int num_pipes_affected = 0;
 534
 535         for (i = 0; i < num_streams; i++) {
 536                 struct dc_stream_state *stream = streams[i];
 537
 538                 for (j = 0; j < MAX_PIPES; j++) {
 539                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 540                                         == stream) {
 541                                 pipes_affected[num_pipes_affected++] =
 542                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 543                         }
 544                 }
 545         }
 546
 547         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 548 }
 549
 550 static void dc_destruct(struct dc *dc)
 551 {
 552         if (dc->current_state) {
 553                 dc_release_state(dc->current_state);
 554                 dc->current_state = NULL;
 555         }
 556
 557         destroy_links(dc);
 558
 559         if (dc->clk_mgr) {
 560                 dc_destroy_clk_mgr(dc->clk_mgr);
 561                 dc->clk_mgr = NULL;
 562         }
 563
 564         dc_destroy_resource_pool(dc);
 565
 566         if (dc->ctx->gpio_service)
 567                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 568
 569         if (dc->ctx->created_bios)
 570                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 571
 572         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 573
 574         kfree(dc->ctx);
 575         dc->ctx = NULL;
 576
 577         kfree(dc->bw_vbios);
 578         dc->bw_vbios = NULL;
 579
 580         kfree(dc->bw_dceip);
 581         dc->bw_dceip = NULL;
 582
 583 #ifdef CONFIG_DRM_AMD_DC_DCN
 584         kfree(dc->dcn_soc);
 585         dc->dcn_soc = NULL;
 586
 587         kfree(dc->dcn_ip);
 588         dc->dcn_ip = NULL;
 589
 590 #endif
 591         kfree(dc->vm_helper);
 592         dc->vm_helper = NULL;
 593
 594 }
 595
 596 static bool dc_construct_ctx(struct dc *dc,
 597                 const struct dc_init_data *init_params)
 598 {
 599         struct dc_context *dc_ctx;
 600         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 601
 602         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 603         if (!dc_ctx)
 604                 return false;
 605
 606         dc_ctx->cgs_device = init_params->cgs_device;
 607         dc_ctx->driver_context = init_params->driver;
 608         dc_ctx->dc = dc;
 609         dc_ctx->asic_id = init_params->asic_id;
 610         dc_ctx->dc_sink_id_count = 0;
 611         dc_ctx->dc_stream_id_count = 0;
 612         dc_ctx->dce_environment = init_params->dce_environment;
 613
 614         /* Create logger */
 615
 616         dc_version = resource_parse_asic_id(init_params->asic_id);
 617         dc_ctx->dce_version = dc_version;
 618
 619         dc_ctx->perf_trace = dc_perf_trace_create();
 620         if (!dc_ctx->perf_trace) {
 621                 ASSERT_CRITICAL(false);
 622                 return false;
 623         }
 624
 625         dc->ctx = dc_ctx;
 626
 627         return true;
 628 }
 629
 630 static bool dc_construct(struct dc *dc,
 631                 const struct dc_init_data *init_params)
 632 {
 633         struct dc_context *dc_ctx;
 634         struct bw_calcs_dceip *dc_dceip;
 635         struct bw_calcs_vbios *dc_vbios;
 636 #ifdef CONFIG_DRM_AMD_DC_DCN
 637         struct dcn_soc_bounding_box *dcn_soc;
 638         struct dcn_ip_params *dcn_ip;
 639 #endif
 640
 641         dc->config = init_params->flags;
 642
 643         // Allocate memory for the vm_helper
 644         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 645         if (!dc->vm_helper) {
 646                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 647                 goto fail;
 648         }
 649
 650         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 651
 652         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 653         if (!dc_dceip) {
 654                 dm_error("%s: failed to create dceip\n", __func__);
 655                 goto fail;
 656         }
 657
 658         dc->bw_dceip = dc_dceip;
 659
 660         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 661         if (!dc_vbios) {
 662                 dm_error("%s: failed to create vbios\n", __func__);
 663                 goto fail;
 664         }
 665
 666         dc->bw_vbios = dc_vbios;
 667 #ifdef CONFIG_DRM_AMD_DC_DCN
 668         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 669         if (!dcn_soc) {
 670                 dm_error("%s: failed to create dcn_soc\n", __func__);
 671                 goto fail;
 672         }
 673
 674         dc->dcn_soc = dcn_soc;
 675
 676         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 677         if (!dcn_ip) {
 678                 dm_error("%s: failed to create dcn_ip\n", __func__);
 679                 goto fail;
 680         }
 681
 682         dc->dcn_ip = dcn_ip;
 683         dc->soc_bounding_box = init_params->soc_bounding_box;
 684 #endif
 685
 686         if (!dc_construct_ctx(dc, init_params)) {
 687                 dm_error("%s: failed to create ctx\n", __func__);
 688                 goto fail;
 689         }
 690
 691         dc_ctx = dc->ctx;
 692
 693         /* Resource should construct all asic specific resources.
 694          * This should be the only place where we need to parse the asic id
 695          */
 696         if (init_params->vbios_override)
 697                 dc_ctx->dc_bios = init_params->vbios_override;
 698         else {
 699                 /* Create BIOS parser */
 700                 struct bp_init_data bp_init_data;
 701
 702                 bp_init_data.ctx = dc_ctx;
 703                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 704
 705                 dc_ctx->dc_bios = dal_bios_parser_create(
 706                                 &bp_init_data, dc_ctx->dce_version);
 707
 708                 if (!dc_ctx->dc_bios) {
 709                         ASSERT_CRITICAL(false);
 710                         goto fail;
 711                 }
 712
 713                 dc_ctx->created_bios = true;
 714         }
 715
 716         dc->vendor_signature = init_params->vendor_signature;
 717
 718         /* Create GPIO service */
 719         dc_ctx->gpio_service = dal_gpio_service_create(
 720                         dc_ctx->dce_version,
 721                         dc_ctx->dce_environment,
 722                         dc_ctx);
 723
 724         if (!dc_ctx->gpio_service) {
 725                 ASSERT_CRITICAL(false);
 726                 goto fail;
 727         }
 728
 729         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 730         if (!dc->res_pool)
 731                 goto fail;
 732
 733         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 734         if (!dc->clk_mgr)
 735                 goto fail;
 736 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
 737         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 738 #endif
 739
 740         dc->debug.force_ignore_link_settings = init_params->force_ignore_link_settings;
 741
 742         if (dc->res_pool->funcs->update_bw_bounding_box)
 743                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 744
 745         /* Creation of current_state must occur after dc->dml
 746          * is initialized in dc_create_resource_pool because
 747          * on creation it copies the contents of dc->dml
 748          */
 749
 750         dc->current_state = dc_create_state(dc);
 751
 752         if (!dc->current_state) {
 753                 dm_error("%s: failed to create validate ctx\n", __func__);
 754                 goto fail;
 755         }
 756
 757         dc_resource_state_construct(dc, dc->current_state);
 758
 759         if (!create_links(dc, init_params->num_virtual_links))
 760                 goto fail;
 761
 762         return true;
 763
 764 fail:
 765         return false;
 766 }
 767
 768 static void disable_all_writeback_pipes_for_stream(
 769                 const struct dc *dc,
 770                 struct dc_stream_state *stream,
 771                 struct dc_state *context)
 772 {
 773         int i;
 774
 775         for (i = 0; i < stream->num_wb_info; i++)
 776                 stream->writeback_info[i].wb_enabled = false;
 777 }
 778
 779 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 780 {
 781         int i = 0;
 782
 783         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 784         if (dc->hwss.interdependent_update_lock)
 785                 dc->hwss.interdependent_update_lock(dc, context, lock);
 786         else {
 787                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 788                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 789                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 790
 791                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 792                         if (stream == pipe_ctx->stream) {
 793                                 if (!pipe_ctx->top_pipe &&
 794                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 795                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 796                         }
 797                 }
 798         }
 799 }
 800
 801 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 802 {
 803         int i, j;
 804         struct dc_state *dangling_context = dc_create_state(dc);
 805         struct dc_state *current_ctx;
 806
 807         if (dangling_context == NULL)
 808                 return;
 809
 810         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 811
 812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 813                 struct dc_stream_state *old_stream =
 814                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 815                 bool should_disable = true;
 816
 817                 for (j = 0; j < context->stream_count; j++) {
 818                         if (old_stream == context->streams[j]) {
 819                                 should_disable = false;
 820                                 break;
 821                         }
 822                 }
 823                 if (should_disable && old_stream) {
 824                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 825                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 826
 827                         if (dc->hwss.apply_ctx_for_surface) {
 828                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 829                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 830                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 831                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 832                         }
 833                         if (dc->hwss.program_front_end_for_ctx) {
 834                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 835                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 836                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 837                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 838                         }
 839                 }
 840         }
 841
 842         current_ctx = dc->current_state;
 843         dc->current_state = dangling_context;
 844         dc_release_state(current_ctx);
 845 }
 846
 847 static void disable_vbios_mode_if_required(
 848                 struct dc *dc,
 849                 struct dc_state *context)
 850 {
 851         unsigned int i, j;
 852
 853         /* check if timing_changed, disable stream*/
 854         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 855                 struct dc_stream_state *stream = NULL;
 856                 struct dc_link *link = NULL;
 857                 struct pipe_ctx *pipe = NULL;
 858
 859                 pipe = &context->res_ctx.pipe_ctx[i];
 860                 stream = pipe->stream;
 861                 if (stream == NULL)
 862                         continue;
 863
 864                 if (stream->link->local_sink &&
 865                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 866                         link = stream->link;
 867                 }
 868
 869                 if (link != NULL) {
 870                         unsigned int enc_inst, tg_inst = 0;
 871                         unsigned int pix_clk_100hz;
 872
 873                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 874                         if (enc_inst != ENGINE_ID_UNKNOWN) {
 875                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 876                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
 877                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
 878                                                         dc->res_pool->stream_enc[j]);
 879                                                 break;
 880                                         }
 881                                 }
 882
 883                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
 884                                         dc->res_pool->dp_clock_source,
 885                                         tg_inst, &pix_clk_100hz);
 886
 887                                 if (link->link_status.link_active) {
 888                                         uint32_t requested_pix_clk_100hz =
 889                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
 890
 891                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
 892                                                 core_link_disable_stream(pipe);
 893                                                 pipe->stream->dpms_off = false;
 894                                         }
 895                                 }
 896                         }
 897                 }
 898         }
 899 }
 900
 901 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 902 {
 903         int i;
 904         PERF_TRACE();
 905         for (i = 0; i < MAX_PIPES; i++) {
 906                 int count = 0;
 907                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 908
 909                 if (!pipe->plane_state)
 910                         continue;
 911
 912                 /* Timeout 100 ms */
 913                 while (count < 100000) {
 914                         /* Must set to false to start with, due to OR in update function */
 915                         pipe->plane_state->status.is_flip_pending = false;
 916                         dc->hwss.update_pending_status(pipe);
 917                         if (!pipe->plane_state->status.is_flip_pending)
 918                                 break;
 919                         udelay(1);
 920                         count++;
 921                 }
 922                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 923         }
 924         PERF_TRACE();
 925 }
 926
 927 /*******************************************************************************
 928  * Public functions
 929  ******************************************************************************/
 930
 931 struct dc *dc_create(const struct dc_init_data *init_params)
 932 {
 933         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 934         unsigned int full_pipe_count;
 935
 936         if (NULL == dc)
 937                 goto alloc_fail;
 938
 939         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 940                 if (false == dc_construct_ctx(dc, init_params)) {
 941                         dc_destruct(dc);
 942                         goto construct_fail;
 943                 }
 944         } else {
 945                 if (false == dc_construct(dc, init_params)) {
 946                         dc_destruct(dc);
 947                         goto construct_fail;
 948                 }
 949
 950                 full_pipe_count = dc->res_pool->pipe_count;
 951                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 952                         full_pipe_count--;
 953                 dc->caps.max_streams = min(
 954                                 full_pipe_count,
 955                                 dc->res_pool->stream_enc_count);
 956
 957                 dc->optimize_seamless_boot_streams = 0;
 958                 dc->caps.max_links = dc->link_count;
 959                 dc->caps.max_audios = dc->res_pool->audio_count;
 960                 dc->caps.linear_pitch_alignment = 64;
 961
 962                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 963
 964                 if (dc->res_pool->dmcu != NULL)
 965                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 966         }
 967
 968         /* Populate versioning information */
 969         dc->versions.dc_ver = DC_VER;
 970
 971         dc->build_id = DC_BUILD_ID;
 972
 973         DC_LOG_DC("Display Core initialized\n");
 974
 975
 976
 977         return dc;
 978
 979 construct_fail:
 980         kfree(dc);
 981
 982 alloc_fail:
 983         return NULL;
 984 }
 985
 986 void dc_hardware_init(struct dc *dc)
 987 {
 988         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
 989                 dc->hwss.init_hw(dc);
 990 }
 991
 992 void dc_init_callbacks(struct dc *dc,
 993                 const struct dc_callback_init *init_params)
 994 {
 995 #ifdef CONFIG_DRM_AMD_DC_HDCP
 996         dc->ctx->cp_psp = init_params->cp_psp;
 997 #endif
 998 }
 999
1000 void dc_deinit_callbacks(struct dc *dc)
1001 {
1002 #ifdef CONFIG_DRM_AMD_DC_HDCP
1003         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1004 #endif
1005 }
1006
1007 void dc_destroy(struct dc **dc)
1008 {
1009         dc_destruct(*dc);
1010         kfree(*dc);
1011         *dc = NULL;
1012 }
1013
1014 static void enable_timing_multisync(
1015                 struct dc *dc,
1016                 struct dc_state *ctx)
1017 {
1018         int i = 0, multisync_count = 0;
1019         int pipe_count = dc->res_pool->pipe_count;
1020         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1021
1022         for (i = 0; i < pipe_count; i++) {
1023                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1024                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1025                         continue;
1026                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1027                         continue;
1028                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1029                 multisync_count++;
1030         }
1031
1032         if (multisync_count > 0) {
1033                 dc->hwss.enable_per_frame_crtc_position_reset(
1034                         dc, multisync_count, multisync_pipes);
1035         }
1036 }
1037
1038 static void program_timing_sync(
1039                 struct dc *dc,
1040                 struct dc_state *ctx)
1041 {
1042         int i, j, k;
1043         int group_index = 0;
1044         int num_group = 0;
1045         int pipe_count = dc->res_pool->pipe_count;
1046         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1047
1048         for (i = 0; i < pipe_count; i++) {
1049                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1050                         continue;
1051
1052                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1053         }
1054
1055         for (i = 0; i < pipe_count; i++) {
1056                 int group_size = 1;
1057                 struct pipe_ctx *pipe_set[MAX_PIPES];
1058
1059                 if (!unsynced_pipes[i])
1060                         continue;
1061
1062                 pipe_set[0] = unsynced_pipes[i];
1063                 unsynced_pipes[i] = NULL;
1064
1065                 /* Add tg to the set, search rest of the tg's for ones with
1066                  * same timing, add all tgs with same timing to the group
1067                  */
1068                 for (j = i + 1; j < pipe_count; j++) {
1069                         if (!unsynced_pipes[j])
1070                                 continue;
1071
1072                         if (resource_are_streams_timing_synchronizable(
1073                                         unsynced_pipes[j]->stream,
1074                                         pipe_set[0]->stream)) {
1075                                 pipe_set[group_size] = unsynced_pipes[j];
1076                                 unsynced_pipes[j] = NULL;
1077                                 group_size++;
1078                         }
1079                 }
1080
1081                 /* set first unblanked pipe as master */
1082                 for (j = 0; j < group_size; j++) {
1083                         bool is_blanked;
1084
1085                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1086                                 is_blanked =
1087                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1088                         else
1089                                 is_blanked =
1090                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1091                         if (!is_blanked) {
1092                                 if (j == 0)
1093                                         break;
1094
1095                                 swap(pipe_set[0], pipe_set[j]);
1096                                 break;
1097                         }
1098                 }
1099
1100
1101                 for (k = 0; k < group_size; k++) {
1102                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1103
1104                         status->timing_sync_info.group_id = num_group;
1105                         status->timing_sync_info.group_size = group_size;
1106                         if (k == 0)
1107                                 status->timing_sync_info.master = true;
1108                         else
1109                                 status->timing_sync_info.master = false;
1110
1111                 }
1112                 /* remove any other unblanked pipes as they have already been synced */
1113                 for (j = j + 1; j < group_size; j++) {
1114                         bool is_blanked;
1115
1116                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1117                                 is_blanked =
1118                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1119                         else
1120                                 is_blanked =
1121                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1122                         if (!is_blanked) {
1123                                 group_size--;
1124                                 pipe_set[j] = pipe_set[group_size];
1125                                 j--;
1126                         }
1127                 }
1128
1129                 if (group_size > 1) {
1130                         dc->hwss.enable_timing_synchronization(
1131                                 dc, group_index, group_size, pipe_set);
1132                         group_index++;
1133                 }
1134                 num_group++;
1135         }
1136 }
1137
1138 static bool context_changed(
1139                 struct dc *dc,
1140                 struct dc_state *context)
1141 {
1142         uint8_t i;
1143
1144         if (context->stream_count != dc->current_state->stream_count)
1145                 return true;
1146
1147         for (i = 0; i < dc->current_state->stream_count; i++) {
1148                 if (dc->current_state->streams[i] != context->streams[i])
1149                         return true;
1150         }
1151
1152         return false;
1153 }
1154
1155 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1156                                 const struct dc_sink *sink,
1157                                 struct dc_crtc_timing *crtc_timing)
1158 {
1159         struct timing_generator *tg;
1160         struct stream_encoder *se = NULL;
1161
1162         struct dc_crtc_timing hw_crtc_timing = {0};
1163
1164         struct dc_link *link = sink->link;
1165         unsigned int i, enc_inst, tg_inst = 0;
1166
1167         // Seamless port only support single DP and EDP so far
1168         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1169                 sink->sink_signal != SIGNAL_TYPE_EDP)
1170                 return false;
1171
1172         /* Check for enabled DIG to identify enabled display */
1173         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1174                 return false;
1175
1176         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1177
1178         if (enc_inst == ENGINE_ID_UNKNOWN)
1179                 return false;
1180
1181         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1182                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1183
1184                         se = dc->res_pool->stream_enc[i];
1185
1186                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1187                                 dc->res_pool->stream_enc[i]);
1188                         break;
1189                 }
1190         }
1191
1192         // tg_inst not found
1193         if (i == dc->res_pool->stream_enc_count)
1194                 return false;
1195
1196         if (tg_inst >= dc->res_pool->timing_generator_count)
1197                 return false;
1198
1199         tg = dc->res_pool->timing_generators[tg_inst];
1200
1201         if (!tg->funcs->get_hw_timing)
1202                 return false;
1203
1204         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1205                 return false;
1206
1207         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1208                 return false;
1209
1210         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1211                 return false;
1212
1213         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1214                 return false;
1215
1216         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1217                 return false;
1218
1219         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1220                 return false;
1221
1222         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1223                 return false;
1224
1225         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1226                 return false;
1227
1228         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1229                 return false;
1230
1231         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1232                 return false;
1233
1234         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1235                 return false;
1236
1237         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1238                 return false;
1239
1240         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1241                 return false;
1242
1243         if (dc_is_dp_signal(link->connector_signal)) {
1244                 unsigned int pix_clk_100hz;
1245
1246                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1247                         dc->res_pool->dp_clock_source,
1248                         tg_inst, &pix_clk_100hz);
1249
1250                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1251                         return false;
1252
1253                 if (!se->funcs->dp_get_pixel_format)
1254                         return false;
1255
1256                 if (!se->funcs->dp_get_pixel_format(
1257                         se,
1258                         &hw_crtc_timing.pixel_encoding,
1259                         &hw_crtc_timing.display_color_depth))
1260                         return false;
1261
1262                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1263                         return false;
1264
1265                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1266                         return false;
1267         }
1268
1269         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1270                 return false;
1271         }
1272
1273         return true;
1274 }
1275
1276 void dc_enable_stereo(
1277         struct dc *dc,
1278         struct dc_state *context,
1279         struct dc_stream_state *streams[],
1280         uint8_t stream_count)
1281 {
1282         int i, j;
1283         struct pipe_ctx *pipe;
1284
1285         for (i = 0; i < MAX_PIPES; i++) {
1286                 if (context != NULL)
1287                         pipe = &context->res_ctx.pipe_ctx[i];
1288                 else
1289                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1290                 for (j = 0 ; pipe && j < stream_count; j++)  {
1291                         if (streams[j] && streams[j] == pipe->stream &&
1292                                 dc->hwss.setup_stereo)
1293                                 dc->hwss.setup_stereo(pipe, dc);
1294                 }
1295         }
1296 }
1297
1298 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1299 {
1300         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1301                 enable_timing_multisync(dc, context);
1302                 program_timing_sync(dc, context);
1303         }
1304 }
1305
1306 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1307 {
1308         int i;
1309         unsigned int stream_mask = 0;
1310
1311         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1312                 if (context->res_ctx.pipe_ctx[i].stream)
1313                         stream_mask |= 1 << i;
1314         }
1315
1316         return stream_mask;
1317 }
1318
1319 /*
1320  * Applies given context to HW and copy it into current context.
1321  * It's up to the user to release the src context afterwards.
1322  */
1323 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1324 {
1325         struct dc_bios *dcb = dc->ctx->dc_bios;
1326         enum dc_status result = DC_ERROR_UNEXPECTED;
1327         struct pipe_ctx *pipe;
1328         int i, k, l;
1329         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1330
1331 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1332         dc_allow_idle_optimizations(dc, false);
1333 #endif
1334
1335         for (i = 0; i < context->stream_count; i++)
1336                 dc_streams[i] =  context->streams[i];
1337
1338         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1339                 disable_vbios_mode_if_required(dc, context);
1340                 dc->hwss.enable_accelerated_mode(dc, context);
1341         }
1342
1343         for (i = 0; i < context->stream_count; i++)
1344                 if (context->streams[i]->apply_seamless_boot_optimization)
1345                         dc->optimize_seamless_boot_streams++;
1346
1347         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1348                 context->stream_count == 0)
1349                 dc->hwss.prepare_bandwidth(dc, context);
1350
1351         disable_dangling_plane(dc, context);
1352         /* re-program planes for existing stream, in case we need to
1353          * free up plane resource for later use
1354          */
1355         if (dc->hwss.apply_ctx_for_surface) {
1356                 for (i = 0; i < context->stream_count; i++) {
1357                         if (context->streams[i]->mode_changed)
1358                                 continue;
1359                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1360                         dc->hwss.apply_ctx_for_surface(
1361                                 dc, context->streams[i],
1362                                 context->stream_status[i].plane_count,
1363                                 context); /* use new pipe config in new context */
1364                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1365                         dc->hwss.post_unlock_program_front_end(dc, context);
1366                 }
1367         }
1368
1369         /* Program hardware */
1370         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1371                 pipe = &context->res_ctx.pipe_ctx[i];
1372                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1373         }
1374
1375         result = dc->hwss.apply_ctx_to_hw(dc, context);
1376
1377         if (result != DC_OK)
1378                 return result;
1379
1380         dc_trigger_sync(dc, context);
1381
1382         /* Program all planes within new context*/
1383         if (dc->hwss.program_front_end_for_ctx) {
1384                 dc->hwss.interdependent_update_lock(dc, context, true);
1385                 dc->hwss.program_front_end_for_ctx(dc, context);
1386                 dc->hwss.interdependent_update_lock(dc, context, false);
1387                 dc->hwss.post_unlock_program_front_end(dc, context);
1388         }
1389         for (i = 0; i < context->stream_count; i++) {
1390                 const struct dc_link *link = context->streams[i]->link;
1391
1392                 if (!context->streams[i]->mode_changed)
1393                         continue;
1394
1395                 if (dc->hwss.apply_ctx_for_surface) {
1396                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1397                         dc->hwss.apply_ctx_for_surface(
1398                                         dc, context->streams[i],
1399                                         context->stream_status[i].plane_count,
1400                                         context);
1401                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1402                         dc->hwss.post_unlock_program_front_end(dc, context);
1403                 }
1404
1405                 /*
1406                  * enable stereo
1407                  * TODO rework dc_enable_stereo call to work with validation sets?
1408                  */
1409                 for (k = 0; k < MAX_PIPES; k++) {
1410                         pipe = &context->res_ctx.pipe_ctx[k];
1411
1412                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1413                                 if (context->streams[l] &&
1414                                         context->streams[l] == pipe->stream &&
1415                                         dc->hwss.setup_stereo)
1416                                         dc->hwss.setup_stereo(pipe, dc);
1417                         }
1418                 }
1419
1420                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1421                                 context->streams[i]->timing.h_addressable,
1422                                 context->streams[i]->timing.v_addressable,
1423                                 context->streams[i]->timing.h_total,
1424                                 context->streams[i]->timing.v_total,
1425                                 context->streams[i]->timing.pix_clk_100hz / 10);
1426         }
1427
1428         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1429
1430         if (context->stream_count > dc->optimize_seamless_boot_streams ||
1431                 context->stream_count == 0) {
1432                 /* Must wait for no flips to be pending before doing optimize bw */
1433                 wait_for_no_pipes_pending(dc, context);
1434                 /* pplib is notified if disp_num changed */
1435                 dc->hwss.optimize_bandwidth(dc, context);
1436         }
1437
1438         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1439                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1440         else
1441                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1442
1443         context->stream_mask = get_stream_mask(dc, context);
1444
1445         if (context->stream_mask != dc->current_state->stream_mask)
1446                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1447
1448         for (i = 0; i < context->stream_count; i++)
1449                 context->streams[i]->mode_changed = false;
1450
1451         dc_release_state(dc->current_state);
1452
1453         dc->current_state = context;
1454
1455         dc_retain_state(dc->current_state);
1456
1457         return result;
1458 }
1459
1460 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1461 {
1462         enum dc_status result = DC_ERROR_UNEXPECTED;
1463         int i;
1464
1465         if (false == context_changed(dc, context))
1466                 return DC_OK;
1467
1468         DC_LOG_DC("%s: %d streams\n",
1469                                 __func__, context->stream_count);
1470
1471         for (i = 0; i < context->stream_count; i++) {
1472                 struct dc_stream_state *stream = context->streams[i];
1473
1474                 dc_stream_log(dc, stream);
1475         }
1476
1477         result = dc_commit_state_no_check(dc, context);
1478
1479         return (result == DC_OK);
1480 }
1481
1482 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1483 bool dc_acquire_release_mpc_3dlut(
1484                 struct dc *dc, bool acquire,
1485                 struct dc_stream_state *stream,
1486                 struct dc_3dlut **lut,
1487                 struct dc_transfer_func **shaper)
1488 {
1489         int pipe_idx;
1490         bool ret = false;
1491         bool found_pipe_idx = false;
1492         const struct resource_pool *pool = dc->res_pool;
1493         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1494         int mpcc_id = 0;
1495
1496         if (pool && res_ctx) {
1497                 if (acquire) {
1498                         /*find pipe idx for the given stream*/
1499                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1500                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1501                                         found_pipe_idx = true;
1502                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1503                                         break;
1504                                 }
1505                         }
1506                 } else
1507                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1508
1509                 if (found_pipe_idx) {
1510                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1511                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1512                         else if (acquire == false && pool->funcs->release_post_bldn_3dlut)
1513                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1514                 }
1515         }
1516         return ret;
1517 }
1518 #endif
1519 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1520 {
1521         int i;
1522         struct pipe_ctx *pipe;
1523
1524         for (i = 0; i < MAX_PIPES; i++) {
1525                 pipe = &context->res_ctx.pipe_ctx[i];
1526
1527                 if (!pipe->plane_state)
1528                         continue;
1529
1530                 /* Must set to false to start with, due to OR in update function */
1531                 pipe->plane_state->status.is_flip_pending = false;
1532                 dc->hwss.update_pending_status(pipe);
1533                 if (pipe->plane_state->status.is_flip_pending)
1534                         return true;
1535         }
1536         return false;
1537 }
1538
1539 void dc_post_update_surfaces_to_stream(struct dc *dc)
1540 {
1541         int i;
1542         struct dc_state *context = dc->current_state;
1543
1544         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1545                 return;
1546
1547         post_surface_trace(dc);
1548
1549         if (is_flip_pending_in_pipes(dc, context))
1550                 return;
1551
1552         for (i = 0; i < dc->res_pool->pipe_count; i++)
1553                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1554                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1555                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1556                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1557                 }
1558
1559         dc->hwss.optimize_bandwidth(dc, context);
1560
1561         dc->optimized_required = false;
1562         dc->wm_optimized_required = false;
1563 }
1564
1565 static void init_state(struct dc *dc, struct dc_state *context)
1566 {
1567         /* Each context must have their own instance of VBA and in order to
1568          * initialize and obtain IP and SOC the base DML instance from DC is
1569          * initially copied into every context
1570          */
1571 #ifdef CONFIG_DRM_AMD_DC_DCN
1572         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1573 #endif
1574 }
1575
1576 struct dc_state *dc_create_state(struct dc *dc)
1577 {
1578         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1579                                            GFP_KERNEL);
1580
1581         if (!context)
1582                 return NULL;
1583
1584         init_state(dc, context);
1585
1586         kref_init(&context->refcount);
1587
1588         return context;
1589 }
1590
1591 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1592 {
1593         int i, j;
1594         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1595
1596         if (!new_ctx)
1597                 return NULL;
1598         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1599
1600         for (i = 0; i < MAX_PIPES; i++) {
1601                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1602
1603                         if (cur_pipe->top_pipe)
1604                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1605
1606                         if (cur_pipe->bottom_pipe)
1607                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1608
1609                         if (cur_pipe->prev_odm_pipe)
1610                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1611
1612                         if (cur_pipe->next_odm_pipe)
1613                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1614
1615         }
1616
1617         for (i = 0; i < new_ctx->stream_count; i++) {
1618                         dc_stream_retain(new_ctx->streams[i]);
1619                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1620                                 dc_plane_state_retain(
1621                                         new_ctx->stream_status[i].plane_states[j]);
1622         }
1623
1624         kref_init(&new_ctx->refcount);
1625
1626         return new_ctx;
1627 }
1628
1629 void dc_retain_state(struct dc_state *context)
1630 {
1631         kref_get(&context->refcount);
1632 }
1633
1634 static void dc_state_free(struct kref *kref)
1635 {
1636         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1637         dc_resource_state_destruct(context);
1638         kvfree(context);
1639 }
1640
1641 void dc_release_state(struct dc_state *context)
1642 {
1643         kref_put(&context->refcount, dc_state_free);
1644 }
1645
1646 bool dc_set_generic_gpio_for_stereo(bool enable,
1647                 struct gpio_service *gpio_service)
1648 {
1649         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1650         struct gpio_pin_info pin_info;
1651         struct gpio *generic;
1652         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1653                            GFP_KERNEL);
1654
1655         if (!config)
1656                 return false;
1657         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1658
1659         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1660                 kfree(config);
1661                 return false;
1662         } else {
1663                 generic = dal_gpio_service_create_generic_mux(
1664                         gpio_service,
1665                         pin_info.offset,
1666                         pin_info.mask);
1667         }
1668
1669         if (!generic) {
1670                 kfree(config);
1671                 return false;
1672         }
1673
1674         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1675
1676         config->enable_output_from_mux = enable;
1677         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1678
1679         if (gpio_result == GPIO_RESULT_OK)
1680                 gpio_result = dal_mux_setup_config(generic, config);
1681
1682         if (gpio_result == GPIO_RESULT_OK) {
1683                 dal_gpio_close(generic);
1684                 dal_gpio_destroy_generic_mux(&generic);
1685                 kfree(config);
1686                 return true;
1687         } else {
1688                 dal_gpio_close(generic);
1689                 dal_gpio_destroy_generic_mux(&generic);
1690                 kfree(config);
1691                 return false;
1692         }
1693 }
1694
1695 static bool is_surface_in_context(
1696                 const struct dc_state *context,
1697                 const struct dc_plane_state *plane_state)
1698 {
1699         int j;
1700
1701         for (j = 0; j < MAX_PIPES; j++) {
1702                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1703
1704                 if (plane_state == pipe_ctx->plane_state) {
1705                         return true;
1706                 }
1707         }
1708
1709         return false;
1710 }
1711
1712 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1713 {
1714         union surface_update_flags *update_flags = &u->surface->update_flags;
1715         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1716
1717         if (!u->plane_info)
1718                 return UPDATE_TYPE_FAST;
1719
1720         if (u->plane_info->color_space != u->surface->color_space) {
1721                 update_flags->bits.color_space_change = 1;
1722                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1723         }
1724
1725         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1726                 update_flags->bits.horizontal_mirror_change = 1;
1727                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1728         }
1729
1730         if (u->plane_info->rotation != u->surface->rotation) {
1731                 update_flags->bits.rotation_change = 1;
1732                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1733         }
1734
1735         if (u->plane_info->format != u->surface->format) {
1736                 update_flags->bits.pixel_format_change = 1;
1737                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1738         }
1739
1740         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1741                 update_flags->bits.stereo_format_change = 1;
1742                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1743         }
1744
1745         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1746                 update_flags->bits.per_pixel_alpha_change = 1;
1747                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1748         }
1749
1750         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1751                 update_flags->bits.global_alpha_change = 1;
1752                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1753         }
1754
1755         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1756                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1757                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1758                 update_flags->bits.dcc_change = 1;
1759                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1760         }
1761
1762         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1763                         resource_pixel_format_to_bpp(u->surface->format)) {
1764                 /* different bytes per element will require full bandwidth
1765                  * and DML calculation
1766                  */
1767                 update_flags->bits.bpp_change = 1;
1768                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1769         }
1770
1771         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1772                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1773                 update_flags->bits.plane_size_change = 1;
1774                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1775         }
1776
1777
1778         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1779                         sizeof(union dc_tiling_info)) != 0) {
1780                 update_flags->bits.swizzle_change = 1;
1781                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1782
1783                 /* todo: below are HW dependent, we should add a hook to
1784                  * DCE/N resource and validated there.
1785                  */
1786                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1787                         /* swizzled mode requires RQ to be setup properly,
1788                          * thus need to run DML to calculate RQ settings
1789                          */
1790                         update_flags->bits.bandwidth_change = 1;
1791                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1792                 }
1793         }
1794
1795         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1796         return update_type;
1797 }
1798
1799 static enum surface_update_type get_scaling_info_update_type(
1800                 const struct dc_surface_update *u)
1801 {
1802         union surface_update_flags *update_flags = &u->surface->update_flags;
1803
1804         if (!u->scaling_info)
1805                 return UPDATE_TYPE_FAST;
1806
1807         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1808                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1809                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1810                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1811                         || u->scaling_info->scaling_quality.integer_scaling !=
1812                                 u->surface->scaling_quality.integer_scaling
1813                         ) {
1814                 update_flags->bits.scaling_change = 1;
1815
1816                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1817                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1818                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1819                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1820                         /* Making dst rect smaller requires a bandwidth change */
1821                         update_flags->bits.bandwidth_change = 1;
1822         }
1823
1824         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1825                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1826
1827                 update_flags->bits.scaling_change = 1;
1828                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1829                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1830                         /* Making src rect bigger requires a bandwidth change */
1831                         update_flags->bits.clock_change = 1;
1832         }
1833
1834         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1835                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1836                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1837                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1838                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1839                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1840                 update_flags->bits.position_change = 1;
1841
1842         if (update_flags->bits.clock_change
1843                         || update_flags->bits.bandwidth_change
1844                         || update_flags->bits.scaling_change)
1845                 return UPDATE_TYPE_FULL;
1846
1847         if (update_flags->bits.position_change)
1848                 return UPDATE_TYPE_MED;
1849
1850         return UPDATE_TYPE_FAST;
1851 }
1852
1853 static enum surface_update_type det_surface_update(const struct dc *dc,
1854                 const struct dc_surface_update *u)
1855 {
1856         const struct dc_state *context = dc->current_state;
1857         enum surface_update_type type;
1858         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1859         union surface_update_flags *update_flags = &u->surface->update_flags;
1860
1861         if (u->flip_addr)
1862                 update_flags->bits.addr_update = 1;
1863
1864         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1865                 update_flags->raw = 0xFFFFFFFF;
1866                 return UPDATE_TYPE_FULL;
1867         }
1868
1869         update_flags->raw = 0; // Reset all flags
1870
1871         type = get_plane_info_update_type(u);
1872         elevate_update_type(&overall_type, type);
1873
1874         type = get_scaling_info_update_type(u);
1875         elevate_update_type(&overall_type, type);
1876
1877         if (u->flip_addr)
1878                 update_flags->bits.addr_update = 1;
1879
1880         if (u->in_transfer_func)
1881                 update_flags->bits.in_transfer_func_change = 1;
1882
1883         if (u->input_csc_color_matrix)
1884                 update_flags->bits.input_csc_change = 1;
1885
1886         if (u->coeff_reduction_factor)
1887                 update_flags->bits.coeff_reduction_change = 1;
1888
1889         if (u->gamut_remap_matrix)
1890                 update_flags->bits.gamut_remap_change = 1;
1891
1892         if (u->gamma) {
1893                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1894
1895                 if (u->plane_info)
1896                         format = u->plane_info->format;
1897                 else if (u->surface)
1898                         format = u->surface->format;
1899
1900                 if (dce_use_lut(format))
1901                         update_flags->bits.gamma_change = 1;
1902         }
1903
1904         if (u->hdr_mult.value)
1905                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1906                         update_flags->bits.hdr_mult = 1;
1907                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1908                 }
1909
1910         if (update_flags->bits.in_transfer_func_change) {
1911                 type = UPDATE_TYPE_MED;
1912                 elevate_update_type(&overall_type, type);
1913         }
1914
1915         if (update_flags->bits.input_csc_change
1916                         || update_flags->bits.coeff_reduction_change
1917                         || update_flags->bits.gamma_change
1918                         || update_flags->bits.gamut_remap_change) {
1919                 type = UPDATE_TYPE_FULL;
1920                 elevate_update_type(&overall_type, type);
1921         }
1922
1923         return overall_type;
1924 }
1925
1926 static enum surface_update_type check_update_surfaces_for_stream(
1927                 struct dc *dc,
1928                 struct dc_surface_update *updates,
1929                 int surface_count,
1930                 struct dc_stream_update *stream_update,
1931                 const struct dc_stream_status *stream_status)
1932 {
1933         int i;
1934         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1935
1936 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1937         if (dc->idle_optimizations_allowed)
1938                 overall_type = UPDATE_TYPE_FULL;
1939
1940 #endif
1941         if (stream_status == NULL || stream_status->plane_count != surface_count)
1942                 overall_type = UPDATE_TYPE_FULL;
1943
1944         /* some stream updates require passive update */
1945         if (stream_update) {
1946                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1947
1948                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1949                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1950                         stream_update->integer_scaling_update)
1951                         su_flags->bits.scaling = 1;
1952
1953                 if (stream_update->out_transfer_func)
1954                         su_flags->bits.out_tf = 1;
1955
1956                 if (stream_update->abm_level)
1957                         su_flags->bits.abm_level = 1;
1958
1959                 if (stream_update->dpms_off)
1960                         su_flags->bits.dpms_off = 1;
1961
1962                 if (stream_update->gamut_remap)
1963                         su_flags->bits.gamut_remap = 1;
1964
1965                 if (stream_update->wb_update)
1966                         su_flags->bits.wb_update = 1;
1967
1968                 if (stream_update->dsc_config)
1969                         su_flags->bits.dsc_changed = 1;
1970
1971                 if (su_flags->raw != 0)
1972                         overall_type = UPDATE_TYPE_FULL;
1973
1974                 if (stream_update->output_csc_transform || stream_update->output_color_space)
1975                         su_flags->bits.out_csc = 1;
1976         }
1977
1978         for (i = 0 ; i < surface_count; i++) {
1979                 enum surface_update_type type =
1980                                 det_surface_update(dc, &updates[i]);
1981
1982                 elevate_update_type(&overall_type, type);
1983         }
1984
1985         return overall_type;
1986 }
1987
1988 /**
1989  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1990  *
1991  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1992  */
1993 enum surface_update_type dc_check_update_surfaces_for_stream(
1994                 struct dc *dc,
1995                 struct dc_surface_update *updates,
1996                 int surface_count,
1997                 struct dc_stream_update *stream_update,
1998                 const struct dc_stream_status *stream_status)
1999 {
2000         int i;
2001         enum surface_update_type type;
2002
2003         if (stream_update)
2004                 stream_update->stream->update_flags.raw = 0;
2005         for (i = 0; i < surface_count; i++)
2006                 updates[i].surface->update_flags.raw = 0;
2007
2008         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2009         if (type == UPDATE_TYPE_FULL) {
2010                 if (stream_update) {
2011                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2012                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2013                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2014                 }
2015                 for (i = 0; i < surface_count; i++)
2016                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2017         }
2018
2019         if (type == UPDATE_TYPE_FAST) {
2020                 // If there's an available clock comparator, we use that.
2021                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2022                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2023                                 dc->optimized_required = true;
2024                 // Else we fallback to mem compare.
2025                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2026                         dc->optimized_required = true;
2027                 }
2028
2029                 dc->optimized_required |= dc->wm_optimized_required;
2030         }
2031
2032         return type;
2033 }
2034
2035 static struct dc_stream_status *stream_get_status(
2036         struct dc_state *ctx,
2037         struct dc_stream_state *stream)
2038 {
2039         uint8_t i;
2040
2041         for (i = 0; i < ctx->stream_count; i++) {
2042                 if (stream == ctx->streams[i]) {
2043                         return &ctx->stream_status[i];
2044                 }
2045         }
2046
2047         return NULL;
2048 }
2049
2050 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2051
2052 static void copy_surface_update_to_plane(
2053                 struct dc_plane_state *surface,
2054                 struct dc_surface_update *srf_update)
2055 {
2056         if (srf_update->flip_addr) {
2057                 surface->address = srf_update->flip_addr->address;
2058                 surface->flip_immediate =
2059                         srf_update->flip_addr->flip_immediate;
2060                 surface->time.time_elapsed_in_us[surface->time.index] =
2061                         srf_update->flip_addr->flip_timestamp_in_us -
2062                                 surface->time.prev_update_time_in_us;
2063                 surface->time.prev_update_time_in_us =
2064                         srf_update->flip_addr->flip_timestamp_in_us;
2065                 surface->time.index++;
2066                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2067                         surface->time.index = 0;
2068
2069                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2070         }
2071
2072         if (srf_update->scaling_info) {
2073                 surface->scaling_quality =
2074                                 srf_update->scaling_info->scaling_quality;
2075                 surface->dst_rect =
2076                                 srf_update->scaling_info->dst_rect;
2077                 surface->src_rect =
2078                                 srf_update->scaling_info->src_rect;
2079                 surface->clip_rect =
2080                                 srf_update->scaling_info->clip_rect;
2081         }
2082
2083         if (srf_update->plane_info) {
2084                 surface->color_space =
2085                                 srf_update->plane_info->color_space;
2086                 surface->format =
2087                                 srf_update->plane_info->format;
2088                 surface->plane_size =
2089                                 srf_update->plane_info->plane_size;
2090                 surface->rotation =
2091                                 srf_update->plane_info->rotation;
2092                 surface->horizontal_mirror =
2093                                 srf_update->plane_info->horizontal_mirror;
2094                 surface->stereo_format =
2095                                 srf_update->plane_info->stereo_format;
2096                 surface->tiling_info =
2097                                 srf_update->plane_info->tiling_info;
2098                 surface->visible =
2099                                 srf_update->plane_info->visible;
2100                 surface->per_pixel_alpha =
2101                                 srf_update->plane_info->per_pixel_alpha;
2102                 surface->global_alpha =
2103                                 srf_update->plane_info->global_alpha;
2104                 surface->global_alpha_value =
2105                                 srf_update->plane_info->global_alpha_value;
2106                 surface->dcc =
2107                                 srf_update->plane_info->dcc;
2108                 surface->layer_index =
2109                                 srf_update->plane_info->layer_index;
2110         }
2111
2112         if (srf_update->gamma &&
2113                         (surface->gamma_correction !=
2114                                         srf_update->gamma)) {
2115                 memcpy(&surface->gamma_correction->entries,
2116                         &srf_update->gamma->entries,
2117                         sizeof(struct dc_gamma_entries));
2118                 surface->gamma_correction->is_identity =
2119                         srf_update->gamma->is_identity;
2120                 surface->gamma_correction->num_entries =
2121                         srf_update->gamma->num_entries;
2122                 surface->gamma_correction->type =
2123                         srf_update->gamma->type;
2124         }
2125
2126         if (srf_update->in_transfer_func &&
2127                         (surface->in_transfer_func !=
2128                                 srf_update->in_transfer_func)) {
2129                 surface->in_transfer_func->sdr_ref_white_level =
2130                         srf_update->in_transfer_func->sdr_ref_white_level;
2131                 surface->in_transfer_func->tf =
2132                         srf_update->in_transfer_func->tf;
2133                 surface->in_transfer_func->type =
2134                         srf_update->in_transfer_func->type;
2135                 memcpy(&surface->in_transfer_func->tf_pts,
2136                         &srf_update->in_transfer_func->tf_pts,
2137                         sizeof(struct dc_transfer_func_distributed_points));
2138         }
2139
2140         if (srf_update->func_shaper &&
2141                         (surface->in_shaper_func !=
2142                         srf_update->func_shaper))
2143                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2144                 sizeof(*surface->in_shaper_func));
2145
2146         if (srf_update->lut3d_func &&
2147                         (surface->lut3d_func !=
2148                         srf_update->lut3d_func))
2149                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2150                 sizeof(*surface->lut3d_func));
2151
2152         if (srf_update->hdr_mult.value)
2153                 surface->hdr_mult =
2154                                 srf_update->hdr_mult;
2155
2156         if (srf_update->blend_tf &&
2157                         (surface->blend_tf !=
2158                         srf_update->blend_tf))
2159                 memcpy(surface->blend_tf, srf_update->blend_tf,
2160                 sizeof(*surface->blend_tf));
2161
2162         if (srf_update->input_csc_color_matrix)
2163                 surface->input_csc_color_matrix =
2164                         *srf_update->input_csc_color_matrix;
2165
2166         if (srf_update->coeff_reduction_factor)
2167                 surface->coeff_reduction_factor =
2168                         *srf_update->coeff_reduction_factor;
2169
2170         if (srf_update->gamut_remap_matrix)
2171                 surface->gamut_remap_matrix =
2172                         *srf_update->gamut_remap_matrix;
2173 }
2174
2175 static void copy_stream_update_to_stream(struct dc *dc,
2176                                          struct dc_state *context,
2177                                          struct dc_stream_state *stream,
2178                                          struct dc_stream_update *update)
2179 {
2180         struct dc_context *dc_ctx = dc->ctx;
2181
2182         if (update == NULL || stream == NULL)
2183                 return;
2184
2185         if (update->src.height && update->src.width)
2186                 stream->src = update->src;
2187
2188         if (update->dst.height && update->dst.width)
2189                 stream->dst = update->dst;
2190
2191         if (update->out_transfer_func &&
2192             stream->out_transfer_func != update->out_transfer_func) {
2193                 stream->out_transfer_func->sdr_ref_white_level =
2194                         update->out_transfer_func->sdr_ref_white_level;
2195                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2196                 stream->out_transfer_func->type =
2197                         update->out_transfer_func->type;
2198                 memcpy(&stream->out_transfer_func->tf_pts,
2199                        &update->out_transfer_func->tf_pts,
2200                        sizeof(struct dc_transfer_func_distributed_points));
2201         }
2202
2203         if (update->hdr_static_metadata)
2204                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2205
2206         if (update->abm_level)
2207                 stream->abm_level = *update->abm_level;
2208
2209         if (update->periodic_interrupt0)
2210                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2211
2212         if (update->periodic_interrupt1)
2213                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2214
2215         if (update->gamut_remap)
2216                 stream->gamut_remap_matrix = *update->gamut_remap;
2217
2218         /* Note: this being updated after mode set is currently not a use case
2219          * however if it arises OCSC would need to be reprogrammed at the
2220          * minimum
2221          */
2222         if (update->output_color_space)
2223                 stream->output_color_space = *update->output_color_space;
2224
2225         if (update->output_csc_transform)
2226                 stream->csc_color_matrix = *update->output_csc_transform;
2227
2228         if (update->vrr_infopacket)
2229                 stream->vrr_infopacket = *update->vrr_infopacket;
2230
2231         if (update->dpms_off)
2232                 stream->dpms_off = *update->dpms_off;
2233
2234         if (update->vsc_infopacket)
2235                 stream->vsc_infopacket = *update->vsc_infopacket;
2236
2237         if (update->vsp_infopacket)
2238                 stream->vsp_infopacket = *update->vsp_infopacket;
2239
2240         if (update->dither_option)
2241                 stream->dither_option = *update->dither_option;
2242         /* update current stream with writeback info */
2243         if (update->wb_update) {
2244                 int i;
2245
2246                 stream->num_wb_info = update->wb_update->num_wb_info;
2247                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2248                 for (i = 0; i < stream->num_wb_info; i++)
2249                         stream->writeback_info[i] =
2250                                 update->wb_update->writeback_info[i];
2251         }
2252         if (update->dsc_config) {
2253                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2254                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2255                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2256                                        update->dsc_config->num_slices_v != 0);
2257
2258                 /* Use temporarry context for validating new DSC config */
2259                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2260
2261                 if (dsc_validate_context) {
2262                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2263
2264                         stream->timing.dsc_cfg = *update->dsc_config;
2265                         stream->timing.flags.DSC = enable_dsc;
2266                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2267                                 stream->timing.dsc_cfg = old_dsc_cfg;
2268                                 stream->timing.flags.DSC = old_dsc_enabled;
2269                                 update->dsc_config = NULL;
2270                         }
2271
2272                         dc_release_state(dsc_validate_context);
2273                 } else {
2274                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2275                         update->dsc_config = NULL;
2276                 }
2277         }
2278 }
2279
2280 static void commit_planes_do_stream_update(struct dc *dc,
2281                 struct dc_stream_state *stream,
2282                 struct dc_stream_update *stream_update,
2283                 enum surface_update_type update_type,
2284                 struct dc_state *context)
2285 {
2286         int j;
2287         bool should_program_abm;
2288
2289         // Stream updates
2290         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2291                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2292
2293                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2294
2295                         if (stream_update->periodic_interrupt0 &&
2296                                         dc->hwss.setup_periodic_interrupt)
2297                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2298
2299                         if (stream_update->periodic_interrupt1 &&
2300                                         dc->hwss.setup_periodic_interrupt)
2301                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2302
2303                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2304                                         stream_update->vrr_infopacket ||
2305                                         stream_update->vsc_infopacket ||
2306                                         stream_update->vsp_infopacket) {
2307                                 resource_build_info_frame(pipe_ctx);
2308                                 dc->hwss.update_info_frame(pipe_ctx);
2309                         }
2310
2311                         if (stream_update->hdr_static_metadata &&
2312                                         stream->use_dynamic_meta &&
2313                                         dc->hwss.set_dmdata_attributes &&
2314                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2315                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2316
2317                         if (stream_update->gamut_remap)
2318                                 dc_stream_set_gamut_remap(dc, stream);
2319
2320                         if (stream_update->output_csc_transform)
2321                                 dc_stream_program_csc_matrix(dc, stream);
2322
2323                         if (stream_update->dither_option) {
2324                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2325                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2326                                                                         &pipe_ctx->stream->bit_depth_params);
2327                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2328                                                 &stream->bit_depth_params,
2329                                                 &stream->clamping);
2330                                 while (odm_pipe) {
2331                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2332                                                         &stream->bit_depth_params,
2333                                                         &stream->clamping);
2334                                         odm_pipe = odm_pipe->next_odm_pipe;
2335                                 }
2336                         }
2337
2338                         /* Full fe update*/
2339                         if (update_type == UPDATE_TYPE_FAST)
2340                                 continue;
2341
2342                         if (stream_update->dsc_config)
2343                                 dp_update_dsc_config(pipe_ctx);
2344
2345                         if (stream_update->dpms_off) {
2346                                 if (*stream_update->dpms_off) {
2347                                         core_link_disable_stream(pipe_ctx);
2348                                         /* for dpms, keep acquired resources*/
2349                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2350                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2351
2352                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2353                                 } else {
2354                                         if (dc->optimize_seamless_boot_streams == 0)
2355                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2356
2357                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2358                                 }
2359                         }
2360
2361                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2362                                 should_program_abm = true;
2363
2364                                 // if otg funcs defined check if blanked before programming
2365                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2366                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2367                                                 should_program_abm = false;
2368
2369                                 if (should_program_abm) {
2370                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2371                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2372                                         } else {
2373                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2374                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2375                                         }
2376                                 }
2377                         }
2378                 }
2379         }
2380 }
2381
2382 static void commit_planes_for_stream(struct dc *dc,
2383                 struct dc_surface_update *srf_updates,
2384                 int surface_count,
2385                 struct dc_stream_state *stream,
2386                 struct dc_stream_update *stream_update,
2387                 enum surface_update_type update_type,
2388                 struct dc_state *context)
2389 {
2390         int i, j;
2391         struct pipe_ctx *top_pipe_to_program = NULL;
2392
2393         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2394                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2395                  * first flip. After first flip, optimization is required to lower
2396                  * bandwidth. Important to note that it is expected UEFI will
2397                  * only light up a single display on POST, therefore we only expect
2398                  * one stream with seamless boot flag set.
2399                  */
2400                 if (stream->apply_seamless_boot_optimization) {
2401                         stream->apply_seamless_boot_optimization = false;
2402                         dc->optimize_seamless_boot_streams--;
2403
2404                         if (dc->optimize_seamless_boot_streams == 0)
2405                                 dc->optimized_required = true;
2406                 }
2407         }
2408
2409         if (update_type == UPDATE_TYPE_FULL) {
2410 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2411                 dc_allow_idle_optimizations(dc, false);
2412
2413 #endif
2414                 if (dc->optimize_seamless_boot_streams == 0)
2415                         dc->hwss.prepare_bandwidth(dc, context);
2416
2417                 context_clock_trace(dc, context);
2418         }
2419
2420         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2421                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2422
2423                 if (!pipe_ctx->top_pipe &&
2424                         !pipe_ctx->prev_odm_pipe &&
2425                         pipe_ctx->stream &&
2426                         pipe_ctx->stream == stream) {
2427                         top_pipe_to_program = pipe_ctx;
2428                 }
2429         }
2430
2431         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2432                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2433                         if (should_use_dmub_lock(stream->link)) {
2434                                 union dmub_hw_lock_flags hw_locks = { 0 };
2435                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2436
2437                                 hw_locks.bits.lock_dig = 1;
2438                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2439
2440                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2441                                                         true,
2442                                                         &hw_locks,
2443                                                         &inst_flags);
2444                         } else
2445                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2446                                                 top_pipe_to_program->stream_res.tg);
2447                 }
2448
2449         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2450                 dc->hwss.interdependent_update_lock(dc, context, true);
2451         else
2452                 /* Lock the top pipe while updating plane addrs, since freesync requires
2453                  *  plane addr update event triggers to be synchronized.
2454                  *  top_pipe_to_program is expected to never be NULL
2455                  */
2456                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2457
2458         // Stream updates
2459         if (stream_update)
2460                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2461
2462         if (surface_count == 0) {
2463                 /*
2464                  * In case of turning off screen, no need to program front end a second time.
2465                  * just return after program blank.
2466                  */
2467                 if (dc->hwss.apply_ctx_for_surface)
2468                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2469                 if (dc->hwss.program_front_end_for_ctx)
2470                         dc->hwss.program_front_end_for_ctx(dc, context);
2471
2472                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2473                         dc->hwss.interdependent_update_lock(dc, context, false);
2474                 else
2475                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2476
2477                 dc->hwss.post_unlock_program_front_end(dc, context);
2478                 return;
2479         }
2480
2481         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2482                 for (i = 0; i < surface_count; i++) {
2483                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2484                         /*set logical flag for lock/unlock use*/
2485                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2486                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2487                                 if (!pipe_ctx->plane_state)
2488                                         continue;
2489                                 if (pipe_ctx->plane_state != plane_state)
2490                                         continue;
2491                                 plane_state->triplebuffer_flips = false;
2492                                 if (update_type == UPDATE_TYPE_FAST &&
2493                                         dc->hwss.program_triplebuffer != NULL &&
2494                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2495                                                 /*triple buffer for VUpdate  only*/
2496                                                 plane_state->triplebuffer_flips = true;
2497                                 }
2498                         }
2499                 }
2500         }
2501
2502         // Update Type FULL, Surface updates
2503         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2504                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2505
2506                 if (!pipe_ctx->top_pipe &&
2507                         !pipe_ctx->prev_odm_pipe &&
2508                         pipe_ctx->stream &&
2509                         pipe_ctx->stream == stream) {
2510                         struct dc_stream_status *stream_status = NULL;
2511
2512                         if (!pipe_ctx->plane_state)
2513                                 continue;
2514
2515                         /* Full fe update*/
2516                         if (update_type == UPDATE_TYPE_FAST)
2517                                 continue;
2518
2519                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2520
2521                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2522                                 /*turn off triple buffer for full update*/
2523                                 dc->hwss.program_triplebuffer(
2524                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2525                         }
2526                         stream_status =
2527                                 stream_get_status(context, pipe_ctx->stream);
2528
2529                         if (dc->hwss.apply_ctx_for_surface)
2530                                 dc->hwss.apply_ctx_for_surface(
2531                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2532                 }
2533         }
2534         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2535                 dc->hwss.program_front_end_for_ctx(dc, context);
2536 #ifdef CONFIG_DRM_AMD_DC_DCN
2537                 if (dc->debug.validate_dml_output) {
2538                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2539                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2540                                 if (cur_pipe.stream == NULL)
2541                                         continue;
2542
2543                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2544                                                 cur_pipe.plane_res.hubp, dc->ctx,
2545                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2546                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2547                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2548                         }
2549                 }
2550 #endif
2551         }
2552
2553         // Update Type FAST, Surface updates
2554         if (update_type == UPDATE_TYPE_FAST) {
2555                 if (dc->hwss.set_flip_control_gsl)
2556                         for (i = 0; i < surface_count; i++) {
2557                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2558
2559                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2560                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2561
2562                                         if (pipe_ctx->stream != stream)
2563                                                 continue;
2564
2565                                         if (pipe_ctx->plane_state != plane_state)
2566                                                 continue;
2567
2568                                         // GSL has to be used for flip immediate
2569                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2570                                                         plane_state->flip_immediate);
2571                                 }
2572                         }
2573                 /* Perform requested Updates */
2574                 for (i = 0; i < surface_count; i++) {
2575                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2576
2577                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2578                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2579
2580                                 if (pipe_ctx->stream != stream)
2581                                         continue;
2582
2583                                 if (pipe_ctx->plane_state != plane_state)
2584                                         continue;
2585                                 /*program triple buffer after lock based on flip type*/
2586                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2587                                         /*only enable triplebuffer for  fast_update*/
2588                                         dc->hwss.program_triplebuffer(
2589                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2590                                 }
2591                                 if (srf_updates[i].flip_addr)
2592                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2593                         }
2594                 }
2595         }
2596
2597         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2598                 dc->hwss.interdependent_update_lock(dc, context, false);
2599         else
2600                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2601
2602         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2603                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2604                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2605                                         top_pipe_to_program->stream_res.tg,
2606                                         CRTC_STATE_VACTIVE);
2607                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2608                                         top_pipe_to_program->stream_res.tg,
2609                                         CRTC_STATE_VBLANK);
2610                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2611                                         top_pipe_to_program->stream_res.tg,
2612                                         CRTC_STATE_VACTIVE);
2613
2614                         if (stream && should_use_dmub_lock(stream->link)) {
2615                                 union dmub_hw_lock_flags hw_locks = { 0 };
2616                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2617
2618                                 hw_locks.bits.lock_dig = 1;
2619                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2620
2621                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2622                                                         false,
2623                                                         &hw_locks,
2624                                                         &inst_flags);
2625                         } else
2626                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2627                                         top_pipe_to_program->stream_res.tg);
2628                 }
2629
2630         if (update_type != UPDATE_TYPE_FAST)
2631                 dc->hwss.post_unlock_program_front_end(dc, context);
2632
2633         // Fire manual trigger only when bottom plane is flipped
2634         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2635                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2636
2637                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2638                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2639                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2640                         continue;
2641
2642                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2643                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2644         }
2645 }
2646
2647 void dc_commit_updates_for_stream(struct dc *dc,
2648                 struct dc_surface_update *srf_updates,
2649                 int surface_count,
2650                 struct dc_stream_state *stream,
2651                 struct dc_stream_update *stream_update,
2652                 struct dc_state *state)
2653 {
2654         const struct dc_stream_status *stream_status;
2655         enum surface_update_type update_type;
2656         struct dc_state *context;
2657         struct dc_context *dc_ctx = dc->ctx;
2658         int i, j;
2659
2660         stream_status = dc_stream_get_status(stream);
2661         context = dc->current_state;
2662
2663         update_type = dc_check_update_surfaces_for_stream(
2664                                 dc, srf_updates, surface_count, stream_update, stream_status);
2665
2666         if (update_type >= update_surface_trace_level)
2667                 update_surface_trace(dc, srf_updates, surface_count);
2668
2669
2670         if (update_type >= UPDATE_TYPE_FULL) {
2671
2672                 /* initialize scratch memory for building context */
2673                 context = dc_create_state(dc);
2674                 if (context == NULL) {
2675                         DC_ERROR("Failed to allocate new validate context!\n");
2676                         return;
2677                 }
2678
2679                 dc_resource_state_copy_construct(state, context);
2680
2681                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2682                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2683                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2684
2685                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2686                                 new_pipe->plane_state->force_full_update = true;
2687                 }
2688         }
2689
2690
2691         for (i = 0; i < surface_count; i++) {
2692                 struct dc_plane_state *surface = srf_updates[i].surface;
2693
2694                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2695
2696                 if (update_type >= UPDATE_TYPE_MED) {
2697                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2698                                 struct pipe_ctx *pipe_ctx =
2699                                         &context->res_ctx.pipe_ctx[j];
2700
2701                                 if (pipe_ctx->plane_state != surface)
2702                                         continue;
2703
2704                                 resource_build_scaling_params(pipe_ctx);
2705                         }
2706                 }
2707         }
2708
2709         copy_stream_update_to_stream(dc, context, stream, stream_update);
2710
2711         if (update_type >= UPDATE_TYPE_FULL) {
2712                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2713                         DC_ERROR("Mode validation failed for stream update!\n");
2714                         dc_release_state(context);
2715                         return;
2716                 }
2717         }
2718
2719         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2720
2721         commit_planes_for_stream(
2722                                 dc,
2723                                 srf_updates,
2724                                 surface_count,
2725                                 stream,
2726                                 stream_update,
2727                                 update_type,
2728                                 context);
2729         /*update current_State*/
2730         if (dc->current_state != context) {
2731
2732                 struct dc_state *old = dc->current_state;
2733
2734                 dc->current_state = context;
2735                 dc_release_state(old);
2736
2737                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2738                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2739
2740                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2741                                 pipe_ctx->plane_state->force_full_update = false;
2742                 }
2743         }
2744         /*let's use current_state to update watermark etc*/
2745         if (update_type >= UPDATE_TYPE_FULL) {
2746                 dc_post_update_surfaces_to_stream(dc);
2747
2748                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
2749                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2750                 else
2751                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2752         }
2753
2754         return;
2755
2756 }
2757
2758 uint8_t dc_get_current_stream_count(struct dc *dc)
2759 {
2760         return dc->current_state->stream_count;
2761 }
2762
2763 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2764 {
2765         if (i < dc->current_state->stream_count)
2766                 return dc->current_state->streams[i];
2767         return NULL;
2768 }
2769
2770 enum dc_irq_source dc_interrupt_to_irq_source(
2771                 struct dc *dc,
2772                 uint32_t src_id,
2773                 uint32_t ext_id)
2774 {
2775         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2776 }
2777
2778 /**
2779  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2780  */
2781 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2782 {
2783
2784         if (dc == NULL)
2785                 return false;
2786
2787         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2788 }
2789
2790 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2791 {
2792         dal_irq_service_ack(dc->res_pool->irqs, src);
2793 }
2794
2795 void dc_power_down_on_boot(struct dc *dc)
2796 {
2797         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
2798                         dc->hwss.power_down_on_boot)
2799                 dc->hwss.power_down_on_boot(dc);
2800 }
2801
2802 void dc_set_power_state(
2803         struct dc *dc,
2804         enum dc_acpi_cm_power_state power_state)
2805 {
2806         struct kref refcount;
2807         struct display_mode_lib *dml;
2808
2809         switch (power_state) {
2810         case DC_ACPI_CM_POWER_STATE_D0:
2811                 dc_resource_state_construct(dc, dc->current_state);
2812
2813                 if (dc->ctx->dmub_srv)
2814                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2815
2816                 dc->hwss.init_hw(dc);
2817
2818                 if (dc->hwss.init_sys_ctx != NULL &&
2819                         dc->vm_pa_config.valid) {
2820                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2821                 }
2822
2823                 break;
2824         default:
2825                 ASSERT(dc->current_state->stream_count == 0);
2826                 /* Zero out the current context so that on resume we start with
2827                  * clean state, and dc hw programming optimizations will not
2828                  * cause any trouble.
2829                  */
2830                 dml = kzalloc(sizeof(struct display_mode_lib),
2831                                 GFP_KERNEL);
2832
2833                 ASSERT(dml);
2834                 if (!dml)
2835                         return;
2836
2837                 /* Preserve refcount */
2838                 refcount = dc->current_state->refcount;
2839                 /* Preserve display mode lib */
2840                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2841
2842                 dc_resource_state_destruct(dc->current_state);
2843                 memset(dc->current_state, 0,
2844                                 sizeof(*dc->current_state));
2845
2846                 dc->current_state->refcount = refcount;
2847                 dc->current_state->bw_ctx.dml = *dml;
2848
2849                 kfree(dml);
2850
2851                 break;
2852         }
2853 }
2854
2855 void dc_resume(struct dc *dc)
2856 {
2857         uint32_t i;
2858
2859         for (i = 0; i < dc->link_count; i++)
2860                 core_link_resume(dc->links[i]);
2861 }
2862
2863 bool dc_is_dmcu_initialized(struct dc *dc)
2864 {
2865         struct dmcu *dmcu = dc->res_pool->dmcu;
2866
2867         if (dmcu)
2868                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2869         return false;
2870 }
2871
2872 bool dc_submit_i2c(
2873                 struct dc *dc,
2874                 uint32_t link_index,
2875                 struct i2c_command *cmd)
2876 {
2877
2878         struct dc_link *link = dc->links[link_index];
2879         struct ddc_service *ddc = link->ddc;
2880         return dce_i2c_submit_command(
2881                 dc->res_pool,
2882                 ddc->ddc_pin,
2883                 cmd);
2884 }
2885
2886 bool dc_submit_i2c_oem(
2887                 struct dc *dc,
2888                 struct i2c_command *cmd)
2889 {
2890         struct ddc_service *ddc = dc->res_pool->oem_device;
2891         return dce_i2c_submit_command(
2892                 dc->res_pool,
2893                 ddc->ddc_pin,
2894                 cmd);
2895 }
2896
2897 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2898 {
2899         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2900                 BREAK_TO_DEBUGGER();
2901                 return false;
2902         }
2903
2904         dc_sink_retain(sink);
2905
2906         dc_link->remote_sinks[dc_link->sink_count] = sink;
2907         dc_link->sink_count++;
2908
2909         return true;
2910 }
2911
2912 /**
2913  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2914  *
2915  * EDID length is in bytes
2916  */
2917 struct dc_sink *dc_link_add_remote_sink(
2918                 struct dc_link *link,
2919                 const uint8_t *edid,
2920                 int len,
2921                 struct dc_sink_init_data *init_data)
2922 {
2923         struct dc_sink *dc_sink;
2924         enum dc_edid_status edid_status;
2925
2926         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2927                 dm_error("Max EDID buffer size breached!\n");
2928                 return NULL;
2929         }
2930
2931         if (!init_data) {
2932                 BREAK_TO_DEBUGGER();
2933                 return NULL;
2934         }
2935
2936         if (!init_data->link) {
2937                 BREAK_TO_DEBUGGER();
2938                 return NULL;
2939         }
2940
2941         dc_sink = dc_sink_create(init_data);
2942
2943         if (!dc_sink)
2944                 return NULL;
2945
2946         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2947         dc_sink->dc_edid.length = len;
2948
2949         if (!link_add_remote_sink_helper(
2950                         link,
2951                         dc_sink))
2952                 goto fail_add_sink;
2953
2954         edid_status = dm_helpers_parse_edid_caps(
2955                         link->ctx,
2956                         &dc_sink->dc_edid,
2957                         &dc_sink->edid_caps);
2958
2959         /*
2960          * Treat device as no EDID device if EDID
2961          * parsing fails
2962          */
2963         if (edid_status != EDID_OK) {
2964                 dc_sink->dc_edid.length = 0;
2965                 dm_error("Bad EDID, status%d!\n", edid_status);
2966         }
2967
2968         return dc_sink;
2969
2970 fail_add_sink:
2971         dc_sink_release(dc_sink);
2972         return NULL;
2973 }
2974
2975 /**
2976  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2977  *
2978  * Note that this just removes the struct dc_sink - it doesn't
2979  * program hardware or alter other members of dc_link
2980  */
2981 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2982 {
2983         int i;
2984
2985         if (!link->sink_count) {
2986                 BREAK_TO_DEBUGGER();
2987                 return;
2988         }
2989
2990         for (i = 0; i < link->sink_count; i++) {
2991                 if (link->remote_sinks[i] == sink) {
2992                         dc_sink_release(sink);
2993                         link->remote_sinks[i] = NULL;
2994
2995                         /* shrink array to remove empty place */
2996                         while (i < link->sink_count - 1) {
2997                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2998                                 i++;
2999                         }
3000                         link->remote_sinks[i] = NULL;
3001                         link->sink_count--;
3002                         return;
3003                 }
3004         }
3005 }
3006
3007 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3008 {
3009         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3010         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3011         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3012         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3013         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3014         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3015         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3016         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3017         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3018 }
3019 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3020 {
3021         if (dc->hwss.set_clock)
3022                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3023         return DC_ERROR_UNEXPECTED;
3024 }
3025 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3026 {
3027         if (dc->hwss.get_clock)
3028                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3029 }
3030
3031 /* enable/disable eDP PSR without specify stream for eDP */
3032 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3033 {
3034         int i;
3035
3036         for (i = 0; i < dc->current_state->stream_count ; i++) {
3037                 struct dc_link *link;
3038                 struct dc_stream_state *stream = dc->current_state->streams[i];
3039
3040                 link = stream->link;
3041                 if (!link)
3042                         continue;
3043
3044                 if (link->psr_settings.psr_feature_enabled) {
3045                         if (enable && !link->psr_settings.psr_allow_active)
3046                                 return dc_link_set_psr_allow_active(link, true, false);
3047                         else if (!enable && link->psr_settings.psr_allow_active)
3048                                 return dc_link_set_psr_allow_active(link, false, true);
3049                 }
3050         }
3051
3052         return true;
3053 }
3054
3055 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
3056
3057 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3058 {
3059         if (dc->debug.disable_idle_power_optimizations)
3060                 return;
3061
3062         if (allow == dc->idle_optimizations_allowed)
3063                 return;
3064
3065         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3066                 dc->idle_optimizations_allowed = allow;
3067 }
3068
3069 /*
3070  * blank all streams, and set min and max memory clock to
3071  * lowest and highest DPM level, respectively
3072  */
3073 void dc_unlock_memory_clock_frequency(struct dc *dc)
3074 {
3075         unsigned int i;
3076
3077         for (i = 0; i < MAX_PIPES; i++)
3078                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3079                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3080
3081         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3082         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3083 }
3084
3085 /*
3086  * set min memory clock to the min required for current mode,
3087  * max to maxDPM, and unblank streams
3088  */
3089 void dc_lock_memory_clock_frequency(struct dc *dc)
3090 {
3091         unsigned int i;
3092
3093         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3094         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3095         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3096
3097         for (i = 0; i < MAX_PIPES; i++)
3098                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3099                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3100 }
3101
3102 bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,
3103                                                  struct dc_plane_state *plane)
3104 {
3105         return false;
3106 }
3107
3108 /* cleanup on driver unload */
3109 void dc_hardware_release(struct dc *dc)
3110 {
3111         if (dc->hwss.hardware_release)
3112                 dc->hwss.hardware_release(dc);
3113 }
3114 #endif