drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #include "dmub/dmub_srv.h"
  70
  71 #include "dce/dmub_hw_lock_mgr.h"
  72
  73 #define CTX \
  74         dc->ctx
  75
  76 #define DC_LOGGER \
  77         dc->ctx->logger
  78
  79 static const char DC_BUILD_ID[] = "production-build";
  80
  81 /**
  82  * DOC: Overview
  83  *
  84  * DC is the OS-agnostic component of the amdgpu DC driver.
  85  *
  86  * DC maintains and validates a set of structs representing the state of the
  87  * driver and writes that state to AMD hardware
  88  *
  89  * Main DC HW structs:
  90  *
  91  * struct dc - The central struct.  One per driver.  Created on driver load,
  92  * destroyed on driver unload.
  93  *
  94  * struct dc_context - One per driver.
  95  * Used as a backpointer by most other structs in dc.
  96  *
  97  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  98  * plugpoints).  Created on driver load, destroyed on driver unload.
  99  *
 100  * struct dc_sink - One per display.  Created on boot or hotplug.
 101  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 102  * (the display directly attached).  It may also have one or more remote
 103  * sinks (in the Multi-Stream Transport case)
 104  *
 105  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 106  * main pipeline.  Not directly accessible by dm.
 107  *
 108  * Main dc state structs:
 109  *
 110  * These structs can be created and destroyed as needed.  There is a full set of
 111  * these structs in dc->current_state representing the currently programmed state.
 112  *
 113  * struct dc_state - The global DC state to track global state information,
 114  * such as bandwidth values.
 115  *
 116  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 117  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 118  *
 119  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 120  * and may have more in the Multi-Plane Overlay case.
 121  *
 122  * struct resource_context - Represents the programmable state of everything in
 123  * the resource_pool.  Not directly accessible by dm.
 124  *
 125  * struct pipe_ctx - A member of struct resource_context.  Represents the
 126  * internal hardware pipeline components.  Each dc_plane_state has either
 127  * one or two (in the pipe-split case).
 128  */
 129
 130 /*******************************************************************************
 131  * Private functions
 132  ******************************************************************************/
 133
 134 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 135 {
 136         if (new > *original)
 137                 *original = new;
 138 }
 139
 140 static void destroy_links(struct dc *dc)
 141 {
 142         uint32_t i;
 143
 144         for (i = 0; i < dc->link_count; i++) {
 145                 if (NULL != dc->links[i])
 146                         link_destroy(&dc->links[i]);
 147         }
 148 }
 149
 150 static bool create_links(
 151                 struct dc *dc,
 152                 uint32_t num_virtual_links)
 153 {
 154         int i;
 155         int connectors_num;
 156         struct dc_bios *bios = dc->ctx->dc_bios;
 157
 158         dc->link_count = 0;
 159
 160         connectors_num = bios->funcs->get_connectors_number(bios);
 161
 162         if (connectors_num > ENUM_ID_COUNT) {
 163                 dm_error(
 164                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 165                         connectors_num,
 166                         ENUM_ID_COUNT);
 167                 return false;
 168         }
 169
 170         dm_output_to_console(
 171                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 172                 __func__,
 173                 connectors_num,
 174                 num_virtual_links);
 175
 176         for (i = 0; i < connectors_num; i++) {
 177                 struct link_init_data link_init_params = {0};
 178                 struct dc_link *link;
 179
 180                 link_init_params.ctx = dc->ctx;
 181                 /* next BIOS object table connector */
 182                 link_init_params.connector_index = i;
 183                 link_init_params.link_index = dc->link_count;
 184                 link_init_params.dc = dc;
 185                 link = link_create(&link_init_params);
 186
 187                 if (link) {
 188                         bool should_destory_link = false;
 189
 190                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 191                                 if (dc->config.edp_not_connected) {
 192                                         if (!IS_DIAG_DC(dc->ctx->dce_environment))
 193                                                 should_destory_link = true;
 194                                 } else {
 195                                         enum dc_connection_type type;
 196                                         dc_link_detect_sink(link, &type);
 197                                         if (type == dc_connection_none)
 198                                                 should_destory_link = true;
 199                                 }
 200                         }
 201
 202                         if (dc->config.force_enum_edp || !should_destory_link) {
 203                                 dc->links[dc->link_count] = link;
 204                                 link->dc = dc;
 205                                 ++dc->link_count;
 206                         } else {
 207                                 link_destroy(&link);
 208                         }
 209                 }
 210         }
 211
 212         for (i = 0; i < num_virtual_links; i++) {
 213                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 214                 struct encoder_init_data enc_init = {0};
 215
 216                 if (link == NULL) {
 217                         BREAK_TO_DEBUGGER();
 218                         goto failed_alloc;
 219                 }
 220
 221                 link->link_index = dc->link_count;
 222                 dc->links[dc->link_count] = link;
 223                 dc->link_count++;
 224
 225                 link->ctx = dc->ctx;
 226                 link->dc = dc;
 227                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 228                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 229                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 230                 link->link_id.enum_id = ENUM_ID_1;
 231                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 232
 233                 if (!link->link_enc) {
 234                         BREAK_TO_DEBUGGER();
 235                         goto failed_alloc;
 236                 }
 237
 238                 link->link_status.dpcd_caps = &link->dpcd_caps;
 239
 240                 enc_init.ctx = dc->ctx;
 241                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 242                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 243                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 244                 enc_init.connector = link->link_id;
 245                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 246                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 247                 enc_init.encoder.enum_id = ENUM_ID_1;
 248                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 249         }
 250
 251         return true;
 252
 253 failed_alloc:
 254         return false;
 255 }
 256
 257 static struct dc_perf_trace *dc_perf_trace_create(void)
 258 {
 259         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 260 }
 261
 262 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 263 {
 264         kfree(*perf_trace);
 265         *perf_trace = NULL;
 266 }
 267
 268 /**
 269  *****************************************************************************
 270  *  Function: dc_stream_adjust_vmin_vmax
 271  *
 272  *  @brief
 273  *     Looks up the pipe context of dc_stream_state and updates the
 274  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 275  *     Rate, which is a power-saving feature that targets reducing panel
 276  *     refresh rate while the screen is static
 277  *
 278  *  @param [in] dc: dc reference
 279  *  @param [in] stream: Initial dc stream state
 280  *  @param [in] adjust: Updated parameters for vertical_total_min and
 281  *  vertical_total_max
 282  *****************************************************************************
 283  */
 284 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 285                 struct dc_stream_state *stream,
 286                 struct dc_crtc_timing_adjust *adjust)
 287 {
 288         int i = 0;
 289         bool ret = false;
 290
 291         stream->adjust = *adjust;
 292
 293         for (i = 0; i < MAX_PIPES; i++) {
 294                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 295
 296                 if (pipe->stream == stream && pipe->stream_res.tg) {
 297                         dc->hwss.set_drr(&pipe,
 298                                         1,
 299                                         adjust->v_total_min,
 300                                         adjust->v_total_max,
 301                                         adjust->v_total_mid,
 302                                         adjust->v_total_mid_frame_num);
 303
 304                         ret = true;
 305                 }
 306         }
 307         return ret;
 308 }
 309
 310 bool dc_stream_get_crtc_position(struct dc *dc,
 311                 struct dc_stream_state **streams, int num_streams,
 312                 unsigned int *v_pos, unsigned int *nom_v_pos)
 313 {
 314         /* TODO: Support multiple streams */
 315         const struct dc_stream_state *stream = streams[0];
 316         int i = 0;
 317         bool ret = false;
 318         struct crtc_position position;
 319
 320         for (i = 0; i < MAX_PIPES; i++) {
 321                 struct pipe_ctx *pipe =
 322                                 &dc->current_state->res_ctx.pipe_ctx[i];
 323
 324                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 325                         dc->hwss.get_position(&pipe, 1, &position);
 326
 327                         *v_pos = position.vertical_count;
 328                         *nom_v_pos = position.nominal_vcount;
 329                         ret = true;
 330                 }
 331         }
 332         return ret;
 333 }
 334
 335 /**
 336  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 337  * @dc: DC Object
 338  * @stream: The stream to configure CRC on.
 339  * @enable: Enable CRC if true, disable otherwise.
 340  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 341  *              once.
 342  *
 343  * By default, only CRC0 is configured, and the entire frame is used to
 344  * calculate the crc.
 345  */
 346 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 347                              bool enable, bool continuous)
 348 {
 349         int i;
 350         struct pipe_ctx *pipe;
 351         struct crc_params param;
 352         struct timing_generator *tg;
 353
 354         for (i = 0; i < MAX_PIPES; i++) {
 355                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 356                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 357                         break;
 358         }
 359         /* Stream not found */
 360         if (i == MAX_PIPES)
 361                 return false;
 362
 363         /* Always capture the full frame */
 364         param.windowa_x_start = 0;
 365         param.windowa_y_start = 0;
 366         param.windowa_x_end = pipe->stream->timing.h_addressable;
 367         param.windowa_y_end = pipe->stream->timing.v_addressable;
 368         param.windowb_x_start = 0;
 369         param.windowb_y_start = 0;
 370         param.windowb_x_end = pipe->stream->timing.h_addressable;
 371         param.windowb_y_end = pipe->stream->timing.v_addressable;
 372
 373         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 374         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 375
 376         /* Default to the union of both windows */
 377         param.selection = UNION_WINDOW_A_B;
 378         param.continuous_mode = continuous;
 379         param.enable = enable;
 380
 381         tg = pipe->stream_res.tg;
 382
 383         /* Only call if supported */
 384         if (tg->funcs->configure_crc)
 385                 return tg->funcs->configure_crc(tg, &param);
 386         DC_LOG_WARNING("CRC capture not supported.");
 387         return false;
 388 }
 389
 390 /**
 391  * dc_stream_get_crc() - Get CRC values for the given stream.
 392  * @dc: DC object
 393  * @stream: The DC stream state of the stream to get CRCs from.
 394  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 395  *
 396  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 397  * Return false if stream is not found, or if CRCs are not enabled.
 398  */
 399 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 400                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 401 {
 402         int i;
 403         struct pipe_ctx *pipe;
 404         struct timing_generator *tg;
 405
 406         for (i = 0; i < MAX_PIPES; i++) {
 407                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 408                 if (pipe->stream == stream)
 409                         break;
 410         }
 411         /* Stream not found */
 412         if (i == MAX_PIPES)
 413                 return false;
 414
 415         tg = pipe->stream_res.tg;
 416
 417         if (tg->funcs->get_crc)
 418                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 419         DC_LOG_WARNING("CRC capture not supported.");
 420         return false;
 421 }
 422
 423 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 424                 enum dc_dynamic_expansion option)
 425 {
 426         /* OPP FMT dyn expansion updates*/
 427         int i = 0;
 428         struct pipe_ctx *pipe_ctx;
 429
 430         for (i = 0; i < MAX_PIPES; i++) {
 431                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 432                                 == stream) {
 433                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 434                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 435                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 436                                         pipe_ctx->stream_res.opp,
 437                                         COLOR_SPACE_YCBCR601,
 438                                         stream->timing.display_color_depth,
 439                                         stream->signal);
 440                 }
 441         }
 442 }
 443
 444 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 445                 enum dc_dither_option option)
 446 {
 447         struct bit_depth_reduction_params params;
 448         struct dc_link *link = stream->link;
 449         struct pipe_ctx *pipes = NULL;
 450         int i;
 451
 452         for (i = 0; i < MAX_PIPES; i++) {
 453                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 454                                 stream) {
 455                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 456                         break;
 457                 }
 458         }
 459
 460         if (!pipes)
 461                 return;
 462         if (option > DITHER_OPTION_MAX)
 463                 return;
 464
 465         stream->dither_option = option;
 466
 467         memset(&params, 0, sizeof(params));
 468         resource_build_bit_depth_reduction_params(stream, &params);
 469         stream->bit_depth_params = params;
 470
 471         if (pipes->plane_res.xfm &&
 472             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 473                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 474                         pipes->plane_res.xfm,
 475                         pipes->plane_res.scl_data.lb_params.depth,
 476                         &stream->bit_depth_params);
 477         }
 478
 479         pipes->stream_res.opp->funcs->
 480                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 481 }
 482
 483 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 484 {
 485         int i = 0;
 486         bool ret = false;
 487         struct pipe_ctx *pipes;
 488
 489         for (i = 0; i < MAX_PIPES; i++) {
 490                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 491                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 492                         dc->hwss.program_gamut_remap(pipes);
 493                         ret = true;
 494                 }
 495         }
 496
 497         return ret;
 498 }
 499
 500 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 501 {
 502         int i = 0;
 503         bool ret = false;
 504         struct pipe_ctx *pipes;
 505
 506         for (i = 0; i < MAX_PIPES; i++) {
 507                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 508                                 == stream) {
 509
 510                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 511                         dc->hwss.program_output_csc(dc,
 512                                         pipes,
 513                                         stream->output_color_space,
 514                                         stream->csc_color_matrix.matrix,
 515                                         pipes->stream_res.opp->inst);
 516                         ret = true;
 517                 }
 518         }
 519
 520         return ret;
 521 }
 522
 523 void dc_stream_set_static_screen_params(struct dc *dc,
 524                 struct dc_stream_state **streams,
 525                 int num_streams,
 526                 const struct dc_static_screen_params *params)
 527 {
 528         int i = 0;
 529         int j = 0;
 530         struct pipe_ctx *pipes_affected[MAX_PIPES];
 531         int num_pipes_affected = 0;
 532
 533         for (i = 0; i < num_streams; i++) {
 534                 struct dc_stream_state *stream = streams[i];
 535
 536                 for (j = 0; j < MAX_PIPES; j++) {
 537                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 538                                         == stream) {
 539                                 pipes_affected[num_pipes_affected++] =
 540                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 541                         }
 542                 }
 543         }
 544
 545         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 546 }
 547
 548 static void dc_destruct(struct dc *dc)
 549 {
 550         if (dc->current_state) {
 551                 dc_release_state(dc->current_state);
 552                 dc->current_state = NULL;
 553         }
 554
 555         destroy_links(dc);
 556
 557         if (dc->clk_mgr) {
 558                 dc_destroy_clk_mgr(dc->clk_mgr);
 559                 dc->clk_mgr = NULL;
 560         }
 561
 562         dc_destroy_resource_pool(dc);
 563
 564         if (dc->ctx->gpio_service)
 565                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 566
 567         if (dc->ctx->created_bios)
 568                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 569
 570         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 571
 572         kfree(dc->ctx);
 573         dc->ctx = NULL;
 574
 575         kfree(dc->bw_vbios);
 576         dc->bw_vbios = NULL;
 577
 578         kfree(dc->bw_dceip);
 579         dc->bw_dceip = NULL;
 580
 581 #ifdef CONFIG_DRM_AMD_DC_DCN
 582         kfree(dc->dcn_soc);
 583         dc->dcn_soc = NULL;
 584
 585         kfree(dc->dcn_ip);
 586         dc->dcn_ip = NULL;
 587
 588 #endif
 589         kfree(dc->vm_helper);
 590         dc->vm_helper = NULL;
 591
 592 }
 593
 594 static bool dc_construct_ctx(struct dc *dc,
 595                 const struct dc_init_data *init_params)
 596 {
 597         struct dc_context *dc_ctx;
 598         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 599
 600         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 601         if (!dc_ctx)
 602                 return false;
 603
 604         dc_ctx->cgs_device = init_params->cgs_device;
 605         dc_ctx->driver_context = init_params->driver;
 606         dc_ctx->dc = dc;
 607         dc_ctx->asic_id = init_params->asic_id;
 608         dc_ctx->dc_sink_id_count = 0;
 609         dc_ctx->dc_stream_id_count = 0;
 610         dc_ctx->dce_environment = init_params->dce_environment;
 611
 612         /* Create logger */
 613
 614         dc_version = resource_parse_asic_id(init_params->asic_id);
 615         dc_ctx->dce_version = dc_version;
 616
 617         dc_ctx->perf_trace = dc_perf_trace_create();
 618         if (!dc_ctx->perf_trace) {
 619                 ASSERT_CRITICAL(false);
 620                 return false;
 621         }
 622
 623         dc->ctx = dc_ctx;
 624
 625         return true;
 626 }
 627
 628 static bool dc_construct(struct dc *dc,
 629                 const struct dc_init_data *init_params)
 630 {
 631         struct dc_context *dc_ctx;
 632         struct bw_calcs_dceip *dc_dceip;
 633         struct bw_calcs_vbios *dc_vbios;
 634 #ifdef CONFIG_DRM_AMD_DC_DCN
 635         struct dcn_soc_bounding_box *dcn_soc;
 636         struct dcn_ip_params *dcn_ip;
 637 #endif
 638
 639         dc->config = init_params->flags;
 640
 641         // Allocate memory for the vm_helper
 642         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 643         if (!dc->vm_helper) {
 644                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 645                 goto fail;
 646         }
 647
 648         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 649
 650         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 651         if (!dc_dceip) {
 652                 dm_error("%s: failed to create dceip\n", __func__);
 653                 goto fail;
 654         }
 655
 656         dc->bw_dceip = dc_dceip;
 657
 658         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 659         if (!dc_vbios) {
 660                 dm_error("%s: failed to create vbios\n", __func__);
 661                 goto fail;
 662         }
 663
 664         dc->bw_vbios = dc_vbios;
 665 #ifdef CONFIG_DRM_AMD_DC_DCN
 666         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 667         if (!dcn_soc) {
 668                 dm_error("%s: failed to create dcn_soc\n", __func__);
 669                 goto fail;
 670         }
 671
 672         dc->dcn_soc = dcn_soc;
 673
 674         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 675         if (!dcn_ip) {
 676                 dm_error("%s: failed to create dcn_ip\n", __func__);
 677                 goto fail;
 678         }
 679
 680         dc->dcn_ip = dcn_ip;
 681         dc->soc_bounding_box = init_params->soc_bounding_box;
 682 #endif
 683
 684         if (!dc_construct_ctx(dc, init_params)) {
 685                 dm_error("%s: failed to create ctx\n", __func__);
 686                 goto fail;
 687         }
 688
 689         dc_ctx = dc->ctx;
 690
 691         /* Resource should construct all asic specific resources.
 692          * This should be the only place where we need to parse the asic id
 693          */
 694         if (init_params->vbios_override)
 695                 dc_ctx->dc_bios = init_params->vbios_override;
 696         else {
 697                 /* Create BIOS parser */
 698                 struct bp_init_data bp_init_data;
 699
 700                 bp_init_data.ctx = dc_ctx;
 701                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 702
 703                 dc_ctx->dc_bios = dal_bios_parser_create(
 704                                 &bp_init_data, dc_ctx->dce_version);
 705
 706                 if (!dc_ctx->dc_bios) {
 707                         ASSERT_CRITICAL(false);
 708                         goto fail;
 709                 }
 710
 711                 dc_ctx->created_bios = true;
 712         }
 713
 714         dc->vendor_signature = init_params->vendor_signature;
 715
 716         /* Create GPIO service */
 717         dc_ctx->gpio_service = dal_gpio_service_create(
 718                         dc_ctx->dce_version,
 719                         dc_ctx->dce_environment,
 720                         dc_ctx);
 721
 722         if (!dc_ctx->gpio_service) {
 723                 ASSERT_CRITICAL(false);
 724                 goto fail;
 725         }
 726
 727         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 728         if (!dc->res_pool)
 729                 goto fail;
 730
 731         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 732         if (!dc->clk_mgr)
 733                 goto fail;
 734 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
 735         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 736 #endif
 737
 738         if (dc->res_pool->funcs->update_bw_bounding_box)
 739                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 740
 741         /* Creation of current_state must occur after dc->dml
 742          * is initialized in dc_create_resource_pool because
 743          * on creation it copies the contents of dc->dml
 744          */
 745
 746         dc->current_state = dc_create_state(dc);
 747
 748         if (!dc->current_state) {
 749                 dm_error("%s: failed to create validate ctx\n", __func__);
 750                 goto fail;
 751         }
 752
 753         dc_resource_state_construct(dc, dc->current_state);
 754
 755         if (!create_links(dc, init_params->num_virtual_links))
 756                 goto fail;
 757
 758         return true;
 759
 760 fail:
 761         return false;
 762 }
 763
 764 static bool disable_all_writeback_pipes_for_stream(
 765                 const struct dc *dc,
 766                 struct dc_stream_state *stream,
 767                 struct dc_state *context)
 768 {
 769         int i;
 770
 771         for (i = 0; i < stream->num_wb_info; i++)
 772                 stream->writeback_info[i].wb_enabled = false;
 773
 774         return true;
 775 }
 776
 777 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 778 {
 779         int i = 0;
 780
 781         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 782         if (dc->hwss.interdependent_update_lock)
 783                 dc->hwss.interdependent_update_lock(dc, context, lock);
 784         else {
 785                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 786                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 787                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 788
 789                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 790                         if (stream == pipe_ctx->stream) {
 791                                 if (!pipe_ctx->top_pipe &&
 792                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 793                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 794                         }
 795                 }
 796         }
 797 }
 798
 799 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 800 {
 801         int i, j;
 802         struct dc_state *dangling_context = dc_create_state(dc);
 803         struct dc_state *current_ctx;
 804
 805         if (dangling_context == NULL)
 806                 return;
 807
 808         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 809
 810         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 811                 struct dc_stream_state *old_stream =
 812                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 813                 bool should_disable = true;
 814
 815                 for (j = 0; j < context->stream_count; j++) {
 816                         if (old_stream == context->streams[j]) {
 817                                 should_disable = false;
 818                                 break;
 819                         }
 820                 }
 821                 if (should_disable && old_stream) {
 822                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 823                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 824
 825                         if (dc->hwss.apply_ctx_for_surface) {
 826                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 827                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 828                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 829                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 830                         }
 831                         if (dc->hwss.program_front_end_for_ctx) {
 832                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 833                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 834                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 835                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 836                         }
 837                 }
 838         }
 839
 840         current_ctx = dc->current_state;
 841         dc->current_state = dangling_context;
 842         dc_release_state(current_ctx);
 843 }
 844
 845 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 846 {
 847         int i;
 848         PERF_TRACE();
 849         for (i = 0; i < MAX_PIPES; i++) {
 850                 int count = 0;
 851                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 852
 853                 if (!pipe->plane_state)
 854                         continue;
 855
 856                 /* Timeout 100 ms */
 857                 while (count < 100000) {
 858                         /* Must set to false to start with, due to OR in update function */
 859                         pipe->plane_state->status.is_flip_pending = false;
 860                         dc->hwss.update_pending_status(pipe);
 861                         if (!pipe->plane_state->status.is_flip_pending)
 862                                 break;
 863                         udelay(1);
 864                         count++;
 865                 }
 866                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 867         }
 868         PERF_TRACE();
 869 }
 870
 871 /*******************************************************************************
 872  * Public functions
 873  ******************************************************************************/
 874
 875 struct dc *dc_create(const struct dc_init_data *init_params)
 876 {
 877         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 878         unsigned int full_pipe_count;
 879
 880         if (NULL == dc)
 881                 goto alloc_fail;
 882
 883         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 884                 if (false == dc_construct_ctx(dc, init_params)) {
 885                         dc_destruct(dc);
 886                         goto construct_fail;
 887                 }
 888         } else {
 889                 if (false == dc_construct(dc, init_params)) {
 890                         dc_destruct(dc);
 891                         goto construct_fail;
 892                 }
 893
 894                 full_pipe_count = dc->res_pool->pipe_count;
 895                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 896                         full_pipe_count--;
 897                 dc->caps.max_streams = min(
 898                                 full_pipe_count,
 899                                 dc->res_pool->stream_enc_count);
 900
 901                 dc->optimize_seamless_boot_streams = 0;
 902                 dc->caps.max_links = dc->link_count;
 903                 dc->caps.max_audios = dc->res_pool->audio_count;
 904                 dc->caps.linear_pitch_alignment = 64;
 905
 906                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 907
 908                 if (dc->res_pool->dmcu != NULL)
 909                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 910         }
 911
 912         /* Populate versioning information */
 913         dc->versions.dc_ver = DC_VER;
 914
 915         dc->build_id = DC_BUILD_ID;
 916
 917         DC_LOG_DC("Display Core initialized\n");
 918
 919
 920
 921         return dc;
 922
 923 construct_fail:
 924         kfree(dc);
 925
 926 alloc_fail:
 927         return NULL;
 928 }
 929
 930 void dc_hardware_init(struct dc *dc)
 931 {
 932         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
 933                 dc->hwss.init_hw(dc);
 934 }
 935
 936 void dc_init_callbacks(struct dc *dc,
 937                 const struct dc_callback_init *init_params)
 938 {
 939 #ifdef CONFIG_DRM_AMD_DC_HDCP
 940         dc->ctx->cp_psp = init_params->cp_psp;
 941 #endif
 942 }
 943
 944 void dc_deinit_callbacks(struct dc *dc)
 945 {
 946 #ifdef CONFIG_DRM_AMD_DC_HDCP
 947         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
 948 #endif
 949 }
 950
 951 void dc_destroy(struct dc **dc)
 952 {
 953         dc_destruct(*dc);
 954         kfree(*dc);
 955         *dc = NULL;
 956 }
 957
 958 static void enable_timing_multisync(
 959                 struct dc *dc,
 960                 struct dc_state *ctx)
 961 {
 962         int i = 0, multisync_count = 0;
 963         int pipe_count = dc->res_pool->pipe_count;
 964         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 965
 966         for (i = 0; i < pipe_count; i++) {
 967                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 968                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 969                         continue;
 970                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 971                         continue;
 972                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 973                 multisync_count++;
 974         }
 975
 976         if (multisync_count > 0) {
 977                 dc->hwss.enable_per_frame_crtc_position_reset(
 978                         dc, multisync_count, multisync_pipes);
 979         }
 980 }
 981
 982 static void program_timing_sync(
 983                 struct dc *dc,
 984                 struct dc_state *ctx)
 985 {
 986         int i, j, k;
 987         int group_index = 0;
 988         int num_group = 0;
 989         int pipe_count = dc->res_pool->pipe_count;
 990         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 991
 992         for (i = 0; i < pipe_count; i++) {
 993                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 994                         continue;
 995
 996                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 997         }
 998
 999         for (i = 0; i < pipe_count; i++) {
1000                 int group_size = 1;
1001                 struct pipe_ctx *pipe_set[MAX_PIPES];
1002
1003                 if (!unsynced_pipes[i])
1004                         continue;
1005
1006                 pipe_set[0] = unsynced_pipes[i];
1007                 unsynced_pipes[i] = NULL;
1008
1009                 /* Add tg to the set, search rest of the tg's for ones with
1010                  * same timing, add all tgs with same timing to the group
1011                  */
1012                 for (j = i + 1; j < pipe_count; j++) {
1013                         if (!unsynced_pipes[j])
1014                                 continue;
1015
1016                         if (resource_are_streams_timing_synchronizable(
1017                                         unsynced_pipes[j]->stream,
1018                                         pipe_set[0]->stream)) {
1019                                 pipe_set[group_size] = unsynced_pipes[j];
1020                                 unsynced_pipes[j] = NULL;
1021                                 group_size++;
1022                         }
1023                 }
1024
1025                 /* set first unblanked pipe as master */
1026                 for (j = 0; j < group_size; j++) {
1027                         bool is_blanked;
1028
1029                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1030                                 is_blanked =
1031                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1032                         else
1033                                 is_blanked =
1034                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1035                         if (!is_blanked) {
1036                                 if (j == 0)
1037                                         break;
1038
1039                                 swap(pipe_set[0], pipe_set[j]);
1040                                 break;
1041                         }
1042                 }
1043
1044
1045                 for (k = 0; k < group_size; k++) {
1046                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1047
1048                         status->timing_sync_info.group_id = num_group;
1049                         status->timing_sync_info.group_size = group_size;
1050                         if (k == 0)
1051                                 status->timing_sync_info.master = true;
1052                         else
1053                                 status->timing_sync_info.master = false;
1054
1055                 }
1056                 /* remove any other unblanked pipes as they have already been synced */
1057                 for (j = j + 1; j < group_size; j++) {
1058                         bool is_blanked;
1059
1060                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1061                                 is_blanked =
1062                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1063                         else
1064                                 is_blanked =
1065                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1066                         if (!is_blanked) {
1067                                 group_size--;
1068                                 pipe_set[j] = pipe_set[group_size];
1069                                 j--;
1070                         }
1071                 }
1072
1073                 if (group_size > 1) {
1074                         dc->hwss.enable_timing_synchronization(
1075                                 dc, group_index, group_size, pipe_set);
1076                         group_index++;
1077                 }
1078                 num_group++;
1079         }
1080 }
1081
1082 static bool context_changed(
1083                 struct dc *dc,
1084                 struct dc_state *context)
1085 {
1086         uint8_t i;
1087
1088         if (context->stream_count != dc->current_state->stream_count)
1089                 return true;
1090
1091         for (i = 0; i < dc->current_state->stream_count; i++) {
1092                 if (dc->current_state->streams[i] != context->streams[i])
1093                         return true;
1094         }
1095
1096         return false;
1097 }
1098
1099 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1100                                 const struct dc_sink *sink,
1101                                 struct dc_crtc_timing *crtc_timing)
1102 {
1103         struct timing_generator *tg;
1104         struct stream_encoder *se = NULL;
1105
1106         struct dc_crtc_timing hw_crtc_timing = {0};
1107
1108         struct dc_link *link = sink->link;
1109         unsigned int i, enc_inst, tg_inst = 0;
1110
1111         // Seamless port only support single DP and EDP so far
1112         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1113                 sink->sink_signal != SIGNAL_TYPE_EDP)
1114                 return false;
1115
1116         /* Check for enabled DIG to identify enabled display */
1117         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1118                 return false;
1119
1120         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1121
1122         if (enc_inst == ENGINE_ID_UNKNOWN)
1123                 return false;
1124
1125         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1126                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1127
1128                         se = dc->res_pool->stream_enc[i];
1129
1130                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1131                                 dc->res_pool->stream_enc[i]);
1132                         break;
1133                 }
1134         }
1135
1136         // tg_inst not found
1137         if (i == dc->res_pool->stream_enc_count)
1138                 return false;
1139
1140         if (tg_inst >= dc->res_pool->timing_generator_count)
1141                 return false;
1142
1143         tg = dc->res_pool->timing_generators[tg_inst];
1144
1145         if (!tg->funcs->get_hw_timing)
1146                 return false;
1147
1148         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1149                 return false;
1150
1151         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1152                 return false;
1153
1154         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1155                 return false;
1156
1157         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1158                 return false;
1159
1160         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1161                 return false;
1162
1163         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1164                 return false;
1165
1166         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1167                 return false;
1168
1169         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1170                 return false;
1171
1172         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1173                 return false;
1174
1175         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1176                 return false;
1177
1178         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1179                 return false;
1180
1181         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1182                 return false;
1183
1184         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1185                 return false;
1186
1187         if (dc_is_dp_signal(link->connector_signal)) {
1188                 unsigned int pix_clk_100hz;
1189
1190                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1191                         dc->res_pool->dp_clock_source,
1192                         tg_inst, &pix_clk_100hz);
1193
1194                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1195                         return false;
1196
1197                 if (!se->funcs->dp_get_pixel_format)
1198                         return false;
1199
1200                 if (!se->funcs->dp_get_pixel_format(
1201                         se,
1202                         &hw_crtc_timing.pixel_encoding,
1203                         &hw_crtc_timing.display_color_depth))
1204                         return false;
1205
1206                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1207                         return false;
1208
1209                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1210                         return false;
1211         }
1212
1213         return true;
1214 }
1215
1216 bool dc_enable_stereo(
1217         struct dc *dc,
1218         struct dc_state *context,
1219         struct dc_stream_state *streams[],
1220         uint8_t stream_count)
1221 {
1222         bool ret = true;
1223         int i, j;
1224         struct pipe_ctx *pipe;
1225
1226         for (i = 0; i < MAX_PIPES; i++) {
1227                 if (context != NULL)
1228                         pipe = &context->res_ctx.pipe_ctx[i];
1229                 else
1230                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1231                 for (j = 0 ; pipe && j < stream_count; j++)  {
1232                         if (streams[j] && streams[j] == pipe->stream &&
1233                                 dc->hwss.setup_stereo)
1234                                 dc->hwss.setup_stereo(pipe, dc);
1235                 }
1236         }
1237
1238         return ret;
1239 }
1240
1241 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1242 {
1243         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1244                 enable_timing_multisync(dc, context);
1245                 program_timing_sync(dc, context);
1246         }
1247 }
1248
1249 /*
1250  * Applies given context to HW and copy it into current context.
1251  * It's up to the user to release the src context afterwards.
1252  */
1253 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1254 {
1255         struct dc_bios *dcb = dc->ctx->dc_bios;
1256         enum dc_status result = DC_ERROR_UNEXPECTED;
1257         struct pipe_ctx *pipe;
1258         int i, k, l;
1259         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1260
1261 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1262         dc_allow_idle_optimizations(dc, false);
1263 #endif
1264
1265         for (i = 0; i < context->stream_count; i++)
1266                 dc_streams[i] =  context->streams[i];
1267
1268         if (!dcb->funcs->is_accelerated_mode(dcb))
1269                 dc->hwss.enable_accelerated_mode(dc, context);
1270
1271         for (i = 0; i < context->stream_count; i++) {
1272                 if (context->streams[i]->apply_seamless_boot_optimization)
1273                         dc->optimize_seamless_boot_streams++;
1274         }
1275
1276         if (dc->optimize_seamless_boot_streams == 0)
1277                 dc->hwss.prepare_bandwidth(dc, context);
1278
1279         disable_dangling_plane(dc, context);
1280         /* re-program planes for existing stream, in case we need to
1281          * free up plane resource for later use
1282          */
1283         if (dc->hwss.apply_ctx_for_surface) {
1284                 for (i = 0; i < context->stream_count; i++) {
1285                         if (context->streams[i]->mode_changed)
1286                                 continue;
1287                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1288                         dc->hwss.apply_ctx_for_surface(
1289                                 dc, context->streams[i],
1290                                 context->stream_status[i].plane_count,
1291                                 context); /* use new pipe config in new context */
1292                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1293                         dc->hwss.post_unlock_program_front_end(dc, context);
1294                 }
1295         }
1296
1297         /* Program hardware */
1298         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1299                 pipe = &context->res_ctx.pipe_ctx[i];
1300                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1301         }
1302
1303         result = dc->hwss.apply_ctx_to_hw(dc, context);
1304
1305         if (result != DC_OK)
1306                 return result;
1307
1308         dc_trigger_sync(dc, context);
1309
1310         /* Program all planes within new context*/
1311         if (dc->hwss.program_front_end_for_ctx) {
1312                 dc->hwss.interdependent_update_lock(dc, context, true);
1313                 dc->hwss.program_front_end_for_ctx(dc, context);
1314                 dc->hwss.interdependent_update_lock(dc, context, false);
1315                 dc->hwss.post_unlock_program_front_end(dc, context);
1316         }
1317         for (i = 0; i < context->stream_count; i++) {
1318                 const struct dc_link *link = context->streams[i]->link;
1319
1320                 if (!context->streams[i]->mode_changed)
1321                         continue;
1322
1323                 if (dc->hwss.apply_ctx_for_surface) {
1324                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1325                         dc->hwss.apply_ctx_for_surface(
1326                                         dc, context->streams[i],
1327                                         context->stream_status[i].plane_count,
1328                                         context);
1329                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1330                         dc->hwss.post_unlock_program_front_end(dc, context);
1331                 }
1332
1333                 /*
1334                  * enable stereo
1335                  * TODO rework dc_enable_stereo call to work with validation sets?
1336                  */
1337                 for (k = 0; k < MAX_PIPES; k++) {
1338                         pipe = &context->res_ctx.pipe_ctx[k];
1339
1340                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1341                                 if (context->streams[l] &&
1342                                         context->streams[l] == pipe->stream &&
1343                                         dc->hwss.setup_stereo)
1344                                         dc->hwss.setup_stereo(pipe, dc);
1345                         }
1346                 }
1347
1348                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1349                                 context->streams[i]->timing.h_addressable,
1350                                 context->streams[i]->timing.v_addressable,
1351                                 context->streams[i]->timing.h_total,
1352                                 context->streams[i]->timing.v_total,
1353                                 context->streams[i]->timing.pix_clk_100hz / 10);
1354         }
1355
1356         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1357
1358         if (dc->optimize_seamless_boot_streams == 0) {
1359                 /* Must wait for no flips to be pending before doing optimize bw */
1360                 wait_for_no_pipes_pending(dc, context);
1361                 /* pplib is notified if disp_num changed */
1362                 dc->hwss.optimize_bandwidth(dc, context);
1363         }
1364
1365         for (i = 0; i < context->stream_count; i++)
1366                 context->streams[i]->mode_changed = false;
1367
1368         dc_release_state(dc->current_state);
1369
1370         dc->current_state = context;
1371
1372         dc_retain_state(dc->current_state);
1373
1374         return result;
1375 }
1376
1377 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1378 {
1379         enum dc_status result = DC_ERROR_UNEXPECTED;
1380         int i;
1381
1382         if (false == context_changed(dc, context))
1383                 return DC_OK;
1384
1385         DC_LOG_DC("%s: %d streams\n",
1386                                 __func__, context->stream_count);
1387
1388         for (i = 0; i < context->stream_count; i++) {
1389                 struct dc_stream_state *stream = context->streams[i];
1390
1391                 dc_stream_log(dc, stream);
1392         }
1393
1394         result = dc_commit_state_no_check(dc, context);
1395
1396         return (result == DC_OK);
1397 }
1398
1399 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1400 bool dc_acquire_release_mpc_3dlut(
1401                 struct dc *dc, bool acquire,
1402                 struct dc_stream_state *stream,
1403                 struct dc_3dlut **lut,
1404                 struct dc_transfer_func **shaper)
1405 {
1406         int pipe_idx;
1407         bool ret = false;
1408         bool found_pipe_idx = false;
1409         const struct resource_pool *pool = dc->res_pool;
1410         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1411         int mpcc_id = 0;
1412
1413         if (pool && res_ctx) {
1414                 if (acquire) {
1415                         /*find pipe idx for the given stream*/
1416                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1417                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1418                                         found_pipe_idx = true;
1419                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1420                                         break;
1421                                 }
1422                         }
1423                 } else
1424                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1425
1426                 if (found_pipe_idx) {
1427                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1428                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1429                         else if (acquire == false && pool->funcs->release_post_bldn_3dlut)
1430                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1431                 }
1432         }
1433         return ret;
1434 }
1435 #endif
1436 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1437 {
1438         int i;
1439         struct pipe_ctx *pipe;
1440
1441         for (i = 0; i < MAX_PIPES; i++) {
1442                 pipe = &context->res_ctx.pipe_ctx[i];
1443
1444                 if (!pipe->plane_state)
1445                         continue;
1446
1447                 /* Must set to false to start with, due to OR in update function */
1448                 pipe->plane_state->status.is_flip_pending = false;
1449                 dc->hwss.update_pending_status(pipe);
1450                 if (pipe->plane_state->status.is_flip_pending)
1451                         return true;
1452         }
1453         return false;
1454 }
1455
1456 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1457 {
1458         int i;
1459         struct dc_state *context = dc->current_state;
1460
1461         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1462                 return true;
1463
1464         post_surface_trace(dc);
1465
1466         if (is_flip_pending_in_pipes(dc, context))
1467                 return true;
1468
1469         for (i = 0; i < dc->res_pool->pipe_count; i++)
1470                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1471                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1472                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1473                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1474                 }
1475
1476         dc->hwss.optimize_bandwidth(dc, context);
1477
1478         dc->optimized_required = false;
1479         dc->wm_optimized_required = false;
1480
1481         return true;
1482 }
1483
1484 static void init_state(struct dc *dc, struct dc_state *context)
1485 {
1486         /* Each context must have their own instance of VBA and in order to
1487          * initialize and obtain IP and SOC the base DML instance from DC is
1488          * initially copied into every context
1489          */
1490 #ifdef CONFIG_DRM_AMD_DC_DCN
1491         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1492 #endif
1493 }
1494
1495 struct dc_state *dc_create_state(struct dc *dc)
1496 {
1497         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1498                                            GFP_KERNEL);
1499
1500         if (!context)
1501                 return NULL;
1502
1503         init_state(dc, context);
1504
1505         kref_init(&context->refcount);
1506
1507         return context;
1508 }
1509
1510 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1511 {
1512         int i, j;
1513         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1514
1515         if (!new_ctx)
1516                 return NULL;
1517         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1518
1519         for (i = 0; i < MAX_PIPES; i++) {
1520                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1521
1522                         if (cur_pipe->top_pipe)
1523                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1524
1525                         if (cur_pipe->bottom_pipe)
1526                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1527
1528                         if (cur_pipe->prev_odm_pipe)
1529                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1530
1531                         if (cur_pipe->next_odm_pipe)
1532                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1533
1534         }
1535
1536         for (i = 0; i < new_ctx->stream_count; i++) {
1537                         dc_stream_retain(new_ctx->streams[i]);
1538                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1539                                 dc_plane_state_retain(
1540                                         new_ctx->stream_status[i].plane_states[j]);
1541         }
1542
1543         kref_init(&new_ctx->refcount);
1544
1545         return new_ctx;
1546 }
1547
1548 void dc_retain_state(struct dc_state *context)
1549 {
1550         kref_get(&context->refcount);
1551 }
1552
1553 static void dc_state_free(struct kref *kref)
1554 {
1555         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1556         dc_resource_state_destruct(context);
1557         kvfree(context);
1558 }
1559
1560 void dc_release_state(struct dc_state *context)
1561 {
1562         kref_put(&context->refcount, dc_state_free);
1563 }
1564
1565 bool dc_set_generic_gpio_for_stereo(bool enable,
1566                 struct gpio_service *gpio_service)
1567 {
1568         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1569         struct gpio_pin_info pin_info;
1570         struct gpio *generic;
1571         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1572                            GFP_KERNEL);
1573
1574         if (!config)
1575                 return false;
1576         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1577
1578         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1579                 kfree(config);
1580                 return false;
1581         } else {
1582                 generic = dal_gpio_service_create_generic_mux(
1583                         gpio_service,
1584                         pin_info.offset,
1585                         pin_info.mask);
1586         }
1587
1588         if (!generic) {
1589                 kfree(config);
1590                 return false;
1591         }
1592
1593         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1594
1595         config->enable_output_from_mux = enable;
1596         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1597
1598         if (gpio_result == GPIO_RESULT_OK)
1599                 gpio_result = dal_mux_setup_config(generic, config);
1600
1601         if (gpio_result == GPIO_RESULT_OK) {
1602                 dal_gpio_close(generic);
1603                 dal_gpio_destroy_generic_mux(&generic);
1604                 kfree(config);
1605                 return true;
1606         } else {
1607                 dal_gpio_close(generic);
1608                 dal_gpio_destroy_generic_mux(&generic);
1609                 kfree(config);
1610                 return false;
1611         }
1612 }
1613
1614 static bool is_surface_in_context(
1615                 const struct dc_state *context,
1616                 const struct dc_plane_state *plane_state)
1617 {
1618         int j;
1619
1620         for (j = 0; j < MAX_PIPES; j++) {
1621                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1622
1623                 if (plane_state == pipe_ctx->plane_state) {
1624                         return true;
1625                 }
1626         }
1627
1628         return false;
1629 }
1630
1631 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1632 {
1633         union surface_update_flags *update_flags = &u->surface->update_flags;
1634         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1635
1636         if (!u->plane_info)
1637                 return UPDATE_TYPE_FAST;
1638
1639         if (u->plane_info->color_space != u->surface->color_space) {
1640                 update_flags->bits.color_space_change = 1;
1641                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1642         }
1643
1644         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1645                 update_flags->bits.horizontal_mirror_change = 1;
1646                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1647         }
1648
1649         if (u->plane_info->rotation != u->surface->rotation) {
1650                 update_flags->bits.rotation_change = 1;
1651                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1652         }
1653
1654         if (u->plane_info->format != u->surface->format) {
1655                 update_flags->bits.pixel_format_change = 1;
1656                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1657         }
1658
1659         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1660                 update_flags->bits.stereo_format_change = 1;
1661                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1662         }
1663
1664         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1665                 update_flags->bits.per_pixel_alpha_change = 1;
1666                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1667         }
1668
1669         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1670                 update_flags->bits.global_alpha_change = 1;
1671                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1672         }
1673
1674         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1675                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1676                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1677                 update_flags->bits.dcc_change = 1;
1678                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1679         }
1680
1681         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1682                         resource_pixel_format_to_bpp(u->surface->format)) {
1683                 /* different bytes per element will require full bandwidth
1684                  * and DML calculation
1685                  */
1686                 update_flags->bits.bpp_change = 1;
1687                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1688         }
1689
1690         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1691                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1692                 update_flags->bits.plane_size_change = 1;
1693                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1694         }
1695
1696
1697         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1698                         sizeof(union dc_tiling_info)) != 0) {
1699                 update_flags->bits.swizzle_change = 1;
1700                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1701
1702                 /* todo: below are HW dependent, we should add a hook to
1703                  * DCE/N resource and validated there.
1704                  */
1705                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1706                         /* swizzled mode requires RQ to be setup properly,
1707                          * thus need to run DML to calculate RQ settings
1708                          */
1709                         update_flags->bits.bandwidth_change = 1;
1710                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1711                 }
1712         }
1713
1714         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1715         return update_type;
1716 }
1717
1718 static enum surface_update_type get_scaling_info_update_type(
1719                 const struct dc_surface_update *u)
1720 {
1721         union surface_update_flags *update_flags = &u->surface->update_flags;
1722
1723         if (!u->scaling_info)
1724                 return UPDATE_TYPE_FAST;
1725
1726         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1727                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1728                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1729                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1730                         || u->scaling_info->scaling_quality.integer_scaling !=
1731                                 u->surface->scaling_quality.integer_scaling
1732                         ) {
1733                 update_flags->bits.scaling_change = 1;
1734
1735                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1736                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1737                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1738                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1739                         /* Making dst rect smaller requires a bandwidth change */
1740                         update_flags->bits.bandwidth_change = 1;
1741         }
1742
1743         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1744                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1745
1746                 update_flags->bits.scaling_change = 1;
1747                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1748                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1749                         /* Making src rect bigger requires a bandwidth change */
1750                         update_flags->bits.clock_change = 1;
1751         }
1752
1753         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1754                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1755                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1756                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1757                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1758                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1759                 update_flags->bits.position_change = 1;
1760
1761         if (update_flags->bits.clock_change
1762                         || update_flags->bits.bandwidth_change
1763                         || update_flags->bits.scaling_change)
1764                 return UPDATE_TYPE_FULL;
1765
1766         if (update_flags->bits.position_change)
1767                 return UPDATE_TYPE_MED;
1768
1769         return UPDATE_TYPE_FAST;
1770 }
1771
1772 static enum surface_update_type det_surface_update(const struct dc *dc,
1773                 const struct dc_surface_update *u)
1774 {
1775         const struct dc_state *context = dc->current_state;
1776         enum surface_update_type type;
1777         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1778         union surface_update_flags *update_flags = &u->surface->update_flags;
1779
1780         if (u->flip_addr)
1781                 update_flags->bits.addr_update = 1;
1782
1783         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1784                 update_flags->raw = 0xFFFFFFFF;
1785                 return UPDATE_TYPE_FULL;
1786         }
1787
1788         update_flags->raw = 0; // Reset all flags
1789
1790         type = get_plane_info_update_type(u);
1791         elevate_update_type(&overall_type, type);
1792
1793         type = get_scaling_info_update_type(u);
1794         elevate_update_type(&overall_type, type);
1795
1796         if (u->flip_addr)
1797                 update_flags->bits.addr_update = 1;
1798
1799         if (u->in_transfer_func)
1800                 update_flags->bits.in_transfer_func_change = 1;
1801
1802         if (u->input_csc_color_matrix)
1803                 update_flags->bits.input_csc_change = 1;
1804
1805         if (u->coeff_reduction_factor)
1806                 update_flags->bits.coeff_reduction_change = 1;
1807
1808         if (u->gamut_remap_matrix)
1809                 update_flags->bits.gamut_remap_change = 1;
1810
1811         if (u->gamma) {
1812                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1813
1814                 if (u->plane_info)
1815                         format = u->plane_info->format;
1816                 else if (u->surface)
1817                         format = u->surface->format;
1818
1819                 if (dce_use_lut(format))
1820                         update_flags->bits.gamma_change = 1;
1821         }
1822
1823         if (u->hdr_mult.value)
1824                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1825                         update_flags->bits.hdr_mult = 1;
1826                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1827                 }
1828
1829         if (update_flags->bits.in_transfer_func_change) {
1830                 type = UPDATE_TYPE_MED;
1831                 elevate_update_type(&overall_type, type);
1832         }
1833
1834         if (update_flags->bits.input_csc_change
1835                         || update_flags->bits.coeff_reduction_change
1836                         || update_flags->bits.gamma_change
1837                         || update_flags->bits.gamut_remap_change) {
1838                 type = UPDATE_TYPE_FULL;
1839                 elevate_update_type(&overall_type, type);
1840         }
1841
1842         return overall_type;
1843 }
1844
1845 static enum surface_update_type check_update_surfaces_for_stream(
1846                 struct dc *dc,
1847                 struct dc_surface_update *updates,
1848                 int surface_count,
1849                 struct dc_stream_update *stream_update,
1850                 const struct dc_stream_status *stream_status)
1851 {
1852         int i;
1853         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1854
1855 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1856         if (dc->idle_optimizations_allowed)
1857                 overall_type = UPDATE_TYPE_FULL;
1858
1859 #endif
1860         if (stream_status == NULL || stream_status->plane_count != surface_count)
1861                 overall_type = UPDATE_TYPE_FULL;
1862
1863         /* some stream updates require passive update */
1864         if (stream_update) {
1865                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1866
1867                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1868                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1869                         stream_update->integer_scaling_update)
1870                         su_flags->bits.scaling = 1;
1871
1872                 if (stream_update->out_transfer_func)
1873                         su_flags->bits.out_tf = 1;
1874
1875                 if (stream_update->abm_level)
1876                         su_flags->bits.abm_level = 1;
1877
1878                 if (stream_update->dpms_off)
1879                         su_flags->bits.dpms_off = 1;
1880
1881                 if (stream_update->gamut_remap)
1882                         su_flags->bits.gamut_remap = 1;
1883
1884                 if (stream_update->wb_update)
1885                         su_flags->bits.wb_update = 1;
1886
1887                 if (stream_update->dsc_config)
1888                         su_flags->bits.dsc_changed = 1;
1889
1890                 if (su_flags->raw != 0)
1891                         overall_type = UPDATE_TYPE_FULL;
1892
1893                 if (stream_update->output_csc_transform || stream_update->output_color_space)
1894                         su_flags->bits.out_csc = 1;
1895         }
1896
1897         for (i = 0 ; i < surface_count; i++) {
1898                 enum surface_update_type type =
1899                                 det_surface_update(dc, &updates[i]);
1900
1901                 elevate_update_type(&overall_type, type);
1902         }
1903
1904         return overall_type;
1905 }
1906
1907 /**
1908  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1909  *
1910  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1911  */
1912 enum surface_update_type dc_check_update_surfaces_for_stream(
1913                 struct dc *dc,
1914                 struct dc_surface_update *updates,
1915                 int surface_count,
1916                 struct dc_stream_update *stream_update,
1917                 const struct dc_stream_status *stream_status)
1918 {
1919         int i;
1920         enum surface_update_type type;
1921
1922         if (stream_update)
1923                 stream_update->stream->update_flags.raw = 0;
1924         for (i = 0; i < surface_count; i++)
1925                 updates[i].surface->update_flags.raw = 0;
1926
1927         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1928         if (type == UPDATE_TYPE_FULL) {
1929                 if (stream_update) {
1930                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
1931                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
1932                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
1933                 }
1934                 for (i = 0; i < surface_count; i++)
1935                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1936         }
1937
1938         if (type == UPDATE_TYPE_FAST) {
1939                 // If there's an available clock comparator, we use that.
1940                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
1941                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
1942                                 dc->optimized_required = true;
1943                 // Else we fallback to mem compare.
1944                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
1945                         dc->optimized_required = true;
1946                 }
1947
1948                 dc->optimized_required |= dc->wm_optimized_required;
1949         }
1950
1951         return type;
1952 }
1953
1954 static struct dc_stream_status *stream_get_status(
1955         struct dc_state *ctx,
1956         struct dc_stream_state *stream)
1957 {
1958         uint8_t i;
1959
1960         for (i = 0; i < ctx->stream_count; i++) {
1961                 if (stream == ctx->streams[i]) {
1962                         return &ctx->stream_status[i];
1963                 }
1964         }
1965
1966         return NULL;
1967 }
1968
1969 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1970
1971 static void copy_surface_update_to_plane(
1972                 struct dc_plane_state *surface,
1973                 struct dc_surface_update *srf_update)
1974 {
1975         if (srf_update->flip_addr) {
1976                 surface->address = srf_update->flip_addr->address;
1977                 surface->flip_immediate =
1978                         srf_update->flip_addr->flip_immediate;
1979                 surface->time.time_elapsed_in_us[surface->time.index] =
1980                         srf_update->flip_addr->flip_timestamp_in_us -
1981                                 surface->time.prev_update_time_in_us;
1982                 surface->time.prev_update_time_in_us =
1983                         srf_update->flip_addr->flip_timestamp_in_us;
1984                 surface->time.index++;
1985                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1986                         surface->time.index = 0;
1987
1988                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
1989         }
1990
1991         if (srf_update->scaling_info) {
1992                 surface->scaling_quality =
1993                                 srf_update->scaling_info->scaling_quality;
1994                 surface->dst_rect =
1995                                 srf_update->scaling_info->dst_rect;
1996                 surface->src_rect =
1997                                 srf_update->scaling_info->src_rect;
1998                 surface->clip_rect =
1999                                 srf_update->scaling_info->clip_rect;
2000         }
2001
2002         if (srf_update->plane_info) {
2003                 surface->color_space =
2004                                 srf_update->plane_info->color_space;
2005                 surface->format =
2006                                 srf_update->plane_info->format;
2007                 surface->plane_size =
2008                                 srf_update->plane_info->plane_size;
2009                 surface->rotation =
2010                                 srf_update->plane_info->rotation;
2011                 surface->horizontal_mirror =
2012                                 srf_update->plane_info->horizontal_mirror;
2013                 surface->stereo_format =
2014                                 srf_update->plane_info->stereo_format;
2015                 surface->tiling_info =
2016                                 srf_update->plane_info->tiling_info;
2017                 surface->visible =
2018                                 srf_update->plane_info->visible;
2019                 surface->per_pixel_alpha =
2020                                 srf_update->plane_info->per_pixel_alpha;
2021                 surface->global_alpha =
2022                                 srf_update->plane_info->global_alpha;
2023                 surface->global_alpha_value =
2024                                 srf_update->plane_info->global_alpha_value;
2025                 surface->dcc =
2026                                 srf_update->plane_info->dcc;
2027                 surface->layer_index =
2028                                 srf_update->plane_info->layer_index;
2029         }
2030
2031         if (srf_update->gamma &&
2032                         (surface->gamma_correction !=
2033                                         srf_update->gamma)) {
2034                 memcpy(&surface->gamma_correction->entries,
2035                         &srf_update->gamma->entries,
2036                         sizeof(struct dc_gamma_entries));
2037                 surface->gamma_correction->is_identity =
2038                         srf_update->gamma->is_identity;
2039                 surface->gamma_correction->num_entries =
2040                         srf_update->gamma->num_entries;
2041                 surface->gamma_correction->type =
2042                         srf_update->gamma->type;
2043         }
2044
2045         if (srf_update->in_transfer_func &&
2046                         (surface->in_transfer_func !=
2047                                 srf_update->in_transfer_func)) {
2048                 surface->in_transfer_func->sdr_ref_white_level =
2049                         srf_update->in_transfer_func->sdr_ref_white_level;
2050                 surface->in_transfer_func->tf =
2051                         srf_update->in_transfer_func->tf;
2052                 surface->in_transfer_func->type =
2053                         srf_update->in_transfer_func->type;
2054                 memcpy(&surface->in_transfer_func->tf_pts,
2055                         &srf_update->in_transfer_func->tf_pts,
2056                         sizeof(struct dc_transfer_func_distributed_points));
2057         }
2058
2059         if (srf_update->func_shaper &&
2060                         (surface->in_shaper_func !=
2061                         srf_update->func_shaper))
2062                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2063                 sizeof(*surface->in_shaper_func));
2064
2065         if (srf_update->lut3d_func &&
2066                         (surface->lut3d_func !=
2067                         srf_update->lut3d_func))
2068                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2069                 sizeof(*surface->lut3d_func));
2070
2071         if (srf_update->hdr_mult.value)
2072                 surface->hdr_mult =
2073                                 srf_update->hdr_mult;
2074
2075         if (srf_update->blend_tf &&
2076                         (surface->blend_tf !=
2077                         srf_update->blend_tf))
2078                 memcpy(surface->blend_tf, srf_update->blend_tf,
2079                 sizeof(*surface->blend_tf));
2080
2081         if (srf_update->input_csc_color_matrix)
2082                 surface->input_csc_color_matrix =
2083                         *srf_update->input_csc_color_matrix;
2084
2085         if (srf_update->coeff_reduction_factor)
2086                 surface->coeff_reduction_factor =
2087                         *srf_update->coeff_reduction_factor;
2088
2089         if (srf_update->gamut_remap_matrix)
2090                 surface->gamut_remap_matrix =
2091                         *srf_update->gamut_remap_matrix;
2092 }
2093
2094 static void copy_stream_update_to_stream(struct dc *dc,
2095                                          struct dc_state *context,
2096                                          struct dc_stream_state *stream,
2097                                          struct dc_stream_update *update)
2098 {
2099         struct dc_context *dc_ctx = dc->ctx;
2100
2101         if (update == NULL || stream == NULL)
2102                 return;
2103
2104         if (update->src.height && update->src.width)
2105                 stream->src = update->src;
2106
2107         if (update->dst.height && update->dst.width)
2108                 stream->dst = update->dst;
2109
2110         if (update->out_transfer_func &&
2111             stream->out_transfer_func != update->out_transfer_func) {
2112                 stream->out_transfer_func->sdr_ref_white_level =
2113                         update->out_transfer_func->sdr_ref_white_level;
2114                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2115                 stream->out_transfer_func->type =
2116                         update->out_transfer_func->type;
2117                 memcpy(&stream->out_transfer_func->tf_pts,
2118                        &update->out_transfer_func->tf_pts,
2119                        sizeof(struct dc_transfer_func_distributed_points));
2120         }
2121
2122         if (update->hdr_static_metadata)
2123                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2124
2125         if (update->abm_level)
2126                 stream->abm_level = *update->abm_level;
2127
2128         if (update->periodic_interrupt0)
2129                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2130
2131         if (update->periodic_interrupt1)
2132                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2133
2134         if (update->gamut_remap)
2135                 stream->gamut_remap_matrix = *update->gamut_remap;
2136
2137         /* Note: this being updated after mode set is currently not a use case
2138          * however if it arises OCSC would need to be reprogrammed at the
2139          * minimum
2140          */
2141         if (update->output_color_space)
2142                 stream->output_color_space = *update->output_color_space;
2143
2144         if (update->output_csc_transform)
2145                 stream->csc_color_matrix = *update->output_csc_transform;
2146
2147         if (update->vrr_infopacket)
2148                 stream->vrr_infopacket = *update->vrr_infopacket;
2149
2150         if (update->dpms_off)
2151                 stream->dpms_off = *update->dpms_off;
2152
2153         if (update->vsc_infopacket)
2154                 stream->vsc_infopacket = *update->vsc_infopacket;
2155
2156         if (update->vsp_infopacket)
2157                 stream->vsp_infopacket = *update->vsp_infopacket;
2158
2159         if (update->dither_option)
2160                 stream->dither_option = *update->dither_option;
2161         /* update current stream with writeback info */
2162         if (update->wb_update) {
2163                 int i;
2164
2165                 stream->num_wb_info = update->wb_update->num_wb_info;
2166                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2167                 for (i = 0; i < stream->num_wb_info; i++)
2168                         stream->writeback_info[i] =
2169                                 update->wb_update->writeback_info[i];
2170         }
2171         if (update->dsc_config) {
2172                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2173                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2174                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2175                                        update->dsc_config->num_slices_v != 0);
2176
2177                 /* Use temporarry context for validating new DSC config */
2178                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2179
2180                 if (dsc_validate_context) {
2181                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2182
2183                         stream->timing.dsc_cfg = *update->dsc_config;
2184                         stream->timing.flags.DSC = enable_dsc;
2185                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2186                                 stream->timing.dsc_cfg = old_dsc_cfg;
2187                                 stream->timing.flags.DSC = old_dsc_enabled;
2188                                 update->dsc_config = NULL;
2189                         }
2190
2191                         dc_release_state(dsc_validate_context);
2192                 } else {
2193                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2194                         update->dsc_config = NULL;
2195                 }
2196         }
2197 }
2198
2199 static void commit_planes_do_stream_update(struct dc *dc,
2200                 struct dc_stream_state *stream,
2201                 struct dc_stream_update *stream_update,
2202                 enum surface_update_type update_type,
2203                 struct dc_state *context)
2204 {
2205         int j;
2206         bool should_program_abm;
2207
2208         // Stream updates
2209         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2210                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2211
2212                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2213
2214                         if (stream_update->periodic_interrupt0 &&
2215                                         dc->hwss.setup_periodic_interrupt)
2216                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2217
2218                         if (stream_update->periodic_interrupt1 &&
2219                                         dc->hwss.setup_periodic_interrupt)
2220                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2221
2222                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2223                                         stream_update->vrr_infopacket ||
2224                                         stream_update->vsc_infopacket ||
2225                                         stream_update->vsp_infopacket) {
2226                                 resource_build_info_frame(pipe_ctx);
2227                                 dc->hwss.update_info_frame(pipe_ctx);
2228                         }
2229
2230                         if (stream_update->hdr_static_metadata &&
2231                                         stream->use_dynamic_meta &&
2232                                         dc->hwss.set_dmdata_attributes &&
2233                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2234                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2235
2236                         if (stream_update->gamut_remap)
2237                                 dc_stream_set_gamut_remap(dc, stream);
2238
2239                         if (stream_update->output_csc_transform)
2240                                 dc_stream_program_csc_matrix(dc, stream);
2241
2242                         if (stream_update->dither_option) {
2243                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2244                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2245                                                                         &pipe_ctx->stream->bit_depth_params);
2246                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2247                                                 &stream->bit_depth_params,
2248                                                 &stream->clamping);
2249                                 while (odm_pipe) {
2250                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2251                                                         &stream->bit_depth_params,
2252                                                         &stream->clamping);
2253                                         odm_pipe = odm_pipe->next_odm_pipe;
2254                                 }
2255                         }
2256
2257                         /* Full fe update*/
2258                         if (update_type == UPDATE_TYPE_FAST)
2259                                 continue;
2260
2261                         if (stream_update->dsc_config)
2262                                 dp_update_dsc_config(pipe_ctx);
2263
2264                         if (stream_update->dpms_off) {
2265                                 if (*stream_update->dpms_off) {
2266                                         core_link_disable_stream(pipe_ctx);
2267                                         /* for dpms, keep acquired resources*/
2268                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2269                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2270
2271                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2272                                 } else {
2273                                         if (dc->optimize_seamless_boot_streams == 0)
2274                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2275
2276                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2277                                 }
2278                         }
2279
2280                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2281                                 should_program_abm = true;
2282
2283                                 // if otg funcs defined check if blanked before programming
2284                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2285                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2286                                                 should_program_abm = false;
2287
2288                                 if (should_program_abm) {
2289                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2290                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2291                                         } else {
2292                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2293                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2294                                         }
2295                                 }
2296                         }
2297                 }
2298         }
2299 }
2300
2301 static void commit_planes_for_stream(struct dc *dc,
2302                 struct dc_surface_update *srf_updates,
2303                 int surface_count,
2304                 struct dc_stream_state *stream,
2305                 struct dc_stream_update *stream_update,
2306                 enum surface_update_type update_type,
2307                 struct dc_state *context)
2308 {
2309         bool mpcc_disconnected = false;
2310         int i, j;
2311         struct pipe_ctx *top_pipe_to_program = NULL;
2312
2313         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2314                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2315                  * first flip. After first flip, optimization is required to lower
2316                  * bandwidth. Important to note that it is expected UEFI will
2317                  * only light up a single display on POST, therefore we only expect
2318                  * one stream with seamless boot flag set.
2319                  */
2320                 if (stream->apply_seamless_boot_optimization) {
2321                         stream->apply_seamless_boot_optimization = false;
2322                         dc->optimize_seamless_boot_streams--;
2323
2324                         if (dc->optimize_seamless_boot_streams == 0)
2325                                 dc->optimized_required = true;
2326                 }
2327         }
2328
2329         if (update_type == UPDATE_TYPE_FULL) {
2330 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2331                 dc_allow_idle_optimizations(dc, false);
2332
2333 #endif
2334                 if (dc->optimize_seamless_boot_streams == 0)
2335                         dc->hwss.prepare_bandwidth(dc, context);
2336
2337                 context_clock_trace(dc, context);
2338         }
2339
2340         if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
2341                 dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
2342                 dc->hwss.interdependent_update_lock(dc, context, true);
2343                 mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
2344                 dc->hwss.interdependent_update_lock(dc, context, false);
2345                 if (mpcc_disconnected)
2346                         dc->hwss.wait_for_pending_cleared(dc, context);
2347         }
2348
2349         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2350                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2351
2352                 if (!pipe_ctx->top_pipe &&
2353                         !pipe_ctx->prev_odm_pipe &&
2354                         pipe_ctx->stream &&
2355                         pipe_ctx->stream == stream) {
2356                         top_pipe_to_program = pipe_ctx;
2357                 }
2358         }
2359
2360         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2361                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2362                         if (should_use_dmub_lock(stream->link)) {
2363                                 union dmub_hw_lock_flags hw_locks = { 0 };
2364                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2365
2366                                 hw_locks.bits.lock_dig = 1;
2367                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2368
2369                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2370                                                         true,
2371                                                         &hw_locks,
2372                                                         &inst_flags);
2373                         } else
2374                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2375                                                 top_pipe_to_program->stream_res.tg);
2376                 }
2377
2378         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2379                 dc->hwss.interdependent_update_lock(dc, context, true);
2380         else
2381                 /* Lock the top pipe while updating plane addrs, since freesync requires
2382                  *  plane addr update event triggers to be synchronized.
2383                  *  top_pipe_to_program is expected to never be NULL
2384                  */
2385                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2386
2387
2388         // Stream updates
2389         if (stream_update)
2390                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2391
2392         if (surface_count == 0) {
2393                 /*
2394                  * In case of turning off screen, no need to program front end a second time.
2395                  * just return after program blank.
2396                  */
2397                 if (dc->hwss.apply_ctx_for_surface)
2398                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2399                 if (dc->hwss.program_front_end_for_ctx)
2400                         dc->hwss.program_front_end_for_ctx(dc, context);
2401
2402                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2403                         dc->hwss.interdependent_update_lock(dc, context, false);
2404                 else
2405                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2406
2407                 dc->hwss.post_unlock_program_front_end(dc, context);
2408                 return;
2409         }
2410
2411         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2412                 for (i = 0; i < surface_count; i++) {
2413                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2414                         /*set logical flag for lock/unlock use*/
2415                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2416                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2417                                 if (!pipe_ctx->plane_state)
2418                                         continue;
2419                                 if (pipe_ctx->plane_state != plane_state)
2420                                         continue;
2421                                 plane_state->triplebuffer_flips = false;
2422                                 if (update_type == UPDATE_TYPE_FAST &&
2423                                         dc->hwss.program_triplebuffer != NULL &&
2424                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2425                                                 /*triple buffer for VUpdate  only*/
2426                                                 plane_state->triplebuffer_flips = true;
2427                                 }
2428                         }
2429                 }
2430         }
2431
2432         // Update Type FULL, Surface updates
2433         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2434                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2435
2436                 if (!pipe_ctx->top_pipe &&
2437                         !pipe_ctx->prev_odm_pipe &&
2438                         pipe_ctx->stream &&
2439                         pipe_ctx->stream == stream) {
2440                         struct dc_stream_status *stream_status = NULL;
2441
2442                         if (!pipe_ctx->plane_state)
2443                                 continue;
2444
2445                         /* Full fe update*/
2446                         if (update_type == UPDATE_TYPE_FAST)
2447                                 continue;
2448
2449                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2450
2451                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2452                                 /*turn off triple buffer for full update*/
2453                                 dc->hwss.program_triplebuffer(
2454                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2455                         }
2456                         stream_status =
2457                                 stream_get_status(context, pipe_ctx->stream);
2458
2459                         if (dc->hwss.apply_ctx_for_surface)
2460                                 dc->hwss.apply_ctx_for_surface(
2461                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2462                 }
2463         }
2464         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2465                 dc->hwss.program_front_end_for_ctx(dc, context);
2466 #ifdef CONFIG_DRM_AMD_DC_DCN
2467                 if (dc->debug.validate_dml_output) {
2468                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2469                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2470                                 if (cur_pipe.stream == NULL)
2471                                         continue;
2472
2473                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2474                                                 cur_pipe.plane_res.hubp, dc->ctx,
2475                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2476                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2477                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2478                         }
2479                 }
2480 #endif
2481         }
2482
2483         // Update Type FAST, Surface updates
2484         if (update_type == UPDATE_TYPE_FAST) {
2485                 if (dc->hwss.set_flip_control_gsl)
2486                         for (i = 0; i < surface_count; i++) {
2487                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2488
2489                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2490                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2491
2492                                         if (pipe_ctx->stream != stream)
2493                                                 continue;
2494
2495                                         if (pipe_ctx->plane_state != plane_state)
2496                                                 continue;
2497
2498                                         // GSL has to be used for flip immediate
2499                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2500                                                         plane_state->flip_immediate);
2501                                 }
2502                         }
2503                 /* Perform requested Updates */
2504                 for (i = 0; i < surface_count; i++) {
2505                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2506
2507                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2508                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2509
2510                                 if (pipe_ctx->stream != stream)
2511                                         continue;
2512
2513                                 if (pipe_ctx->plane_state != plane_state)
2514                                         continue;
2515                                 /*program triple buffer after lock based on flip type*/
2516                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2517                                         /*only enable triplebuffer for  fast_update*/
2518                                         dc->hwss.program_triplebuffer(
2519                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2520                                 }
2521                                 if (srf_updates[i].flip_addr)
2522                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2523                         }
2524                 }
2525         }
2526
2527         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2528                 dc->hwss.interdependent_update_lock(dc, context, false);
2529         else
2530                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2531
2532         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2533                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2534                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2535                                         top_pipe_to_program->stream_res.tg,
2536                                         CRTC_STATE_VACTIVE);
2537                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2538                                         top_pipe_to_program->stream_res.tg,
2539                                         CRTC_STATE_VBLANK);
2540                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2541                                         top_pipe_to_program->stream_res.tg,
2542                                         CRTC_STATE_VACTIVE);
2543
2544                         if (stream && should_use_dmub_lock(stream->link)) {
2545                                 union dmub_hw_lock_flags hw_locks = { 0 };
2546                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2547
2548                                 hw_locks.bits.lock_dig = 1;
2549                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2550
2551                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2552                                                         false,
2553                                                         &hw_locks,
2554                                                         &inst_flags);
2555                         } else
2556                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2557                                         top_pipe_to_program->stream_res.tg);
2558                 }
2559
2560         if (update_type != UPDATE_TYPE_FAST)
2561                 dc->hwss.post_unlock_program_front_end(dc, context);
2562
2563         // Fire manual trigger only when bottom plane is flipped
2564         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2565                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2566
2567                 if (pipe_ctx->bottom_pipe ||
2568                                 !pipe_ctx->stream ||
2569                                 pipe_ctx->stream != stream ||
2570                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2571                         continue;
2572
2573                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2574                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2575         }
2576 }
2577
2578 void dc_commit_updates_for_stream(struct dc *dc,
2579                 struct dc_surface_update *srf_updates,
2580                 int surface_count,
2581                 struct dc_stream_state *stream,
2582                 struct dc_stream_update *stream_update,
2583                 struct dc_state *state)
2584 {
2585         const struct dc_stream_status *stream_status;
2586         enum surface_update_type update_type;
2587         struct dc_state *context;
2588         struct dc_context *dc_ctx = dc->ctx;
2589         int i, j;
2590
2591         stream_status = dc_stream_get_status(stream);
2592         context = dc->current_state;
2593
2594         update_type = dc_check_update_surfaces_for_stream(
2595                                 dc, srf_updates, surface_count, stream_update, stream_status);
2596
2597         if (update_type >= update_surface_trace_level)
2598                 update_surface_trace(dc, srf_updates, surface_count);
2599
2600
2601         if (update_type >= UPDATE_TYPE_FULL) {
2602
2603                 /* initialize scratch memory for building context */
2604                 context = dc_create_state(dc);
2605                 if (context == NULL) {
2606                         DC_ERROR("Failed to allocate new validate context!\n");
2607                         return;
2608                 }
2609
2610                 dc_resource_state_copy_construct(state, context);
2611
2612                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2613                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2614                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2615
2616                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2617                                 new_pipe->plane_state->force_full_update = true;
2618                 }
2619         }
2620
2621
2622         for (i = 0; i < surface_count; i++) {
2623                 struct dc_plane_state *surface = srf_updates[i].surface;
2624
2625                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2626
2627                 if (update_type >= UPDATE_TYPE_MED) {
2628                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2629                                 struct pipe_ctx *pipe_ctx =
2630                                         &context->res_ctx.pipe_ctx[j];
2631
2632                                 if (pipe_ctx->plane_state != surface)
2633                                         continue;
2634
2635                                 resource_build_scaling_params(pipe_ctx);
2636                         }
2637                 }
2638         }
2639
2640         copy_stream_update_to_stream(dc, context, stream, stream_update);
2641
2642         if (update_type >= UPDATE_TYPE_FULL) {
2643                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2644                         DC_ERROR("Mode validation failed for stream update!\n");
2645                         dc_release_state(context);
2646                         return;
2647                 }
2648         }
2649
2650         commit_planes_for_stream(
2651                                 dc,
2652                                 srf_updates,
2653                                 surface_count,
2654                                 stream,
2655                                 stream_update,
2656                                 update_type,
2657                                 context);
2658         /*update current_State*/
2659         if (dc->current_state != context) {
2660
2661                 struct dc_state *old = dc->current_state;
2662
2663                 dc->current_state = context;
2664                 dc_release_state(old);
2665
2666                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2667                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2668
2669                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2670                                 pipe_ctx->plane_state->force_full_update = false;
2671                 }
2672         }
2673         /*let's use current_state to update watermark etc*/
2674         if (update_type >= UPDATE_TYPE_FULL)
2675                 dc_post_update_surfaces_to_stream(dc);
2676
2677         return;
2678
2679 }
2680
2681 uint8_t dc_get_current_stream_count(struct dc *dc)
2682 {
2683         return dc->current_state->stream_count;
2684 }
2685
2686 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2687 {
2688         if (i < dc->current_state->stream_count)
2689                 return dc->current_state->streams[i];
2690         return NULL;
2691 }
2692
2693 enum dc_irq_source dc_interrupt_to_irq_source(
2694                 struct dc *dc,
2695                 uint32_t src_id,
2696                 uint32_t ext_id)
2697 {
2698         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2699 }
2700
2701 /**
2702  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2703  */
2704 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2705 {
2706
2707         if (dc == NULL)
2708                 return false;
2709
2710         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2711 }
2712
2713 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2714 {
2715         dal_irq_service_ack(dc->res_pool->irqs, src);
2716 }
2717
2718 void dc_power_down_on_boot(struct dc *dc)
2719 {
2720         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
2721                         dc->hwss.power_down_on_boot)
2722                 dc->hwss.power_down_on_boot(dc);
2723 }
2724
2725 void dc_set_power_state(
2726         struct dc *dc,
2727         enum dc_acpi_cm_power_state power_state)
2728 {
2729         struct kref refcount;
2730         struct display_mode_lib *dml;
2731
2732         switch (power_state) {
2733         case DC_ACPI_CM_POWER_STATE_D0:
2734                 dc_resource_state_construct(dc, dc->current_state);
2735
2736                 if (dc->ctx->dmub_srv)
2737                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2738
2739                 dc->hwss.init_hw(dc);
2740
2741                 if (dc->hwss.init_sys_ctx != NULL &&
2742                         dc->vm_pa_config.valid) {
2743                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2744                 }
2745
2746                 break;
2747         default:
2748                 ASSERT(dc->current_state->stream_count == 0);
2749                 /* Zero out the current context so that on resume we start with
2750                  * clean state, and dc hw programming optimizations will not
2751                  * cause any trouble.
2752                  */
2753                 dml = kzalloc(sizeof(struct display_mode_lib),
2754                                 GFP_KERNEL);
2755
2756                 ASSERT(dml);
2757                 if (!dml)
2758                         return;
2759
2760                 /* Preserve refcount */
2761                 refcount = dc->current_state->refcount;
2762                 /* Preserve display mode lib */
2763                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2764
2765                 dc_resource_state_destruct(dc->current_state);
2766                 memset(dc->current_state, 0,
2767                                 sizeof(*dc->current_state));
2768
2769                 dc->current_state->refcount = refcount;
2770                 dc->current_state->bw_ctx.dml = *dml;
2771
2772                 kfree(dml);
2773
2774                 break;
2775         }
2776 }
2777
2778 void dc_resume(struct dc *dc)
2779 {
2780         uint32_t i;
2781
2782         for (i = 0; i < dc->link_count; i++)
2783                 core_link_resume(dc->links[i]);
2784 }
2785
2786 bool dc_is_dmcu_initialized(struct dc *dc)
2787 {
2788         struct dmcu *dmcu = dc->res_pool->dmcu;
2789
2790         if (dmcu)
2791                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2792         return false;
2793 }
2794
2795 bool dc_submit_i2c(
2796                 struct dc *dc,
2797                 uint32_t link_index,
2798                 struct i2c_command *cmd)
2799 {
2800
2801         struct dc_link *link = dc->links[link_index];
2802         struct ddc_service *ddc = link->ddc;
2803         return dce_i2c_submit_command(
2804                 dc->res_pool,
2805                 ddc->ddc_pin,
2806                 cmd);
2807 }
2808
2809 bool dc_submit_i2c_oem(
2810                 struct dc *dc,
2811                 struct i2c_command *cmd)
2812 {
2813         struct ddc_service *ddc = dc->res_pool->oem_device;
2814         return dce_i2c_submit_command(
2815                 dc->res_pool,
2816                 ddc->ddc_pin,
2817                 cmd);
2818 }
2819
2820 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2821 {
2822         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2823                 BREAK_TO_DEBUGGER();
2824                 return false;
2825         }
2826
2827         dc_sink_retain(sink);
2828
2829         dc_link->remote_sinks[dc_link->sink_count] = sink;
2830         dc_link->sink_count++;
2831
2832         return true;
2833 }
2834
2835 /**
2836  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2837  *
2838  * EDID length is in bytes
2839  */
2840 struct dc_sink *dc_link_add_remote_sink(
2841                 struct dc_link *link,
2842                 const uint8_t *edid,
2843                 int len,
2844                 struct dc_sink_init_data *init_data)
2845 {
2846         struct dc_sink *dc_sink;
2847         enum dc_edid_status edid_status;
2848
2849         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2850                 dm_error("Max EDID buffer size breached!\n");
2851                 return NULL;
2852         }
2853
2854         if (!init_data) {
2855                 BREAK_TO_DEBUGGER();
2856                 return NULL;
2857         }
2858
2859         if (!init_data->link) {
2860                 BREAK_TO_DEBUGGER();
2861                 return NULL;
2862         }
2863
2864         dc_sink = dc_sink_create(init_data);
2865
2866         if (!dc_sink)
2867                 return NULL;
2868
2869         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2870         dc_sink->dc_edid.length = len;
2871
2872         if (!link_add_remote_sink_helper(
2873                         link,
2874                         dc_sink))
2875                 goto fail_add_sink;
2876
2877         edid_status = dm_helpers_parse_edid_caps(
2878                         link->ctx,
2879                         &dc_sink->dc_edid,
2880                         &dc_sink->edid_caps);
2881
2882         /*
2883          * Treat device as no EDID device if EDID
2884          * parsing fails
2885          */
2886         if (edid_status != EDID_OK) {
2887                 dc_sink->dc_edid.length = 0;
2888                 dm_error("Bad EDID, status%d!\n", edid_status);
2889         }
2890
2891         return dc_sink;
2892
2893 fail_add_sink:
2894         dc_sink_release(dc_sink);
2895         return NULL;
2896 }
2897
2898 /**
2899  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2900  *
2901  * Note that this just removes the struct dc_sink - it doesn't
2902  * program hardware or alter other members of dc_link
2903  */
2904 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2905 {
2906         int i;
2907
2908         if (!link->sink_count) {
2909                 BREAK_TO_DEBUGGER();
2910                 return;
2911         }
2912
2913         for (i = 0; i < link->sink_count; i++) {
2914                 if (link->remote_sinks[i] == sink) {
2915                         dc_sink_release(sink);
2916                         link->remote_sinks[i] = NULL;
2917
2918                         /* shrink array to remove empty place */
2919                         while (i < link->sink_count - 1) {
2920                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2921                                 i++;
2922                         }
2923                         link->remote_sinks[i] = NULL;
2924                         link->sink_count--;
2925                         return;
2926                 }
2927         }
2928 }
2929
2930 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2931 {
2932         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2933         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2934         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2935         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2936         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
2937         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
2938         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
2939         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
2940         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
2941 }
2942 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
2943 {
2944         if (dc->hwss.set_clock)
2945                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
2946         return DC_ERROR_UNEXPECTED;
2947 }
2948 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
2949 {
2950         if (dc->hwss.get_clock)
2951                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
2952 }
2953
2954 /* enable/disable eDP PSR without specify stream for eDP */
2955 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
2956 {
2957         int i;
2958
2959         for (i = 0; i < dc->current_state->stream_count ; i++) {
2960                 struct dc_link *link;
2961                 struct dc_stream_state *stream = dc->current_state->streams[i];
2962
2963                 link = stream->link;
2964                 if (!link)
2965                         continue;
2966
2967                 if (link->psr_settings.psr_feature_enabled) {
2968                         if (enable && !link->psr_settings.psr_allow_active)
2969                                 return dc_link_set_psr_allow_active(link, true, false);
2970                         else if (!enable && link->psr_settings.psr_allow_active)
2971                                 return dc_link_set_psr_allow_active(link, false, false);
2972                 }
2973         }
2974
2975         return true;
2976 }
2977
2978 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2979
2980 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
2981 {
2982         if (dc->debug.disable_idle_power_optimizations)
2983                 return;
2984
2985         if (allow == dc->idle_optimizations_allowed)
2986                 return;
2987
2988         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
2989                 dc->idle_optimizations_allowed = allow;
2990 }
2991
2992 /*
2993  * blank all streams, and set min and max memory clock to
2994  * lowest and highest DPM level, respectively
2995  */
2996 void dc_unlock_memory_clock_frequency(struct dc *dc)
2997 {
2998         unsigned int i;
2999
3000         for (i = 0; i < MAX_PIPES; i++)
3001                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3002                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3003
3004         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3005         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3006 }
3007
3008 /*
3009  * set min memory clock to the min required for current mode,
3010  * max to maxDPM, and unblank streams
3011  */
3012 void dc_lock_memory_clock_frequency(struct dc *dc)
3013 {
3014         unsigned int i;
3015
3016         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3017         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3018         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3019
3020         for (i = 0; i < MAX_PIPES; i++)
3021                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3022                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3023 }
3024 #endif