drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #include "dmub/dmub_srv.h"
  70
  71 #include "dce/dmub_hw_lock_mgr.h"
  72
  73 #define CTX \
  74         dc->ctx
  75
  76 #define DC_LOGGER \
  77         dc->ctx->logger
  78
  79 static const char DC_BUILD_ID[] = "production-build";
  80
  81 /**
  82  * DOC: Overview
  83  *
  84  * DC is the OS-agnostic component of the amdgpu DC driver.
  85  *
  86  * DC maintains and validates a set of structs representing the state of the
  87  * driver and writes that state to AMD hardware
  88  *
  89  * Main DC HW structs:
  90  *
  91  * struct dc - The central struct.  One per driver.  Created on driver load,
  92  * destroyed on driver unload.
  93  *
  94  * struct dc_context - One per driver.
  95  * Used as a backpointer by most other structs in dc.
  96  *
  97  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  98  * plugpoints).  Created on driver load, destroyed on driver unload.
  99  *
 100  * struct dc_sink - One per display.  Created on boot or hotplug.
 101  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 102  * (the display directly attached).  It may also have one or more remote
 103  * sinks (in the Multi-Stream Transport case)
 104  *
 105  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 106  * main pipeline.  Not directly accessible by dm.
 107  *
 108  * Main dc state structs:
 109  *
 110  * These structs can be created and destroyed as needed.  There is a full set of
 111  * these structs in dc->current_state representing the currently programmed state.
 112  *
 113  * struct dc_state - The global DC state to track global state information,
 114  * such as bandwidth values.
 115  *
 116  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 117  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 118  *
 119  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 120  * and may have more in the Multi-Plane Overlay case.
 121  *
 122  * struct resource_context - Represents the programmable state of everything in
 123  * the resource_pool.  Not directly accessible by dm.
 124  *
 125  * struct pipe_ctx - A member of struct resource_context.  Represents the
 126  * internal hardware pipeline components.  Each dc_plane_state has either
 127  * one or two (in the pipe-split case).
 128  */
 129
 130 /*******************************************************************************
 131  * Private functions
 132  ******************************************************************************/
 133
 134 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 135 {
 136         if (new > *original)
 137                 *original = new;
 138 }
 139
 140 static void destroy_links(struct dc *dc)
 141 {
 142         uint32_t i;
 143
 144         for (i = 0; i < dc->link_count; i++) {
 145                 if (NULL != dc->links[i])
 146                         link_destroy(&dc->links[i]);
 147         }
 148 }
 149
 150 static bool create_links(
 151                 struct dc *dc,
 152                 uint32_t num_virtual_links)
 153 {
 154         int i;
 155         int connectors_num;
 156         struct dc_bios *bios = dc->ctx->dc_bios;
 157
 158         dc->link_count = 0;
 159
 160         connectors_num = bios->funcs->get_connectors_number(bios);
 161
 162         if (connectors_num > ENUM_ID_COUNT) {
 163                 dm_error(
 164                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 165                         connectors_num,
 166                         ENUM_ID_COUNT);
 167                 return false;
 168         }
 169
 170         dm_output_to_console(
 171                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 172                 __func__,
 173                 connectors_num,
 174                 num_virtual_links);
 175
 176         for (i = 0; i < connectors_num; i++) {
 177                 struct link_init_data link_init_params = {0};
 178                 struct dc_link *link;
 179
 180                 link_init_params.ctx = dc->ctx;
 181                 /* next BIOS object table connector */
 182                 link_init_params.connector_index = i;
 183                 link_init_params.link_index = dc->link_count;
 184                 link_init_params.dc = dc;
 185                 link = link_create(&link_init_params);
 186
 187                 if (link) {
 188                         bool should_destory_link = false;
 189
 190                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 191                                 if (dc->config.edp_not_connected) {
 192                                         if (!IS_DIAG_DC(dc->ctx->dce_environment))
 193                                                 should_destory_link = true;
 194                                 } else {
 195                                         enum dc_connection_type type;
 196                                         dc_link_detect_sink(link, &type);
 197                                         if (type == dc_connection_none)
 198                                                 should_destory_link = true;
 199                                 }
 200                         }
 201
 202                         if (dc->config.force_enum_edp || !should_destory_link) {
 203                                 dc->links[dc->link_count] = link;
 204                                 link->dc = dc;
 205                                 ++dc->link_count;
 206                         } else {
 207                                 link_destroy(&link);
 208                         }
 209                 }
 210         }
 211
 212         for (i = 0; i < num_virtual_links; i++) {
 213                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 214                 struct encoder_init_data enc_init = {0};
 215
 216                 if (link == NULL) {
 217                         BREAK_TO_DEBUGGER();
 218                         goto failed_alloc;
 219                 }
 220
 221                 link->link_index = dc->link_count;
 222                 dc->links[dc->link_count] = link;
 223                 dc->link_count++;
 224
 225                 link->ctx = dc->ctx;
 226                 link->dc = dc;
 227                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 228                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 229                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 230                 link->link_id.enum_id = ENUM_ID_1;
 231                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 232
 233                 if (!link->link_enc) {
 234                         BREAK_TO_DEBUGGER();
 235                         goto failed_alloc;
 236                 }
 237
 238                 link->link_status.dpcd_caps = &link->dpcd_caps;
 239
 240                 enc_init.ctx = dc->ctx;
 241                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 242                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 243                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 244                 enc_init.connector = link->link_id;
 245                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 246                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 247                 enc_init.encoder.enum_id = ENUM_ID_1;
 248                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 249         }
 250
 251         return true;
 252
 253 failed_alloc:
 254         return false;
 255 }
 256
 257 static struct dc_perf_trace *dc_perf_trace_create(void)
 258 {
 259         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 260 }
 261
 262 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 263 {
 264         kfree(*perf_trace);
 265         *perf_trace = NULL;
 266 }
 267
 268 /**
 269  *****************************************************************************
 270  *  Function: dc_stream_adjust_vmin_vmax
 271  *
 272  *  @brief
 273  *     Looks up the pipe context of dc_stream_state and updates the
 274  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 275  *     Rate, which is a power-saving feature that targets reducing panel
 276  *     refresh rate while the screen is static
 277  *
 278  *  @param [in] dc: dc reference
 279  *  @param [in] stream: Initial dc stream state
 280  *  @param [in] adjust: Updated parameters for vertical_total_min and
 281  *  vertical_total_max
 282  *****************************************************************************
 283  */
 284 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 285                 struct dc_stream_state *stream,
 286                 struct dc_crtc_timing_adjust *adjust)
 287 {
 288         int i = 0;
 289         bool ret = false;
 290
 291         stream->adjust = *adjust;
 292
 293         for (i = 0; i < MAX_PIPES; i++) {
 294                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 295
 296                 if (pipe->stream == stream && pipe->stream_res.tg) {
 297                         dc->hwss.set_drr(&pipe,
 298                                         1,
 299                                         adjust->v_total_min,
 300                                         adjust->v_total_max,
 301                                         adjust->v_total_mid,
 302                                         adjust->v_total_mid_frame_num);
 303
 304                         ret = true;
 305                 }
 306         }
 307         return ret;
 308 }
 309
 310 bool dc_stream_get_crtc_position(struct dc *dc,
 311                 struct dc_stream_state **streams, int num_streams,
 312                 unsigned int *v_pos, unsigned int *nom_v_pos)
 313 {
 314         /* TODO: Support multiple streams */
 315         const struct dc_stream_state *stream = streams[0];
 316         int i = 0;
 317         bool ret = false;
 318         struct crtc_position position;
 319
 320         for (i = 0; i < MAX_PIPES; i++) {
 321                 struct pipe_ctx *pipe =
 322                                 &dc->current_state->res_ctx.pipe_ctx[i];
 323
 324                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 325                         dc->hwss.get_position(&pipe, 1, &position);
 326
 327                         *v_pos = position.vertical_count;
 328                         *nom_v_pos = position.nominal_vcount;
 329                         ret = true;
 330                 }
 331         }
 332         return ret;
 333 }
 334
 335 /**
 336  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 337  * @dc: DC Object
 338  * @stream: The stream to configure CRC on.
 339  * @enable: Enable CRC if true, disable otherwise.
 340  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 341  *              once.
 342  *
 343  * By default, only CRC0 is configured, and the entire frame is used to
 344  * calculate the crc.
 345  */
 346 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 347                              bool enable, bool continuous)
 348 {
 349         int i;
 350         struct pipe_ctx *pipe;
 351         struct crc_params param;
 352         struct timing_generator *tg;
 353
 354         for (i = 0; i < MAX_PIPES; i++) {
 355                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 356                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 357                         break;
 358         }
 359         /* Stream not found */
 360         if (i == MAX_PIPES)
 361                 return false;
 362
 363         /* Always capture the full frame */
 364         param.windowa_x_start = 0;
 365         param.windowa_y_start = 0;
 366         param.windowa_x_end = pipe->stream->timing.h_addressable;
 367         param.windowa_y_end = pipe->stream->timing.v_addressable;
 368         param.windowb_x_start = 0;
 369         param.windowb_y_start = 0;
 370         param.windowb_x_end = pipe->stream->timing.h_addressable;
 371         param.windowb_y_end = pipe->stream->timing.v_addressable;
 372
 373         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 374         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 375
 376         /* Default to the union of both windows */
 377         param.selection = UNION_WINDOW_A_B;
 378         param.continuous_mode = continuous;
 379         param.enable = enable;
 380
 381         tg = pipe->stream_res.tg;
 382
 383         /* Only call if supported */
 384         if (tg->funcs->configure_crc)
 385                 return tg->funcs->configure_crc(tg, &param);
 386         DC_LOG_WARNING("CRC capture not supported.");
 387         return false;
 388 }
 389
 390 /**
 391  * dc_stream_get_crc() - Get CRC values for the given stream.
 392  * @dc: DC object
 393  * @stream: The DC stream state of the stream to get CRCs from.
 394  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 395  *
 396  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 397  * Return false if stream is not found, or if CRCs are not enabled.
 398  */
 399 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 400                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 401 {
 402         int i;
 403         struct pipe_ctx *pipe;
 404         struct timing_generator *tg;
 405
 406         for (i = 0; i < MAX_PIPES; i++) {
 407                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 408                 if (pipe->stream == stream)
 409                         break;
 410         }
 411         /* Stream not found */
 412         if (i == MAX_PIPES)
 413                 return false;
 414
 415         tg = pipe->stream_res.tg;
 416
 417         if (tg->funcs->get_crc)
 418                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 419         DC_LOG_WARNING("CRC capture not supported.");
 420         return false;
 421 }
 422
 423 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 424                 enum dc_dynamic_expansion option)
 425 {
 426         /* OPP FMT dyn expansion updates*/
 427         int i = 0;
 428         struct pipe_ctx *pipe_ctx;
 429
 430         for (i = 0; i < MAX_PIPES; i++) {
 431                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 432                                 == stream) {
 433                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 434                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 435                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 436                                         pipe_ctx->stream_res.opp,
 437                                         COLOR_SPACE_YCBCR601,
 438                                         stream->timing.display_color_depth,
 439                                         stream->signal);
 440                 }
 441         }
 442 }
 443
 444 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 445                 enum dc_dither_option option)
 446 {
 447         struct bit_depth_reduction_params params;
 448         struct dc_link *link = stream->link;
 449         struct pipe_ctx *pipes = NULL;
 450         int i;
 451
 452         for (i = 0; i < MAX_PIPES; i++) {
 453                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 454                                 stream) {
 455                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 456                         break;
 457                 }
 458         }
 459
 460         if (!pipes)
 461                 return;
 462         if (option > DITHER_OPTION_MAX)
 463                 return;
 464
 465         stream->dither_option = option;
 466
 467         memset(&params, 0, sizeof(params));
 468         resource_build_bit_depth_reduction_params(stream, &params);
 469         stream->bit_depth_params = params;
 470
 471         if (pipes->plane_res.xfm &&
 472             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 473                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 474                         pipes->plane_res.xfm,
 475                         pipes->plane_res.scl_data.lb_params.depth,
 476                         &stream->bit_depth_params);
 477         }
 478
 479         pipes->stream_res.opp->funcs->
 480                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 481 }
 482
 483 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 484 {
 485         int i = 0;
 486         bool ret = false;
 487         struct pipe_ctx *pipes;
 488
 489         for (i = 0; i < MAX_PIPES; i++) {
 490                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 491                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 492                         dc->hwss.program_gamut_remap(pipes);
 493                         ret = true;
 494                 }
 495         }
 496
 497         return ret;
 498 }
 499
 500 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 501 {
 502         int i = 0;
 503         bool ret = false;
 504         struct pipe_ctx *pipes;
 505
 506         for (i = 0; i < MAX_PIPES; i++) {
 507                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 508                                 == stream) {
 509
 510                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 511                         dc->hwss.program_output_csc(dc,
 512                                         pipes,
 513                                         stream->output_color_space,
 514                                         stream->csc_color_matrix.matrix,
 515                                         pipes->stream_res.opp->inst);
 516                         ret = true;
 517                 }
 518         }
 519
 520         return ret;
 521 }
 522
 523 void dc_stream_set_static_screen_params(struct dc *dc,
 524                 struct dc_stream_state **streams,
 525                 int num_streams,
 526                 const struct dc_static_screen_params *params)
 527 {
 528         int i = 0;
 529         int j = 0;
 530         struct pipe_ctx *pipes_affected[MAX_PIPES];
 531         int num_pipes_affected = 0;
 532
 533         for (i = 0; i < num_streams; i++) {
 534                 struct dc_stream_state *stream = streams[i];
 535
 536                 for (j = 0; j < MAX_PIPES; j++) {
 537                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 538                                         == stream) {
 539                                 pipes_affected[num_pipes_affected++] =
 540                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 541                         }
 542                 }
 543         }
 544
 545         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 546 }
 547
 548 static void dc_destruct(struct dc *dc)
 549 {
 550         if (dc->current_state) {
 551                 dc_release_state(dc->current_state);
 552                 dc->current_state = NULL;
 553         }
 554
 555         destroy_links(dc);
 556
 557         if (dc->clk_mgr) {
 558                 dc_destroy_clk_mgr(dc->clk_mgr);
 559                 dc->clk_mgr = NULL;
 560         }
 561
 562         dc_destroy_resource_pool(dc);
 563
 564         if (dc->ctx->gpio_service)
 565                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 566
 567         if (dc->ctx->created_bios)
 568                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 569
 570         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 571
 572         kfree(dc->ctx);
 573         dc->ctx = NULL;
 574
 575         kfree(dc->bw_vbios);
 576         dc->bw_vbios = NULL;
 577
 578         kfree(dc->bw_dceip);
 579         dc->bw_dceip = NULL;
 580
 581 #ifdef CONFIG_DRM_AMD_DC_DCN
 582         kfree(dc->dcn_soc);
 583         dc->dcn_soc = NULL;
 584
 585         kfree(dc->dcn_ip);
 586         dc->dcn_ip = NULL;
 587
 588 #endif
 589         kfree(dc->vm_helper);
 590         dc->vm_helper = NULL;
 591
 592 }
 593
 594 static bool dc_construct_ctx(struct dc *dc,
 595                 const struct dc_init_data *init_params)
 596 {
 597         struct dc_context *dc_ctx;
 598         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 599
 600         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 601         if (!dc_ctx)
 602                 return false;
 603
 604         dc_ctx->cgs_device = init_params->cgs_device;
 605         dc_ctx->driver_context = init_params->driver;
 606         dc_ctx->dc = dc;
 607         dc_ctx->asic_id = init_params->asic_id;
 608         dc_ctx->dc_sink_id_count = 0;
 609         dc_ctx->dc_stream_id_count = 0;
 610         dc_ctx->dce_environment = init_params->dce_environment;
 611
 612         /* Create logger */
 613
 614         dc_version = resource_parse_asic_id(init_params->asic_id);
 615         dc_ctx->dce_version = dc_version;
 616
 617         dc_ctx->perf_trace = dc_perf_trace_create();
 618         if (!dc_ctx->perf_trace) {
 619                 ASSERT_CRITICAL(false);
 620                 return false;
 621         }
 622
 623         dc->ctx = dc_ctx;
 624
 625         return true;
 626 }
 627
 628 static bool dc_construct(struct dc *dc,
 629                 const struct dc_init_data *init_params)
 630 {
 631         struct dc_context *dc_ctx;
 632         struct bw_calcs_dceip *dc_dceip;
 633         struct bw_calcs_vbios *dc_vbios;
 634 #ifdef CONFIG_DRM_AMD_DC_DCN
 635         struct dcn_soc_bounding_box *dcn_soc;
 636         struct dcn_ip_params *dcn_ip;
 637 #endif
 638
 639         dc->config = init_params->flags;
 640
 641         // Allocate memory for the vm_helper
 642         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 643         if (!dc->vm_helper) {
 644                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 645                 goto fail;
 646         }
 647
 648         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 649
 650         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 651         if (!dc_dceip) {
 652                 dm_error("%s: failed to create dceip\n", __func__);
 653                 goto fail;
 654         }
 655
 656         dc->bw_dceip = dc_dceip;
 657
 658         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 659         if (!dc_vbios) {
 660                 dm_error("%s: failed to create vbios\n", __func__);
 661                 goto fail;
 662         }
 663
 664         dc->bw_vbios = dc_vbios;
 665 #ifdef CONFIG_DRM_AMD_DC_DCN
 666         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 667         if (!dcn_soc) {
 668                 dm_error("%s: failed to create dcn_soc\n", __func__);
 669                 goto fail;
 670         }
 671
 672         dc->dcn_soc = dcn_soc;
 673
 674         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 675         if (!dcn_ip) {
 676                 dm_error("%s: failed to create dcn_ip\n", __func__);
 677                 goto fail;
 678         }
 679
 680         dc->dcn_ip = dcn_ip;
 681         dc->soc_bounding_box = init_params->soc_bounding_box;
 682 #endif
 683
 684         if (!dc_construct_ctx(dc, init_params)) {
 685                 dm_error("%s: failed to create ctx\n", __func__);
 686                 goto fail;
 687         }
 688
 689         dc_ctx = dc->ctx;
 690
 691         /* Resource should construct all asic specific resources.
 692          * This should be the only place where we need to parse the asic id
 693          */
 694         if (init_params->vbios_override)
 695                 dc_ctx->dc_bios = init_params->vbios_override;
 696         else {
 697                 /* Create BIOS parser */
 698                 struct bp_init_data bp_init_data;
 699
 700                 bp_init_data.ctx = dc_ctx;
 701                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 702
 703                 dc_ctx->dc_bios = dal_bios_parser_create(
 704                                 &bp_init_data, dc_ctx->dce_version);
 705
 706                 if (!dc_ctx->dc_bios) {
 707                         ASSERT_CRITICAL(false);
 708                         goto fail;
 709                 }
 710
 711                 dc_ctx->created_bios = true;
 712         }
 713
 714         dc->vendor_signature = init_params->vendor_signature;
 715
 716         /* Create GPIO service */
 717         dc_ctx->gpio_service = dal_gpio_service_create(
 718                         dc_ctx->dce_version,
 719                         dc_ctx->dce_environment,
 720                         dc_ctx);
 721
 722         if (!dc_ctx->gpio_service) {
 723                 ASSERT_CRITICAL(false);
 724                 goto fail;
 725         }
 726
 727         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 728         if (!dc->res_pool)
 729                 goto fail;
 730
 731         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 732         if (!dc->clk_mgr)
 733                 goto fail;
 734 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
 735         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 736 #endif
 737
 738         if (dc->res_pool->funcs->update_bw_bounding_box)
 739                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 740
 741         /* Creation of current_state must occur after dc->dml
 742          * is initialized in dc_create_resource_pool because
 743          * on creation it copies the contents of dc->dml
 744          */
 745
 746         dc->current_state = dc_create_state(dc);
 747
 748         if (!dc->current_state) {
 749                 dm_error("%s: failed to create validate ctx\n", __func__);
 750                 goto fail;
 751         }
 752
 753         dc_resource_state_construct(dc, dc->current_state);
 754
 755         if (!create_links(dc, init_params->num_virtual_links))
 756                 goto fail;
 757
 758         return true;
 759
 760 fail:
 761         return false;
 762 }
 763
 764 static bool disable_all_writeback_pipes_for_stream(
 765                 const struct dc *dc,
 766                 struct dc_stream_state *stream,
 767                 struct dc_state *context)
 768 {
 769         int i;
 770
 771         for (i = 0; i < stream->num_wb_info; i++)
 772                 stream->writeback_info[i].wb_enabled = false;
 773
 774         return true;
 775 }
 776
 777 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 778 {
 779         int i = 0;
 780
 781         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 782         if (dc->hwss.interdependent_update_lock)
 783                 dc->hwss.interdependent_update_lock(dc, context, lock);
 784         else {
 785                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 786                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 787                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 788
 789                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 790                         if (stream == pipe_ctx->stream) {
 791                                 if (!pipe_ctx->top_pipe &&
 792                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 793                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 794                         }
 795                 }
 796         }
 797 }
 798
 799 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 800 {
 801         int i, j;
 802         struct dc_state *dangling_context = dc_create_state(dc);
 803         struct dc_state *current_ctx;
 804
 805         if (dangling_context == NULL)
 806                 return;
 807
 808         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 809
 810         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 811                 struct dc_stream_state *old_stream =
 812                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 813                 bool should_disable = true;
 814
 815                 for (j = 0; j < context->stream_count; j++) {
 816                         if (old_stream == context->streams[j]) {
 817                                 should_disable = false;
 818                                 break;
 819                         }
 820                 }
 821                 if (should_disable && old_stream) {
 822                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 823                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 824
 825                         if (dc->hwss.apply_ctx_for_surface) {
 826                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 827                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 828                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 829                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 830                         }
 831                         if (dc->hwss.program_front_end_for_ctx) {
 832                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 833                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 834                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 835                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 836                         }
 837                 }
 838         }
 839
 840         current_ctx = dc->current_state;
 841         dc->current_state = dangling_context;
 842         dc_release_state(current_ctx);
 843 }
 844
 845 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 846 {
 847         int i;
 848         PERF_TRACE();
 849         for (i = 0; i < MAX_PIPES; i++) {
 850                 int count = 0;
 851                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 852
 853                 if (!pipe->plane_state)
 854                         continue;
 855
 856                 /* Timeout 100 ms */
 857                 while (count < 100000) {
 858                         /* Must set to false to start with, due to OR in update function */
 859                         pipe->plane_state->status.is_flip_pending = false;
 860                         dc->hwss.update_pending_status(pipe);
 861                         if (!pipe->plane_state->status.is_flip_pending)
 862                                 break;
 863                         udelay(1);
 864                         count++;
 865                 }
 866                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 867         }
 868         PERF_TRACE();
 869 }
 870
 871 /*******************************************************************************
 872  * Public functions
 873  ******************************************************************************/
 874
 875 struct dc *dc_create(const struct dc_init_data *init_params)
 876 {
 877         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 878         unsigned int full_pipe_count;
 879
 880         if (NULL == dc)
 881                 goto alloc_fail;
 882
 883         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 884                 if (false == dc_construct_ctx(dc, init_params)) {
 885                         dc_destruct(dc);
 886                         goto construct_fail;
 887                 }
 888         } else {
 889                 if (false == dc_construct(dc, init_params)) {
 890                         dc_destruct(dc);
 891                         goto construct_fail;
 892                 }
 893
 894                 full_pipe_count = dc->res_pool->pipe_count;
 895                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 896                         full_pipe_count--;
 897                 dc->caps.max_streams = min(
 898                                 full_pipe_count,
 899                                 dc->res_pool->stream_enc_count);
 900
 901                 dc->optimize_seamless_boot_streams = 0;
 902                 dc->caps.max_links = dc->link_count;
 903                 dc->caps.max_audios = dc->res_pool->audio_count;
 904                 dc->caps.linear_pitch_alignment = 64;
 905
 906                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 907
 908                 if (dc->res_pool->dmcu != NULL)
 909                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 910         }
 911
 912         /* Populate versioning information */
 913         dc->versions.dc_ver = DC_VER;
 914
 915         dc->build_id = DC_BUILD_ID;
 916
 917         DC_LOG_DC("Display Core initialized\n");
 918
 919
 920
 921         return dc;
 922
 923 construct_fail:
 924         kfree(dc);
 925
 926 alloc_fail:
 927         return NULL;
 928 }
 929
 930 void dc_hardware_init(struct dc *dc)
 931 {
 932         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
 933                 dc->hwss.init_hw(dc);
 934 }
 935
 936 void dc_init_callbacks(struct dc *dc,
 937                 const struct dc_callback_init *init_params)
 938 {
 939 #ifdef CONFIG_DRM_AMD_DC_HDCP
 940         dc->ctx->cp_psp = init_params->cp_psp;
 941 #endif
 942 }
 943
 944 void dc_deinit_callbacks(struct dc *dc)
 945 {
 946 #ifdef CONFIG_DRM_AMD_DC_HDCP
 947         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
 948 #endif
 949 }
 950
 951 void dc_destroy(struct dc **dc)
 952 {
 953         dc_destruct(*dc);
 954         kfree(*dc);
 955         *dc = NULL;
 956 }
 957
 958 static void enable_timing_multisync(
 959                 struct dc *dc,
 960                 struct dc_state *ctx)
 961 {
 962         int i = 0, multisync_count = 0;
 963         int pipe_count = dc->res_pool->pipe_count;
 964         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 965
 966         for (i = 0; i < pipe_count; i++) {
 967                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 968                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 969                         continue;
 970                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 971                         continue;
 972                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 973                 multisync_count++;
 974         }
 975
 976         if (multisync_count > 0) {
 977                 dc->hwss.enable_per_frame_crtc_position_reset(
 978                         dc, multisync_count, multisync_pipes);
 979         }
 980 }
 981
 982 static void program_timing_sync(
 983                 struct dc *dc,
 984                 struct dc_state *ctx)
 985 {
 986         int i, j, k;
 987         int group_index = 0;
 988         int num_group = 0;
 989         int pipe_count = dc->res_pool->pipe_count;
 990         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 991
 992         for (i = 0; i < pipe_count; i++) {
 993                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 994                         continue;
 995
 996                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 997         }
 998
 999         for (i = 0; i < pipe_count; i++) {
1000                 int group_size = 1;
1001                 struct pipe_ctx *pipe_set[MAX_PIPES];
1002
1003                 if (!unsynced_pipes[i])
1004                         continue;
1005
1006                 pipe_set[0] = unsynced_pipes[i];
1007                 unsynced_pipes[i] = NULL;
1008
1009                 /* Add tg to the set, search rest of the tg's for ones with
1010                  * same timing, add all tgs with same timing to the group
1011                  */
1012                 for (j = i + 1; j < pipe_count; j++) {
1013                         if (!unsynced_pipes[j])
1014                                 continue;
1015
1016                         if (resource_are_streams_timing_synchronizable(
1017                                         unsynced_pipes[j]->stream,
1018                                         pipe_set[0]->stream)) {
1019                                 pipe_set[group_size] = unsynced_pipes[j];
1020                                 unsynced_pipes[j] = NULL;
1021                                 group_size++;
1022                         }
1023                 }
1024
1025                 /* set first unblanked pipe as master */
1026                 for (j = 0; j < group_size; j++) {
1027                         bool is_blanked;
1028
1029                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1030                                 is_blanked =
1031                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1032                         else
1033                                 is_blanked =
1034                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1035                         if (!is_blanked) {
1036                                 if (j == 0)
1037                                         break;
1038
1039                                 swap(pipe_set[0], pipe_set[j]);
1040                                 break;
1041                         }
1042                 }
1043
1044
1045                 for (k = 0; k < group_size; k++) {
1046                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1047
1048                         status->timing_sync_info.group_id = num_group;
1049                         status->timing_sync_info.group_size = group_size;
1050                         if (k == 0)
1051                                 status->timing_sync_info.master = true;
1052                         else
1053                                 status->timing_sync_info.master = false;
1054
1055                 }
1056                 /* remove any other unblanked pipes as they have already been synced */
1057                 for (j = j + 1; j < group_size; j++) {
1058                         bool is_blanked;
1059
1060                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1061                                 is_blanked =
1062                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1063                         else
1064                                 is_blanked =
1065                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1066                         if (!is_blanked) {
1067                                 group_size--;
1068                                 pipe_set[j] = pipe_set[group_size];
1069                                 j--;
1070                         }
1071                 }
1072
1073                 if (group_size > 1) {
1074                         dc->hwss.enable_timing_synchronization(
1075                                 dc, group_index, group_size, pipe_set);
1076                         group_index++;
1077                 }
1078                 num_group++;
1079         }
1080 }
1081
1082 static bool context_changed(
1083                 struct dc *dc,
1084                 struct dc_state *context)
1085 {
1086         uint8_t i;
1087
1088         if (context->stream_count != dc->current_state->stream_count)
1089                 return true;
1090
1091         for (i = 0; i < dc->current_state->stream_count; i++) {
1092                 if (dc->current_state->streams[i] != context->streams[i])
1093                         return true;
1094         }
1095
1096         return false;
1097 }
1098
1099 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1100                                 const struct dc_sink *sink,
1101                                 struct dc_crtc_timing *crtc_timing)
1102 {
1103         struct timing_generator *tg;
1104         struct stream_encoder *se = NULL;
1105
1106         struct dc_crtc_timing hw_crtc_timing = {0};
1107
1108         struct dc_link *link = sink->link;
1109         unsigned int i, enc_inst, tg_inst = 0;
1110
1111         // Seamless port only support single DP and EDP so far
1112         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1113                 sink->sink_signal != SIGNAL_TYPE_EDP)
1114                 return false;
1115
1116         /* Check for enabled DIG to identify enabled display */
1117         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1118                 return false;
1119
1120         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1121
1122         if (enc_inst == ENGINE_ID_UNKNOWN)
1123                 return false;
1124
1125         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1126                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1127
1128                         se = dc->res_pool->stream_enc[i];
1129
1130                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1131                                 dc->res_pool->stream_enc[i]);
1132                         break;
1133                 }
1134         }
1135
1136         // tg_inst not found
1137         if (i == dc->res_pool->stream_enc_count)
1138                 return false;
1139
1140         if (tg_inst >= dc->res_pool->timing_generator_count)
1141                 return false;
1142
1143         tg = dc->res_pool->timing_generators[tg_inst];
1144
1145         if (!tg->funcs->get_hw_timing)
1146                 return false;
1147
1148         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1149                 return false;
1150
1151         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1152                 return false;
1153
1154         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1155                 return false;
1156
1157         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1158                 return false;
1159
1160         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1161                 return false;
1162
1163         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1164                 return false;
1165
1166         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1167                 return false;
1168
1169         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1170                 return false;
1171
1172         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1173                 return false;
1174
1175         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1176                 return false;
1177
1178         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1179                 return false;
1180
1181         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1182                 return false;
1183
1184         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1185                 return false;
1186
1187         if (dc_is_dp_signal(link->connector_signal)) {
1188                 unsigned int pix_clk_100hz;
1189
1190                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1191                         dc->res_pool->dp_clock_source,
1192                         tg_inst, &pix_clk_100hz);
1193
1194                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1195                         return false;
1196
1197                 if (!se->funcs->dp_get_pixel_format)
1198                         return false;
1199
1200                 if (!se->funcs->dp_get_pixel_format(
1201                         se,
1202                         &hw_crtc_timing.pixel_encoding,
1203                         &hw_crtc_timing.display_color_depth))
1204                         return false;
1205
1206                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1207                         return false;
1208
1209                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1210                         return false;
1211         }
1212
1213         return true;
1214 }
1215
1216 bool dc_enable_stereo(
1217         struct dc *dc,
1218         struct dc_state *context,
1219         struct dc_stream_state *streams[],
1220         uint8_t stream_count)
1221 {
1222         bool ret = true;
1223         int i, j;
1224         struct pipe_ctx *pipe;
1225
1226         for (i = 0; i < MAX_PIPES; i++) {
1227                 if (context != NULL)
1228                         pipe = &context->res_ctx.pipe_ctx[i];
1229                 else
1230                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1231                 for (j = 0 ; pipe && j < stream_count; j++)  {
1232                         if (streams[j] && streams[j] == pipe->stream &&
1233                                 dc->hwss.setup_stereo)
1234                                 dc->hwss.setup_stereo(pipe, dc);
1235                 }
1236         }
1237
1238         return ret;
1239 }
1240
1241 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1242 {
1243         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1244                 enable_timing_multisync(dc, context);
1245                 program_timing_sync(dc, context);
1246         }
1247 }
1248
1249 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1250 {
1251         int i;
1252         unsigned int stream_mask = 0;
1253
1254         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1255                 if (context->res_ctx.pipe_ctx[i].stream)
1256                         stream_mask |= 1 << i;
1257         }
1258
1259         return stream_mask;
1260 }
1261
1262 /*
1263  * Applies given context to HW and copy it into current context.
1264  * It's up to the user to release the src context afterwards.
1265  */
1266 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1267 {
1268         struct dc_bios *dcb = dc->ctx->dc_bios;
1269         enum dc_status result = DC_ERROR_UNEXPECTED;
1270         struct pipe_ctx *pipe;
1271         int i, k, l;
1272         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1273
1274 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1275         dc_allow_idle_optimizations(dc, false);
1276 #endif
1277
1278         for (i = 0; i < context->stream_count; i++)
1279                 dc_streams[i] =  context->streams[i];
1280
1281         if (!dcb->funcs->is_accelerated_mode(dcb))
1282                 dc->hwss.enable_accelerated_mode(dc, context);
1283
1284         for (i = 0; i < context->stream_count; i++) {
1285                 if (context->streams[i]->apply_seamless_boot_optimization)
1286                         dc->optimize_seamless_boot_streams++;
1287         }
1288
1289         if (context->stream_count > dc->optimize_seamless_boot_streams)
1290                 dc->hwss.prepare_bandwidth(dc, context);
1291
1292         disable_dangling_plane(dc, context);
1293         /* re-program planes for existing stream, in case we need to
1294          * free up plane resource for later use
1295          */
1296         if (dc->hwss.apply_ctx_for_surface) {
1297                 for (i = 0; i < context->stream_count; i++) {
1298                         if (context->streams[i]->mode_changed)
1299                                 continue;
1300                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1301                         dc->hwss.apply_ctx_for_surface(
1302                                 dc, context->streams[i],
1303                                 context->stream_status[i].plane_count,
1304                                 context); /* use new pipe config in new context */
1305                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1306                         dc->hwss.post_unlock_program_front_end(dc, context);
1307                 }
1308         }
1309
1310         /* Program hardware */
1311         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1312                 pipe = &context->res_ctx.pipe_ctx[i];
1313                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1314         }
1315
1316         result = dc->hwss.apply_ctx_to_hw(dc, context);
1317
1318         if (result != DC_OK)
1319                 return result;
1320
1321         dc_trigger_sync(dc, context);
1322
1323         /* Program all planes within new context*/
1324         if (dc->hwss.program_front_end_for_ctx) {
1325                 dc->hwss.interdependent_update_lock(dc, context, true);
1326                 dc->hwss.program_front_end_for_ctx(dc, context);
1327                 dc->hwss.interdependent_update_lock(dc, context, false);
1328                 dc->hwss.post_unlock_program_front_end(dc, context);
1329         }
1330         for (i = 0; i < context->stream_count; i++) {
1331                 const struct dc_link *link = context->streams[i]->link;
1332
1333                 if (!context->streams[i]->mode_changed)
1334                         continue;
1335
1336                 if (dc->hwss.apply_ctx_for_surface) {
1337                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1338                         dc->hwss.apply_ctx_for_surface(
1339                                         dc, context->streams[i],
1340                                         context->stream_status[i].plane_count,
1341                                         context);
1342                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1343                         dc->hwss.post_unlock_program_front_end(dc, context);
1344                 }
1345
1346                 /*
1347                  * enable stereo
1348                  * TODO rework dc_enable_stereo call to work with validation sets?
1349                  */
1350                 for (k = 0; k < MAX_PIPES; k++) {
1351                         pipe = &context->res_ctx.pipe_ctx[k];
1352
1353                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1354                                 if (context->streams[l] &&
1355                                         context->streams[l] == pipe->stream &&
1356                                         dc->hwss.setup_stereo)
1357                                         dc->hwss.setup_stereo(pipe, dc);
1358                         }
1359                 }
1360
1361                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1362                                 context->streams[i]->timing.h_addressable,
1363                                 context->streams[i]->timing.v_addressable,
1364                                 context->streams[i]->timing.h_total,
1365                                 context->streams[i]->timing.v_total,
1366                                 context->streams[i]->timing.pix_clk_100hz / 10);
1367         }
1368
1369         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1370
1371         if (context->stream_count > dc->optimize_seamless_boot_streams) {
1372                 /* Must wait for no flips to be pending before doing optimize bw */
1373                 wait_for_no_pipes_pending(dc, context);
1374                 /* pplib is notified if disp_num changed */
1375                 dc->hwss.optimize_bandwidth(dc, context);
1376         }
1377
1378         context->stream_mask = get_stream_mask(dc, context);
1379
1380         if (context->stream_mask != dc->current_state->stream_mask)
1381                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1382
1383         for (i = 0; i < context->stream_count; i++)
1384                 context->streams[i]->mode_changed = false;
1385
1386         dc_release_state(dc->current_state);
1387
1388         dc->current_state = context;
1389
1390         dc_retain_state(dc->current_state);
1391
1392         return result;
1393 }
1394
1395 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1396 {
1397         enum dc_status result = DC_ERROR_UNEXPECTED;
1398         int i;
1399
1400         if (false == context_changed(dc, context))
1401                 return DC_OK;
1402
1403         DC_LOG_DC("%s: %d streams\n",
1404                                 __func__, context->stream_count);
1405
1406         for (i = 0; i < context->stream_count; i++) {
1407                 struct dc_stream_state *stream = context->streams[i];
1408
1409                 dc_stream_log(dc, stream);
1410         }
1411
1412         result = dc_commit_state_no_check(dc, context);
1413
1414         return (result == DC_OK);
1415 }
1416
1417 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1418 bool dc_acquire_release_mpc_3dlut(
1419                 struct dc *dc, bool acquire,
1420                 struct dc_stream_state *stream,
1421                 struct dc_3dlut **lut,
1422                 struct dc_transfer_func **shaper)
1423 {
1424         int pipe_idx;
1425         bool ret = false;
1426         bool found_pipe_idx = false;
1427         const struct resource_pool *pool = dc->res_pool;
1428         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1429         int mpcc_id = 0;
1430
1431         if (pool && res_ctx) {
1432                 if (acquire) {
1433                         /*find pipe idx for the given stream*/
1434                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1435                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1436                                         found_pipe_idx = true;
1437                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1438                                         break;
1439                                 }
1440                         }
1441                 } else
1442                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1443
1444                 if (found_pipe_idx) {
1445                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1446                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1447                         else if (acquire == false && pool->funcs->release_post_bldn_3dlut)
1448                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1449                 }
1450         }
1451         return ret;
1452 }
1453 #endif
1454 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1455 {
1456         int i;
1457         struct pipe_ctx *pipe;
1458
1459         for (i = 0; i < MAX_PIPES; i++) {
1460                 pipe = &context->res_ctx.pipe_ctx[i];
1461
1462                 if (!pipe->plane_state)
1463                         continue;
1464
1465                 /* Must set to false to start with, due to OR in update function */
1466                 pipe->plane_state->status.is_flip_pending = false;
1467                 dc->hwss.update_pending_status(pipe);
1468                 if (pipe->plane_state->status.is_flip_pending)
1469                         return true;
1470         }
1471         return false;
1472 }
1473
1474 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1475 {
1476         int i;
1477         struct dc_state *context = dc->current_state;
1478
1479         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1480                 return true;
1481
1482         post_surface_trace(dc);
1483
1484         if (is_flip_pending_in_pipes(dc, context))
1485                 return true;
1486
1487         for (i = 0; i < dc->res_pool->pipe_count; i++)
1488                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1489                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1490                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1491                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1492                 }
1493
1494         dc->hwss.optimize_bandwidth(dc, context);
1495
1496         dc->optimized_required = false;
1497         dc->wm_optimized_required = false;
1498
1499         return true;
1500 }
1501
1502 static void init_state(struct dc *dc, struct dc_state *context)
1503 {
1504         /* Each context must have their own instance of VBA and in order to
1505          * initialize and obtain IP and SOC the base DML instance from DC is
1506          * initially copied into every context
1507          */
1508 #ifdef CONFIG_DRM_AMD_DC_DCN
1509         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1510 #endif
1511 }
1512
1513 struct dc_state *dc_create_state(struct dc *dc)
1514 {
1515         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1516                                            GFP_KERNEL);
1517
1518         if (!context)
1519                 return NULL;
1520
1521         init_state(dc, context);
1522
1523         kref_init(&context->refcount);
1524
1525         return context;
1526 }
1527
1528 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1529 {
1530         int i, j;
1531         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1532
1533         if (!new_ctx)
1534                 return NULL;
1535         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1536
1537         for (i = 0; i < MAX_PIPES; i++) {
1538                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1539
1540                         if (cur_pipe->top_pipe)
1541                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1542
1543                         if (cur_pipe->bottom_pipe)
1544                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1545
1546                         if (cur_pipe->prev_odm_pipe)
1547                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1548
1549                         if (cur_pipe->next_odm_pipe)
1550                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1551
1552         }
1553
1554         for (i = 0; i < new_ctx->stream_count; i++) {
1555                         dc_stream_retain(new_ctx->streams[i]);
1556                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1557                                 dc_plane_state_retain(
1558                                         new_ctx->stream_status[i].plane_states[j]);
1559         }
1560
1561         kref_init(&new_ctx->refcount);
1562
1563         return new_ctx;
1564 }
1565
1566 void dc_retain_state(struct dc_state *context)
1567 {
1568         kref_get(&context->refcount);
1569 }
1570
1571 static void dc_state_free(struct kref *kref)
1572 {
1573         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1574         dc_resource_state_destruct(context);
1575         kvfree(context);
1576 }
1577
1578 void dc_release_state(struct dc_state *context)
1579 {
1580         kref_put(&context->refcount, dc_state_free);
1581 }
1582
1583 bool dc_set_generic_gpio_for_stereo(bool enable,
1584                 struct gpio_service *gpio_service)
1585 {
1586         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1587         struct gpio_pin_info pin_info;
1588         struct gpio *generic;
1589         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1590                            GFP_KERNEL);
1591
1592         if (!config)
1593                 return false;
1594         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1595
1596         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1597                 kfree(config);
1598                 return false;
1599         } else {
1600                 generic = dal_gpio_service_create_generic_mux(
1601                         gpio_service,
1602                         pin_info.offset,
1603                         pin_info.mask);
1604         }
1605
1606         if (!generic) {
1607                 kfree(config);
1608                 return false;
1609         }
1610
1611         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1612
1613         config->enable_output_from_mux = enable;
1614         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1615
1616         if (gpio_result == GPIO_RESULT_OK)
1617                 gpio_result = dal_mux_setup_config(generic, config);
1618
1619         if (gpio_result == GPIO_RESULT_OK) {
1620                 dal_gpio_close(generic);
1621                 dal_gpio_destroy_generic_mux(&generic);
1622                 kfree(config);
1623                 return true;
1624         } else {
1625                 dal_gpio_close(generic);
1626                 dal_gpio_destroy_generic_mux(&generic);
1627                 kfree(config);
1628                 return false;
1629         }
1630 }
1631
1632 static bool is_surface_in_context(
1633                 const struct dc_state *context,
1634                 const struct dc_plane_state *plane_state)
1635 {
1636         int j;
1637
1638         for (j = 0; j < MAX_PIPES; j++) {
1639                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1640
1641                 if (plane_state == pipe_ctx->plane_state) {
1642                         return true;
1643                 }
1644         }
1645
1646         return false;
1647 }
1648
1649 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1650 {
1651         union surface_update_flags *update_flags = &u->surface->update_flags;
1652         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1653
1654         if (!u->plane_info)
1655                 return UPDATE_TYPE_FAST;
1656
1657         if (u->plane_info->color_space != u->surface->color_space) {
1658                 update_flags->bits.color_space_change = 1;
1659                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1660         }
1661
1662         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1663                 update_flags->bits.horizontal_mirror_change = 1;
1664                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1665         }
1666
1667         if (u->plane_info->rotation != u->surface->rotation) {
1668                 update_flags->bits.rotation_change = 1;
1669                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1670         }
1671
1672         if (u->plane_info->format != u->surface->format) {
1673                 update_flags->bits.pixel_format_change = 1;
1674                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1675         }
1676
1677         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1678                 update_flags->bits.stereo_format_change = 1;
1679                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1680         }
1681
1682         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1683                 update_flags->bits.per_pixel_alpha_change = 1;
1684                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1685         }
1686
1687         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1688                 update_flags->bits.global_alpha_change = 1;
1689                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1690         }
1691
1692         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1693                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1694                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1695                 update_flags->bits.dcc_change = 1;
1696                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1697         }
1698
1699         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1700                         resource_pixel_format_to_bpp(u->surface->format)) {
1701                 /* different bytes per element will require full bandwidth
1702                  * and DML calculation
1703                  */
1704                 update_flags->bits.bpp_change = 1;
1705                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1706         }
1707
1708         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1709                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1710                 update_flags->bits.plane_size_change = 1;
1711                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1712         }
1713
1714
1715         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1716                         sizeof(union dc_tiling_info)) != 0) {
1717                 update_flags->bits.swizzle_change = 1;
1718                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1719
1720                 /* todo: below are HW dependent, we should add a hook to
1721                  * DCE/N resource and validated there.
1722                  */
1723                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1724                         /* swizzled mode requires RQ to be setup properly,
1725                          * thus need to run DML to calculate RQ settings
1726                          */
1727                         update_flags->bits.bandwidth_change = 1;
1728                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1729                 }
1730         }
1731
1732         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1733         return update_type;
1734 }
1735
1736 static enum surface_update_type get_scaling_info_update_type(
1737                 const struct dc_surface_update *u)
1738 {
1739         union surface_update_flags *update_flags = &u->surface->update_flags;
1740
1741         if (!u->scaling_info)
1742                 return UPDATE_TYPE_FAST;
1743
1744         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1745                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1746                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1747                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1748                         || u->scaling_info->scaling_quality.integer_scaling !=
1749                                 u->surface->scaling_quality.integer_scaling
1750                         ) {
1751                 update_flags->bits.scaling_change = 1;
1752
1753                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1754                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1755                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1756                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1757                         /* Making dst rect smaller requires a bandwidth change */
1758                         update_flags->bits.bandwidth_change = 1;
1759         }
1760
1761         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1762                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1763
1764                 update_flags->bits.scaling_change = 1;
1765                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1766                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1767                         /* Making src rect bigger requires a bandwidth change */
1768                         update_flags->bits.clock_change = 1;
1769         }
1770
1771         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1772                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1773                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1774                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1775                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1776                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1777                 update_flags->bits.position_change = 1;
1778
1779         if (update_flags->bits.clock_change
1780                         || update_flags->bits.bandwidth_change
1781                         || update_flags->bits.scaling_change)
1782                 return UPDATE_TYPE_FULL;
1783
1784         if (update_flags->bits.position_change)
1785                 return UPDATE_TYPE_MED;
1786
1787         return UPDATE_TYPE_FAST;
1788 }
1789
1790 static enum surface_update_type det_surface_update(const struct dc *dc,
1791                 const struct dc_surface_update *u)
1792 {
1793         const struct dc_state *context = dc->current_state;
1794         enum surface_update_type type;
1795         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1796         union surface_update_flags *update_flags = &u->surface->update_flags;
1797
1798         if (u->flip_addr)
1799                 update_flags->bits.addr_update = 1;
1800
1801         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1802                 update_flags->raw = 0xFFFFFFFF;
1803                 return UPDATE_TYPE_FULL;
1804         }
1805
1806         update_flags->raw = 0; // Reset all flags
1807
1808         type = get_plane_info_update_type(u);
1809         elevate_update_type(&overall_type, type);
1810
1811         type = get_scaling_info_update_type(u);
1812         elevate_update_type(&overall_type, type);
1813
1814         if (u->flip_addr)
1815                 update_flags->bits.addr_update = 1;
1816
1817         if (u->in_transfer_func)
1818                 update_flags->bits.in_transfer_func_change = 1;
1819
1820         if (u->input_csc_color_matrix)
1821                 update_flags->bits.input_csc_change = 1;
1822
1823         if (u->coeff_reduction_factor)
1824                 update_flags->bits.coeff_reduction_change = 1;
1825
1826         if (u->gamut_remap_matrix)
1827                 update_flags->bits.gamut_remap_change = 1;
1828
1829         if (u->gamma) {
1830                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1831
1832                 if (u->plane_info)
1833                         format = u->plane_info->format;
1834                 else if (u->surface)
1835                         format = u->surface->format;
1836
1837                 if (dce_use_lut(format))
1838                         update_flags->bits.gamma_change = 1;
1839         }
1840
1841         if (u->hdr_mult.value)
1842                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1843                         update_flags->bits.hdr_mult = 1;
1844                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1845                 }
1846
1847         if (update_flags->bits.in_transfer_func_change) {
1848                 type = UPDATE_TYPE_MED;
1849                 elevate_update_type(&overall_type, type);
1850         }
1851
1852         if (update_flags->bits.input_csc_change
1853                         || update_flags->bits.coeff_reduction_change
1854                         || update_flags->bits.gamma_change
1855                         || update_flags->bits.gamut_remap_change) {
1856                 type = UPDATE_TYPE_FULL;
1857                 elevate_update_type(&overall_type, type);
1858         }
1859
1860         return overall_type;
1861 }
1862
1863 static enum surface_update_type check_update_surfaces_for_stream(
1864                 struct dc *dc,
1865                 struct dc_surface_update *updates,
1866                 int surface_count,
1867                 struct dc_stream_update *stream_update,
1868                 const struct dc_stream_status *stream_status)
1869 {
1870         int i;
1871         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1872
1873 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1874         if (dc->idle_optimizations_allowed)
1875                 overall_type = UPDATE_TYPE_FULL;
1876
1877 #endif
1878         if (stream_status == NULL || stream_status->plane_count != surface_count)
1879                 overall_type = UPDATE_TYPE_FULL;
1880
1881         /* some stream updates require passive update */
1882         if (stream_update) {
1883                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1884
1885                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1886                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1887                         stream_update->integer_scaling_update)
1888                         su_flags->bits.scaling = 1;
1889
1890                 if (stream_update->out_transfer_func)
1891                         su_flags->bits.out_tf = 1;
1892
1893                 if (stream_update->abm_level)
1894                         su_flags->bits.abm_level = 1;
1895
1896                 if (stream_update->dpms_off)
1897                         su_flags->bits.dpms_off = 1;
1898
1899                 if (stream_update->gamut_remap)
1900                         su_flags->bits.gamut_remap = 1;
1901
1902                 if (stream_update->wb_update)
1903                         su_flags->bits.wb_update = 1;
1904
1905                 if (stream_update->dsc_config)
1906                         su_flags->bits.dsc_changed = 1;
1907
1908                 if (su_flags->raw != 0)
1909                         overall_type = UPDATE_TYPE_FULL;
1910
1911                 if (stream_update->output_csc_transform || stream_update->output_color_space)
1912                         su_flags->bits.out_csc = 1;
1913         }
1914
1915         for (i = 0 ; i < surface_count; i++) {
1916                 enum surface_update_type type =
1917                                 det_surface_update(dc, &updates[i]);
1918
1919                 elevate_update_type(&overall_type, type);
1920         }
1921
1922         return overall_type;
1923 }
1924
1925 /**
1926  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1927  *
1928  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1929  */
1930 enum surface_update_type dc_check_update_surfaces_for_stream(
1931                 struct dc *dc,
1932                 struct dc_surface_update *updates,
1933                 int surface_count,
1934                 struct dc_stream_update *stream_update,
1935                 const struct dc_stream_status *stream_status)
1936 {
1937         int i;
1938         enum surface_update_type type;
1939
1940         if (stream_update)
1941                 stream_update->stream->update_flags.raw = 0;
1942         for (i = 0; i < surface_count; i++)
1943                 updates[i].surface->update_flags.raw = 0;
1944
1945         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1946         if (type == UPDATE_TYPE_FULL) {
1947                 if (stream_update) {
1948                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
1949                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
1950                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
1951                 }
1952                 for (i = 0; i < surface_count; i++)
1953                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1954         }
1955
1956         if (type == UPDATE_TYPE_FAST) {
1957                 // If there's an available clock comparator, we use that.
1958                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
1959                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
1960                                 dc->optimized_required = true;
1961                 // Else we fallback to mem compare.
1962                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
1963                         dc->optimized_required = true;
1964                 }
1965
1966                 dc->optimized_required |= dc->wm_optimized_required;
1967         }
1968
1969         return type;
1970 }
1971
1972 static struct dc_stream_status *stream_get_status(
1973         struct dc_state *ctx,
1974         struct dc_stream_state *stream)
1975 {
1976         uint8_t i;
1977
1978         for (i = 0; i < ctx->stream_count; i++) {
1979                 if (stream == ctx->streams[i]) {
1980                         return &ctx->stream_status[i];
1981                 }
1982         }
1983
1984         return NULL;
1985 }
1986
1987 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1988
1989 static void copy_surface_update_to_plane(
1990                 struct dc_plane_state *surface,
1991                 struct dc_surface_update *srf_update)
1992 {
1993         if (srf_update->flip_addr) {
1994                 surface->address = srf_update->flip_addr->address;
1995                 surface->flip_immediate =
1996                         srf_update->flip_addr->flip_immediate;
1997                 surface->time.time_elapsed_in_us[surface->time.index] =
1998                         srf_update->flip_addr->flip_timestamp_in_us -
1999                                 surface->time.prev_update_time_in_us;
2000                 surface->time.prev_update_time_in_us =
2001                         srf_update->flip_addr->flip_timestamp_in_us;
2002                 surface->time.index++;
2003                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2004                         surface->time.index = 0;
2005
2006                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2007         }
2008
2009         if (srf_update->scaling_info) {
2010                 surface->scaling_quality =
2011                                 srf_update->scaling_info->scaling_quality;
2012                 surface->dst_rect =
2013                                 srf_update->scaling_info->dst_rect;
2014                 surface->src_rect =
2015                                 srf_update->scaling_info->src_rect;
2016                 surface->clip_rect =
2017                                 srf_update->scaling_info->clip_rect;
2018         }
2019
2020         if (srf_update->plane_info) {
2021                 surface->color_space =
2022                                 srf_update->plane_info->color_space;
2023                 surface->format =
2024                                 srf_update->plane_info->format;
2025                 surface->plane_size =
2026                                 srf_update->plane_info->plane_size;
2027                 surface->rotation =
2028                                 srf_update->plane_info->rotation;
2029                 surface->horizontal_mirror =
2030                                 srf_update->plane_info->horizontal_mirror;
2031                 surface->stereo_format =
2032                                 srf_update->plane_info->stereo_format;
2033                 surface->tiling_info =
2034                                 srf_update->plane_info->tiling_info;
2035                 surface->visible =
2036                                 srf_update->plane_info->visible;
2037                 surface->per_pixel_alpha =
2038                                 srf_update->plane_info->per_pixel_alpha;
2039                 surface->global_alpha =
2040                                 srf_update->plane_info->global_alpha;
2041                 surface->global_alpha_value =
2042                                 srf_update->plane_info->global_alpha_value;
2043                 surface->dcc =
2044                                 srf_update->plane_info->dcc;
2045                 surface->layer_index =
2046                                 srf_update->plane_info->layer_index;
2047         }
2048
2049         if (srf_update->gamma &&
2050                         (surface->gamma_correction !=
2051                                         srf_update->gamma)) {
2052                 memcpy(&surface->gamma_correction->entries,
2053                         &srf_update->gamma->entries,
2054                         sizeof(struct dc_gamma_entries));
2055                 surface->gamma_correction->is_identity =
2056                         srf_update->gamma->is_identity;
2057                 surface->gamma_correction->num_entries =
2058                         srf_update->gamma->num_entries;
2059                 surface->gamma_correction->type =
2060                         srf_update->gamma->type;
2061         }
2062
2063         if (srf_update->in_transfer_func &&
2064                         (surface->in_transfer_func !=
2065                                 srf_update->in_transfer_func)) {
2066                 surface->in_transfer_func->sdr_ref_white_level =
2067                         srf_update->in_transfer_func->sdr_ref_white_level;
2068                 surface->in_transfer_func->tf =
2069                         srf_update->in_transfer_func->tf;
2070                 surface->in_transfer_func->type =
2071                         srf_update->in_transfer_func->type;
2072                 memcpy(&surface->in_transfer_func->tf_pts,
2073                         &srf_update->in_transfer_func->tf_pts,
2074                         sizeof(struct dc_transfer_func_distributed_points));
2075         }
2076
2077         if (srf_update->func_shaper &&
2078                         (surface->in_shaper_func !=
2079                         srf_update->func_shaper))
2080                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2081                 sizeof(*surface->in_shaper_func));
2082
2083         if (srf_update->lut3d_func &&
2084                         (surface->lut3d_func !=
2085                         srf_update->lut3d_func))
2086                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2087                 sizeof(*surface->lut3d_func));
2088
2089         if (srf_update->hdr_mult.value)
2090                 surface->hdr_mult =
2091                                 srf_update->hdr_mult;
2092
2093         if (srf_update->blend_tf &&
2094                         (surface->blend_tf !=
2095                         srf_update->blend_tf))
2096                 memcpy(surface->blend_tf, srf_update->blend_tf,
2097                 sizeof(*surface->blend_tf));
2098
2099         if (srf_update->input_csc_color_matrix)
2100                 surface->input_csc_color_matrix =
2101                         *srf_update->input_csc_color_matrix;
2102
2103         if (srf_update->coeff_reduction_factor)
2104                 surface->coeff_reduction_factor =
2105                         *srf_update->coeff_reduction_factor;
2106
2107         if (srf_update->gamut_remap_matrix)
2108                 surface->gamut_remap_matrix =
2109                         *srf_update->gamut_remap_matrix;
2110 }
2111
2112 static void copy_stream_update_to_stream(struct dc *dc,
2113                                          struct dc_state *context,
2114                                          struct dc_stream_state *stream,
2115                                          struct dc_stream_update *update)
2116 {
2117         struct dc_context *dc_ctx = dc->ctx;
2118
2119         if (update == NULL || stream == NULL)
2120                 return;
2121
2122         if (update->src.height && update->src.width)
2123                 stream->src = update->src;
2124
2125         if (update->dst.height && update->dst.width)
2126                 stream->dst = update->dst;
2127
2128         if (update->out_transfer_func &&
2129             stream->out_transfer_func != update->out_transfer_func) {
2130                 stream->out_transfer_func->sdr_ref_white_level =
2131                         update->out_transfer_func->sdr_ref_white_level;
2132                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2133                 stream->out_transfer_func->type =
2134                         update->out_transfer_func->type;
2135                 memcpy(&stream->out_transfer_func->tf_pts,
2136                        &update->out_transfer_func->tf_pts,
2137                        sizeof(struct dc_transfer_func_distributed_points));
2138         }
2139
2140         if (update->hdr_static_metadata)
2141                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2142
2143         if (update->abm_level)
2144                 stream->abm_level = *update->abm_level;
2145
2146         if (update->periodic_interrupt0)
2147                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2148
2149         if (update->periodic_interrupt1)
2150                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2151
2152         if (update->gamut_remap)
2153                 stream->gamut_remap_matrix = *update->gamut_remap;
2154
2155         /* Note: this being updated after mode set is currently not a use case
2156          * however if it arises OCSC would need to be reprogrammed at the
2157          * minimum
2158          */
2159         if (update->output_color_space)
2160                 stream->output_color_space = *update->output_color_space;
2161
2162         if (update->output_csc_transform)
2163                 stream->csc_color_matrix = *update->output_csc_transform;
2164
2165         if (update->vrr_infopacket)
2166                 stream->vrr_infopacket = *update->vrr_infopacket;
2167
2168         if (update->dpms_off)
2169                 stream->dpms_off = *update->dpms_off;
2170
2171         if (update->vsc_infopacket)
2172                 stream->vsc_infopacket = *update->vsc_infopacket;
2173
2174         if (update->vsp_infopacket)
2175                 stream->vsp_infopacket = *update->vsp_infopacket;
2176
2177         if (update->dither_option)
2178                 stream->dither_option = *update->dither_option;
2179         /* update current stream with writeback info */
2180         if (update->wb_update) {
2181                 int i;
2182
2183                 stream->num_wb_info = update->wb_update->num_wb_info;
2184                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2185                 for (i = 0; i < stream->num_wb_info; i++)
2186                         stream->writeback_info[i] =
2187                                 update->wb_update->writeback_info[i];
2188         }
2189         if (update->dsc_config) {
2190                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2191                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2192                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2193                                        update->dsc_config->num_slices_v != 0);
2194
2195                 /* Use temporarry context for validating new DSC config */
2196                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2197
2198                 if (dsc_validate_context) {
2199                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2200
2201                         stream->timing.dsc_cfg = *update->dsc_config;
2202                         stream->timing.flags.DSC = enable_dsc;
2203                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2204                                 stream->timing.dsc_cfg = old_dsc_cfg;
2205                                 stream->timing.flags.DSC = old_dsc_enabled;
2206                                 update->dsc_config = NULL;
2207                         }
2208
2209                         dc_release_state(dsc_validate_context);
2210                 } else {
2211                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2212                         update->dsc_config = NULL;
2213                 }
2214         }
2215 }
2216
2217 static void commit_planes_do_stream_update(struct dc *dc,
2218                 struct dc_stream_state *stream,
2219                 struct dc_stream_update *stream_update,
2220                 enum surface_update_type update_type,
2221                 struct dc_state *context)
2222 {
2223         int j;
2224         bool should_program_abm;
2225
2226         // Stream updates
2227         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2228                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2229
2230                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2231
2232                         if (stream_update->periodic_interrupt0 &&
2233                                         dc->hwss.setup_periodic_interrupt)
2234                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2235
2236                         if (stream_update->periodic_interrupt1 &&
2237                                         dc->hwss.setup_periodic_interrupt)
2238                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2239
2240                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2241                                         stream_update->vrr_infopacket ||
2242                                         stream_update->vsc_infopacket ||
2243                                         stream_update->vsp_infopacket) {
2244                                 resource_build_info_frame(pipe_ctx);
2245                                 dc->hwss.update_info_frame(pipe_ctx);
2246                         }
2247
2248                         if (stream_update->hdr_static_metadata &&
2249                                         stream->use_dynamic_meta &&
2250                                         dc->hwss.set_dmdata_attributes &&
2251                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2252                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2253
2254                         if (stream_update->gamut_remap)
2255                                 dc_stream_set_gamut_remap(dc, stream);
2256
2257                         if (stream_update->output_csc_transform)
2258                                 dc_stream_program_csc_matrix(dc, stream);
2259
2260                         if (stream_update->dither_option) {
2261                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2262                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2263                                                                         &pipe_ctx->stream->bit_depth_params);
2264                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2265                                                 &stream->bit_depth_params,
2266                                                 &stream->clamping);
2267                                 while (odm_pipe) {
2268                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2269                                                         &stream->bit_depth_params,
2270                                                         &stream->clamping);
2271                                         odm_pipe = odm_pipe->next_odm_pipe;
2272                                 }
2273                         }
2274
2275                         /* Full fe update*/
2276                         if (update_type == UPDATE_TYPE_FAST)
2277                                 continue;
2278
2279                         if (stream_update->dsc_config)
2280                                 dp_update_dsc_config(pipe_ctx);
2281
2282                         if (stream_update->dpms_off) {
2283                                 if (*stream_update->dpms_off) {
2284                                         core_link_disable_stream(pipe_ctx);
2285                                         /* for dpms, keep acquired resources*/
2286                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2287                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2288
2289                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2290                                 } else {
2291                                         if (dc->optimize_seamless_boot_streams == 0)
2292                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2293
2294                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2295                                 }
2296                         }
2297
2298                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2299                                 should_program_abm = true;
2300
2301                                 // if otg funcs defined check if blanked before programming
2302                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2303                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2304                                                 should_program_abm = false;
2305
2306                                 if (should_program_abm) {
2307                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2308                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2309                                         } else {
2310                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2311                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2312                                         }
2313                                 }
2314                         }
2315                 }
2316         }
2317 }
2318
2319 static void commit_planes_for_stream(struct dc *dc,
2320                 struct dc_surface_update *srf_updates,
2321                 int surface_count,
2322                 struct dc_stream_state *stream,
2323                 struct dc_stream_update *stream_update,
2324                 enum surface_update_type update_type,
2325                 struct dc_state *context)
2326 {
2327         bool mpcc_disconnected = false;
2328         int i, j;
2329         struct pipe_ctx *top_pipe_to_program = NULL;
2330
2331         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2332                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2333                  * first flip. After first flip, optimization is required to lower
2334                  * bandwidth. Important to note that it is expected UEFI will
2335                  * only light up a single display on POST, therefore we only expect
2336                  * one stream with seamless boot flag set.
2337                  */
2338                 if (stream->apply_seamless_boot_optimization) {
2339                         stream->apply_seamless_boot_optimization = false;
2340                         dc->optimize_seamless_boot_streams--;
2341
2342                         if (dc->optimize_seamless_boot_streams == 0)
2343                                 dc->optimized_required = true;
2344                 }
2345         }
2346
2347         if (update_type == UPDATE_TYPE_FULL) {
2348 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2349                 dc_allow_idle_optimizations(dc, false);
2350
2351 #endif
2352                 if (dc->optimize_seamless_boot_streams == 0)
2353                         dc->hwss.prepare_bandwidth(dc, context);
2354
2355                 context_clock_trace(dc, context);
2356         }
2357
2358         if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
2359                 dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
2360                 dc->hwss.interdependent_update_lock(dc, context, true);
2361                 mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
2362                 dc->hwss.interdependent_update_lock(dc, context, false);
2363                 if (mpcc_disconnected)
2364                         dc->hwss.wait_for_pending_cleared(dc, context);
2365         }
2366
2367         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2368                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2369
2370                 if (!pipe_ctx->top_pipe &&
2371                         !pipe_ctx->prev_odm_pipe &&
2372                         pipe_ctx->stream &&
2373                         pipe_ctx->stream == stream) {
2374                         top_pipe_to_program = pipe_ctx;
2375                 }
2376         }
2377
2378         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2379                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2380                         if (should_use_dmub_lock(stream->link)) {
2381                                 union dmub_hw_lock_flags hw_locks = { 0 };
2382                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2383
2384                                 hw_locks.bits.lock_dig = 1;
2385                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2386
2387                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2388                                                         true,
2389                                                         &hw_locks,
2390                                                         &inst_flags);
2391                         } else
2392                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2393                                                 top_pipe_to_program->stream_res.tg);
2394                 }
2395
2396         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2397                 dc->hwss.interdependent_update_lock(dc, context, true);
2398         else
2399                 /* Lock the top pipe while updating plane addrs, since freesync requires
2400                  *  plane addr update event triggers to be synchronized.
2401                  *  top_pipe_to_program is expected to never be NULL
2402                  */
2403                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2404
2405
2406         // Stream updates
2407         if (stream_update)
2408                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2409
2410         if (surface_count == 0) {
2411                 /*
2412                  * In case of turning off screen, no need to program front end a second time.
2413                  * just return after program blank.
2414                  */
2415                 if (dc->hwss.apply_ctx_for_surface)
2416                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2417                 if (dc->hwss.program_front_end_for_ctx)
2418                         dc->hwss.program_front_end_for_ctx(dc, context);
2419
2420                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2421                         dc->hwss.interdependent_update_lock(dc, context, false);
2422                 else
2423                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2424
2425                 dc->hwss.post_unlock_program_front_end(dc, context);
2426                 return;
2427         }
2428
2429         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2430                 for (i = 0; i < surface_count; i++) {
2431                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2432                         /*set logical flag for lock/unlock use*/
2433                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2434                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2435                                 if (!pipe_ctx->plane_state)
2436                                         continue;
2437                                 if (pipe_ctx->plane_state != plane_state)
2438                                         continue;
2439                                 plane_state->triplebuffer_flips = false;
2440                                 if (update_type == UPDATE_TYPE_FAST &&
2441                                         dc->hwss.program_triplebuffer != NULL &&
2442                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2443                                                 /*triple buffer for VUpdate  only*/
2444                                                 plane_state->triplebuffer_flips = true;
2445                                 }
2446                         }
2447                 }
2448         }
2449
2450         // Update Type FULL, Surface updates
2451         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2452                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2453
2454                 if (!pipe_ctx->top_pipe &&
2455                         !pipe_ctx->prev_odm_pipe &&
2456                         pipe_ctx->stream &&
2457                         pipe_ctx->stream == stream) {
2458                         struct dc_stream_status *stream_status = NULL;
2459
2460                         if (!pipe_ctx->plane_state)
2461                                 continue;
2462
2463                         /* Full fe update*/
2464                         if (update_type == UPDATE_TYPE_FAST)
2465                                 continue;
2466
2467                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2468
2469                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2470                                 /*turn off triple buffer for full update*/
2471                                 dc->hwss.program_triplebuffer(
2472                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2473                         }
2474                         stream_status =
2475                                 stream_get_status(context, pipe_ctx->stream);
2476
2477                         if (dc->hwss.apply_ctx_for_surface)
2478                                 dc->hwss.apply_ctx_for_surface(
2479                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2480                 }
2481         }
2482         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2483                 dc->hwss.program_front_end_for_ctx(dc, context);
2484 #ifdef CONFIG_DRM_AMD_DC_DCN
2485                 if (dc->debug.validate_dml_output) {
2486                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2487                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2488                                 if (cur_pipe.stream == NULL)
2489                                         continue;
2490
2491                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2492                                                 cur_pipe.plane_res.hubp, dc->ctx,
2493                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2494                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2495                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2496                         }
2497                 }
2498 #endif
2499         }
2500
2501         // Update Type FAST, Surface updates
2502         if (update_type == UPDATE_TYPE_FAST) {
2503                 if (dc->hwss.set_flip_control_gsl)
2504                         for (i = 0; i < surface_count; i++) {
2505                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2506
2507                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2508                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2509
2510                                         if (pipe_ctx->stream != stream)
2511                                                 continue;
2512
2513                                         if (pipe_ctx->plane_state != plane_state)
2514                                                 continue;
2515
2516                                         // GSL has to be used for flip immediate
2517                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2518                                                         plane_state->flip_immediate);
2519                                 }
2520                         }
2521                 /* Perform requested Updates */
2522                 for (i = 0; i < surface_count; i++) {
2523                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2524
2525                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2526                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2527
2528                                 if (pipe_ctx->stream != stream)
2529                                         continue;
2530
2531                                 if (pipe_ctx->plane_state != plane_state)
2532                                         continue;
2533                                 /*program triple buffer after lock based on flip type*/
2534                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2535                                         /*only enable triplebuffer for  fast_update*/
2536                                         dc->hwss.program_triplebuffer(
2537                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2538                                 }
2539                                 if (srf_updates[i].flip_addr)
2540                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2541                         }
2542                 }
2543         }
2544
2545         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2546                 dc->hwss.interdependent_update_lock(dc, context, false);
2547         else
2548                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2549
2550         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2551                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2552                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2553                                         top_pipe_to_program->stream_res.tg,
2554                                         CRTC_STATE_VACTIVE);
2555                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2556                                         top_pipe_to_program->stream_res.tg,
2557                                         CRTC_STATE_VBLANK);
2558                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2559                                         top_pipe_to_program->stream_res.tg,
2560                                         CRTC_STATE_VACTIVE);
2561
2562                         if (stream && should_use_dmub_lock(stream->link)) {
2563                                 union dmub_hw_lock_flags hw_locks = { 0 };
2564                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2565
2566                                 hw_locks.bits.lock_dig = 1;
2567                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2568
2569                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2570                                                         false,
2571                                                         &hw_locks,
2572                                                         &inst_flags);
2573                         } else
2574                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2575                                         top_pipe_to_program->stream_res.tg);
2576                 }
2577
2578         if (update_type != UPDATE_TYPE_FAST)
2579                 dc->hwss.post_unlock_program_front_end(dc, context);
2580
2581         // Fire manual trigger only when bottom plane is flipped
2582         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2583                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2584
2585                 if (pipe_ctx->bottom_pipe ||
2586                                 !pipe_ctx->stream ||
2587                                 pipe_ctx->stream != stream ||
2588                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2589                         continue;
2590
2591                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2592                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2593         }
2594 }
2595
2596 void dc_commit_updates_for_stream(struct dc *dc,
2597                 struct dc_surface_update *srf_updates,
2598                 int surface_count,
2599                 struct dc_stream_state *stream,
2600                 struct dc_stream_update *stream_update,
2601                 struct dc_state *state)
2602 {
2603         const struct dc_stream_status *stream_status;
2604         enum surface_update_type update_type;
2605         struct dc_state *context;
2606         struct dc_context *dc_ctx = dc->ctx;
2607         int i, j;
2608
2609         stream_status = dc_stream_get_status(stream);
2610         context = dc->current_state;
2611
2612         update_type = dc_check_update_surfaces_for_stream(
2613                                 dc, srf_updates, surface_count, stream_update, stream_status);
2614
2615         if (update_type >= update_surface_trace_level)
2616                 update_surface_trace(dc, srf_updates, surface_count);
2617
2618
2619         if (update_type >= UPDATE_TYPE_FULL) {
2620
2621                 /* initialize scratch memory for building context */
2622                 context = dc_create_state(dc);
2623                 if (context == NULL) {
2624                         DC_ERROR("Failed to allocate new validate context!\n");
2625                         return;
2626                 }
2627
2628                 dc_resource_state_copy_construct(state, context);
2629
2630                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2631                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2632                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2633
2634                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2635                                 new_pipe->plane_state->force_full_update = true;
2636                 }
2637         }
2638
2639
2640         for (i = 0; i < surface_count; i++) {
2641                 struct dc_plane_state *surface = srf_updates[i].surface;
2642
2643                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2644
2645                 if (update_type >= UPDATE_TYPE_MED) {
2646                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2647                                 struct pipe_ctx *pipe_ctx =
2648                                         &context->res_ctx.pipe_ctx[j];
2649
2650                                 if (pipe_ctx->plane_state != surface)
2651                                         continue;
2652
2653                                 resource_build_scaling_params(pipe_ctx);
2654                         }
2655                 }
2656         }
2657
2658         copy_stream_update_to_stream(dc, context, stream, stream_update);
2659
2660         if (update_type >= UPDATE_TYPE_FULL) {
2661                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2662                         DC_ERROR("Mode validation failed for stream update!\n");
2663                         dc_release_state(context);
2664                         return;
2665                 }
2666         }
2667
2668         commit_planes_for_stream(
2669                                 dc,
2670                                 srf_updates,
2671                                 surface_count,
2672                                 stream,
2673                                 stream_update,
2674                                 update_type,
2675                                 context);
2676         /*update current_State*/
2677         if (dc->current_state != context) {
2678
2679                 struct dc_state *old = dc->current_state;
2680
2681                 dc->current_state = context;
2682                 dc_release_state(old);
2683
2684                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2685                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2686
2687                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2688                                 pipe_ctx->plane_state->force_full_update = false;
2689                 }
2690         }
2691         /*let's use current_state to update watermark etc*/
2692         if (update_type >= UPDATE_TYPE_FULL)
2693                 dc_post_update_surfaces_to_stream(dc);
2694
2695         return;
2696
2697 }
2698
2699 uint8_t dc_get_current_stream_count(struct dc *dc)
2700 {
2701         return dc->current_state->stream_count;
2702 }
2703
2704 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2705 {
2706         if (i < dc->current_state->stream_count)
2707                 return dc->current_state->streams[i];
2708         return NULL;
2709 }
2710
2711 enum dc_irq_source dc_interrupt_to_irq_source(
2712                 struct dc *dc,
2713                 uint32_t src_id,
2714                 uint32_t ext_id)
2715 {
2716         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2717 }
2718
2719 /**
2720  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2721  */
2722 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2723 {
2724
2725         if (dc == NULL)
2726                 return false;
2727
2728         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2729 }
2730
2731 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2732 {
2733         dal_irq_service_ack(dc->res_pool->irqs, src);
2734 }
2735
2736 void dc_power_down_on_boot(struct dc *dc)
2737 {
2738         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
2739                         dc->hwss.power_down_on_boot)
2740                 dc->hwss.power_down_on_boot(dc);
2741 }
2742
2743 void dc_set_power_state(
2744         struct dc *dc,
2745         enum dc_acpi_cm_power_state power_state)
2746 {
2747         struct kref refcount;
2748         struct display_mode_lib *dml;
2749
2750         switch (power_state) {
2751         case DC_ACPI_CM_POWER_STATE_D0:
2752                 dc_resource_state_construct(dc, dc->current_state);
2753
2754                 if (dc->ctx->dmub_srv)
2755                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2756
2757                 dc->hwss.init_hw(dc);
2758
2759                 if (dc->hwss.init_sys_ctx != NULL &&
2760                         dc->vm_pa_config.valid) {
2761                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2762                 }
2763
2764                 break;
2765         default:
2766                 ASSERT(dc->current_state->stream_count == 0);
2767                 /* Zero out the current context so that on resume we start with
2768                  * clean state, and dc hw programming optimizations will not
2769                  * cause any trouble.
2770                  */
2771                 dml = kzalloc(sizeof(struct display_mode_lib),
2772                                 GFP_KERNEL);
2773
2774                 ASSERT(dml);
2775                 if (!dml)
2776                         return;
2777
2778                 /* Preserve refcount */
2779                 refcount = dc->current_state->refcount;
2780                 /* Preserve display mode lib */
2781                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2782
2783                 dc_resource_state_destruct(dc->current_state);
2784                 memset(dc->current_state, 0,
2785                                 sizeof(*dc->current_state));
2786
2787                 dc->current_state->refcount = refcount;
2788                 dc->current_state->bw_ctx.dml = *dml;
2789
2790                 kfree(dml);
2791
2792                 break;
2793         }
2794 }
2795
2796 void dc_resume(struct dc *dc)
2797 {
2798         uint32_t i;
2799
2800         for (i = 0; i < dc->link_count; i++)
2801                 core_link_resume(dc->links[i]);
2802 }
2803
2804 bool dc_is_dmcu_initialized(struct dc *dc)
2805 {
2806         struct dmcu *dmcu = dc->res_pool->dmcu;
2807
2808         if (dmcu)
2809                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2810         return false;
2811 }
2812
2813 bool dc_submit_i2c(
2814                 struct dc *dc,
2815                 uint32_t link_index,
2816                 struct i2c_command *cmd)
2817 {
2818
2819         struct dc_link *link = dc->links[link_index];
2820         struct ddc_service *ddc = link->ddc;
2821         return dce_i2c_submit_command(
2822                 dc->res_pool,
2823                 ddc->ddc_pin,
2824                 cmd);
2825 }
2826
2827 bool dc_submit_i2c_oem(
2828                 struct dc *dc,
2829                 struct i2c_command *cmd)
2830 {
2831         struct ddc_service *ddc = dc->res_pool->oem_device;
2832         return dce_i2c_submit_command(
2833                 dc->res_pool,
2834                 ddc->ddc_pin,
2835                 cmd);
2836 }
2837
2838 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2839 {
2840         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2841                 BREAK_TO_DEBUGGER();
2842                 return false;
2843         }
2844
2845         dc_sink_retain(sink);
2846
2847         dc_link->remote_sinks[dc_link->sink_count] = sink;
2848         dc_link->sink_count++;
2849
2850         return true;
2851 }
2852
2853 /**
2854  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2855  *
2856  * EDID length is in bytes
2857  */
2858 struct dc_sink *dc_link_add_remote_sink(
2859                 struct dc_link *link,
2860                 const uint8_t *edid,
2861                 int len,
2862                 struct dc_sink_init_data *init_data)
2863 {
2864         struct dc_sink *dc_sink;
2865         enum dc_edid_status edid_status;
2866
2867         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2868                 dm_error("Max EDID buffer size breached!\n");
2869                 return NULL;
2870         }
2871
2872         if (!init_data) {
2873                 BREAK_TO_DEBUGGER();
2874                 return NULL;
2875         }
2876
2877         if (!init_data->link) {
2878                 BREAK_TO_DEBUGGER();
2879                 return NULL;
2880         }
2881
2882         dc_sink = dc_sink_create(init_data);
2883
2884         if (!dc_sink)
2885                 return NULL;
2886
2887         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2888         dc_sink->dc_edid.length = len;
2889
2890         if (!link_add_remote_sink_helper(
2891                         link,
2892                         dc_sink))
2893                 goto fail_add_sink;
2894
2895         edid_status = dm_helpers_parse_edid_caps(
2896                         link->ctx,
2897                         &dc_sink->dc_edid,
2898                         &dc_sink->edid_caps);
2899
2900         /*
2901          * Treat device as no EDID device if EDID
2902          * parsing fails
2903          */
2904         if (edid_status != EDID_OK) {
2905                 dc_sink->dc_edid.length = 0;
2906                 dm_error("Bad EDID, status%d!\n", edid_status);
2907         }
2908
2909         return dc_sink;
2910
2911 fail_add_sink:
2912         dc_sink_release(dc_sink);
2913         return NULL;
2914 }
2915
2916 /**
2917  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2918  *
2919  * Note that this just removes the struct dc_sink - it doesn't
2920  * program hardware or alter other members of dc_link
2921  */
2922 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2923 {
2924         int i;
2925
2926         if (!link->sink_count) {
2927                 BREAK_TO_DEBUGGER();
2928                 return;
2929         }
2930
2931         for (i = 0; i < link->sink_count; i++) {
2932                 if (link->remote_sinks[i] == sink) {
2933                         dc_sink_release(sink);
2934                         link->remote_sinks[i] = NULL;
2935
2936                         /* shrink array to remove empty place */
2937                         while (i < link->sink_count - 1) {
2938                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2939                                 i++;
2940                         }
2941                         link->remote_sinks[i] = NULL;
2942                         link->sink_count--;
2943                         return;
2944                 }
2945         }
2946 }
2947
2948 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2949 {
2950         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2951         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2952         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2953         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2954         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
2955         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
2956         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
2957         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
2958         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
2959 }
2960 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
2961 {
2962         if (dc->hwss.set_clock)
2963                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
2964         return DC_ERROR_UNEXPECTED;
2965 }
2966 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
2967 {
2968         if (dc->hwss.get_clock)
2969                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
2970 }
2971
2972 /* enable/disable eDP PSR without specify stream for eDP */
2973 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
2974 {
2975         int i;
2976
2977         for (i = 0; i < dc->current_state->stream_count ; i++) {
2978                 struct dc_link *link;
2979                 struct dc_stream_state *stream = dc->current_state->streams[i];
2980
2981                 link = stream->link;
2982                 if (!link)
2983                         continue;
2984
2985                 if (link->psr_settings.psr_feature_enabled) {
2986                         if (enable && !link->psr_settings.psr_allow_active)
2987                                 return dc_link_set_psr_allow_active(link, true, false);
2988                         else if (!enable && link->psr_settings.psr_allow_active)
2989                                 return dc_link_set_psr_allow_active(link, false, true);
2990                 }
2991         }
2992
2993         return true;
2994 }
2995
2996 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2997
2998 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
2999 {
3000         if (dc->debug.disable_idle_power_optimizations)
3001                 return;
3002
3003         if (allow == dc->idle_optimizations_allowed)
3004                 return;
3005
3006         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3007                 dc->idle_optimizations_allowed = allow;
3008 }
3009
3010 /*
3011  * blank all streams, and set min and max memory clock to
3012  * lowest and highest DPM level, respectively
3013  */
3014 void dc_unlock_memory_clock_frequency(struct dc *dc)
3015 {
3016         unsigned int i;
3017
3018         for (i = 0; i < MAX_PIPES; i++)
3019                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3020                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3021
3022         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3023         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3024 }
3025
3026 /*
3027  * set min memory clock to the min required for current mode,
3028  * max to maxDPM, and unblank streams
3029  */
3030 void dc_lock_memory_clock_frequency(struct dc *dc)
3031 {
3032         unsigned int i;
3033
3034         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3035         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3036         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3037
3038         for (i = 0; i < MAX_PIPES; i++)
3039                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3040                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3041 }
3042
3043 bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,
3044                                                  struct dc_plane_state *plane)
3045 {
3046         return false;
3047 }
3048 #endif