2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/slab.h>
28 #include "dm_services.h"
32 #include "core_status.h"
33 #include "core_types.h"
34 #include "hw_sequencer.h"
35 #include "dce/dce_hwseq.h"
40 #include "clock_source.h"
41 #include "dc_bios_types.h"
43 #include "bios_parser_interface.h"
44 #include "include/irq_service_interface.h"
45 #include "transform.h"
48 #include "timing_generator.h"
50 #include "virtual/virtual_link_encoder.h"
52 #include "link_hwss.h"
53 #include "link_encoder.h"
55 #include "dc_link_ddc.h"
56 #include "dm_helpers.h"
57 #include "mem_input.h"
60 #include "dc_link_dp.h"
61 #include "dc_dmub_srv.h"
65 #include "vm_helper.h"
67 #include "dce/dce_i2c.h"
72 const static char DC_BUILD_ID[] = "production-build";
77 * DC is the OS-agnostic component of the amdgpu DC driver.
79 * DC maintains and validates a set of structs representing the state of the
80 * driver and writes that state to AMD hardware
84 * struct dc - The central struct. One per driver. Created on driver load,
85 * destroyed on driver unload.
87 * struct dc_context - One per driver.
88 * Used as a backpointer by most other structs in dc.
90 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
91 * plugpoints). Created on driver load, destroyed on driver unload.
93 * struct dc_sink - One per display. Created on boot or hotplug.
94 * Destroyed on shutdown or hotunplug. A dc_link can have a local sink
95 * (the display directly attached). It may also have one or more remote
96 * sinks (in the Multi-Stream Transport case)
98 * struct resource_pool - One per driver. Represents the hw blocks not in the
99 * main pipeline. Not directly accessible by dm.
101 * Main dc state structs:
103 * These structs can be created and destroyed as needed. There is a full set of
104 * these structs in dc->current_state representing the currently programmed state.
106 * struct dc_state - The global DC state to track global state information,
107 * such as bandwidth values.
109 * struct dc_stream_state - Represents the hw configuration for the pipeline from
110 * a framebuffer to a display. Maps one-to-one with dc_sink.
112 * struct dc_plane_state - Represents a framebuffer. Each stream has at least one,
113 * and may have more in the Multi-Plane Overlay case.
115 * struct resource_context - Represents the programmable state of everything in
116 * the resource_pool. Not directly accessible by dm.
118 * struct pipe_ctx - A member of struct resource_context. Represents the
119 * internal hardware pipeline components. Each dc_plane_state has either
120 * one or two (in the pipe-split case).
123 /*******************************************************************************
125 ******************************************************************************/
127 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
133 static void destroy_links(struct dc *dc)
137 for (i = 0; i < dc->link_count; i++) {
138 if (NULL != dc->links[i])
139 link_destroy(&dc->links[i]);
143 static bool create_links(
145 uint32_t num_virtual_links)
149 struct dc_bios *bios = dc->ctx->dc_bios;
153 connectors_num = bios->funcs->get_connectors_number(bios);
155 if (connectors_num > ENUM_ID_COUNT) {
157 "DC: Number of connectors %d exceeds maximum of %d!\n",
163 dm_output_to_console(
164 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
169 for (i = 0; i < connectors_num; i++) {
170 struct link_init_data link_init_params = {0};
171 struct dc_link *link;
173 link_init_params.ctx = dc->ctx;
174 /* next BIOS object table connector */
175 link_init_params.connector_index = i;
176 link_init_params.link_index = dc->link_count;
177 link_init_params.dc = dc;
178 link = link_create(&link_init_params);
181 bool should_destory_link = false;
183 if (link->connector_signal == SIGNAL_TYPE_EDP) {
184 if (dc->config.edp_not_connected)
185 should_destory_link = true;
186 else if (dc->debug.remove_disconnect_edp) {
187 enum dc_connection_type type;
188 dc_link_detect_sink(link, &type);
189 if (type == dc_connection_none)
190 should_destory_link = true;
194 if (dc->config.force_enum_edp || !should_destory_link) {
195 dc->links[dc->link_count] = link;
204 for (i = 0; i < num_virtual_links; i++) {
205 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
206 struct encoder_init_data enc_init = {0};
213 link->link_index = dc->link_count;
214 dc->links[dc->link_count] = link;
219 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
220 link->link_id.type = OBJECT_TYPE_CONNECTOR;
221 link->link_id.id = CONNECTOR_ID_VIRTUAL;
222 link->link_id.enum_id = ENUM_ID_1;
223 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
225 if (!link->link_enc) {
230 link->link_status.dpcd_caps = &link->dpcd_caps;
232 enc_init.ctx = dc->ctx;
233 enc_init.channel = CHANNEL_ID_UNKNOWN;
234 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
235 enc_init.transmitter = TRANSMITTER_UNKNOWN;
236 enc_init.connector = link->link_id;
237 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
238 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
239 enc_init.encoder.enum_id = ENUM_ID_1;
240 virtual_link_encoder_construct(link->link_enc, &enc_init);
249 static struct dc_perf_trace *dc_perf_trace_create(void)
251 return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
254 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
261 *****************************************************************************
262 * Function: dc_stream_adjust_vmin_vmax
265 * Looks up the pipe context of dc_stream_state and updates the
266 * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
267 * Rate, which is a power-saving feature that targets reducing panel
268 * refresh rate while the screen is static
270 * @param [in] dc: dc reference
271 * @param [in] stream: Initial dc stream state
272 * @param [in] adjust: Updated parameters for vertical_total_min and
274 *****************************************************************************
276 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
277 struct dc_stream_state *stream,
278 struct dc_crtc_timing_adjust *adjust)
283 for (i = 0; i < MAX_PIPES; i++) {
284 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
286 if (pipe->stream == stream && pipe->stream_res.tg) {
287 pipe->stream->adjust = *adjust;
288 dc->hwss.set_drr(&pipe,
293 adjust->v_total_mid_frame_num);
301 bool dc_stream_get_crtc_position(struct dc *dc,
302 struct dc_stream_state **streams, int num_streams,
303 unsigned int *v_pos, unsigned int *nom_v_pos)
305 /* TODO: Support multiple streams */
306 const struct dc_stream_state *stream = streams[0];
309 struct crtc_position position;
311 for (i = 0; i < MAX_PIPES; i++) {
312 struct pipe_ctx *pipe =
313 &dc->current_state->res_ctx.pipe_ctx[i];
315 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
316 dc->hwss.get_position(&pipe, 1, &position);
318 *v_pos = position.vertical_count;
319 *nom_v_pos = position.nominal_vcount;
327 * dc_stream_configure_crc() - Configure CRC capture for the given stream.
329 * @stream: The stream to configure CRC on.
330 * @enable: Enable CRC if true, disable otherwise.
331 * @continuous: Capture CRC on every frame if true. Otherwise, only capture
334 * By default, only CRC0 is configured, and the entire frame is used to
337 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
338 bool enable, bool continuous)
341 struct pipe_ctx *pipe;
342 struct crc_params param;
343 struct timing_generator *tg;
345 for (i = 0; i < MAX_PIPES; i++) {
346 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
347 if (pipe->stream == stream)
350 /* Stream not found */
354 /* Always capture the full frame */
355 param.windowa_x_start = 0;
356 param.windowa_y_start = 0;
357 param.windowa_x_end = pipe->stream->timing.h_addressable;
358 param.windowa_y_end = pipe->stream->timing.v_addressable;
359 param.windowb_x_start = 0;
360 param.windowb_y_start = 0;
361 param.windowb_x_end = pipe->stream->timing.h_addressable;
362 param.windowb_y_end = pipe->stream->timing.v_addressable;
364 /* Default to the union of both windows */
365 param.selection = UNION_WINDOW_A_B;
366 param.continuous_mode = continuous;
367 param.enable = enable;
369 tg = pipe->stream_res.tg;
371 /* Only call if supported */
372 if (tg->funcs->configure_crc)
373 return tg->funcs->configure_crc(tg, ¶m);
374 DC_LOG_WARNING("CRC capture not supported.");
379 * dc_stream_get_crc() - Get CRC values for the given stream.
381 * @stream: The DC stream state of the stream to get CRCs from.
382 * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
384 * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
385 * Return false if stream is not found, or if CRCs are not enabled.
387 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
388 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
391 struct pipe_ctx *pipe;
392 struct timing_generator *tg;
394 for (i = 0; i < MAX_PIPES; i++) {
395 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
396 if (pipe->stream == stream)
399 /* Stream not found */
403 tg = pipe->stream_res.tg;
405 if (tg->funcs->get_crc)
406 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
407 DC_LOG_WARNING("CRC capture not supported.");
411 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
412 enum dc_dynamic_expansion option)
414 /* OPP FMT dyn expansion updates*/
416 struct pipe_ctx *pipe_ctx;
418 for (i = 0; i < MAX_PIPES; i++) {
419 if (dc->current_state->res_ctx.pipe_ctx[i].stream
421 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
422 pipe_ctx->stream_res.opp->dyn_expansion = option;
423 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
424 pipe_ctx->stream_res.opp,
425 COLOR_SPACE_YCBCR601,
426 stream->timing.display_color_depth,
432 void dc_stream_set_dither_option(struct dc_stream_state *stream,
433 enum dc_dither_option option)
435 struct bit_depth_reduction_params params;
436 struct dc_link *link = stream->link;
437 struct pipe_ctx *pipes = NULL;
440 for (i = 0; i < MAX_PIPES; i++) {
441 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
443 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
450 if (option > DITHER_OPTION_MAX)
453 stream->dither_option = option;
455 memset(¶ms, 0, sizeof(params));
456 resource_build_bit_depth_reduction_params(stream, ¶ms);
457 stream->bit_depth_params = params;
459 if (pipes->plane_res.xfm &&
460 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
461 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
462 pipes->plane_res.xfm,
463 pipes->plane_res.scl_data.lb_params.depth,
464 &stream->bit_depth_params);
467 pipes->stream_res.opp->funcs->
468 opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms);
471 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
475 struct pipe_ctx *pipes;
477 for (i = 0; i < MAX_PIPES; i++) {
478 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
479 pipes = &dc->current_state->res_ctx.pipe_ctx[i];
480 dc->hwss.program_gamut_remap(pipes);
488 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
492 struct pipe_ctx *pipes;
494 for (i = 0; i < MAX_PIPES; i++) {
495 if (dc->current_state->res_ctx.pipe_ctx[i].stream
498 pipes = &dc->current_state->res_ctx.pipe_ctx[i];
499 dc->hwss.program_output_csc(dc,
501 stream->output_color_space,
502 stream->csc_color_matrix.matrix,
503 pipes->stream_res.opp->inst);
511 void dc_stream_set_static_screen_events(struct dc *dc,
512 struct dc_stream_state **streams,
514 const struct dc_static_screen_events *events)
518 struct pipe_ctx *pipes_affected[MAX_PIPES];
519 int num_pipes_affected = 0;
521 for (i = 0; i < num_streams; i++) {
522 struct dc_stream_state *stream = streams[i];
524 for (j = 0; j < MAX_PIPES; j++) {
525 if (dc->current_state->res_ctx.pipe_ctx[j].stream
527 pipes_affected[num_pipes_affected++] =
528 &dc->current_state->res_ctx.pipe_ctx[j];
533 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
536 static void destruct(struct dc *dc)
538 if (dc->current_state) {
539 dc_release_state(dc->current_state);
540 dc->current_state = NULL;
546 dc_destroy_clk_mgr(dc->clk_mgr);
550 dc_destroy_resource_pool(dc);
552 if (dc->ctx->gpio_service)
553 dal_gpio_service_destroy(&dc->ctx->gpio_service);
555 if (dc->ctx->created_bios)
556 dal_bios_parser_destroy(&dc->ctx->dc_bios);
558 dc_perf_trace_destroy(&dc->ctx->perf_trace);
569 #ifdef CONFIG_DRM_AMD_DC_DCN
577 kfree(dc->vm_helper);
578 dc->vm_helper = NULL;
582 static bool construct(struct dc *dc,
583 const struct dc_init_data *init_params)
585 struct dc_context *dc_ctx;
586 struct bw_calcs_dceip *dc_dceip;
587 struct bw_calcs_vbios *dc_vbios;
588 #ifdef CONFIG_DRM_AMD_DC_DCN
589 struct dcn_soc_bounding_box *dcn_soc;
590 struct dcn_ip_params *dcn_ip;
593 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
594 dc->config = init_params->flags;
596 // Allocate memory for the vm_helper
597 dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
598 if (!dc->vm_helper) {
599 dm_error("%s: failed to create dc->vm_helper\n", __func__);
603 memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
605 dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
607 dm_error("%s: failed to create dceip\n", __func__);
611 dc->bw_dceip = dc_dceip;
613 dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
615 dm_error("%s: failed to create vbios\n", __func__);
619 dc->bw_vbios = dc_vbios;
620 #ifdef CONFIG_DRM_AMD_DC_DCN
621 dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
623 dm_error("%s: failed to create dcn_soc\n", __func__);
627 dc->dcn_soc = dcn_soc;
629 dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
631 dm_error("%s: failed to create dcn_ip\n", __func__);
636 dc->soc_bounding_box = init_params->soc_bounding_box;
639 dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
641 dm_error("%s: failed to create ctx\n", __func__);
645 dc_ctx->cgs_device = init_params->cgs_device;
646 dc_ctx->driver_context = init_params->driver;
648 dc_ctx->asic_id = init_params->asic_id;
649 dc_ctx->dc_sink_id_count = 0;
650 dc_ctx->dc_stream_id_count = 0;
655 dc_ctx->dce_environment = init_params->dce_environment;
657 dc_version = resource_parse_asic_id(init_params->asic_id);
658 dc_ctx->dce_version = dc_version;
660 /* Resource should construct all asic specific resources.
661 * This should be the only place where we need to parse the asic id
663 if (init_params->vbios_override)
664 dc_ctx->dc_bios = init_params->vbios_override;
666 /* Create BIOS parser */
667 struct bp_init_data bp_init_data;
669 bp_init_data.ctx = dc_ctx;
670 bp_init_data.bios = init_params->asic_id.atombios_base_address;
672 dc_ctx->dc_bios = dal_bios_parser_create(
673 &bp_init_data, dc_version);
675 if (!dc_ctx->dc_bios) {
676 ASSERT_CRITICAL(false);
680 dc_ctx->created_bios = true;
683 dc_ctx->perf_trace = dc_perf_trace_create();
684 if (!dc_ctx->perf_trace) {
685 ASSERT_CRITICAL(false);
689 /* Create GPIO service */
690 dc_ctx->gpio_service = dal_gpio_service_create(
692 dc_ctx->dce_environment,
695 if (!dc_ctx->gpio_service) {
696 ASSERT_CRITICAL(false);
700 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
704 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
708 if (dc->res_pool->funcs->update_bw_bounding_box)
709 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
711 /* Creation of current_state must occur after dc->dml
712 * is initialized in dc_create_resource_pool because
713 * on creation it copies the contents of dc->dml
716 dc->current_state = dc_create_state(dc);
718 if (!dc->current_state) {
719 dm_error("%s: failed to create validate ctx\n", __func__);
723 dc_resource_state_construct(dc, dc->current_state);
725 if (!create_links(dc, init_params->num_virtual_links))
736 static bool disable_all_writeback_pipes_for_stream(
738 struct dc_stream_state *stream,
739 struct dc_state *context)
743 for (i = 0; i < stream->num_wb_info; i++)
744 stream->writeback_info[i].wb_enabled = false;
749 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
752 struct dc_state *dangling_context = dc_create_state(dc);
753 struct dc_state *current_ctx;
755 if (dangling_context == NULL)
758 dc_resource_state_copy_construct(dc->current_state, dangling_context);
760 for (i = 0; i < dc->res_pool->pipe_count; i++) {
761 struct dc_stream_state *old_stream =
762 dc->current_state->res_ctx.pipe_ctx[i].stream;
763 bool should_disable = true;
765 for (j = 0; j < context->stream_count; j++) {
766 if (old_stream == context->streams[j]) {
767 should_disable = false;
771 if (should_disable && old_stream) {
772 dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
773 disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
774 if (dc->hwss.apply_ctx_for_surface)
775 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
777 if (dc->hwss.program_front_end_for_ctx)
778 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
781 current_ctx = dc->current_state;
782 dc->current_state = dangling_context;
783 dc_release_state(current_ctx);
786 /*******************************************************************************
788 ******************************************************************************/
790 struct dc *dc_create(const struct dc_init_data *init_params)
792 struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
793 unsigned int full_pipe_count;
798 if (false == construct(dc, init_params))
801 full_pipe_count = dc->res_pool->pipe_count;
802 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
804 dc->caps.max_streams = min(
806 dc->res_pool->stream_enc_count);
808 dc->caps.max_links = dc->link_count;
809 dc->caps.max_audios = dc->res_pool->audio_count;
810 dc->caps.linear_pitch_alignment = 64;
812 /* Populate versioning information */
813 dc->versions.dc_ver = DC_VER;
815 if (dc->res_pool->dmcu != NULL)
816 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
818 dc->build_id = DC_BUILD_ID;
820 DC_LOG_DC("Display Core initialized\n");
833 void dc_hardware_init(struct dc *dc)
835 dc->hwss.init_hw(dc);
838 void dc_init_callbacks(struct dc *dc,
839 const struct dc_callback_init *init_params)
841 #ifdef CONFIG_DRM_AMD_DC_HDCP
842 dc->ctx->cp_psp = init_params->cp_psp;
846 void dc_deinit_callbacks(struct dc *dc)
848 #ifdef CONFIG_DRM_AMD_DC_HDCP
849 memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
853 void dc_destroy(struct dc **dc)
860 static void enable_timing_multisync(
862 struct dc_state *ctx)
864 int i = 0, multisync_count = 0;
865 int pipe_count = dc->res_pool->pipe_count;
866 struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
868 for (i = 0; i < pipe_count; i++) {
869 if (!ctx->res_ctx.pipe_ctx[i].stream ||
870 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
872 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
874 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
878 if (multisync_count > 0) {
879 dc->hwss.enable_per_frame_crtc_position_reset(
880 dc, multisync_count, multisync_pipes);
884 static void program_timing_sync(
886 struct dc_state *ctx)
891 int pipe_count = dc->res_pool->pipe_count;
892 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
894 for (i = 0; i < pipe_count; i++) {
895 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
898 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
901 for (i = 0; i < pipe_count; i++) {
903 struct pipe_ctx *pipe_set[MAX_PIPES];
905 if (!unsynced_pipes[i])
908 pipe_set[0] = unsynced_pipes[i];
909 unsynced_pipes[i] = NULL;
911 /* Add tg to the set, search rest of the tg's for ones with
912 * same timing, add all tgs with same timing to the group
914 for (j = i + 1; j < pipe_count; j++) {
915 if (!unsynced_pipes[j])
918 if (resource_are_streams_timing_synchronizable(
919 unsynced_pipes[j]->stream,
920 pipe_set[0]->stream)) {
921 pipe_set[group_size] = unsynced_pipes[j];
922 unsynced_pipes[j] = NULL;
927 /* set first pipe with plane as master */
928 for (j = 0; j < group_size; j++) {
929 if (pipe_set[j]->plane_state) {
933 swap(pipe_set[0], pipe_set[j]);
939 for (k = 0; k < group_size; k++) {
940 struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
942 status->timing_sync_info.group_id = num_group;
943 status->timing_sync_info.group_size = group_size;
945 status->timing_sync_info.master = true;
947 status->timing_sync_info.master = false;
950 /* remove any other pipes with plane as they have already been synced */
951 for (j = j + 1; j < group_size; j++) {
952 if (pipe_set[j]->plane_state) {
954 pipe_set[j] = pipe_set[group_size];
959 if (group_size > 1) {
960 dc->hwss.enable_timing_synchronization(
961 dc, group_index, group_size, pipe_set);
968 static bool context_changed(
970 struct dc_state *context)
974 if (context->stream_count != dc->current_state->stream_count)
977 for (i = 0; i < dc->current_state->stream_count; i++) {
978 if (dc->current_state->streams[i] != context->streams[i])
985 bool dc_validate_seamless_boot_timing(const struct dc *dc,
986 const struct dc_sink *sink,
987 struct dc_crtc_timing *crtc_timing)
989 struct timing_generator *tg;
990 struct stream_encoder *se = NULL;
992 struct dc_crtc_timing hw_crtc_timing = {0};
994 struct dc_link *link = sink->link;
995 unsigned int i, enc_inst, tg_inst = 0;
997 // Seamless port only support single DP and EDP so far
998 if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
999 sink->sink_signal != SIGNAL_TYPE_EDP)
1002 /* Check for enabled DIG to identify enabled display */
1003 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1006 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1008 if (enc_inst == ENGINE_ID_UNKNOWN)
1011 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1012 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1014 se = dc->res_pool->stream_enc[i];
1016 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1017 dc->res_pool->stream_enc[i]);
1022 // tg_inst not found
1023 if (i == dc->res_pool->stream_enc_count)
1026 if (tg_inst >= dc->res_pool->timing_generator_count)
1029 tg = dc->res_pool->timing_generators[tg_inst];
1031 if (!tg->funcs->get_hw_timing)
1034 if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1037 if (crtc_timing->h_total != hw_crtc_timing.h_total)
1040 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1043 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1046 if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1049 if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1052 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1055 if (crtc_timing->v_total != hw_crtc_timing.v_total)
1058 if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1061 if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1064 if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1067 if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1070 if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1073 if (dc_is_dp_signal(link->connector_signal)) {
1074 unsigned int pix_clk_100hz;
1076 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1077 dc->res_pool->dp_clock_source,
1078 tg_inst, &pix_clk_100hz);
1080 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1083 if (!se->funcs->dp_get_pixel_format)
1086 if (!se->funcs->dp_get_pixel_format(
1088 &hw_crtc_timing.pixel_encoding,
1089 &hw_crtc_timing.display_color_depth))
1092 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1095 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1102 bool dc_enable_stereo(
1104 struct dc_state *context,
1105 struct dc_stream_state *streams[],
1106 uint8_t stream_count)
1110 struct pipe_ctx *pipe;
1112 for (i = 0; i < MAX_PIPES; i++) {
1113 if (context != NULL)
1114 pipe = &context->res_ctx.pipe_ctx[i];
1116 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1117 for (j = 0 ; pipe && j < stream_count; j++) {
1118 if (streams[j] && streams[j] == pipe->stream &&
1119 dc->hwss.setup_stereo)
1120 dc->hwss.setup_stereo(pipe, dc);
1128 * Applies given context to HW and copy it into current context.
1129 * It's up to the user to release the src context afterwards.
1131 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1133 struct dc_bios *dcb = dc->ctx->dc_bios;
1134 enum dc_status result = DC_ERROR_UNEXPECTED;
1135 struct pipe_ctx *pipe;
1137 struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1139 disable_dangling_plane(dc, context);
1141 for (i = 0; i < context->stream_count; i++)
1142 dc_streams[i] = context->streams[i];
1144 if (!dcb->funcs->is_accelerated_mode(dcb))
1145 dc->hwss.enable_accelerated_mode(dc, context);
1147 for (i = 0; i < context->stream_count; i++) {
1148 if (context->streams[i]->apply_seamless_boot_optimization)
1149 dc->optimize_seamless_boot = true;
1152 if (!dc->optimize_seamless_boot)
1153 dc->hwss.prepare_bandwidth(dc, context);
1155 /* re-program planes for existing stream, in case we need to
1156 * free up plane resource for later use
1158 if (dc->hwss.apply_ctx_for_surface)
1159 for (i = 0; i < context->stream_count; i++) {
1160 if (context->streams[i]->mode_changed)
1163 dc->hwss.apply_ctx_for_surface(
1164 dc, context->streams[i],
1165 context->stream_status[i].plane_count,
1166 context); /* use new pipe config in new context */
1168 if (dc->hwss.program_front_end_for_ctx)
1169 dc->hwss.program_front_end_for_ctx(dc, context);
1171 /* Program hardware */
1172 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1173 pipe = &context->res_ctx.pipe_ctx[i];
1174 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1177 result = dc->hwss.apply_ctx_to_hw(dc, context);
1179 if (result != DC_OK)
1182 if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1183 enable_timing_multisync(dc, context);
1184 program_timing_sync(dc, context);
1187 /* Program all planes within new context*/
1188 if (dc->hwss.program_front_end_for_ctx)
1189 dc->hwss.program_front_end_for_ctx(dc, context);
1190 for (i = 0; i < context->stream_count; i++) {
1191 const struct dc_link *link = context->streams[i]->link;
1193 if (!context->streams[i]->mode_changed)
1196 if (dc->hwss.apply_ctx_for_surface)
1197 dc->hwss.apply_ctx_for_surface(
1198 dc, context->streams[i],
1199 context->stream_status[i].plane_count,
1204 * TODO rework dc_enable_stereo call to work with validation sets?
1206 for (k = 0; k < MAX_PIPES; k++) {
1207 pipe = &context->res_ctx.pipe_ctx[k];
1209 for (l = 0 ; pipe && l < context->stream_count; l++) {
1210 if (context->streams[l] &&
1211 context->streams[l] == pipe->stream &&
1212 dc->hwss.setup_stereo)
1213 dc->hwss.setup_stereo(pipe, dc);
1217 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1218 context->streams[i]->timing.h_addressable,
1219 context->streams[i]->timing.v_addressable,
1220 context->streams[i]->timing.h_total,
1221 context->streams[i]->timing.v_total,
1222 context->streams[i]->timing.pix_clk_100hz / 10);
1225 dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1227 if (!dc->optimize_seamless_boot)
1228 /* pplib is notified if disp_num changed */
1229 dc->hwss.optimize_bandwidth(dc, context);
1231 for (i = 0; i < context->stream_count; i++)
1232 context->streams[i]->mode_changed = false;
1234 dc_release_state(dc->current_state);
1236 dc->current_state = context;
1238 dc_retain_state(dc->current_state);
1243 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1245 enum dc_status result = DC_ERROR_UNEXPECTED;
1248 if (false == context_changed(dc, context))
1251 DC_LOG_DC("%s: %d streams\n",
1252 __func__, context->stream_count);
1254 for (i = 0; i < context->stream_count; i++) {
1255 struct dc_stream_state *stream = context->streams[i];
1257 dc_stream_log(dc, stream);
1260 result = dc_commit_state_no_check(dc, context);
1262 return (result == DC_OK);
1265 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1268 struct dc_state *context = dc->current_state;
1270 if (!dc->optimized_required || dc->optimize_seamless_boot)
1273 post_surface_trace(dc);
1275 for (i = 0; i < dc->res_pool->pipe_count; i++)
1276 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1277 context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1278 context->res_ctx.pipe_ctx[i].pipe_idx = i;
1279 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1282 dc->optimized_required = false;
1284 dc->hwss.optimize_bandwidth(dc, context);
1288 struct dc_state *dc_create_state(struct dc *dc)
1290 struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1295 /* Each context must have their own instance of VBA and in order to
1296 * initialize and obtain IP and SOC the base DML instance from DC is
1297 * initially copied into every context
1299 #ifdef CONFIG_DRM_AMD_DC_DCN
1300 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1303 kref_init(&context->refcount);
1308 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1311 struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1315 memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1317 for (i = 0; i < MAX_PIPES; i++) {
1318 struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1320 if (cur_pipe->top_pipe)
1321 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1323 if (cur_pipe->bottom_pipe)
1324 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1326 if (cur_pipe->prev_odm_pipe)
1327 cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1329 if (cur_pipe->next_odm_pipe)
1330 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1334 for (i = 0; i < new_ctx->stream_count; i++) {
1335 dc_stream_retain(new_ctx->streams[i]);
1336 for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1337 dc_plane_state_retain(
1338 new_ctx->stream_status[i].plane_states[j]);
1341 kref_init(&new_ctx->refcount);
1346 void dc_retain_state(struct dc_state *context)
1348 kref_get(&context->refcount);
1351 static void dc_state_free(struct kref *kref)
1353 struct dc_state *context = container_of(kref, struct dc_state, refcount);
1354 dc_resource_state_destruct(context);
1358 void dc_release_state(struct dc_state *context)
1360 kref_put(&context->refcount, dc_state_free);
1363 bool dc_set_generic_gpio_for_stereo(bool enable,
1364 struct gpio_service *gpio_service)
1366 enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1367 struct gpio_pin_info pin_info;
1368 struct gpio *generic;
1369 struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1374 pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1376 if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1380 generic = dal_gpio_service_create_generic_mux(
1391 gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1393 config->enable_output_from_mux = enable;
1394 config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1396 if (gpio_result == GPIO_RESULT_OK)
1397 gpio_result = dal_mux_setup_config(generic, config);
1399 if (gpio_result == GPIO_RESULT_OK) {
1400 dal_gpio_close(generic);
1401 dal_gpio_destroy_generic_mux(&generic);
1405 dal_gpio_close(generic);
1406 dal_gpio_destroy_generic_mux(&generic);
1412 static bool is_surface_in_context(
1413 const struct dc_state *context,
1414 const struct dc_plane_state *plane_state)
1418 for (j = 0; j < MAX_PIPES; j++) {
1419 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1421 if (plane_state == pipe_ctx->plane_state) {
1429 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1431 union surface_update_flags *update_flags = &u->surface->update_flags;
1432 enum surface_update_type update_type = UPDATE_TYPE_FAST;
1435 return UPDATE_TYPE_FAST;
1437 if (u->plane_info->color_space != u->surface->color_space) {
1438 update_flags->bits.color_space_change = 1;
1439 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1442 if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1443 update_flags->bits.horizontal_mirror_change = 1;
1444 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1447 if (u->plane_info->rotation != u->surface->rotation) {
1448 update_flags->bits.rotation_change = 1;
1449 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1452 if (u->plane_info->format != u->surface->format) {
1453 update_flags->bits.pixel_format_change = 1;
1454 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1457 if (u->plane_info->stereo_format != u->surface->stereo_format) {
1458 update_flags->bits.stereo_format_change = 1;
1459 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1462 if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1463 update_flags->bits.per_pixel_alpha_change = 1;
1464 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1467 if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1468 update_flags->bits.global_alpha_change = 1;
1469 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1472 if (u->plane_info->sdr_white_level != u->surface->sdr_white_level) {
1473 update_flags->bits.sdr_white_level = 1;
1474 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1477 if (u->plane_info->dcc.enable != u->surface->dcc.enable
1478 || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1479 || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1480 update_flags->bits.dcc_change = 1;
1481 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1484 if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1485 resource_pixel_format_to_bpp(u->surface->format)) {
1486 /* different bytes per element will require full bandwidth
1487 * and DML calculation
1489 update_flags->bits.bpp_change = 1;
1490 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1493 if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1494 || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1495 update_flags->bits.plane_size_change = 1;
1496 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1500 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1501 sizeof(union dc_tiling_info)) != 0) {
1502 update_flags->bits.swizzle_change = 1;
1503 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1505 /* todo: below are HW dependent, we should add a hook to
1506 * DCE/N resource and validated there.
1508 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1509 /* swizzled mode requires RQ to be setup properly,
1510 * thus need to run DML to calculate RQ settings
1512 update_flags->bits.bandwidth_change = 1;
1513 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1517 /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1521 static enum surface_update_type get_scaling_info_update_type(
1522 const struct dc_surface_update *u)
1524 union surface_update_flags *update_flags = &u->surface->update_flags;
1526 if (!u->scaling_info)
1527 return UPDATE_TYPE_FAST;
1529 if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1530 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1531 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1532 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1533 || u->scaling_info->scaling_quality.integer_scaling !=
1534 u->surface->scaling_quality.integer_scaling
1536 update_flags->bits.scaling_change = 1;
1538 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1539 || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1540 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1541 || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1542 /* Making dst rect smaller requires a bandwidth change */
1543 update_flags->bits.bandwidth_change = 1;
1546 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1547 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1549 update_flags->bits.scaling_change = 1;
1550 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1551 && u->scaling_info->src_rect.height > u->surface->src_rect.height)
1552 /* Making src rect bigger requires a bandwidth change */
1553 update_flags->bits.clock_change = 1;
1556 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1557 || u->scaling_info->src_rect.y != u->surface->src_rect.y
1558 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1559 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1560 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1561 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1562 update_flags->bits.position_change = 1;
1564 if (update_flags->bits.clock_change
1565 || update_flags->bits.bandwidth_change)
1566 return UPDATE_TYPE_FULL;
1568 if (update_flags->bits.scaling_change
1569 || update_flags->bits.position_change)
1570 return UPDATE_TYPE_MED;
1572 return UPDATE_TYPE_FAST;
1575 static enum surface_update_type det_surface_update(const struct dc *dc,
1576 const struct dc_surface_update *u)
1578 const struct dc_state *context = dc->current_state;
1579 enum surface_update_type type;
1580 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1581 union surface_update_flags *update_flags = &u->surface->update_flags;
1584 update_flags->bits.addr_update = 1;
1586 if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1587 update_flags->raw = 0xFFFFFFFF;
1588 return UPDATE_TYPE_FULL;
1591 update_flags->raw = 0; // Reset all flags
1593 type = get_plane_info_update_type(u);
1594 elevate_update_type(&overall_type, type);
1596 type = get_scaling_info_update_type(u);
1597 elevate_update_type(&overall_type, type);
1600 update_flags->bits.addr_update = 1;
1602 if (u->in_transfer_func)
1603 update_flags->bits.in_transfer_func_change = 1;
1605 if (u->input_csc_color_matrix)
1606 update_flags->bits.input_csc_change = 1;
1608 if (u->coeff_reduction_factor)
1609 update_flags->bits.coeff_reduction_change = 1;
1612 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1615 format = u->plane_info->format;
1616 else if (u->surface)
1617 format = u->surface->format;
1619 if (dce_use_lut(format))
1620 update_flags->bits.gamma_change = 1;
1623 if (update_flags->bits.in_transfer_func_change) {
1624 type = UPDATE_TYPE_MED;
1625 elevate_update_type(&overall_type, type);
1628 if (update_flags->bits.input_csc_change
1629 || update_flags->bits.coeff_reduction_change
1630 || update_flags->bits.gamma_change) {
1631 type = UPDATE_TYPE_FULL;
1632 elevate_update_type(&overall_type, type);
1635 return overall_type;
1638 static enum surface_update_type check_update_surfaces_for_stream(
1640 struct dc_surface_update *updates,
1642 struct dc_stream_update *stream_update,
1643 const struct dc_stream_status *stream_status)
1646 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1648 if (stream_status == NULL || stream_status->plane_count != surface_count)
1649 overall_type = UPDATE_TYPE_FULL;
1651 /* some stream updates require passive update */
1652 if (stream_update) {
1653 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1655 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1656 (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1657 stream_update->integer_scaling_update)
1658 su_flags->bits.scaling = 1;
1660 if (stream_update->out_transfer_func)
1661 su_flags->bits.out_tf = 1;
1663 if (stream_update->abm_level)
1664 su_flags->bits.abm_level = 1;
1666 if (stream_update->dpms_off)
1667 su_flags->bits.dpms_off = 1;
1669 if (stream_update->gamut_remap)
1670 su_flags->bits.gamut_remap = 1;
1672 if (stream_update->wb_update)
1673 su_flags->bits.wb_update = 1;
1674 if (su_flags->raw != 0)
1675 overall_type = UPDATE_TYPE_FULL;
1677 if (stream_update->output_csc_transform || stream_update->output_color_space)
1678 su_flags->bits.out_csc = 1;
1681 for (i = 0 ; i < surface_count; i++) {
1682 enum surface_update_type type =
1683 det_surface_update(dc, &updates[i]);
1685 elevate_update_type(&overall_type, type);
1688 return overall_type;
1692 * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1694 * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1696 enum surface_update_type dc_check_update_surfaces_for_stream(
1698 struct dc_surface_update *updates,
1700 struct dc_stream_update *stream_update,
1701 const struct dc_stream_status *stream_status)
1704 enum surface_update_type type;
1707 stream_update->stream->update_flags.raw = 0;
1708 for (i = 0; i < surface_count; i++)
1709 updates[i].surface->update_flags.raw = 0;
1711 type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1712 if (type == UPDATE_TYPE_FULL) {
1714 stream_update->stream->update_flags.raw = 0xFFFFFFFF;
1715 for (i = 0; i < surface_count; i++)
1716 updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1719 if (type == UPDATE_TYPE_FAST) {
1720 // If there's an available clock comparator, we use that.
1721 if (dc->clk_mgr->funcs->are_clock_states_equal) {
1722 if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
1723 dc->optimized_required = true;
1724 // Else we fallback to mem compare.
1725 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
1726 dc->optimized_required = true;
1733 static struct dc_stream_status *stream_get_status(
1734 struct dc_state *ctx,
1735 struct dc_stream_state *stream)
1739 for (i = 0; i < ctx->stream_count; i++) {
1740 if (stream == ctx->streams[i]) {
1741 return &ctx->stream_status[i];
1748 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1750 static void copy_surface_update_to_plane(
1751 struct dc_plane_state *surface,
1752 struct dc_surface_update *srf_update)
1754 if (srf_update->flip_addr) {
1755 surface->address = srf_update->flip_addr->address;
1756 surface->flip_immediate =
1757 srf_update->flip_addr->flip_immediate;
1758 surface->time.time_elapsed_in_us[surface->time.index] =
1759 srf_update->flip_addr->flip_timestamp_in_us -
1760 surface->time.prev_update_time_in_us;
1761 surface->time.prev_update_time_in_us =
1762 srf_update->flip_addr->flip_timestamp_in_us;
1763 surface->time.index++;
1764 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1765 surface->time.index = 0;
1768 if (srf_update->scaling_info) {
1769 surface->scaling_quality =
1770 srf_update->scaling_info->scaling_quality;
1772 srf_update->scaling_info->dst_rect;
1774 srf_update->scaling_info->src_rect;
1775 surface->clip_rect =
1776 srf_update->scaling_info->clip_rect;
1779 if (srf_update->plane_info) {
1780 surface->color_space =
1781 srf_update->plane_info->color_space;
1783 srf_update->plane_info->format;
1784 surface->plane_size =
1785 srf_update->plane_info->plane_size;
1787 srf_update->plane_info->rotation;
1788 surface->horizontal_mirror =
1789 srf_update->plane_info->horizontal_mirror;
1790 surface->stereo_format =
1791 srf_update->plane_info->stereo_format;
1792 surface->tiling_info =
1793 srf_update->plane_info->tiling_info;
1795 srf_update->plane_info->visible;
1796 surface->per_pixel_alpha =
1797 srf_update->plane_info->per_pixel_alpha;
1798 surface->global_alpha =
1799 srf_update->plane_info->global_alpha;
1800 surface->global_alpha_value =
1801 srf_update->plane_info->global_alpha_value;
1803 srf_update->plane_info->dcc;
1804 surface->sdr_white_level =
1805 srf_update->plane_info->sdr_white_level;
1806 surface->layer_index =
1807 srf_update->plane_info->layer_index;
1810 if (srf_update->gamma &&
1811 (surface->gamma_correction !=
1812 srf_update->gamma)) {
1813 memcpy(&surface->gamma_correction->entries,
1814 &srf_update->gamma->entries,
1815 sizeof(struct dc_gamma_entries));
1816 surface->gamma_correction->is_identity =
1817 srf_update->gamma->is_identity;
1818 surface->gamma_correction->num_entries =
1819 srf_update->gamma->num_entries;
1820 surface->gamma_correction->type =
1821 srf_update->gamma->type;
1824 if (srf_update->in_transfer_func &&
1825 (surface->in_transfer_func !=
1826 srf_update->in_transfer_func)) {
1827 surface->in_transfer_func->sdr_ref_white_level =
1828 srf_update->in_transfer_func->sdr_ref_white_level;
1829 surface->in_transfer_func->tf =
1830 srf_update->in_transfer_func->tf;
1831 surface->in_transfer_func->type =
1832 srf_update->in_transfer_func->type;
1833 memcpy(&surface->in_transfer_func->tf_pts,
1834 &srf_update->in_transfer_func->tf_pts,
1835 sizeof(struct dc_transfer_func_distributed_points));
1838 if (srf_update->func_shaper &&
1839 (surface->in_shaper_func !=
1840 srf_update->func_shaper))
1841 memcpy(surface->in_shaper_func, srf_update->func_shaper,
1842 sizeof(*surface->in_shaper_func));
1844 if (srf_update->lut3d_func &&
1845 (surface->lut3d_func !=
1846 srf_update->lut3d_func))
1847 memcpy(surface->lut3d_func, srf_update->lut3d_func,
1848 sizeof(*surface->lut3d_func));
1850 if (srf_update->blend_tf &&
1851 (surface->blend_tf !=
1852 srf_update->blend_tf))
1853 memcpy(surface->blend_tf, srf_update->blend_tf,
1854 sizeof(*surface->blend_tf));
1856 if (srf_update->input_csc_color_matrix)
1857 surface->input_csc_color_matrix =
1858 *srf_update->input_csc_color_matrix;
1860 if (srf_update->coeff_reduction_factor)
1861 surface->coeff_reduction_factor =
1862 *srf_update->coeff_reduction_factor;
1865 static void copy_stream_update_to_stream(struct dc *dc,
1866 struct dc_state *context,
1867 struct dc_stream_state *stream,
1868 const struct dc_stream_update *update)
1870 if (update == NULL || stream == NULL)
1873 if (update->src.height && update->src.width)
1874 stream->src = update->src;
1876 if (update->dst.height && update->dst.width)
1877 stream->dst = update->dst;
1879 if (update->out_transfer_func &&
1880 stream->out_transfer_func != update->out_transfer_func) {
1881 stream->out_transfer_func->sdr_ref_white_level =
1882 update->out_transfer_func->sdr_ref_white_level;
1883 stream->out_transfer_func->tf = update->out_transfer_func->tf;
1884 stream->out_transfer_func->type =
1885 update->out_transfer_func->type;
1886 memcpy(&stream->out_transfer_func->tf_pts,
1887 &update->out_transfer_func->tf_pts,
1888 sizeof(struct dc_transfer_func_distributed_points));
1891 if (update->hdr_static_metadata)
1892 stream->hdr_static_metadata = *update->hdr_static_metadata;
1894 if (update->abm_level)
1895 stream->abm_level = *update->abm_level;
1897 if (update->periodic_interrupt0)
1898 stream->periodic_interrupt0 = *update->periodic_interrupt0;
1900 if (update->periodic_interrupt1)
1901 stream->periodic_interrupt1 = *update->periodic_interrupt1;
1903 if (update->gamut_remap)
1904 stream->gamut_remap_matrix = *update->gamut_remap;
1906 /* Note: this being updated after mode set is currently not a use case
1907 * however if it arises OCSC would need to be reprogrammed at the
1910 if (update->output_color_space)
1911 stream->output_color_space = *update->output_color_space;
1913 if (update->output_csc_transform)
1914 stream->csc_color_matrix = *update->output_csc_transform;
1916 if (update->vrr_infopacket)
1917 stream->vrr_infopacket = *update->vrr_infopacket;
1919 if (update->dpms_off)
1920 stream->dpms_off = *update->dpms_off;
1922 if (update->vsc_infopacket)
1923 stream->vsc_infopacket = *update->vsc_infopacket;
1925 if (update->vsp_infopacket)
1926 stream->vsp_infopacket = *update->vsp_infopacket;
1928 if (update->dither_option)
1929 stream->dither_option = *update->dither_option;
1930 /* update current stream with writeback info */
1931 if (update->wb_update) {
1934 stream->num_wb_info = update->wb_update->num_wb_info;
1935 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
1936 for (i = 0; i < stream->num_wb_info; i++)
1937 stream->writeback_info[i] =
1938 update->wb_update->writeback_info[i];
1940 if (update->dsc_config) {
1941 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
1942 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
1943 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
1944 update->dsc_config->num_slices_v != 0);
1946 stream->timing.dsc_cfg = *update->dsc_config;
1947 stream->timing.flags.DSC = enable_dsc;
1948 if (!dc->res_pool->funcs->validate_bandwidth(dc, context,
1950 stream->timing.dsc_cfg = old_dsc_cfg;
1951 stream->timing.flags.DSC = old_dsc_enabled;
1956 static void commit_planes_do_stream_update(struct dc *dc,
1957 struct dc_stream_state *stream,
1958 struct dc_stream_update *stream_update,
1959 enum surface_update_type update_type,
1960 struct dc_state *context)
1963 bool should_program_abm;
1966 for (j = 0; j < dc->res_pool->pipe_count; j++) {
1967 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1969 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
1971 if (stream_update->periodic_interrupt0 &&
1972 dc->hwss.setup_periodic_interrupt)
1973 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
1975 if (stream_update->periodic_interrupt1 &&
1976 dc->hwss.setup_periodic_interrupt)
1977 dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
1979 if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
1980 stream_update->vrr_infopacket ||
1981 stream_update->vsc_infopacket ||
1982 stream_update->vsp_infopacket) {
1983 resource_build_info_frame(pipe_ctx);
1984 dc->hwss.update_info_frame(pipe_ctx);
1987 if (stream_update->gamut_remap)
1988 dc_stream_set_gamut_remap(dc, stream);
1990 if (stream_update->output_csc_transform)
1991 dc_stream_program_csc_matrix(dc, stream);
1993 if (stream_update->dither_option) {
1994 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1995 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1996 &pipe_ctx->stream->bit_depth_params);
1997 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
1998 &stream->bit_depth_params,
2001 odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2002 &stream->bit_depth_params,
2004 odm_pipe = odm_pipe->next_odm_pipe;
2008 if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
2009 dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
2010 dp_update_dsc_config(pipe_ctx);
2011 dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
2014 if (update_type == UPDATE_TYPE_FAST)
2017 if (stream_update->dpms_off) {
2018 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2020 if (*stream_update->dpms_off) {
2021 core_link_disable_stream(pipe_ctx);
2022 /* for dpms, keep acquired resources*/
2023 if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2024 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2026 dc->hwss.optimize_bandwidth(dc, dc->current_state);
2028 if (!dc->optimize_seamless_boot)
2029 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2031 core_link_enable_stream(dc->current_state, pipe_ctx);
2034 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2037 if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2038 should_program_abm = true;
2040 // if otg funcs defined check if blanked before programming
2041 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2042 if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2043 should_program_abm = false;
2045 if (should_program_abm) {
2046 if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2047 pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
2049 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2050 pipe_ctx->stream_res.abm, stream->abm_level);
2058 static void commit_planes_for_stream(struct dc *dc,
2059 struct dc_surface_update *srf_updates,
2061 struct dc_stream_state *stream,
2062 struct dc_stream_update *stream_update,
2063 enum surface_update_type update_type,
2064 struct dc_state *context)
2067 struct pipe_ctx *top_pipe_to_program = NULL;
2069 if (dc->optimize_seamless_boot && surface_count > 0) {
2070 /* Optimize seamless boot flag keeps clocks and watermarks high until
2071 * first flip. After first flip, optimization is required to lower
2072 * bandwidth. Important to note that it is expected UEFI will
2073 * only light up a single display on POST, therefore we only expect
2074 * one stream with seamless boot flag set.
2076 if (stream->apply_seamless_boot_optimization) {
2077 stream->apply_seamless_boot_optimization = false;
2078 dc->optimize_seamless_boot = false;
2079 dc->optimized_required = true;
2083 if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) {
2084 dc->hwss.prepare_bandwidth(dc, context);
2085 context_clock_trace(dc, context);
2090 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2092 if (surface_count == 0) {
2094 * In case of turning off screen, no need to program front end a second time.
2095 * just return after program blank.
2097 if (dc->hwss.apply_ctx_for_surface)
2098 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2099 if (dc->hwss.program_front_end_for_ctx)
2100 dc->hwss.program_front_end_for_ctx(dc, context);
2105 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2106 for (i = 0; i < surface_count; i++) {
2107 struct dc_plane_state *plane_state = srf_updates[i].surface;
2108 /*set logical flag for lock/unlock use*/
2109 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2110 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2111 if (!pipe_ctx->plane_state)
2113 if (pipe_ctx->plane_state != plane_state)
2115 plane_state->triplebuffer_flips = false;
2116 if (update_type == UPDATE_TYPE_FAST &&
2117 dc->hwss.program_triplebuffer != NULL &&
2118 !plane_state->flip_immediate &&
2119 !dc->debug.disable_tri_buf) {
2120 /*triple buffer for VUpdate only*/
2121 plane_state->triplebuffer_flips = true;
2127 // Update Type FULL, Surface updates
2128 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2129 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2131 if (!pipe_ctx->top_pipe &&
2132 !pipe_ctx->prev_odm_pipe &&
2134 pipe_ctx->stream == stream) {
2135 struct dc_stream_status *stream_status = NULL;
2137 top_pipe_to_program = pipe_ctx;
2139 if (!pipe_ctx->plane_state)
2143 if (update_type == UPDATE_TYPE_FAST)
2146 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2148 if (dc->hwss.program_triplebuffer != NULL &&
2149 !dc->debug.disable_tri_buf) {
2150 /*turn off triple buffer for full update*/
2151 dc->hwss.program_triplebuffer(
2152 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2155 stream_get_status(context, pipe_ctx->stream);
2157 if (dc->hwss.apply_ctx_for_surface)
2158 dc->hwss.apply_ctx_for_surface(
2159 dc, pipe_ctx->stream, stream_status->plane_count, context);
2162 if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST)
2163 dc->hwss.program_front_end_for_ctx(dc, context);
2165 // Update Type FAST, Surface updates
2166 if (update_type == UPDATE_TYPE_FAST) {
2167 /* Lock the top pipe while updating plane addrs, since freesync requires
2168 * plane addr update event triggers to be synchronized.
2169 * top_pipe_to_program is expected to never be NULL
2171 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2173 if (dc->hwss.set_flip_control_gsl)
2174 for (i = 0; i < surface_count; i++) {
2175 struct dc_plane_state *plane_state = srf_updates[i].surface;
2177 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2178 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2180 if (pipe_ctx->stream != stream)
2183 if (pipe_ctx->plane_state != plane_state)
2186 // GSL has to be used for flip immediate
2187 dc->hwss.set_flip_control_gsl(pipe_ctx,
2188 plane_state->flip_immediate);
2191 /* Perform requested Updates */
2192 for (i = 0; i < surface_count; i++) {
2193 struct dc_plane_state *plane_state = srf_updates[i].surface;
2195 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2196 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2198 if (pipe_ctx->stream != stream)
2201 if (pipe_ctx->plane_state != plane_state)
2203 /*program triple buffer after lock based on flip type*/
2204 if (dc->hwss.program_triplebuffer != NULL &&
2205 !dc->debug.disable_tri_buf) {
2206 /*only enable triplebuffer for fast_update*/
2207 dc->hwss.program_triplebuffer(
2208 dc, pipe_ctx, plane_state->triplebuffer_flips);
2210 if (srf_updates[i].flip_addr)
2211 dc->hwss.update_plane_addr(dc, pipe_ctx);
2215 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2218 // Fire manual trigger only when bottom plane is flipped
2219 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2220 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2222 if (pipe_ctx->bottom_pipe ||
2223 !pipe_ctx->stream ||
2224 pipe_ctx->stream != stream ||
2225 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2228 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2229 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2233 void dc_commit_updates_for_stream(struct dc *dc,
2234 struct dc_surface_update *srf_updates,
2236 struct dc_stream_state *stream,
2237 struct dc_stream_update *stream_update,
2238 struct dc_state *state)
2240 const struct dc_stream_status *stream_status;
2241 enum surface_update_type update_type;
2242 struct dc_state *context;
2243 struct dc_context *dc_ctx = dc->ctx;
2246 stream_status = dc_stream_get_status(stream);
2247 context = dc->current_state;
2249 update_type = dc_check_update_surfaces_for_stream(
2250 dc, srf_updates, surface_count, stream_update, stream_status);
2252 if (update_type >= update_surface_trace_level)
2253 update_surface_trace(dc, srf_updates, surface_count);
2256 if (update_type >= UPDATE_TYPE_FULL) {
2258 /* initialize scratch memory for building context */
2259 context = dc_create_state(dc);
2260 if (context == NULL) {
2261 DC_ERROR("Failed to allocate new validate context!\n");
2265 dc_resource_state_copy_construct(state, context);
2267 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2268 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2269 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2271 if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2272 new_pipe->plane_state->force_full_update = true;
2277 for (i = 0; i < surface_count; i++) {
2278 struct dc_plane_state *surface = srf_updates[i].surface;
2280 copy_surface_update_to_plane(surface, &srf_updates[i]);
2284 copy_stream_update_to_stream(dc, context, stream, stream_update);
2286 commit_planes_for_stream(
2294 /*update current_State*/
2295 if (dc->current_state != context) {
2297 struct dc_state *old = dc->current_state;
2299 dc->current_state = context;
2300 dc_release_state(old);
2302 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2303 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2305 if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2306 pipe_ctx->plane_state->force_full_update = false;
2309 /*let's use current_state to update watermark etc*/
2310 if (update_type >= UPDATE_TYPE_FULL)
2311 dc_post_update_surfaces_to_stream(dc);
2317 uint8_t dc_get_current_stream_count(struct dc *dc)
2319 return dc->current_state->stream_count;
2322 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2324 if (i < dc->current_state->stream_count)
2325 return dc->current_state->streams[i];
2329 enum dc_irq_source dc_interrupt_to_irq_source(
2334 return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2338 * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2340 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2346 return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2349 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2351 dal_irq_service_ack(dc->res_pool->irqs, src);
2354 void dc_set_power_state(
2356 enum dc_acpi_cm_power_state power_state)
2358 struct kref refcount;
2359 struct display_mode_lib *dml = kzalloc(sizeof(struct display_mode_lib),
2366 switch (power_state) {
2367 case DC_ACPI_CM_POWER_STATE_D0:
2368 dc_resource_state_construct(dc, dc->current_state);
2370 if (dc->ctx->dmub_srv)
2371 dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2373 dc->hwss.init_hw(dc);
2375 if (dc->hwss.init_sys_ctx != NULL &&
2376 dc->vm_pa_config.valid) {
2377 dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2382 ASSERT(dc->current_state->stream_count == 0);
2383 /* Zero out the current context so that on resume we start with
2384 * clean state, and dc hw programming optimizations will not
2385 * cause any trouble.
2388 /* Preserve refcount */
2389 refcount = dc->current_state->refcount;
2390 /* Preserve display mode lib */
2391 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2393 dc_resource_state_destruct(dc->current_state);
2394 memset(dc->current_state, 0,
2395 sizeof(*dc->current_state));
2397 dc->current_state->refcount = refcount;
2398 dc->current_state->bw_ctx.dml = *dml;
2406 void dc_resume(struct dc *dc)
2411 for (i = 0; i < dc->link_count; i++)
2412 core_link_resume(dc->links[i]);
2415 unsigned int dc_get_current_backlight_pwm(struct dc *dc)
2417 struct abm *abm = dc->res_pool->abm;
2420 return abm->funcs->get_current_backlight(abm);
2425 unsigned int dc_get_target_backlight_pwm(struct dc *dc)
2427 struct abm *abm = dc->res_pool->abm;
2430 return abm->funcs->get_target_backlight(abm);
2435 bool dc_is_dmcu_initialized(struct dc *dc)
2437 struct dmcu *dmcu = dc->res_pool->dmcu;
2440 return dmcu->funcs->is_dmcu_initialized(dmcu);
2446 uint32_t link_index,
2447 struct i2c_command *cmd)
2450 struct dc_link *link = dc->links[link_index];
2451 struct ddc_service *ddc = link->ddc;
2452 return dce_i2c_submit_command(
2458 bool dc_submit_i2c_oem(
2460 struct i2c_command *cmd)
2462 struct ddc_service *ddc = dc->res_pool->oem_device;
2463 return dce_i2c_submit_command(
2469 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2471 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2472 BREAK_TO_DEBUGGER();
2476 dc_sink_retain(sink);
2478 dc_link->remote_sinks[dc_link->sink_count] = sink;
2479 dc_link->sink_count++;
2485 * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2487 * EDID length is in bytes
2489 struct dc_sink *dc_link_add_remote_sink(
2490 struct dc_link *link,
2491 const uint8_t *edid,
2493 struct dc_sink_init_data *init_data)
2495 struct dc_sink *dc_sink;
2496 enum dc_edid_status edid_status;
2498 if (len > DC_MAX_EDID_BUFFER_SIZE) {
2499 dm_error("Max EDID buffer size breached!\n");
2504 BREAK_TO_DEBUGGER();
2508 if (!init_data->link) {
2509 BREAK_TO_DEBUGGER();
2513 dc_sink = dc_sink_create(init_data);
2518 memmove(dc_sink->dc_edid.raw_edid, edid, len);
2519 dc_sink->dc_edid.length = len;
2521 if (!link_add_remote_sink_helper(
2526 edid_status = dm_helpers_parse_edid_caps(
2529 &dc_sink->edid_caps);
2532 * Treat device as no EDID device if EDID
2535 if (edid_status != EDID_OK) {
2536 dc_sink->dc_edid.length = 0;
2537 dm_error("Bad EDID, status%d!\n", edid_status);
2543 dc_sink_release(dc_sink);
2548 * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2550 * Note that this just removes the struct dc_sink - it doesn't
2551 * program hardware or alter other members of dc_link
2553 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2557 if (!link->sink_count) {
2558 BREAK_TO_DEBUGGER();
2562 for (i = 0; i < link->sink_count; i++) {
2563 if (link->remote_sinks[i] == sink) {
2564 dc_sink_release(sink);
2565 link->remote_sinks[i] = NULL;
2567 /* shrink array to remove empty place */
2568 while (i < link->sink_count - 1) {
2569 link->remote_sinks[i] = link->remote_sinks[i+1];
2572 link->remote_sinks[i] = NULL;
2579 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2581 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2582 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2583 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2584 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2585 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
2586 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
2587 info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
2588 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
2589 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
2591 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
2593 if (dc->hwss.set_clock)
2594 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
2595 return DC_ERROR_UNEXPECTED;
2597 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
2599 if (dc->hwss.get_clock)
2600 dc->hwss.get_clock(dc, clock_type, clock_cfg);