drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "bios/bios_parser_helper.h"
  45 #include "include/irq_service_interface.h"
  46 #include "transform.h"
  47 #include "dmcu.h"
  48 #include "dpp.h"
  49 #include "timing_generator.h"
  50 #include "abm.h"
  51 #include "virtual/virtual_link_encoder.h"
  52 #include "hubp.h"
  53
  54 #include "link_hwss.h"
  55 #include "link_encoder.h"
  56 #include "link_enc_cfg.h"
  57
  58 #include "dc_link.h"
  59 #include "dc_link_ddc.h"
  60 #include "dm_helpers.h"
  61 #include "mem_input.h"
  62
  63 #include "dc_link_dp.h"
  64 #include "dc_dmub_srv.h"
  65
  66 #include "dsc.h"
  67
  68 #include "vm_helper.h"
  69
  70 #include "dce/dce_i2c.h"
  71
  72 #include "dmub/dmub_srv.h"
  73
  74 #include "i2caux_interface.h"
  75 #include "dce/dmub_hw_lock_mgr.h"
  76
  77 #include "dc_trace.h"
  78
  79 #define CTX \
  80         dc->ctx
  81
  82 #define DC_LOGGER \
  83         dc->ctx->logger
  84
  85 static const char DC_BUILD_ID[] = "production-build";
  86
  87 /**
  88  * DOC: Overview
  89  *
  90  * DC is the OS-agnostic component of the amdgpu DC driver.
  91  *
  92  * DC maintains and validates a set of structs representing the state of the
  93  * driver and writes that state to AMD hardware
  94  *
  95  * Main DC HW structs:
  96  *
  97  * struct dc - The central struct.  One per driver.  Created on driver load,
  98  * destroyed on driver unload.
  99  *
 100  * struct dc_context - One per driver.
 101  * Used as a backpointer by most other structs in dc.
 102  *
 103  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 104  * plugpoints).  Created on driver load, destroyed on driver unload.
 105  *
 106  * struct dc_sink - One per display.  Created on boot or hotplug.
 107  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 108  * (the display directly attached).  It may also have one or more remote
 109  * sinks (in the Multi-Stream Transport case)
 110  *
 111  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 112  * main pipeline.  Not directly accessible by dm.
 113  *
 114  * Main dc state structs:
 115  *
 116  * These structs can be created and destroyed as needed.  There is a full set of
 117  * these structs in dc->current_state representing the currently programmed state.
 118  *
 119  * struct dc_state - The global DC state to track global state information,
 120  * such as bandwidth values.
 121  *
 122  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 123  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 124  *
 125  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 126  * and may have more in the Multi-Plane Overlay case.
 127  *
 128  * struct resource_context - Represents the programmable state of everything in
 129  * the resource_pool.  Not directly accessible by dm.
 130  *
 131  * struct pipe_ctx - A member of struct resource_context.  Represents the
 132  * internal hardware pipeline components.  Each dc_plane_state has either
 133  * one or two (in the pipe-split case).
 134  */
 135
 136 /*******************************************************************************
 137  * Private functions
 138  ******************************************************************************/
 139
 140 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 141 {
 142         if (new > *original)
 143                 *original = new;
 144 }
 145
 146 static void destroy_links(struct dc *dc)
 147 {
 148         uint32_t i;
 149
 150         for (i = 0; i < dc->link_count; i++) {
 151                 if (NULL != dc->links[i])
 152                         link_destroy(&dc->links[i]);
 153         }
 154 }
 155
 156 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 157 {
 158         int i;
 159         uint32_t count = 0;
 160
 161         for (i = 0; i < num_links; i++) {
 162                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 163                                 links[i]->is_internal_display)
 164                         count++;
 165         }
 166
 167         return count;
 168 }
 169
 170 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 171 {
 172         uint8_t i;
 173         uint8_t seamless_boot_stream_count = 0;
 174
 175         for (i = 0; i < ctx->stream_count; i++)
 176                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 177                         seamless_boot_stream_count++;
 178
 179         return seamless_boot_stream_count;
 180 }
 181
 182 static bool create_links(
 183                 struct dc *dc,
 184                 uint32_t num_virtual_links)
 185 {
 186         int i;
 187         int connectors_num;
 188         struct dc_bios *bios = dc->ctx->dc_bios;
 189
 190         dc->link_count = 0;
 191
 192         connectors_num = bios->funcs->get_connectors_number(bios);
 193
 194         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 195
 196         if (connectors_num > ENUM_ID_COUNT) {
 197                 dm_error(
 198                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 199                         connectors_num,
 200                         ENUM_ID_COUNT);
 201                 return false;
 202         }
 203
 204         dm_output_to_console(
 205                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 206                 __func__,
 207                 connectors_num,
 208                 num_virtual_links);
 209
 210         for (i = 0; i < connectors_num; i++) {
 211                 struct link_init_data link_init_params = {0};
 212                 struct dc_link *link;
 213
 214                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 215
 216                 link_init_params.ctx = dc->ctx;
 217                 /* next BIOS object table connector */
 218                 link_init_params.connector_index = i;
 219                 link_init_params.link_index = dc->link_count;
 220                 link_init_params.dc = dc;
 221                 link = link_create(&link_init_params);
 222
 223                 if (link) {
 224                                 dc->links[dc->link_count] = link;
 225                                 link->dc = dc;
 226                                 ++dc->link_count;
 227                 }
 228         }
 229
 230         DC_LOG_DC("BIOS object table - end");
 231
 232         for (i = 0; i < num_virtual_links; i++) {
 233                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 234                 struct encoder_init_data enc_init = {0};
 235
 236                 if (link == NULL) {
 237                         BREAK_TO_DEBUGGER();
 238                         goto failed_alloc;
 239                 }
 240
 241                 link->link_index = dc->link_count;
 242                 dc->links[dc->link_count] = link;
 243                 dc->link_count++;
 244
 245                 link->ctx = dc->ctx;
 246                 link->dc = dc;
 247                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 248                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 249                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 250                 link->link_id.enum_id = ENUM_ID_1;
 251                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 252
 253                 if (!link->link_enc) {
 254                         BREAK_TO_DEBUGGER();
 255                         goto failed_alloc;
 256                 }
 257
 258                 link->link_status.dpcd_caps = &link->dpcd_caps;
 259
 260                 enc_init.ctx = dc->ctx;
 261                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 262                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 263                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 264                 enc_init.connector = link->link_id;
 265                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 266                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 267                 enc_init.encoder.enum_id = ENUM_ID_1;
 268                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 269         }
 270
 271         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 272
 273         return true;
 274
 275 failed_alloc:
 276         return false;
 277 }
 278
 279 static struct dc_perf_trace *dc_perf_trace_create(void)
 280 {
 281         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 282 }
 283
 284 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 285 {
 286         kfree(*perf_trace);
 287         *perf_trace = NULL;
 288 }
 289
 290 /**
 291  *  dc_stream_adjust_vmin_vmax:
 292  *
 293  *  Looks up the pipe context of dc_stream_state and updates the
 294  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 295  *  Rate, which is a power-saving feature that targets reducing panel
 296  *  refresh rate while the screen is static
 297  *
 298  *  @dc:     dc reference
 299  *  @stream: Initial dc stream state
 300  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 301  */
 302 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 303                 struct dc_stream_state *stream,
 304                 struct dc_crtc_timing_adjust *adjust)
 305 {
 306         int i;
 307         bool ret = false;
 308
 309         stream->adjust.v_total_max = adjust->v_total_max;
 310         stream->adjust.v_total_mid = adjust->v_total_mid;
 311         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 312         stream->adjust.v_total_min = adjust->v_total_min;
 313
 314         for (i = 0; i < MAX_PIPES; i++) {
 315                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 316
 317                 if (pipe->stream == stream && pipe->stream_res.tg) {
 318                         dc->hwss.set_drr(&pipe,
 319                                         1,
 320                                         *adjust);
 321
 322                         ret = true;
 323                 }
 324         }
 325         return ret;
 326 }
 327
 328 bool dc_stream_get_crtc_position(struct dc *dc,
 329                 struct dc_stream_state **streams, int num_streams,
 330                 unsigned int *v_pos, unsigned int *nom_v_pos)
 331 {
 332         /* TODO: Support multiple streams */
 333         const struct dc_stream_state *stream = streams[0];
 334         int i;
 335         bool ret = false;
 336         struct crtc_position position;
 337
 338         for (i = 0; i < MAX_PIPES; i++) {
 339                 struct pipe_ctx *pipe =
 340                                 &dc->current_state->res_ctx.pipe_ctx[i];
 341
 342                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 343                         dc->hwss.get_position(&pipe, 1, &position);
 344
 345                         *v_pos = position.vertical_count;
 346                         *nom_v_pos = position.nominal_vcount;
 347                         ret = true;
 348                 }
 349         }
 350         return ret;
 351 }
 352
 353 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 354 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
 355                              struct crc_params *crc_window)
 356 {
 357         int i;
 358         struct dmcu *dmcu = dc->res_pool->dmcu;
 359         struct pipe_ctx *pipe;
 360         struct crc_region tmp_win, *crc_win;
 361         struct otg_phy_mux mapping_tmp, *mux_mapping;
 362
 363         /*crc window can't be null*/
 364         if (!crc_window)
 365                 return false;
 366
 367         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 368                 crc_win = &tmp_win;
 369                 mux_mapping = &mapping_tmp;
 370                 /*set crc window*/
 371                 tmp_win.x_start = crc_window->windowa_x_start;
 372                 tmp_win.y_start = crc_window->windowa_y_start;
 373                 tmp_win.x_end = crc_window->windowa_x_end;
 374                 tmp_win.y_end = crc_window->windowa_y_end;
 375
 376                 for (i = 0; i < MAX_PIPES; i++) {
 377                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 378                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 379                                 break;
 380                 }
 381
 382                 /* Stream not found */
 383                 if (i == MAX_PIPES)
 384                         return false;
 385
 386
 387                 /*set mux routing info*/
 388                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 389                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 390
 391                 dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping);
 392         } else {
 393                 DC_LOG_DC("dmcu is not initialized");
 394                 return false;
 395         }
 396
 397         return true;
 398 }
 399
 400 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream)
 401 {
 402         int i;
 403         struct dmcu *dmcu = dc->res_pool->dmcu;
 404         struct pipe_ctx *pipe;
 405         struct otg_phy_mux mapping_tmp, *mux_mapping;
 406
 407         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 408                 mux_mapping = &mapping_tmp;
 409
 410                 for (i = 0; i < MAX_PIPES; i++) {
 411                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 412                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 413                                 break;
 414                 }
 415
 416                 /* Stream not found */
 417                 if (i == MAX_PIPES)
 418                         return false;
 419
 420
 421                 /*set mux routing info*/
 422                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 423                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 424
 425                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 426         } else {
 427                 DC_LOG_DC("dmcu is not initialized");
 428                 return false;
 429         }
 430
 431         return true;
 432 }
 433 #endif
 434
 435 /**
 436  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 437  * @dc: DC Object
 438  * @stream: The stream to configure CRC on.
 439  * @enable: Enable CRC if true, disable otherwise.
 440  * @crc_window: CRC window (x/y start/end) information
 441  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 442  *              once.
 443  *
 444  * By default, only CRC0 is configured, and the entire frame is used to
 445  * calculate the crc.
 446  */
 447 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 448                              struct crc_params *crc_window, bool enable, bool continuous)
 449 {
 450         int i;
 451         struct pipe_ctx *pipe;
 452         struct crc_params param;
 453         struct timing_generator *tg;
 454
 455         for (i = 0; i < MAX_PIPES; i++) {
 456                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 457                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 458                         break;
 459         }
 460         /* Stream not found */
 461         if (i == MAX_PIPES)
 462                 return false;
 463
 464         /* By default, capture the full frame */
 465         param.windowa_x_start = 0;
 466         param.windowa_y_start = 0;
 467         param.windowa_x_end = pipe->stream->timing.h_addressable;
 468         param.windowa_y_end = pipe->stream->timing.v_addressable;
 469         param.windowb_x_start = 0;
 470         param.windowb_y_start = 0;
 471         param.windowb_x_end = pipe->stream->timing.h_addressable;
 472         param.windowb_y_end = pipe->stream->timing.v_addressable;
 473
 474         if (crc_window) {
 475                 param.windowa_x_start = crc_window->windowa_x_start;
 476                 param.windowa_y_start = crc_window->windowa_y_start;
 477                 param.windowa_x_end = crc_window->windowa_x_end;
 478                 param.windowa_y_end = crc_window->windowa_y_end;
 479                 param.windowb_x_start = crc_window->windowb_x_start;
 480                 param.windowb_y_start = crc_window->windowb_y_start;
 481                 param.windowb_x_end = crc_window->windowb_x_end;
 482                 param.windowb_y_end = crc_window->windowb_y_end;
 483         }
 484
 485         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 486         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 487
 488         /* Default to the union of both windows */
 489         param.selection = UNION_WINDOW_A_B;
 490         param.continuous_mode = continuous;
 491         param.enable = enable;
 492
 493         tg = pipe->stream_res.tg;
 494
 495         /* Only call if supported */
 496         if (tg->funcs->configure_crc)
 497                 return tg->funcs->configure_crc(tg, &param);
 498         DC_LOG_WARNING("CRC capture not supported.");
 499         return false;
 500 }
 501
 502 /**
 503  * dc_stream_get_crc() - Get CRC values for the given stream.
 504  * @dc: DC object
 505  * @stream: The DC stream state of the stream to get CRCs from.
 506  * @r_cr: CRC value for the first of the 3 channels stored here.
 507  * @g_y:  CRC value for the second of the 3 channels stored here.
 508  * @b_cb: CRC value for the third of the 3 channels stored here.
 509  *
 510  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 511  * Return false if stream is not found, or if CRCs are not enabled.
 512  */
 513 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 514                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 515 {
 516         int i;
 517         struct pipe_ctx *pipe;
 518         struct timing_generator *tg;
 519
 520         for (i = 0; i < MAX_PIPES; i++) {
 521                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 522                 if (pipe->stream == stream)
 523                         break;
 524         }
 525         /* Stream not found */
 526         if (i == MAX_PIPES)
 527                 return false;
 528
 529         tg = pipe->stream_res.tg;
 530
 531         if (tg->funcs->get_crc)
 532                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 533         DC_LOG_WARNING("CRC capture not supported.");
 534         return false;
 535 }
 536
 537 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 538                 enum dc_dynamic_expansion option)
 539 {
 540         /* OPP FMT dyn expansion updates*/
 541         int i;
 542         struct pipe_ctx *pipe_ctx;
 543
 544         for (i = 0; i < MAX_PIPES; i++) {
 545                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 546                                 == stream) {
 547                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 548                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 549                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 550                                         pipe_ctx->stream_res.opp,
 551                                         COLOR_SPACE_YCBCR601,
 552                                         stream->timing.display_color_depth,
 553                                         stream->signal);
 554                 }
 555         }
 556 }
 557
 558 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 559                 enum dc_dither_option option)
 560 {
 561         struct bit_depth_reduction_params params;
 562         struct dc_link *link = stream->link;
 563         struct pipe_ctx *pipes = NULL;
 564         int i;
 565
 566         for (i = 0; i < MAX_PIPES; i++) {
 567                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 568                                 stream) {
 569                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 570                         break;
 571                 }
 572         }
 573
 574         if (!pipes)
 575                 return;
 576         if (option > DITHER_OPTION_MAX)
 577                 return;
 578
 579         stream->dither_option = option;
 580
 581         memset(&params, 0, sizeof(params));
 582         resource_build_bit_depth_reduction_params(stream, &params);
 583         stream->bit_depth_params = params;
 584
 585         if (pipes->plane_res.xfm &&
 586             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 587                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 588                         pipes->plane_res.xfm,
 589                         pipes->plane_res.scl_data.lb_params.depth,
 590                         &stream->bit_depth_params);
 591         }
 592
 593         pipes->stream_res.opp->funcs->
 594                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 595 }
 596
 597 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 598 {
 599         int i;
 600         bool ret = false;
 601         struct pipe_ctx *pipes;
 602
 603         for (i = 0; i < MAX_PIPES; i++) {
 604                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 605                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 606                         dc->hwss.program_gamut_remap(pipes);
 607                         ret = true;
 608                 }
 609         }
 610
 611         return ret;
 612 }
 613
 614 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 615 {
 616         int i;
 617         bool ret = false;
 618         struct pipe_ctx *pipes;
 619
 620         for (i = 0; i < MAX_PIPES; i++) {
 621                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 622                                 == stream) {
 623
 624                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 625                         dc->hwss.program_output_csc(dc,
 626                                         pipes,
 627                                         stream->output_color_space,
 628                                         stream->csc_color_matrix.matrix,
 629                                         pipes->stream_res.opp->inst);
 630                         ret = true;
 631                 }
 632         }
 633
 634         return ret;
 635 }
 636
 637 void dc_stream_set_static_screen_params(struct dc *dc,
 638                 struct dc_stream_state **streams,
 639                 int num_streams,
 640                 const struct dc_static_screen_params *params)
 641 {
 642         int i, j;
 643         struct pipe_ctx *pipes_affected[MAX_PIPES];
 644         int num_pipes_affected = 0;
 645
 646         for (i = 0; i < num_streams; i++) {
 647                 struct dc_stream_state *stream = streams[i];
 648
 649                 for (j = 0; j < MAX_PIPES; j++) {
 650                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 651                                         == stream) {
 652                                 pipes_affected[num_pipes_affected++] =
 653                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 654                         }
 655                 }
 656         }
 657
 658         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 659 }
 660
 661 static void dc_destruct(struct dc *dc)
 662 {
 663         if (dc->current_state) {
 664                 dc_release_state(dc->current_state);
 665                 dc->current_state = NULL;
 666         }
 667
 668         destroy_links(dc);
 669
 670         if (dc->clk_mgr) {
 671                 dc_destroy_clk_mgr(dc->clk_mgr);
 672                 dc->clk_mgr = NULL;
 673         }
 674
 675         dc_destroy_resource_pool(dc);
 676
 677         if (dc->ctx->gpio_service)
 678                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 679
 680         if (dc->ctx->created_bios)
 681                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 682
 683         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 684
 685         kfree(dc->ctx);
 686         dc->ctx = NULL;
 687
 688         kfree(dc->bw_vbios);
 689         dc->bw_vbios = NULL;
 690
 691         kfree(dc->bw_dceip);
 692         dc->bw_dceip = NULL;
 693
 694 #ifdef CONFIG_DRM_AMD_DC_DCN
 695         kfree(dc->dcn_soc);
 696         dc->dcn_soc = NULL;
 697
 698         kfree(dc->dcn_ip);
 699         dc->dcn_ip = NULL;
 700
 701 #endif
 702         kfree(dc->vm_helper);
 703         dc->vm_helper = NULL;
 704
 705 }
 706
 707 static bool dc_construct_ctx(struct dc *dc,
 708                 const struct dc_init_data *init_params)
 709 {
 710         struct dc_context *dc_ctx;
 711         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 712
 713         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 714         if (!dc_ctx)
 715                 return false;
 716
 717         dc_ctx->cgs_device = init_params->cgs_device;
 718         dc_ctx->driver_context = init_params->driver;
 719         dc_ctx->dc = dc;
 720         dc_ctx->asic_id = init_params->asic_id;
 721         dc_ctx->dc_sink_id_count = 0;
 722         dc_ctx->dc_stream_id_count = 0;
 723         dc_ctx->dce_environment = init_params->dce_environment;
 724
 725         /* Create logger */
 726
 727         dc_version = resource_parse_asic_id(init_params->asic_id);
 728         dc_ctx->dce_version = dc_version;
 729
 730         dc_ctx->perf_trace = dc_perf_trace_create();
 731         if (!dc_ctx->perf_trace) {
 732                 ASSERT_CRITICAL(false);
 733                 return false;
 734         }
 735
 736         dc->ctx = dc_ctx;
 737
 738         return true;
 739 }
 740
 741 static bool dc_construct(struct dc *dc,
 742                 const struct dc_init_data *init_params)
 743 {
 744         struct dc_context *dc_ctx;
 745         struct bw_calcs_dceip *dc_dceip;
 746         struct bw_calcs_vbios *dc_vbios;
 747 #ifdef CONFIG_DRM_AMD_DC_DCN
 748         struct dcn_soc_bounding_box *dcn_soc;
 749         struct dcn_ip_params *dcn_ip;
 750 #endif
 751
 752         dc->config = init_params->flags;
 753
 754         // Allocate memory for the vm_helper
 755         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 756         if (!dc->vm_helper) {
 757                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 758                 goto fail;
 759         }
 760
 761         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 762
 763         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 764         if (!dc_dceip) {
 765                 dm_error("%s: failed to create dceip\n", __func__);
 766                 goto fail;
 767         }
 768
 769         dc->bw_dceip = dc_dceip;
 770
 771         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 772         if (!dc_vbios) {
 773                 dm_error("%s: failed to create vbios\n", __func__);
 774                 goto fail;
 775         }
 776
 777         dc->bw_vbios = dc_vbios;
 778 #ifdef CONFIG_DRM_AMD_DC_DCN
 779         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 780         if (!dcn_soc) {
 781                 dm_error("%s: failed to create dcn_soc\n", __func__);
 782                 goto fail;
 783         }
 784
 785         dc->dcn_soc = dcn_soc;
 786
 787         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 788         if (!dcn_ip) {
 789                 dm_error("%s: failed to create dcn_ip\n", __func__);
 790                 goto fail;
 791         }
 792
 793         dc->dcn_ip = dcn_ip;
 794 #endif
 795
 796         if (!dc_construct_ctx(dc, init_params)) {
 797                 dm_error("%s: failed to create ctx\n", __func__);
 798                 goto fail;
 799         }
 800
 801         dc_ctx = dc->ctx;
 802
 803         /* Resource should construct all asic specific resources.
 804          * This should be the only place where we need to parse the asic id
 805          */
 806         if (init_params->vbios_override)
 807                 dc_ctx->dc_bios = init_params->vbios_override;
 808         else {
 809                 /* Create BIOS parser */
 810                 struct bp_init_data bp_init_data;
 811
 812                 bp_init_data.ctx = dc_ctx;
 813                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 814
 815                 dc_ctx->dc_bios = dal_bios_parser_create(
 816                                 &bp_init_data, dc_ctx->dce_version);
 817
 818                 if (!dc_ctx->dc_bios) {
 819                         ASSERT_CRITICAL(false);
 820                         goto fail;
 821                 }
 822
 823                 dc_ctx->created_bios = true;
 824         }
 825
 826         dc->vendor_signature = init_params->vendor_signature;
 827
 828         /* Create GPIO service */
 829         dc_ctx->gpio_service = dal_gpio_service_create(
 830                         dc_ctx->dce_version,
 831                         dc_ctx->dce_environment,
 832                         dc_ctx);
 833
 834         if (!dc_ctx->gpio_service) {
 835                 ASSERT_CRITICAL(false);
 836                 goto fail;
 837         }
 838
 839         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 840         if (!dc->res_pool)
 841                 goto fail;
 842
 843         /* set i2c speed if not done by the respective dcnxxx__resource.c */
 844         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
 845                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
 846
 847         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 848         if (!dc->clk_mgr)
 849                 goto fail;
 850 #ifdef CONFIG_DRM_AMD_DC_DCN
 851         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 852 #endif
 853
 854         if (dc->res_pool->funcs->update_bw_bounding_box)
 855                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 856
 857         /* Creation of current_state must occur after dc->dml
 858          * is initialized in dc_create_resource_pool because
 859          * on creation it copies the contents of dc->dml
 860          */
 861
 862         dc->current_state = dc_create_state(dc);
 863
 864         if (!dc->current_state) {
 865                 dm_error("%s: failed to create validate ctx\n", __func__);
 866                 goto fail;
 867         }
 868
 869         dc_resource_state_construct(dc, dc->current_state);
 870
 871         if (!create_links(dc, init_params->num_virtual_links))
 872                 goto fail;
 873
 874         /* Initialise DIG link encoder resource tracking variables. */
 875         link_enc_cfg_init(dc, dc->current_state);
 876
 877         return true;
 878
 879 fail:
 880         return false;
 881 }
 882
 883 static void disable_all_writeback_pipes_for_stream(
 884                 const struct dc *dc,
 885                 struct dc_stream_state *stream,
 886                 struct dc_state *context)
 887 {
 888         int i;
 889
 890         for (i = 0; i < stream->num_wb_info; i++)
 891                 stream->writeback_info[i].wb_enabled = false;
 892 }
 893
 894 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
 895                                           struct dc_stream_state *stream, bool lock)
 896 {
 897         int i;
 898
 899         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 900         if (dc->hwss.interdependent_update_lock)
 901                 dc->hwss.interdependent_update_lock(dc, context, lock);
 902         else {
 903                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 904                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 905                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 906
 907                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 908                         if (stream == pipe_ctx->stream) {
 909                                 if (!pipe_ctx->top_pipe &&
 910                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 911                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 912                         }
 913                 }
 914         }
 915 }
 916
 917 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 918 {
 919         int i, j;
 920         struct dc_state *dangling_context = dc_create_state(dc);
 921         struct dc_state *current_ctx;
 922
 923         if (dangling_context == NULL)
 924                 return;
 925
 926         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 927
 928         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 929                 struct dc_stream_state *old_stream =
 930                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 931                 bool should_disable = true;
 932
 933                 for (j = 0; j < context->stream_count; j++) {
 934                         if (old_stream == context->streams[j]) {
 935                                 should_disable = false;
 936                                 break;
 937                         }
 938                 }
 939                 if (should_disable && old_stream) {
 940                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 941                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 942
 943                         if (dc->hwss.apply_ctx_for_surface) {
 944                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 945                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 946                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 947                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 948                         }
 949                         if (dc->hwss.program_front_end_for_ctx) {
 950                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 951                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 952                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 953                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 954                         }
 955                 }
 956         }
 957
 958         current_ctx = dc->current_state;
 959         dc->current_state = dangling_context;
 960         dc_release_state(current_ctx);
 961 }
 962
 963 static void disable_vbios_mode_if_required(
 964                 struct dc *dc,
 965                 struct dc_state *context)
 966 {
 967         unsigned int i, j;
 968
 969         /* check if timing_changed, disable stream*/
 970         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 971                 struct dc_stream_state *stream = NULL;
 972                 struct dc_link *link = NULL;
 973                 struct pipe_ctx *pipe = NULL;
 974
 975                 pipe = &context->res_ctx.pipe_ctx[i];
 976                 stream = pipe->stream;
 977                 if (stream == NULL)
 978                         continue;
 979
 980                 // only looking for first odm pipe
 981                 if (pipe->prev_odm_pipe)
 982                         continue;
 983
 984                 if (stream->link->local_sink &&
 985                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 986                         link = stream->link;
 987                 }
 988
 989                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 990                         unsigned int enc_inst, tg_inst = 0;
 991                         unsigned int pix_clk_100hz;
 992
 993                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 994                         if (enc_inst != ENGINE_ID_UNKNOWN) {
 995                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 996                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
 997                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
 998                                                         dc->res_pool->stream_enc[j]);
 999                                                 break;
1000                                         }
1001                                 }
1002
1003                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1004                                         dc->res_pool->dp_clock_source,
1005                                         tg_inst, &pix_clk_100hz);
1006
1007                                 if (link->link_status.link_active) {
1008                                         uint32_t requested_pix_clk_100hz =
1009                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1010
1011                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1012                                                 core_link_disable_stream(pipe);
1013                                                 pipe->stream->dpms_off = false;
1014                                         }
1015                                 }
1016                         }
1017                 }
1018         }
1019 }
1020
1021 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1022 {
1023         int i;
1024         PERF_TRACE();
1025         for (i = 0; i < MAX_PIPES; i++) {
1026                 int count = 0;
1027                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1028
1029                 if (!pipe->plane_state)
1030                         continue;
1031
1032                 /* Timeout 100 ms */
1033                 while (count < 100000) {
1034                         /* Must set to false to start with, due to OR in update function */
1035                         pipe->plane_state->status.is_flip_pending = false;
1036                         dc->hwss.update_pending_status(pipe);
1037                         if (!pipe->plane_state->status.is_flip_pending)
1038                                 break;
1039                         udelay(1);
1040                         count++;
1041                 }
1042                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1043         }
1044         PERF_TRACE();
1045 }
1046
1047 /*******************************************************************************
1048  * Public functions
1049  ******************************************************************************/
1050
1051 struct dc *dc_create(const struct dc_init_data *init_params)
1052 {
1053         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1054         unsigned int full_pipe_count;
1055
1056         if (!dc)
1057                 return NULL;
1058
1059         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1060                 if (!dc_construct_ctx(dc, init_params))
1061                         goto destruct_dc;
1062         } else {
1063                 if (!dc_construct(dc, init_params))
1064                         goto destruct_dc;
1065
1066                 full_pipe_count = dc->res_pool->pipe_count;
1067                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1068                         full_pipe_count--;
1069                 dc->caps.max_streams = min(
1070                                 full_pipe_count,
1071                                 dc->res_pool->stream_enc_count);
1072
1073                 dc->caps.max_links = dc->link_count;
1074                 dc->caps.max_audios = dc->res_pool->audio_count;
1075                 dc->caps.linear_pitch_alignment = 64;
1076
1077                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1078
1079                 if (dc->res_pool->dmcu != NULL)
1080                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1081         }
1082
1083         /* Populate versioning information */
1084         dc->versions.dc_ver = DC_VER;
1085
1086         dc->build_id = DC_BUILD_ID;
1087
1088         DC_LOG_DC("Display Core initialized\n");
1089
1090
1091
1092         return dc;
1093
1094 destruct_dc:
1095         dc_destruct(dc);
1096         kfree(dc);
1097         return NULL;
1098 }
1099
1100 static void detect_edp_presence(struct dc *dc)
1101 {
1102         struct dc_link *edp_links[MAX_NUM_EDP];
1103         struct dc_link *edp_link = NULL;
1104         enum dc_connection_type type;
1105         int i;
1106         int edp_num;
1107
1108         get_edp_links(dc, edp_links, &edp_num);
1109         if (!edp_num)
1110                 return;
1111
1112         for (i = 0; i < edp_num; i++) {
1113                 edp_link = edp_links[i];
1114                 if (dc->config.edp_not_connected) {
1115                         edp_link->edp_sink_present = false;
1116                 } else {
1117                         dc_link_detect_sink(edp_link, &type);
1118                         edp_link->edp_sink_present = (type != dc_connection_none);
1119                 }
1120         }
1121 }
1122
1123 void dc_hardware_init(struct dc *dc)
1124 {
1125
1126         detect_edp_presence(dc);
1127         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1128                 dc->hwss.init_hw(dc);
1129 }
1130
1131 void dc_init_callbacks(struct dc *dc,
1132                 const struct dc_callback_init *init_params)
1133 {
1134 #ifdef CONFIG_DRM_AMD_DC_HDCP
1135         dc->ctx->cp_psp = init_params->cp_psp;
1136 #endif
1137 }
1138
1139 void dc_deinit_callbacks(struct dc *dc)
1140 {
1141 #ifdef CONFIG_DRM_AMD_DC_HDCP
1142         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1143 #endif
1144 }
1145
1146 void dc_destroy(struct dc **dc)
1147 {
1148         dc_destruct(*dc);
1149         kfree(*dc);
1150         *dc = NULL;
1151 }
1152
1153 static void enable_timing_multisync(
1154                 struct dc *dc,
1155                 struct dc_state *ctx)
1156 {
1157         int i, multisync_count = 0;
1158         int pipe_count = dc->res_pool->pipe_count;
1159         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1160
1161         for (i = 0; i < pipe_count; i++) {
1162                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1163                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1164                         continue;
1165                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1166                         continue;
1167                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1168                 multisync_count++;
1169         }
1170
1171         if (multisync_count > 0) {
1172                 dc->hwss.enable_per_frame_crtc_position_reset(
1173                         dc, multisync_count, multisync_pipes);
1174         }
1175 }
1176
1177 static void program_timing_sync(
1178                 struct dc *dc,
1179                 struct dc_state *ctx)
1180 {
1181         int i, j, k;
1182         int group_index = 0;
1183         int num_group = 0;
1184         int pipe_count = dc->res_pool->pipe_count;
1185         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1186
1187         for (i = 0; i < pipe_count; i++) {
1188                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1189                         continue;
1190
1191                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1192         }
1193
1194         for (i = 0; i < pipe_count; i++) {
1195                 int group_size = 1;
1196                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1197                 struct pipe_ctx *pipe_set[MAX_PIPES];
1198
1199                 if (!unsynced_pipes[i])
1200                         continue;
1201
1202                 pipe_set[0] = unsynced_pipes[i];
1203                 unsynced_pipes[i] = NULL;
1204
1205                 /* Add tg to the set, search rest of the tg's for ones with
1206                  * same timing, add all tgs with same timing to the group
1207                  */
1208                 for (j = i + 1; j < pipe_count; j++) {
1209                         if (!unsynced_pipes[j])
1210                                 continue;
1211                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1212                                 dc->hwss.enable_vblanks_synchronization &&
1213                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1214                                 resource_are_vblanks_synchronizable(
1215                                         unsynced_pipes[j]->stream,
1216                                         pipe_set[0]->stream)) {
1217                                 sync_type = VBLANK_SYNCHRONIZABLE;
1218                                 pipe_set[group_size] = unsynced_pipes[j];
1219                                 unsynced_pipes[j] = NULL;
1220                                 group_size++;
1221                         } else
1222                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1223                                 resource_are_streams_timing_synchronizable(
1224                                         unsynced_pipes[j]->stream,
1225                                         pipe_set[0]->stream)) {
1226                                 sync_type = TIMING_SYNCHRONIZABLE;
1227                                 pipe_set[group_size] = unsynced_pipes[j];
1228                                 unsynced_pipes[j] = NULL;
1229                                 group_size++;
1230                         }
1231                 }
1232
1233                 /* set first unblanked pipe as master */
1234                 for (j = 0; j < group_size; j++) {
1235                         bool is_blanked;
1236
1237                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1238                                 is_blanked =
1239                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1240                         else
1241                                 is_blanked =
1242                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1243                         if (!is_blanked) {
1244                                 if (j == 0)
1245                                         break;
1246
1247                                 swap(pipe_set[0], pipe_set[j]);
1248                                 break;
1249                         }
1250                 }
1251
1252                 for (k = 0; k < group_size; k++) {
1253                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1254
1255                         status->timing_sync_info.group_id = num_group;
1256                         status->timing_sync_info.group_size = group_size;
1257                         if (k == 0)
1258                                 status->timing_sync_info.master = true;
1259                         else
1260                                 status->timing_sync_info.master = false;
1261
1262                 }
1263                 /* remove any other unblanked pipes as they have already been synced */
1264                 for (j = j + 1; j < group_size; j++) {
1265                         bool is_blanked;
1266
1267                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1268                                 is_blanked =
1269                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1270                         else
1271                                 is_blanked =
1272                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1273                         if (!is_blanked) {
1274                                 group_size--;
1275                                 pipe_set[j] = pipe_set[group_size];
1276                                 j--;
1277                         }
1278                 }
1279
1280                 if (group_size > 1) {
1281                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1282                                 dc->hwss.enable_timing_synchronization(
1283                                         dc, group_index, group_size, pipe_set);
1284                         } else
1285                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1286                                 dc->hwss.enable_vblanks_synchronization(
1287                                         dc, group_index, group_size, pipe_set);
1288                                 }
1289                         group_index++;
1290                 }
1291                 num_group++;
1292         }
1293 }
1294
1295 static bool context_changed(
1296                 struct dc *dc,
1297                 struct dc_state *context)
1298 {
1299         uint8_t i;
1300
1301         if (context->stream_count != dc->current_state->stream_count)
1302                 return true;
1303
1304         for (i = 0; i < dc->current_state->stream_count; i++) {
1305                 if (dc->current_state->streams[i] != context->streams[i])
1306                         return true;
1307         }
1308
1309         return false;
1310 }
1311
1312 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1313                                 const struct dc_sink *sink,
1314                                 struct dc_crtc_timing *crtc_timing)
1315 {
1316         struct timing_generator *tg;
1317         struct stream_encoder *se = NULL;
1318
1319         struct dc_crtc_timing hw_crtc_timing = {0};
1320
1321         struct dc_link *link = sink->link;
1322         unsigned int i, enc_inst, tg_inst = 0;
1323
1324         /* Support seamless boot on EDP displays only */
1325         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1326                 return false;
1327         }
1328
1329         /* Check for enabled DIG to identify enabled display */
1330         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1331                 return false;
1332
1333         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1334
1335         if (enc_inst == ENGINE_ID_UNKNOWN)
1336                 return false;
1337
1338         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1339                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1340
1341                         se = dc->res_pool->stream_enc[i];
1342
1343                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1344                                 dc->res_pool->stream_enc[i]);
1345                         break;
1346                 }
1347         }
1348
1349         // tg_inst not found
1350         if (i == dc->res_pool->stream_enc_count)
1351                 return false;
1352
1353         if (tg_inst >= dc->res_pool->timing_generator_count)
1354                 return false;
1355
1356         tg = dc->res_pool->timing_generators[tg_inst];
1357
1358         if (!tg->funcs->get_hw_timing)
1359                 return false;
1360
1361         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1362                 return false;
1363
1364         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1365                 return false;
1366
1367         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1368                 return false;
1369
1370         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1371                 return false;
1372
1373         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1374                 return false;
1375
1376         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1377                 return false;
1378
1379         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1380                 return false;
1381
1382         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1383                 return false;
1384
1385         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1386                 return false;
1387
1388         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1389                 return false;
1390
1391         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1392                 return false;
1393
1394         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1395                 return false;
1396
1397         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1398                 return false;
1399
1400         /* block DSC for now, as VBIOS does not currently support DSC timings */
1401         if (crtc_timing->flags.DSC)
1402                 return false;
1403
1404         if (dc_is_dp_signal(link->connector_signal)) {
1405                 unsigned int pix_clk_100hz;
1406
1407                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1408                         dc->res_pool->dp_clock_source,
1409                         tg_inst, &pix_clk_100hz);
1410
1411                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1412                         return false;
1413
1414                 if (!se->funcs->dp_get_pixel_format)
1415                         return false;
1416
1417                 if (!se->funcs->dp_get_pixel_format(
1418                         se,
1419                         &hw_crtc_timing.pixel_encoding,
1420                         &hw_crtc_timing.display_color_depth))
1421                         return false;
1422
1423                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1424                         return false;
1425
1426                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1427                         return false;
1428         }
1429
1430         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1431                 return false;
1432         }
1433
1434         if (is_edp_ilr_optimization_required(link, crtc_timing)) {
1435                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1436                 return false;
1437         }
1438
1439         return true;
1440 }
1441
1442 void dc_enable_stereo(
1443         struct dc *dc,
1444         struct dc_state *context,
1445         struct dc_stream_state *streams[],
1446         uint8_t stream_count)
1447 {
1448         int i, j;
1449         struct pipe_ctx *pipe;
1450
1451         for (i = 0; i < MAX_PIPES; i++) {
1452                 if (context != NULL)
1453                         pipe = &context->res_ctx.pipe_ctx[i];
1454                 else
1455                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1456                 for (j = 0 ; pipe && j < stream_count; j++)  {
1457                         if (streams[j] && streams[j] == pipe->stream &&
1458                                 dc->hwss.setup_stereo)
1459                                 dc->hwss.setup_stereo(pipe, dc);
1460                 }
1461         }
1462 }
1463
1464 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1465 {
1466         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1467                 enable_timing_multisync(dc, context);
1468                 program_timing_sync(dc, context);
1469         }
1470 }
1471
1472 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1473 {
1474         int i;
1475         unsigned int stream_mask = 0;
1476
1477         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1478                 if (context->res_ctx.pipe_ctx[i].stream)
1479                         stream_mask |= 1 << i;
1480         }
1481
1482         return stream_mask;
1483 }
1484
1485 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
1486 void dc_z10_restore(struct dc *dc)
1487 {
1488         if (dc->hwss.z10_restore)
1489                 dc->hwss.z10_restore(dc);
1490 }
1491 #endif
1492 /*
1493  * Applies given context to HW and copy it into current context.
1494  * It's up to the user to release the src context afterwards.
1495  */
1496 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1497 {
1498         struct dc_bios *dcb = dc->ctx->dc_bios;
1499         enum dc_status result = DC_ERROR_UNEXPECTED;
1500         struct pipe_ctx *pipe;
1501         int i, k, l;
1502         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1503
1504 #if defined(CONFIG_DRM_AMD_DC_DCN)
1505 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
1506         dc_z10_restore(dc);
1507 #endif
1508         dc_allow_idle_optimizations(dc, false);
1509 #endif
1510
1511         for (i = 0; i < context->stream_count; i++)
1512                 dc_streams[i] =  context->streams[i];
1513
1514         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1515                 disable_vbios_mode_if_required(dc, context);
1516                 dc->hwss.enable_accelerated_mode(dc, context);
1517         }
1518
1519         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1520                 context->stream_count == 0)
1521                 dc->hwss.prepare_bandwidth(dc, context);
1522
1523         disable_dangling_plane(dc, context);
1524         /* re-program planes for existing stream, in case we need to
1525          * free up plane resource for later use
1526          */
1527         if (dc->hwss.apply_ctx_for_surface) {
1528                 for (i = 0; i < context->stream_count; i++) {
1529                         if (context->streams[i]->mode_changed)
1530                                 continue;
1531                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1532                         dc->hwss.apply_ctx_for_surface(
1533                                 dc, context->streams[i],
1534                                 context->stream_status[i].plane_count,
1535                                 context); /* use new pipe config in new context */
1536                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1537                         dc->hwss.post_unlock_program_front_end(dc, context);
1538                 }
1539         }
1540
1541         /* Program hardware */
1542         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1543                 pipe = &context->res_ctx.pipe_ctx[i];
1544                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1545         }
1546
1547         result = dc->hwss.apply_ctx_to_hw(dc, context);
1548
1549         if (result != DC_OK)
1550                 return result;
1551
1552         dc_trigger_sync(dc, context);
1553
1554         /* Program all planes within new context*/
1555         if (dc->hwss.program_front_end_for_ctx) {
1556                 dc->hwss.interdependent_update_lock(dc, context, true);
1557                 dc->hwss.program_front_end_for_ctx(dc, context);
1558                 dc->hwss.interdependent_update_lock(dc, context, false);
1559                 dc->hwss.post_unlock_program_front_end(dc, context);
1560         }
1561         for (i = 0; i < context->stream_count; i++) {
1562                 const struct dc_link *link = context->streams[i]->link;
1563
1564                 if (!context->streams[i]->mode_changed)
1565                         continue;
1566
1567                 if (dc->hwss.apply_ctx_for_surface) {
1568                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1569                         dc->hwss.apply_ctx_for_surface(
1570                                         dc, context->streams[i],
1571                                         context->stream_status[i].plane_count,
1572                                         context);
1573                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1574                         dc->hwss.post_unlock_program_front_end(dc, context);
1575                 }
1576
1577                 /*
1578                  * enable stereo
1579                  * TODO rework dc_enable_stereo call to work with validation sets?
1580                  */
1581                 for (k = 0; k < MAX_PIPES; k++) {
1582                         pipe = &context->res_ctx.pipe_ctx[k];
1583
1584                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1585                                 if (context->streams[l] &&
1586                                         context->streams[l] == pipe->stream &&
1587                                         dc->hwss.setup_stereo)
1588                                         dc->hwss.setup_stereo(pipe, dc);
1589                         }
1590                 }
1591
1592                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1593                                 context->streams[i]->timing.h_addressable,
1594                                 context->streams[i]->timing.v_addressable,
1595                                 context->streams[i]->timing.h_total,
1596                                 context->streams[i]->timing.v_total,
1597                                 context->streams[i]->timing.pix_clk_100hz / 10);
1598         }
1599
1600         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1601
1602         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1603                 context->stream_count == 0) {
1604                 /* Must wait for no flips to be pending before doing optimize bw */
1605                 wait_for_no_pipes_pending(dc, context);
1606                 /* pplib is notified if disp_num changed */
1607                 dc->hwss.optimize_bandwidth(dc, context);
1608         }
1609
1610         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1611                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1612         else
1613                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1614
1615         context->stream_mask = get_stream_mask(dc, context);
1616
1617         if (context->stream_mask != dc->current_state->stream_mask)
1618                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1619
1620         for (i = 0; i < context->stream_count; i++)
1621                 context->streams[i]->mode_changed = false;
1622
1623         dc_release_state(dc->current_state);
1624
1625         dc->current_state = context;
1626
1627         dc_retain_state(dc->current_state);
1628
1629         return result;
1630 }
1631
1632 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1633 {
1634         enum dc_status result = DC_ERROR_UNEXPECTED;
1635         int i;
1636
1637         if (!context_changed(dc, context))
1638                 return DC_OK;
1639
1640         DC_LOG_DC("%s: %d streams\n",
1641                                 __func__, context->stream_count);
1642
1643         for (i = 0; i < context->stream_count; i++) {
1644                 struct dc_stream_state *stream = context->streams[i];
1645
1646                 dc_stream_log(dc, stream);
1647         }
1648
1649         result = dc_commit_state_no_check(dc, context);
1650
1651         return (result == DC_OK);
1652 }
1653
1654 #if defined(CONFIG_DRM_AMD_DC_DCN)
1655 bool dc_acquire_release_mpc_3dlut(
1656                 struct dc *dc, bool acquire,
1657                 struct dc_stream_state *stream,
1658                 struct dc_3dlut **lut,
1659                 struct dc_transfer_func **shaper)
1660 {
1661         int pipe_idx;
1662         bool ret = false;
1663         bool found_pipe_idx = false;
1664         const struct resource_pool *pool = dc->res_pool;
1665         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1666         int mpcc_id = 0;
1667
1668         if (pool && res_ctx) {
1669                 if (acquire) {
1670                         /*find pipe idx for the given stream*/
1671                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1672                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1673                                         found_pipe_idx = true;
1674                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1675                                         break;
1676                                 }
1677                         }
1678                 } else
1679                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1680
1681                 if (found_pipe_idx) {
1682                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1683                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1684                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
1685                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1686                 }
1687         }
1688         return ret;
1689 }
1690 #endif
1691 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1692 {
1693         int i;
1694         struct pipe_ctx *pipe;
1695
1696         for (i = 0; i < MAX_PIPES; i++) {
1697                 pipe = &context->res_ctx.pipe_ctx[i];
1698
1699                 if (!pipe->plane_state)
1700                         continue;
1701
1702                 /* Must set to false to start with, due to OR in update function */
1703                 pipe->plane_state->status.is_flip_pending = false;
1704                 dc->hwss.update_pending_status(pipe);
1705                 if (pipe->plane_state->status.is_flip_pending)
1706                         return true;
1707         }
1708         return false;
1709 }
1710
1711 void dc_post_update_surfaces_to_stream(struct dc *dc)
1712 {
1713         int i;
1714         struct dc_state *context = dc->current_state;
1715
1716         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
1717                 return;
1718
1719         post_surface_trace(dc);
1720
1721         if (is_flip_pending_in_pipes(dc, context))
1722                 return;
1723
1724         for (i = 0; i < dc->res_pool->pipe_count; i++)
1725                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1726                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1727                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1728                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1729                 }
1730
1731         dc->hwss.optimize_bandwidth(dc, context);
1732
1733         dc->optimized_required = false;
1734         dc->wm_optimized_required = false;
1735 }
1736
1737 static void init_state(struct dc *dc, struct dc_state *context)
1738 {
1739         /* Each context must have their own instance of VBA and in order to
1740          * initialize and obtain IP and SOC the base DML instance from DC is
1741          * initially copied into every context
1742          */
1743 #ifdef CONFIG_DRM_AMD_DC_DCN
1744         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1745 #endif
1746 }
1747
1748 struct dc_state *dc_create_state(struct dc *dc)
1749 {
1750         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1751                                             GFP_KERNEL);
1752
1753         if (!context)
1754                 return NULL;
1755
1756         init_state(dc, context);
1757
1758         kref_init(&context->refcount);
1759
1760         return context;
1761 }
1762
1763 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1764 {
1765         int i, j;
1766         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1767
1768         if (!new_ctx)
1769                 return NULL;
1770         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1771
1772         for (i = 0; i < MAX_PIPES; i++) {
1773                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1774
1775                         if (cur_pipe->top_pipe)
1776                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1777
1778                         if (cur_pipe->bottom_pipe)
1779                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1780
1781                         if (cur_pipe->prev_odm_pipe)
1782                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1783
1784                         if (cur_pipe->next_odm_pipe)
1785                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1786
1787         }
1788
1789         for (i = 0; i < new_ctx->stream_count; i++) {
1790                         dc_stream_retain(new_ctx->streams[i]);
1791                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1792                                 dc_plane_state_retain(
1793                                         new_ctx->stream_status[i].plane_states[j]);
1794         }
1795
1796         kref_init(&new_ctx->refcount);
1797
1798         return new_ctx;
1799 }
1800
1801 void dc_retain_state(struct dc_state *context)
1802 {
1803         kref_get(&context->refcount);
1804 }
1805
1806 static void dc_state_free(struct kref *kref)
1807 {
1808         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1809         dc_resource_state_destruct(context);
1810         kvfree(context);
1811 }
1812
1813 void dc_release_state(struct dc_state *context)
1814 {
1815         kref_put(&context->refcount, dc_state_free);
1816 }
1817
1818 bool dc_set_generic_gpio_for_stereo(bool enable,
1819                 struct gpio_service *gpio_service)
1820 {
1821         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1822         struct gpio_pin_info pin_info;
1823         struct gpio *generic;
1824         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1825                            GFP_KERNEL);
1826
1827         if (!config)
1828                 return false;
1829         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1830
1831         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1832                 kfree(config);
1833                 return false;
1834         } else {
1835                 generic = dal_gpio_service_create_generic_mux(
1836                         gpio_service,
1837                         pin_info.offset,
1838                         pin_info.mask);
1839         }
1840
1841         if (!generic) {
1842                 kfree(config);
1843                 return false;
1844         }
1845
1846         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1847
1848         config->enable_output_from_mux = enable;
1849         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1850
1851         if (gpio_result == GPIO_RESULT_OK)
1852                 gpio_result = dal_mux_setup_config(generic, config);
1853
1854         if (gpio_result == GPIO_RESULT_OK) {
1855                 dal_gpio_close(generic);
1856                 dal_gpio_destroy_generic_mux(&generic);
1857                 kfree(config);
1858                 return true;
1859         } else {
1860                 dal_gpio_close(generic);
1861                 dal_gpio_destroy_generic_mux(&generic);
1862                 kfree(config);
1863                 return false;
1864         }
1865 }
1866
1867 static bool is_surface_in_context(
1868                 const struct dc_state *context,
1869                 const struct dc_plane_state *plane_state)
1870 {
1871         int j;
1872
1873         for (j = 0; j < MAX_PIPES; j++) {
1874                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1875
1876                 if (plane_state == pipe_ctx->plane_state) {
1877                         return true;
1878                 }
1879         }
1880
1881         return false;
1882 }
1883
1884 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1885 {
1886         union surface_update_flags *update_flags = &u->surface->update_flags;
1887         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1888
1889         if (!u->plane_info)
1890                 return UPDATE_TYPE_FAST;
1891
1892         if (u->plane_info->color_space != u->surface->color_space) {
1893                 update_flags->bits.color_space_change = 1;
1894                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1895         }
1896
1897         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1898                 update_flags->bits.horizontal_mirror_change = 1;
1899                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1900         }
1901
1902         if (u->plane_info->rotation != u->surface->rotation) {
1903                 update_flags->bits.rotation_change = 1;
1904                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1905         }
1906
1907         if (u->plane_info->format != u->surface->format) {
1908                 update_flags->bits.pixel_format_change = 1;
1909                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1910         }
1911
1912         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1913                 update_flags->bits.stereo_format_change = 1;
1914                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1915         }
1916
1917         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1918                 update_flags->bits.per_pixel_alpha_change = 1;
1919                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1920         }
1921
1922         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1923                 update_flags->bits.global_alpha_change = 1;
1924                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1925         }
1926
1927         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1928                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1929                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1930                 /* During DCC on/off, stutter period is calculated before
1931                  * DCC has fully transitioned. This results in incorrect
1932                  * stutter period calculation. Triggering a full update will
1933                  * recalculate stutter period.
1934                  */
1935                 update_flags->bits.dcc_change = 1;
1936                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1937         }
1938
1939         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1940                         resource_pixel_format_to_bpp(u->surface->format)) {
1941                 /* different bytes per element will require full bandwidth
1942                  * and DML calculation
1943                  */
1944                 update_flags->bits.bpp_change = 1;
1945                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1946         }
1947
1948         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1949                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1950                 update_flags->bits.plane_size_change = 1;
1951                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1952         }
1953
1954
1955         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1956                         sizeof(union dc_tiling_info)) != 0) {
1957                 update_flags->bits.swizzle_change = 1;
1958                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1959
1960                 /* todo: below are HW dependent, we should add a hook to
1961                  * DCE/N resource and validated there.
1962                  */
1963                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1964                         /* swizzled mode requires RQ to be setup properly,
1965                          * thus need to run DML to calculate RQ settings
1966                          */
1967                         update_flags->bits.bandwidth_change = 1;
1968                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1969                 }
1970         }
1971
1972         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1973         return update_type;
1974 }
1975
1976 static enum surface_update_type get_scaling_info_update_type(
1977                 const struct dc_surface_update *u)
1978 {
1979         union surface_update_flags *update_flags = &u->surface->update_flags;
1980
1981         if (!u->scaling_info)
1982                 return UPDATE_TYPE_FAST;
1983
1984         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1985                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1986                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1987                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1988                         || u->scaling_info->scaling_quality.integer_scaling !=
1989                                 u->surface->scaling_quality.integer_scaling
1990                         ) {
1991                 update_flags->bits.scaling_change = 1;
1992
1993                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1994                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1995                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1996                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1997                         /* Making dst rect smaller requires a bandwidth change */
1998                         update_flags->bits.bandwidth_change = 1;
1999         }
2000
2001         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2002                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2003
2004                 update_flags->bits.scaling_change = 1;
2005                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2006                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2007                         /* Making src rect bigger requires a bandwidth change */
2008                         update_flags->bits.clock_change = 1;
2009         }
2010
2011         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2012                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2013                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2014                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2015                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2016                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2017                 update_flags->bits.position_change = 1;
2018
2019         if (update_flags->bits.clock_change
2020                         || update_flags->bits.bandwidth_change
2021                         || update_flags->bits.scaling_change)
2022                 return UPDATE_TYPE_FULL;
2023
2024         if (update_flags->bits.position_change)
2025                 return UPDATE_TYPE_MED;
2026
2027         return UPDATE_TYPE_FAST;
2028 }
2029
2030 static enum surface_update_type det_surface_update(const struct dc *dc,
2031                 const struct dc_surface_update *u)
2032 {
2033         const struct dc_state *context = dc->current_state;
2034         enum surface_update_type type;
2035         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2036         union surface_update_flags *update_flags = &u->surface->update_flags;
2037
2038         if (u->flip_addr)
2039                 update_flags->bits.addr_update = 1;
2040
2041         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2042                 update_flags->raw = 0xFFFFFFFF;
2043                 return UPDATE_TYPE_FULL;
2044         }
2045
2046         update_flags->raw = 0; // Reset all flags
2047
2048         type = get_plane_info_update_type(u);
2049         elevate_update_type(&overall_type, type);
2050
2051         type = get_scaling_info_update_type(u);
2052         elevate_update_type(&overall_type, type);
2053
2054         if (u->flip_addr)
2055                 update_flags->bits.addr_update = 1;
2056
2057         if (u->in_transfer_func)
2058                 update_flags->bits.in_transfer_func_change = 1;
2059
2060         if (u->input_csc_color_matrix)
2061                 update_flags->bits.input_csc_change = 1;
2062
2063         if (u->coeff_reduction_factor)
2064                 update_flags->bits.coeff_reduction_change = 1;
2065
2066         if (u->gamut_remap_matrix)
2067                 update_flags->bits.gamut_remap_change = 1;
2068
2069         if (u->gamma) {
2070                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2071
2072                 if (u->plane_info)
2073                         format = u->plane_info->format;
2074                 else if (u->surface)
2075                         format = u->surface->format;
2076
2077                 if (dce_use_lut(format))
2078                         update_flags->bits.gamma_change = 1;
2079         }
2080
2081         if (u->hdr_mult.value)
2082                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2083                         update_flags->bits.hdr_mult = 1;
2084                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2085                 }
2086
2087         if (update_flags->bits.in_transfer_func_change) {
2088                 type = UPDATE_TYPE_MED;
2089                 elevate_update_type(&overall_type, type);
2090         }
2091
2092         if (update_flags->bits.input_csc_change
2093                         || update_flags->bits.coeff_reduction_change
2094                         || update_flags->bits.gamma_change
2095                         || update_flags->bits.gamut_remap_change) {
2096                 type = UPDATE_TYPE_FULL;
2097                 elevate_update_type(&overall_type, type);
2098         }
2099
2100         return overall_type;
2101 }
2102
2103 static enum surface_update_type check_update_surfaces_for_stream(
2104                 struct dc *dc,
2105                 struct dc_surface_update *updates,
2106                 int surface_count,
2107                 struct dc_stream_update *stream_update,
2108                 const struct dc_stream_status *stream_status)
2109 {
2110         int i;
2111         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2112
2113 #if defined(CONFIG_DRM_AMD_DC_DCN)
2114         if (dc->idle_optimizations_allowed)
2115                 overall_type = UPDATE_TYPE_FULL;
2116
2117 #endif
2118         if (stream_status == NULL || stream_status->plane_count != surface_count)
2119                 overall_type = UPDATE_TYPE_FULL;
2120
2121         if (stream_update && stream_update->pending_test_pattern) {
2122                 overall_type = UPDATE_TYPE_FULL;
2123         }
2124
2125         /* some stream updates require passive update */
2126         if (stream_update) {
2127                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2128
2129                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2130                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2131                         stream_update->integer_scaling_update)
2132                         su_flags->bits.scaling = 1;
2133
2134                 if (stream_update->out_transfer_func)
2135                         su_flags->bits.out_tf = 1;
2136
2137                 if (stream_update->abm_level)
2138                         su_flags->bits.abm_level = 1;
2139
2140                 if (stream_update->dpms_off)
2141                         su_flags->bits.dpms_off = 1;
2142
2143                 if (stream_update->gamut_remap)
2144                         su_flags->bits.gamut_remap = 1;
2145
2146                 if (stream_update->wb_update)
2147                         su_flags->bits.wb_update = 1;
2148
2149                 if (stream_update->dsc_config)
2150                         su_flags->bits.dsc_changed = 1;
2151
2152                 if (su_flags->raw != 0)
2153                         overall_type = UPDATE_TYPE_FULL;
2154
2155                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2156                         su_flags->bits.out_csc = 1;
2157         }
2158
2159         for (i = 0 ; i < surface_count; i++) {
2160                 enum surface_update_type type =
2161                                 det_surface_update(dc, &updates[i]);
2162
2163                 elevate_update_type(&overall_type, type);
2164         }
2165
2166         return overall_type;
2167 }
2168
2169 /*
2170  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2171  *
2172  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2173  */
2174 enum surface_update_type dc_check_update_surfaces_for_stream(
2175                 struct dc *dc,
2176                 struct dc_surface_update *updates,
2177                 int surface_count,
2178                 struct dc_stream_update *stream_update,
2179                 const struct dc_stream_status *stream_status)
2180 {
2181         int i;
2182         enum surface_update_type type;
2183
2184         if (stream_update)
2185                 stream_update->stream->update_flags.raw = 0;
2186         for (i = 0; i < surface_count; i++)
2187                 updates[i].surface->update_flags.raw = 0;
2188
2189         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2190         if (type == UPDATE_TYPE_FULL) {
2191                 if (stream_update) {
2192                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2193                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2194                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2195                 }
2196                 for (i = 0; i < surface_count; i++)
2197                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2198         }
2199
2200         if (type == UPDATE_TYPE_FAST) {
2201                 // If there's an available clock comparator, we use that.
2202                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2203                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2204                                 dc->optimized_required = true;
2205                 // Else we fallback to mem compare.
2206                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2207                         dc->optimized_required = true;
2208                 }
2209
2210                 dc->optimized_required |= dc->wm_optimized_required;
2211         }
2212
2213         return type;
2214 }
2215
2216 static struct dc_stream_status *stream_get_status(
2217         struct dc_state *ctx,
2218         struct dc_stream_state *stream)
2219 {
2220         uint8_t i;
2221
2222         for (i = 0; i < ctx->stream_count; i++) {
2223                 if (stream == ctx->streams[i]) {
2224                         return &ctx->stream_status[i];
2225                 }
2226         }
2227
2228         return NULL;
2229 }
2230
2231 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2232
2233 static void copy_surface_update_to_plane(
2234                 struct dc_plane_state *surface,
2235                 struct dc_surface_update *srf_update)
2236 {
2237         if (srf_update->flip_addr) {
2238                 surface->address = srf_update->flip_addr->address;
2239                 surface->flip_immediate =
2240                         srf_update->flip_addr->flip_immediate;
2241                 surface->time.time_elapsed_in_us[surface->time.index] =
2242                         srf_update->flip_addr->flip_timestamp_in_us -
2243                                 surface->time.prev_update_time_in_us;
2244                 surface->time.prev_update_time_in_us =
2245                         srf_update->flip_addr->flip_timestamp_in_us;
2246                 surface->time.index++;
2247                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2248                         surface->time.index = 0;
2249
2250                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2251         }
2252
2253         if (srf_update->scaling_info) {
2254                 surface->scaling_quality =
2255                                 srf_update->scaling_info->scaling_quality;
2256                 surface->dst_rect =
2257                                 srf_update->scaling_info->dst_rect;
2258                 surface->src_rect =
2259                                 srf_update->scaling_info->src_rect;
2260                 surface->clip_rect =
2261                                 srf_update->scaling_info->clip_rect;
2262         }
2263
2264         if (srf_update->plane_info) {
2265                 surface->color_space =
2266                                 srf_update->plane_info->color_space;
2267                 surface->format =
2268                                 srf_update->plane_info->format;
2269                 surface->plane_size =
2270                                 srf_update->plane_info->plane_size;
2271                 surface->rotation =
2272                                 srf_update->plane_info->rotation;
2273                 surface->horizontal_mirror =
2274                                 srf_update->plane_info->horizontal_mirror;
2275                 surface->stereo_format =
2276                                 srf_update->plane_info->stereo_format;
2277                 surface->tiling_info =
2278                                 srf_update->plane_info->tiling_info;
2279                 surface->visible =
2280                                 srf_update->plane_info->visible;
2281                 surface->per_pixel_alpha =
2282                                 srf_update->plane_info->per_pixel_alpha;
2283                 surface->global_alpha =
2284                                 srf_update->plane_info->global_alpha;
2285                 surface->global_alpha_value =
2286                                 srf_update->plane_info->global_alpha_value;
2287                 surface->dcc =
2288                                 srf_update->plane_info->dcc;
2289                 surface->layer_index =
2290                                 srf_update->plane_info->layer_index;
2291         }
2292
2293         if (srf_update->gamma &&
2294                         (surface->gamma_correction !=
2295                                         srf_update->gamma)) {
2296                 memcpy(&surface->gamma_correction->entries,
2297                         &srf_update->gamma->entries,
2298                         sizeof(struct dc_gamma_entries));
2299                 surface->gamma_correction->is_identity =
2300                         srf_update->gamma->is_identity;
2301                 surface->gamma_correction->num_entries =
2302                         srf_update->gamma->num_entries;
2303                 surface->gamma_correction->type =
2304                         srf_update->gamma->type;
2305         }
2306
2307         if (srf_update->in_transfer_func &&
2308                         (surface->in_transfer_func !=
2309                                 srf_update->in_transfer_func)) {
2310                 surface->in_transfer_func->sdr_ref_white_level =
2311                         srf_update->in_transfer_func->sdr_ref_white_level;
2312                 surface->in_transfer_func->tf =
2313                         srf_update->in_transfer_func->tf;
2314                 surface->in_transfer_func->type =
2315                         srf_update->in_transfer_func->type;
2316                 memcpy(&surface->in_transfer_func->tf_pts,
2317                         &srf_update->in_transfer_func->tf_pts,
2318                         sizeof(struct dc_transfer_func_distributed_points));
2319         }
2320
2321         if (srf_update->func_shaper &&
2322                         (surface->in_shaper_func !=
2323                         srf_update->func_shaper))
2324                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2325                 sizeof(*surface->in_shaper_func));
2326
2327         if (srf_update->lut3d_func &&
2328                         (surface->lut3d_func !=
2329                         srf_update->lut3d_func))
2330                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2331                 sizeof(*surface->lut3d_func));
2332
2333         if (srf_update->hdr_mult.value)
2334                 surface->hdr_mult =
2335                                 srf_update->hdr_mult;
2336
2337         if (srf_update->blend_tf &&
2338                         (surface->blend_tf !=
2339                         srf_update->blend_tf))
2340                 memcpy(surface->blend_tf, srf_update->blend_tf,
2341                 sizeof(*surface->blend_tf));
2342
2343         if (srf_update->input_csc_color_matrix)
2344                 surface->input_csc_color_matrix =
2345                         *srf_update->input_csc_color_matrix;
2346
2347         if (srf_update->coeff_reduction_factor)
2348                 surface->coeff_reduction_factor =
2349                         *srf_update->coeff_reduction_factor;
2350
2351         if (srf_update->gamut_remap_matrix)
2352                 surface->gamut_remap_matrix =
2353                         *srf_update->gamut_remap_matrix;
2354 }
2355
2356 static void copy_stream_update_to_stream(struct dc *dc,
2357                                          struct dc_state *context,
2358                                          struct dc_stream_state *stream,
2359                                          struct dc_stream_update *update)
2360 {
2361         struct dc_context *dc_ctx = dc->ctx;
2362
2363         if (update == NULL || stream == NULL)
2364                 return;
2365
2366         if (update->src.height && update->src.width)
2367                 stream->src = update->src;
2368
2369         if (update->dst.height && update->dst.width)
2370                 stream->dst = update->dst;
2371
2372         if (update->out_transfer_func &&
2373             stream->out_transfer_func != update->out_transfer_func) {
2374                 stream->out_transfer_func->sdr_ref_white_level =
2375                         update->out_transfer_func->sdr_ref_white_level;
2376                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2377                 stream->out_transfer_func->type =
2378                         update->out_transfer_func->type;
2379                 memcpy(&stream->out_transfer_func->tf_pts,
2380                        &update->out_transfer_func->tf_pts,
2381                        sizeof(struct dc_transfer_func_distributed_points));
2382         }
2383
2384         if (update->hdr_static_metadata)
2385                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2386
2387         if (update->abm_level)
2388                 stream->abm_level = *update->abm_level;
2389
2390         if (update->periodic_interrupt0)
2391                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2392
2393         if (update->periodic_interrupt1)
2394                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2395
2396         if (update->gamut_remap)
2397                 stream->gamut_remap_matrix = *update->gamut_remap;
2398
2399         /* Note: this being updated after mode set is currently not a use case
2400          * however if it arises OCSC would need to be reprogrammed at the
2401          * minimum
2402          */
2403         if (update->output_color_space)
2404                 stream->output_color_space = *update->output_color_space;
2405
2406         if (update->output_csc_transform)
2407                 stream->csc_color_matrix = *update->output_csc_transform;
2408
2409         if (update->vrr_infopacket)
2410                 stream->vrr_infopacket = *update->vrr_infopacket;
2411
2412         if (update->dpms_off)
2413                 stream->dpms_off = *update->dpms_off;
2414
2415         if (update->vsc_infopacket)
2416                 stream->vsc_infopacket = *update->vsc_infopacket;
2417
2418         if (update->vsp_infopacket)
2419                 stream->vsp_infopacket = *update->vsp_infopacket;
2420
2421         if (update->dither_option)
2422                 stream->dither_option = *update->dither_option;
2423
2424         if (update->pending_test_pattern)
2425                 stream->test_pattern = *update->pending_test_pattern;
2426         /* update current stream with writeback info */
2427         if (update->wb_update) {
2428                 int i;
2429
2430                 stream->num_wb_info = update->wb_update->num_wb_info;
2431                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2432                 for (i = 0; i < stream->num_wb_info; i++)
2433                         stream->writeback_info[i] =
2434                                 update->wb_update->writeback_info[i];
2435         }
2436         if (update->dsc_config) {
2437                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2438                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2439                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2440                                        update->dsc_config->num_slices_v != 0);
2441
2442                 /* Use temporarry context for validating new DSC config */
2443                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2444
2445                 if (dsc_validate_context) {
2446                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2447
2448                         stream->timing.dsc_cfg = *update->dsc_config;
2449                         stream->timing.flags.DSC = enable_dsc;
2450                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2451                                 stream->timing.dsc_cfg = old_dsc_cfg;
2452                                 stream->timing.flags.DSC = old_dsc_enabled;
2453                                 update->dsc_config = NULL;
2454                         }
2455
2456                         dc_release_state(dsc_validate_context);
2457                 } else {
2458                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2459                         update->dsc_config = NULL;
2460                 }
2461         }
2462 }
2463
2464 static void commit_planes_do_stream_update(struct dc *dc,
2465                 struct dc_stream_state *stream,
2466                 struct dc_stream_update *stream_update,
2467                 enum surface_update_type update_type,
2468                 struct dc_state *context)
2469 {
2470         int j;
2471
2472         // Stream updates
2473         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2474                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2475
2476                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2477
2478                         if (stream_update->periodic_interrupt0 &&
2479                                         dc->hwss.setup_periodic_interrupt)
2480                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2481
2482                         if (stream_update->periodic_interrupt1 &&
2483                                         dc->hwss.setup_periodic_interrupt)
2484                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2485
2486                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2487                                         stream_update->vrr_infopacket ||
2488                                         stream_update->vsc_infopacket ||
2489                                         stream_update->vsp_infopacket) {
2490                                 resource_build_info_frame(pipe_ctx);
2491                                 dc->hwss.update_info_frame(pipe_ctx);
2492                         }
2493
2494                         if (stream_update->hdr_static_metadata &&
2495                                         stream->use_dynamic_meta &&
2496                                         dc->hwss.set_dmdata_attributes &&
2497                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2498                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2499
2500                         if (stream_update->gamut_remap)
2501                                 dc_stream_set_gamut_remap(dc, stream);
2502
2503                         if (stream_update->output_csc_transform)
2504                                 dc_stream_program_csc_matrix(dc, stream);
2505
2506                         if (stream_update->dither_option) {
2507                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2508                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2509                                                                         &pipe_ctx->stream->bit_depth_params);
2510                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2511                                                 &stream->bit_depth_params,
2512                                                 &stream->clamping);
2513                                 while (odm_pipe) {
2514                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2515                                                         &stream->bit_depth_params,
2516                                                         &stream->clamping);
2517                                         odm_pipe = odm_pipe->next_odm_pipe;
2518                                 }
2519                         }
2520
2521
2522                         /* Full fe update*/
2523                         if (update_type == UPDATE_TYPE_FAST)
2524                                 continue;
2525
2526                         if (stream_update->dsc_config)
2527                                 dp_update_dsc_config(pipe_ctx);
2528
2529                         if (stream_update->pending_test_pattern) {
2530                                 dc_link_dp_set_test_pattern(stream->link,
2531                                         stream->test_pattern.type,
2532                                         stream->test_pattern.color_space,
2533                                         stream->test_pattern.p_link_settings,
2534                                         stream->test_pattern.p_custom_pattern,
2535                                         stream->test_pattern.cust_pattern_size);
2536                         }
2537
2538                         if (stream_update->dpms_off) {
2539                                 if (*stream_update->dpms_off) {
2540                                         core_link_disable_stream(pipe_ctx);
2541                                         /* for dpms, keep acquired resources*/
2542                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2543                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2544
2545                                         dc->optimized_required = true;
2546
2547                                 } else {
2548                                         if (get_seamless_boot_stream_count(context) == 0)
2549                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2550
2551                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2552                                 }
2553                         }
2554
2555                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2556                                 bool should_program_abm = true;
2557
2558                                 // if otg funcs defined check if blanked before programming
2559                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2560                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2561                                                 should_program_abm = false;
2562
2563                                 if (should_program_abm) {
2564                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2565                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2566                                         } else {
2567                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2568                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2569                                         }
2570                                 }
2571                         }
2572                 }
2573         }
2574 }
2575
2576 static void commit_planes_for_stream(struct dc *dc,
2577                 struct dc_surface_update *srf_updates,
2578                 int surface_count,
2579                 struct dc_stream_state *stream,
2580                 struct dc_stream_update *stream_update,
2581                 enum surface_update_type update_type,
2582                 struct dc_state *context)
2583 {
2584         int i, j;
2585         struct pipe_ctx *top_pipe_to_program = NULL;
2586
2587 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
2588         dc_z10_restore(dc);
2589 #endif
2590
2591         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
2592                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2593                  * first flip. After first flip, optimization is required to lower
2594                  * bandwidth. Important to note that it is expected UEFI will
2595                  * only light up a single display on POST, therefore we only expect
2596                  * one stream with seamless boot flag set.
2597                  */
2598                 if (stream->apply_seamless_boot_optimization) {
2599                         stream->apply_seamless_boot_optimization = false;
2600
2601                         if (get_seamless_boot_stream_count(context) == 0)
2602                                 dc->optimized_required = true;
2603                 }
2604         }
2605
2606         if (update_type == UPDATE_TYPE_FULL) {
2607 #if defined(CONFIG_DRM_AMD_DC_DCN)
2608                 dc_allow_idle_optimizations(dc, false);
2609
2610 #endif
2611                 if (get_seamless_boot_stream_count(context) == 0)
2612                         dc->hwss.prepare_bandwidth(dc, context);
2613
2614                 context_clock_trace(dc, context);
2615         }
2616
2617         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2618                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2619
2620                 if (!pipe_ctx->top_pipe &&
2621                         !pipe_ctx->prev_odm_pipe &&
2622                         pipe_ctx->stream &&
2623                         pipe_ctx->stream == stream) {
2624                         top_pipe_to_program = pipe_ctx;
2625                 }
2626         }
2627
2628 #ifdef CONFIG_DRM_AMD_DC_DCN
2629         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2630                 struct pipe_ctx *mpcc_pipe;
2631                 struct pipe_ctx *odm_pipe;
2632
2633                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
2634                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2635                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
2636         }
2637 #endif
2638
2639         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2640                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2641                         if (should_use_dmub_lock(stream->link)) {
2642                                 union dmub_hw_lock_flags hw_locks = { 0 };
2643                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2644
2645                                 hw_locks.bits.lock_dig = 1;
2646                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2647
2648                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2649                                                         true,
2650                                                         &hw_locks,
2651                                                         &inst_flags);
2652                         } else
2653                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2654                                                 top_pipe_to_program->stream_res.tg);
2655                 }
2656
2657         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2658                 dc->hwss.interdependent_update_lock(dc, context, true);
2659         else
2660                 /* Lock the top pipe while updating plane addrs, since freesync requires
2661                  *  plane addr update event triggers to be synchronized.
2662                  *  top_pipe_to_program is expected to never be NULL
2663                  */
2664                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2665
2666         // Stream updates
2667         if (stream_update)
2668                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2669
2670         if (surface_count == 0) {
2671                 /*
2672                  * In case of turning off screen, no need to program front end a second time.
2673                  * just return after program blank.
2674                  */
2675                 if (dc->hwss.apply_ctx_for_surface)
2676                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2677                 if (dc->hwss.program_front_end_for_ctx)
2678                         dc->hwss.program_front_end_for_ctx(dc, context);
2679
2680                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2681                         dc->hwss.interdependent_update_lock(dc, context, false);
2682                 else
2683                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2684                 dc->hwss.post_unlock_program_front_end(dc, context);
2685                 return;
2686         }
2687
2688         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2689                 for (i = 0; i < surface_count; i++) {
2690                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2691                         /*set logical flag for lock/unlock use*/
2692                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2693                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2694                                 if (!pipe_ctx->plane_state)
2695                                         continue;
2696                                 if (pipe_ctx->plane_state != plane_state)
2697                                         continue;
2698                                 plane_state->triplebuffer_flips = false;
2699                                 if (update_type == UPDATE_TYPE_FAST &&
2700                                         dc->hwss.program_triplebuffer != NULL &&
2701                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2702                                                 /*triple buffer for VUpdate  only*/
2703                                                 plane_state->triplebuffer_flips = true;
2704                                 }
2705                         }
2706                         if (update_type == UPDATE_TYPE_FULL) {
2707                                 /* force vsync flip when reconfiguring pipes to prevent underflow */
2708                                 plane_state->flip_immediate = false;
2709                         }
2710                 }
2711         }
2712
2713         // Update Type FULL, Surface updates
2714         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2715                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2716
2717                 if (!pipe_ctx->top_pipe &&
2718                         !pipe_ctx->prev_odm_pipe &&
2719                         pipe_ctx->stream &&
2720                         pipe_ctx->stream == stream) {
2721                         struct dc_stream_status *stream_status = NULL;
2722
2723                         if (!pipe_ctx->plane_state)
2724                                 continue;
2725
2726                         /* Full fe update*/
2727                         if (update_type == UPDATE_TYPE_FAST)
2728                                 continue;
2729
2730                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2731
2732                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2733                                 /*turn off triple buffer for full update*/
2734                                 dc->hwss.program_triplebuffer(
2735                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2736                         }
2737                         stream_status =
2738                                 stream_get_status(context, pipe_ctx->stream);
2739
2740                         if (dc->hwss.apply_ctx_for_surface)
2741                                 dc->hwss.apply_ctx_for_surface(
2742                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2743                 }
2744         }
2745         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2746                 dc->hwss.program_front_end_for_ctx(dc, context);
2747 #ifdef CONFIG_DRM_AMD_DC_DCN
2748                 if (dc->debug.validate_dml_output) {
2749                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2750                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2751                                 if (cur_pipe.stream == NULL)
2752                                         continue;
2753
2754                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2755                                                 cur_pipe.plane_res.hubp, dc->ctx,
2756                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2757                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2758                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2759                         }
2760                 }
2761 #endif
2762         }
2763
2764         // Update Type FAST, Surface updates
2765         if (update_type == UPDATE_TYPE_FAST) {
2766                 if (dc->hwss.set_flip_control_gsl)
2767                         for (i = 0; i < surface_count; i++) {
2768                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2769
2770                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2771                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2772
2773                                         if (pipe_ctx->stream != stream)
2774                                                 continue;
2775
2776                                         if (pipe_ctx->plane_state != plane_state)
2777                                                 continue;
2778
2779                                         // GSL has to be used for flip immediate
2780                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2781                                                         plane_state->flip_immediate);
2782                                 }
2783                         }
2784
2785                 /* Perform requested Updates */
2786                 for (i = 0; i < surface_count; i++) {
2787                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2788
2789                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2790                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2791
2792                                 if (pipe_ctx->stream != stream)
2793                                         continue;
2794
2795                                 if (pipe_ctx->plane_state != plane_state)
2796                                         continue;
2797                                 /*program triple buffer after lock based on flip type*/
2798                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2799                                         /*only enable triplebuffer for  fast_update*/
2800                                         dc->hwss.program_triplebuffer(
2801                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2802                                 }
2803                                 if (srf_updates[i].flip_addr)
2804                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2805                         }
2806                 }
2807
2808         }
2809
2810         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2811                 dc->hwss.interdependent_update_lock(dc, context, false);
2812         else
2813                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2814
2815         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2816                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2817                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2818                                         top_pipe_to_program->stream_res.tg,
2819                                         CRTC_STATE_VACTIVE);
2820                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2821                                         top_pipe_to_program->stream_res.tg,
2822                                         CRTC_STATE_VBLANK);
2823                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2824                                         top_pipe_to_program->stream_res.tg,
2825                                         CRTC_STATE_VACTIVE);
2826
2827                         if (stream && should_use_dmub_lock(stream->link)) {
2828                                 union dmub_hw_lock_flags hw_locks = { 0 };
2829                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2830
2831                                 hw_locks.bits.lock_dig = 1;
2832                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2833
2834                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2835                                                         false,
2836                                                         &hw_locks,
2837                                                         &inst_flags);
2838                         } else
2839                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2840                                         top_pipe_to_program->stream_res.tg);
2841                 }
2842
2843         if (update_type != UPDATE_TYPE_FAST)
2844                 dc->hwss.post_unlock_program_front_end(dc, context);
2845
2846         // Fire manual trigger only when bottom plane is flipped
2847         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2848                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2849
2850                 if (!pipe_ctx->plane_state)
2851                         continue;
2852
2853                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2854                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2855                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
2856                                 pipe_ctx->plane_state->skip_manual_trigger)
2857                         continue;
2858
2859                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2860                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2861         }
2862 }
2863
2864 void dc_commit_updates_for_stream(struct dc *dc,
2865                 struct dc_surface_update *srf_updates,
2866                 int surface_count,
2867                 struct dc_stream_state *stream,
2868                 struct dc_stream_update *stream_update,
2869                 struct dc_state *state)
2870 {
2871         const struct dc_stream_status *stream_status;
2872         enum surface_update_type update_type;
2873         struct dc_state *context;
2874         struct dc_context *dc_ctx = dc->ctx;
2875         int i, j;
2876
2877         stream_status = dc_stream_get_status(stream);
2878         context = dc->current_state;
2879
2880         update_type = dc_check_update_surfaces_for_stream(
2881                                 dc, srf_updates, surface_count, stream_update, stream_status);
2882
2883         if (update_type >= update_surface_trace_level)
2884                 update_surface_trace(dc, srf_updates, surface_count);
2885
2886
2887         if (update_type >= UPDATE_TYPE_FULL) {
2888
2889                 /* initialize scratch memory for building context */
2890                 context = dc_create_state(dc);
2891                 if (context == NULL) {
2892                         DC_ERROR("Failed to allocate new validate context!\n");
2893                         return;
2894                 }
2895
2896                 dc_resource_state_copy_construct(state, context);
2897
2898                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2899                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2900                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2901
2902                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2903                                 new_pipe->plane_state->force_full_update = true;
2904                 }
2905         }
2906
2907
2908         for (i = 0; i < surface_count; i++) {
2909                 struct dc_plane_state *surface = srf_updates[i].surface;
2910
2911                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2912
2913                 if (update_type >= UPDATE_TYPE_MED) {
2914                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2915                                 struct pipe_ctx *pipe_ctx =
2916                                         &context->res_ctx.pipe_ctx[j];
2917
2918                                 if (pipe_ctx->plane_state != surface)
2919                                         continue;
2920
2921                                 resource_build_scaling_params(pipe_ctx);
2922                         }
2923                 }
2924         }
2925
2926         copy_stream_update_to_stream(dc, context, stream, stream_update);
2927
2928         if (update_type >= UPDATE_TYPE_FULL) {
2929                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2930                         DC_ERROR("Mode validation failed for stream update!\n");
2931                         dc_release_state(context);
2932                         return;
2933                 }
2934         }
2935
2936         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2937
2938         commit_planes_for_stream(
2939                                 dc,
2940                                 srf_updates,
2941                                 surface_count,
2942                                 stream,
2943                                 stream_update,
2944                                 update_type,
2945                                 context);
2946         /*update current_State*/
2947         if (dc->current_state != context) {
2948
2949                 struct dc_state *old = dc->current_state;
2950
2951                 dc->current_state = context;
2952                 dc_release_state(old);
2953
2954                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2955                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2956
2957                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2958                                 pipe_ctx->plane_state->force_full_update = false;
2959                 }
2960         }
2961         /*let's use current_state to update watermark etc*/
2962         if (update_type >= UPDATE_TYPE_FULL) {
2963                 dc_post_update_surfaces_to_stream(dc);
2964
2965                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
2966                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2967                 else
2968                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2969         }
2970
2971         return;
2972
2973 }
2974
2975 uint8_t dc_get_current_stream_count(struct dc *dc)
2976 {
2977         return dc->current_state->stream_count;
2978 }
2979
2980 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2981 {
2982         if (i < dc->current_state->stream_count)
2983                 return dc->current_state->streams[i];
2984         return NULL;
2985 }
2986
2987 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
2988 {
2989         uint8_t i;
2990         struct dc_context *ctx = link->ctx;
2991
2992         for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
2993                 if (ctx->dc->current_state->streams[i]->link == link)
2994                         return ctx->dc->current_state->streams[i];
2995         }
2996
2997         return NULL;
2998 }
2999
3000 enum dc_irq_source dc_interrupt_to_irq_source(
3001                 struct dc *dc,
3002                 uint32_t src_id,
3003                 uint32_t ext_id)
3004 {
3005         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
3006 }
3007
3008 /*
3009  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
3010  */
3011 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
3012 {
3013
3014         if (dc == NULL)
3015                 return false;
3016
3017         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
3018 }
3019
3020 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
3021 {
3022         dal_irq_service_ack(dc->res_pool->irqs, src);
3023 }
3024
3025 void dc_power_down_on_boot(struct dc *dc)
3026 {
3027         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
3028                         dc->hwss.power_down_on_boot)
3029                 dc->hwss.power_down_on_boot(dc);
3030 }
3031
3032 void dc_set_power_state(
3033         struct dc *dc,
3034         enum dc_acpi_cm_power_state power_state)
3035 {
3036         struct kref refcount;
3037         struct display_mode_lib *dml;
3038
3039         if (!dc->current_state)
3040                 return;
3041
3042         switch (power_state) {
3043         case DC_ACPI_CM_POWER_STATE_D0:
3044                 dc_resource_state_construct(dc, dc->current_state);
3045
3046 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
3047                 dc_z10_restore(dc);
3048 #endif
3049                 if (dc->ctx->dmub_srv)
3050                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
3051
3052                 dc->hwss.init_hw(dc);
3053
3054                 if (dc->hwss.init_sys_ctx != NULL &&
3055                         dc->vm_pa_config.valid) {
3056                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
3057                 }
3058
3059                 break;
3060         default:
3061                 ASSERT(dc->current_state->stream_count == 0);
3062                 /* Zero out the current context so that on resume we start with
3063                  * clean state, and dc hw programming optimizations will not
3064                  * cause any trouble.
3065                  */
3066                 dml = kzalloc(sizeof(struct display_mode_lib),
3067                                 GFP_KERNEL);
3068
3069                 ASSERT(dml);
3070                 if (!dml)
3071                         return;
3072
3073                 /* Preserve refcount */
3074                 refcount = dc->current_state->refcount;
3075                 /* Preserve display mode lib */
3076                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
3077
3078                 dc_resource_state_destruct(dc->current_state);
3079                 memset(dc->current_state, 0,
3080                                 sizeof(*dc->current_state));
3081
3082                 dc->current_state->refcount = refcount;
3083                 dc->current_state->bw_ctx.dml = *dml;
3084
3085                 kfree(dml);
3086
3087                 break;
3088         }
3089 }
3090
3091 void dc_resume(struct dc *dc)
3092 {
3093         uint32_t i;
3094
3095         for (i = 0; i < dc->link_count; i++)
3096                 core_link_resume(dc->links[i]);
3097 }
3098
3099 bool dc_is_dmcu_initialized(struct dc *dc)
3100 {
3101         struct dmcu *dmcu = dc->res_pool->dmcu;
3102
3103         if (dmcu)
3104                 return dmcu->funcs->is_dmcu_initialized(dmcu);
3105         return false;
3106 }
3107
3108 bool dc_submit_i2c(
3109                 struct dc *dc,
3110                 uint32_t link_index,
3111                 struct i2c_command *cmd)
3112 {
3113
3114         struct dc_link *link = dc->links[link_index];
3115         struct ddc_service *ddc = link->ddc;
3116         return dce_i2c_submit_command(
3117                 dc->res_pool,
3118                 ddc->ddc_pin,
3119                 cmd);
3120 }
3121
3122 bool dc_submit_i2c_oem(
3123                 struct dc *dc,
3124                 struct i2c_command *cmd)
3125 {
3126         struct ddc_service *ddc = dc->res_pool->oem_device;
3127         return dce_i2c_submit_command(
3128                 dc->res_pool,
3129                 ddc->ddc_pin,
3130                 cmd);
3131 }
3132
3133 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
3134 {
3135         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
3136                 BREAK_TO_DEBUGGER();
3137                 return false;
3138         }
3139
3140         dc_sink_retain(sink);
3141
3142         dc_link->remote_sinks[dc_link->sink_count] = sink;
3143         dc_link->sink_count++;
3144
3145         return true;
3146 }
3147
3148 /*
3149  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
3150  *
3151  * EDID length is in bytes
3152  */
3153 struct dc_sink *dc_link_add_remote_sink(
3154                 struct dc_link *link,
3155                 const uint8_t *edid,
3156                 int len,
3157                 struct dc_sink_init_data *init_data)
3158 {
3159         struct dc_sink *dc_sink;
3160         enum dc_edid_status edid_status;
3161
3162         if (len > DC_MAX_EDID_BUFFER_SIZE) {
3163                 dm_error("Max EDID buffer size breached!\n");
3164                 return NULL;
3165         }
3166
3167         if (!init_data) {
3168                 BREAK_TO_DEBUGGER();
3169                 return NULL;
3170         }
3171
3172         if (!init_data->link) {
3173                 BREAK_TO_DEBUGGER();
3174                 return NULL;
3175         }
3176
3177         dc_sink = dc_sink_create(init_data);
3178
3179         if (!dc_sink)
3180                 return NULL;
3181
3182         memmove(dc_sink->dc_edid.raw_edid, edid, len);
3183         dc_sink->dc_edid.length = len;
3184
3185         if (!link_add_remote_sink_helper(
3186                         link,
3187                         dc_sink))
3188                 goto fail_add_sink;
3189
3190         edid_status = dm_helpers_parse_edid_caps(
3191                         link->ctx,
3192                         &dc_sink->dc_edid,
3193                         &dc_sink->edid_caps);
3194
3195         /*
3196          * Treat device as no EDID device if EDID
3197          * parsing fails
3198          */
3199         if (edid_status != EDID_OK) {
3200                 dc_sink->dc_edid.length = 0;
3201                 dm_error("Bad EDID, status%d!\n", edid_status);
3202         }
3203
3204         return dc_sink;
3205
3206 fail_add_sink:
3207         dc_sink_release(dc_sink);
3208         return NULL;
3209 }
3210
3211 /*
3212  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
3213  *
3214  * Note that this just removes the struct dc_sink - it doesn't
3215  * program hardware or alter other members of dc_link
3216  */
3217 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
3218 {
3219         int i;
3220
3221         if (!link->sink_count) {
3222                 BREAK_TO_DEBUGGER();
3223                 return;
3224         }
3225
3226         for (i = 0; i < link->sink_count; i++) {
3227                 if (link->remote_sinks[i] == sink) {
3228                         dc_sink_release(sink);
3229                         link->remote_sinks[i] = NULL;
3230
3231                         /* shrink array to remove empty place */
3232                         while (i < link->sink_count - 1) {
3233                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3234                                 i++;
3235                         }
3236                         link->remote_sinks[i] = NULL;
3237                         link->sink_count--;
3238                         return;
3239                 }
3240         }
3241 }
3242
3243 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3244 {
3245         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3246         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3247         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3248         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3249         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3250         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3251         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3252         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3253         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3254 }
3255 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3256 {
3257         if (dc->hwss.set_clock)
3258                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3259         return DC_ERROR_UNEXPECTED;
3260 }
3261 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3262 {
3263         if (dc->hwss.get_clock)
3264                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3265 }
3266
3267 /* enable/disable eDP PSR without specify stream for eDP */
3268 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3269 {
3270         int i;
3271
3272         for (i = 0; i < dc->current_state->stream_count ; i++) {
3273                 struct dc_link *link;
3274                 struct dc_stream_state *stream = dc->current_state->streams[i];
3275
3276                 link = stream->link;
3277                 if (!link)
3278                         continue;
3279
3280                 if (link->psr_settings.psr_feature_enabled) {
3281                         if (enable && !link->psr_settings.psr_allow_active)
3282                                 return dc_link_set_psr_allow_active(link, true, false, false);
3283                         else if (!enable && link->psr_settings.psr_allow_active)
3284                                 return dc_link_set_psr_allow_active(link, false, true, false);
3285                 }
3286         }
3287
3288         return true;
3289 }
3290
3291 #if defined(CONFIG_DRM_AMD_DC_DCN)
3292
3293 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3294 {
3295         if (dc->debug.disable_idle_power_optimizations)
3296                 return;
3297
3298         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
3299                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
3300                         return;
3301
3302         if (allow == dc->idle_optimizations_allowed)
3303                 return;
3304
3305         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3306                 dc->idle_optimizations_allowed = allow;
3307 }
3308
3309 /*
3310  * blank all streams, and set min and max memory clock to
3311  * lowest and highest DPM level, respectively
3312  */
3313 void dc_unlock_memory_clock_frequency(struct dc *dc)
3314 {
3315         unsigned int i;
3316
3317         for (i = 0; i < MAX_PIPES; i++)
3318                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3319                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3320
3321         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3322         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3323 }
3324
3325 /*
3326  * set min memory clock to the min required for current mode,
3327  * max to maxDPM, and unblank streams
3328  */
3329 void dc_lock_memory_clock_frequency(struct dc *dc)
3330 {
3331         unsigned int i;
3332
3333         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3334         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3335         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3336
3337         for (i = 0; i < MAX_PIPES; i++)
3338                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3339                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3340 }
3341
3342 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
3343                 struct dc_cursor_attributes *cursor_attr)
3344 {
3345         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
3346                 return true;
3347         return false;
3348 }
3349
3350 /* cleanup on driver unload */
3351 void dc_hardware_release(struct dc *dc)
3352 {
3353         if (dc->hwss.hardware_release)
3354                 dc->hwss.hardware_release(dc);
3355 }
3356 #endif
3357
3358 /**
3359  * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled
3360  * @dc: dc structure
3361  *
3362  * Returns: True to enable dmub notifications, False otherwise
3363  */
3364 bool dc_enable_dmub_notifications(struct dc *dc)
3365 {
3366         /* dmub aux needs dmub notifications to be enabled */
3367         return dc->debug.enable_dmub_aux_for_legacy_ddc;
3368 }
3369
3370 /**
3371  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
3372  *                                      Sets port index appropriately for legacy DDC
3373  * @dc: dc structure
3374  * @link_index: link index
3375  * @payload: aux payload
3376  *
3377  * Returns: True if successful, False if failure
3378  */
3379 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
3380                                 uint32_t link_index,
3381                                 struct aux_payload *payload)
3382 {
3383         uint8_t action;
3384         union dmub_rb_cmd cmd = {0};
3385         struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3386
3387         ASSERT(payload->length <= 16);
3388
3389         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
3390         cmd.dp_aux_access.header.payload_bytes = 0;
3391         cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
3392         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
3393         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
3394         cmd.dp_aux_access.aux_control.timeout = 0;
3395         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
3396         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
3397         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
3398
3399         /* set aux action */
3400         if (payload->i2c_over_aux) {
3401                 if (payload->write) {
3402                         if (payload->mot)
3403                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
3404                         else
3405                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
3406                 } else {
3407                         if (payload->mot)
3408                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
3409                         else
3410                                 action = DP_AUX_REQ_ACTION_I2C_READ;
3411                         }
3412         } else {
3413                 if (payload->write)
3414                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
3415                 else
3416                         action = DP_AUX_REQ_ACTION_DPCD_READ;
3417         }
3418
3419         cmd.dp_aux_access.aux_control.dpaux.action = action;
3420
3421         if (payload->length && payload->write) {
3422                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
3423                         payload->data,
3424                         payload->length
3425                         );
3426         }
3427
3428         dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
3429         dc_dmub_srv_cmd_execute(dmub_srv);
3430         dc_dmub_srv_wait_idle(dmub_srv);
3431
3432         return true;
3433 }
3434
3435 /**
3436  * dc_disable_accelerated_mode - disable accelerated mode
3437  * @dc: dc structure
3438  */
3439 void dc_disable_accelerated_mode(struct dc *dc)
3440 {
3441         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
3442 }