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26 #ifndef DAL_DC_316_SMU_H_
27 #define DAL_DC_316_SMU_H_
30 #define PMFW_DRIVER_IF_VERSION 4
32 #define NUM_DCFCLK_DPM_LEVELS 8
33 #define NUM_DISPCLK_DPM_LEVELS 8
34 #define NUM_DPPCLK_DPM_LEVELS 8
35 #define NUM_SOCCLK_DPM_LEVELS 8
36 #define NUM_VCN_DPM_LEVELS 8
37 #define NUM_SOC_VOLTAGE_LEVELS 8
38 #define NUM_DF_PSTATE_LEVELS 4
41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
42 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
46 uint8_t WmType; // Used for normal pstate change or memory retraining
48 } WatermarkRowGeneric_t;
50 #define NUM_WM_RANGES 4
51 #define WM_PSTATE_CHG 0
52 #define WM_RETRAINING 1
61 WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
76 //Voltage in milli volts with 2 fractional bits
78 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
79 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
80 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
81 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
82 uint32_t VClocks[NUM_VCN_DPM_LEVELS];
83 uint32_t DClocks[NUM_VCN_DPM_LEVELS];
84 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
85 DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
86 uint8_t NumDcfClkLevelsEnabled;
87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
88 uint8_t NumSocClkLevelsEnabled;
89 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
90 uint8_t NumDfPstatesEnabled;
96 struct dcn316_watermarks {
98 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
99 uint32_t MmHubPadding[7]; // SMU internal use
102 struct dcn316_smu_dpm_clks {
103 DpmClocks_316_t *dpm_clks;
104 union large_integer mc_address;
107 #define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
108 #define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
110 struct display_idle_optimization {
111 unsigned int df_request_disabled : 1;
112 unsigned int phy_ref_clk_off : 1;
113 unsigned int s0i2_rdy : 1;
114 unsigned int reserved : 29;
117 union display_idle_optimization_u {
118 struct display_idle_optimization idle_info;
122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
124 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
125 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
129 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
132 void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
133 void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
134 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
135 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
136 int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
137 int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);
139 #endif /* DAL_DC_316_SMU_H_ */