drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27
  28 #include "dccg.h"
  29 #include "clk_mgr_internal.h"
  30
  31 // For dce12_get_dp_ref_freq_khz
  32 #include "dce100/dce_clk_mgr.h"
  33 // For dcn20_update_clocks_update_dpp_dto
  34 #include "dcn20/dcn20_clk_mgr.h"
  35 #include "dcn31/dcn31_clk_mgr.h"
  36 #include "dcn316_clk_mgr.h"
  37 #include "reg_helper.h"
  38 #include "core_types.h"
  39 #include "dcn316_smu.h"
  40 #include "dm_helpers.h"
  41 #include "dc_dmub_srv.h"
  42 #include "dc_link_dp.h"
  43
  44 // DCN316 this is CLK1 instance
  45 #define MAX_INSTANCE                                        7
  46 #define MAX_SEGMENT                                         6
  47
  48 struct IP_BASE_INSTANCE
  49 {
  50     unsigned int segment[MAX_SEGMENT];
  51 };
  52
  53 struct IP_BASE
  54 {
  55     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
  56 };
  57
  58 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
  59                                         { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
  60                                         { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
  61                                         { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
  62                                         { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
  63                                         { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
  64                                         { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
  65
  66 #define regCLK1_CLK_PLL_REQ                                             0x0237
  67 #define regCLK1_CLK_PLL_REQ_BASE_IDX                    0
  68
  69 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT             0x0
  70 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT    0xc
  71 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT    0x10
  72 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK               0x000001FFL
  73 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000F000L
  74 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK              0xFFFF0000L
  75
  76 #define REG(reg_name) \
  77         (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
  78
  79 #define TO_CLK_MGR_DCN316(clk_mgr)\
  80         container_of(clk_mgr, struct clk_mgr_dcn316, base)
  81
  82 static int dcn316_get_active_display_cnt_wa(
  83                 struct dc *dc,
  84                 struct dc_state *context)
  85 {
  86         int i, display_count;
  87         bool tmds_present = false;
  88
  89         display_count = 0;
  90         for (i = 0; i < context->stream_count; i++) {
  91                 const struct dc_stream_state *stream = context->streams[i];
  92
  93                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  94                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  95                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  96                         tmds_present = true;
  97         }
  98
  99         for (i = 0; i < dc->link_count; i++) {
 100                 const struct dc_link *link = dc->links[i];
 101
 102                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
 103                 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
 104                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
 105                         display_count++;
 106         }
 107
 108         /* WA for hang on HDMI after display off back back on*/
 109         if (display_count == 0 && tmds_present)
 110                 display_count = 1;
 111
 112         return display_count;
 113 }
 114
 115 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
 116 {
 117         struct dc *dc = clk_mgr_base->ctx->dc;
 118         int i;
 119
 120         for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 121                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 122
 123                 if (pipe->top_pipe || pipe->prev_odm_pipe)
 124                         continue;
 125                 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
 126                                      dc_is_virtual_signal(pipe->stream->signal))) {
 127                         if (disable)
 128                                 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
 129                         else
 130                                 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 131                 }
 132         }
 133 }
 134
 135 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 136 {
 137         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 138
 139         dcn316_smu_enable_pme_wa(clk_mgr);
 140 }
 141
 142 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
 143                         struct dc_state *context,
 144                         bool safe_to_lower)
 145 {
 146         union dmub_rb_cmd cmd;
 147         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 148         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 149         struct dc *dc = clk_mgr_base->ctx->dc;
 150         int display_count;
 151         bool update_dppclk = false;
 152         bool update_dispclk = false;
 153         bool dpp_clock_lowered = false;
 154
 155         if (dc->work_arounds.skip_clock_update)
 156                 return;
 157
 158         /*
 159          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 160          * also if safe to lower is false, we just go in the higher state
 161          */
 162         clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 163         if (safe_to_lower) {
 164                 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
 165                         dcn316_smu_set_dtbclk(clk_mgr, false);
 166                         clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
 167                 }
 168                 /* check that we're not already in lower */
 169                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 170                         display_count = dcn316_get_active_display_cnt_wa(dc, context);
 171                         /* if we can go lower, go lower */
 172                         if (display_count == 0) {
 173                                 union display_idle_optimization_u idle_info = { 0 };
 174                                 idle_info.idle_info.df_request_disabled = 1;
 175                                 idle_info.idle_info.phy_ref_clk_off = 1;
 176                                 idle_info.idle_info.s0i2_rdy = 1;
 177                                 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 178                                 /* update power state */
 179                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 180                         }
 181                 }
 182         } else {
 183                 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
 184                         dcn316_smu_set_dtbclk(clk_mgr, true);
 185                         clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
 186                 }
 187
 188                 /* check that we're not already in D0 */
 189                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 190                         union display_idle_optimization_u idle_info = { 0 };
 191                         dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 192                         /* update power state */
 193                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 194                 }
 195         }
 196
 197         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 198                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 199                 dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 200         }
 201
 202         if (should_set_clock(safe_to_lower,
 203                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 204                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 205                 dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 206         }
 207
 208         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 209         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 210                 if (new_clocks->dppclk_khz < 100000)
 211                         new_clocks->dppclk_khz = 100000;
 212                 if (new_clocks->dispclk_khz < 100000)
 213                         new_clocks->dispclk_khz = 100000;
 214         }
 215
 216         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 217                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 218                         dpp_clock_lowered = true;
 219                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 220                 update_dppclk = true;
 221         }
 222
 223         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 224                 dcn316_disable_otg_wa(clk_mgr_base, true);
 225
 226                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 227                 dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 228                 dcn316_disable_otg_wa(clk_mgr_base, false);
 229
 230                 update_dispclk = true;
 231         }
 232
 233         if (dpp_clock_lowered) {
 234                 // increase per DPP DTO before lowering global dppclk
 235                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 236                 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 237         } else {
 238                 // increase global DPPCLK before lowering per DPP DTO
 239                 if (update_dppclk || update_dispclk)
 240                         dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 241                 // always update dtos unless clock is lowered and not safe to lower
 242                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 243                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 244         }
 245
 246         // notify DMCUB of latest clocks
 247         memset(&cmd, 0, sizeof(cmd));
 248         cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
 249         cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
 250         cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
 251         cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
 252                 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
 253         cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
 254         cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
 255
 256         dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
 257         dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
 258         dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 259 }
 260
 261 static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 262                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 263 {
 264         return;
 265 }
 266
 267 static struct clk_bw_params dcn316_bw_params = {
 268         .vram_type = Ddr4MemType,
 269         .num_channels = 1,
 270         .clk_table = {
 271                 .num_entries = 5,
 272         },
 273
 274 };
 275
 276 static struct wm_table ddr4_wm_table = {
 277         .entries = {
 278                 {
 279                         .wm_inst = WM_A,
 280                         .wm_type = WM_TYPE_PSTATE_CHG,
 281                         .pstate_latency_us = 11.72,
 282                         .sr_exit_time_us = 6.09,
 283                         .sr_enter_plus_exit_time_us = 7.14,
 284                         .valid = true,
 285                 },
 286                 {
 287                         .wm_inst = WM_B,
 288                         .wm_type = WM_TYPE_PSTATE_CHG,
 289                         .pstate_latency_us = 11.72,
 290                         .sr_exit_time_us = 10.12,
 291                         .sr_enter_plus_exit_time_us = 11.48,
 292                         .valid = true,
 293                 },
 294                 {
 295                         .wm_inst = WM_C,
 296                         .wm_type = WM_TYPE_PSTATE_CHG,
 297                         .pstate_latency_us = 11.72,
 298                         .sr_exit_time_us = 10.12,
 299                         .sr_enter_plus_exit_time_us = 11.48,
 300                         .valid = true,
 301                 },
 302                 {
 303                         .wm_inst = WM_D,
 304                         .wm_type = WM_TYPE_PSTATE_CHG,
 305                         .pstate_latency_us = 11.72,
 306                         .sr_exit_time_us = 10.12,
 307                         .sr_enter_plus_exit_time_us = 11.48,
 308                         .valid = true,
 309                 },
 310         }
 311 };
 312
 313 static struct wm_table lpddr5_wm_table = {
 314         .entries = {
 315                 {
 316                         .wm_inst = WM_A,
 317                         .wm_type = WM_TYPE_PSTATE_CHG,
 318                         .pstate_latency_us = 11.65333,
 319                         .sr_exit_time_us = 11.5,
 320                         .sr_enter_plus_exit_time_us = 14.5,
 321                         .valid = true,
 322                 },
 323                 {
 324                         .wm_inst = WM_B,
 325                         .wm_type = WM_TYPE_PSTATE_CHG,
 326                         .pstate_latency_us = 11.65333,
 327                         .sr_exit_time_us = 11.5,
 328                         .sr_enter_plus_exit_time_us = 14.5,
 329                         .valid = true,
 330                 },
 331                 {
 332                         .wm_inst = WM_C,
 333                         .wm_type = WM_TYPE_PSTATE_CHG,
 334                         .pstate_latency_us = 11.65333,
 335                         .sr_exit_time_us = 11.5,
 336                         .sr_enter_plus_exit_time_us = 14.5,
 337                         .valid = true,
 338                 },
 339                 {
 340                         .wm_inst = WM_D,
 341                         .wm_type = WM_TYPE_PSTATE_CHG,
 342                         .pstate_latency_us = 11.65333,
 343                         .sr_exit_time_us = 11.5,
 344                         .sr_enter_plus_exit_time_us = 14.5,
 345                         .valid = true,
 346                 },
 347         }
 348 };
 349
 350 static DpmClocks_316_t dummy_clocks;
 351
 352 static struct dcn316_watermarks dummy_wms = { 0 };
 353
 354 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
 355 {
 356         int i, num_valid_sets;
 357
 358         num_valid_sets = 0;
 359
 360         for (i = 0; i < WM_SET_COUNT; i++) {
 361                 /* skip empty entries, the smu array has no holes*/
 362                 if (!bw_params->wm_table.entries[i].valid)
 363                         continue;
 364
 365                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
 366                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
 367                 /* We will not select WM based on fclk, so leave it as unconstrained */
 368                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 369                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 370
 371                 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
 372                         if (i == 0)
 373                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
 374                         else {
 375                                 /* add 1 to make it non-overlapping with next lvl */
 376                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
 377                                                 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 378                         }
 379                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
 380                                         bw_params->clk_table.entries[i].dcfclk_mhz;
 381
 382                 } else {
 383                         /* unconstrained for memory retraining */
 384                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 385                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 386
 387                         /* Modify previous watermark range to cover up to max */
 388                         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 389                 }
 390                 num_valid_sets++;
 391         }
 392
 393         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 394
 395         /* modify the min and max to make sure we cover the whole range*/
 396         table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
 397         table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
 398         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
 399         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 400
 401         /* This is for writeback only, does not matter currently as no writeback support*/
 402         table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
 403         table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
 404         table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
 405         table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
 406         table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
 407 }
 408
 409 static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 410 {
 411         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 412         struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);
 413         struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
 414
 415         if (!clk_mgr->smu_ver)
 416                 return;
 417
 418         if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
 419                 return;
 420
 421         memset(table, 0, sizeof(*table));
 422
 423         dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
 424
 425         dcn316_smu_set_dram_addr_high(clk_mgr,
 426                         clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
 427         dcn316_smu_set_dram_addr_low(clk_mgr,
 428                         clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
 429         dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 430 }
 431
 432 static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
 433                 struct dcn316_smu_dpm_clks *smu_dpm_clks)
 434 {
 435         DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
 436
 437         if (!clk_mgr->smu_ver)
 438                 return;
 439
 440         if (!table || smu_dpm_clks->mc_address.quad_part == 0)
 441                 return;
 442
 443         memset(table, 0, sizeof(*table));
 444
 445         dcn316_smu_set_dram_addr_high(clk_mgr,
 446                         smu_dpm_clks->mc_address.high_part);
 447         dcn316_smu_set_dram_addr_low(clk_mgr,
 448                         smu_dpm_clks->mc_address.low_part);
 449         dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
 450 }
 451
 452 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
 453 {
 454         uint32_t max = 0;
 455         int i;
 456
 457         for (i = 0; i < num_clocks; ++i) {
 458                 if (clocks[i] > max)
 459                         max = clocks[i];
 460         }
 461
 462         return max;
 463 }
 464
 465 static unsigned int find_clk_for_voltage(
 466                 const DpmClocks_316_t *clock_table,
 467                 const uint32_t clocks[],
 468                 unsigned int voltage)
 469 {
 470         int i;
 471         int max_voltage = 0;
 472         int clock = 0;
 473
 474         for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
 475                 if (clock_table->SocVoltage[i] == voltage) {
 476                         return clocks[i];
 477                 } else if (clock_table->SocVoltage[i] >= max_voltage &&
 478                                 clock_table->SocVoltage[i] < voltage) {
 479                         max_voltage = clock_table->SocVoltage[i];
 480                         clock = clocks[i];
 481                 }
 482         }
 483
 484         ASSERT(clock);
 485         return clock;
 486 }
 487
 488 static void dcn316_clk_mgr_helper_populate_bw_params(
 489                 struct clk_mgr_internal *clk_mgr,
 490                 struct integrated_info *bios_info,
 491                 const DpmClocks_316_t *clock_table)
 492 {
 493         int i, j;
 494         struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
 495         uint32_t max_dispclk = 0, max_dppclk = 0;
 496
 497         j = -1;
 498
 499         ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
 500
 501         /* Find lowest DPM, FCLK is filled in reverse order*/
 502
 503         for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
 504                 if (clock_table->DfPstateTable[i].FClk != 0) {
 505                         j = i;
 506                         break;
 507                 }
 508         }
 509
 510         if (j == -1) {
 511                 /* clock table is all 0s, just use our own hardcode */
 512                 ASSERT(0);
 513                 return;
 514         }
 515
 516         bw_params->clk_table.num_entries = j + 1;
 517
 518         /* dispclk and dppclk can be max at any voltage, same number of levels for both */
 519         if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
 520             clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
 521                 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
 522                 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
 523         } else {
 524                 ASSERT(0);
 525         }
 526
 527         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 528                 int temp;
 529
 530                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
 531                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
 532                 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
 533                 switch (clock_table->DfPstateTable[j].WckRatio) {
 534                 case WCK_RATIO_1_2:
 535                         bw_params->clk_table.entries[i].wck_ratio = 2;
 536                         break;
 537                 case WCK_RATIO_1_4:
 538                         bw_params->clk_table.entries[i].wck_ratio = 4;
 539                         break;
 540                 default:
 541                         bw_params->clk_table.entries[i].wck_ratio = 1;
 542                 }
 543                 temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
 544                 if (temp)
 545                         bw_params->clk_table.entries[i].dcfclk_mhz = temp;
 546                 temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
 547                 if (temp)
 548                         bw_params->clk_table.entries[i].socclk_mhz = temp;
 549                 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
 550                 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
 551         }
 552
 553         bw_params->vram_type = bios_info->memory_type;
 554         bw_params->num_channels = bios_info->ma_channel_number;
 555
 556         for (i = 0; i < WM_SET_COUNT; i++) {
 557                 bw_params->wm_table.entries[i].wm_inst = i;
 558
 559                 if (i >= bw_params->clk_table.num_entries) {
 560                         bw_params->wm_table.entries[i].valid = false;
 561                         continue;
 562                 }
 563
 564                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 565                 bw_params->wm_table.entries[i].valid = true;
 566         }
 567 }
 568
 569
 570
 571 static struct clk_mgr_funcs dcn316_funcs = {
 572         .enable_pme_wa = dcn316_enable_pme_wa,
 573         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 574         .update_clocks = dcn316_update_clocks,
 575         .init_clocks = dcn31_init_clocks,
 576         .are_clock_states_equal = dcn31_are_clock_states_equal,
 577         .notify_wm_ranges = dcn316_notify_wm_ranges
 578 };
 579 extern struct clk_mgr_funcs dcn3_fpga_funcs;
 580
 581 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 582 {
 583         /* get FbMult value */
 584         struct fixed31_32 pll_req;
 585         unsigned int fbmult_frac_val = 0;
 586         unsigned int fbmult_int_val = 0;
 587
 588         /*
 589          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 590          * to leverage the fix point operations available in driver
 591          */
 592
 593         REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 594         REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 595
 596         pll_req = dc_fixpt_from_int(fbmult_int_val);
 597
 598         /*
 599          * since fractional part is only 16 bit in register definition but is 32 bit
 600          * in our fix point definiton, need to shift left by 16 to obtain correct value
 601          */
 602         pll_req.value |= fbmult_frac_val << 16;
 603
 604         /* multiply by REFCLK period */
 605         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 606
 607         /* integer part is now VCO frequency in kHz */
 608         return dc_fixpt_floor(pll_req);
 609 }
 610
 611 void dcn316_clk_mgr_construct(
 612                 struct dc_context *ctx,
 613                 struct clk_mgr_dcn316 *clk_mgr,
 614                 struct pp_smu_funcs *pp_smu,
 615                 struct dccg *dccg)
 616 {
 617         struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
 618
 619         clk_mgr->base.base.ctx = ctx;
 620         clk_mgr->base.base.funcs = &dcn316_funcs;
 621
 622         clk_mgr->base.pp_smu = pp_smu;
 623
 624         clk_mgr->base.dccg = dccg;
 625         clk_mgr->base.dfs_bypass_disp_clk = 0;
 626
 627         clk_mgr->base.dprefclk_ss_percentage = 0;
 628         clk_mgr->base.dprefclk_ss_divider = 1000;
 629         clk_mgr->base.ss_on_dprefclk = false;
 630         clk_mgr->base.dfs_ref_freq_khz = 48000;
 631
 632         clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
 633                                 clk_mgr->base.base.ctx,
 634                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 635                                 sizeof(struct dcn316_watermarks),
 636                                 &clk_mgr->smu_wm_set.mc_address.quad_part);
 637
 638         if (!clk_mgr->smu_wm_set.wm_set) {
 639                 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
 640                 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
 641         }
 642         ASSERT(clk_mgr->smu_wm_set.wm_set);
 643
 644         smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
 645                                 clk_mgr->base.base.ctx,
 646                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 647                                 sizeof(DpmClocks_316_t),
 648                                 &smu_dpm_clks.mc_address.quad_part);
 649
 650         if (smu_dpm_clks.dpm_clks == NULL) {
 651                 smu_dpm_clks.dpm_clks = &dummy_clocks;
 652                 smu_dpm_clks.mc_address.quad_part = 0;
 653         }
 654
 655         ASSERT(smu_dpm_clks.dpm_clks);
 656
 657         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 658                 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
 659                 clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
 660         } else {
 661                 struct clk_log_info log_info = {0};
 662
 663                 clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
 664
 665                 if (clk_mgr->base.smu_ver > 0)
 666                         clk_mgr->base.smu_present = true;
 667
 668                 // Skip this for now as it did not work on DCN315, renable during bring up
 669                 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
 670
 671                 /* in case we don't get a value from the register, use default */
 672                 if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
 673                         clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */
 674
 675
 676                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
 677                         dcn316_bw_params.wm_table = lpddr5_wm_table;
 678                 } else {
 679                         dcn316_bw_params.wm_table = ddr4_wm_table;
 680                 }
 681                 /* Saved clocks configured at boot for debug purposes */
 682                  dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
 683
 684         }
 685
 686         clk_mgr->base.base.dprefclk_khz = 600000;
 687         clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
 688         clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
 689         dce_clock_read_ss_info(&clk_mgr->base);
 690         /*clk_mgr->base.dccg->ref_dtbclk_khz =
 691         dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
 692
 693         clk_mgr->base.base.bw_params = &dcn316_bw_params;
 694
 695         if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
 696                 dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
 697
 698                 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
 699                         dcn316_clk_mgr_helper_populate_bw_params(
 700                                         &clk_mgr->base,
 701                                         ctx->dc_bios->integrated_info,
 702                                         smu_dpm_clks.dpm_clks);
 703                 }
 704         }
 705
 706         if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
 707                 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 708                                 smu_dpm_clks.dpm_clks);
 709 }
 710
 711 void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
 712 {
 713         struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);
 714
 715         if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
 716                 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 717                                 clk_mgr->smu_wm_set.wm_set);
 718 }