2 * Copyright 2019 Advanced Micro Devices, Inc.
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26 #ifndef __DCN31_CLK_MGR_H__
27 #define __DCN31_CLK_MGR_H__
28 #include "clk_mgr_internal.h"
31 #ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
32 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
33 #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
34 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
35 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
36 #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
37 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
39 #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0
40 #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL
41 /*DPREF clock related*/
42 #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
43 #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
44 #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
45 #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
46 #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
47 #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
48 #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
49 #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
51 //CLK3_0_CLK3_CLK_PLL_REQ
52 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
53 #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
54 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
55 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
56 #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
57 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
59 #define mmCLK0_CLK3_DFS_CNTL 0x16C60
60 #define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60
61 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60
62 #define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060
63 #define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260
65 #define mmCLK0_CLK_PLL_REQ 0x16C10
66 #define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10
67 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10
68 #define mmCLK02_CLK0_CLK_PLL_REQ 0x17010
69 #define mmCLK03_CLK0_CLK_PLL_REQ 0x17210
71 #define mmCLK1_CLK_PLL_REQ 0x1B00D
72 #define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D
73 #define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
74 #define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D
75 #define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D
77 #define mmCLK2_CLK_PLL_REQ 0x17E0D
80 #define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F
81 #define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
84 struct dcn31_watermarks;
86 struct dcn31_smu_watermark_set {
87 struct dcn31_watermarks *wm_set;
88 union large_integer mc_address;
91 struct clk_mgr_dcn31 {
92 struct clk_mgr_internal base;
93 struct dcn31_smu_watermark_set smu_wm_set;
96 void dcn31_clk_mgr_construct(struct dc_context *ctx,
97 struct clk_mgr_dcn31 *clk_mgr,
98 struct pp_smu_funcs *pp_smu,
101 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
103 #endif //__DCN31_CLK_MGR_H__