2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #include "clk_mgr_internal.h"
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
34 // For dcn20_update_clocks_update_dpp_dto
35 #include "dcn20/dcn20_clk_mgr.h"
39 #include "dcn31_clk_mgr.h"
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn31_smu.h"
44 #include "dm_helpers.h"
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
49 #include "dc_dmub_srv.h"
51 #include "yellow_carp_offset.h"
53 #define regCLK1_CLK_PLL_REQ 0x0237
54 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
56 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
57 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
58 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
59 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
60 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
61 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
63 #define REG(reg_name) \
64 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
66 #define TO_CLK_MGR_DCN31(clk_mgr)\
67 container_of(clk_mgr, struct clk_mgr_dcn31, base)
69 static int dcn31_get_active_display_cnt_wa(
71 struct dc_state *context)
74 bool tmds_present = false;
77 for (i = 0; i < context->stream_count; i++) {
78 const struct dc_stream_state *stream = context->streams[i];
80 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
81 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
82 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
86 for (i = 0; i < dc->link_count; i++) {
87 const struct dc_link *link = dc->links[i];
89 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
90 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
91 link->link_enc->funcs->is_dig_enabled(link->link_enc))
95 /* WA for hang on HDMI after display off back back on*/
96 if (display_count == 0 && tmds_present)
102 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
104 struct dc *dc = clk_mgr_base->ctx->dc;
107 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
108 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
110 if (pipe->top_pipe || pipe->prev_odm_pipe)
112 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
114 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
116 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
121 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
122 struct dc_state *context,
125 union dmub_rb_cmd cmd;
126 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
128 struct dc *dc = clk_mgr_base->ctx->dc;
130 bool update_dppclk = false;
131 bool update_dispclk = false;
132 bool dpp_clock_lowered = false;
134 if (dc->work_arounds.skip_clock_update)
138 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
139 * also if safe to lower is false, we just go in the higher state
142 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
143 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
144 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
145 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
149 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
150 dcn31_smu_set_dtbclk(clk_mgr, false);
151 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
153 /* check that we're not already in lower */
154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
155 display_count = dcn31_get_active_display_cnt_wa(dc, context);
156 /* if we can go lower, go lower */
157 if (display_count == 0) {
158 union display_idle_optimization_u idle_info = { 0 };
159 idle_info.idle_info.df_request_disabled = 1;
160 idle_info.idle_info.phy_ref_clk_off = 1;
161 idle_info.idle_info.s0i2_rdy = 1;
162 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
163 /* update power state */
164 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
168 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
169 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
170 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
171 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
172 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
175 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
176 dcn31_smu_set_dtbclk(clk_mgr, true);
177 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
180 /* check that we're not already in D0 */
181 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
182 union display_idle_optimization_u idle_info = { 0 };
183 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
184 /* update power state */
185 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
189 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
190 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
191 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
194 if (should_set_clock(safe_to_lower,
195 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
196 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
197 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
200 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
201 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
202 if (new_clocks->dppclk_khz < 100000)
203 new_clocks->dppclk_khz = 100000;
206 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
207 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
208 dpp_clock_lowered = true;
209 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
210 update_dppclk = true;
213 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
214 dcn31_disable_otg_wa(clk_mgr_base, true);
216 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
217 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
218 dcn31_disable_otg_wa(clk_mgr_base, false);
220 update_dispclk = true;
223 if (dpp_clock_lowered) {
224 // increase per DPP DTO before lowering global dppclk
225 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
226 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
228 // increase global DPPCLK before lowering per DPP DTO
229 if (update_dppclk || update_dispclk)
230 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
231 // always update dtos unless clock is lowered and not safe to lower
232 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
233 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
236 // notify DMCUB of latest clocks
237 memset(&cmd, 0, sizeof(cmd));
238 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
239 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
240 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
241 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
242 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
243 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
244 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
246 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
247 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
248 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
251 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
253 /* get FbMult value */
254 struct fixed31_32 pll_req;
255 unsigned int fbmult_frac_val = 0;
256 unsigned int fbmult_int_val = 0;
259 * Register value of fbmult is in 8.16 format, we are converting to 31.32
260 * to leverage the fix point operations available in driver
263 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
264 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
266 pll_req = dc_fixpt_from_int(fbmult_int_val);
269 * since fractional part is only 16 bit in register definition but is 32 bit
270 * in our fix point definiton, need to shift left by 16 to obtain correct value
272 pll_req.value |= fbmult_frac_val << 16;
274 /* multiply by REFCLK period */
275 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
277 /* integer part is now VCO frequency in kHz */
278 return dc_fixpt_floor(pll_req);
281 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
283 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
285 dcn31_smu_enable_pme_wa(clk_mgr);
288 void dcn31_init_clocks(struct clk_mgr *clk_mgr)
290 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
291 // Assumption is that boot state always supports pstate
292 clk_mgr->clks.p_state_change_support = true;
293 clk_mgr->clks.prev_p_state_change_support = true;
294 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
295 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
298 bool dcn31_are_clock_states_equal(struct dc_clocks *a,
301 if (a->dispclk_khz != b->dispclk_khz)
303 else if (a->dppclk_khz != b->dppclk_khz)
305 else if (a->dcfclk_khz != b->dcfclk_khz)
307 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
309 else if (a->zstate_support != b->zstate_support)
311 else if (a->dtbclk_en != b->dtbclk_en)
317 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
318 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
323 static struct clk_bw_params dcn31_bw_params = {
324 .vram_type = Ddr4MemType,
332 static struct wm_table ddr5_wm_table = {
336 .wm_type = WM_TYPE_PSTATE_CHG,
337 .pstate_latency_us = 11.72,
338 .sr_exit_time_us = 9,
339 .sr_enter_plus_exit_time_us = 11,
344 .wm_type = WM_TYPE_PSTATE_CHG,
345 .pstate_latency_us = 11.72,
346 .sr_exit_time_us = 9,
347 .sr_enter_plus_exit_time_us = 11,
352 .wm_type = WM_TYPE_PSTATE_CHG,
353 .pstate_latency_us = 11.72,
354 .sr_exit_time_us = 9,
355 .sr_enter_plus_exit_time_us = 11,
360 .wm_type = WM_TYPE_PSTATE_CHG,
361 .pstate_latency_us = 11.72,
362 .sr_exit_time_us = 9,
363 .sr_enter_plus_exit_time_us = 11,
369 static struct wm_table lpddr5_wm_table = {
373 .wm_type = WM_TYPE_PSTATE_CHG,
374 .pstate_latency_us = 11.65333,
375 .sr_exit_time_us = 11.5,
376 .sr_enter_plus_exit_time_us = 14.5,
381 .wm_type = WM_TYPE_PSTATE_CHG,
382 .pstate_latency_us = 11.65333,
383 .sr_exit_time_us = 11.5,
384 .sr_enter_plus_exit_time_us = 14.5,
389 .wm_type = WM_TYPE_PSTATE_CHG,
390 .pstate_latency_us = 11.65333,
391 .sr_exit_time_us = 11.5,
392 .sr_enter_plus_exit_time_us = 14.5,
397 .wm_type = WM_TYPE_PSTATE_CHG,
398 .pstate_latency_us = 11.65333,
399 .sr_exit_time_us = 11.5,
400 .sr_enter_plus_exit_time_us = 14.5,
406 static DpmClocks_t dummy_clocks;
408 static struct dcn31_watermarks dummy_wms = { 0 };
410 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
412 int i, num_valid_sets;
416 for (i = 0; i < WM_SET_COUNT; i++) {
417 /* skip empty entries, the smu array has no holes*/
418 if (!bw_params->wm_table.entries[i].valid)
421 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
423 /* We will not select WM based on fclk, so leave it as unconstrained */
424 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
425 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
427 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
431 /* add 1 to make it non-overlapping with next lvl */
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
433 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
436 bw_params->clk_table.entries[i].dcfclk_mhz;
439 /* unconstrained for memory retraining */
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
443 /* Modify previous watermark range to cover up to max */
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
449 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
451 /* modify the min and max to make sure we cover the whole range*/
452 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
453 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
454 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
457 /* This is for writeback only, does not matter currently as no writeback support*/
458 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
459 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
460 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
461 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
462 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
465 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
467 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
468 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
469 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
471 if (!clk_mgr->smu_ver)
474 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
477 memset(table, 0, sizeof(*table));
479 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
481 dcn31_smu_set_dram_addr_high(clk_mgr,
482 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
483 dcn31_smu_set_dram_addr_low(clk_mgr,
484 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
485 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
488 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
489 struct dcn31_smu_dpm_clks *smu_dpm_clks)
491 DpmClocks_t *table = smu_dpm_clks->dpm_clks;
493 if (!clk_mgr->smu_ver)
496 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
499 memset(table, 0, sizeof(*table));
501 dcn31_smu_set_dram_addr_high(clk_mgr,
502 smu_dpm_clks->mc_address.high_part);
503 dcn31_smu_set_dram_addr_low(clk_mgr,
504 smu_dpm_clks->mc_address.low_part);
505 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
508 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
513 for (i = 0; i < num_clocks; ++i) {
521 static unsigned int find_clk_for_voltage(
522 const DpmClocks_t *clock_table,
523 const uint32_t clocks[],
524 unsigned int voltage)
530 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
531 if (clock_table->SocVoltage[i] == voltage) {
533 } else if (clock_table->SocVoltage[i] >= max_voltage &&
534 clock_table->SocVoltage[i] < voltage) {
535 max_voltage = clock_table->SocVoltage[i];
544 static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
545 struct integrated_info *bios_info,
546 const DpmClocks_t *clock_table)
549 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
550 uint32_t max_dispclk = 0, max_dppclk = 0;
554 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
556 /* Find lowest DPM, FCLK is filled in reverse order*/
558 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
559 if (clock_table->DfPstateTable[i].FClk != 0) {
566 /* clock table is all 0s, just use our own hardcode */
571 bw_params->clk_table.num_entries = j + 1;
573 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
574 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
575 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
576 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
577 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
582 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
583 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
584 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
585 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
586 switch (clock_table->DfPstateTable[j].WckRatio) {
588 bw_params->clk_table.entries[i].wck_ratio = 2;
591 bw_params->clk_table.entries[i].wck_ratio = 4;
594 bw_params->clk_table.entries[i].wck_ratio = 1;
596 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
597 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
598 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
599 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
602 bw_params->vram_type = bios_info->memory_type;
603 bw_params->num_channels = bios_info->ma_channel_number;
605 for (i = 0; i < WM_SET_COUNT; i++) {
606 bw_params->wm_table.entries[i].wm_inst = i;
608 if (i >= bw_params->clk_table.num_entries) {
609 bw_params->wm_table.entries[i].valid = false;
613 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
614 bw_params->wm_table.entries[i].valid = true;
618 void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
621 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
622 struct dc *dc = clk_mgr_base->ctx->dc;
623 struct dc_state *context = dc->current_state;
625 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
626 display_count = dcn31_get_active_display_cnt_wa(dc, context);
627 /* if we can go lower, go lower */
628 if (display_count == 0) {
629 union display_idle_optimization_u idle_info = { 0 };
631 idle_info.idle_info.df_request_disabled = 1;
632 idle_info.idle_info.phy_ref_clk_off = 1;
633 idle_info.idle_info.s0i2_rdy = 1;
634 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
635 /* update power state */
636 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
641 static struct clk_mgr_funcs dcn31_funcs = {
642 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
643 .update_clocks = dcn31_update_clocks,
644 .init_clocks = dcn31_init_clocks,
645 .enable_pme_wa = dcn31_enable_pme_wa,
646 .are_clock_states_equal = dcn31_are_clock_states_equal,
647 .notify_wm_ranges = dcn31_notify_wm_ranges,
648 .set_low_power_state = dcn31_set_low_power_state
650 extern struct clk_mgr_funcs dcn3_fpga_funcs;
652 void dcn31_clk_mgr_construct(
653 struct dc_context *ctx,
654 struct clk_mgr_dcn31 *clk_mgr,
655 struct pp_smu_funcs *pp_smu,
658 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
660 clk_mgr->base.base.ctx = ctx;
661 clk_mgr->base.base.funcs = &dcn31_funcs;
663 clk_mgr->base.pp_smu = pp_smu;
665 clk_mgr->base.dccg = dccg;
666 clk_mgr->base.dfs_bypass_disp_clk = 0;
668 clk_mgr->base.dprefclk_ss_percentage = 0;
669 clk_mgr->base.dprefclk_ss_divider = 1000;
670 clk_mgr->base.ss_on_dprefclk = false;
671 clk_mgr->base.dfs_ref_freq_khz = 48000;
673 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
674 clk_mgr->base.base.ctx,
675 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
676 sizeof(struct dcn31_watermarks),
677 &clk_mgr->smu_wm_set.mc_address.quad_part);
679 if (!clk_mgr->smu_wm_set.wm_set) {
680 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
681 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
683 ASSERT(clk_mgr->smu_wm_set.wm_set);
685 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
686 clk_mgr->base.base.ctx,
687 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
689 &smu_dpm_clks.mc_address.quad_part);
691 if (smu_dpm_clks.dpm_clks == NULL) {
692 smu_dpm_clks.dpm_clks = &dummy_clocks;
693 smu_dpm_clks.mc_address.quad_part = 0;
696 ASSERT(smu_dpm_clks.dpm_clks);
698 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
699 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
701 struct clk_log_info log_info = {0};
703 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
705 if (clk_mgr->base.smu_ver)
706 clk_mgr->base.smu_present = true;
708 /* TODO: Check we get what we expect during bringup */
709 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
711 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
712 dcn31_bw_params.wm_table = lpddr5_wm_table;
714 dcn31_bw_params.wm_table = ddr5_wm_table;
716 /* Saved clocks configured at boot for debug purposes */
717 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
721 clk_mgr->base.base.dprefclk_khz = 600000;
722 clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
723 dce_clock_read_ss_info(&clk_mgr->base);
724 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
725 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
727 clk_mgr->base.base.bw_params = &dcn31_bw_params;
729 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
730 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
732 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
733 dcn31_clk_mgr_helper_populate_bw_params(
735 ctx->dc_bios->integrated_info,
736 smu_dpm_clks.dpm_clks);
740 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
741 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
742 smu_dpm_clks.dpm_clks);
745 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
747 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
749 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
750 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
751 clk_mgr->smu_wm_set.wm_set);