2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "clk_mgr_internal.h"
28 #include "dcn30_clk_mgr_smu_msg.h"
29 #include "dcn20/dcn20_clk_mgr.h"
30 #include "dce100/dce_clk_mgr.h"
31 #include "dcn30/dcn30_clk_mgr.h"
32 #include "reg_helper.h"
33 #include "core_types.h"
34 #include "dm_helpers.h"
35 #include "atomfirmware.h"
36 #include "sienna_cichlid_ip_offset.h"
37 #include "dcn/dcn_3_0_0_offset.h"
38 #include "dcn/dcn_3_0_0_sh_mask.h"
39 #include "nbio/nbio_7_4_offset.h"
40 #include "dpcs/dpcs_3_0_0_offset.h"
41 #include "dpcs/dpcs_3_0_0_sh_mask.h"
42 #include "mmhub/mmhub_2_0_0_offset.h"
43 #include "mmhub/mmhub_2_0_0_sh_mask.h"
44 #include "dcn30_smu11_driver_if.h"
47 #define FN(reg_name, field_name) \
48 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
55 #define BASE(seg) BASE_INNER(seg)
58 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
62 #define CLK_SRI(reg_name, block, inst)\
63 .reg_name = mm ## block ## _ ## reg_name
65 static const struct clk_mgr_registers clk_mgr_regs = {
69 static const struct clk_mgr_shift clk_mgr_shift = {
70 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT)
73 static const struct clk_mgr_mask clk_mgr_mask = {
74 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)
78 /* Query SMU for all clock states for a particular clock */
79 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)
82 char *entry_i = (char *)entry_0;
83 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
86 /* fine-grained, only min and max */
89 /* discrete, a number of fixed states */
90 /* will set num_levels to 0 on failure */
91 *num_levels = ret & 0xFF;
93 /* if the initial message failed, num_levels will be 0 */
94 for (i = 0; i < *num_levels; i++) {
95 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
96 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
100 static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
103 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
104 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
105 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
106 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
108 /* Set A - Normal - default values*/
109 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
110 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
111 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
112 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
113 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
114 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
115 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
119 /* Set B - Performance - higher minimum clocks */
120 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
121 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
122 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
123 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
124 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
125 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;
126 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
127 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;
128 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
130 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
131 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
132 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
133 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
134 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
135 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
136 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;
137 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
141 /* Set D - MALL - SR enter and exit times adjusted for MALL */
142 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
144 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
145 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
147 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
148 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
149 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
150 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
153 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
155 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
156 unsigned int num_levels;
158 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
159 clk_mgr_base->clks.p_state_change_support = true;
160 clk_mgr_base->clks.prev_p_state_change_support = true;
161 clk_mgr->smu_present = false;
163 if (!clk_mgr_base->bw_params)
166 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
167 clk_mgr->smu_present = true;
169 if (!clk_mgr->smu_present)
172 // do we fail if these fail? if so, how? do we not care to check?
173 dcn30_smu_check_driver_if_version(clk_mgr);
174 dcn30_smu_check_msg_header_version(clk_mgr);
177 dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,
178 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
180 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, 0);
183 dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,
184 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
188 dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
194 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
195 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
199 dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,
200 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
204 dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
205 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
208 /* Get UCLK, update bounding box */
209 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
213 dcn3_build_wm_range_table(clk_mgr);
217 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
219 /* get FbMult value */
220 struct fixed31_32 pll_req;
221 /* get FbMult value */
222 uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
224 /* set up a fixed-point number
225 * this works because the int part is on the right edge of the register
226 * and the frac part is on the left edge
228 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
229 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
231 /* multiply by REFCLK period */
232 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
234 return dc_fixpt_floor(pll_req);
237 static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
238 struct dc_state *context,
241 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
242 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
243 struct dc *dc = clk_mgr_base->ctx->dc;
245 bool update_dppclk = false;
246 bool update_dispclk = false;
247 bool enter_display_off = false;
248 bool dpp_clock_lowered = false;
249 bool update_pstate_unsupported_clk = false;
250 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
251 bool force_reset = false;
252 bool update_uclk = false;
253 bool p_state_change_support;
254 int total_plane_count;
256 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
259 if (clk_mgr_base->clks.dispclk_khz == 0 ||
260 (dc->debug.force_clock_mode & 0x1)) {
261 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */
264 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
266 /* force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. */
268 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
270 if (display_count == 0)
271 enter_display_off = true;
273 if (enter_display_off == safe_to_lower)
274 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
276 if (dc->debug.force_min_dcfclk_mhz > 0)
277 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
278 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
280 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
281 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
282 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
285 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
286 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
287 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
290 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
291 /* We don't actually care about socclk, don't notify SMU of hard min */
292 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
294 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
295 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
296 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
298 // invalidate the current P-State forced min in certain dc_mode_softmax situations
299 if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {
300 if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) !=
301 (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000))
302 update_pstate_unsupported_clk = true;
305 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) ||
306 update_pstate_unsupported_clk) {
307 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
309 /* to disable P-State switching, set UCLK min = max */
310 if (!clk_mgr_base->clks.p_state_change_support) {
311 if (dc->clk_mgr->dc_mode_softmax_enabled &&
312 new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
313 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
314 dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
316 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
317 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
321 /* Always update saved value, even if new value not set due to P-State switching unsupported */
322 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
323 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
327 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
328 if (clk_mgr_base->clks.p_state_change_support &&
329 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
330 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
332 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
333 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
334 dpp_clock_lowered = true;
336 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
337 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
338 update_dppclk = true;
341 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
342 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
343 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
344 update_dispclk = true;
347 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
348 if (dpp_clock_lowered) {
349 /* if clock is being lowered, increase DTO before lowering refclk */
350 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
351 dcn20_update_clocks_update_dentist(clk_mgr, context);
353 /* if clock is being raised, increase refclk before lowering DTO */
354 if (update_dppclk || update_dispclk)
355 dcn20_update_clocks_update_dentist(clk_mgr, context);
356 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
357 * that we do not lower dto when it is not safe to lower. We do not need to
358 * compare the current and new dppclk before calling this function.*/
359 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
363 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
364 /*update dmcu for wait_loop count*/
365 dmcu->funcs->set_psr_wait_loop(dmcu,
366 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
370 static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
373 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
374 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
376 if (!clk_mgr->smu_present)
380 // should log failure
383 memset(table, 0, sizeof(*table));
385 /* collect valid ranges, place in pmfw table */
386 for (i = 0; i < WM_SET_COUNT; i++)
387 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
388 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
389 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
390 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
391 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
392 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
393 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
396 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
397 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
398 dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);
401 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
402 static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
404 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
406 if (!clk_mgr->smu_present)
410 if (clk_mgr_base->clks.p_state_change_support)
411 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
412 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
414 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
415 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
417 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
418 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
422 /* Set max memclk to highest DPM value */
423 static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
425 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
427 if (!clk_mgr->smu_present)
430 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
431 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
434 static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
436 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
438 if (!clk_mgr->smu_present)
441 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
443 static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
445 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
447 if (!clk_mgr->smu_present)
449 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
452 /* Get current memclk states, update bounding box */
453 static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
455 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
456 unsigned int num_levels;
458 if (!clk_mgr->smu_present)
461 /* Refresh memclk states */
462 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
463 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
465 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
467 clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
469 /* Refresh bounding box */
471 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
472 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
476 static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
478 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
479 return clk_mgr->smu_present;
482 static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
485 if (a->dispclk_khz != b->dispclk_khz)
487 else if (a->dppclk_khz != b->dppclk_khz)
489 else if (a->dcfclk_khz != b->dcfclk_khz)
491 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
493 else if (a->dramclk_khz != b->dramclk_khz)
495 else if (a->p_state_change_support != b->p_state_change_support)
501 static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
503 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
505 if (!clk_mgr->smu_present)
508 dcn30_smu_set_pme_workaround(clk_mgr);
511 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
512 static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
514 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
515 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
517 if (!clk_mgr->smu_present)
520 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
522 for (i = 0; i < MAX_PIPES * 2; i++) {
523 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
524 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
527 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
528 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
529 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
533 static struct clk_mgr_funcs dcn3_funcs = {
534 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
535 .update_clocks = dcn3_update_clocks,
536 .init_clocks = dcn3_init_clocks,
537 .notify_wm_ranges = dcn3_notify_wm_ranges,
538 .set_hard_min_memclk = dcn3_set_hard_min_memclk,
539 .set_hard_max_memclk = dcn3_set_hard_max_memclk,
540 .set_max_memclk = dcn3_set_max_memclk,
541 .set_min_memclk = dcn3_set_min_memclk,
542 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
543 .are_clock_states_equal = dcn3_are_clock_states_equal,
544 .enable_pme_wa = dcn3_enable_pme_wa,
545 .notify_link_rate_change = dcn30_notify_link_rate_change,
546 .is_smu_present = dcn3_is_smu_present
549 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
551 dcn2_init_clocks(clk_mgr);
553 /* TODO: Implement the functions and remove the ifndef guard */
556 struct clk_mgr_funcs dcn3_fpga_funcs = {
557 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
558 .update_clocks = dcn2_update_clocks_fpga,
559 .init_clocks = dcn3_init_clocks_fpga,
562 /*todo for dcn30 for clk register offset*/
563 void dcn3_clk_mgr_construct(
564 struct dc_context *ctx,
565 struct clk_mgr_internal *clk_mgr,
566 struct pp_smu_funcs *pp_smu,
569 clk_mgr->base.ctx = ctx;
570 clk_mgr->base.funcs = &dcn3_funcs;
571 clk_mgr->regs = &clk_mgr_regs;
572 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
573 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
575 clk_mgr->dccg = dccg;
576 clk_mgr->dfs_bypass_disp_clk = 0;
578 clk_mgr->dprefclk_ss_percentage = 0;
579 clk_mgr->dprefclk_ss_divider = 1000;
580 clk_mgr->ss_on_dprefclk = false;
581 clk_mgr->dfs_ref_freq_khz = 100000;
583 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
585 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
586 clk_mgr->base.funcs = &dcn3_fpga_funcs;
587 clk_mgr->base.dentist_vco_freq_khz = 3650000;
590 struct clk_state_registers_and_bypass s = { 0 };
592 /* integer part is now VCO frequency in kHz */
593 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
595 /* in case we don't get a value from the register, use default */
596 if (clk_mgr->base.dentist_vco_freq_khz == 0)
597 clk_mgr->base.dentist_vco_freq_khz = 3650000;
598 /* Convert dprefclk units from MHz to KHz */
599 /* Value already divided by 10, some resolution lost */
601 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */
602 //ASSERT(s.dprefclk != 0);
604 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
607 clk_mgr->dfs_bypass_enabled = false;
609 clk_mgr->smu_present = false;
611 dce_clock_read_ss_info(clk_mgr);
613 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
615 /* need physical address of table to give to PMFW */
616 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
617 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
618 &clk_mgr->wm_range_table_addr);
621 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
623 kfree(clk_mgr->base.bw_params);
625 if (clk_mgr->wm_range_table)
626 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
627 clk_mgr->wm_range_table);