drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28 #include "dcn30_clk_mgr_smu_msg.h"
  29 #include "dcn20/dcn20_clk_mgr.h"
  30 #include "dce100/dce_clk_mgr.h"
  31 #include "dcn30/dcn30_clk_mgr.h"
  32 #include "reg_helper.h"
  33 #include "core_types.h"
  34 #include "dm_helpers.h"
  35 #include "atomfirmware.h"
  36 #include "sienna_cichlid_ip_offset.h"
  37 #include "dcn/dcn_3_0_0_offset.h"
  38 #include "dcn/dcn_3_0_0_sh_mask.h"
  39 #include "nbio/nbio_7_4_offset.h"
  40 #include "dpcs/dpcs_3_0_0_offset.h"
  41 #include "dpcs/dpcs_3_0_0_sh_mask.h"
  42 #include "mmhub/mmhub_2_0_0_offset.h"
  43 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  44 #include "dcn30_smu11_driver_if.h"
  45
  46 #undef FN
  47 #define FN(reg_name, field_name) \
  48         clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
  49
  50 #define REG(reg) \
  51         (clk_mgr->regs->reg)
  52
  53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
  54
  55 #define BASE(seg) BASE_INNER(seg)
  56
  57 #define SR(reg_name)\
  58                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
  59                                         mm ## reg_name
  60
  61 #undef CLK_SRI
  62 #define CLK_SRI(reg_name, block, inst)\
  63         .reg_name = mm ## block ## _ ## reg_name
  64
  65 static const struct clk_mgr_registers clk_mgr_regs = {
  66         CLK_REG_LIST_DCN3()
  67 };
  68
  69 static const struct clk_mgr_shift clk_mgr_shift = {
  70         CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT)
  71 };
  72
  73 static const struct clk_mgr_mask clk_mgr_mask = {
  74         CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)
  75 };
  76
  77
  78 /* Query SMU for all clock states for a particular clock */
  79 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)
  80 {
  81         unsigned int i;
  82         char *entry_i = (char *)entry_0;
  83         uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
  84
  85         if (ret & (1 << 31))
  86                 /* fine-grained, only min and max */
  87                 *num_levels = 2;
  88         else
  89                 /* discrete, a number of fixed states */
  90                 /* will set num_levels to 0 on failure */
  91                 *num_levels = ret & 0xFF;
  92
  93         /* if the initial message failed, num_levels will be 0 */
  94         for (i = 0; i < *num_levels; i++) {
  95                 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
  96                 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
  97         }
  98 }
  99
 100 static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 101 {
 102         /* defaults */
 103         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 104         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 105         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 106         uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 107
 108         /* Set A - Normal - default values*/
 109         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 110         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 111         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 112         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 113         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 114         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
 115         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 116         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 117         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 118
 119         /* Set B - Performance - higher minimum clocks */
 120 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 121 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 122 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 123 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 124 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 125 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;
 126 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 127 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;
 128 //      clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 129
 130         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 131         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 132         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;
 133         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 134         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 135         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 136         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;
 137         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 138         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 139         clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 140         clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;
 141         clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
 142         clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;
 143         clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 144         clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;
 145         clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 146         clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = 16000;
 147         clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 148
 149         /* Set D - MALL - SR enter and exit times adjusted for MALL */
 150         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 151         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
 152         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
 153         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
 154         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 155         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
 156         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 157         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 158         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 159 }
 160
 161 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
 162 {
 163         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 164         unsigned int num_levels;
 165
 166         memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
 167         clk_mgr_base->clks.p_state_change_support = true;
 168         clk_mgr_base->clks.prev_p_state_change_support = true;
 169         clk_mgr->smu_present = false;
 170
 171         if (!clk_mgr_base->bw_params)
 172                 return;
 173
 174         if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
 175                 clk_mgr->smu_present = true;
 176
 177         if (!clk_mgr->smu_present)
 178                 return;
 179
 180         // do we fail if these fail? if so, how? do we not care to check?
 181         dcn30_smu_check_driver_if_version(clk_mgr);
 182         dcn30_smu_check_msg_header_version(clk_mgr);
 183
 184         /* DCFCLK */
 185         dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,
 186                         &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
 187                         &num_levels);
 188         dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, 0);
 189
 190         /* DTBCLK */
 191         dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,
 192                         &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
 193                         &num_levels);
 194
 195         /* SOCCLK */
 196         dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
 197                                         &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
 198                                         &num_levels);
 199         // DPREFCLK ???
 200
 201         /* DISPCLK */
 202         dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
 203                         &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
 204                         &num_levels);
 205
 206         /* DPPCLK */
 207         dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,
 208                         &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
 209                         &num_levels);
 210
 211         /* PHYCLK */
 212         dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
 213                         &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
 214                         &num_levels);
 215
 216         /* Get UCLK, update bounding box */
 217         clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
 218
 219         /* WM range table */
 220         DC_FP_START();
 221         dcn3_build_wm_range_table(clk_mgr);
 222         DC_FP_END();
 223 }
 224
 225 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 226 {
 227         /* get FbMult value */
 228         struct fixed31_32 pll_req;
 229         /* get FbMult value */
 230         uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
 231
 232         /* set up a fixed-point number
 233          * this works because the int part is on the right edge of the register
 234          * and the frac part is on the left edge
 235          */
 236         pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
 237         pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
 238
 239         /* multiply by REFCLK period */
 240         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 241
 242         return dc_fixpt_floor(pll_req);
 243 }
 244
 245 static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 246                         struct dc_state *context,
 247                         bool safe_to_lower)
 248 {
 249         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 250         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 251         struct dc *dc = clk_mgr_base->ctx->dc;
 252         int display_count;
 253         bool update_dppclk = false;
 254         bool update_dispclk = false;
 255         bool enter_display_off = false;
 256         bool dpp_clock_lowered = false;
 257         bool update_pstate_unsupported_clk = false;
 258         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 259         bool force_reset = false;
 260         bool update_uclk = false;
 261         bool p_state_change_support;
 262         int total_plane_count;
 263
 264         if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
 265                 return;
 266
 267         if (clk_mgr_base->clks.dispclk_khz == 0 ||
 268                         (dc->debug.force_clock_mode & 0x1)) {
 269                 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */
 270                 force_reset = true;
 271
 272                 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
 273
 274                 /* force_clock_mode 0x1:  force reset the clock even it is the same clock as long as it is in Passive level. */
 275         }
 276         display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
 277
 278         if (display_count == 0)
 279                 enter_display_off = true;
 280
 281         if (enter_display_off == safe_to_lower)
 282                 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
 283
 284         if (dc->debug.force_min_dcfclk_mhz > 0)
 285                 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
 286                                 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
 287
 288         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 289                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 290                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
 291         }
 292
 293         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 294                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 295                 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
 296         }
 297
 298         if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
 299                 /* We don't actually care about socclk, don't notify SMU of hard min */
 300                 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
 301
 302         clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
 303         total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
 304         p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
 305
 306         // invalidate the current P-State forced min in certain dc_mode_softmax situations
 307         if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {
 308                 if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) !=
 309                                 (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000))
 310                         update_pstate_unsupported_clk = true;
 311         }
 312
 313         if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) ||
 314                         update_pstate_unsupported_clk) {
 315                 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
 316
 317                 /* to disable P-State switching, set UCLK min = max */
 318                 if (!clk_mgr_base->clks.p_state_change_support) {
 319                         if (dc->clk_mgr->dc_mode_softmax_enabled &&
 320                                 new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
 321                                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 322                                         dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
 323                         else
 324                                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 325                                         clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 326                 }
 327         }
 328
 329         /* Always update saved value, even if new value not set due to P-State switching unsupported */
 330         if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
 331                 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
 332                 update_uclk = true;
 333         }
 334
 335         /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
 336         if (clk_mgr_base->clks.p_state_change_support &&
 337                         (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
 338                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 339
 340         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
 341                 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
 342                         dpp_clock_lowered = true;
 343
 344                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 345                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
 346                 update_dppclk = true;
 347         }
 348
 349         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 350                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 351                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
 352                 update_dispclk = true;
 353         }
 354
 355         if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
 356                 if (dpp_clock_lowered) {
 357                         /* if clock is being lowered, increase DTO before lowering refclk */
 358                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 359                         dcn20_update_clocks_update_dentist(clk_mgr, context);
 360                 } else {
 361                         /* if clock is being raised, increase refclk before lowering DTO */
 362                         if (update_dppclk || update_dispclk)
 363                                 dcn20_update_clocks_update_dentist(clk_mgr, context);
 364                         /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
 365                          * that we do not lower dto when it is not safe to lower. We do not need to
 366                          * compare the current and new dppclk before calling this function.*/
 367                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 368                 }
 369         }
 370
 371         if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 372                 /*update dmcu for wait_loop count*/
 373                 dmcu->funcs->set_psr_wait_loop(dmcu,
 374                                 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 375 }
 376
 377
 378 static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 379 {
 380         unsigned int i;
 381         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 382         WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
 383
 384         if (!clk_mgr->smu_present)
 385                 return;
 386
 387         if (!table)
 388                 // should log failure
 389                 return;
 390
 391         memset(table, 0, sizeof(*table));
 392
 393         /* collect valid ranges, place in pmfw table */
 394         for (i = 0; i < WM_SET_COUNT; i++)
 395                 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
 396                         table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
 397                         table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
 398                         table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
 399                         table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
 400                         table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
 401                         table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
 402                 }
 403
 404         dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
 405         dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
 406         dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 407 }
 408
 409 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
 410 static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
 411 {
 412         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 413
 414         if (!clk_mgr->smu_present)
 415                 return;
 416
 417         if (current_mode) {
 418                 if (clk_mgr_base->clks.p_state_change_support)
 419                         dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 420                                         khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 421                 else
 422                         dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 423                                         clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 424         } else {
 425                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
 426                                 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
 427         }
 428 }
 429
 430 /* Set max memclk to highest DPM value */
 431 static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
 432 {
 433         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 434
 435         if (!clk_mgr->smu_present)
 436                 return;
 437
 438         dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
 439                         clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 440 }
 441
 442 static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
 443 {
 444         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 445
 446         if (!clk_mgr->smu_present)
 447                 return;
 448
 449         dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
 450 }
 451 static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
 452 {
 453         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 454
 455         if (!clk_mgr->smu_present)
 456                 return;
 457         dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
 458 }
 459
 460 /* Get current memclk states, update bounding box */
 461 static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 462 {
 463         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 464         unsigned int num_levels;
 465
 466         if (!clk_mgr->smu_present)
 467                 return;
 468
 469         /* Refresh memclk states */
 470         dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
 471                         &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
 472                         &num_levels);
 473         clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
 474
 475         clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
 476
 477         /* Refresh bounding box */
 478         DC_FP_START();
 479         clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
 480                         clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
 481         DC_FP_END();
 482 }
 483
 484 static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
 485 {
 486         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 487         return clk_mgr->smu_present;
 488 }
 489
 490 static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
 491                                         struct dc_clocks *b)
 492 {
 493         if (a->dispclk_khz != b->dispclk_khz)
 494                 return false;
 495         else if (a->dppclk_khz != b->dppclk_khz)
 496                 return false;
 497         else if (a->dcfclk_khz != b->dcfclk_khz)
 498                 return false;
 499         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 500                 return false;
 501         else if (a->dramclk_khz != b->dramclk_khz)
 502                 return false;
 503         else if (a->p_state_change_support != b->p_state_change_support)
 504                 return false;
 505
 506         return true;
 507 }
 508
 509 static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 510 {
 511         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 512
 513         if (!clk_mgr->smu_present)
 514                 return;
 515
 516         dcn30_smu_set_pme_workaround(clk_mgr);
 517 }
 518
 519 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
 520 static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
 521 {
 522         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 523         unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
 524
 525         if (!clk_mgr->smu_present)
 526                 return;
 527
 528         /* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */
 529
 530         clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 531
 532         for (i = 0; i < MAX_PIPES * 2; i++) {
 533                 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
 534                         max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
 535         }
 536
 537         if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
 538                 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
 539                 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
 540         }
 541 }
 542
 543 static struct clk_mgr_funcs dcn3_funcs = {
 544                 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 545                 .update_clocks = dcn3_update_clocks,
 546                 .init_clocks = dcn3_init_clocks,
 547                 .notify_wm_ranges = dcn3_notify_wm_ranges,
 548                 .set_hard_min_memclk = dcn3_set_hard_min_memclk,
 549                 .set_hard_max_memclk = dcn3_set_hard_max_memclk,
 550                 .set_max_memclk = dcn3_set_max_memclk,
 551                 .set_min_memclk = dcn3_set_min_memclk,
 552                 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
 553                 .are_clock_states_equal = dcn3_are_clock_states_equal,
 554                 .enable_pme_wa = dcn3_enable_pme_wa,
 555                 .notify_link_rate_change = dcn30_notify_link_rate_change,
 556                 .is_smu_present = dcn3_is_smu_present
 557 };
 558
 559 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
 560 {
 561         dcn2_init_clocks(clk_mgr);
 562
 563 /* TODO: Implement the functions and remove the ifndef guard */
 564 }
 565
 566 struct clk_mgr_funcs dcn3_fpga_funcs = {
 567         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 568         .update_clocks = dcn2_update_clocks_fpga,
 569         .init_clocks = dcn3_init_clocks_fpga,
 570 };
 571
 572 /*todo for dcn30 for clk register offset*/
 573 void dcn3_clk_mgr_construct(
 574                 struct dc_context *ctx,
 575                 struct clk_mgr_internal *clk_mgr,
 576                 struct pp_smu_funcs *pp_smu,
 577                 struct dccg *dccg)
 578 {
 579         clk_mgr->base.ctx = ctx;
 580         clk_mgr->base.funcs = &dcn3_funcs;
 581         clk_mgr->regs = &clk_mgr_regs;
 582         clk_mgr->clk_mgr_shift = &clk_mgr_shift;
 583         clk_mgr->clk_mgr_mask = &clk_mgr_mask;
 584
 585         clk_mgr->dccg = dccg;
 586         clk_mgr->dfs_bypass_disp_clk = 0;
 587
 588         clk_mgr->dprefclk_ss_percentage = 0;
 589         clk_mgr->dprefclk_ss_divider = 1000;
 590         clk_mgr->ss_on_dprefclk = false;
 591         clk_mgr->dfs_ref_freq_khz = 100000;
 592
 593         clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
 594
 595         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 596                 clk_mgr->base.funcs  = &dcn3_fpga_funcs;
 597                 clk_mgr->base.dentist_vco_freq_khz = 3650000;
 598
 599         } else {
 600                 struct clk_state_registers_and_bypass s = { 0 };
 601
 602                 /* integer part is now VCO frequency in kHz */
 603                 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
 604
 605                 /* in case we don't get a value from the register, use default */
 606                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 607                         clk_mgr->base.dentist_vco_freq_khz = 3650000;
 608                 /* Convert dprefclk units from MHz to KHz */
 609                 /* Value already divided by 10, some resolution lost */
 610
 611                 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */
 612                 //ASSERT(s.dprefclk != 0);
 613                 if (s.dprefclk != 0)
 614                         clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
 615         }
 616
 617         clk_mgr->dfs_bypass_enabled = false;
 618
 619         clk_mgr->smu_present = false;
 620
 621         dce_clock_read_ss_info(clk_mgr);
 622
 623         clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
 624
 625         /* need physical address of table to give to PMFW */
 626         clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
 627                         DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
 628                         &clk_mgr->wm_range_table_addr);
 629 }
 630
 631 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
 632 {
 633         if (clk_mgr->base.bw_params)
 634                 kfree(clk_mgr->base.bw_params);
 635
 636         if (clk_mgr->wm_range_table)
 637                 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
 638                                 clk_mgr->wm_range_table);
 639 }