drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "rn_clk_mgr.h"
  28
  29 #include "dcn20/dcn20_clk_mgr.h"
  30 #include "dml/dcn20/dcn20_fpu.h"
  31
  32 #include "dce100/dce_clk_mgr.h"
  33 #include "rn_clk_mgr_vbios_smu.h"
  34 #include "reg_helper.h"
  35 #include "core_types.h"
  36 #include "dm_helpers.h"
  37
  38 #include "atomfirmware.h"
  39 #include "clk/clk_10_0_2_offset.h"
  40 #include "clk/clk_10_0_2_sh_mask.h"
  41 #include "renoir_ip_offset.h"
  42
  43
  44 /* Constants */
  45
  46 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */
  47
  48 /* Macros */
  49
  50 #define REG(reg_name) \
  51         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  52
  53
  54 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  55 static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)
  56 {
  57         int i, display_count;
  58         bool tmds_present = false;
  59
  60         display_count = 0;
  61         for (i = 0; i < context->stream_count; i++) {
  62                 const struct dc_stream_state *stream = context->streams[i];
  63
  64                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  65                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  66                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  67                         tmds_present = true;
  68         }
  69
  70         for (i = 0; i < dc->link_count; i++) {
  71                 const struct dc_link *link = dc->links[i];
  72
  73                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  74                 if (link->link_enc->funcs->is_dig_enabled &&
  75                     link->link_enc->funcs->is_dig_enabled(link->link_enc))
  76                         display_count++;
  77         }
  78
  79         /* WA for hang on HDMI after display off back back on*/
  80         if (display_count == 0 && tmds_present)
  81                 display_count = 1;
  82
  83         return display_count;
  84 }
  85
  86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
  87 {
  88         int display_count;
  89         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
  90         struct dc *dc = clk_mgr_base->ctx->dc;
  91         struct dc_state *context = dc->current_state;
  92
  93         if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
  94
  95                 display_count = rn_get_active_display_cnt_wa(dc, context);
  96
  97                 /* if we can go lower, go lower */
  98                 if (display_count == 0) {
  99                         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 100                         /* update power state */
 101                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 102                 }
 103         }
 104 }
 105
 106 static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 107                 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)
 108 {
 109         int i;
 110
 111         clk_mgr->dccg->ref_dppclk = ref_dpp_clk;
 112
 113         for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 114                 int dpp_inst, dppclk_khz, prev_dppclk_khz;
 115
 116                 /* Loop index may not match dpp->inst if some pipes disabled,
 117                  * so select correct inst from res_pool
 118                  */
 119                 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
 120                 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 121
 122                 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];
 123
 124                 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
 125                         clk_mgr->dccg->funcs->update_dpp_dto(
 126                                                         clk_mgr->dccg, dpp_inst, dppclk_khz);
 127         }
 128 }
 129
 130
 131 static void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 132                         struct dc_state *context,
 133                         bool safe_to_lower)
 134 {
 135         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 136         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 137         struct dc *dc = clk_mgr_base->ctx->dc;
 138         int display_count;
 139         bool update_dppclk = false;
 140         bool update_dispclk = false;
 141         bool dpp_clock_lowered = false;
 142
 143         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 144
 145         if (dc->work_arounds.skip_clock_update)
 146                 return;
 147
 148         /*
 149          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 150          * also if safe to lower is false, we just go in the higher state
 151          */
 152         if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {
 153                 /* check that we're not already in lower */
 154                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 155
 156                         display_count = rn_get_active_display_cnt_wa(dc, context);
 157
 158                         /* if we can go lower, go lower */
 159                         if (display_count == 0) {
 160                                 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 161                                 /* update power state */
 162                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 163                         }
 164                 }
 165         } else {
 166                 /* check that we're not already in D0 */
 167                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 168                         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
 169                         /* update power state */
 170                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 171                 }
 172         }
 173
 174         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 175                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 176                 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 177         }
 178
 179         if (should_set_clock(safe_to_lower,
 180                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 181                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 182                 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 183         }
 184
 185         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 186         // Do not adjust dppclk if dppclk is 0 to avoid unexpected result
 187         if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
 188                 new_clocks->dppclk_khz = 100000;
 189
 190         /*
 191          * Temporally ignore thew 0 cases for disp and dpp clks.
 192          * We may have a new feature that requires 0 clks in the future.
 193          */
 194         if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
 195                 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
 196                 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
 197         }
 198
 199         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
 200                 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
 201                         dpp_clock_lowered = true;
 202                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 203                 update_dppclk = true;
 204         }
 205
 206         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 207                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 208                 clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 209
 210                 update_dispclk = true;
 211         }
 212
 213         if (dpp_clock_lowered) {
 214                 // increase per DPP DTO before lowering global dppclk with requested dppclk
 215                 rn_update_clocks_update_dpp_dto(
 216                                 clk_mgr,
 217                                 context,
 218                                 clk_mgr_base->clks.dppclk_khz,
 219                                 safe_to_lower);
 220
 221                 clk_mgr_base->clks.actual_dppclk_khz =
 222                                 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 223
 224                 //update dpp dto with actual dpp clk.
 225                 rn_update_clocks_update_dpp_dto(
 226                                 clk_mgr,
 227                                 context,
 228                                 clk_mgr_base->clks.actual_dppclk_khz,
 229                                 safe_to_lower);
 230
 231         } else {
 232                 // increase global DPPCLK before lowering per DPP DTO
 233                 if (update_dppclk || update_dispclk)
 234                         clk_mgr_base->clks.actual_dppclk_khz =
 235                                         rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 236
 237                 // always update dtos unless clock is lowered and not safe to lower
 238                 rn_update_clocks_update_dpp_dto(
 239                                 clk_mgr,
 240                                 context,
 241                                 clk_mgr_base->clks.actual_dppclk_khz,
 242                                 safe_to_lower);
 243         }
 244
 245         if (update_dispclk &&
 246                         dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 247                 /*update dmcu for wait_loop count*/
 248                 dmcu->funcs->set_psr_wait_loop(dmcu,
 249                         clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 250         }
 251 }
 252
 253 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 254 {
 255         /* get FbMult value */
 256         struct fixed31_32 pll_req;
 257         unsigned int fbmult_frac_val = 0;
 258         unsigned int fbmult_int_val = 0;
 259
 260
 261         /*
 262          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 263          * to leverage the fix point operations available in driver
 264          */
 265
 266         REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 267         REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 268
 269         pll_req = dc_fixpt_from_int(fbmult_int_val);
 270
 271         /*
 272          * since fractional part is only 16 bit in register definition but is 32 bit
 273          * in our fix point definiton, need to shift left by 16 to obtain correct value
 274          */
 275         pll_req.value |= fbmult_frac_val << 16;
 276
 277         /* multiply by REFCLK period */
 278         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 279
 280         /* integer part is now VCO frequency in kHz */
 281         return dc_fixpt_floor(pll_req);
 282 }
 283
 284 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 285 {
 286         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 287
 288         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
 289         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
 290
 291         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);      //dcf deep sleep divider
 292         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
 293
 294         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
 295         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
 296
 297         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
 298         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
 299
 300         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
 301         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
 302 }
 303
 304 /* This function collect raw clk register values */
 305 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 306                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 307 {
 308         struct rn_clk_internal internal = {0};
 309         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 310         unsigned int chars_printed = 0;
 311         unsigned int remaining_buffer = log_info->bufSize;
 312
 313         rn_dump_clk_registers_internal(&internal, clk_mgr_base);
 314
 315         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 316         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 317         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 318         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 319         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 320         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 321
 322         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 323         if (regs_and_bypass->dppclk_bypass > 4)
 324                 regs_and_bypass->dppclk_bypass = 0;
 325         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 326         if (regs_and_bypass->dcfclk_bypass > 4)
 327                 regs_and_bypass->dcfclk_bypass = 0;
 328         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 329         if (regs_and_bypass->dispclk_bypass > 4)
 330                 regs_and_bypass->dispclk_bypass = 0;
 331         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 332         if (regs_and_bypass->dprefclk_bypass > 4)
 333                 regs_and_bypass->dprefclk_bypass = 0;
 334
 335         if (log_info->enabled) {
 336                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 337                 remaining_buffer -= chars_printed;
 338                 *log_info->sum_chars_printed += chars_printed;
 339                 log_info->pBuf += chars_printed;
 340
 341                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 342                         regs_and_bypass->dcfclk,
 343                         regs_and_bypass->dcf_deep_sleep_divider,
 344                         regs_and_bypass->dcf_deep_sleep_allow,
 345                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 346                 remaining_buffer -= chars_printed;
 347                 *log_info->sum_chars_printed += chars_printed;
 348                 log_info->pBuf += chars_printed;
 349
 350                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 351                         regs_and_bypass->dprefclk,
 352                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 353                 remaining_buffer -= chars_printed;
 354                 *log_info->sum_chars_printed += chars_printed;
 355                 log_info->pBuf += chars_printed;
 356
 357                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 358                         regs_and_bypass->dispclk,
 359                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 360                 remaining_buffer -= chars_printed;
 361                 *log_info->sum_chars_printed += chars_printed;
 362                 log_info->pBuf += chars_printed;
 363
 364                 //split
 365                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 366                 remaining_buffer -= chars_printed;
 367                 *log_info->sum_chars_printed += chars_printed;
 368                 log_info->pBuf += chars_printed;
 369
 370                 // REGISTER VALUES
 371                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 372                 remaining_buffer -= chars_printed;
 373                 *log_info->sum_chars_printed += chars_printed;
 374                 log_info->pBuf += chars_printed;
 375
 376                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 377                                 internal.CLK1_CLK3_CURRENT_CNT);
 378                 remaining_buffer -= chars_printed;
 379                 *log_info->sum_chars_printed += chars_printed;
 380                 log_info->pBuf += chars_printed;
 381
 382                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 383                                         internal.CLK1_CLK3_DS_CNTL);
 384                 remaining_buffer -= chars_printed;
 385                 *log_info->sum_chars_printed += chars_printed;
 386                 log_info->pBuf += chars_printed;
 387
 388                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 389                                         internal.CLK1_CLK3_ALLOW_DS);
 390                 remaining_buffer -= chars_printed;
 391                 *log_info->sum_chars_printed += chars_printed;
 392                 log_info->pBuf += chars_printed;
 393
 394                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 395                                         internal.CLK1_CLK2_CURRENT_CNT);
 396                 remaining_buffer -= chars_printed;
 397                 *log_info->sum_chars_printed += chars_printed;
 398                 log_info->pBuf += chars_printed;
 399
 400                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 401                                         internal.CLK1_CLK0_CURRENT_CNT);
 402                 remaining_buffer -= chars_printed;
 403                 *log_info->sum_chars_printed += chars_printed;
 404                 log_info->pBuf += chars_printed;
 405
 406                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 407                                         internal.CLK1_CLK1_CURRENT_CNT);
 408                 remaining_buffer -= chars_printed;
 409                 *log_info->sum_chars_printed += chars_printed;
 410                 log_info->pBuf += chars_printed;
 411
 412                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 413                                         internal.CLK1_CLK3_BYPASS_CNTL);
 414                 remaining_buffer -= chars_printed;
 415                 *log_info->sum_chars_printed += chars_printed;
 416                 log_info->pBuf += chars_printed;
 417
 418                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 419                                         internal.CLK1_CLK2_BYPASS_CNTL);
 420                 remaining_buffer -= chars_printed;
 421                 *log_info->sum_chars_printed += chars_printed;
 422                 log_info->pBuf += chars_printed;
 423
 424                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 425                                         internal.CLK1_CLK0_BYPASS_CNTL);
 426                 remaining_buffer -= chars_printed;
 427                 *log_info->sum_chars_printed += chars_printed;
 428                 log_info->pBuf += chars_printed;
 429
 430                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 431                                         internal.CLK1_CLK1_BYPASS_CNTL);
 432                 remaining_buffer -= chars_printed;
 433                 *log_info->sum_chars_printed += chars_printed;
 434                 log_info->pBuf += chars_printed;
 435         }
 436 }
 437
 438 static void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 439 {
 440         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 441
 442         rn_vbios_smu_enable_pme_wa(clk_mgr);
 443 }
 444
 445 static void rn_init_clocks(struct clk_mgr *clk_mgr)
 446 {
 447         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 448         // Assumption is that boot state always supports pstate
 449         clk_mgr->clks.p_state_change_support = true;
 450         clk_mgr->clks.prev_p_state_change_support = true;
 451         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 452 }
 453
 454 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 455 {
 456         int i, num_valid_sets;
 457
 458         num_valid_sets = 0;
 459
 460         for (i = 0; i < WM_SET_COUNT; i++) {
 461                 /* skip empty entries, the smu array has no holes*/
 462                 if (!bw_params->wm_table.entries[i].valid)
 463                         continue;
 464
 465                 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
 466                 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
 467                 /* We will not select WM based on fclk, so leave it as unconstrained */
 468                 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 469                 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 470                 /* dcfclk wil be used to select WM*/
 471
 472                 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
 473                         if (i == 0)
 474                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
 475                         else {
 476                                 /* add 1 to make it non-overlapping with next lvl */
 477                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 478                         }
 479                         ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
 480
 481                 } else {
 482                         /* unconstrained for memory retraining */
 483                         ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 484                         ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 485
 486                         /* Modify previous watermark range to cover up to max */
 487                         if (num_valid_sets > 0)
 488                                 ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 489                 }
 490                 num_valid_sets++;
 491         }
 492
 493         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 494         ranges->num_reader_wm_sets = num_valid_sets;
 495
 496         /* modify the min and max to make sure we cover the whole range*/
 497         ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 498         ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 499         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 500         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 501
 502         /* This is for writeback only, does not matter currently as no writeback support*/
 503         ranges->num_writer_wm_sets = 1;
 504         ranges->writer_wm_sets[0].wm_inst = WM_A;
 505         ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 506         ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 507         ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 508         ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 509
 510 }
 511
 512 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 513 {
 514         struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
 515         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 516         struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
 517
 518         if (!debug->disable_pplib_wm_range) {
 519                 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
 520
 521                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 522                 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
 523                         pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);
 524         }
 525
 526 }
 527
 528 static bool rn_are_clock_states_equal(struct dc_clocks *a,
 529                 struct dc_clocks *b)
 530 {
 531         if (a->dispclk_khz != b->dispclk_khz)
 532                 return false;
 533         else if (a->dppclk_khz != b->dppclk_khz)
 534                 return false;
 535         else if (a->dcfclk_khz != b->dcfclk_khz)
 536                 return false;
 537         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 538                 return false;
 539
 540         return true;
 541 }
 542
 543
 544 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
 545 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
 546 {
 547         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 548         unsigned int i, max_phyclk_req = 0;
 549
 550         clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 551
 552         for (i = 0; i < MAX_LINKS; i++) {
 553                 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
 554                         max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
 555         }
 556
 557         if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
 558                 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
 559                 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
 560         }
 561 }
 562
 563 static struct clk_mgr_funcs dcn21_funcs = {
 564         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 565         .update_clocks = rn_update_clocks,
 566         .init_clocks = rn_init_clocks,
 567         .enable_pme_wa = rn_enable_pme_wa,
 568         .are_clock_states_equal = rn_are_clock_states_equal,
 569         .set_low_power_state = rn_set_low_power_state,
 570         .notify_wm_ranges = rn_notify_wm_ranges,
 571         .notify_link_rate_change = rn_notify_link_rate_change,
 572 };
 573
 574 static struct clk_bw_params rn_bw_params = {
 575         .vram_type = Ddr4MemType,
 576         .num_channels = 1,
 577         .clk_table = {
 578                 .entries = {
 579                         {
 580                                 .voltage = 0,
 581                                 .dcfclk_mhz = 400,
 582                                 .fclk_mhz = 400,
 583                                 .memclk_mhz = 800,
 584                                 .socclk_mhz = 0,
 585                         },
 586                         {
 587                                 .voltage = 0,
 588                                 .dcfclk_mhz = 483,
 589                                 .fclk_mhz = 800,
 590                                 .memclk_mhz = 1600,
 591                                 .socclk_mhz = 0,
 592                         },
 593                         {
 594                                 .voltage = 0,
 595                                 .dcfclk_mhz = 602,
 596                                 .fclk_mhz = 1067,
 597                                 .memclk_mhz = 1067,
 598                                 .socclk_mhz = 0,
 599                         },
 600                         {
 601                                 .voltage = 0,
 602                                 .dcfclk_mhz = 738,
 603                                 .fclk_mhz = 1333,
 604                                 .memclk_mhz = 1600,
 605                                 .socclk_mhz = 0,
 606                         },
 607                 },
 608
 609                 .num_entries = 4,
 610         },
 611
 612 };
 613
 614 static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 615 {
 616         int i;
 617
 618         for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
 619                 if (clock_table->SocClocks[i].Vol == voltage)
 620                         return clock_table->SocClocks[i].Freq;
 621         }
 622
 623         ASSERT(0);
 624         return 0;
 625 }
 626
 627 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 628 {
 629         int i;
 630
 631         for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
 632                 if (clock_table->DcfClocks[i].Vol == voltage)
 633                         return clock_table->DcfClocks[i].Freq;
 634         }
 635
 636         ASSERT(0);
 637         return 0;
 638 }
 639
 640 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 641 {
 642         int i, j = 0;
 643
 644         j = -1;
 645
 646         static_assert(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL,
 647                 "number of reported FCLK DPM levels exceed maximum");
 648
 649         /* Find lowest DPM, FCLK is filled in reverse order*/
 650
 651         for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 652                 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) {
 653                         j = i;
 654                         break;
 655                 }
 656         }
 657
 658         if (j == -1) {
 659                 /* clock table is all 0s, just use our own hardcode */
 660                 ASSERT(0);
 661                 return;
 662         }
 663
 664         bw_params->clk_table.num_entries = j + 1;
 665
 666         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 667                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
 668                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
 669                 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
 670                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
 671                 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table,
 672                                                                         bw_params->clk_table.entries[i].voltage);
 673         }
 674
 675         bw_params->vram_type = bios_info->memory_type;
 676         bw_params->num_channels = bios_info->ma_channel_number;
 677
 678         for (i = 0; i < WM_SET_COUNT; i++) {
 679                 bw_params->wm_table.entries[i].wm_inst = i;
 680
 681                 if (i >= bw_params->clk_table.num_entries) {
 682                         bw_params->wm_table.entries[i].valid = false;
 683                         continue;
 684                 }
 685
 686                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 687                 bw_params->wm_table.entries[i].valid = true;
 688         }
 689
 690         if (bw_params->vram_type == LpDdr4MemType) {
 691                 /*
 692                  * WM set D will be re-purposed for memory retraining
 693                  */
 694                 DC_FP_START();
 695                 dcn21_clk_mgr_set_bw_params_wm_table(bw_params);
 696                 DC_FP_END();
 697         }
 698 }
 699
 700 void rn_clk_mgr_construct(
 701                 struct dc_context *ctx,
 702                 struct clk_mgr_internal *clk_mgr,
 703                 struct pp_smu_funcs *pp_smu,
 704                 struct dccg *dccg)
 705 {
 706         struct dc_debug_options *debug = &ctx->dc->debug;
 707         struct dpm_clocks clock_table = { 0 };
 708         enum pp_smu_status status = 0;
 709         int is_green_sardine = 0;
 710         struct clk_log_info log_info = {0};
 711
 712         is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
 713
 714         clk_mgr->base.ctx = ctx;
 715         clk_mgr->base.funcs = &dcn21_funcs;
 716
 717         clk_mgr->pp_smu = pp_smu;
 718
 719         clk_mgr->dccg = dccg;
 720         clk_mgr->dfs_bypass_disp_clk = 0;
 721
 722         clk_mgr->dprefclk_ss_percentage = 0;
 723         clk_mgr->dprefclk_ss_divider = 1000;
 724         clk_mgr->ss_on_dprefclk = false;
 725         clk_mgr->dfs_ref_freq_khz = 48000;
 726
 727         clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
 728
 729         clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
 730
 731         /* SMU Version 55.51.0 and up no longer have an issue
 732          * that needs to limit minimum dispclk */
 733         if (clk_mgr->smu_ver >= SMU_VER_55_51_0)
 734                 debug->min_disp_clk_khz = 0;
 735
 736         /* TODO: Check we get what we expect during bringup */
 737         clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 738
 739         /* in case we don't get a value from the register, use default */
 740         if (clk_mgr->base.dentist_vco_freq_khz == 0)
 741                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 742
 743         if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
 744                 if (clk_mgr->periodic_retraining_disabled) {
 745                         rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
 746                 } else {
 747                         if (is_green_sardine)
 748                                 rn_bw_params.wm_table = lpddr4_wm_table_gs;
 749                         else
 750                                 rn_bw_params.wm_table = lpddr4_wm_table_rn;
 751                 }
 752         } else {
 753                 if (is_green_sardine)
 754                         rn_bw_params.wm_table = ddr4_wm_table_gs;
 755                 else {
 756                         if (ctx->dc->config.is_single_rank_dimm)
 757                                 rn_bw_params.wm_table = ddr4_1R_wm_table_rn;
 758                         else
 759                                 rn_bw_params.wm_table = ddr4_wm_table_rn;
 760                 }
 761         }
 762         /* Saved clocks configured at boot for debug purposes */
 763         rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
 764
 765         clk_mgr->base.dprefclk_khz = 600000;
 766         dce_clock_read_ss_info(clk_mgr);
 767
 768
 769         clk_mgr->base.bw_params = &rn_bw_params;
 770
 771         if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
 772                 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
 773
 774                 if (status == PP_SMU_RESULT_OK &&
 775                     ctx->dc_bios->integrated_info) {
 776                         rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
 777                         /* treat memory config as single channel if memory is asymmetrics. */
 778                         if (ctx->dc->config.is_asymmetric_memory)
 779                                 clk_mgr->base.bw_params->num_channels = 1;
 780                 }
 781         }
 782
 783         /* enable powerfeatures when displaycount goes to 0 */
 784         if (clk_mgr->smu_ver >= 0x00371500)
 785                 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
 786 }
 787