drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28
  29
  30 #include "dcn20/dcn20_clk_mgr.h"
  31 #include "rn_clk_mgr.h"
  32
  33
  34 #include "dce100/dce_clk_mgr.h"
  35 #include "rn_clk_mgr_vbios_smu.h"
  36 #include "reg_helper.h"
  37 #include "core_types.h"
  38 #include "dm_helpers.h"
  39
  40 #include "atomfirmware.h"
  41 #include "clk/clk_10_0_2_offset.h"
  42 #include "clk/clk_10_0_2_sh_mask.h"
  43 #include "renoir_ip_offset.h"
  44
  45
  46 /* Constants */
  47
  48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  49 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */
  50
  51 /* Macros */
  52
  53 #define REG(reg_name) \
  54         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  55
  56
  57 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  58 int rn_get_active_display_cnt_wa(
  59                 struct dc *dc,
  60                 struct dc_state *context)
  61 {
  62         int i, display_count;
  63         bool tmds_present = false;
  64
  65         display_count = 0;
  66         for (i = 0; i < context->stream_count; i++) {
  67                 const struct dc_stream_state *stream = context->streams[i];
  68
  69                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  70                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  71                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  72                         tmds_present = true;
  73         }
  74
  75         for (i = 0; i < dc->link_count; i++) {
  76                 const struct dc_link *link = dc->links[i];
  77
  78                 /*
  79                  * Only notify active stream or virtual stream.
  80                  * Need to notify virtual stream to work around
  81                  * headless case. HPD does not fire when system is in
  82                  * S0i2.
  83                  */
  84                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  85                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
  86                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
  87                         display_count++;
  88         }
  89
  90         /* WA for hang on HDMI after display off back back on*/
  91         if (display_count == 0 && tmds_present)
  92                 display_count = 1;
  93
  94         return display_count;
  95 }
  96
  97 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
  98 {
  99         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 100
 101         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 102         /* update power state */
 103         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 104 }
 105
 106 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 107                         struct dc_state *context,
 108                         bool safe_to_lower)
 109 {
 110         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 111         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 112         struct dc *dc = clk_mgr_base->ctx->dc;
 113         int display_count;
 114         bool update_dppclk = false;
 115         bool update_dispclk = false;
 116         bool dpp_clock_lowered = false;
 117
 118         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 119
 120         if (dc->work_arounds.skip_clock_update)
 121                 return;
 122
 123         /*
 124          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 125          * also if safe to lower is false, we just go in the higher state
 126          */
 127         if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {
 128                 /* check that we're not already in lower */
 129                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 130
 131                         display_count = rn_get_active_display_cnt_wa(dc, context);
 132                         /* if we can go lower, go lower */
 133                         if (display_count == 0) {
 134                                 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 135                                 /* update power state */
 136                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 137                         }
 138                 }
 139         } else {
 140                 /* check that we're not already in D0 */
 141                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 142                         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
 143                         /* update power state */
 144                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 145                 }
 146         }
 147
 148         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 149                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 150                 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 151         }
 152
 153         if (should_set_clock(safe_to_lower,
 154                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 155                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 156                 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 157         }
 158
 159         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 160         // Do not adjust dppclk if dppclk is 0 to avoid unexpected result
 161         if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
 162                 new_clocks->dppclk_khz = 100000;
 163
 164         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 165                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 166                         dpp_clock_lowered = true;
 167                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 168                 update_dppclk = true;
 169         }
 170
 171         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 172                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 173                 clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 174
 175                 update_dispclk = true;
 176         }
 177
 178         if (dpp_clock_lowered) {
 179                 // increase per DPP DTO before lowering global dppclk
 180                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 181                 clk_mgr_base->clks.actual_dppclk_khz =
 182                                 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 183
 184         } else {
 185                 // increase global DPPCLK before lowering per DPP DTO
 186                 if (update_dppclk || update_dispclk)
 187                         clk_mgr_base->clks.actual_dppclk_khz =
 188                                         rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 189                 // always update dtos unless clock is lowered and not safe to lower
 190                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 191                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 192         }
 193
 194         if (update_dispclk &&
 195                         dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 196                 /*update dmcu for wait_loop count*/
 197                 dmcu->funcs->set_psr_wait_loop(dmcu,
 198                         clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 199         }
 200 }
 201
 202
 203 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 204 {
 205         /* get FbMult value */
 206         struct fixed31_32 pll_req;
 207         unsigned int fbmult_frac_val = 0;
 208         unsigned int fbmult_int_val = 0;
 209
 210
 211         /*
 212          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 213          * to leverage the fix point operations available in driver
 214          */
 215
 216         REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 217         REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 218
 219         pll_req = dc_fixpt_from_int(fbmult_int_val);
 220
 221         /*
 222          * since fractional part is only 16 bit in register definition but is 32 bit
 223          * in our fix point definiton, need to shift left by 16 to obtain correct value
 224          */
 225         pll_req.value |= fbmult_frac_val << 16;
 226
 227         /* multiply by REFCLK period */
 228         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 229
 230         /* integer part is now VCO frequency in kHz */
 231         return dc_fixpt_floor(pll_req);
 232 }
 233
 234 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 235 {
 236         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 237
 238         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
 239         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
 240
 241         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);      //dcf deep sleep divider
 242         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
 243
 244         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
 245         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
 246
 247         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
 248         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
 249
 250         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
 251         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
 252 }
 253
 254 /* This function collect raw clk register values */
 255 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 256                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 257 {
 258         struct rn_clk_internal internal = {0};
 259         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 260         unsigned int chars_printed = 0;
 261         unsigned int remaining_buffer = log_info->bufSize;
 262
 263         rn_dump_clk_registers_internal(&internal, clk_mgr_base);
 264
 265         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 266         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 267         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 268         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 269         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 270         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 271
 272         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 273         if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
 274                 regs_and_bypass->dppclk_bypass = 0;
 275         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 276         if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
 277                 regs_and_bypass->dcfclk_bypass = 0;
 278         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 279         if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
 280                 regs_and_bypass->dispclk_bypass = 0;
 281         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 282         if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
 283                 regs_and_bypass->dprefclk_bypass = 0;
 284
 285         if (log_info->enabled) {
 286                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 287                 remaining_buffer -= chars_printed;
 288                 *log_info->sum_chars_printed += chars_printed;
 289                 log_info->pBuf += chars_printed;
 290
 291                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 292                         regs_and_bypass->dcfclk,
 293                         regs_and_bypass->dcf_deep_sleep_divider,
 294                         regs_and_bypass->dcf_deep_sleep_allow,
 295                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 296                 remaining_buffer -= chars_printed;
 297                 *log_info->sum_chars_printed += chars_printed;
 298                 log_info->pBuf += chars_printed;
 299
 300                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 301                         regs_and_bypass->dprefclk,
 302                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 303                 remaining_buffer -= chars_printed;
 304                 *log_info->sum_chars_printed += chars_printed;
 305                 log_info->pBuf += chars_printed;
 306
 307                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 308                         regs_and_bypass->dispclk,
 309                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 310                 remaining_buffer -= chars_printed;
 311                 *log_info->sum_chars_printed += chars_printed;
 312                 log_info->pBuf += chars_printed;
 313
 314                 //split
 315                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 316                 remaining_buffer -= chars_printed;
 317                 *log_info->sum_chars_printed += chars_printed;
 318                 log_info->pBuf += chars_printed;
 319
 320                 // REGISTER VALUES
 321                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 322                 remaining_buffer -= chars_printed;
 323                 *log_info->sum_chars_printed += chars_printed;
 324                 log_info->pBuf += chars_printed;
 325
 326                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 327                                 internal.CLK1_CLK3_CURRENT_CNT);
 328                 remaining_buffer -= chars_printed;
 329                 *log_info->sum_chars_printed += chars_printed;
 330                 log_info->pBuf += chars_printed;
 331
 332                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 333                                         internal.CLK1_CLK3_DS_CNTL);
 334                 remaining_buffer -= chars_printed;
 335                 *log_info->sum_chars_printed += chars_printed;
 336                 log_info->pBuf += chars_printed;
 337
 338                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 339                                         internal.CLK1_CLK3_ALLOW_DS);
 340                 remaining_buffer -= chars_printed;
 341                 *log_info->sum_chars_printed += chars_printed;
 342                 log_info->pBuf += chars_printed;
 343
 344                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 345                                         internal.CLK1_CLK2_CURRENT_CNT);
 346                 remaining_buffer -= chars_printed;
 347                 *log_info->sum_chars_printed += chars_printed;
 348                 log_info->pBuf += chars_printed;
 349
 350                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 351                                         internal.CLK1_CLK0_CURRENT_CNT);
 352                 remaining_buffer -= chars_printed;
 353                 *log_info->sum_chars_printed += chars_printed;
 354                 log_info->pBuf += chars_printed;
 355
 356                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 357                                         internal.CLK1_CLK1_CURRENT_CNT);
 358                 remaining_buffer -= chars_printed;
 359                 *log_info->sum_chars_printed += chars_printed;
 360                 log_info->pBuf += chars_printed;
 361
 362                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 363                                         internal.CLK1_CLK3_BYPASS_CNTL);
 364                 remaining_buffer -= chars_printed;
 365                 *log_info->sum_chars_printed += chars_printed;
 366                 log_info->pBuf += chars_printed;
 367
 368                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 369                                         internal.CLK1_CLK2_BYPASS_CNTL);
 370                 remaining_buffer -= chars_printed;
 371                 *log_info->sum_chars_printed += chars_printed;
 372                 log_info->pBuf += chars_printed;
 373
 374                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 375                                         internal.CLK1_CLK0_BYPASS_CNTL);
 376                 remaining_buffer -= chars_printed;
 377                 *log_info->sum_chars_printed += chars_printed;
 378                 log_info->pBuf += chars_printed;
 379
 380                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 381                                         internal.CLK1_CLK1_BYPASS_CNTL);
 382                 remaining_buffer -= chars_printed;
 383                 *log_info->sum_chars_printed += chars_printed;
 384                 log_info->pBuf += chars_printed;
 385         }
 386 }
 387
 388 /* This function produce translated logical clk state values*/
 389 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 390 {
 391         struct clk_state_registers_and_bypass sb = { 0 };
 392         struct clk_log_info log_info = { 0 };
 393
 394         rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 395
 396         s->dprefclk_khz = sb.dprefclk * 1000;
 397 }
 398
 399 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 400 {
 401         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 402
 403         rn_vbios_smu_enable_pme_wa(clk_mgr);
 404 }
 405
 406 void rn_init_clocks(struct clk_mgr *clk_mgr)
 407 {
 408         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 409         // Assumption is that boot state always supports pstate
 410         clk_mgr->clks.p_state_change_support = true;
 411         clk_mgr->clks.prev_p_state_change_support = true;
 412         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 413 }
 414
 415 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 416 {
 417         int i, num_valid_sets;
 418
 419         num_valid_sets = 0;
 420
 421         for (i = 0; i < WM_SET_COUNT; i++) {
 422                 /* skip empty entries, the smu array has no holes*/
 423                 if (!bw_params->wm_table.entries[i].valid)
 424                         continue;
 425
 426                 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
 427                 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
 428                 /* We will not select WM based on fclk, so leave it as unconstrained */
 429                 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 430                 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 431                 /* dcfclk wil be used to select WM*/
 432
 433                 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
 434                         if (i == 0)
 435                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
 436                         else {
 437                                 /* add 1 to make it non-overlapping with next lvl */
 438                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 439                         }
 440                         ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
 441
 442                 } else {
 443                         /* unconstrained for memory retraining */
 444                         ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 445                         ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 446
 447                         /* Modify previous watermark range to cover up to max */
 448                         ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 449                 }
 450                 num_valid_sets++;
 451         }
 452
 453         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 454         ranges->num_reader_wm_sets = num_valid_sets;
 455
 456         /* modify the min and max to make sure we cover the whole range*/
 457         ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 458         ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 459         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 460         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 461
 462         /* This is for writeback only, does not matter currently as no writeback support*/
 463         ranges->num_writer_wm_sets = 1;
 464         ranges->writer_wm_sets[0].wm_inst = WM_A;
 465         ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 466         ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 467         ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 468         ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 469
 470 }
 471
 472 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 473 {
 474         struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
 475         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 476         struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
 477
 478         if (!debug->disable_pplib_wm_range) {
 479                 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
 480
 481                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 482                 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
 483                         pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);
 484         }
 485
 486 }
 487
 488 static bool rn_are_clock_states_equal(struct dc_clocks *a,
 489                 struct dc_clocks *b)
 490 {
 491         if (a->dispclk_khz != b->dispclk_khz)
 492                 return false;
 493         else if (a->dppclk_khz != b->dppclk_khz)
 494                 return false;
 495         else if (a->dcfclk_khz != b->dcfclk_khz)
 496                 return false;
 497         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 498                 return false;
 499
 500         return true;
 501 }
 502
 503
 504 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
 505 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
 506 {
 507         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 508         unsigned int i, max_phyclk_req = 0;
 509
 510         clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 511
 512         for (i = 0; i < MAX_PIPES * 2; i++) {
 513                 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
 514                         max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
 515         }
 516
 517         if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
 518                 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
 519                 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
 520         }
 521 }
 522
 523 static struct clk_mgr_funcs dcn21_funcs = {
 524         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 525         .update_clocks = rn_update_clocks,
 526         .init_clocks = rn_init_clocks,
 527         .enable_pme_wa = rn_enable_pme_wa,
 528         .are_clock_states_equal = rn_are_clock_states_equal,
 529         .set_low_power_state = rn_set_low_power_state,
 530         .notify_wm_ranges = rn_notify_wm_ranges,
 531         .notify_link_rate_change = rn_notify_link_rate_change,
 532 };
 533
 534 static struct clk_bw_params rn_bw_params = {
 535         .vram_type = Ddr4MemType,
 536         .num_channels = 1,
 537         .clk_table = {
 538                 .entries = {
 539                         {
 540                                 .voltage = 0,
 541                                 .dcfclk_mhz = 400,
 542                                 .fclk_mhz = 400,
 543                                 .memclk_mhz = 800,
 544                                 .socclk_mhz = 0,
 545                         },
 546                         {
 547                                 .voltage = 0,
 548                                 .dcfclk_mhz = 483,
 549                                 .fclk_mhz = 800,
 550                                 .memclk_mhz = 1600,
 551                                 .socclk_mhz = 0,
 552                         },
 553                         {
 554                                 .voltage = 0,
 555                                 .dcfclk_mhz = 602,
 556                                 .fclk_mhz = 1067,
 557                                 .memclk_mhz = 1067,
 558                                 .socclk_mhz = 0,
 559                         },
 560                         {
 561                                 .voltage = 0,
 562                                 .dcfclk_mhz = 738,
 563                                 .fclk_mhz = 1333,
 564                                 .memclk_mhz = 1600,
 565                                 .socclk_mhz = 0,
 566                         },
 567                 },
 568
 569                 .num_entries = 4,
 570         },
 571
 572 };
 573
 574 static struct wm_table ddr4_wm_table = {
 575         .entries = {
 576                 {
 577                         .wm_inst = WM_A,
 578                         .wm_type = WM_TYPE_PSTATE_CHG,
 579                         .pstate_latency_us = 11.72,
 580                         .sr_exit_time_us = 6.09,
 581                         .sr_enter_plus_exit_time_us = 7.14,
 582                         .valid = true,
 583                 },
 584                 {
 585                         .wm_inst = WM_B,
 586                         .wm_type = WM_TYPE_PSTATE_CHG,
 587                         .pstate_latency_us = 11.72,
 588                         .sr_exit_time_us = 10.12,
 589                         .sr_enter_plus_exit_time_us = 11.48,
 590                         .valid = true,
 591                 },
 592                 {
 593                         .wm_inst = WM_C,
 594                         .wm_type = WM_TYPE_PSTATE_CHG,
 595                         .pstate_latency_us = 11.72,
 596                         .sr_exit_time_us = 10.12,
 597                         .sr_enter_plus_exit_time_us = 11.48,
 598                         .valid = true,
 599                 },
 600                 {
 601                         .wm_inst = WM_D,
 602                         .wm_type = WM_TYPE_PSTATE_CHG,
 603                         .pstate_latency_us = 11.72,
 604                         .sr_exit_time_us = 10.12,
 605                         .sr_enter_plus_exit_time_us = 11.48,
 606                         .valid = true,
 607                 },
 608         }
 609 };
 610
 611 static struct wm_table lpddr4_wm_table = {
 612         .entries = {
 613                 {
 614                         .wm_inst = WM_A,
 615                         .wm_type = WM_TYPE_PSTATE_CHG,
 616                         .pstate_latency_us = 11.65333,
 617                         .sr_exit_time_us = 5.32,
 618                         .sr_enter_plus_exit_time_us = 6.38,
 619                         .valid = true,
 620                 },
 621                 {
 622                         .wm_inst = WM_B,
 623                         .wm_type = WM_TYPE_PSTATE_CHG,
 624                         .pstate_latency_us = 11.65333,
 625                         .sr_exit_time_us = 9.82,
 626                         .sr_enter_plus_exit_time_us = 11.196,
 627                         .valid = true,
 628                 },
 629                 {
 630                         .wm_inst = WM_C,
 631                         .wm_type = WM_TYPE_PSTATE_CHG,
 632                         .pstate_latency_us = 11.65333,
 633                         .sr_exit_time_us = 9.89,
 634                         .sr_enter_plus_exit_time_us = 11.24,
 635                         .valid = true,
 636                 },
 637                 {
 638                         .wm_inst = WM_D,
 639                         .wm_type = WM_TYPE_PSTATE_CHG,
 640                         .pstate_latency_us = 11.65333,
 641                         .sr_exit_time_us = 9.748,
 642                         .sr_enter_plus_exit_time_us = 11.102,
 643                         .valid = true,
 644                 },
 645         }
 646 };
 647
 648 static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
 649         .entries = {
 650                 {
 651                         .wm_inst = WM_A,
 652                         .wm_type = WM_TYPE_PSTATE_CHG,
 653                         .pstate_latency_us = 11.65333,
 654                         .sr_exit_time_us = 8.32,
 655                         .sr_enter_plus_exit_time_us = 9.38,
 656                         .valid = true,
 657                 },
 658                 {
 659                         .wm_inst = WM_B,
 660                         .wm_type = WM_TYPE_PSTATE_CHG,
 661                         .pstate_latency_us = 11.65333,
 662                         .sr_exit_time_us = 9.82,
 663                         .sr_enter_plus_exit_time_us = 11.196,
 664                         .valid = true,
 665                 },
 666                 {
 667                         .wm_inst = WM_C,
 668                         .wm_type = WM_TYPE_PSTATE_CHG,
 669                         .pstate_latency_us = 11.65333,
 670                         .sr_exit_time_us = 9.89,
 671                         .sr_enter_plus_exit_time_us = 11.24,
 672                         .valid = true,
 673                 },
 674                 {
 675                         .wm_inst = WM_D,
 676                         .wm_type = WM_TYPE_PSTATE_CHG,
 677                         .pstate_latency_us = 11.65333,
 678                         .sr_exit_time_us = 9.748,
 679                         .sr_enter_plus_exit_time_us = 11.102,
 680                         .valid = true,
 681                 },
 682         }
 683 };
 684
 685 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 686 {
 687         int i;
 688
 689         for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
 690                 if (clock_table->DcfClocks[i].Vol == voltage)
 691                         return clock_table->DcfClocks[i].Freq;
 692         }
 693
 694         ASSERT(0);
 695         return 0;
 696 }
 697
 698 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 699 {
 700         int i, j = 0;
 701
 702         j = -1;
 703
 704         ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 705
 706         /* Find lowest DPM, FCLK is filled in reverse order*/
 707
 708         for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 709                 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) {
 710                         j = i;
 711                         break;
 712                 }
 713         }
 714
 715         if (j == -1) {
 716                 /* clock table is all 0s, just use our own hardcode */
 717                 ASSERT(0);
 718                 return;
 719         }
 720
 721         bw_params->clk_table.num_entries = j + 1;
 722
 723         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 724                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
 725                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
 726                 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
 727                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
 728         }
 729
 730         bw_params->vram_type = bios_info->memory_type;
 731         bw_params->num_channels = bios_info->ma_channel_number;
 732
 733         for (i = 0; i < WM_SET_COUNT; i++) {
 734                 bw_params->wm_table.entries[i].wm_inst = i;
 735
 736                 if (i >= bw_params->clk_table.num_entries) {
 737                         bw_params->wm_table.entries[i].valid = false;
 738                         continue;
 739                 }
 740
 741                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 742                 bw_params->wm_table.entries[i].valid = true;
 743         }
 744
 745         if (bw_params->vram_type == LpDdr4MemType) {
 746                 /*
 747                  * WM set D will be re-purposed for memory retraining
 748                  */
 749                 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
 750                 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
 751                 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
 752                 bw_params->wm_table.entries[WM_D].valid = true;
 753         }
 754
 755 }
 756
 757 void rn_clk_mgr_construct(
 758                 struct dc_context *ctx,
 759                 struct clk_mgr_internal *clk_mgr,
 760                 struct pp_smu_funcs *pp_smu,
 761                 struct dccg *dccg)
 762 {
 763         struct dc_debug_options *debug = &ctx->dc->debug;
 764         struct dpm_clocks clock_table = { 0 };
 765         enum pp_smu_status status = 0;
 766
 767         clk_mgr->base.ctx = ctx;
 768         clk_mgr->base.funcs = &dcn21_funcs;
 769
 770         clk_mgr->pp_smu = pp_smu;
 771
 772         clk_mgr->dccg = dccg;
 773         clk_mgr->dfs_bypass_disp_clk = 0;
 774
 775         clk_mgr->dprefclk_ss_percentage = 0;
 776         clk_mgr->dprefclk_ss_divider = 1000;
 777         clk_mgr->ss_on_dprefclk = false;
 778         clk_mgr->dfs_ref_freq_khz = 48000;
 779
 780         clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
 781
 782         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 783                 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
 784                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 785         } else {
 786                 struct clk_log_info log_info = {0};
 787
 788                 clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
 789
 790                 /* SMU Version 55.51.0 and up no longer have an issue
 791                  * that needs to limit minimum dispclk */
 792                 if (clk_mgr->smu_ver >= SMU_VER_55_51_0)
 793                         debug->min_disp_clk_khz = 0;
 794
 795                 /* TODO: Check we get what we expect during bringup */
 796                 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 797
 798                 /* in case we don't get a value from the register, use default */
 799                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 800                         clk_mgr->base.dentist_vco_freq_khz = 3600000;
 801
 802                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
 803                         if (clk_mgr->periodic_retraining_disabled) {
 804                                 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
 805                         } else {
 806                                 rn_bw_params.wm_table = lpddr4_wm_table;
 807                         }
 808                 } else {
 809                         rn_bw_params.wm_table = ddr4_wm_table;
 810                 }
 811                 /* Saved clocks configured at boot for debug purposes */
 812                 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
 813         }
 814
 815         clk_mgr->base.dprefclk_khz = 600000;
 816         dce_clock_read_ss_info(clk_mgr);
 817
 818
 819         clk_mgr->base.bw_params = &rn_bw_params;
 820
 821         if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
 822                 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
 823
 824                 if (status == PP_SMU_RESULT_OK &&
 825                     ctx->dc_bios && ctx->dc_bios->integrated_info) {
 826                         rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
 827                 }
 828         }
 829
 830         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
 831                 /* enable powerfeatures when displaycount goes to 0 */
 832                 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
 833         }
 834 }
 835