2 * Copyright 2012-16 Advanced Micro Devices, Inc.
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26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
31 #include "dce110_clk_mgr.h"
32 #include "../clk_mgr/dce100/dce_clk_mgr.h"
34 /* set register offset */
36 .reg_name = mm ## reg_name
38 /* set register offset with instance */
39 #define SRI(reg_name, block, id)\
40 .reg_name = mm ## block ## id ## _ ## reg_name
42 static const struct clk_mgr_registers disp_clk_regs = {
43 CLK_COMMON_REG_LIST_DCE_BASE()
46 static const struct clk_mgr_shift disp_clk_shift = {
47 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
50 static const struct clk_mgr_mask disp_clk_mask = {
51 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
54 static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
55 /*ClocksStateInvalid - should not be used*/
56 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
57 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
58 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
60 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
61 /*ClocksStateNominal*/
62 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
63 /*ClocksStatePerformance*/
64 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
66 static int determine_sclk_from_bounding_box(
73 * Some asics do not give us sclk levels, so we just report the actual
76 if (dc->sclk_lvls.num_levels == 0)
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
80 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
81 return dc->sclk_lvls.clocks_in_khz[i];
84 * even maximum level could not satisfy requirement, this
85 * is unexpected at this stage, should have been caught at
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
92 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
95 uint32_t min_vertical_blank_time = -1;
97 for (j = 0; j < context->stream_count; j++) {
98 struct dc_stream_state *stream = context->streams[j];
99 uint32_t vertical_blank_in_pixels = 0;
100 uint32_t vertical_blank_time = 0;
102 vertical_blank_in_pixels = stream->timing.h_total *
103 (stream->timing.v_total
104 - stream->timing.v_addressable);
106 vertical_blank_time = vertical_blank_in_pixels
107 * 10000 / stream->timing.pix_clk_100hz;
109 if (min_vertical_blank_time > vertical_blank_time)
110 min_vertical_blank_time = vertical_blank_time;
113 return min_vertical_blank_time;
116 void dce110_fill_display_configs(
117 const struct dc_state *context,
118 struct dm_pp_display_configuration *pp_display_cfg)
123 for (j = 0; j < context->stream_count; j++) {
126 const struct dc_stream_state *stream = context->streams[j];
127 struct dm_pp_single_disp_config *cfg =
128 &pp_display_cfg->disp_configs[num_cfgs];
129 const struct pipe_ctx *pipe_ctx = NULL;
131 for (k = 0; k < MAX_PIPES; k++)
132 if (stream == context->res_ctx.pipe_ctx[k].stream) {
133 pipe_ctx = &context->res_ctx.pipe_ctx[k];
137 ASSERT(pipe_ctx != NULL);
139 /* only notify active stream */
140 if (stream->dpms_off)
144 cfg->signal = pipe_ctx->stream->signal;
145 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
146 cfg->src_height = stream->src.height;
147 cfg->src_width = stream->src.width;
148 cfg->ddi_channel_mapping =
149 stream->link->ddi_channel_mapping.raw;
151 stream->link->link_enc->transmitter;
152 cfg->link_settings.lane_count =
153 stream->link->cur_link_settings.lane_count;
154 cfg->link_settings.link_rate =
155 stream->link->cur_link_settings.link_rate;
156 cfg->link_settings.link_spread =
157 stream->link->cur_link_settings.link_spread;
158 cfg->sym_clock = stream->phy_pix_clk;
160 cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
161 cfg->v_refresh /= stream->timing.h_total;
162 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
163 / stream->timing.v_total;
166 pp_display_cfg->display_count = num_cfgs;
169 void dce11_pplib_apply_display_requirements(
171 struct dc_state *context)
173 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
175 pp_display_cfg->all_displays_in_sync =
176 context->bw_ctx.bw.dce.all_displays_in_sync;
177 pp_display_cfg->nb_pstate_switch_disable =
178 context->bw_ctx.bw.dce.nbp_state_change_enable == false;
179 pp_display_cfg->cpu_cc6_disable =
180 context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
181 pp_display_cfg->cpu_pstate_disable =
182 context->bw_ctx.bw.dce.cpup_state_change_enable == false;
183 pp_display_cfg->cpu_pstate_separation_time =
184 context->bw_ctx.bw.dce.blackout_recovery_time_us;
186 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
187 / MEMORY_TYPE_MULTIPLIER_CZ;
189 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
191 context->bw_ctx.bw.dce.sclk_khz);
194 * As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
195 * This is not required for less than 5 displays,
196 * thus don't request decfclk in dc to avoid impact
200 pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
201 pp_display_cfg->min_engine_clock_khz : 0;
203 pp_display_cfg->min_engine_clock_deep_sleep_khz
204 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
206 pp_display_cfg->avail_mclk_switch_time_us =
207 dce110_get_min_vblank_time_us(context);
209 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
211 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
213 dce110_fill_display_configs(context, pp_display_cfg);
215 /* TODO: is this still applicable?*/
216 if (pp_display_cfg->display_count == 1) {
217 const struct dc_crtc_timing *timing =
218 &context->streams[0]->timing;
220 pp_display_cfg->crtc_index =
221 pp_display_cfg->disp_configs[0].pipe_idx;
222 pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
225 if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
226 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
229 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base,
230 struct dc_state *context,
233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
234 struct dm_pp_power_level_change_request level_change_req;
235 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
237 /*TODO: W/A for dal3 linux, investigate why this works */
238 if (!clk_mgr_dce->dfs_bypass_active)
239 patched_disp_clk = patched_disp_clk * 115 / 100;
241 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
242 /* get max clock state from PPLIB */
243 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
244 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
245 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
246 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
249 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
250 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
251 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
253 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
256 static struct clk_mgr_funcs dce110_funcs = {
257 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
258 .update_clocks = dce11_update_clocks
261 void dce110_clk_mgr_construct(
262 struct dc_context *ctx,
263 struct clk_mgr_internal *clk_mgr)
265 memcpy(clk_mgr->max_clks_by_state,
266 dce110_max_clks_by_state,
267 sizeof(dce110_max_clks_by_state));
269 dce_clk_mgr_construct(ctx, clk_mgr);
271 clk_mgr->regs = &disp_clk_regs;
272 clk_mgr->clk_mgr_shift = &disp_clk_shift;
273 clk_mgr->clk_mgr_mask = &disp_clk_mask;
274 clk_mgr->base.funcs = &dce110_funcs;