drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dal_asic_id.h"
  29 #include "dc_types.h"
  30 #include "dccg.h"
  31 #include "clk_mgr_internal.h"
  32
  33 #include "dce100/dce_clk_mgr.h"
  34 #include "dce110/dce110_clk_mgr.h"
  35 #include "dce112/dce112_clk_mgr.h"
  36 #include "dce120/dce120_clk_mgr.h"
  37 #include "dce60/dce60_clk_mgr.h"
  38 #include "dcn10/rv1_clk_mgr.h"
  39 #include "dcn10/rv2_clk_mgr.h"
  40 #include "dcn20/dcn20_clk_mgr.h"
  41 #include "dcn21/rn_clk_mgr.h"
  42 #include "dcn201/dcn201_clk_mgr.h"
  43 #include "dcn30/dcn30_clk_mgr.h"
  44 #include "dcn301/vg_clk_mgr.h"
  45 #include "dcn31/dcn31_clk_mgr.h"
  46
  47
  48 int clk_mgr_helper_get_active_display_cnt(
  49                 struct dc *dc,
  50                 struct dc_state *context)
  51 {
  52         int i, display_count;
  53
  54         display_count = 0;
  55         for (i = 0; i < context->stream_count; i++) {
  56                 const struct dc_stream_state *stream = context->streams[i];
  57
  58                 /*
  59                  * Only notify active stream or virtual stream.
  60                  * Need to notify virtual stream to work around
  61                  * headless case. HPD does not fire when system is in
  62                  * S0i2.
  63                  */
  64                 if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
  65                         display_count++;
  66         }
  67
  68         return display_count;
  69 }
  70
  71 int clk_mgr_helper_get_active_plane_cnt(
  72                 struct dc *dc,
  73                 struct dc_state *context)
  74 {
  75         int i, total_plane_count;
  76
  77         total_plane_count = 0;
  78         for (i = 0; i < context->stream_count; i++) {
  79                 const struct dc_stream_status stream_status = context->stream_status[i];
  80
  81                 /*
  82                  * Sum up plane_count for all streams ( active and virtual ).
  83                  */
  84                 total_plane_count += stream_status.plane_count;
  85         }
  86
  87         return total_plane_count;
  88 }
  89
  90 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
  91 {
  92         struct dc_link *edp_links[MAX_NUM_EDP];
  93         struct dc_link *edp_link = NULL;
  94         int edp_num;
  95         unsigned int panel_inst;
  96
  97         get_edp_links(dc, edp_links, &edp_num);
  98         if (dc->hwss.exit_optimized_pwr_state)
  99                 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
 100
 101         if (edp_num) {
 102                 for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
 103                         bool allow_active = false;
 104
 105                         edp_link = edp_links[panel_inst];
 106                         if (!edp_link->psr_settings.psr_feature_enabled)
 107                                 continue;
 108                         clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
 109                         dc_link_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);
 110                 }
 111         }
 112
 113 }
 114
 115 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
 116 {
 117         struct dc_link *edp_links[MAX_NUM_EDP];
 118         struct dc_link *edp_link = NULL;
 119         int edp_num;
 120         unsigned int panel_inst;
 121
 122         get_edp_links(dc, edp_links, &edp_num);
 123         if (edp_num) {
 124                 for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
 125                         edp_link = edp_links[panel_inst];
 126                         if (!edp_link->psr_settings.psr_feature_enabled)
 127                                 continue;
 128                         dc_link_set_psr_allow_active(edp_link,
 129                                         &clk_mgr->psr_allow_active_cache, false, false, NULL);
 130                 }
 131         }
 132
 133         if (dc->hwss.optimize_pwr_state)
 134                 dc->hwss.optimize_pwr_state(dc, dc->current_state);
 135
 136 }
 137
 138 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
 139 {
 140         struct hw_asic_id asic_id = ctx->asic_id;
 141
 142         switch (asic_id.chip_family) {
 143 #if defined(CONFIG_DRM_AMD_DC_SI)
 144         case FAMILY_SI: {
 145                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 146
 147                 if (clk_mgr == NULL) {
 148                         BREAK_TO_DEBUGGER();
 149                         return NULL;
 150                 }
 151                 dce60_clk_mgr_construct(ctx, clk_mgr);
 152                 dce_clk_mgr_construct(ctx, clk_mgr);
 153                 return &clk_mgr->base;
 154         }
 155 #endif
 156         case FAMILY_CI:
 157         case FAMILY_KV: {
 158                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 159
 160                 if (clk_mgr == NULL) {
 161                         BREAK_TO_DEBUGGER();
 162                         return NULL;
 163                 }
 164                 dce_clk_mgr_construct(ctx, clk_mgr);
 165                 return &clk_mgr->base;
 166         }
 167         case FAMILY_CZ: {
 168                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 169
 170                 if (clk_mgr == NULL) {
 171                         BREAK_TO_DEBUGGER();
 172                         return NULL;
 173                 }
 174                 dce110_clk_mgr_construct(ctx, clk_mgr);
 175                 return &clk_mgr->base;
 176         }
 177         case FAMILY_VI: {
 178                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 179
 180                 if (clk_mgr == NULL) {
 181                         BREAK_TO_DEBUGGER();
 182                         return NULL;
 183                 }
 184                 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
 185                                 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
 186                         dce_clk_mgr_construct(ctx, clk_mgr);
 187                         return &clk_mgr->base;
 188                 }
 189                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
 190                                 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
 191                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
 192                         dce112_clk_mgr_construct(ctx, clk_mgr);
 193                         return &clk_mgr->base;
 194                 }
 195                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
 196                         dce112_clk_mgr_construct(ctx, clk_mgr);
 197                         return &clk_mgr->base;
 198                 }
 199                 return &clk_mgr->base;
 200         }
 201         case FAMILY_AI: {
 202                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 203
 204                 if (clk_mgr == NULL) {
 205                         BREAK_TO_DEBUGGER();
 206                         return NULL;
 207                 }
 208                 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
 209                         dce121_clk_mgr_construct(ctx, clk_mgr);
 210                 else
 211                         dce120_clk_mgr_construct(ctx, clk_mgr);
 212                 return &clk_mgr->base;
 213         }
 214 #if defined(CONFIG_DRM_AMD_DC_DCN)
 215         case FAMILY_RV: {
 216                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 217
 218                 if (clk_mgr == NULL) {
 219                         BREAK_TO_DEBUGGER();
 220                         return NULL;
 221                 }
 222
 223                 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
 224                         rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 225                         return &clk_mgr->base;
 226                 }
 227
 228                 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
 229                         rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 230                         return &clk_mgr->base;
 231                 }
 232                 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
 233                         rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 234                         return &clk_mgr->base;
 235                 }
 236                 if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
 237                                 ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
 238                         rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 239                         return &clk_mgr->base;
 240                 }
 241                 return &clk_mgr->base;
 242         }
 243         case FAMILY_NV: {
 244                 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 245
 246                 if (clk_mgr == NULL) {
 247                         BREAK_TO_DEBUGGER();
 248                         return NULL;
 249                 }
 250                 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
 251                         dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 252                         return &clk_mgr->base;
 253                 }
 254                 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {
 255                         dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 256                         return &clk_mgr->base;
 257                 }
 258                 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
 259                         dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 260                         return &clk_mgr->base;
 261                 }
 262                 if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
 263                         dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 264                         return &clk_mgr->base;
 265                 }
 266                 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 267                 return &clk_mgr->base;
 268         }
 269         case FAMILY_VGH:
 270                 if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev)) {
 271                         struct clk_mgr_vgh *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 272
 273                         if (clk_mgr == NULL) {
 274                                 BREAK_TO_DEBUGGER();
 275                                 return NULL;
 276                         }
 277                         vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 278                         return &clk_mgr->base.base;
 279                 }
 280                 break;
 281         case FAMILY_YELLOW_CARP: {
 282                 struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
 283
 284                 if (clk_mgr == NULL) {
 285                         BREAK_TO_DEBUGGER();
 286                         return NULL;
 287                 }
 288
 289                 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 290                 return &clk_mgr->base.base;
 291         }
 292 #endif
 293
 294         default:
 295                 ASSERT(0); /* Unknown Asic */
 296                 break;
 297         }
 298
 299         return NULL;
 300 }
 301
 302 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 303 {
 304         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 305
 306 #ifdef CONFIG_DRM_AMD_DC_DCN
 307         switch (clk_mgr_base->ctx->asic_id.chip_family) {
 308         case FAMILY_NV:
 309                 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 310                         dcn3_clk_mgr_destroy(clk_mgr);
 311                 }
 312                 if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 313                         dcn3_clk_mgr_destroy(clk_mgr);
 314                 }
 315                 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 316                         dcn3_clk_mgr_destroy(clk_mgr);
 317                 }
 318                 break;
 319
 320         case FAMILY_VGH:
 321                 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
 322                         vg_clk_mgr_destroy(clk_mgr);
 323                 break;
 324
 325         case FAMILY_YELLOW_CARP:
 326                         dcn31_clk_mgr_destroy(clk_mgr);
 327                 break;
 328
 329         default:
 330                 break;
 331         }
 332 #endif
 333
 334         kfree(clk_mgr);
 335 }
 336