drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28 #include "dcn_calcs.h"
  29 #include "dcn_calc_auto.h"
  30 #include "dal_asic_id.h"
  31 #include "resource.h"
  32 #include "dcn10/dcn10_resource.h"
  33 #include "dcn10/dcn10_hubbub.h"
  34 #include "dml/dml1_display_rq_dlg_calc.h"
  35
  36 #include "dcn_calc_math.h"
  37
  38 #define DC_LOGGER \
  39         dc->ctx->logger
  40
  41 #define WM_SET_COUNT 4
  42 #define WM_A 0
  43 #define WM_B 1
  44 #define WM_C 2
  45 #define WM_D 3
  46
  47 /*
  48  * NOTE:
  49  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  50  *
  51  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  52  * ways. Unless there is something clearly wrong with it the code should
  53  * remain as-is as it provides us with a guarantee from HW that it is correct.
  54  */
  55
  56 /* Defaults from spreadsheet rev#247.
  57  * RV2 delta: dram_clock_change_latency, max_num_dpp
  58  */
  59 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
  60                 /* latencies */
  61                 .sr_exit_time = 17, /*us*/
  62                 .sr_enter_plus_exit_time = 19, /*us*/
  63                 .urgent_latency = 4, /*us*/
  64                 .dram_clock_change_latency = 17, /*us*/
  65                 .write_back_latency = 12, /*us*/
  66                 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
  67
  68                 /* below default clocks derived from STA target base on
  69                  * slow-slow corner + 10% margin with voltages aligned to FCLK.
  70                  *
  71                  * Use these value if fused value doesn't make sense as earlier
  72                  * part don't have correct value fused */
  73                 /* default DCF CLK DPM on RV*/
  74                 .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
  75                 .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
  76                 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
  77                 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
  78
  79                 /* default DISP CLK voltage state on RV */
  80                 .max_dispclk_vmax0p9 = 1108,    /* MHz, = 3600/3.25 */
  81                 .max_dispclk_vnom0p8 = 1029,    /* MHz, = 3600/3.5 */
  82                 .max_dispclk_vmid0p72 = 960,    /* MHz, = 3600/3.75 */
  83                 .max_dispclk_vmin0p65 = 626,    /* MHz, = 3600/5.75 */
  84
  85                 /* default DPP CLK voltage state on RV */
  86                 .max_dppclk_vmax0p9 = 720,      /* MHz, = 3600/5 */
  87                 .max_dppclk_vnom0p8 = 686,      /* MHz, = 3600/5.25 */
  88                 .max_dppclk_vmid0p72 = 626,     /* MHz, = 3600/5.75 */
  89                 .max_dppclk_vmin0p65 = 400,     /* MHz, = 3600/9 */
  90
  91                 /* default PHY CLK voltage state on RV */
  92                 .phyclkv_max0p9 = 900, /*MHz*/
  93                 .phyclkv_nom0p8 = 847, /*MHz*/
  94                 .phyclkv_mid0p72 = 800, /*MHz*/
  95                 .phyclkv_min0p65 = 600, /*MHz*/
  96
  97                 /* BW depend on FCLK, MCLK, # of channels */
  98                 /* dual channel BW */
  99                 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
 100                 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
 101                 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
 102                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
 103                 /* single channel BW
 104                 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
 105                 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
 106                 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
 107                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
 108                 */
 109
 110                 .number_of_channels = 2,
 111
 112                 .socclk = 208, /*MHz*/
 113                 .downspreading = 0.5f, /*%*/
 114                 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
 115                 .urgent_out_of_order_return_per_channel = 256, /*bytes*/
 116                 .vmm_page_size = 4096, /*bytes*/
 117                 .return_bus_width = 64, /*bytes*/
 118                 .max_request_size = 256, /*bytes*/
 119
 120                 /* Depends on user class (client vs embedded, workstation, etc) */
 121                 .percent_disp_bw_limit = 0.3f /*%*/
 122 };
 123
 124 const struct dcn_ip_params dcn10_ip_defaults = {
 125                 .rob_buffer_size_in_kbyte = 64,
 126                 .det_buffer_size_in_kbyte = 164,
 127                 .dpp_output_buffer_pixels = 2560,
 128                 .opp_output_buffer_lines = 1,
 129                 .pixel_chunk_size_in_kbyte = 8,
 130                 .pte_enable = dcn_bw_yes,
 131                 .pte_chunk_size = 2, /*kbytes*/
 132                 .meta_chunk_size = 2, /*kbytes*/
 133                 .writeback_chunk_size = 2, /*kbytes*/
 134                 .odm_capability = dcn_bw_no,
 135                 .dsc_capability = dcn_bw_no,
 136                 .line_buffer_size = 589824, /*bit*/
 137                 .max_line_buffer_lines = 12,
 138                 .is_line_buffer_bpp_fixed = dcn_bw_no,
 139                 .line_buffer_fixed_bpp = dcn_bw_na,
 140                 .writeback_luma_buffer_size = 12, /*kbytes*/
 141                 .writeback_chroma_buffer_size = 8, /*kbytes*/
 142                 .max_num_dpp = 4,
 143                 .max_num_writeback = 2,
 144                 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
 145                 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
 146                 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
 147                 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
 148                 .max_hscl_ratio = 4,
 149                 .max_vscl_ratio = 4,
 150                 .max_hscl_taps = 8,
 151                 .max_vscl_taps = 8,
 152                 .pte_buffer_size_in_requests = 42,
 153                 .dispclk_ramping_margin = 1, /*%*/
 154                 .under_scan_factor = 1.11f,
 155                 .max_inter_dcn_tile_repeaters = 8,
 156                 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
 157                 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
 158                 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
 159 };
 160
 161 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
 162 {
 163         switch (sw_mode) {
 164         case DC_SW_LINEAR:
 165                 return dcn_bw_sw_linear;
 166         case DC_SW_4KB_S:
 167                 return dcn_bw_sw_4_kb_s;
 168         case DC_SW_4KB_D:
 169                 return dcn_bw_sw_4_kb_d;
 170         case DC_SW_64KB_S:
 171                 return dcn_bw_sw_64_kb_s;
 172         case DC_SW_64KB_D:
 173                 return dcn_bw_sw_64_kb_d;
 174         case DC_SW_VAR_S:
 175                 return dcn_bw_sw_var_s;
 176         case DC_SW_VAR_D:
 177                 return dcn_bw_sw_var_d;
 178         case DC_SW_64KB_S_T:
 179                 return dcn_bw_sw_64_kb_s_t;
 180         case DC_SW_64KB_D_T:
 181                 return dcn_bw_sw_64_kb_d_t;
 182         case DC_SW_4KB_S_X:
 183                 return dcn_bw_sw_4_kb_s_x;
 184         case DC_SW_4KB_D_X:
 185                 return dcn_bw_sw_4_kb_d_x;
 186         case DC_SW_64KB_S_X:
 187                 return dcn_bw_sw_64_kb_s_x;
 188         case DC_SW_64KB_D_X:
 189                 return dcn_bw_sw_64_kb_d_x;
 190         case DC_SW_VAR_S_X:
 191                 return dcn_bw_sw_var_s_x;
 192         case DC_SW_VAR_D_X:
 193                 return dcn_bw_sw_var_d_x;
 194         case DC_SW_256B_S:
 195         case DC_SW_256_D:
 196         case DC_SW_256_R:
 197         case DC_SW_4KB_R:
 198         case DC_SW_64KB_R:
 199         case DC_SW_VAR_R:
 200         case DC_SW_4KB_R_X:
 201         case DC_SW_64KB_R_X:
 202         case DC_SW_VAR_R_X:
 203         default:
 204                 BREAK_TO_DEBUGGER(); /*not in formula*/
 205                 return dcn_bw_sw_4_kb_s;
 206         }
 207 }
 208
 209 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
 210 {
 211         switch (depth) {
 212         case LB_PIXEL_DEPTH_18BPP:
 213                 return 18;
 214         case LB_PIXEL_DEPTH_24BPP:
 215                 return 24;
 216         case LB_PIXEL_DEPTH_30BPP:
 217                 return 30;
 218         case LB_PIXEL_DEPTH_36BPP:
 219                 return 36;
 220         default:
 221                 return 30;
 222         }
 223 }
 224
 225 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
 226 {
 227         switch (format) {
 228         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 229         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 230                 return dcn_bw_rgb_sub_16;
 231         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 232         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 233         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 234         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 235         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 236                 return dcn_bw_rgb_sub_32;
 237         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 238         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 239         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 240                 return dcn_bw_rgb_sub_64;
 241         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 242         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 243                 return dcn_bw_yuv420_sub_8;
 244         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 245         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 246                 return dcn_bw_yuv420_sub_10;
 247         default:
 248                 return dcn_bw_rgb_sub_32;
 249         }
 250 }
 251
 252 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
 253 {
 254         switch (sw_mode) {
 255         /* for 4/8/16 high tiles */
 256         case DC_SW_LINEAR:
 257                 return dm_4k_tile;
 258         case DC_SW_4KB_S:
 259         case DC_SW_4KB_S_X:
 260                 return dm_4k_tile;
 261         case DC_SW_64KB_S:
 262         case DC_SW_64KB_S_X:
 263         case DC_SW_64KB_S_T:
 264                 return dm_64k_tile;
 265         case DC_SW_VAR_S:
 266         case DC_SW_VAR_S_X:
 267                 return dm_256k_tile;
 268
 269         /* For 64bpp 2 high tiles */
 270         case DC_SW_4KB_D:
 271         case DC_SW_4KB_D_X:
 272                 return dm_4k_tile;
 273         case DC_SW_64KB_D:
 274         case DC_SW_64KB_D_X:
 275         case DC_SW_64KB_D_T:
 276                 return dm_64k_tile;
 277         case DC_SW_VAR_D:
 278         case DC_SW_VAR_D_X:
 279                 return dm_256k_tile;
 280
 281         case DC_SW_4KB_R:
 282         case DC_SW_4KB_R_X:
 283                 return dm_4k_tile;
 284         case DC_SW_64KB_R:
 285         case DC_SW_64KB_R_X:
 286                 return dm_64k_tile;
 287         case DC_SW_VAR_R:
 288         case DC_SW_VAR_R_X:
 289                 return dm_256k_tile;
 290
 291         /* Unsupported swizzle modes for dcn */
 292         case DC_SW_256B_S:
 293         default:
 294                 ASSERT(0); /* Not supported */
 295                 return 0;
 296         }
 297 }
 298
 299 static void pipe_ctx_to_e2e_pipe_params (
 300                 const struct pipe_ctx *pipe,
 301                 struct _vcs_dpi_display_pipe_params_st *input)
 302 {
 303         input->src.is_hsplit = false;
 304         if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
 305                 input->src.is_hsplit = true;
 306         else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
 307                 input->src.is_hsplit = true;
 308
 309         if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
 310                 /*
 311                  * this method requires us to always re-calculate watermark when dcc change
 312                  * between flip.
 313                  */
 314                 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
 315         } else {
 316                 /*
 317                  * allow us to disable dcc on the fly without re-calculating WM
 318                  *
 319                  * extra overhead for DCC is quite small.  for 1080p WM without
 320                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
 321                  */
 322                 unsigned int bpe;
 323
 324                 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
 325                         dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
 326         }
 327         input->src.dcc_rate            = 1;
 328         input->src.meta_pitch          = pipe->plane_state->dcc.meta_pitch;
 329         input->src.source_scan         = dm_horz;
 330         input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
 331
 332         input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
 333         input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
 334         input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
 335         input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
 336         input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
 337         input->src.cur0_bpp            = 32;
 338
 339         input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
 340
 341         switch (pipe->plane_state->rotation) {
 342         case ROTATION_ANGLE_0:
 343         case ROTATION_ANGLE_180:
 344                 input->src.source_scan = dm_horz;
 345                 break;
 346         case ROTATION_ANGLE_90:
 347         case ROTATION_ANGLE_270:
 348                 input->src.source_scan = dm_vert;
 349                 break;
 350         default:
 351                 ASSERT(0); /* Not supported */
 352                 break;
 353         }
 354
 355         /* TODO: Fix pixel format mappings */
 356         switch (pipe->plane_state->format) {
 357         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 358         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 359                 input->src.source_format = dm_420_8;
 360                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 361                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 362                 break;
 363         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 364         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 365                 input->src.source_format = dm_420_10;
 366                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 367                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 368                 break;
 369         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 370         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 371         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 372                 input->src.source_format = dm_444_64;
 373                 input->src.viewport_width_c    = input->src.viewport_width;
 374                 input->src.viewport_height_c   = input->src.viewport_height;
 375                 break;
 376         default:
 377                 input->src.source_format = dm_444_32;
 378                 input->src.viewport_width_c    = input->src.viewport_width;
 379                 input->src.viewport_height_c   = input->src.viewport_height;
 380                 break;
 381         }
 382
 383         input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
 384         input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
 385         input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
 386         input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
 387         if (input->scale_ratio_depth.vinit < 1.0)
 388                         input->scale_ratio_depth.vinit = 1;
 389         input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
 390         input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
 391         input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
 392         input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
 393         input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
 394         input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
 395         if (input->scale_ratio_depth.vinit_c < 1.0)
 396                         input->scale_ratio_depth.vinit_c = 1;
 397         switch (pipe->plane_res.scl_data.lb_params.depth) {
 398         case LB_PIXEL_DEPTH_30BPP:
 399                 input->scale_ratio_depth.lb_depth = 30; break;
 400         case LB_PIXEL_DEPTH_36BPP:
 401                 input->scale_ratio_depth.lb_depth = 36; break;
 402         default:
 403                 input->scale_ratio_depth.lb_depth = 24; break;
 404         }
 405
 406
 407         input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
 408                         + pipe->stream->timing.v_border_bottom;
 409
 410         input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
 411         input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
 412
 413         input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
 414         input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
 415
 416         input->dest.htotal         = pipe->stream->timing.h_total;
 417         input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
 418         input->dest.hblank_end     = input->dest.hblank_start
 419                         - pipe->stream->timing.h_addressable
 420                         - pipe->stream->timing.h_border_left
 421                         - pipe->stream->timing.h_border_right;
 422
 423         input->dest.vtotal         = pipe->stream->timing.v_total;
 424         input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
 425         input->dest.vblank_end     = input->dest.vblank_start
 426                         - pipe->stream->timing.v_addressable
 427                         - pipe->stream->timing.v_border_bottom
 428                         - pipe->stream->timing.v_border_top;
 429         input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
 430         input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
 431         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 432         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 433         input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
 434
 435 }
 436
 437 static void dcn_bw_calc_rq_dlg_ttu(
 438                 const struct dc *dc,
 439                 const struct dcn_bw_internal_vars *v,
 440                 struct pipe_ctx *pipe,
 441                 int in_idx)
 442 {
 443         struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
 444         struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
 445         struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
 446         struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
 447         struct _vcs_dpi_display_rq_params_st rq_param = {0};
 448         struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
 449         struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
 450         float total_active_bw = 0;
 451         float total_prefetch_bw = 0;
 452         int total_flip_bytes = 0;
 453         int i;
 454
 455         memset(dlg_regs, 0, sizeof(*dlg_regs));
 456         memset(ttu_regs, 0, sizeof(*ttu_regs));
 457         memset(rq_regs, 0, sizeof(*rq_regs));
 458
 459         for (i = 0; i < number_of_planes; i++) {
 460                 total_active_bw += v->read_bandwidth[i];
 461                 total_prefetch_bw += v->prefetch_bandwidth[i];
 462                 total_flip_bytes += v->total_immediate_flip_bytes[i];
 463         }
 464         dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
 465         if (dlg_sys_param.total_flip_bw < 0.0)
 466                 dlg_sys_param.total_flip_bw = 0;
 467
 468         dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
 469         dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
 470         dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
 471         dlg_sys_param.t_extra_us = v->urgent_extra_latency;
 472         dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
 473         dlg_sys_param.total_flip_bytes = total_flip_bytes;
 474
 475         pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
 476         input.clks_cfg.dcfclk_mhz = v->dcfclk;
 477         input.clks_cfg.dispclk_mhz = v->dispclk;
 478         input.clks_cfg.dppclk_mhz = v->dppclk;
 479         input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
 480         input.clks_cfg.socclk_mhz = v->socclk;
 481         input.clks_cfg.voltage = v->voltage_level;
 482 //      dc->dml.logger = pool->base.logger;
 483         input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
 484         input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
 485         //input[in_idx].dout.output_standard;
 486
 487         /*todo: soc->sr_enter_plus_exit_time??*/
 488         dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
 489
 490         dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
 491         dml1_extract_rq_regs(dml, rq_regs, rq_param);
 492         dml1_rq_dlg_get_dlg_params(
 493                         dml,
 494                         dlg_regs,
 495                         ttu_regs,
 496                         rq_param.dlg,
 497                         dlg_sys_param,
 498                         input,
 499                         true,
 500                         true,
 501                         v->pte_enable == dcn_bw_yes,
 502                         pipe->plane_state->flip_immediate);
 503 }
 504
 505 static void split_stream_across_pipes(
 506                 struct resource_context *res_ctx,
 507                 const struct resource_pool *pool,
 508                 struct pipe_ctx *primary_pipe,
 509                 struct pipe_ctx *secondary_pipe)
 510 {
 511         int pipe_idx = secondary_pipe->pipe_idx;
 512
 513         if (!primary_pipe->plane_state)
 514                 return;
 515
 516         *secondary_pipe = *primary_pipe;
 517
 518         secondary_pipe->pipe_idx = pipe_idx;
 519         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
 520         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
 521         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
 522         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
 523         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
 524         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
 525         if (primary_pipe->bottom_pipe) {
 526                 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
 527                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
 528                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
 529         }
 530         primary_pipe->bottom_pipe = secondary_pipe;
 531         secondary_pipe->top_pipe = primary_pipe;
 532
 533         resource_build_scaling_params(primary_pipe);
 534         resource_build_scaling_params(secondary_pipe);
 535 }
 536
 537 #if 0
 538 static void calc_wm_sets_and_perf_params(
 539                 struct dc_state *context,
 540                 struct dcn_bw_internal_vars *v)
 541 {
 542         /* Calculate set A last to keep internal var state consistent for required config */
 543         if (v->voltage_level < 2) {
 544                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
 545                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
 546                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
 547                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 548
 549                 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
 550                         v->stutter_exit_watermark * 1000;
 551                 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
 552                                 v->stutter_enter_plus_exit_watermark * 1000;
 553                 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
 554                                 v->dram_clock_change_watermark * 1000;
 555                 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 556                 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
 557
 558                 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
 559                 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
 560                 v->dcfclk = v->dcfclkv_nom0p8;
 561                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 562
 563                 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
 564                         v->stutter_exit_watermark * 1000;
 565                 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
 566                                 v->stutter_enter_plus_exit_watermark * 1000;
 567                 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
 568                                 v->dram_clock_change_watermark * 1000;
 569                 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 570                 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
 571         }
 572
 573         if (v->voltage_level < 3) {
 574                 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
 575                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
 576                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
 577                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
 578                 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
 579                 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
 580                 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
 581                 v->dcfclk = v->dcfclkv_max0p9;
 582                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 583
 584                 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
 585                         v->stutter_exit_watermark * 1000;
 586                 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
 587                                 v->stutter_enter_plus_exit_watermark * 1000;
 588                 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
 589                                 v->dram_clock_change_watermark * 1000;
 590                 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 591                 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
 592         }
 593
 594         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 595         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 596         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 597         v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
 598         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 599         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 600         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 601         v->dcfclk = v->dcfclk_per_state[v->voltage_level];
 602         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 603
 604         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
 605                 v->stutter_exit_watermark * 1000;
 606         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
 607                         v->stutter_enter_plus_exit_watermark * 1000;
 608         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
 609                         v->dram_clock_change_watermark * 1000;
 610         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 611         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
 612         if (v->voltage_level >= 2) {
 613                 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
 614                 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
 615         }
 616         if (v->voltage_level >= 3)
 617                 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
 618 }
 619 #endif
 620
 621 static bool dcn_bw_apply_registry_override(struct dc *dc)
 622 {
 623         bool updated = false;
 624
 625         kernel_fpu_begin();
 626         if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
 627                         && dc->debug.sr_exit_time_ns) {
 628                 updated = true;
 629                 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
 630         }
 631
 632         if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
 633                                 != dc->debug.sr_enter_plus_exit_time_ns
 634                         && dc->debug.sr_enter_plus_exit_time_ns) {
 635                 updated = true;
 636                 dc->dcn_soc->sr_enter_plus_exit_time =
 637                                 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
 638         }
 639
 640         if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
 641                         && dc->debug.urgent_latency_ns) {
 642                 updated = true;
 643                 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
 644         }
 645
 646         if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
 647                                 != dc->debug.percent_of_ideal_drambw
 648                         && dc->debug.percent_of_ideal_drambw) {
 649                 updated = true;
 650                 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
 651                                 dc->debug.percent_of_ideal_drambw;
 652         }
 653
 654         if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
 655                                 != dc->debug.dram_clock_change_latency_ns
 656                         && dc->debug.dram_clock_change_latency_ns) {
 657                 updated = true;
 658                 dc->dcn_soc->dram_clock_change_latency =
 659                                 dc->debug.dram_clock_change_latency_ns / 1000.0;
 660         }
 661         kernel_fpu_end();
 662
 663         return updated;
 664 }
 665
 666 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
 667 {
 668         /*
 669          * disable optional pipe split by lower dispclk bounding box
 670          * at DPM0
 671          */
 672         v->max_dispclk[0] = v->max_dppclk_vmin0p65;
 673 }
 674
 675 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
 676                 unsigned int pixel_rate_100hz)
 677 {
 678         float pixel_rate_mhz = pixel_rate_100hz / 10000;
 679
 680         /*
 681          * force enabling pipe split by lower dpp clock for DPM0 to just
 682          * below the specify pixel_rate, so bw calc would split pipe.
 683          */
 684         if (pixel_rate_mhz < v->max_dppclk[0])
 685                 v->max_dppclk[0] = pixel_rate_mhz;
 686 }
 687
 688 static void hack_bounding_box(struct dcn_bw_internal_vars *v,
 689                 struct dc_debug_options *dbg,
 690                 struct dc_state *context)
 691 {
 692         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
 693                 hack_disable_optional_pipe_split(v);
 694
 695         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
 696                 context->stream_count >= 2)
 697                 hack_disable_optional_pipe_split(v);
 698
 699         if (context->stream_count == 1 &&
 700                         dbg->force_single_disp_pipe_split)
 701                 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 702 }
 703
 704
 705 unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
 706 {
 707         /* for dali, the highest voltage level we want is 0 */
 708         if (ASICREV_IS_DALI(hw_internal_rev))
 709                 return 0;
 710
 711         /* we are ok with all levels */
 712         return 4;
 713 }
 714
 715 bool dcn_validate_bandwidth(
 716                 struct dc *dc,
 717                 struct dc_state *context,
 718                 bool fast_validate)
 719 {
 720         /*
 721          * we want a breakdown of the various stages of validation, which the
 722          * perf_trace macro doesn't support
 723          */
 724         BW_VAL_TRACE_SETUP();
 725
 726         const struct resource_pool *pool = dc->res_pool;
 727         struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
 728         int i, input_idx, k;
 729         int vesa_sync_start, asic_blank_end, asic_blank_start;
 730         bool bw_limit_pass;
 731         float bw_limit;
 732
 733         PERFORMANCE_TRACE_START();
 734
 735         BW_VAL_TRACE_COUNT();
 736
 737         if (dcn_bw_apply_registry_override(dc))
 738                 dcn_bw_sync_calcs_and_dml(dc);
 739
 740         memset(v, 0, sizeof(*v));
 741         kernel_fpu_begin();
 742
 743         v->sr_exit_time = dc->dcn_soc->sr_exit_time;
 744         v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
 745         v->urgent_latency = dc->dcn_soc->urgent_latency;
 746         v->write_back_latency = dc->dcn_soc->write_back_latency;
 747         v->percent_of_ideal_drambw_received_after_urg_latency =
 748                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
 749
 750         v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
 751         v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
 752         v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
 753         v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
 754
 755         v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
 756         v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
 757         v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
 758         v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
 759
 760         v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
 761         v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
 762         v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
 763         v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
 764
 765         v->socclk = dc->dcn_soc->socclk;
 766
 767         v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
 768         v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
 769         v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
 770         v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
 771
 772         v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
 773         v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
 774         v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
 775         v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
 776
 777         v->downspreading = dc->dcn_soc->downspreading;
 778         v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
 779         v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
 780         v->number_of_channels = dc->dcn_soc->number_of_channels;
 781         v->vmm_page_size = dc->dcn_soc->vmm_page_size;
 782         v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
 783         v->return_bus_width = dc->dcn_soc->return_bus_width;
 784
 785         v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
 786         v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
 787         v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
 788         v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
 789         v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
 790         v->pte_enable = dc->dcn_ip->pte_enable;
 791         v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
 792         v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
 793         v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
 794         v->odm_capability = dc->dcn_ip->odm_capability;
 795         v->dsc_capability = dc->dcn_ip->dsc_capability;
 796         v->line_buffer_size = dc->dcn_ip->line_buffer_size;
 797         v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
 798         v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
 799         v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
 800         v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
 801         v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
 802         v->max_num_dpp = dc->dcn_ip->max_num_dpp;
 803         v->max_num_writeback = dc->dcn_ip->max_num_writeback;
 804         v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
 805         v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
 806         v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
 807         v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
 808         v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
 809         v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
 810         v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
 811         v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
 812         v->under_scan_factor = dc->dcn_ip->under_scan_factor;
 813         v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
 814         v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
 815         v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
 816         v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
 817                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 818         v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
 819                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
 820
 821         v->voltage[5] = dcn_bw_no_support;
 822         v->voltage[4] = dcn_bw_v_max0p9;
 823         v->voltage[3] = dcn_bw_v_max0p9;
 824         v->voltage[2] = dcn_bw_v_nom0p8;
 825         v->voltage[1] = dcn_bw_v_mid0p72;
 826         v->voltage[0] = dcn_bw_v_min0p65;
 827         v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
 828         v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
 829         v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
 830         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 831         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 832         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 833         v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
 834         v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
 835         v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
 836         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 837         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 838         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 839         v->max_dispclk[5] = v->max_dispclk_vmax0p9;
 840         v->max_dispclk[4] = v->max_dispclk_vmax0p9;
 841         v->max_dispclk[3] = v->max_dispclk_vmax0p9;
 842         v->max_dispclk[2] = v->max_dispclk_vnom0p8;
 843         v->max_dispclk[1] = v->max_dispclk_vmid0p72;
 844         v->max_dispclk[0] = v->max_dispclk_vmin0p65;
 845         v->max_dppclk[5] = v->max_dppclk_vmax0p9;
 846         v->max_dppclk[4] = v->max_dppclk_vmax0p9;
 847         v->max_dppclk[3] = v->max_dppclk_vmax0p9;
 848         v->max_dppclk[2] = v->max_dppclk_vnom0p8;
 849         v->max_dppclk[1] = v->max_dppclk_vmid0p72;
 850         v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 851         v->phyclk_per_state[5] = v->phyclkv_max0p9;
 852         v->phyclk_per_state[4] = v->phyclkv_max0p9;
 853         v->phyclk_per_state[3] = v->phyclkv_max0p9;
 854         v->phyclk_per_state[2] = v->phyclkv_nom0p8;
 855         v->phyclk_per_state[1] = v->phyclkv_mid0p72;
 856         v->phyclk_per_state[0] = v->phyclkv_min0p65;
 857         v->synchronized_vblank = dcn_bw_no;
 858         v->ta_pscalculation = dcn_bw_override;
 859         v->allow_different_hratio_vratio = dcn_bw_yes;
 860
 861         for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
 862                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 863
 864                 if (!pipe->stream)
 865                         continue;
 866                 /* skip all but first of split pipes */
 867                 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
 868                         continue;
 869
 870                 v->underscan_output[input_idx] = false; /* taken care of in recout already*/
 871                 v->interlace_output[input_idx] = false;
 872
 873                 v->htotal[input_idx] = pipe->stream->timing.h_total;
 874                 v->vtotal[input_idx] = pipe->stream->timing.v_total;
 875                 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
 876                                 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
 877                 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
 878                                 - v->vactive[input_idx]
 879                                 - pipe->stream->timing.v_front_porch;
 880                 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
 881                 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 882                         v->pixel_clock[input_idx] *= 2;
 883                 if (!pipe->plane_state) {
 884                         v->dcc_enable[input_idx] = dcn_bw_yes;
 885                         v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
 886                         v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
 887                         v->lb_bit_per_pixel[input_idx] = 30;
 888                         v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
 889                         v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
 890                         /*
 891                          * for cases where we have no plane, we want to validate up to 1080p
 892                          * source size because here we are only interested in if the output
 893                          * timing is supported or not. if we cannot support native resolution
 894                          * of the high res display, we still want to support lower res up scale
 895                          * to native
 896                          */
 897                         if (v->viewport_width[input_idx] > 1920)
 898                                 v->viewport_width[input_idx] = 1920;
 899                         if (v->viewport_height[input_idx] > 1080)
 900                                 v->viewport_height[input_idx] = 1080;
 901                         v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
 902                         v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
 903                         v->override_hta_ps[input_idx] = 1;
 904                         v->override_vta_ps[input_idx] = 1;
 905                         v->override_hta_pschroma[input_idx] = 1;
 906                         v->override_vta_pschroma[input_idx] = 1;
 907                         v->source_scan[input_idx] = dcn_bw_hor;
 908
 909                 } else {
 910                         v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
 911                         v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
 912                         v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
 913                         v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
 914                         if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
 915                                 if (pipe->plane_state->rotation % 2 == 0) {
 916                                         int viewport_end = pipe->plane_res.scl_data.viewport.width
 917                                                         + pipe->plane_res.scl_data.viewport.x;
 918                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
 919                                                         + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 920
 921                                         if (viewport_end > viewport_b_end)
 922                                                 v->viewport_width[input_idx] = viewport_end
 923                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 924                                         else
 925                                                 v->viewport_width[input_idx] = viewport_b_end
 926                                                                         - pipe->plane_res.scl_data.viewport.x;
 927                                 } else  {
 928                                         int viewport_end = pipe->plane_res.scl_data.viewport.height
 929                                                 + pipe->plane_res.scl_data.viewport.y;
 930                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
 931                                                 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 932
 933                                         if (viewport_end > viewport_b_end)
 934                                                 v->viewport_height[input_idx] = viewport_end
 935                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 936                                         else
 937                                                 v->viewport_height[input_idx] = viewport_b_end
 938                                                                         - pipe->plane_res.scl_data.viewport.y;
 939                                 }
 940                                 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
 941                                                 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
 942                         }
 943
 944                         if (pipe->plane_state->rotation % 2 == 0) {
 945                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
 946                                         || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
 947                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
 948                                         || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
 949                         } else {
 950                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
 951                                         || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
 952                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
 953                                         || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
 954                         }
 955
 956                         if (dc->debug.optimized_watermark) {
 957                                 /*
 958                                  * this method requires us to always re-calculate watermark when dcc change
 959                                  * between flip.
 960                                  */
 961                                 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
 962                         } else {
 963                                 /*
 964                                  * allow us to disable dcc on the fly without re-calculating WM
 965                                  *
 966                                  * extra overhead for DCC is quite small.  for 1080p WM without
 967                                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
 968                                  */
 969                                 unsigned int bpe;
 970
 971                                 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
 972                                                 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
 973                         }
 974
 975                         v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
 976                                         pipe->plane_state->format);
 977                         v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
 978                                         pipe->plane_state->tiling_info.gfx9.swizzle);
 979                         v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
 980                         v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
 981                         v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
 982                         v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
 983                         v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
 984                         /*
 985                          * Spreadsheet doesn't handle taps_c is one properly,
 986                          * need to force Chroma to always be scaled to pass
 987                          * bandwidth validation.
 988                          */
 989                         if (v->override_hta_pschroma[input_idx] == 1)
 990                                 v->override_hta_pschroma[input_idx] = 2;
 991                         if (v->override_vta_pschroma[input_idx] == 1)
 992                                 v->override_vta_pschroma[input_idx] = 2;
 993                         v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
 994                 }
 995                 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
 996                         v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
 997                 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
 998                 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
 999                                 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
1000                 v->output[input_idx] = pipe->stream->signal ==
1001                                 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
1002                 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
1003                 if (v->output[input_idx] == dcn_bw_hdmi) {
1004                         switch (pipe->stream->timing.display_color_depth) {
1005                         case COLOR_DEPTH_101010:
1006                                 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
1007                                 break;
1008                         case COLOR_DEPTH_121212:
1009                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_12bpc;
1010                                 break;
1011                         case COLOR_DEPTH_161616:
1012                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_16bpc;
1013                                 break;
1014                         default:
1015                                 break;
1016                         }
1017                 }
1018
1019                 input_idx++;
1020         }
1021         v->number_of_active_planes = input_idx;
1022
1023         scaler_settings_calculation(v);
1024
1025         hack_bounding_box(v, &dc->debug, context);
1026
1027         mode_support_and_system_configuration(v);
1028
1029         /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1030         if (v->voltage_level != 0
1031                         && context->stream_count == 1
1032                         && dc->debug.force_single_disp_pipe_split) {
1033                 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
1034                 mode_support_and_system_configuration(v);
1035         }
1036
1037         if (v->voltage_level == 0 &&
1038                         (dc->debug.sr_exit_time_dpm0_ns
1039                                 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
1040
1041                 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
1042                         v->sr_enter_plus_exit_time =
1043                                 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1044                 if (dc->debug.sr_exit_time_dpm0_ns)
1045                         v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1046                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1047                 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1048                 mode_support_and_system_configuration(v);
1049         }
1050
1051         display_pipe_configuration(v);
1052
1053         for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1054                 if (v->source_scan[k] == dcn_bw_hor)
1055                         v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
1056                 else
1057                         v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
1058         }
1059         for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1060                 if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
1061                         v->byte_per_pixel_dety[k] = 8.0;
1062                         v->byte_per_pixel_detc[k] = 0.0;
1063                 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
1064                         v->byte_per_pixel_dety[k] = 4.0;
1065                         v->byte_per_pixel_detc[k] = 0.0;
1066                 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
1067                         v->byte_per_pixel_dety[k] = 2.0;
1068                         v->byte_per_pixel_detc[k] = 0.0;
1069                 } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
1070                         v->byte_per_pixel_dety[k] = 1.0;
1071                         v->byte_per_pixel_detc[k] = 2.0;
1072                 } else {
1073                         v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
1074                         v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
1075                 }
1076         }
1077
1078         v->total_data_read_bandwidth = 0.0;
1079         for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1080                 v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
1081                                 dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
1082                 v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
1083                                 dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
1084                 v->total_data_read_bandwidth = v->total_data_read_bandwidth +
1085                                 v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
1086         }
1087
1088         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1089
1090         if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1091                 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1092
1093                 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1094                         bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1095                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1096                         bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1097                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1098                         bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1099                 else
1100                         bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1101
1102                 if (bw_consumed < v->fabric_and_dram_bandwidth)
1103                         if (dc->debug.voltage_align_fclk)
1104                                 bw_consumed = v->fabric_and_dram_bandwidth;
1105
1106                 display_pipe_configuration(v);
1107                 /*calc_wm_sets_and_perf_params(context, v);*/
1108                 /* Only 1 set is used by dcn since no noticeable
1109                  * performance improvement was measured and due to hw bug DEGVIDCN10-254
1110                  */
1111                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1112
1113                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1114                         v->stutter_exit_watermark * 1000;
1115                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1116                                 v->stutter_enter_plus_exit_watermark * 1000;
1117                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1118                                 v->dram_clock_change_watermark * 1000;
1119                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1120                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1121                 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1122                 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1123                 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1124
1125                 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1126                                 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1127                 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
1128                         context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1129
1130                 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1131                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1132
1133                 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1134                 if (dc->debug.max_disp_clk == true)
1135                         context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1136
1137                 if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
1138                                 dc->debug.min_disp_clk_khz) {
1139                         context->bw_ctx.bw.dcn.clk.dispclk_khz =
1140                                         dc->debug.min_disp_clk_khz;
1141                 }
1142
1143                 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1144                                 v->dispclk_dppclk_ratio;
1145                 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1146                 switch (v->voltage_level) {
1147                 case 0:
1148                         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1149                                         (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1150                         break;
1151                 case 1:
1152                         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1153                                         (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1154                         break;
1155                 case 2:
1156                         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1157                                         (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1158                         break;
1159                 default:
1160                         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1161                                         (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1162                         break;
1163                 }
1164
1165                 BW_VAL_TRACE_END_WATERMARKS();
1166
1167                 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1168                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1169
1170                         /* skip inactive pipe */
1171                         if (!pipe->stream)
1172                                 continue;
1173                         /* skip all but first of split pipes */
1174                         if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1175                                 continue;
1176
1177                         pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1178                         pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1179                         pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1180                         pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1181
1182                         pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1183                         pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1184                         vesa_sync_start = pipe->stream->timing.v_addressable +
1185                                                 pipe->stream->timing.v_border_bottom +
1186                                                 pipe->stream->timing.v_front_porch;
1187
1188                         asic_blank_end = (pipe->stream->timing.v_total -
1189                                                 vesa_sync_start -
1190                                                 pipe->stream->timing.v_border_top)
1191                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1192
1193                         asic_blank_start = asic_blank_end +
1194                                                 (pipe->stream->timing.v_border_top +
1195                                                 pipe->stream->timing.v_addressable +
1196                                                 pipe->stream->timing.v_border_bottom)
1197                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1198
1199                         pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1200                         pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1201
1202                         if (pipe->plane_state) {
1203                                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1204
1205                                 pipe->plane_state->update_flags.bits.full_update = 1;
1206
1207                                 if (v->dpp_per_plane[input_idx] == 2 ||
1208                                         ((pipe->stream->view_format ==
1209                                           VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1210                                           pipe->stream->view_format ==
1211                                           VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1212                                         (pipe->stream->timing.timing_3d_format ==
1213                                          TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1214                                          pipe->stream->timing.timing_3d_format ==
1215                                          TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1216                                         if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1217                                                 /* update previously split pipe */
1218                                                 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1219                                                 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1220                                                 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1221                                                 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1222
1223                                                 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1224                                                 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1225                                                 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1226                                                 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1227                                         } else {
1228                                                 /* pipe not split previously needs split */
1229                                                 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1230                                                 ASSERT(hsplit_pipe);
1231                                                 split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1232                                         }
1233
1234                                         dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1235                                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1236                                         /* merge previously split pipe */
1237                                         pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1238                                         if (hsplit_pipe->bottom_pipe)
1239                                                 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1240                                         hsplit_pipe->plane_state = NULL;
1241                                         hsplit_pipe->stream = NULL;
1242                                         hsplit_pipe->top_pipe = NULL;
1243                                         hsplit_pipe->bottom_pipe = NULL;
1244                                         /* Clear plane_res and stream_res */
1245                                         memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1246                                         memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1247                                         resource_build_scaling_params(pipe);
1248                                 }
1249                                 /* for now important to do this after pipe split for building e2e params */
1250                                 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1251                         }
1252
1253                         input_idx++;
1254                 }
1255         } else if (v->voltage_level == number_of_states_plus_one) {
1256                 BW_VAL_TRACE_SKIP(fail);
1257         } else if (fast_validate) {
1258                 BW_VAL_TRACE_SKIP(fast);
1259         }
1260
1261         if (v->voltage_level == 0) {
1262                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
1263                                 dc->dcn_soc->sr_enter_plus_exit_time;
1264                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1265         }
1266
1267         /*
1268          * BW limit is set to prevent display from impacting other system functions
1269          */
1270
1271         bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1272         bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1273
1274         kernel_fpu_end();
1275
1276         PERFORMANCE_TRACE_END();
1277         BW_VAL_TRACE_FINISH();
1278
1279         if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
1280                 return true;
1281         else
1282                 return false;
1283 }
1284
1285 static unsigned int dcn_find_normalized_clock_vdd_Level(
1286         const struct dc *dc,
1287         enum dm_pp_clock_type clocks_type,
1288         int clocks_in_khz)
1289 {
1290         int vdd_level = dcn_bw_v_min0p65;
1291
1292         if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1293                 return vdd_level;
1294
1295         switch (clocks_type) {
1296         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1297                 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1298                         vdd_level = dcn_bw_v_max0p91;
1299                         BREAK_TO_DEBUGGER();
1300                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1301                         vdd_level = dcn_bw_v_max0p9;
1302                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1303                         vdd_level = dcn_bw_v_nom0p8;
1304                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1305                         vdd_level = dcn_bw_v_mid0p72;
1306                 } else
1307                         vdd_level = dcn_bw_v_min0p65;
1308                 break;
1309         case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1310                 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1311                         vdd_level = dcn_bw_v_max0p91;
1312                         BREAK_TO_DEBUGGER();
1313                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1314                         vdd_level = dcn_bw_v_max0p9;
1315                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1316                         vdd_level = dcn_bw_v_nom0p8;
1317                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1318                         vdd_level = dcn_bw_v_mid0p72;
1319                 } else
1320                         vdd_level = dcn_bw_v_min0p65;
1321                 break;
1322
1323         case DM_PP_CLOCK_TYPE_DPPCLK:
1324                 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1325                         vdd_level = dcn_bw_v_max0p91;
1326                         BREAK_TO_DEBUGGER();
1327                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1328                         vdd_level = dcn_bw_v_max0p9;
1329                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1330                         vdd_level = dcn_bw_v_nom0p8;
1331                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1332                         vdd_level = dcn_bw_v_mid0p72;
1333                 } else
1334                         vdd_level = dcn_bw_v_min0p65;
1335                 break;
1336
1337         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1338                 {
1339                         unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1340
1341                         if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1342                                 vdd_level = dcn_bw_v_max0p91;
1343                                 BREAK_TO_DEBUGGER();
1344                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1345                                 vdd_level = dcn_bw_v_max0p9;
1346                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1347                                 vdd_level = dcn_bw_v_nom0p8;
1348                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1349                                 vdd_level = dcn_bw_v_mid0p72;
1350                         } else
1351                                 vdd_level = dcn_bw_v_min0p65;
1352                 }
1353                 break;
1354
1355         case DM_PP_CLOCK_TYPE_DCFCLK:
1356                 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1357                         vdd_level = dcn_bw_v_max0p91;
1358                         BREAK_TO_DEBUGGER();
1359                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1360                         vdd_level = dcn_bw_v_max0p9;
1361                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1362                         vdd_level = dcn_bw_v_nom0p8;
1363                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1364                         vdd_level = dcn_bw_v_mid0p72;
1365                 } else
1366                         vdd_level = dcn_bw_v_min0p65;
1367                 break;
1368
1369         default:
1370                  break;
1371         }
1372         return vdd_level;
1373 }
1374
1375 unsigned int dcn_find_dcfclk_suits_all(
1376         const struct dc *dc,
1377         struct dc_clocks *clocks)
1378 {
1379         unsigned vdd_level, vdd_level_temp;
1380         unsigned dcf_clk;
1381
1382         /*find a common supported voltage level*/
1383         vdd_level = dcn_find_normalized_clock_vdd_Level(
1384                 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1385         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1386                 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1387
1388         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1389         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1390                 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1391         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1392
1393         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1394                 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1395         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1396         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1397                 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1398
1399         /*find that level conresponding dcfclk*/
1400         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1401         if (vdd_level == dcn_bw_v_max0p91) {
1402                 BREAK_TO_DEBUGGER();
1403                 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1404         } else if (vdd_level == dcn_bw_v_max0p9)
1405                 dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
1406         else if (vdd_level == dcn_bw_v_nom0p8)
1407                 dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
1408         else if (vdd_level == dcn_bw_v_mid0p72)
1409                 dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
1410         else
1411                 dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
1412
1413         DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1414         return dcf_clk;
1415 }
1416
1417 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1418 {
1419         int i;
1420
1421         if (clks->num_levels == 0)
1422                 return false;
1423
1424         for (i = 0; i < clks->num_levels; i++)
1425                 /* Ensure that the result is sane */
1426                 if (clks->data[i].clocks_in_khz == 0)
1427                         return false;
1428
1429         return true;
1430 }
1431
1432 void dcn_bw_update_from_pplib(struct dc *dc)
1433 {
1434         struct dc_context *ctx = dc->ctx;
1435         struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1436         bool res;
1437
1438         /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1439         res = dm_pp_get_clock_levels_by_type_with_voltage(
1440                         ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1441
1442         kernel_fpu_begin();
1443
1444         if (res)
1445                 res = verify_clock_values(&fclks);
1446
1447         if (res) {
1448                 ASSERT(fclks.num_levels >= 3);
1449                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
1450                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
1451                                 (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
1452                                 * ddr4_dram_factor_single_Channel / 1000.0;
1453                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
1454                                 (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
1455                                 * ddr4_dram_factor_single_Channel / 1000.0;
1456                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
1457                                 (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
1458                                 * ddr4_dram_factor_single_Channel / 1000.0;
1459         } else
1460                 BREAK_TO_DEBUGGER();
1461
1462         kernel_fpu_end();
1463
1464         res = dm_pp_get_clock_levels_by_type_with_voltage(
1465                         ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1466
1467         kernel_fpu_begin();
1468
1469         if (res)
1470                 res = verify_clock_values(&dcfclks);
1471
1472         if (res && dcfclks.num_levels >= 3) {
1473                 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1474                 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1475                 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1476                 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1477         } else
1478                 BREAK_TO_DEBUGGER();
1479
1480         kernel_fpu_end();
1481 }
1482
1483 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1484 {
1485         struct pp_smu_funcs_rv *pp = NULL;
1486         struct pp_smu_wm_range_sets ranges = {0};
1487         int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1488         const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1489
1490         if (dc->res_pool->pp_smu)
1491                 pp = &dc->res_pool->pp_smu->rv_funcs;
1492         if (!pp || !pp->set_wm_ranges)
1493                 return;
1494
1495         kernel_fpu_begin();
1496         min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1497         min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1498         socclk_khz = dc->dcn_soc->socclk * 1000;
1499         kernel_fpu_end();
1500
1501         /* Now notify PPLib/SMU about which Watermarks sets they should select
1502          * depending on DPM state they are in. And update BW MGR GFX Engine and
1503          * Memory clock member variables for Watermarks calculations for each
1504          * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1505          */
1506         /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1507          * care what the value is, hence min to overdrive level
1508          */
1509         ranges.num_reader_wm_sets = WM_SET_COUNT;
1510         ranges.num_writer_wm_sets = WM_SET_COUNT;
1511         ranges.reader_wm_sets[0].wm_inst = WM_A;
1512         ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1513         ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1514         ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1515         ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1516         ranges.writer_wm_sets[0].wm_inst = WM_A;
1517         ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1518         ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1519         ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1520         ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1521
1522         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1523                 ranges.reader_wm_sets[0].wm_inst = WM_A;
1524                 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1525                 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1526                 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1527                 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1528                 ranges.writer_wm_sets[0].wm_inst = WM_A;
1529                 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1530                 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1531                 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1532                 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1533         }
1534
1535         ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1536         ranges.reader_wm_sets[1].wm_inst = WM_B;
1537
1538         ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1539         ranges.reader_wm_sets[2].wm_inst = WM_C;
1540
1541         ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1542         ranges.reader_wm_sets[3].wm_inst = WM_D;
1543
1544         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1545         pp->set_wm_ranges(&pp->pp_smu, &ranges);
1546 }
1547
1548 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1549 {
1550         kernel_fpu_begin();
1551         DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1552                         "sr_enter_plus_exit_time: %f ns\n"
1553                         "urgent_latency: %f ns\n"
1554                         "write_back_latency: %f ns\n"
1555                         "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1556                         "max_request_size: %d bytes\n"
1557                         "dcfclkv_max0p9: %f kHz\n"
1558                         "dcfclkv_nom0p8: %f kHz\n"
1559                         "dcfclkv_mid0p72: %f kHz\n"
1560                         "dcfclkv_min0p65: %f kHz\n"
1561                         "max_dispclk_vmax0p9: %f kHz\n"
1562                         "max_dispclk_vnom0p8: %f kHz\n"
1563                         "max_dispclk_vmid0p72: %f kHz\n"
1564                         "max_dispclk_vmin0p65: %f kHz\n"
1565                         "max_dppclk_vmax0p9: %f kHz\n"
1566                         "max_dppclk_vnom0p8: %f kHz\n"
1567                         "max_dppclk_vmid0p72: %f kHz\n"
1568                         "max_dppclk_vmin0p65: %f kHz\n"
1569                         "socclk: %f kHz\n"
1570                         "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1571                         "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1572                         "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1573                         "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1574                         "phyclkv_max0p9: %f kHz\n"
1575                         "phyclkv_nom0p8: %f kHz\n"
1576                         "phyclkv_mid0p72: %f kHz\n"
1577                         "phyclkv_min0p65: %f kHz\n"
1578                         "downspreading: %f %%\n"
1579                         "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1580                         "urgent_out_of_order_return_per_channel: %d Bytes\n"
1581                         "number_of_channels: %d\n"
1582                         "vmm_page_size: %d Bytes\n"
1583                         "dram_clock_change_latency: %f ns\n"
1584                         "return_bus_width: %d Bytes\n",
1585                         dc->dcn_soc->sr_exit_time * 1000,
1586                         dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1587                         dc->dcn_soc->urgent_latency * 1000,
1588                         dc->dcn_soc->write_back_latency * 1000,
1589                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1590                         dc->dcn_soc->max_request_size,
1591                         dc->dcn_soc->dcfclkv_max0p9 * 1000,
1592                         dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1593                         dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1594                         dc->dcn_soc->dcfclkv_min0p65 * 1000,
1595                         dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1596                         dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1597                         dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1598                         dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1599                         dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1600                         dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1601                         dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1602                         dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1603                         dc->dcn_soc->socclk * 1000,
1604                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1605                         dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1606                         dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1607                         dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1608                         dc->dcn_soc->phyclkv_max0p9 * 1000,
1609                         dc->dcn_soc->phyclkv_nom0p8 * 1000,
1610                         dc->dcn_soc->phyclkv_mid0p72 * 1000,
1611                         dc->dcn_soc->phyclkv_min0p65 * 1000,
1612                         dc->dcn_soc->downspreading * 100,
1613                         dc->dcn_soc->round_trip_ping_latency_cycles,
1614                         dc->dcn_soc->urgent_out_of_order_return_per_channel,
1615                         dc->dcn_soc->number_of_channels,
1616                         dc->dcn_soc->vmm_page_size,
1617                         dc->dcn_soc->dram_clock_change_latency * 1000,
1618                         dc->dcn_soc->return_bus_width);
1619         DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1620                         "det_buffer_size_in_kbyte: %f\n"
1621                         "dpp_output_buffer_pixels: %f\n"
1622                         "opp_output_buffer_lines: %f\n"
1623                         "pixel_chunk_size_in_kbyte: %f\n"
1624                         "pte_enable: %d\n"
1625                         "pte_chunk_size: %d kbytes\n"
1626                         "meta_chunk_size: %d kbytes\n"
1627                         "writeback_chunk_size: %d kbytes\n"
1628                         "odm_capability: %d\n"
1629                         "dsc_capability: %d\n"
1630                         "line_buffer_size: %d bits\n"
1631                         "max_line_buffer_lines: %d\n"
1632                         "is_line_buffer_bpp_fixed: %d\n"
1633                         "line_buffer_fixed_bpp: %d\n"
1634                         "writeback_luma_buffer_size: %d kbytes\n"
1635                         "writeback_chroma_buffer_size: %d kbytes\n"
1636                         "max_num_dpp: %d\n"
1637                         "max_num_writeback: %d\n"
1638                         "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1639                         "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1640                         "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1641                         "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1642                         "max_hscl_ratio: %f\n"
1643                         "max_vscl_ratio: %f\n"
1644                         "max_hscl_taps: %d\n"
1645                         "max_vscl_taps: %d\n"
1646                         "pte_buffer_size_in_requests: %d\n"
1647                         "dispclk_ramping_margin: %f %%\n"
1648                         "under_scan_factor: %f %%\n"
1649                         "max_inter_dcn_tile_repeaters: %d\n"
1650                         "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1651                         "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1652                         "dcfclk_cstate_latency: %d\n",
1653                         dc->dcn_ip->rob_buffer_size_in_kbyte,
1654                         dc->dcn_ip->det_buffer_size_in_kbyte,
1655                         dc->dcn_ip->dpp_output_buffer_pixels,
1656                         dc->dcn_ip->opp_output_buffer_lines,
1657                         dc->dcn_ip->pixel_chunk_size_in_kbyte,
1658                         dc->dcn_ip->pte_enable,
1659                         dc->dcn_ip->pte_chunk_size,
1660                         dc->dcn_ip->meta_chunk_size,
1661                         dc->dcn_ip->writeback_chunk_size,
1662                         dc->dcn_ip->odm_capability,
1663                         dc->dcn_ip->dsc_capability,
1664                         dc->dcn_ip->line_buffer_size,
1665                         dc->dcn_ip->max_line_buffer_lines,
1666                         dc->dcn_ip->is_line_buffer_bpp_fixed,
1667                         dc->dcn_ip->line_buffer_fixed_bpp,
1668                         dc->dcn_ip->writeback_luma_buffer_size,
1669                         dc->dcn_ip->writeback_chroma_buffer_size,
1670                         dc->dcn_ip->max_num_dpp,
1671                         dc->dcn_ip->max_num_writeback,
1672                         dc->dcn_ip->max_dchub_topscl_throughput,
1673                         dc->dcn_ip->max_pscl_tolb_throughput,
1674                         dc->dcn_ip->max_lb_tovscl_throughput,
1675                         dc->dcn_ip->max_vscl_tohscl_throughput,
1676                         dc->dcn_ip->max_hscl_ratio,
1677                         dc->dcn_ip->max_vscl_ratio,
1678                         dc->dcn_ip->max_hscl_taps,
1679                         dc->dcn_ip->max_vscl_taps,
1680                         dc->dcn_ip->pte_buffer_size_in_requests,
1681                         dc->dcn_ip->dispclk_ramping_margin,
1682                         dc->dcn_ip->under_scan_factor * 100,
1683                         dc->dcn_ip->max_inter_dcn_tile_repeaters,
1684                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1685                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1686                         dc->dcn_ip->dcfclk_cstate_latency);
1687
1688         dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1689         dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1690         dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1691         dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1692         dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1693                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1694         dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1695         dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1696         dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1697                         dc->dcn_soc->round_trip_ping_latency_cycles;
1698         dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1699                         dc->dcn_soc->urgent_out_of_order_return_per_channel;
1700         dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1701         dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1702         dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1703         dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1704
1705         dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1706         dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1707         dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1708         dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1709         dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1710         dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1711         dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1712         dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1713         dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1714         dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1715         dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1716         dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1717         dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1718         dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1719         dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1720         dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1721         dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1722         dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1723         dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1724         dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1725         dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1726         dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1727         dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1728         dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1729         dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1730         /*pte_buffer_size_in_requests missing in dml*/
1731         dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1732         dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1733         dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1734         dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1735                 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1736         dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1737                 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1738         dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1739         kernel_fpu_end();
1740 }