drivers/gpu/drm/amd/display/dc/bios/command_table2.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "ObjectID.h"
  29
  30 #include "atomfirmware.h"
  31 #include "atom.h"
  32 #include "include/bios_parser_interface.h"
  33
  34 #include "command_table2.h"
  35 #include "command_table_helper2.h"
  36 #include "bios_parser_helper.h"
  37 #include "bios_parser_types_internal2.h"
  38 #include "amdgpu.h"
  39
  40 #include "dc_dmub_srv.h"
  41 #include "dc.h"
  42
  43 #define DC_LOGGER \
  44         bp->base.ctx->logger
  45
  46 #define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
  47         (((char *)(&((\
  48                 struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\
  49                 ->FieldName)-(char *)0)/sizeof(uint16_t))
  50
  51 #define EXEC_BIOS_CMD_TABLE(fname, params)\
  52         (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
  53                 GET_INDEX_INTO_MASTER_TABLE(command, fname), \
  54                 (uint32_t *)&params) == 0)
  55
  56 #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
  57         amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
  58                 GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
  59
  60 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\
  61         bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
  62                         GET_INDEX_INTO_MASTER_TABLE(command, fname))
  63
  64
  65
  66 static uint32_t bios_cmd_table_para_revision(void *dev,
  67                                              uint32_t index)
  68 {
  69         struct amdgpu_device *adev = dev;
  70         uint8_t frev, crev;
  71
  72         if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
  73                                         index,
  74                                         &frev, &crev))
  75                 return crev;
  76         else
  77                 return 0;
  78 }
  79
  80 /******************************************************************************
  81  ******************************************************************************
  82  **
  83  **                  D I G E N C O D E R C O N T R O L
  84  **
  85  ******************************************************************************
  86  *****************************************************************************/
  87
  88 static enum bp_result encoder_control_digx_v1_5(
  89         struct bios_parser *bp,
  90         struct bp_encoder_control *cntl);
  91
  92 static enum bp_result encoder_control_fallback(
  93         struct bios_parser *bp,
  94         struct bp_encoder_control *cntl);
  95
  96 static void init_dig_encoder_control(struct bios_parser *bp)
  97 {
  98         uint32_t version =
  99                 BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol);
 100
 101         switch (version) {
 102         case 5:
 103                 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;
 104                 break;
 105         default:
 106                 dm_output_to_console("Don't have dig_encoder_control for v%d\n", version);
 107                 bp->cmd_tbl.dig_encoder_control = encoder_control_fallback;
 108                 break;
 109         }
 110 }
 111
 112 static void encoder_control_dmcub(
 113                 struct dc_dmub_srv *dmcub,
 114                 struct dig_encoder_stream_setup_parameters_v1_5 *dig)
 115 {
 116         struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 };
 117
 118         encoder_control.header.type = DMUB_CMD__VBIOS;
 119         encoder_control.header.sub_type = DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL;
 120         encoder_control.encoder_control.dig.stream_param = *dig;
 121
 122         dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header);
 123         dc_dmub_srv_cmd_execute(dmcub);
 124         dc_dmub_srv_wait_idle(dmcub);
 125 }
 126
 127 static enum bp_result encoder_control_digx_v1_5(
 128         struct bios_parser *bp,
 129         struct bp_encoder_control *cntl)
 130 {
 131         enum bp_result result = BP_RESULT_FAILURE;
 132         struct dig_encoder_stream_setup_parameters_v1_5 params = {0};
 133
 134         params.digid = (uint8_t)(cntl->engine_id);
 135         params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
 136
 137         params.pclk_10khz = cntl->pixel_clock / 10;
 138         params.digmode =
 139                         (uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
 140                                         cntl->signal,
 141                                         cntl->enable_dp_audio));
 142         params.lanenum = (uint8_t)(cntl->lanes_number);
 143
 144         switch (cntl->color_depth) {
 145         case COLOR_DEPTH_888:
 146                 params.bitpercolor = PANEL_8BIT_PER_COLOR;
 147                 break;
 148         case COLOR_DEPTH_101010:
 149                 params.bitpercolor = PANEL_10BIT_PER_COLOR;
 150                 break;
 151         case COLOR_DEPTH_121212:
 152                 params.bitpercolor = PANEL_12BIT_PER_COLOR;
 153                 break;
 154         case COLOR_DEPTH_161616:
 155                 params.bitpercolor = PANEL_16BIT_PER_COLOR;
 156                 break;
 157         default:
 158                 break;
 159         }
 160
 161         if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
 162                 switch (cntl->color_depth) {
 163                 case COLOR_DEPTH_101010:
 164                         params.pclk_10khz =
 165                                 (params.pclk_10khz * 30) / 24;
 166                         break;
 167                 case COLOR_DEPTH_121212:
 168                         params.pclk_10khz =
 169                                 (params.pclk_10khz * 36) / 24;
 170                         break;
 171                 case COLOR_DEPTH_161616:
 172                         params.pclk_10khz =
 173                                 (params.pclk_10khz * 48) / 24;
 174                         break;
 175                 default:
 176                         break;
 177                 }
 178
 179         if (bp->base.ctx->dc->ctx->dmub_srv &&
 180             bp->base.ctx->dc->debug.dmub_command_table) {
 181                 encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
 182                 return BP_RESULT_OK;
 183         }
 184
 185         if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
 186                 result = BP_RESULT_OK;
 187
 188         return result;
 189 }
 190
 191 static enum bp_result encoder_control_fallback(
 192         struct bios_parser *bp,
 193         struct bp_encoder_control *cntl)
 194 {
 195         if (bp->base.ctx->dc->ctx->dmub_srv &&
 196             bp->base.ctx->dc->debug.dmub_command_table) {
 197                 return encoder_control_digx_v1_5(bp, cntl);
 198         }
 199
 200         return BP_RESULT_FAILURE;
 201 }
 202
 203 /*****************************************************************************
 204  ******************************************************************************
 205  **
 206  **                  TRANSMITTER CONTROL
 207  **
 208  ******************************************************************************
 209  *****************************************************************************/
 210
 211 static enum bp_result transmitter_control_v1_6(
 212         struct bios_parser *bp,
 213         struct bp_transmitter_control *cntl);
 214
 215 static enum bp_result transmitter_control_fallback(
 216         struct bios_parser *bp,
 217         struct bp_transmitter_control *cntl);
 218
 219 static void init_transmitter_control(struct bios_parser *bp)
 220 {
 221         uint8_t frev;
 222         uint8_t crev;
 223
 224         BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev);
 225
 226         switch (crev) {
 227         case 6:
 228                 bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
 229                 break;
 230         default:
 231                 dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
 232                 bp->cmd_tbl.transmitter_control = transmitter_control_fallback;
 233                 break;
 234         }
 235 }
 236
 237 static void transmitter_control_dmcub(
 238                 struct dc_dmub_srv *dmcub,
 239                 struct dig_transmitter_control_parameters_v1_6 *dig)
 240 {
 241         struct dmub_rb_cmd_dig1_transmitter_control transmitter_control;
 242
 243         transmitter_control.header.type = DMUB_CMD__VBIOS;
 244         transmitter_control.header.sub_type =
 245                 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL;
 246         transmitter_control.transmitter_control.dig = *dig;
 247
 248         dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header);
 249         dc_dmub_srv_cmd_execute(dmcub);
 250         dc_dmub_srv_wait_idle(dmcub);
 251 }
 252
 253 static enum bp_result transmitter_control_v1_6(
 254         struct bios_parser *bp,
 255         struct bp_transmitter_control *cntl)
 256 {
 257         enum bp_result result = BP_RESULT_FAILURE;
 258         const struct command_table_helper *cmd = bp->cmd_helper;
 259         struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } };
 260
 261         ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter);
 262         ps.param.action = (uint8_t)cntl->action;
 263
 264         if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
 265                 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
 266         else
 267                 ps.param.mode_laneset.digmode =
 268                                 cmd->signal_type_to_atom_dig_mode(cntl->signal);
 269
 270         ps.param.lanenum = (uint8_t)cntl->lanes_number;
 271         ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
 272         ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
 273         ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;
 274         ps.param.symclk_10khz = cntl->pixel_clock/10;
 275
 276
 277         if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
 278                 cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
 279                 cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
 280                 DC_LOG_BIOS("%s:ps.param.symclk_10khz = %d\n",\
 281                 __func__, ps.param.symclk_10khz);
 282         }
 283
 284         if (bp->base.ctx->dc->ctx->dmub_srv &&
 285             bp->base.ctx->dc->debug.dmub_command_table) {
 286                 transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
 287                 return BP_RESULT_OK;
 288         }
 289
 290 /*color_depth not used any more, driver has deep color factor in the Phyclk*/
 291         if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
 292                 result = BP_RESULT_OK;
 293         return result;
 294 }
 295
 296 static enum bp_result transmitter_control_fallback(
 297         struct bios_parser *bp,
 298         struct bp_transmitter_control *cntl)
 299 {
 300         if (bp->base.ctx->dc->ctx->dmub_srv &&
 301             bp->base.ctx->dc->debug.dmub_command_table) {
 302                 return transmitter_control_v1_6(bp, cntl);
 303         }
 304
 305         return BP_RESULT_FAILURE;
 306 }
 307
 308 /******************************************************************************
 309  ******************************************************************************
 310  **
 311  **                  SET PIXEL CLOCK
 312  **
 313  ******************************************************************************
 314  *****************************************************************************/
 315
 316 static enum bp_result set_pixel_clock_v7(
 317         struct bios_parser *bp,
 318         struct bp_pixel_clock_parameters *bp_params);
 319
 320 static enum bp_result set_pixel_clock_fallback(
 321         struct bios_parser *bp,
 322         struct bp_pixel_clock_parameters *bp_params);
 323
 324 static void init_set_pixel_clock(struct bios_parser *bp)
 325 {
 326         switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
 327         case 7:
 328                 bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
 329                 break;
 330         default:
 331                 dm_output_to_console("Don't have set_pixel_clock for v%d\n",
 332                          BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));
 333                 bp->cmd_tbl.set_pixel_clock = set_pixel_clock_fallback;
 334                 break;
 335         }
 336 }
 337
 338 static void set_pixel_clock_dmcub(
 339                 struct dc_dmub_srv *dmcub,
 340                 struct set_pixel_clock_parameter_v1_7 *clk)
 341 {
 342         struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 };
 343
 344         pixel_clock.header.type = DMUB_CMD__VBIOS;
 345         pixel_clock.header.sub_type = DMUB_CMD__VBIOS_SET_PIXEL_CLOCK;
 346         pixel_clock.pixel_clock.clk = *clk;
 347
 348         dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header);
 349         dc_dmub_srv_cmd_execute(dmcub);
 350         dc_dmub_srv_wait_idle(dmcub);
 351 }
 352
 353 static enum bp_result set_pixel_clock_v7(
 354         struct bios_parser *bp,
 355         struct bp_pixel_clock_parameters *bp_params)
 356 {
 357         enum bp_result result = BP_RESULT_FAILURE;
 358         struct set_pixel_clock_parameter_v1_7 clk;
 359         uint8_t controller_id;
 360         uint32_t pll_id;
 361
 362         memset(&clk, 0, sizeof(clk));
 363
 364         if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
 365                         && bp->cmd_helper->controller_id_to_atom(bp_params->
 366                                         controller_id, &controller_id)) {
 367                 /* Note: VBIOS still wants to use ucCRTC name which is now
 368                  * 1 byte in ULONG
 369                  *typedef struct _CRTC_PIXEL_CLOCK_FREQ
 370                  *{
 371                  * target the pixel clock to drive the CRTC timing.
 372                  * ULONG ulPixelClock:24;
 373                  * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
 374                  * previous version.
 375                  * ATOM_CRTC1~6, indicate the CRTC controller to
 376                  * ULONG ucCRTC:8;
 377                  * drive the pixel clock. not used for DCPLL case.
 378                  *}CRTC_PIXEL_CLOCK_FREQ;
 379                  *union
 380                  *{
 381                  * pixel clock and CRTC id frequency
 382                  * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
 383                  * ULONG ulDispEngClkFreq; dispclk frequency
 384                  *};
 385                  */
 386                 clk.crtc_id = controller_id;
 387                 clk.pll_id = (uint8_t) pll_id;
 388                 clk.encoderobjid =
 389                         bp->cmd_helper->encoder_id_to_atom(
 390                                 dal_graphics_object_id_get_encoder_id(
 391                                         bp_params->encoder_object_id));
 392
 393                 clk.encoder_mode = (uint8_t) bp->
 394                         cmd_helper->encoder_mode_bp_to_atom(
 395                                 bp_params->signal_type, false);
 396
 397                 clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);
 398
 399                 clk.deep_color_ratio =
 400                         (uint8_t) bp->cmd_helper->
 401                                 transmitter_color_depth_to_atom(
 402                                         bp_params->color_depth);
 403
 404                 DC_LOG_BIOS("%s:program display clock = %d, tg = %d, pll = %d, "\
 405                                 "colorDepth = %d\n", __func__,
 406                                 bp_params->target_pixel_clock_100hz, (int)controller_id,
 407                                 pll_id, bp_params->color_depth);
 408
 409                 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
 410                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
 411
 412                 if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
 413                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
 414
 415                 if (bp_params->flags.SUPPORT_YUV_420)
 416                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
 417
 418                 if (bp_params->flags.SET_XTALIN_REF_SRC)
 419                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
 420
 421                 if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
 422                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
 423
 424                 if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
 425                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
 426
 427                 if (bp->base.ctx->dc->ctx->dmub_srv &&
 428                     bp->base.ctx->dc->debug.dmub_command_table) {
 429                         set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
 430                         return BP_RESULT_OK;
 431                 }
 432
 433                 if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
 434                         result = BP_RESULT_OK;
 435         }
 436         return result;
 437 }
 438
 439 static enum bp_result set_pixel_clock_fallback(
 440         struct bios_parser *bp,
 441         struct bp_pixel_clock_parameters *bp_params)
 442 {
 443         if (bp->base.ctx->dc->ctx->dmub_srv &&
 444             bp->base.ctx->dc->debug.dmub_command_table) {
 445                 return set_pixel_clock_v7(bp, bp_params);
 446         }
 447
 448         return BP_RESULT_FAILURE;
 449 }
 450
 451 /******************************************************************************
 452  ******************************************************************************
 453  **
 454  **                  SET CRTC TIMING
 455  **
 456  ******************************************************************************
 457  *****************************************************************************/
 458
 459 static enum bp_result set_crtc_using_dtd_timing_v3(
 460         struct bios_parser *bp,
 461         struct bp_hw_crtc_timing_parameters *bp_params);
 462
 463 static void init_set_crtc_timing(struct bios_parser *bp)
 464 {
 465         uint32_t dtd_version =
 466                         BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
 467
 468         switch (dtd_version) {
 469         case 3:
 470                 bp->cmd_tbl.set_crtc_timing =
 471                         set_crtc_using_dtd_timing_v3;
 472                 break;
 473         default:
 474                 dm_output_to_console("Don't have set_crtc_timing for v%d\n", dtd_version);
 475                 bp->cmd_tbl.set_crtc_timing = NULL;
 476                 break;
 477         }
 478 }
 479
 480 static enum bp_result set_crtc_using_dtd_timing_v3(
 481         struct bios_parser *bp,
 482         struct bp_hw_crtc_timing_parameters *bp_params)
 483 {
 484         enum bp_result result = BP_RESULT_FAILURE;
 485         struct set_crtc_using_dtd_timing_parameters params = {0};
 486         uint8_t atom_controller_id;
 487
 488         if (bp->cmd_helper->controller_id_to_atom(
 489                         bp_params->controller_id, &atom_controller_id))
 490                 params.crtc_id = atom_controller_id;
 491
 492         /* bios usH_Size wants h addressable size */
 493         params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable);
 494         /* bios usH_Blanking_Time wants borders included in blanking */
 495         params.h_blanking_time =
 496                         cpu_to_le16((uint16_t)(bp_params->h_total -
 497                                         bp_params->h_addressable));
 498         /* bios usV_Size wants v addressable size */
 499         params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable);
 500         /* bios usV_Blanking_Time wants borders included in blanking */
 501         params.v_blanking_time =
 502                         cpu_to_le16((uint16_t)(bp_params->v_total -
 503                                         bp_params->v_addressable));
 504         /* bios usHSyncOffset is the offset from the end of h addressable,
 505          * our horizontalSyncStart is the offset from the beginning
 506          * of h addressable
 507          */
 508         params.h_syncoffset =
 509                         cpu_to_le16((uint16_t)(bp_params->h_sync_start -
 510                                         bp_params->h_addressable));
 511         params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
 512         /* bios usHSyncOffset is the offset from the end of v addressable,
 513          * our verticalSyncStart is the offset from the beginning of
 514          * v addressable
 515          */
 516         params.v_syncoffset =
 517                         cpu_to_le16((uint16_t)(bp_params->v_sync_start -
 518                                         bp_params->v_addressable));
 519         params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
 520
 521         /* we assume that overscan from original timing does not get bigger
 522          * than 255
 523          * we will program all the borders in the Set CRTC Overscan call below
 524          */
 525
 526         if (bp_params->flags.HSYNC_POSITIVE_POLARITY == 0)
 527                 params.modemiscinfo =
 528                                 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 529                                                 ATOM_HSYNC_POLARITY);
 530
 531         if (bp_params->flags.VSYNC_POSITIVE_POLARITY == 0)
 532                 params.modemiscinfo =
 533                                 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 534                                                 ATOM_VSYNC_POLARITY);
 535
 536         if (bp_params->flags.INTERLACE) {
 537                 params.modemiscinfo =
 538                                 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 539                                                 ATOM_INTERLACE);
 540
 541                 /* original DAL code has this condition to apply this
 542                  * for non-TV/CV only
 543                  * due to complex MV testing for possible impact
 544                  * if ( pACParameters->signal != SignalType_YPbPr &&
 545                  *  pACParameters->signal != SignalType_Composite &&
 546                  *  pACParameters->signal != SignalType_SVideo)
 547                  */
 548                 {
 549                         /* HW will deduct 0.5 line from 2nd feild.
 550                          * i.e. for 1080i, it is 2 lines for 1st field,
 551                          * 2.5 lines for the 2nd feild. we need input as 5
 552                          * instead of 4.
 553                          * but it is 4 either from Edid data (spec CEA 861)
 554                          * or CEA timing table.
 555                          */
 556                         params.v_syncoffset =
 557                                 cpu_to_le16(le16_to_cpu(params.v_syncoffset) +
 558                                                 1);
 559
 560                 }
 561         }
 562
 563         if (bp_params->flags.HORZ_COUNT_BY_TWO)
 564                 params.modemiscinfo =
 565                         cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 566                                         0x100); /* ATOM_DOUBLE_CLOCK_MODE */
 567
 568         if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params))
 569                 result = BP_RESULT_OK;
 570
 571         return result;
 572 }
 573
 574 /******************************************************************************
 575  ******************************************************************************
 576  **
 577  **                  ENABLE CRTC
 578  **
 579  ******************************************************************************
 580  *****************************************************************************/
 581
 582 static enum bp_result enable_crtc_v1(
 583         struct bios_parser *bp,
 584         enum controller_id controller_id,
 585         bool enable);
 586
 587 static void init_enable_crtc(struct bios_parser *bp)
 588 {
 589         switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) {
 590         case 1:
 591                 bp->cmd_tbl.enable_crtc = enable_crtc_v1;
 592                 break;
 593         default:
 594                 dm_output_to_console("Don't have enable_crtc for v%d\n",
 595                          BIOS_CMD_TABLE_PARA_REVISION(enablecrtc));
 596                 bp->cmd_tbl.enable_crtc = NULL;
 597                 break;
 598         }
 599 }
 600
 601 static enum bp_result enable_crtc_v1(
 602         struct bios_parser *bp,
 603         enum controller_id controller_id,
 604         bool enable)
 605 {
 606         bool result = BP_RESULT_FAILURE;
 607         struct enable_crtc_parameters params = {0};
 608         uint8_t id;
 609
 610         if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
 611                 params.crtc_id = id;
 612         else
 613                 return BP_RESULT_BADINPUT;
 614
 615         if (enable)
 616                 params.enable = ATOM_ENABLE;
 617         else
 618                 params.enable = ATOM_DISABLE;
 619
 620         if (EXEC_BIOS_CMD_TABLE(enablecrtc, params))
 621                 result = BP_RESULT_OK;
 622
 623         return result;
 624 }
 625
 626 /******************************************************************************
 627  ******************************************************************************
 628  **
 629  **                  DISPLAY PLL
 630  **
 631  ******************************************************************************
 632  *****************************************************************************/
 633
 634
 635
 636 /******************************************************************************
 637  ******************************************************************************
 638  **
 639  **                  EXTERNAL ENCODER CONTROL
 640  **
 641  ******************************************************************************
 642  *****************************************************************************/
 643
 644 static enum bp_result external_encoder_control_v3(
 645         struct bios_parser *bp,
 646         struct bp_external_encoder_control *cntl);
 647
 648 static void init_external_encoder_control(
 649         struct bios_parser *bp)
 650 {
 651         switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) {
 652         case 3:
 653                 bp->cmd_tbl.external_encoder_control =
 654                                 external_encoder_control_v3;
 655                 break;
 656         default:
 657                 bp->cmd_tbl.external_encoder_control = NULL;
 658                 break;
 659         }
 660 }
 661
 662 static enum bp_result external_encoder_control_v3(
 663         struct bios_parser *bp,
 664         struct bp_external_encoder_control *cntl)
 665 {
 666         /* TODO */
 667         return BP_RESULT_OK;
 668 }
 669
 670 /******************************************************************************
 671  ******************************************************************************
 672  **
 673  **                  ENABLE DISPLAY POWER GATING
 674  **
 675  ******************************************************************************
 676  *****************************************************************************/
 677
 678 static enum bp_result enable_disp_power_gating_v2_1(
 679         struct bios_parser *bp,
 680         enum controller_id crtc_id,
 681         enum bp_pipe_control_action action);
 682
 683 static enum bp_result enable_disp_power_gating_fallback(
 684         struct bios_parser *bp,
 685         enum controller_id crtc_id,
 686         enum bp_pipe_control_action action);
 687
 688 static void init_enable_disp_power_gating(
 689         struct bios_parser *bp)
 690 {
 691         switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) {
 692         case 1:
 693                 bp->cmd_tbl.enable_disp_power_gating =
 694                                 enable_disp_power_gating_v2_1;
 695                 break;
 696         default:
 697                 dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n",
 698                          BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating));
 699                 bp->cmd_tbl.enable_disp_power_gating = enable_disp_power_gating_fallback;
 700                 break;
 701         }
 702 }
 703
 704 static void enable_disp_power_gating_dmcub(
 705         struct dc_dmub_srv *dmcub,
 706         struct enable_disp_power_gating_parameters_v2_1 *pwr)
 707 {
 708         struct dmub_rb_cmd_enable_disp_power_gating power_gating;
 709
 710         power_gating.header.type = DMUB_CMD__VBIOS;
 711         power_gating.header.sub_type = DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING;
 712         power_gating.power_gating.pwr = *pwr;
 713
 714         dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
 715         dc_dmub_srv_cmd_execute(dmcub);
 716         dc_dmub_srv_wait_idle(dmcub);
 717 }
 718
 719 static enum bp_result enable_disp_power_gating_v2_1(
 720         struct bios_parser *bp,
 721         enum controller_id crtc_id,
 722         enum bp_pipe_control_action action)
 723 {
 724         enum bp_result result = BP_RESULT_FAILURE;
 725
 726
 727         struct enable_disp_power_gating_ps_allocation ps = { { 0 } };
 728         uint8_t atom_crtc_id;
 729
 730         if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
 731                 ps.param.disp_pipe_id = atom_crtc_id;
 732         else
 733                 return BP_RESULT_BADINPUT;
 734
 735         ps.param.enable =
 736                 bp->cmd_helper->disp_power_gating_action_to_atom(action);
 737
 738         if (bp->base.ctx->dc->ctx->dmub_srv &&
 739             bp->base.ctx->dc->debug.dmub_command_table) {
 740                 enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
 741                                                &ps.param);
 742                 return BP_RESULT_OK;
 743         }
 744
 745         if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
 746                 result = BP_RESULT_OK;
 747
 748         return result;
 749 }
 750
 751 static enum bp_result enable_disp_power_gating_fallback(
 752         struct bios_parser *bp,
 753         enum controller_id crtc_id,
 754         enum bp_pipe_control_action action)
 755 {
 756         if (bp->base.ctx->dc->ctx->dmub_srv &&
 757             bp->base.ctx->dc->debug.dmub_command_table) {
 758                 return enable_disp_power_gating_v2_1(bp, crtc_id, action);
 759         }
 760
 761         return BP_RESULT_FAILURE;
 762 }
 763
 764 /******************************************************************************
 765 *******************************************************************************
 766  **
 767  **                  SET DCE CLOCK
 768  **
 769 *******************************************************************************
 770 *******************************************************************************/
 771
 772 static enum bp_result set_dce_clock_v2_1(
 773         struct bios_parser *bp,
 774         struct bp_set_dce_clock_parameters *bp_params);
 775
 776 static void init_set_dce_clock(struct bios_parser *bp)
 777 {
 778         switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) {
 779         case 1:
 780                 bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
 781                 break;
 782         default:
 783                 dm_output_to_console("Don't have set_dce_clock for v%d\n",
 784                          BIOS_CMD_TABLE_PARA_REVISION(setdceclock));
 785                 bp->cmd_tbl.set_dce_clock = NULL;
 786                 break;
 787         }
 788 }
 789
 790 static enum bp_result set_dce_clock_v2_1(
 791         struct bios_parser *bp,
 792         struct bp_set_dce_clock_parameters *bp_params)
 793 {
 794         enum bp_result result = BP_RESULT_FAILURE;
 795
 796         struct set_dce_clock_ps_allocation_v2_1 params;
 797         uint32_t atom_pll_id;
 798         uint32_t atom_clock_type;
 799         const struct command_table_helper *cmd = bp->cmd_helper;
 800
 801         memset(&params, 0, sizeof(params));
 802
 803         if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
 804                         !cmd->dc_clock_type_to_atom(bp_params->clock_type,
 805                                         &atom_clock_type))
 806                 return BP_RESULT_BADINPUT;
 807
 808         params.param.dceclksrc  = atom_pll_id;
 809         params.param.dceclktype = atom_clock_type;
 810
 811         if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
 812                 if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
 813                         params.param.dceclkflag |=
 814                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
 815
 816                 if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
 817                         params.param.dceclkflag |=
 818                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
 819
 820                 if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
 821                         params.param.dceclkflag |=
 822                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
 823
 824                 if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
 825                         params.param.dceclkflag |=
 826                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
 827         } else
 828                 /* only program clock frequency if display clock is used;
 829                  * VBIOS will program DPREFCLK
 830                  * We need to convert from KHz units into 10KHz units
 831                  */
 832                 params.param.dceclk_10khz = cpu_to_le32(
 833                                 bp_params->target_clock_frequency / 10);
 834         DC_LOG_BIOS("%s:target_clock_frequency = %d"\
 835                         "clock_type = %d \n", __func__,\
 836                         bp_params->target_clock_frequency,\
 837                         bp_params->clock_type);
 838
 839         if (EXEC_BIOS_CMD_TABLE(setdceclock, params)) {
 840                 /* Convert from 10KHz units back to KHz */
 841                 bp_params->target_clock_frequency = le32_to_cpu(
 842                                 params.param.dceclk_10khz) * 10;
 843                 result = BP_RESULT_OK;
 844         }
 845
 846         return result;
 847 }
 848
 849
 850 /******************************************************************************
 851  ******************************************************************************
 852  **
 853  **                  GET SMU CLOCK INFO
 854  **
 855  ******************************************************************************
 856  *****************************************************************************/
 857
 858 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id);
 859
 860 static void init_get_smu_clock_info(struct bios_parser *bp)
 861 {
 862         /* TODO add switch for table vrsion */
 863         bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1;
 864
 865 }
 866
 867 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
 868 {
 869         struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0};
 870         struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output;
 871
 872         smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ;
 873         smu_input.syspll_id = id;
 874
 875         /* Get Specific Clock */
 876         if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) {
 877                 memmove(&smu_output, &smu_input, sizeof(
 878                         struct atom_get_smu_clock_info_parameters_v3_1));
 879                 return smu_output.atom_smu_outputclkfreq.syspllvcofreq_10khz;
 880         }
 881
 882         return 0;
 883 }
 884
 885 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
 886 {
 887         init_dig_encoder_control(bp);
 888         init_transmitter_control(bp);
 889         init_set_pixel_clock(bp);
 890
 891         init_set_crtc_timing(bp);
 892
 893         init_enable_crtc(bp);
 894
 895         init_external_encoder_control(bp);
 896         init_enable_disp_power_gating(bp);
 897         init_set_dce_clock(bp);
 898         init_get_smu_clock_info(bp);
 899
 900 }