drivers/gpu/drm/amd/display/dc/bios/command_table2.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "ObjectID.h"
  29
  30 #include "atomfirmware.h"
  31 #include "atom.h"
  32 #include "include/bios_parser_interface.h"
  33
  34 #include "command_table2.h"
  35 #include "command_table_helper2.h"
  36 #include "bios_parser_helper.h"
  37 #include "bios_parser_types_internal2.h"
  38 #include "amdgpu.h"
  39
  40 #ifdef CONFIG_DRM_AMD_DC_DMUB
  41 #include "dc_dmub_srv.h"
  42 #include "dc.h"
  43 #endif
  44
  45 #define DC_LOGGER \
  46         bp->base.ctx->logger
  47
  48 #define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
  49         (((char *)(&((\
  50                 struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\
  51                 ->FieldName)-(char *)0)/sizeof(uint16_t))
  52
  53 #define EXEC_BIOS_CMD_TABLE(fname, params)\
  54         (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
  55                 GET_INDEX_INTO_MASTER_TABLE(command, fname), \
  56                 (uint32_t *)&params) == 0)
  57
  58 #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
  59         amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
  60                 GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
  61
  62 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\
  63         bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
  64                         GET_INDEX_INTO_MASTER_TABLE(command, fname))
  65
  66
  67
  68 static uint32_t bios_cmd_table_para_revision(void *dev,
  69                                              uint32_t index)
  70 {
  71         struct amdgpu_device *adev = dev;
  72         uint8_t frev, crev;
  73
  74         if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
  75                                         index,
  76                                         &frev, &crev))
  77                 return crev;
  78         else
  79                 return 0;
  80 }
  81
  82 /******************************************************************************
  83  ******************************************************************************
  84  **
  85  **                  D I G E N C O D E R C O N T R O L
  86  **
  87  ******************************************************************************
  88  *****************************************************************************/
  89
  90 static enum bp_result encoder_control_digx_v1_5(
  91         struct bios_parser *bp,
  92         struct bp_encoder_control *cntl);
  93
  94 static void init_dig_encoder_control(struct bios_parser *bp)
  95 {
  96         uint32_t version =
  97                 BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol);
  98
  99         switch (version) {
 100         case 5:
 101                 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;
 102                 break;
 103         default:
 104                 dm_output_to_console("Don't have dig_encoder_control for v%d\n", version);
 105                 bp->cmd_tbl.dig_encoder_control = NULL;
 106                 break;
 107         }
 108 }
 109
 110 #ifdef CONFIG_DRM_AMD_DC_DMUB
 111 static void encoder_control_dmcub(
 112                 struct dc_dmub_srv *dmcub,
 113                 struct dig_encoder_stream_setup_parameters_v1_5 *dig)
 114 {
 115         struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 };
 116
 117         encoder_control.header.type = DMUB_CMD__DIGX_ENCODER_CONTROL;
 118         encoder_control.encoder_control.dig.stream_param = *dig;
 119
 120         dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header);
 121         dc_dmub_srv_cmd_execute(dmcub);
 122         dc_dmub_srv_wait_idle(dmcub);
 123 }
 124 #endif
 125 static enum bp_result encoder_control_digx_v1_5(
 126         struct bios_parser *bp,
 127         struct bp_encoder_control *cntl)
 128 {
 129         enum bp_result result = BP_RESULT_FAILURE;
 130         struct dig_encoder_stream_setup_parameters_v1_5 params = {0};
 131
 132         params.digid = (uint8_t)(cntl->engine_id);
 133         params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
 134
 135         params.pclk_10khz = cntl->pixel_clock / 10;
 136         params.digmode =
 137                         (uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
 138                                         cntl->signal,
 139                                         cntl->enable_dp_audio));
 140         params.lanenum = (uint8_t)(cntl->lanes_number);
 141
 142         switch (cntl->color_depth) {
 143         case COLOR_DEPTH_888:
 144                 params.bitpercolor = PANEL_8BIT_PER_COLOR;
 145                 break;
 146         case COLOR_DEPTH_101010:
 147                 params.bitpercolor = PANEL_10BIT_PER_COLOR;
 148                 break;
 149         case COLOR_DEPTH_121212:
 150                 params.bitpercolor = PANEL_12BIT_PER_COLOR;
 151                 break;
 152         case COLOR_DEPTH_161616:
 153                 params.bitpercolor = PANEL_16BIT_PER_COLOR;
 154                 break;
 155         default:
 156                 break;
 157         }
 158
 159         if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
 160                 switch (cntl->color_depth) {
 161                 case COLOR_DEPTH_101010:
 162                         params.pclk_10khz =
 163                                 (params.pclk_10khz * 30) / 24;
 164                         break;
 165                 case COLOR_DEPTH_121212:
 166                         params.pclk_10khz =
 167                                 (params.pclk_10khz * 36) / 24;
 168                         break;
 169                 case COLOR_DEPTH_161616:
 170                         params.pclk_10khz =
 171                                 (params.pclk_10khz * 48) / 24;
 172                         break;
 173                 default:
 174                         break;
 175                 }
 176 #ifdef CONFIG_DRM_AMD_DC_DMUB
 177         if (bp->base.ctx->dc->ctx->dmub_srv &&
 178             bp->base.ctx->dc->debug.dmub_command_table) {
 179                 encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
 180                 return BP_RESULT_OK;
 181         }
 182 #endif
 183
 184         if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
 185                 result = BP_RESULT_OK;
 186
 187         return result;
 188 }
 189
 190 /*****************************************************************************
 191  ******************************************************************************
 192  **
 193  **                  TRANSMITTER CONTROL
 194  **
 195  ******************************************************************************
 196  *****************************************************************************/
 197
 198 static enum bp_result transmitter_control_v1_6(
 199         struct bios_parser *bp,
 200         struct bp_transmitter_control *cntl);
 201
 202 static void init_transmitter_control(struct bios_parser *bp)
 203 {
 204         uint8_t frev;
 205         uint8_t crev;
 206
 207         if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) == false)
 208                 BREAK_TO_DEBUGGER();
 209         switch (crev) {
 210         case 6:
 211                 bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
 212                 break;
 213         default:
 214                 dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
 215                 bp->cmd_tbl.transmitter_control = NULL;
 216                 break;
 217         }
 218 }
 219 #ifdef CONFIG_DRM_AMD_DC_DMUB
 220 static void transmitter_control_dmcub(
 221                 struct dc_dmub_srv *dmcub,
 222                 struct dig_transmitter_control_parameters_v1_6 *dig)
 223 {
 224         struct dmub_rb_cmd_dig1_transmitter_control transmitter_control;
 225
 226         transmitter_control.header.type = DMUB_CMD__DIG1_TRANSMITTER_CONTROL;
 227         transmitter_control.transmitter_control.dig = *dig;
 228
 229         dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header);
 230         dc_dmub_srv_cmd_execute(dmcub);
 231         dc_dmub_srv_wait_idle(dmcub);
 232 }
 233 #endif
 234 static enum bp_result transmitter_control_v1_6(
 235         struct bios_parser *bp,
 236         struct bp_transmitter_control *cntl)
 237 {
 238         enum bp_result result = BP_RESULT_FAILURE;
 239         const struct command_table_helper *cmd = bp->cmd_helper;
 240         struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } };
 241
 242         ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter);
 243         ps.param.action = (uint8_t)cntl->action;
 244
 245         if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
 246                 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
 247         else
 248                 ps.param.mode_laneset.digmode =
 249                                 cmd->signal_type_to_atom_dig_mode(cntl->signal);
 250
 251         ps.param.lanenum = (uint8_t)cntl->lanes_number;
 252         ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
 253         ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
 254         ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;
 255         ps.param.symclk_10khz = cntl->pixel_clock/10;
 256
 257
 258         if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
 259                 cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
 260                 cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
 261                 DC_LOG_BIOS("%s:ps.param.symclk_10khz = %d\n",\
 262                 __func__, ps.param.symclk_10khz);
 263         }
 264
 265
 266 #ifdef CONFIG_DRM_AMD_DC_DMUB
 267         if (bp->base.ctx->dc->ctx->dmub_srv &&
 268             bp->base.ctx->dc->debug.dmub_command_table) {
 269                 transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
 270                 return BP_RESULT_OK;
 271         }
 272 #endif
 273
 274 /*color_depth not used any more, driver has deep color factor in the Phyclk*/
 275         if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
 276                 result = BP_RESULT_OK;
 277         return result;
 278 }
 279
 280 /******************************************************************************
 281  ******************************************************************************
 282  **
 283  **                  SET PIXEL CLOCK
 284  **
 285  ******************************************************************************
 286  *****************************************************************************/
 287
 288 static enum bp_result set_pixel_clock_v7(
 289         struct bios_parser *bp,
 290         struct bp_pixel_clock_parameters *bp_params);
 291
 292 static void init_set_pixel_clock(struct bios_parser *bp)
 293 {
 294         switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
 295         case 7:
 296                 bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
 297                 break;
 298         default:
 299                 dm_output_to_console("Don't have set_pixel_clock for v%d\n",
 300                          BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));
 301                 bp->cmd_tbl.set_pixel_clock = NULL;
 302                 break;
 303         }
 304 }
 305
 306 #ifdef CONFIG_DRM_AMD_DC_DMUB
 307 static void set_pixel_clock_dmcub(
 308                 struct dc_dmub_srv *dmcub,
 309                 struct set_pixel_clock_parameter_v1_7 *clk)
 310 {
 311         struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 };
 312
 313         pixel_clock.header.type     = DMUB_CMD__SET_PIXEL_CLOCK;
 314         pixel_clock.pixel_clock.clk = *clk;
 315
 316         dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header);
 317         dc_dmub_srv_cmd_execute(dmcub);
 318         dc_dmub_srv_wait_idle(dmcub);
 319 }
 320 #endif
 321
 322 static enum bp_result set_pixel_clock_v7(
 323         struct bios_parser *bp,
 324         struct bp_pixel_clock_parameters *bp_params)
 325 {
 326         enum bp_result result = BP_RESULT_FAILURE;
 327         struct set_pixel_clock_parameter_v1_7 clk;
 328         uint8_t controller_id;
 329         uint32_t pll_id;
 330
 331         memset(&clk, 0, sizeof(clk));
 332
 333         if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
 334                         && bp->cmd_helper->controller_id_to_atom(bp_params->
 335                                         controller_id, &controller_id)) {
 336                 /* Note: VBIOS still wants to use ucCRTC name which is now
 337                  * 1 byte in ULONG
 338                  *typedef struct _CRTC_PIXEL_CLOCK_FREQ
 339                  *{
 340                  * target the pixel clock to drive the CRTC timing.
 341                  * ULONG ulPixelClock:24;
 342                  * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
 343                  * previous version.
 344                  * ATOM_CRTC1~6, indicate the CRTC controller to
 345                  * ULONG ucCRTC:8;
 346                  * drive the pixel clock. not used for DCPLL case.
 347                  *}CRTC_PIXEL_CLOCK_FREQ;
 348                  *union
 349                  *{
 350                  * pixel clock and CRTC id frequency
 351                  * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
 352                  * ULONG ulDispEngClkFreq; dispclk frequency
 353                  *};
 354                  */
 355                 clk.crtc_id = controller_id;
 356                 clk.pll_id = (uint8_t) pll_id;
 357                 clk.encoderobjid =
 358                         bp->cmd_helper->encoder_id_to_atom(
 359                                 dal_graphics_object_id_get_encoder_id(
 360                                         bp_params->encoder_object_id));
 361
 362                 clk.encoder_mode = (uint8_t) bp->
 363                         cmd_helper->encoder_mode_bp_to_atom(
 364                                 bp_params->signal_type, false);
 365
 366                 clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);
 367
 368                 clk.deep_color_ratio =
 369                         (uint8_t) bp->cmd_helper->
 370                                 transmitter_color_depth_to_atom(
 371                                         bp_params->color_depth);
 372
 373                 DC_LOG_BIOS("%s:program display clock = %d, tg = %d, pll = %d, "\
 374                                 "colorDepth = %d\n", __func__,
 375                                 bp_params->target_pixel_clock_100hz, (int)controller_id,
 376                                 pll_id, bp_params->color_depth);
 377
 378                 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
 379                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
 380
 381                 if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
 382                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
 383
 384                 if (bp_params->flags.SUPPORT_YUV_420)
 385                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
 386
 387                 if (bp_params->flags.SET_XTALIN_REF_SRC)
 388                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
 389
 390                 if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
 391                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
 392
 393                 if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
 394                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
 395
 396 #ifdef CONFIG_DRM_AMD_DC_DMUB
 397                 if (bp->base.ctx->dc->ctx->dmub_srv &&
 398                     bp->base.ctx->dc->debug.dmub_command_table) {
 399                         set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
 400                         return BP_RESULT_OK;
 401                 }
 402 #endif
 403                 if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
 404                         result = BP_RESULT_OK;
 405         }
 406         return result;
 407 }
 408
 409 /******************************************************************************
 410  ******************************************************************************
 411  **
 412  **                  SET CRTC TIMING
 413  **
 414  ******************************************************************************
 415  *****************************************************************************/
 416
 417 static enum bp_result set_crtc_using_dtd_timing_v3(
 418         struct bios_parser *bp,
 419         struct bp_hw_crtc_timing_parameters *bp_params);
 420
 421 static void init_set_crtc_timing(struct bios_parser *bp)
 422 {
 423         uint32_t dtd_version =
 424                         BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
 425
 426         switch (dtd_version) {
 427         case 3:
 428                 bp->cmd_tbl.set_crtc_timing =
 429                         set_crtc_using_dtd_timing_v3;
 430                 break;
 431         default:
 432                 dm_output_to_console("Don't have set_crtc_timing for v%d\n", dtd_version);
 433                 bp->cmd_tbl.set_crtc_timing = NULL;
 434                 break;
 435         }
 436 }
 437
 438 static enum bp_result set_crtc_using_dtd_timing_v3(
 439         struct bios_parser *bp,
 440         struct bp_hw_crtc_timing_parameters *bp_params)
 441 {
 442         enum bp_result result = BP_RESULT_FAILURE;
 443         struct set_crtc_using_dtd_timing_parameters params = {0};
 444         uint8_t atom_controller_id;
 445
 446         if (bp->cmd_helper->controller_id_to_atom(
 447                         bp_params->controller_id, &atom_controller_id))
 448                 params.crtc_id = atom_controller_id;
 449
 450         /* bios usH_Size wants h addressable size */
 451         params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable);
 452         /* bios usH_Blanking_Time wants borders included in blanking */
 453         params.h_blanking_time =
 454                         cpu_to_le16((uint16_t)(bp_params->h_total -
 455                                         bp_params->h_addressable));
 456         /* bios usV_Size wants v addressable size */
 457         params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable);
 458         /* bios usV_Blanking_Time wants borders included in blanking */
 459         params.v_blanking_time =
 460                         cpu_to_le16((uint16_t)(bp_params->v_total -
 461                                         bp_params->v_addressable));
 462         /* bios usHSyncOffset is the offset from the end of h addressable,
 463          * our horizontalSyncStart is the offset from the beginning
 464          * of h addressable
 465          */
 466         params.h_syncoffset =
 467                         cpu_to_le16((uint16_t)(bp_params->h_sync_start -
 468                                         bp_params->h_addressable));
 469         params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
 470         /* bios usHSyncOffset is the offset from the end of v addressable,
 471          * our verticalSyncStart is the offset from the beginning of
 472          * v addressable
 473          */
 474         params.v_syncoffset =
 475                         cpu_to_le16((uint16_t)(bp_params->v_sync_start -
 476                                         bp_params->v_addressable));
 477         params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
 478
 479         /* we assume that overscan from original timing does not get bigger
 480          * than 255
 481          * we will program all the borders in the Set CRTC Overscan call below
 482          */
 483
 484         if (bp_params->flags.HSYNC_POSITIVE_POLARITY == 0)
 485                 params.modemiscinfo =
 486                                 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 487                                                 ATOM_HSYNC_POLARITY);
 488
 489         if (bp_params->flags.VSYNC_POSITIVE_POLARITY == 0)
 490                 params.modemiscinfo =
 491                                 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 492                                                 ATOM_VSYNC_POLARITY);
 493
 494         if (bp_params->flags.INTERLACE) {
 495                 params.modemiscinfo =
 496                                 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 497                                                 ATOM_INTERLACE);
 498
 499                 /* original DAL code has this condition to apply this
 500                  * for non-TV/CV only
 501                  * due to complex MV testing for possible impact
 502                  * if ( pACParameters->signal != SignalType_YPbPr &&
 503                  *  pACParameters->signal != SignalType_Composite &&
 504                  *  pACParameters->signal != SignalType_SVideo)
 505                  */
 506                 {
 507                         /* HW will deduct 0.5 line from 2nd feild.
 508                          * i.e. for 1080i, it is 2 lines for 1st field,
 509                          * 2.5 lines for the 2nd feild. we need input as 5
 510                          * instead of 4.
 511                          * but it is 4 either from Edid data (spec CEA 861)
 512                          * or CEA timing table.
 513                          */
 514                         params.v_syncoffset =
 515                                 cpu_to_le16(le16_to_cpu(params.v_syncoffset) +
 516                                                 1);
 517
 518                 }
 519         }
 520
 521         if (bp_params->flags.HORZ_COUNT_BY_TWO)
 522                 params.modemiscinfo =
 523                         cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
 524                                         0x100); /* ATOM_DOUBLE_CLOCK_MODE */
 525
 526         if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params))
 527                 result = BP_RESULT_OK;
 528
 529         return result;
 530 }
 531
 532 /******************************************************************************
 533  ******************************************************************************
 534  **
 535  **                  ENABLE CRTC
 536  **
 537  ******************************************************************************
 538  *****************************************************************************/
 539
 540 static enum bp_result enable_crtc_v1(
 541         struct bios_parser *bp,
 542         enum controller_id controller_id,
 543         bool enable);
 544
 545 static void init_enable_crtc(struct bios_parser *bp)
 546 {
 547         switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) {
 548         case 1:
 549                 bp->cmd_tbl.enable_crtc = enable_crtc_v1;
 550                 break;
 551         default:
 552                 dm_output_to_console("Don't have enable_crtc for v%d\n",
 553                          BIOS_CMD_TABLE_PARA_REVISION(enablecrtc));
 554                 bp->cmd_tbl.enable_crtc = NULL;
 555                 break;
 556         }
 557 }
 558
 559 static enum bp_result enable_crtc_v1(
 560         struct bios_parser *bp,
 561         enum controller_id controller_id,
 562         bool enable)
 563 {
 564         bool result = BP_RESULT_FAILURE;
 565         struct enable_crtc_parameters params = {0};
 566         uint8_t id;
 567
 568         if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
 569                 params.crtc_id = id;
 570         else
 571                 return BP_RESULT_BADINPUT;
 572
 573         if (enable)
 574                 params.enable = ATOM_ENABLE;
 575         else
 576                 params.enable = ATOM_DISABLE;
 577
 578         if (EXEC_BIOS_CMD_TABLE(enablecrtc, params))
 579                 result = BP_RESULT_OK;
 580
 581         return result;
 582 }
 583
 584 /******************************************************************************
 585  ******************************************************************************
 586  **
 587  **                  DISPLAY PLL
 588  **
 589  ******************************************************************************
 590  *****************************************************************************/
 591
 592
 593
 594 /******************************************************************************
 595  ******************************************************************************
 596  **
 597  **                  EXTERNAL ENCODER CONTROL
 598  **
 599  ******************************************************************************
 600  *****************************************************************************/
 601
 602 static enum bp_result external_encoder_control_v3(
 603         struct bios_parser *bp,
 604         struct bp_external_encoder_control *cntl);
 605
 606 static void init_external_encoder_control(
 607         struct bios_parser *bp)
 608 {
 609         switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) {
 610         case 3:
 611                 bp->cmd_tbl.external_encoder_control =
 612                                 external_encoder_control_v3;
 613                 break;
 614         default:
 615                 bp->cmd_tbl.external_encoder_control = NULL;
 616                 break;
 617         }
 618 }
 619
 620 static enum bp_result external_encoder_control_v3(
 621         struct bios_parser *bp,
 622         struct bp_external_encoder_control *cntl)
 623 {
 624         /* TODO */
 625         return BP_RESULT_OK;
 626 }
 627
 628 /******************************************************************************
 629  ******************************************************************************
 630  **
 631  **                  ENABLE DISPLAY POWER GATING
 632  **
 633  ******************************************************************************
 634  *****************************************************************************/
 635
 636 static enum bp_result enable_disp_power_gating_v2_1(
 637         struct bios_parser *bp,
 638         enum controller_id crtc_id,
 639         enum bp_pipe_control_action action);
 640
 641 static void init_enable_disp_power_gating(
 642         struct bios_parser *bp)
 643 {
 644         switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) {
 645         case 1:
 646                 bp->cmd_tbl.enable_disp_power_gating =
 647                                 enable_disp_power_gating_v2_1;
 648                 break;
 649         default:
 650                 dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n",
 651                          BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating));
 652                 bp->cmd_tbl.enable_disp_power_gating = NULL;
 653                 break;
 654         }
 655 }
 656 #ifdef CONFIG_DRM_AMD_DC_DMUB
 657 static void enable_disp_power_gating_dmcub(
 658         struct dc_dmub_srv *dmcub,
 659         struct enable_disp_power_gating_parameters_v2_1 *pwr)
 660 {
 661         struct dmub_rb_cmd_enable_disp_power_gating power_gating;
 662
 663         power_gating.header.type      = DMUB_CMD__ENABLE_DISP_POWER_GATING;
 664         power_gating.power_gating.pwr = *pwr;
 665
 666         dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
 667         dc_dmub_srv_cmd_execute(dmcub);
 668         dc_dmub_srv_wait_idle(dmcub);
 669 }
 670 #endif
 671 static enum bp_result enable_disp_power_gating_v2_1(
 672         struct bios_parser *bp,
 673         enum controller_id crtc_id,
 674         enum bp_pipe_control_action action)
 675 {
 676         enum bp_result result = BP_RESULT_FAILURE;
 677
 678
 679         struct enable_disp_power_gating_ps_allocation ps = { { 0 } };
 680         uint8_t atom_crtc_id;
 681
 682         if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
 683                 ps.param.disp_pipe_id = atom_crtc_id;
 684         else
 685                 return BP_RESULT_BADINPUT;
 686
 687         ps.param.enable =
 688                 bp->cmd_helper->disp_power_gating_action_to_atom(action);
 689
 690 #ifdef CONFIG_DRM_AMD_DC_DMUB
 691         if (bp->base.ctx->dc->ctx->dmub_srv &&
 692             bp->base.ctx->dc->debug.dmub_command_table) {
 693                 enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
 694                                                &ps.param);
 695                 return BP_RESULT_OK;
 696         }
 697 #endif
 698         if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
 699                 result = BP_RESULT_OK;
 700
 701         return result;
 702 }
 703
 704 /******************************************************************************
 705 *******************************************************************************
 706  **
 707  **                  SET DCE CLOCK
 708  **
 709 *******************************************************************************
 710 *******************************************************************************/
 711
 712 static enum bp_result set_dce_clock_v2_1(
 713         struct bios_parser *bp,
 714         struct bp_set_dce_clock_parameters *bp_params);
 715
 716 static void init_set_dce_clock(struct bios_parser *bp)
 717 {
 718         switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) {
 719         case 1:
 720                 bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
 721                 break;
 722         default:
 723                 dm_output_to_console("Don't have set_dce_clock for v%d\n",
 724                          BIOS_CMD_TABLE_PARA_REVISION(setdceclock));
 725                 bp->cmd_tbl.set_dce_clock = NULL;
 726                 break;
 727         }
 728 }
 729
 730 static enum bp_result set_dce_clock_v2_1(
 731         struct bios_parser *bp,
 732         struct bp_set_dce_clock_parameters *bp_params)
 733 {
 734         enum bp_result result = BP_RESULT_FAILURE;
 735
 736         struct set_dce_clock_ps_allocation_v2_1 params;
 737         uint32_t atom_pll_id;
 738         uint32_t atom_clock_type;
 739         const struct command_table_helper *cmd = bp->cmd_helper;
 740
 741         memset(&params, 0, sizeof(params));
 742
 743         if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
 744                         !cmd->dc_clock_type_to_atom(bp_params->clock_type,
 745                                         &atom_clock_type))
 746                 return BP_RESULT_BADINPUT;
 747
 748         params.param.dceclksrc  = atom_pll_id;
 749         params.param.dceclktype = atom_clock_type;
 750
 751         if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
 752                 if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
 753                         params.param.dceclkflag |=
 754                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
 755
 756                 if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
 757                         params.param.dceclkflag |=
 758                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
 759
 760                 if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
 761                         params.param.dceclkflag |=
 762                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
 763
 764                 if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
 765                         params.param.dceclkflag |=
 766                                         DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
 767         } else
 768                 /* only program clock frequency if display clock is used;
 769                  * VBIOS will program DPREFCLK
 770                  * We need to convert from KHz units into 10KHz units
 771                  */
 772                 params.param.dceclk_10khz = cpu_to_le32(
 773                                 bp_params->target_clock_frequency / 10);
 774         DC_LOG_BIOS("%s:target_clock_frequency = %d"\
 775                         "clock_type = %d \n", __func__,\
 776                         bp_params->target_clock_frequency,\
 777                         bp_params->clock_type);
 778
 779         if (EXEC_BIOS_CMD_TABLE(setdceclock, params)) {
 780                 /* Convert from 10KHz units back to KHz */
 781                 bp_params->target_clock_frequency = le32_to_cpu(
 782                                 params.param.dceclk_10khz) * 10;
 783                 result = BP_RESULT_OK;
 784         }
 785
 786         return result;
 787 }
 788
 789
 790 /******************************************************************************
 791  ******************************************************************************
 792  **
 793  **                  GET SMU CLOCK INFO
 794  **
 795  ******************************************************************************
 796  *****************************************************************************/
 797
 798 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id);
 799
 800 static void init_get_smu_clock_info(struct bios_parser *bp)
 801 {
 802         /* TODO add switch for table vrsion */
 803         bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1;
 804
 805 }
 806
 807 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
 808 {
 809         struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0};
 810         struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output;
 811
 812         smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ;
 813         smu_input.syspll_id = id;
 814
 815         /* Get Specific Clock */
 816         if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) {
 817                 memmove(&smu_output, &smu_input, sizeof(
 818                         struct atom_get_smu_clock_info_parameters_v3_1));
 819                 return smu_output.atom_smu_outputclkfreq.syspllvcofreq_10khz;
 820         }
 821
 822         return 0;
 823 }
 824
 825 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
 826 {
 827         init_dig_encoder_control(bp);
 828         init_transmitter_control(bp);
 829         init_set_pixel_clock(bp);
 830
 831         init_set_crtc_timing(bp);
 832
 833         init_enable_crtc(bp);
 834
 835         init_external_encoder_control(bp);
 836         init_enable_disp_power_gating(bp);
 837         init_set_dce_clock(bp);
 838         init_get_smu_clock_info(bp);
 839
 840 }