2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
31 #include "atomfirmware.h"
33 #include "dc_bios_types.h"
34 #include "include/grph_object_ctrl_defs.h"
35 #include "include/bios_parser_interface.h"
36 #include "include/i2caux_interface.h"
37 #include "include/logger_interface.h"
39 #include "command_table2.h"
41 #include "bios_parser_helper.h"
42 #include "command_table_helper2.h"
43 #include "bios_parser2.h"
44 #include "bios_parser_types_internal2.h"
45 #include "bios_parser_interface.h"
47 #include "bios_parser_common.h"
49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
71 #define LAST_RECORD_TYPE 0xff
72 #define SMU9_SYSPLL0_ID 0
74 struct i2c_id_config_access {
75 uint8_t bfI2C_LineMux:4;
76 uint8_t bfHW_EngineID:3;
77 uint8_t bfHW_Capable:1;
81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
82 struct atom_i2c_record *record,
83 struct graphics_object_i2c_info *info);
85 static enum bp_result bios_parser_get_firmware_info(
87 struct dc_firmware_info *info);
89 static enum bp_result bios_parser_get_encoder_cap_info(
91 struct graphics_object_id object_id,
92 struct bp_encoder_cap_info *info);
94 static enum bp_result get_firmware_info_v3_1(
95 struct bios_parser *bp,
96 struct dc_firmware_info *info);
98 static enum bp_result get_firmware_info_v3_2(
99 struct bios_parser *bp,
100 struct dc_firmware_info *info);
102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
103 struct atom_display_object_path_v2 *object);
105 static struct atom_encoder_caps_record *get_encoder_cap_record(
106 struct bios_parser *bp,
107 struct atom_display_object_path_v2 *object);
109 #define BIOS_IMAGE_SIZE_OFFSET 2
110 #define BIOS_IMAGE_SIZE_UNIT 512
112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
114 static void bios_parser2_destruct(struct bios_parser *bp)
116 kfree(bp->base.bios_local_image);
117 kfree(bp->base.integrated_info);
120 static void firmware_parser_destroy(struct dc_bios **dcb)
122 struct bios_parser *bp = BP_FROM_DCB(*dcb);
129 bios_parser2_destruct(bp);
135 static void get_atom_data_table_revision(
136 struct atom_common_table_header *atom_data_tbl,
137 struct atom_data_revision *tbl_revision)
142 /* initialize the revision to 0 which is invalid revision */
143 tbl_revision->major = 0;
144 tbl_revision->minor = 0;
149 tbl_revision->major =
150 (uint32_t) atom_data_tbl->format_revision & 0x3f;
151 tbl_revision->minor =
152 (uint32_t) atom_data_tbl->content_revision & 0x3f;
155 /* BIOS oject table displaypath is per connector.
156 * There is extra path not for connector. BIOS fill its encoderid as 0
158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
160 struct bios_parser *bp = BP_FROM_DCB(dcb);
161 unsigned int count = 0;
164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
171 static struct graphics_object_id bios_parser_get_connector_id(
175 struct bios_parser *bp = BP_FROM_DCB(dcb);
176 struct graphics_object_id object_id = dal_graphics_object_id_init(
177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
178 struct object_info_table *tbl = &bp->object_info_tbl;
179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
181 if (v1_4->number_of_path > i) {
182 /* If display_objid is generic object id, the encoderObj
183 * /extencoderobjId should be 0
185 if (v1_4->display_path[i].encoderobjid != 0 &&
186 v1_4->display_path[i].display_objid != 0)
187 object_id = object_id_from_bios_object_id(
188 v1_4->display_path[i].display_objid);
194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
195 struct graphics_object_id object_id, uint32_t index,
196 struct graphics_object_id *src_object_id)
198 struct bios_parser *bp = BP_FROM_DCB(dcb);
200 enum bp_result bp_result = BP_RESULT_BADINPUT;
201 struct graphics_object_id obj_id = {0};
202 struct object_info_table *tbl = &bp->object_info_tbl;
207 switch (object_id.type) {
208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
211 case OBJECT_TYPE_ENCODER:
212 /* TODO: since num of src must be less than 2.
213 * If found in for loop, should break.
214 * DAL2 implementation may be changed too
216 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
217 obj_id = object_id_from_bios_object_id(
218 tbl->v1_4->display_path[i].encoderobjid);
219 if (object_id.type == obj_id.type &&
220 object_id.id == obj_id.id &&
224 object_id_from_bios_object_id(0x1100);
228 bp_result = BP_RESULT_OK;
230 case OBJECT_TYPE_CONNECTOR:
231 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
232 obj_id = object_id_from_bios_object_id(
233 tbl->v1_4->display_path[i].display_objid);
235 if (object_id.type == obj_id.type &&
236 object_id.id == obj_id.id &&
237 object_id.enum_id == obj_id.enum_id) {
239 object_id_from_bios_object_id(
240 tbl->v1_4->display_path[i].encoderobjid);
244 bp_result = BP_RESULT_OK;
253 /* from graphics_object_id, find display path which includes the object_id */
254 static struct atom_display_object_path_v2 *get_bios_object(
255 struct bios_parser *bp,
256 struct graphics_object_id id)
259 struct graphics_object_id obj_id = {0};
262 case OBJECT_TYPE_ENCODER:
263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
264 obj_id = object_id_from_bios_object_id(
265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
266 if (id.type == obj_id.type && id.id == obj_id.id
267 && id.enum_id == obj_id.enum_id)
268 return &bp->object_info_tbl.v1_4->display_path[i];
271 case OBJECT_TYPE_CONNECTOR:
272 case OBJECT_TYPE_GENERIC:
273 /* Both Generic and Connector Object ID
274 * will be stored on display_objid
276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
277 obj_id = object_id_from_bios_object_id(
278 bp->object_info_tbl.v1_4->display_path[i].display_objid);
279 if (id.type == obj_id.type && id.id == obj_id.id
280 && id.enum_id == obj_id.enum_id)
281 return &bp->object_info_tbl.v1_4->display_path[i];
289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
290 struct graphics_object_id id,
291 struct graphics_object_i2c_info *info)
294 struct atom_display_object_path_v2 *object;
295 struct atom_common_record_header *header;
296 struct atom_i2c_record *record;
297 struct atom_i2c_record dummy_record = {0};
298 struct bios_parser *bp = BP_FROM_DCB(dcb);
301 return BP_RESULT_BADINPUT;
303 if (id.type == OBJECT_TYPE_GENERIC) {
304 dummy_record.i2c_id = id.id;
306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
309 return BP_RESULT_NORECORD;
312 object = get_bios_object(bp, id);
315 return BP_RESULT_BADINPUT;
317 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
320 header = GET_IMAGE(struct atom_common_record_header, offset);
323 return BP_RESULT_BADBIOSTABLE;
325 if (header->record_type == LAST_RECORD_TYPE ||
326 !header->record_size)
329 if (header->record_type == ATOM_I2C_RECORD_TYPE
330 && sizeof(struct atom_i2c_record) <=
331 header->record_size) {
332 /* get the I2C info */
333 record = (struct atom_i2c_record *) header;
335 if (get_gpio_i2c_info(bp, record, info) ==
340 offset += header->record_size;
343 return BP_RESULT_NORECORD;
346 static enum bp_result get_gpio_i2c_info(
347 struct bios_parser *bp,
348 struct atom_i2c_record *record,
349 struct graphics_object_i2c_info *info)
351 struct atom_gpio_pin_lut_v2_1 *header;
353 unsigned int table_index = 0;
354 bool find_valid = false;
357 return BP_RESULT_BADINPUT;
359 /* get the GPIO_I2C info */
360 if (!DATA_TABLES(gpio_pin_lut))
361 return BP_RESULT_BADBIOSTABLE;
363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
364 DATA_TABLES(gpio_pin_lut));
366 return BP_RESULT_BADBIOSTABLE;
368 if (sizeof(struct atom_common_table_header) +
369 sizeof(struct atom_gpio_pin_assignment) >
370 le16_to_cpu(header->table_header.structuresize))
371 return BP_RESULT_BADBIOSTABLE;
373 /* TODO: is version change? */
374 if (header->table_header.content_revision != 1)
375 return BP_RESULT_UNSUPPORTED;
378 count = (le16_to_cpu(header->table_header.structuresize)
379 - sizeof(struct atom_common_table_header))
380 / sizeof(struct atom_gpio_pin_assignment);
382 for (table_index = 0; table_index < count; table_index++) {
383 if (((record->i2c_id & I2C_HW_CAP) == (
384 header->gpio_pin[table_index].gpio_id &
386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
387 (header->gpio_pin[table_index].gpio_id &
388 I2C_HW_ENGINE_ID_MASK)) &&
389 ((record->i2c_id & I2C_HW_LANE_MUX) ==
390 (header->gpio_pin[table_index].gpio_id &
398 /* If we don't find the entry that we are looking for then
399 * we will return BP_Result_BadBiosTable.
401 if (find_valid == false)
402 return BP_RESULT_BADBIOSTABLE;
404 /* get the GPIO_I2C_INFO */
405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
408 info->i2c_slave_address = record->i2c_slave_addr;
410 /* TODO: check how to get register offset for en, Y, etc. */
411 info->gpio_info.clk_a_register_index =
413 header->gpio_pin[table_index].data_a_reg_index);
414 info->gpio_info.clk_a_shift =
415 header->gpio_pin[table_index].gpio_bitshift;
420 static enum bp_result bios_parser_get_hpd_info(
422 struct graphics_object_id id,
423 struct graphics_object_hpd_info *info)
425 struct bios_parser *bp = BP_FROM_DCB(dcb);
426 struct atom_display_object_path_v2 *object;
427 struct atom_hpd_int_record *record = NULL;
430 return BP_RESULT_BADINPUT;
432 object = get_bios_object(bp, id);
435 return BP_RESULT_BADINPUT;
437 record = get_hpd_record(bp, object);
439 if (record != NULL) {
440 info->hpd_int_gpio_uid = record->pin_id;
441 info->hpd_active = record->plugin_pin_state;
445 return BP_RESULT_NORECORD;
448 static struct atom_hpd_int_record *get_hpd_record(
449 struct bios_parser *bp,
450 struct atom_display_object_path_v2 *object)
452 struct atom_common_record_header *header;
456 BREAK_TO_DEBUGGER(); /* Invalid object */
460 offset = le16_to_cpu(object->disp_recordoffset)
461 + bp->object_info_tbl_offset;
464 header = GET_IMAGE(struct atom_common_record_header, offset);
469 if (header->record_type == LAST_RECORD_TYPE ||
470 !header->record_size)
473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
474 && sizeof(struct atom_hpd_int_record) <=
476 return (struct atom_hpd_int_record *) header;
478 offset += header->record_size;
485 * bios_parser_get_gpio_pin_info
486 * Get GpioPin information of input gpio id
488 * @param gpio_id, GPIO ID
489 * @param info, GpioPin information structure
490 * @return Bios parser result code
492 * to get the GPIO PIN INFO, we need:
493 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
495 * to get the registerA offset/mask
497 static enum bp_result bios_parser_get_gpio_pin_info(
500 struct gpio_pin_info *info)
502 struct bios_parser *bp = BP_FROM_DCB(dcb);
503 struct atom_gpio_pin_lut_v2_1 *header;
507 if (!DATA_TABLES(gpio_pin_lut))
508 return BP_RESULT_BADBIOSTABLE;
510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
511 DATA_TABLES(gpio_pin_lut));
513 return BP_RESULT_BADBIOSTABLE;
515 if (sizeof(struct atom_common_table_header) +
516 sizeof(struct atom_gpio_pin_assignment)
517 > le16_to_cpu(header->table_header.structuresize))
518 return BP_RESULT_BADBIOSTABLE;
520 if (header->table_header.content_revision != 1)
521 return BP_RESULT_UNSUPPORTED;
523 /* Temporary hard code gpio pin info */
524 #if defined(FOR_SIMNOW_BOOT)
526 struct atom_gpio_pin_assignment gpio_pin[8] = {
527 {0x5db5, 0, 0, 1, 0},
528 {0x5db5, 8, 8, 2, 0},
529 {0x5db5, 0x10, 0x10, 3, 0},
530 {0x5db5, 0x18, 0x14, 4, 0},
531 {0x5db5, 0x1A, 0x18, 5, 0},
532 {0x5db5, 0x1C, 0x1C, 6, 0},
536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
539 count = (le16_to_cpu(header->table_header.structuresize)
540 - sizeof(struct atom_common_table_header))
541 / sizeof(struct atom_gpio_pin_assignment);
543 for (i = 0; i < count; ++i) {
544 if (header->gpio_pin[i].gpio_id != gpio_id)
548 (uint32_t) le16_to_cpu(
549 header->gpio_pin[i].data_a_reg_index);
550 info->offset_y = info->offset + 2;
551 info->offset_en = info->offset + 1;
552 info->offset_mask = info->offset - 1;
554 info->mask = (uint32_t) (1 <<
555 header->gpio_pin[i].gpio_bitshift);
556 info->mask_y = info->mask + 2;
557 info->mask_en = info->mask + 1;
558 info->mask_mask = info->mask - 1;
563 return BP_RESULT_NORECORD;
566 static struct device_id device_type_from_device_id(uint16_t device_id)
569 struct device_id result_device_id;
571 result_device_id.raw_device_tag = device_id;
574 case ATOM_DISPLAY_LCD1_SUPPORT:
575 result_device_id.device_type = DEVICE_TYPE_LCD;
576 result_device_id.enum_id = 1;
579 case ATOM_DISPLAY_DFP1_SUPPORT:
580 result_device_id.device_type = DEVICE_TYPE_DFP;
581 result_device_id.enum_id = 1;
584 case ATOM_DISPLAY_DFP2_SUPPORT:
585 result_device_id.device_type = DEVICE_TYPE_DFP;
586 result_device_id.enum_id = 2;
589 case ATOM_DISPLAY_DFP3_SUPPORT:
590 result_device_id.device_type = DEVICE_TYPE_DFP;
591 result_device_id.enum_id = 3;
594 case ATOM_DISPLAY_DFP4_SUPPORT:
595 result_device_id.device_type = DEVICE_TYPE_DFP;
596 result_device_id.enum_id = 4;
599 case ATOM_DISPLAY_DFP5_SUPPORT:
600 result_device_id.device_type = DEVICE_TYPE_DFP;
601 result_device_id.enum_id = 5;
604 case ATOM_DISPLAY_DFP6_SUPPORT:
605 result_device_id.device_type = DEVICE_TYPE_DFP;
606 result_device_id.enum_id = 6;
610 BREAK_TO_DEBUGGER(); /* Invalid device Id */
611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
612 result_device_id.enum_id = 0;
614 return result_device_id;
617 static enum bp_result bios_parser_get_device_tag(
619 struct graphics_object_id connector_object_id,
620 uint32_t device_tag_index,
621 struct connector_device_tag_info *info)
623 struct bios_parser *bp = BP_FROM_DCB(dcb);
624 struct atom_display_object_path_v2 *object;
627 return BP_RESULT_BADINPUT;
629 /* getBiosObject will return MXM object */
630 object = get_bios_object(bp, connector_object_id);
633 BREAK_TO_DEBUGGER(); /* Invalid object id */
634 return BP_RESULT_BADINPUT;
637 info->acpi_device = 0; /* BIOS no longer provides this */
638 info->dev_id = device_type_from_device_id(object->device_tag);
643 static enum bp_result get_ss_info_v4_1(
644 struct bios_parser *bp,
647 struct spread_spectrum_info *ss_info)
649 enum bp_result result = BP_RESULT_OK;
650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
651 struct atom_smu_info_v3_3 *smu_info = NULL;
654 return BP_RESULT_BADINPUT;
656 if (!DATA_TABLES(dce_info))
657 return BP_RESULT_BADBIOSTABLE;
659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
660 DATA_TABLES(dce_info));
662 return BP_RESULT_BADBIOSTABLE;
665 ss_info->type.STEP_AND_DELAY_INFO = false;
666 ss_info->spread_percentage_divider = 1000;
667 /* BIOS no longer uses target clock. Always enable for now */
668 ss_info->target_clock_range = 0xffffffff;
671 case AS_SIGNAL_TYPE_DVI:
672 ss_info->spread_spectrum_percentage =
673 disp_cntl_tbl->dvi_ss_percentage;
674 ss_info->spread_spectrum_range =
675 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
677 ss_info->type.CENTER_MODE = true;
679 case AS_SIGNAL_TYPE_HDMI:
680 ss_info->spread_spectrum_percentage =
681 disp_cntl_tbl->hdmi_ss_percentage;
682 ss_info->spread_spectrum_range =
683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
685 ss_info->type.CENTER_MODE = true;
687 /* TODO LVDS not support anymore? */
688 case AS_SIGNAL_TYPE_DISPLAY_PORT:
689 ss_info->spread_spectrum_percentage =
690 disp_cntl_tbl->dp_ss_percentage;
691 ss_info->spread_spectrum_range =
692 disp_cntl_tbl->dp_ss_rate_10hz * 10;
693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
694 ss_info->type.CENTER_MODE = true;
696 case AS_SIGNAL_TYPE_GPU_PLL:
697 /* atom_firmware: DAL only get data from dce_info table.
698 * if data within smu_info is needed for DAL, VBIOS should
699 * copy it into dce_info
701 result = BP_RESULT_UNSUPPORTED;
703 case AS_SIGNAL_TYPE_XGMI:
704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
705 DATA_TABLES(smu_info));
707 return BP_RESULT_BADBIOSTABLE;
709 ss_info->spread_spectrum_percentage =
710 smu_info->waflclk_ss_percentage;
711 ss_info->spread_spectrum_range =
712 smu_info->gpuclk_ss_rate_10hz * 10;
713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
714 ss_info->type.CENTER_MODE = true;
717 result = BP_RESULT_UNSUPPORTED;
723 static enum bp_result get_ss_info_v4_2(
724 struct bios_parser *bp,
727 struct spread_spectrum_info *ss_info)
729 enum bp_result result = BP_RESULT_OK;
730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
731 struct atom_smu_info_v3_1 *smu_info = NULL;
734 return BP_RESULT_BADINPUT;
736 if (!DATA_TABLES(dce_info))
737 return BP_RESULT_BADBIOSTABLE;
739 if (!DATA_TABLES(smu_info))
740 return BP_RESULT_BADBIOSTABLE;
742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
743 DATA_TABLES(dce_info));
745 return BP_RESULT_BADBIOSTABLE;
747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
749 return BP_RESULT_BADBIOSTABLE;
751 ss_info->type.STEP_AND_DELAY_INFO = false;
752 ss_info->spread_percentage_divider = 1000;
753 /* BIOS no longer uses target clock. Always enable for now */
754 ss_info->target_clock_range = 0xffffffff;
757 case AS_SIGNAL_TYPE_DVI:
758 ss_info->spread_spectrum_percentage =
759 disp_cntl_tbl->dvi_ss_percentage;
760 ss_info->spread_spectrum_range =
761 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
763 ss_info->type.CENTER_MODE = true;
765 case AS_SIGNAL_TYPE_HDMI:
766 ss_info->spread_spectrum_percentage =
767 disp_cntl_tbl->hdmi_ss_percentage;
768 ss_info->spread_spectrum_range =
769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
771 ss_info->type.CENTER_MODE = true;
773 /* TODO LVDS not support anymore? */
774 case AS_SIGNAL_TYPE_DISPLAY_PORT:
775 ss_info->spread_spectrum_percentage =
776 smu_info->gpuclk_ss_percentage;
777 ss_info->spread_spectrum_range =
778 smu_info->gpuclk_ss_rate_10hz * 10;
779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
780 ss_info->type.CENTER_MODE = true;
782 case AS_SIGNAL_TYPE_GPU_PLL:
783 /* atom_firmware: DAL only get data from dce_info table.
784 * if data within smu_info is needed for DAL, VBIOS should
785 * copy it into dce_info
787 result = BP_RESULT_UNSUPPORTED;
790 result = BP_RESULT_UNSUPPORTED;
797 * bios_parser_get_spread_spectrum_info
798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
802 * there is only one entry for each signal /ss id. However, there is
803 * no planning of supporting multiple spread Sprectum entry for EverGreen
805 * @param [in] signal, ASSignalType to be converted to info index
806 * @param [in] index, number of entries that match the converted info index
807 * @param [out] ss_info, sprectrum information structure,
808 * @return Bios parser result code
810 static enum bp_result bios_parser_get_spread_spectrum_info(
812 enum as_signal_type signal,
814 struct spread_spectrum_info *ss_info)
816 struct bios_parser *bp = BP_FROM_DCB(dcb);
817 enum bp_result result = BP_RESULT_UNSUPPORTED;
818 struct atom_common_table_header *header;
819 struct atom_data_revision tbl_revision;
821 if (!ss_info) /* check for bad input */
822 return BP_RESULT_BADINPUT;
824 if (!DATA_TABLES(dce_info))
825 return BP_RESULT_UNSUPPORTED;
827 header = GET_IMAGE(struct atom_common_table_header,
828 DATA_TABLES(dce_info));
829 get_atom_data_table_revision(header, &tbl_revision);
831 switch (tbl_revision.major) {
833 switch (tbl_revision.minor) {
835 return get_ss_info_v4_1(bp, signal, index, ss_info);
838 return get_ss_info_v4_2(bp, signal, index, ss_info);
846 /* there can not be more then one entry for SS Info table */
850 static enum bp_result get_embedded_panel_info_v2_1(
851 struct bios_parser *bp,
852 struct embedded_panel_info *info)
854 struct lcd_info_v2_1 *lvds;
857 return BP_RESULT_BADINPUT;
859 if (!DATA_TABLES(lcd_info))
860 return BP_RESULT_UNSUPPORTED;
862 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
865 return BP_RESULT_BADBIOSTABLE;
867 /* TODO: previous vv1_3, should v2_1 */
868 if (!((lvds->table_header.format_revision == 2)
869 && (lvds->table_header.content_revision >= 1)))
870 return BP_RESULT_UNSUPPORTED;
872 memset(info, 0, sizeof(struct embedded_panel_info));
874 /* We need to convert from 10KHz units into KHz units */
875 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
876 /* usHActive does not include borders, according to VBIOS team */
877 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
878 /* usHBlanking_Time includes borders, so we should really be
879 * subtractingborders duing this translation, but LVDS generally
880 * doesn't have borders, so we should be okay leaving this as is for
881 * now. May need to revisit if we ever have LVDS with borders
883 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
884 /* usVActive does not include borders, according to VBIOS team*/
885 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
886 /* usVBlanking_Time includes borders, so we should really be
887 * subtracting borders duing this translation, but LVDS generally
888 * doesn't have borders, so we should be okay leaving this as is for
889 * now. May need to revisit if we ever have LVDS with borders
891 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
892 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
893 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
894 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
895 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
896 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
897 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
899 /* not provided by VBIOS */
900 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
902 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
903 & ATOM_HSYNC_POLARITY);
904 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
905 & ATOM_VSYNC_POLARITY);
907 /* not provided by VBIOS */
908 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
910 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
911 & ATOM_H_REPLICATIONBY2);
912 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
913 & ATOM_V_REPLICATIONBY2);
914 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
915 & ATOM_COMPOSITESYNC);
916 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
918 /* not provided by VBIOS*/
919 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
920 /* not provided by VBIOS*/
923 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
928 static enum bp_result bios_parser_get_embedded_panel_info(
930 struct embedded_panel_info *info)
933 *bp = BP_FROM_DCB(dcb);
934 struct atom_common_table_header *header;
935 struct atom_data_revision tbl_revision;
937 if (!DATA_TABLES(lcd_info))
938 return BP_RESULT_FAILURE;
940 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
943 return BP_RESULT_BADBIOSTABLE;
945 get_atom_data_table_revision(header, &tbl_revision);
947 switch (tbl_revision.major) {
949 switch (tbl_revision.minor) {
951 return get_embedded_panel_info_v2_1(bp, info);
959 return BP_RESULT_FAILURE;
962 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
964 enum dal_device_type device_type = device_id.device_type;
965 uint32_t enum_id = device_id.enum_id;
967 switch (device_type) {
968 case DEVICE_TYPE_LCD:
971 return ATOM_DISPLAY_LCD1_SUPPORT;
976 case DEVICE_TYPE_DFP:
979 return ATOM_DISPLAY_DFP1_SUPPORT;
981 return ATOM_DISPLAY_DFP2_SUPPORT;
983 return ATOM_DISPLAY_DFP3_SUPPORT;
985 return ATOM_DISPLAY_DFP4_SUPPORT;
987 return ATOM_DISPLAY_DFP5_SUPPORT;
989 return ATOM_DISPLAY_DFP6_SUPPORT;
998 /* Unidentified device ID, return empty support mask. */
1002 static bool bios_parser_is_device_id_supported(
1003 struct dc_bios *dcb,
1004 struct device_id id)
1006 struct bios_parser *bp = BP_FROM_DCB(dcb);
1008 uint32_t mask = get_support_mask_for_device_id(id);
1010 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1014 static uint32_t bios_parser_get_ss_entry_number(
1015 struct dc_bios *dcb,
1016 enum as_signal_type signal)
1018 /* TODO: DAL2 atomfirmware implementation does not need this.
1019 * why DAL3 need this?
1024 static enum bp_result bios_parser_transmitter_control(
1025 struct dc_bios *dcb,
1026 struct bp_transmitter_control *cntl)
1028 struct bios_parser *bp = BP_FROM_DCB(dcb);
1030 if (!bp->cmd_tbl.transmitter_control)
1031 return BP_RESULT_FAILURE;
1033 return bp->cmd_tbl.transmitter_control(bp, cntl);
1036 static enum bp_result bios_parser_encoder_control(
1037 struct dc_bios *dcb,
1038 struct bp_encoder_control *cntl)
1040 struct bios_parser *bp = BP_FROM_DCB(dcb);
1042 if (!bp->cmd_tbl.dig_encoder_control)
1043 return BP_RESULT_FAILURE;
1045 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1048 static enum bp_result bios_parser_set_pixel_clock(
1049 struct dc_bios *dcb,
1050 struct bp_pixel_clock_parameters *bp_params)
1052 struct bios_parser *bp = BP_FROM_DCB(dcb);
1054 if (!bp->cmd_tbl.set_pixel_clock)
1055 return BP_RESULT_FAILURE;
1057 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1060 static enum bp_result bios_parser_set_dce_clock(
1061 struct dc_bios *dcb,
1062 struct bp_set_dce_clock_parameters *bp_params)
1064 struct bios_parser *bp = BP_FROM_DCB(dcb);
1066 if (!bp->cmd_tbl.set_dce_clock)
1067 return BP_RESULT_FAILURE;
1069 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1072 static enum bp_result bios_parser_program_crtc_timing(
1073 struct dc_bios *dcb,
1074 struct bp_hw_crtc_timing_parameters *bp_params)
1076 struct bios_parser *bp = BP_FROM_DCB(dcb);
1078 if (!bp->cmd_tbl.set_crtc_timing)
1079 return BP_RESULT_FAILURE;
1081 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1084 static enum bp_result bios_parser_enable_crtc(
1085 struct dc_bios *dcb,
1086 enum controller_id id,
1089 struct bios_parser *bp = BP_FROM_DCB(dcb);
1091 if (!bp->cmd_tbl.enable_crtc)
1092 return BP_RESULT_FAILURE;
1094 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1097 static enum bp_result bios_parser_enable_disp_power_gating(
1098 struct dc_bios *dcb,
1099 enum controller_id controller_id,
1100 enum bp_pipe_control_action action)
1102 struct bios_parser *bp = BP_FROM_DCB(dcb);
1104 if (!bp->cmd_tbl.enable_disp_power_gating)
1105 return BP_RESULT_FAILURE;
1107 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1111 static bool bios_parser_is_accelerated_mode(
1112 struct dc_bios *dcb)
1114 return bios_is_accelerated_mode(dcb);
1118 * bios_parser_set_scratch_critical_state
1121 * update critical state bit in VBIOS scratch register
1124 * bool - to set or reset state
1126 static void bios_parser_set_scratch_critical_state(
1127 struct dc_bios *dcb,
1130 bios_set_scratch_critical_state(dcb, state);
1133 static enum bp_result bios_parser_get_firmware_info(
1134 struct dc_bios *dcb,
1135 struct dc_firmware_info *info)
1137 struct bios_parser *bp = BP_FROM_DCB(dcb);
1138 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1139 struct atom_common_table_header *header;
1141 struct atom_data_revision revision;
1143 if (info && DATA_TABLES(firmwareinfo)) {
1144 header = GET_IMAGE(struct atom_common_table_header,
1145 DATA_TABLES(firmwareinfo));
1146 get_atom_data_table_revision(header, &revision);
1147 switch (revision.major) {
1149 switch (revision.minor) {
1151 result = get_firmware_info_v3_1(bp, info);
1154 result = get_firmware_info_v3_2(bp, info);
1157 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
1160 result = get_firmware_info_v3_2(bp, info);
1174 static enum bp_result get_firmware_info_v3_1(
1175 struct bios_parser *bp,
1176 struct dc_firmware_info *info)
1178 struct atom_firmware_info_v3_1 *firmware_info;
1179 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1182 return BP_RESULT_BADINPUT;
1184 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1185 DATA_TABLES(firmwareinfo));
1187 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1188 DATA_TABLES(dce_info));
1190 if (!firmware_info || !dce_info)
1191 return BP_RESULT_BADBIOSTABLE;
1193 memset(info, 0, sizeof(*info));
1195 /* Pixel clock pll information. */
1196 /* We need to convert from 10KHz units into KHz units */
1197 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1198 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1200 /* 27MHz for Vega10: */
1201 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1203 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1204 if (info->pll_info.crystal_frequency == 0)
1205 info->pll_info.crystal_frequency = 27000;
1206 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1207 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1208 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1210 /* Get GPU PLL VCO Clock */
1212 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1213 /* VBIOS gives in 10KHz */
1214 info->smu_gpu_pll_output_freq =
1215 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1218 info->oem_i2c_present = false;
1220 return BP_RESULT_OK;
1223 static enum bp_result get_firmware_info_v3_2(
1224 struct bios_parser *bp,
1225 struct dc_firmware_info *info)
1227 struct atom_firmware_info_v3_2 *firmware_info;
1228 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1229 struct atom_common_table_header *header;
1230 struct atom_data_revision revision;
1231 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1232 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1235 return BP_RESULT_BADINPUT;
1237 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1238 DATA_TABLES(firmwareinfo));
1240 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1241 DATA_TABLES(dce_info));
1243 if (!firmware_info || !dce_info)
1244 return BP_RESULT_BADBIOSTABLE;
1246 memset(info, 0, sizeof(*info));
1248 header = GET_IMAGE(struct atom_common_table_header,
1249 DATA_TABLES(smu_info));
1250 get_atom_data_table_revision(header, &revision);
1252 if (revision.minor == 2) {
1254 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1255 DATA_TABLES(smu_info));
1258 return BP_RESULT_BADBIOSTABLE;
1260 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1261 } else if (revision.minor == 3) {
1263 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1264 DATA_TABLES(smu_info));
1267 return BP_RESULT_BADBIOSTABLE;
1269 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1272 // We need to convert from 10KHz units into KHz units.
1273 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1275 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1276 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1277 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1278 if (info->pll_info.crystal_frequency == 0) {
1279 if (revision.minor == 2)
1280 info->pll_info.crystal_frequency = 27000;
1281 else if (revision.minor == 3)
1282 info->pll_info.crystal_frequency = 100000;
1284 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1285 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1286 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1288 /* Get GPU PLL VCO Clock */
1289 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1290 if (revision.minor == 2)
1291 info->smu_gpu_pll_output_freq =
1292 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1293 else if (revision.minor == 3)
1294 info->smu_gpu_pll_output_freq =
1295 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1298 if (firmware_info->board_i2c_feature_id == 0x2) {
1299 info->oem_i2c_present = true;
1300 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1302 info->oem_i2c_present = false;
1305 return BP_RESULT_OK;
1308 static enum bp_result bios_parser_get_encoder_cap_info(
1309 struct dc_bios *dcb,
1310 struct graphics_object_id object_id,
1311 struct bp_encoder_cap_info *info)
1313 struct bios_parser *bp = BP_FROM_DCB(dcb);
1314 struct atom_display_object_path_v2 *object;
1315 struct atom_encoder_caps_record *record = NULL;
1318 return BP_RESULT_BADINPUT;
1320 object = get_bios_object(bp, object_id);
1323 return BP_RESULT_BADINPUT;
1325 record = get_encoder_cap_record(bp, object);
1327 return BP_RESULT_NORECORD;
1329 info->DP_HBR2_CAP = (record->encodercaps &
1330 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1331 info->DP_HBR2_EN = (record->encodercaps &
1332 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1333 info->DP_HBR3_EN = (record->encodercaps &
1334 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1335 info->HDMI_6GB_EN = (record->encodercaps &
1336 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1337 info->DP_IS_USB_C = (record->encodercaps &
1338 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1340 return BP_RESULT_OK;
1344 static struct atom_encoder_caps_record *get_encoder_cap_record(
1345 struct bios_parser *bp,
1346 struct atom_display_object_path_v2 *object)
1348 struct atom_common_record_header *header;
1352 BREAK_TO_DEBUGGER(); /* Invalid object */
1356 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1359 header = GET_IMAGE(struct atom_common_record_header, offset);
1364 offset += header->record_size;
1366 if (header->record_type == LAST_RECORD_TYPE ||
1367 !header->record_size)
1370 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1373 if (sizeof(struct atom_encoder_caps_record) <=
1374 header->record_size)
1375 return (struct atom_encoder_caps_record *)header;
1381 static enum bp_result get_vram_info_v23(
1382 struct bios_parser *bp,
1383 struct dc_vram_info *info)
1385 struct atom_vram_info_header_v2_3 *info_v23;
1386 enum bp_result result = BP_RESULT_OK;
1388 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
1389 DATA_TABLES(vram_info));
1391 if (info_v23 == NULL)
1392 return BP_RESULT_BADBIOSTABLE;
1394 info->num_chans = info_v23->vram_module[0].channel_num;
1395 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
1400 static enum bp_result get_vram_info_v24(
1401 struct bios_parser *bp,
1402 struct dc_vram_info *info)
1404 struct atom_vram_info_header_v2_4 *info_v24;
1405 enum bp_result result = BP_RESULT_OK;
1407 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
1408 DATA_TABLES(vram_info));
1410 if (info_v24 == NULL)
1411 return BP_RESULT_BADBIOSTABLE;
1413 info->num_chans = info_v24->vram_module[0].channel_num;
1414 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
1419 static enum bp_result get_vram_info_v25(
1420 struct bios_parser *bp,
1421 struct dc_vram_info *info)
1423 struct atom_vram_info_header_v2_5 *info_v25;
1424 enum bp_result result = BP_RESULT_OK;
1426 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
1427 DATA_TABLES(vram_info));
1429 if (info_v25 == NULL)
1430 return BP_RESULT_BADBIOSTABLE;
1432 info->num_chans = info_v25->vram_module[0].channel_num;
1433 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
1439 * get_integrated_info_v11
1442 * Get V8 integrated BIOS information
1445 * bios_parser *bp - [in]BIOS parser handler to get master data table
1446 * integrated_info *info - [out] store and output integrated info
1449 * enum bp_result - BP_RESULT_OK if information is available,
1450 * BP_RESULT_BADBIOSTABLE otherwise.
1452 static enum bp_result get_integrated_info_v11(
1453 struct bios_parser *bp,
1454 struct integrated_info *info)
1456 struct atom_integrated_system_info_v1_11 *info_v11;
1459 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1460 DATA_TABLES(integratedsysteminfo));
1462 if (info_v11 == NULL)
1463 return BP_RESULT_BADBIOSTABLE;
1465 info->gpu_cap_info =
1466 le32_to_cpu(info_v11->gpucapinfo);
1468 * system_config: Bit[0] = 0 : PCIE power gating disabled
1469 * = 1 : PCIE power gating enabled
1470 * Bit[1] = 0 : DDR-PLL shut down disabled
1471 * = 1 : DDR-PLL shut down enabled
1472 * Bit[2] = 0 : DDR-PLL power down disabled
1473 * = 1 : DDR-PLL power down enabled
1475 info->system_config = le32_to_cpu(info_v11->system_config);
1476 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1477 info->memory_type = info_v11->memorytype;
1478 info->ma_channel_number = info_v11->umachannelnumber;
1479 info->lvds_ss_percentage =
1480 le16_to_cpu(info_v11->lvds_ss_percentage);
1481 info->dp_ss_control =
1482 le16_to_cpu(info_v11->reserved1);
1483 info->lvds_sspread_rate_in_10hz =
1484 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1485 info->hdmi_ss_percentage =
1486 le16_to_cpu(info_v11->hdmi_ss_percentage);
1487 info->hdmi_sspread_rate_in_10hz =
1488 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1489 info->dvi_ss_percentage =
1490 le16_to_cpu(info_v11->dvi_ss_percentage);
1491 info->dvi_sspread_rate_in_10_hz =
1492 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1493 info->lvds_misc = info_v11->lvds_misc;
1494 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1495 info->ext_disp_conn_info.gu_id[i] =
1496 info_v11->extdispconninfo.guid[i];
1499 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1500 info->ext_disp_conn_info.path[i].device_connector_id =
1501 object_id_from_bios_object_id(
1502 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1504 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1505 object_id_from_bios_object_id(
1507 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1509 info->ext_disp_conn_info.path[i].device_tag =
1511 info_v11->extdispconninfo.path[i].device_tag);
1512 info->ext_disp_conn_info.path[i].device_acpi_enum =
1514 info_v11->extdispconninfo.path[i].device_acpi_enum);
1515 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1516 info_v11->extdispconninfo.path[i].auxddclut_index;
1517 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1518 info_v11->extdispconninfo.path[i].hpdlut_index;
1519 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1520 info_v11->extdispconninfo.path[i].channelmapping;
1521 info->ext_disp_conn_info.path[i].caps =
1522 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1524 info->ext_disp_conn_info.checksum =
1525 info_v11->extdispconninfo.checksum;
1527 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1528 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1529 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1530 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1531 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1532 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1533 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1535 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1536 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1537 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1538 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1539 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1540 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1543 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1544 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1545 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1546 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1547 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1548 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1549 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1551 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1552 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1553 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1554 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1555 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1556 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1559 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1560 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1561 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1562 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1563 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1564 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1565 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1567 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1568 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1569 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1570 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1571 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1572 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1575 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1576 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1577 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1578 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1579 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1580 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1581 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1583 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1584 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1585 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1586 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1587 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1588 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1592 /** TODO - review **/
1594 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1596 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1597 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1599 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1600 /* Convert [10KHz] into [KHz] */
1601 info->disp_clk_voltage[i].max_supported_clk =
1602 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1603 ulMaximumSupportedCLK) * 10;
1604 info->disp_clk_voltage[i].voltage_index =
1605 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1608 info->boot_up_req_display_vector =
1609 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1610 info->boot_up_nb_voltage =
1611 le16_to_cpu(info_v11->usBootUpNBVoltage);
1612 info->ext_disp_conn_info_offset =
1613 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1614 info->gmc_restore_reset_time =
1615 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1616 info->minimum_n_clk =
1617 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1618 for (i = 1; i < 4; ++i)
1619 info->minimum_n_clk =
1620 info->minimum_n_clk <
1621 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1622 info->minimum_n_clk : le32_to_cpu(
1623 info_v11->ulNbpStateNClkFreq[i]);
1625 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1626 info->ddr_dll_power_up_time =
1627 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1628 info->ddr_pll_power_up_time =
1629 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1630 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1631 info->max_lvds_pclk_freq_in_single_link =
1632 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1633 info->max_lvds_pclk_freq_in_single_link =
1634 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1635 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1636 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1637 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1638 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1639 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1640 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1641 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1642 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1643 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1644 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1645 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1646 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1647 info->lvds_off_to_on_delay_in_4ms =
1648 info_v11->ucLVDSOffToOnDelay_in4Ms;
1649 info->lvds_bit_depth_control_val =
1650 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1652 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1653 /* Convert [10KHz] into [KHz] */
1654 info->avail_s_clk[i].supported_s_clk =
1655 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1657 info->avail_s_clk[i].voltage_index =
1658 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1659 info->avail_s_clk[i].voltage_id =
1660 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1664 return BP_RESULT_OK;
1669 * construct_integrated_info
1672 * Get integrated BIOS information based on table revision
1675 * bios_parser *bp - [in]BIOS parser handler to get master data table
1676 * integrated_info *info - [out] store and output integrated info
1679 * enum bp_result - BP_RESULT_OK if information is available,
1680 * BP_RESULT_BADBIOSTABLE otherwise.
1682 static enum bp_result construct_integrated_info(
1683 struct bios_parser *bp,
1684 struct integrated_info *info)
1686 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1688 struct atom_common_table_header *header;
1689 struct atom_data_revision revision;
1693 if (info && DATA_TABLES(integratedsysteminfo)) {
1694 header = GET_IMAGE(struct atom_common_table_header,
1695 DATA_TABLES(integratedsysteminfo));
1697 get_atom_data_table_revision(header, &revision);
1699 /* Don't need to check major revision as they are all 1 */
1700 switch (revision.minor) {
1703 result = get_integrated_info_v11(bp, info);
1710 if (result != BP_RESULT_OK)
1713 /* Sort voltage table from low to high*/
1714 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1715 for (j = i; j > 0; --j) {
1716 if (info->disp_clk_voltage[j].max_supported_clk <
1717 info->disp_clk_voltage[j-1].max_supported_clk
1719 /* swap j and j - 1*/
1720 swap(info->disp_clk_voltage[j - 1],
1721 info->disp_clk_voltage[j]);
1729 static enum bp_result bios_parser_get_vram_info(
1730 struct dc_bios *dcb,
1731 struct dc_vram_info *info)
1733 struct bios_parser *bp = BP_FROM_DCB(dcb);
1734 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1735 struct atom_common_table_header *header;
1736 struct atom_data_revision revision;
1738 if (info && DATA_TABLES(vram_info)) {
1739 header = GET_IMAGE(struct atom_common_table_header,
1740 DATA_TABLES(vram_info));
1742 get_atom_data_table_revision(header, &revision);
1744 switch (revision.major) {
1746 switch (revision.minor) {
1748 result = get_vram_info_v23(bp, info);
1751 result = get_vram_info_v24(bp, info);
1754 result = get_vram_info_v25(bp, info);
1769 static struct integrated_info *bios_parser_create_integrated_info(
1770 struct dc_bios *dcb)
1772 struct bios_parser *bp = BP_FROM_DCB(dcb);
1773 struct integrated_info *info = NULL;
1775 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
1782 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
1790 static enum bp_result update_slot_layout_info(
1791 struct dc_bios *dcb,
1793 struct slot_layout_info *slot_layout_info)
1795 unsigned int record_offset;
1797 struct atom_display_object_path_v2 *object;
1798 struct atom_bracket_layout_record *record;
1799 struct atom_common_record_header *record_header;
1800 enum bp_result result;
1801 struct bios_parser *bp;
1802 struct object_info_table *tbl;
1803 struct display_object_info_table_v1_4 *v1_4;
1806 record_header = NULL;
1807 result = BP_RESULT_NORECORD;
1809 bp = BP_FROM_DCB(dcb);
1810 tbl = &bp->object_info_tbl;
1813 object = &v1_4->display_path[i];
1814 record_offset = (unsigned int)
1815 (object->disp_recordoffset) +
1816 (unsigned int)(bp->object_info_tbl_offset);
1820 record_header = (struct atom_common_record_header *)
1821 GET_IMAGE(struct atom_common_record_header,
1823 if (record_header == NULL) {
1824 result = BP_RESULT_BADBIOSTABLE;
1828 /* the end of the list */
1829 if (record_header->record_type == 0xff ||
1830 record_header->record_size == 0) {
1834 if (record_header->record_type ==
1835 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
1836 sizeof(struct atom_bracket_layout_record)
1837 <= record_header->record_size) {
1838 record = (struct atom_bracket_layout_record *)
1840 result = BP_RESULT_OK;
1844 record_offset += record_header->record_size;
1847 /* return if the record not found */
1848 if (result != BP_RESULT_OK)
1851 /* get slot sizes */
1852 slot_layout_info->length = record->bracketlen;
1853 slot_layout_info->width = record->bracketwidth;
1855 /* get info for each connector in the slot */
1856 slot_layout_info->num_of_connectors = record->conn_num;
1857 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
1858 slot_layout_info->connectors[j].connector_type =
1859 (enum connector_layout_type)
1860 (record->conn_info[j].connector_type);
1861 switch (record->conn_info[j].connector_type) {
1862 case CONNECTOR_TYPE_DVI_D:
1863 slot_layout_info->connectors[j].connector_type =
1864 CONNECTOR_LAYOUT_TYPE_DVI_D;
1865 slot_layout_info->connectors[j].length =
1869 case CONNECTOR_TYPE_HDMI:
1870 slot_layout_info->connectors[j].connector_type =
1871 CONNECTOR_LAYOUT_TYPE_HDMI;
1872 slot_layout_info->connectors[j].length =
1873 CONNECTOR_SIZE_HDMI;
1876 case CONNECTOR_TYPE_DISPLAY_PORT:
1877 slot_layout_info->connectors[j].connector_type =
1878 CONNECTOR_LAYOUT_TYPE_DP;
1879 slot_layout_info->connectors[j].length =
1883 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
1884 slot_layout_info->connectors[j].connector_type =
1885 CONNECTOR_LAYOUT_TYPE_MINI_DP;
1886 slot_layout_info->connectors[j].length =
1887 CONNECTOR_SIZE_MINI_DP;
1891 slot_layout_info->connectors[j].connector_type =
1892 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
1893 slot_layout_info->connectors[j].length =
1894 CONNECTOR_SIZE_UNKNOWN;
1897 slot_layout_info->connectors[j].position =
1898 record->conn_info[j].position;
1899 slot_layout_info->connectors[j].connector_id =
1900 object_id_from_bios_object_id(
1901 record->conn_info[j].connectorobjid);
1907 static enum bp_result get_bracket_layout_record(
1908 struct dc_bios *dcb,
1909 unsigned int bracket_layout_id,
1910 struct slot_layout_info *slot_layout_info)
1913 struct bios_parser *bp = BP_FROM_DCB(dcb);
1914 enum bp_result result;
1915 struct object_info_table *tbl;
1916 struct display_object_info_table_v1_4 *v1_4;
1918 if (slot_layout_info == NULL) {
1919 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
1920 return BP_RESULT_BADINPUT;
1922 tbl = &bp->object_info_tbl;
1925 result = BP_RESULT_NORECORD;
1926 for (i = 0; i < v1_4->number_of_path; ++i) {
1928 if (bracket_layout_id ==
1929 v1_4->display_path[i].display_objid) {
1930 result = update_slot_layout_info(dcb, i,
1938 static enum bp_result bios_get_board_layout_info(
1939 struct dc_bios *dcb,
1940 struct board_layout_info *board_layout_info)
1943 enum bp_result record_result;
1945 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
1946 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
1947 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
1951 if (board_layout_info == NULL) {
1952 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
1953 return BP_RESULT_BADINPUT;
1956 board_layout_info->num_of_slots = 0;
1958 for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
1959 record_result = get_bracket_layout_record(dcb,
1960 slot_index_to_vbios_id[i],
1961 &board_layout_info->slots[i]);
1963 if (record_result == BP_RESULT_NORECORD && i > 0)
1964 break; /* no more slots present in bios */
1965 else if (record_result != BP_RESULT_OK)
1966 return record_result; /* fail */
1968 ++board_layout_info->num_of_slots;
1971 /* all data is valid */
1972 board_layout_info->is_number_of_slots_valid = 1;
1973 board_layout_info->is_slots_size_valid = 1;
1974 board_layout_info->is_connector_offsets_valid = 1;
1975 board_layout_info->is_connector_lengths_valid = 1;
1977 return BP_RESULT_OK;
1981 static uint16_t bios_parser_pack_data_tables(
1982 struct dc_bios *dcb,
1985 #ifdef PACK_BIOS_DATA
1986 struct bios_parser *bp = BP_FROM_DCB(dcb);
1987 struct atom_rom_header_v2_2 *rom_header = NULL;
1988 struct atom_rom_header_v2_2 *packed_rom_header = NULL;
1989 struct atom_common_table_header *data_tbl_header = NULL;
1990 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL;
1991 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL;
1992 struct atom_data_revision tbl_rev = {0};
1993 uint16_t *rom_header_offset = NULL;
1994 const uint8_t *bios = bp->base.bios;
1995 uint8_t *bios_dst = (uint8_t *)dst;
1996 uint16_t packed_rom_header_offset;
1997 uint16_t packed_masterdatatable_offset;
1998 uint16_t packed_data_tbl_offset;
1999 uint16_t data_tbl_offset;
2003 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2005 if (!rom_header_offset)
2008 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
2013 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
2014 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
2017 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev);
2018 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1))
2021 packed_rom_header_offset =
2022 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset);
2024 packed_masterdatatable_offset =
2025 packed_rom_header_offset + rom_header->table_header.structuresize;
2027 packed_data_tbl_offset =
2028 packed_masterdatatable_offset +
2029 bp->master_data_tbl->table_header.structuresize;
2032 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset);
2034 packed_master_data_tbl =
2035 (struct atom_master_data_table_v2_1 *)(bios_dst +
2036 packed_masterdatatable_offset);
2038 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2040 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) =
2041 packed_rom_header_offset;
2043 memcpy(bios_dst + packed_rom_header_offset, rom_header,
2044 rom_header->table_header.structuresize);
2046 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset;
2048 memcpy(&packed_master_data_tbl->table_header,
2049 &bp->master_data_tbl->table_header,
2050 sizeof(bp->master_data_tbl->table_header));
2052 data_tbl_list = &bp->master_data_tbl->listOfdatatables;
2054 /* Each data table offset in data table list is 2 bytes,
2055 * we can use that to iterate through listOfdatatables
2056 * without knowing the name of each member.
2058 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) {
2059 data_tbl_offset = *((uint16_t *)data_tbl_list + i);
2061 if (data_tbl_offset) {
2063 (struct atom_common_table_header *)(bios + data_tbl_offset);
2065 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header,
2066 data_tbl_header->structuresize);
2068 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) =
2069 packed_data_tbl_offset;
2071 packed_data_tbl_offset += data_tbl_header->structuresize;
2073 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0;
2076 return packed_data_tbl_offset;
2078 // TODO: There is data bytes alignment issue, disable it for now.
2082 static const struct dc_vbios_funcs vbios_funcs = {
2083 .get_connectors_number = bios_parser_get_connectors_number,
2085 .get_connector_id = bios_parser_get_connector_id,
2087 .get_src_obj = bios_parser_get_src_obj,
2089 .get_i2c_info = bios_parser_get_i2c_info,
2091 .get_hpd_info = bios_parser_get_hpd_info,
2093 .get_device_tag = bios_parser_get_device_tag,
2095 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
2097 .get_ss_entry_number = bios_parser_get_ss_entry_number,
2099 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
2101 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
2103 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
2105 .is_device_id_supported = bios_parser_is_device_id_supported,
2107 .is_accelerated_mode = bios_parser_is_accelerated_mode,
2109 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
2113 .encoder_control = bios_parser_encoder_control,
2115 .transmitter_control = bios_parser_transmitter_control,
2117 .enable_crtc = bios_parser_enable_crtc,
2119 .set_pixel_clock = bios_parser_set_pixel_clock,
2121 .set_dce_clock = bios_parser_set_dce_clock,
2123 .program_crtc_timing = bios_parser_program_crtc_timing,
2125 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
2127 .bios_parser_destroy = firmware_parser_destroy,
2129 .get_board_layout_info = bios_get_board_layout_info,
2130 .pack_data_tables = bios_parser_pack_data_tables,
2133 static bool bios_parser2_construct(
2134 struct bios_parser *bp,
2135 struct bp_init_data *init,
2136 enum dce_version dce_version)
2138 uint16_t *rom_header_offset = NULL;
2139 struct atom_rom_header_v2_2 *rom_header = NULL;
2140 struct display_object_info_table_v1_4 *object_info_tbl;
2141 struct atom_data_revision tbl_rev = {0};
2149 bp->base.funcs = &vbios_funcs;
2150 bp->base.bios = init->bios;
2151 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
2153 bp->base.ctx = init->ctx;
2155 bp->base.bios_local_image = NULL;
2158 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
2160 if (!rom_header_offset)
2163 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
2168 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
2169 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
2172 bp->master_data_tbl =
2173 GET_IMAGE(struct atom_master_data_table_v2_1,
2174 rom_header->masterdatatable_offset);
2176 if (!bp->master_data_tbl)
2179 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
2181 if (!bp->object_info_tbl_offset)
2185 GET_IMAGE(struct display_object_info_table_v1_4,
2186 bp->object_info_tbl_offset);
2188 if (!object_info_tbl)
2191 get_atom_data_table_revision(&object_info_tbl->table_header,
2192 &bp->object_info_tbl.revision);
2194 if (bp->object_info_tbl.revision.major == 1
2195 && bp->object_info_tbl.revision.minor >= 4) {
2196 struct display_object_info_table_v1_4 *tbl_v1_4;
2198 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
2199 bp->object_info_tbl_offset);
2203 bp->object_info_tbl.v1_4 = tbl_v1_4;
2207 dal_firmware_parser_init_cmd_tbl(bp);
2208 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2210 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2211 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2212 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
2217 struct dc_bios *firmware_parser_create(
2218 struct bp_init_data *init,
2219 enum dce_version dce_version)
2221 struct bios_parser *bp = NULL;
2223 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2227 if (bios_parser2_construct(bp, init, dce_version))