2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
31 #include "atomfirmware.h"
33 #include "dc_bios_types.h"
34 #include "include/grph_object_ctrl_defs.h"
35 #include "include/bios_parser_interface.h"
36 #include "include/i2caux_interface.h"
37 #include "include/logger_interface.h"
39 #include "command_table2.h"
41 #include "bios_parser_helper.h"
42 #include "command_table_helper2.h"
43 #include "bios_parser2.h"
44 #include "bios_parser_types_internal2.h"
45 #include "bios_parser_interface.h"
47 #include "bios_parser_common.h"
49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
71 #define LAST_RECORD_TYPE 0xff
72 #define SMU9_SYSPLL0_ID 0
74 struct i2c_id_config_access {
75 uint8_t bfI2C_LineMux:4;
76 uint8_t bfHW_EngineID:3;
77 uint8_t bfHW_Capable:1;
81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
82 struct atom_i2c_record *record,
83 struct graphics_object_i2c_info *info);
85 static enum bp_result bios_parser_get_firmware_info(
87 struct dc_firmware_info *info);
89 static enum bp_result bios_parser_get_encoder_cap_info(
91 struct graphics_object_id object_id,
92 struct bp_encoder_cap_info *info);
94 static enum bp_result get_firmware_info_v3_1(
95 struct bios_parser *bp,
96 struct dc_firmware_info *info);
98 static enum bp_result get_firmware_info_v3_2(
99 struct bios_parser *bp,
100 struct dc_firmware_info *info);
102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
103 struct atom_display_object_path_v2 *object);
105 static struct atom_encoder_caps_record *get_encoder_cap_record(
106 struct bios_parser *bp,
107 struct atom_display_object_path_v2 *object);
109 #define BIOS_IMAGE_SIZE_OFFSET 2
110 #define BIOS_IMAGE_SIZE_UNIT 512
112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
114 static void destruct(struct bios_parser *bp)
116 kfree(bp->base.bios_local_image);
117 kfree(bp->base.integrated_info);
120 static void firmware_parser_destroy(struct dc_bios **dcb)
122 struct bios_parser *bp = BP_FROM_DCB(*dcb);
135 static void get_atom_data_table_revision(
136 struct atom_common_table_header *atom_data_tbl,
137 struct atom_data_revision *tbl_revision)
142 /* initialize the revision to 0 which is invalid revision */
143 tbl_revision->major = 0;
144 tbl_revision->minor = 0;
149 tbl_revision->major =
150 (uint32_t) atom_data_tbl->format_revision & 0x3f;
151 tbl_revision->minor =
152 (uint32_t) atom_data_tbl->content_revision & 0x3f;
155 /* BIOS oject table displaypath is per connector.
156 * There is extra path not for connector. BIOS fill its encoderid as 0
158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
160 struct bios_parser *bp = BP_FROM_DCB(dcb);
161 unsigned int count = 0;
164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
171 static struct graphics_object_id bios_parser_get_connector_id(
175 struct bios_parser *bp = BP_FROM_DCB(dcb);
176 struct graphics_object_id object_id = dal_graphics_object_id_init(
177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
178 struct object_info_table *tbl = &bp->object_info_tbl;
179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
181 if (v1_4->number_of_path > i) {
182 /* If display_objid is generic object id, the encoderObj
183 * /extencoderobjId should be 0
185 if (v1_4->display_path[i].encoderobjid != 0 &&
186 v1_4->display_path[i].display_objid != 0)
187 object_id = object_id_from_bios_object_id(
188 v1_4->display_path[i].display_objid);
194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
195 struct graphics_object_id object_id, uint32_t index,
196 struct graphics_object_id *src_object_id)
198 struct bios_parser *bp = BP_FROM_DCB(dcb);
200 enum bp_result bp_result = BP_RESULT_BADINPUT;
201 struct graphics_object_id obj_id = {0};
202 struct object_info_table *tbl = &bp->object_info_tbl;
207 switch (object_id.type) {
208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
211 case OBJECT_TYPE_ENCODER:
212 /* TODO: since num of src must be less than 2.
213 * If found in for loop, should break.
214 * DAL2 implementation may be changed too
216 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
217 obj_id = object_id_from_bios_object_id(
218 tbl->v1_4->display_path[i].encoderobjid);
219 if (object_id.type == obj_id.type &&
220 object_id.id == obj_id.id &&
224 object_id_from_bios_object_id(0x1100);
228 bp_result = BP_RESULT_OK;
230 case OBJECT_TYPE_CONNECTOR:
231 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
232 obj_id = object_id_from_bios_object_id(
233 tbl->v1_4->display_path[i].display_objid);
235 if (object_id.type == obj_id.type &&
236 object_id.id == obj_id.id &&
237 object_id.enum_id == obj_id.enum_id) {
239 object_id_from_bios_object_id(
240 tbl->v1_4->display_path[i].encoderobjid);
244 bp_result = BP_RESULT_OK;
253 /* from graphics_object_id, find display path which includes the object_id */
254 static struct atom_display_object_path_v2 *get_bios_object(
255 struct bios_parser *bp,
256 struct graphics_object_id id)
259 struct graphics_object_id obj_id = {0};
262 case OBJECT_TYPE_ENCODER:
263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
264 obj_id = object_id_from_bios_object_id(
265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
266 if (id.type == obj_id.type && id.id == obj_id.id
267 && id.enum_id == obj_id.enum_id)
268 return &bp->object_info_tbl.v1_4->display_path[i];
271 case OBJECT_TYPE_CONNECTOR:
272 case OBJECT_TYPE_GENERIC:
273 /* Both Generic and Connector Object ID
274 * will be stored on display_objid
276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
277 obj_id = object_id_from_bios_object_id(
278 bp->object_info_tbl.v1_4->display_path[i].display_objid);
279 if (id.type == obj_id.type && id.id == obj_id.id
280 && id.enum_id == obj_id.enum_id)
281 return &bp->object_info_tbl.v1_4->display_path[i];
289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
290 struct graphics_object_id id,
291 struct graphics_object_i2c_info *info)
294 struct atom_display_object_path_v2 *object;
295 struct atom_common_record_header *header;
296 struct atom_i2c_record *record;
297 struct atom_i2c_record dummy_record = {0};
298 struct bios_parser *bp = BP_FROM_DCB(dcb);
301 return BP_RESULT_BADINPUT;
303 if (id.type == OBJECT_TYPE_GENERIC) {
304 dummy_record.i2c_id = id.id;
306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
309 return BP_RESULT_NORECORD;
312 object = get_bios_object(bp, id);
315 return BP_RESULT_BADINPUT;
317 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
320 header = GET_IMAGE(struct atom_common_record_header, offset);
323 return BP_RESULT_BADBIOSTABLE;
325 if (header->record_type == LAST_RECORD_TYPE ||
326 !header->record_size)
329 if (header->record_type == ATOM_I2C_RECORD_TYPE
330 && sizeof(struct atom_i2c_record) <=
331 header->record_size) {
332 /* get the I2C info */
333 record = (struct atom_i2c_record *) header;
335 if (get_gpio_i2c_info(bp, record, info) ==
340 offset += header->record_size;
343 return BP_RESULT_NORECORD;
346 static enum bp_result get_gpio_i2c_info(
347 struct bios_parser *bp,
348 struct atom_i2c_record *record,
349 struct graphics_object_i2c_info *info)
351 struct atom_gpio_pin_lut_v2_1 *header;
353 unsigned int table_index = 0;
354 bool find_valid = false;
357 return BP_RESULT_BADINPUT;
359 /* get the GPIO_I2C info */
360 if (!DATA_TABLES(gpio_pin_lut))
361 return BP_RESULT_BADBIOSTABLE;
363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
364 DATA_TABLES(gpio_pin_lut));
366 return BP_RESULT_BADBIOSTABLE;
368 if (sizeof(struct atom_common_table_header) +
369 sizeof(struct atom_gpio_pin_assignment) >
370 le16_to_cpu(header->table_header.structuresize))
371 return BP_RESULT_BADBIOSTABLE;
373 /* TODO: is version change? */
374 if (header->table_header.content_revision != 1)
375 return BP_RESULT_UNSUPPORTED;
378 count = (le16_to_cpu(header->table_header.structuresize)
379 - sizeof(struct atom_common_table_header))
380 / sizeof(struct atom_gpio_pin_assignment);
382 for (table_index = 0; table_index < count; table_index++) {
383 if (((record->i2c_id & I2C_HW_CAP) == (
384 header->gpio_pin[table_index].gpio_id &
386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
387 (header->gpio_pin[table_index].gpio_id &
388 I2C_HW_ENGINE_ID_MASK)) &&
389 ((record->i2c_id & I2C_HW_LANE_MUX) ==
390 (header->gpio_pin[table_index].gpio_id &
398 /* If we don't find the entry that we are looking for then
399 * we will return BP_Result_BadBiosTable.
401 if (find_valid == false)
402 return BP_RESULT_BADBIOSTABLE;
404 /* get the GPIO_I2C_INFO */
405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
408 info->i2c_slave_address = record->i2c_slave_addr;
410 /* TODO: check how to get register offset for en, Y, etc. */
411 info->gpio_info.clk_a_register_index =
413 header->gpio_pin[table_index].data_a_reg_index);
414 info->gpio_info.clk_a_shift =
415 header->gpio_pin[table_index].gpio_bitshift;
420 static enum bp_result bios_parser_get_hpd_info(
422 struct graphics_object_id id,
423 struct graphics_object_hpd_info *info)
425 struct bios_parser *bp = BP_FROM_DCB(dcb);
426 struct atom_display_object_path_v2 *object;
427 struct atom_hpd_int_record *record = NULL;
430 return BP_RESULT_BADINPUT;
432 object = get_bios_object(bp, id);
435 return BP_RESULT_BADINPUT;
437 record = get_hpd_record(bp, object);
439 if (record != NULL) {
440 info->hpd_int_gpio_uid = record->pin_id;
441 info->hpd_active = record->plugin_pin_state;
445 return BP_RESULT_NORECORD;
448 static struct atom_hpd_int_record *get_hpd_record(
449 struct bios_parser *bp,
450 struct atom_display_object_path_v2 *object)
452 struct atom_common_record_header *header;
456 BREAK_TO_DEBUGGER(); /* Invalid object */
460 offset = le16_to_cpu(object->disp_recordoffset)
461 + bp->object_info_tbl_offset;
464 header = GET_IMAGE(struct atom_common_record_header, offset);
469 if (header->record_type == LAST_RECORD_TYPE ||
470 !header->record_size)
473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
474 && sizeof(struct atom_hpd_int_record) <=
476 return (struct atom_hpd_int_record *) header;
478 offset += header->record_size;
485 * bios_parser_get_gpio_pin_info
486 * Get GpioPin information of input gpio id
488 * @param gpio_id, GPIO ID
489 * @param info, GpioPin information structure
490 * @return Bios parser result code
492 * to get the GPIO PIN INFO, we need:
493 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
495 * to get the registerA offset/mask
497 static enum bp_result bios_parser_get_gpio_pin_info(
500 struct gpio_pin_info *info)
502 struct bios_parser *bp = BP_FROM_DCB(dcb);
503 struct atom_gpio_pin_lut_v2_1 *header;
507 if (!DATA_TABLES(gpio_pin_lut))
508 return BP_RESULT_BADBIOSTABLE;
510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
511 DATA_TABLES(gpio_pin_lut));
513 return BP_RESULT_BADBIOSTABLE;
515 if (sizeof(struct atom_common_table_header) +
516 sizeof(struct atom_gpio_pin_assignment)
517 > le16_to_cpu(header->table_header.structuresize))
518 return BP_RESULT_BADBIOSTABLE;
520 if (header->table_header.content_revision != 1)
521 return BP_RESULT_UNSUPPORTED;
523 /* Temporary hard code gpio pin info */
524 #if defined(FOR_SIMNOW_BOOT)
526 struct atom_gpio_pin_assignment gpio_pin[8] = {
527 {0x5db5, 0, 0, 1, 0},
528 {0x5db5, 8, 8, 2, 0},
529 {0x5db5, 0x10, 0x10, 3, 0},
530 {0x5db5, 0x18, 0x14, 4, 0},
531 {0x5db5, 0x1A, 0x18, 5, 0},
532 {0x5db5, 0x1C, 0x1C, 6, 0},
536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
539 count = (le16_to_cpu(header->table_header.structuresize)
540 - sizeof(struct atom_common_table_header))
541 / sizeof(struct atom_gpio_pin_assignment);
543 for (i = 0; i < count; ++i) {
544 if (header->gpio_pin[i].gpio_id != gpio_id)
548 (uint32_t) le16_to_cpu(
549 header->gpio_pin[i].data_a_reg_index);
550 info->offset_y = info->offset + 2;
551 info->offset_en = info->offset + 1;
552 info->offset_mask = info->offset - 1;
554 info->mask = (uint32_t) (1 <<
555 header->gpio_pin[i].gpio_bitshift);
556 info->mask_y = info->mask + 2;
557 info->mask_en = info->mask + 1;
558 info->mask_mask = info->mask - 1;
563 return BP_RESULT_NORECORD;
566 static struct device_id device_type_from_device_id(uint16_t device_id)
569 struct device_id result_device_id;
571 result_device_id.raw_device_tag = device_id;
574 case ATOM_DISPLAY_LCD1_SUPPORT:
575 result_device_id.device_type = DEVICE_TYPE_LCD;
576 result_device_id.enum_id = 1;
579 case ATOM_DISPLAY_DFP1_SUPPORT:
580 result_device_id.device_type = DEVICE_TYPE_DFP;
581 result_device_id.enum_id = 1;
584 case ATOM_DISPLAY_DFP2_SUPPORT:
585 result_device_id.device_type = DEVICE_TYPE_DFP;
586 result_device_id.enum_id = 2;
589 case ATOM_DISPLAY_DFP3_SUPPORT:
590 result_device_id.device_type = DEVICE_TYPE_DFP;
591 result_device_id.enum_id = 3;
594 case ATOM_DISPLAY_DFP4_SUPPORT:
595 result_device_id.device_type = DEVICE_TYPE_DFP;
596 result_device_id.enum_id = 4;
599 case ATOM_DISPLAY_DFP5_SUPPORT:
600 result_device_id.device_type = DEVICE_TYPE_DFP;
601 result_device_id.enum_id = 5;
604 case ATOM_DISPLAY_DFP6_SUPPORT:
605 result_device_id.device_type = DEVICE_TYPE_DFP;
606 result_device_id.enum_id = 6;
610 BREAK_TO_DEBUGGER(); /* Invalid device Id */
611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
612 result_device_id.enum_id = 0;
614 return result_device_id;
617 static enum bp_result bios_parser_get_device_tag(
619 struct graphics_object_id connector_object_id,
620 uint32_t device_tag_index,
621 struct connector_device_tag_info *info)
623 struct bios_parser *bp = BP_FROM_DCB(dcb);
624 struct atom_display_object_path_v2 *object;
627 return BP_RESULT_BADINPUT;
629 /* getBiosObject will return MXM object */
630 object = get_bios_object(bp, connector_object_id);
633 BREAK_TO_DEBUGGER(); /* Invalid object id */
634 return BP_RESULT_BADINPUT;
637 info->acpi_device = 0; /* BIOS no longer provides this */
638 info->dev_id = device_type_from_device_id(object->device_tag);
643 static enum bp_result get_ss_info_v4_1(
644 struct bios_parser *bp,
647 struct spread_spectrum_info *ss_info)
649 enum bp_result result = BP_RESULT_OK;
650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
651 struct atom_smu_info_v3_3 *smu_info = NULL;
654 return BP_RESULT_BADINPUT;
656 if (!DATA_TABLES(dce_info))
657 return BP_RESULT_BADBIOSTABLE;
659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
660 DATA_TABLES(dce_info));
662 return BP_RESULT_BADBIOSTABLE;
665 ss_info->type.STEP_AND_DELAY_INFO = false;
666 ss_info->spread_percentage_divider = 1000;
667 /* BIOS no longer uses target clock. Always enable for now */
668 ss_info->target_clock_range = 0xffffffff;
671 case AS_SIGNAL_TYPE_DVI:
672 ss_info->spread_spectrum_percentage =
673 disp_cntl_tbl->dvi_ss_percentage;
674 ss_info->spread_spectrum_range =
675 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
677 ss_info->type.CENTER_MODE = true;
679 case AS_SIGNAL_TYPE_HDMI:
680 ss_info->spread_spectrum_percentage =
681 disp_cntl_tbl->hdmi_ss_percentage;
682 ss_info->spread_spectrum_range =
683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
685 ss_info->type.CENTER_MODE = true;
687 /* TODO LVDS not support anymore? */
688 case AS_SIGNAL_TYPE_DISPLAY_PORT:
689 ss_info->spread_spectrum_percentage =
690 disp_cntl_tbl->dp_ss_percentage;
691 ss_info->spread_spectrum_range =
692 disp_cntl_tbl->dp_ss_rate_10hz * 10;
693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
694 ss_info->type.CENTER_MODE = true;
696 case AS_SIGNAL_TYPE_GPU_PLL:
697 /* atom_firmware: DAL only get data from dce_info table.
698 * if data within smu_info is needed for DAL, VBIOS should
699 * copy it into dce_info
701 result = BP_RESULT_UNSUPPORTED;
703 case AS_SIGNAL_TYPE_XGMI:
704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
705 DATA_TABLES(smu_info));
707 return BP_RESULT_BADBIOSTABLE;
709 ss_info->spread_spectrum_percentage =
710 smu_info->waflclk_ss_percentage;
711 ss_info->spread_spectrum_range =
712 smu_info->gpuclk_ss_rate_10hz * 10;
713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
714 ss_info->type.CENTER_MODE = true;
717 result = BP_RESULT_UNSUPPORTED;
723 static enum bp_result get_ss_info_v4_2(
724 struct bios_parser *bp,
727 struct spread_spectrum_info *ss_info)
729 enum bp_result result = BP_RESULT_OK;
730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
731 struct atom_smu_info_v3_1 *smu_info = NULL;
734 return BP_RESULT_BADINPUT;
736 if (!DATA_TABLES(dce_info))
737 return BP_RESULT_BADBIOSTABLE;
739 if (!DATA_TABLES(smu_info))
740 return BP_RESULT_BADBIOSTABLE;
742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
743 DATA_TABLES(dce_info));
745 return BP_RESULT_BADBIOSTABLE;
747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
749 return BP_RESULT_BADBIOSTABLE;
751 ss_info->type.STEP_AND_DELAY_INFO = false;
752 ss_info->spread_percentage_divider = 1000;
753 /* BIOS no longer uses target clock. Always enable for now */
754 ss_info->target_clock_range = 0xffffffff;
757 case AS_SIGNAL_TYPE_DVI:
758 ss_info->spread_spectrum_percentage =
759 disp_cntl_tbl->dvi_ss_percentage;
760 ss_info->spread_spectrum_range =
761 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
763 ss_info->type.CENTER_MODE = true;
765 case AS_SIGNAL_TYPE_HDMI:
766 ss_info->spread_spectrum_percentage =
767 disp_cntl_tbl->hdmi_ss_percentage;
768 ss_info->spread_spectrum_range =
769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
771 ss_info->type.CENTER_MODE = true;
773 /* TODO LVDS not support anymore? */
774 case AS_SIGNAL_TYPE_DISPLAY_PORT:
775 ss_info->spread_spectrum_percentage =
776 smu_info->gpuclk_ss_percentage;
777 ss_info->spread_spectrum_range =
778 smu_info->gpuclk_ss_rate_10hz * 10;
779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
780 ss_info->type.CENTER_MODE = true;
782 case AS_SIGNAL_TYPE_GPU_PLL:
783 /* atom_firmware: DAL only get data from dce_info table.
784 * if data within smu_info is needed for DAL, VBIOS should
785 * copy it into dce_info
787 result = BP_RESULT_UNSUPPORTED;
790 result = BP_RESULT_UNSUPPORTED;
797 * bios_parser_get_spread_spectrum_info
798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
802 * there is only one entry for each signal /ss id. However, there is
803 * no planning of supporting multiple spread Sprectum entry for EverGreen
805 * @param [in] signal, ASSignalType to be converted to info index
806 * @param [in] index, number of entries that match the converted info index
807 * @param [out] ss_info, sprectrum information structure,
808 * @return Bios parser result code
810 static enum bp_result bios_parser_get_spread_spectrum_info(
812 enum as_signal_type signal,
814 struct spread_spectrum_info *ss_info)
816 struct bios_parser *bp = BP_FROM_DCB(dcb);
817 enum bp_result result = BP_RESULT_UNSUPPORTED;
818 struct atom_common_table_header *header;
819 struct atom_data_revision tbl_revision;
821 if (!ss_info) /* check for bad input */
822 return BP_RESULT_BADINPUT;
824 if (!DATA_TABLES(dce_info))
825 return BP_RESULT_UNSUPPORTED;
827 header = GET_IMAGE(struct atom_common_table_header,
828 DATA_TABLES(dce_info));
829 get_atom_data_table_revision(header, &tbl_revision);
831 switch (tbl_revision.major) {
833 switch (tbl_revision.minor) {
835 return get_ss_info_v4_1(bp, signal, index, ss_info);
837 return get_ss_info_v4_2(bp, signal, index, ss_info);
845 /* there can not be more then one entry for SS Info table */
849 static enum bp_result get_embedded_panel_info_v2_1(
850 struct bios_parser *bp,
851 struct embedded_panel_info *info)
853 struct lcd_info_v2_1 *lvds;
856 return BP_RESULT_BADINPUT;
858 if (!DATA_TABLES(lcd_info))
859 return BP_RESULT_UNSUPPORTED;
861 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
864 return BP_RESULT_BADBIOSTABLE;
866 /* TODO: previous vv1_3, should v2_1 */
867 if (!((lvds->table_header.format_revision == 2)
868 && (lvds->table_header.content_revision >= 1)))
869 return BP_RESULT_UNSUPPORTED;
871 memset(info, 0, sizeof(struct embedded_panel_info));
873 /* We need to convert from 10KHz units into KHz units */
874 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
875 /* usHActive does not include borders, according to VBIOS team */
876 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
877 /* usHBlanking_Time includes borders, so we should really be
878 * subtractingborders duing this translation, but LVDS generally
879 * doesn't have borders, so we should be okay leaving this as is for
880 * now. May need to revisit if we ever have LVDS with borders
882 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
883 /* usVActive does not include borders, according to VBIOS team*/
884 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
885 /* usVBlanking_Time includes borders, so we should really be
886 * subtracting borders duing this translation, but LVDS generally
887 * doesn't have borders, so we should be okay leaving this as is for
888 * now. May need to revisit if we ever have LVDS with borders
890 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
891 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
892 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
893 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
894 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
895 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
896 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
898 /* not provided by VBIOS */
899 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
901 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
902 & ATOM_HSYNC_POLARITY);
903 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
904 & ATOM_VSYNC_POLARITY);
906 /* not provided by VBIOS */
907 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
909 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
910 & ATOM_H_REPLICATIONBY2);
911 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
912 & ATOM_V_REPLICATIONBY2);
913 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
914 & ATOM_COMPOSITESYNC);
915 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
917 /* not provided by VBIOS*/
918 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
919 /* not provided by VBIOS*/
922 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
927 static enum bp_result bios_parser_get_embedded_panel_info(
929 struct embedded_panel_info *info)
932 *bp = BP_FROM_DCB(dcb);
933 struct atom_common_table_header *header;
934 struct atom_data_revision tbl_revision;
936 if (!DATA_TABLES(lcd_info))
937 return BP_RESULT_FAILURE;
939 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
942 return BP_RESULT_BADBIOSTABLE;
944 get_atom_data_table_revision(header, &tbl_revision);
946 switch (tbl_revision.major) {
948 switch (tbl_revision.minor) {
950 return get_embedded_panel_info_v2_1(bp, info);
958 return BP_RESULT_FAILURE;
961 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
963 enum dal_device_type device_type = device_id.device_type;
964 uint32_t enum_id = device_id.enum_id;
966 switch (device_type) {
967 case DEVICE_TYPE_LCD:
970 return ATOM_DISPLAY_LCD1_SUPPORT;
975 case DEVICE_TYPE_DFP:
978 return ATOM_DISPLAY_DFP1_SUPPORT;
980 return ATOM_DISPLAY_DFP2_SUPPORT;
982 return ATOM_DISPLAY_DFP3_SUPPORT;
984 return ATOM_DISPLAY_DFP4_SUPPORT;
986 return ATOM_DISPLAY_DFP5_SUPPORT;
988 return ATOM_DISPLAY_DFP6_SUPPORT;
997 /* Unidentified device ID, return empty support mask. */
1001 static bool bios_parser_is_device_id_supported(
1002 struct dc_bios *dcb,
1003 struct device_id id)
1005 struct bios_parser *bp = BP_FROM_DCB(dcb);
1007 uint32_t mask = get_support_mask_for_device_id(id);
1009 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1013 static uint32_t bios_parser_get_ss_entry_number(
1014 struct dc_bios *dcb,
1015 enum as_signal_type signal)
1017 /* TODO: DAL2 atomfirmware implementation does not need this.
1018 * why DAL3 need this?
1023 static enum bp_result bios_parser_transmitter_control(
1024 struct dc_bios *dcb,
1025 struct bp_transmitter_control *cntl)
1027 struct bios_parser *bp = BP_FROM_DCB(dcb);
1029 if (!bp->cmd_tbl.transmitter_control)
1030 return BP_RESULT_FAILURE;
1032 return bp->cmd_tbl.transmitter_control(bp, cntl);
1035 static enum bp_result bios_parser_encoder_control(
1036 struct dc_bios *dcb,
1037 struct bp_encoder_control *cntl)
1039 struct bios_parser *bp = BP_FROM_DCB(dcb);
1041 if (!bp->cmd_tbl.dig_encoder_control)
1042 return BP_RESULT_FAILURE;
1044 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1047 static enum bp_result bios_parser_set_pixel_clock(
1048 struct dc_bios *dcb,
1049 struct bp_pixel_clock_parameters *bp_params)
1051 struct bios_parser *bp = BP_FROM_DCB(dcb);
1053 if (!bp->cmd_tbl.set_pixel_clock)
1054 return BP_RESULT_FAILURE;
1056 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1059 static enum bp_result bios_parser_set_dce_clock(
1060 struct dc_bios *dcb,
1061 struct bp_set_dce_clock_parameters *bp_params)
1063 struct bios_parser *bp = BP_FROM_DCB(dcb);
1065 if (!bp->cmd_tbl.set_dce_clock)
1066 return BP_RESULT_FAILURE;
1068 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1071 static enum bp_result bios_parser_program_crtc_timing(
1072 struct dc_bios *dcb,
1073 struct bp_hw_crtc_timing_parameters *bp_params)
1075 struct bios_parser *bp = BP_FROM_DCB(dcb);
1077 if (!bp->cmd_tbl.set_crtc_timing)
1078 return BP_RESULT_FAILURE;
1080 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1083 static enum bp_result bios_parser_enable_crtc(
1084 struct dc_bios *dcb,
1085 enum controller_id id,
1088 struct bios_parser *bp = BP_FROM_DCB(dcb);
1090 if (!bp->cmd_tbl.enable_crtc)
1091 return BP_RESULT_FAILURE;
1093 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1096 static enum bp_result bios_parser_enable_disp_power_gating(
1097 struct dc_bios *dcb,
1098 enum controller_id controller_id,
1099 enum bp_pipe_control_action action)
1101 struct bios_parser *bp = BP_FROM_DCB(dcb);
1103 if (!bp->cmd_tbl.enable_disp_power_gating)
1104 return BP_RESULT_FAILURE;
1106 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1110 static bool bios_parser_is_accelerated_mode(
1111 struct dc_bios *dcb)
1113 return bios_is_accelerated_mode(dcb);
1117 * bios_parser_set_scratch_critical_state
1120 * update critical state bit in VBIOS scratch register
1123 * bool - to set or reset state
1125 static void bios_parser_set_scratch_critical_state(
1126 struct dc_bios *dcb,
1129 bios_set_scratch_critical_state(dcb, state);
1132 static enum bp_result bios_parser_get_firmware_info(
1133 struct dc_bios *dcb,
1134 struct dc_firmware_info *info)
1136 struct bios_parser *bp = BP_FROM_DCB(dcb);
1137 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1138 struct atom_common_table_header *header;
1140 struct atom_data_revision revision;
1142 if (info && DATA_TABLES(firmwareinfo)) {
1143 header = GET_IMAGE(struct atom_common_table_header,
1144 DATA_TABLES(firmwareinfo));
1145 get_atom_data_table_revision(header, &revision);
1146 switch (revision.major) {
1148 switch (revision.minor) {
1150 result = get_firmware_info_v3_1(bp, info);
1153 result = get_firmware_info_v3_2(bp, info);
1156 result = get_firmware_info_v3_2(bp, info);
1170 static enum bp_result get_firmware_info_v3_1(
1171 struct bios_parser *bp,
1172 struct dc_firmware_info *info)
1174 struct atom_firmware_info_v3_1 *firmware_info;
1175 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1178 return BP_RESULT_BADINPUT;
1180 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1181 DATA_TABLES(firmwareinfo));
1183 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1184 DATA_TABLES(dce_info));
1186 if (!firmware_info || !dce_info)
1187 return BP_RESULT_BADBIOSTABLE;
1189 memset(info, 0, sizeof(*info));
1191 /* Pixel clock pll information. */
1192 /* We need to convert from 10KHz units into KHz units */
1193 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1194 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1196 /* 27MHz for Vega10: */
1197 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1199 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1200 if (info->pll_info.crystal_frequency == 0)
1201 info->pll_info.crystal_frequency = 27000;
1202 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1203 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1204 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1206 /* Get GPU PLL VCO Clock */
1208 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1209 /* VBIOS gives in 10KHz */
1210 info->smu_gpu_pll_output_freq =
1211 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1214 info->oem_i2c_present = false;
1216 return BP_RESULT_OK;
1219 static enum bp_result get_firmware_info_v3_2(
1220 struct bios_parser *bp,
1221 struct dc_firmware_info *info)
1223 struct atom_firmware_info_v3_2 *firmware_info;
1224 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1225 struct atom_common_table_header *header;
1226 struct atom_data_revision revision;
1227 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1228 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1231 return BP_RESULT_BADINPUT;
1233 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1234 DATA_TABLES(firmwareinfo));
1236 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1237 DATA_TABLES(dce_info));
1239 if (!firmware_info || !dce_info)
1240 return BP_RESULT_BADBIOSTABLE;
1242 memset(info, 0, sizeof(*info));
1244 header = GET_IMAGE(struct atom_common_table_header,
1245 DATA_TABLES(smu_info));
1246 get_atom_data_table_revision(header, &revision);
1248 if (revision.minor == 2) {
1250 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1251 DATA_TABLES(smu_info));
1254 return BP_RESULT_BADBIOSTABLE;
1256 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1257 } else if (revision.minor == 3) {
1259 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1260 DATA_TABLES(smu_info));
1263 return BP_RESULT_BADBIOSTABLE;
1265 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1268 // We need to convert from 10KHz units into KHz units.
1269 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1271 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1272 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1273 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1274 if (info->pll_info.crystal_frequency == 0) {
1275 if (revision.minor == 2)
1276 info->pll_info.crystal_frequency = 27000;
1277 else if (revision.minor == 3)
1278 info->pll_info.crystal_frequency = 100000;
1280 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1281 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1282 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1284 /* Get GPU PLL VCO Clock */
1285 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1286 if (revision.minor == 2)
1287 info->smu_gpu_pll_output_freq =
1288 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1289 else if (revision.minor == 3)
1290 info->smu_gpu_pll_output_freq =
1291 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1294 if (firmware_info->board_i2c_feature_id == 0x2) {
1295 info->oem_i2c_present = true;
1296 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1298 info->oem_i2c_present = false;
1301 return BP_RESULT_OK;
1304 static enum bp_result bios_parser_get_encoder_cap_info(
1305 struct dc_bios *dcb,
1306 struct graphics_object_id object_id,
1307 struct bp_encoder_cap_info *info)
1309 struct bios_parser *bp = BP_FROM_DCB(dcb);
1310 struct atom_display_object_path_v2 *object;
1311 struct atom_encoder_caps_record *record = NULL;
1314 return BP_RESULT_BADINPUT;
1316 object = get_bios_object(bp, object_id);
1319 return BP_RESULT_BADINPUT;
1321 record = get_encoder_cap_record(bp, object);
1323 return BP_RESULT_NORECORD;
1325 info->DP_HBR2_CAP = (record->encodercaps &
1326 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1327 info->DP_HBR2_EN = (record->encodercaps &
1328 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1329 info->DP_HBR3_EN = (record->encodercaps &
1330 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1331 info->HDMI_6GB_EN = (record->encodercaps &
1332 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1333 info->DP_IS_USB_C = (record->encodercaps &
1334 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1336 return BP_RESULT_OK;
1340 static struct atom_encoder_caps_record *get_encoder_cap_record(
1341 struct bios_parser *bp,
1342 struct atom_display_object_path_v2 *object)
1344 struct atom_common_record_header *header;
1348 BREAK_TO_DEBUGGER(); /* Invalid object */
1352 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1355 header = GET_IMAGE(struct atom_common_record_header, offset);
1360 offset += header->record_size;
1362 if (header->record_type == LAST_RECORD_TYPE ||
1363 !header->record_size)
1366 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1369 if (sizeof(struct atom_encoder_caps_record) <=
1370 header->record_size)
1371 return (struct atom_encoder_caps_record *)header;
1378 * get_integrated_info_v11
1381 * Get V8 integrated BIOS information
1384 * bios_parser *bp - [in]BIOS parser handler to get master data table
1385 * integrated_info *info - [out] store and output integrated info
1388 * enum bp_result - BP_RESULT_OK if information is available,
1389 * BP_RESULT_BADBIOSTABLE otherwise.
1391 static enum bp_result get_integrated_info_v11(
1392 struct bios_parser *bp,
1393 struct integrated_info *info)
1395 struct atom_integrated_system_info_v1_11 *info_v11;
1398 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1399 DATA_TABLES(integratedsysteminfo));
1401 if (info_v11 == NULL)
1402 return BP_RESULT_BADBIOSTABLE;
1404 info->gpu_cap_info =
1405 le32_to_cpu(info_v11->gpucapinfo);
1407 * system_config: Bit[0] = 0 : PCIE power gating disabled
1408 * = 1 : PCIE power gating enabled
1409 * Bit[1] = 0 : DDR-PLL shut down disabled
1410 * = 1 : DDR-PLL shut down enabled
1411 * Bit[2] = 0 : DDR-PLL power down disabled
1412 * = 1 : DDR-PLL power down enabled
1414 info->system_config = le32_to_cpu(info_v11->system_config);
1415 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1416 info->memory_type = info_v11->memorytype;
1417 info->ma_channel_number = info_v11->umachannelnumber;
1418 info->lvds_ss_percentage =
1419 le16_to_cpu(info_v11->lvds_ss_percentage);
1420 info->dp_ss_control =
1421 le16_to_cpu(info_v11->reserved1);
1422 info->lvds_sspread_rate_in_10hz =
1423 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1424 info->hdmi_ss_percentage =
1425 le16_to_cpu(info_v11->hdmi_ss_percentage);
1426 info->hdmi_sspread_rate_in_10hz =
1427 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1428 info->dvi_ss_percentage =
1429 le16_to_cpu(info_v11->dvi_ss_percentage);
1430 info->dvi_sspread_rate_in_10_hz =
1431 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1432 info->lvds_misc = info_v11->lvds_misc;
1433 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1434 info->ext_disp_conn_info.gu_id[i] =
1435 info_v11->extdispconninfo.guid[i];
1438 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1439 info->ext_disp_conn_info.path[i].device_connector_id =
1440 object_id_from_bios_object_id(
1441 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1443 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1444 object_id_from_bios_object_id(
1446 info_v11->extdispconninfo.path[i].ext_encoder_objid));
1448 info->ext_disp_conn_info.path[i].device_tag =
1450 info_v11->extdispconninfo.path[i].device_tag);
1451 info->ext_disp_conn_info.path[i].device_acpi_enum =
1453 info_v11->extdispconninfo.path[i].device_acpi_enum);
1454 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1455 info_v11->extdispconninfo.path[i].auxddclut_index;
1456 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1457 info_v11->extdispconninfo.path[i].hpdlut_index;
1458 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1459 info_v11->extdispconninfo.path[i].channelmapping;
1460 info->ext_disp_conn_info.path[i].caps =
1461 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1463 info->ext_disp_conn_info.checksum =
1464 info_v11->extdispconninfo.checksum;
1466 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1467 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1468 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1469 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1470 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1471 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1472 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1474 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1475 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1476 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1477 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1478 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1479 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1482 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1483 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1484 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1485 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1486 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1487 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1488 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1490 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1491 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1492 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1493 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1494 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1495 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1498 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1499 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1500 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1501 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1502 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1503 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1504 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1506 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1507 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1508 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1509 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1510 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1511 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1514 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1515 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1516 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1517 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1518 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1519 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1520 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1522 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1523 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1524 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1525 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1526 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1527 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1531 /** TODO - review **/
1533 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1535 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1536 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1538 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1539 /* Convert [10KHz] into [KHz] */
1540 info->disp_clk_voltage[i].max_supported_clk =
1541 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1542 ulMaximumSupportedCLK) * 10;
1543 info->disp_clk_voltage[i].voltage_index =
1544 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1547 info->boot_up_req_display_vector =
1548 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1549 info->boot_up_nb_voltage =
1550 le16_to_cpu(info_v11->usBootUpNBVoltage);
1551 info->ext_disp_conn_info_offset =
1552 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1553 info->gmc_restore_reset_time =
1554 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1555 info->minimum_n_clk =
1556 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1557 for (i = 1; i < 4; ++i)
1558 info->minimum_n_clk =
1559 info->minimum_n_clk <
1560 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1561 info->minimum_n_clk : le32_to_cpu(
1562 info_v11->ulNbpStateNClkFreq[i]);
1564 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1565 info->ddr_dll_power_up_time =
1566 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1567 info->ddr_pll_power_up_time =
1568 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1569 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1570 info->max_lvds_pclk_freq_in_single_link =
1571 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1572 info->max_lvds_pclk_freq_in_single_link =
1573 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1574 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1575 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1576 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1577 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1578 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1579 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1580 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1581 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1582 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1583 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1584 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1585 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1586 info->lvds_off_to_on_delay_in_4ms =
1587 info_v11->ucLVDSOffToOnDelay_in4Ms;
1588 info->lvds_bit_depth_control_val =
1589 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1591 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1592 /* Convert [10KHz] into [KHz] */
1593 info->avail_s_clk[i].supported_s_clk =
1594 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1596 info->avail_s_clk[i].voltage_index =
1597 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1598 info->avail_s_clk[i].voltage_id =
1599 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1603 return BP_RESULT_OK;
1608 * construct_integrated_info
1611 * Get integrated BIOS information based on table revision
1614 * bios_parser *bp - [in]BIOS parser handler to get master data table
1615 * integrated_info *info - [out] store and output integrated info
1618 * enum bp_result - BP_RESULT_OK if information is available,
1619 * BP_RESULT_BADBIOSTABLE otherwise.
1621 static enum bp_result construct_integrated_info(
1622 struct bios_parser *bp,
1623 struct integrated_info *info)
1625 enum bp_result result = BP_RESULT_BADBIOSTABLE;
1627 struct atom_common_table_header *header;
1628 struct atom_data_revision revision;
1632 if (info && DATA_TABLES(integratedsysteminfo)) {
1633 header = GET_IMAGE(struct atom_common_table_header,
1634 DATA_TABLES(integratedsysteminfo));
1636 get_atom_data_table_revision(header, &revision);
1638 /* Don't need to check major revision as they are all 1 */
1639 switch (revision.minor) {
1641 result = get_integrated_info_v11(bp, info);
1648 if (result != BP_RESULT_OK)
1651 /* Sort voltage table from low to high*/
1652 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1653 for (j = i; j > 0; --j) {
1654 if (info->disp_clk_voltage[j].max_supported_clk <
1655 info->disp_clk_voltage[j-1].max_supported_clk
1657 /* swap j and j - 1*/
1658 swap(info->disp_clk_voltage[j - 1],
1659 info->disp_clk_voltage[j]);
1667 static struct integrated_info *bios_parser_create_integrated_info(
1668 struct dc_bios *dcb)
1670 struct bios_parser *bp = BP_FROM_DCB(dcb);
1671 struct integrated_info *info = NULL;
1673 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
1680 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
1688 static enum bp_result update_slot_layout_info(
1689 struct dc_bios *dcb,
1691 struct slot_layout_info *slot_layout_info)
1693 unsigned int record_offset;
1695 struct atom_display_object_path_v2 *object;
1696 struct atom_bracket_layout_record *record;
1697 struct atom_common_record_header *record_header;
1698 enum bp_result result;
1699 struct bios_parser *bp;
1700 struct object_info_table *tbl;
1701 struct display_object_info_table_v1_4 *v1_4;
1704 record_header = NULL;
1705 result = BP_RESULT_NORECORD;
1707 bp = BP_FROM_DCB(dcb);
1708 tbl = &bp->object_info_tbl;
1711 object = &v1_4->display_path[i];
1712 record_offset = (unsigned int)
1713 (object->disp_recordoffset) +
1714 (unsigned int)(bp->object_info_tbl_offset);
1718 record_header = (struct atom_common_record_header *)
1719 GET_IMAGE(struct atom_common_record_header,
1721 if (record_header == NULL) {
1722 result = BP_RESULT_BADBIOSTABLE;
1726 /* the end of the list */
1727 if (record_header->record_type == 0xff ||
1728 record_header->record_size == 0) {
1732 if (record_header->record_type ==
1733 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
1734 sizeof(struct atom_bracket_layout_record)
1735 <= record_header->record_size) {
1736 record = (struct atom_bracket_layout_record *)
1738 result = BP_RESULT_OK;
1742 record_offset += record_header->record_size;
1745 /* return if the record not found */
1746 if (result != BP_RESULT_OK)
1749 /* get slot sizes */
1750 slot_layout_info->length = record->bracketlen;
1751 slot_layout_info->width = record->bracketwidth;
1753 /* get info for each connector in the slot */
1754 slot_layout_info->num_of_connectors = record->conn_num;
1755 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
1756 slot_layout_info->connectors[j].connector_type =
1757 (enum connector_layout_type)
1758 (record->conn_info[j].connector_type);
1759 switch (record->conn_info[j].connector_type) {
1760 case CONNECTOR_TYPE_DVI_D:
1761 slot_layout_info->connectors[j].connector_type =
1762 CONNECTOR_LAYOUT_TYPE_DVI_D;
1763 slot_layout_info->connectors[j].length =
1767 case CONNECTOR_TYPE_HDMI:
1768 slot_layout_info->connectors[j].connector_type =
1769 CONNECTOR_LAYOUT_TYPE_HDMI;
1770 slot_layout_info->connectors[j].length =
1771 CONNECTOR_SIZE_HDMI;
1774 case CONNECTOR_TYPE_DISPLAY_PORT:
1775 slot_layout_info->connectors[j].connector_type =
1776 CONNECTOR_LAYOUT_TYPE_DP;
1777 slot_layout_info->connectors[j].length =
1781 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
1782 slot_layout_info->connectors[j].connector_type =
1783 CONNECTOR_LAYOUT_TYPE_MINI_DP;
1784 slot_layout_info->connectors[j].length =
1785 CONNECTOR_SIZE_MINI_DP;
1789 slot_layout_info->connectors[j].connector_type =
1790 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
1791 slot_layout_info->connectors[j].length =
1792 CONNECTOR_SIZE_UNKNOWN;
1795 slot_layout_info->connectors[j].position =
1796 record->conn_info[j].position;
1797 slot_layout_info->connectors[j].connector_id =
1798 object_id_from_bios_object_id(
1799 record->conn_info[j].connectorobjid);
1805 static enum bp_result get_bracket_layout_record(
1806 struct dc_bios *dcb,
1807 unsigned int bracket_layout_id,
1808 struct slot_layout_info *slot_layout_info)
1811 struct bios_parser *bp = BP_FROM_DCB(dcb);
1812 enum bp_result result;
1813 struct object_info_table *tbl;
1814 struct display_object_info_table_v1_4 *v1_4;
1816 if (slot_layout_info == NULL) {
1817 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
1818 return BP_RESULT_BADINPUT;
1820 tbl = &bp->object_info_tbl;
1823 result = BP_RESULT_NORECORD;
1824 for (i = 0; i < v1_4->number_of_path; ++i) {
1826 if (bracket_layout_id ==
1827 v1_4->display_path[i].display_objid) {
1828 result = update_slot_layout_info(dcb, i,
1836 static enum bp_result bios_get_board_layout_info(
1837 struct dc_bios *dcb,
1838 struct board_layout_info *board_layout_info)
1841 struct bios_parser *bp;
1842 enum bp_result record_result;
1844 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
1845 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
1846 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
1850 bp = BP_FROM_DCB(dcb);
1851 if (board_layout_info == NULL) {
1852 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
1853 return BP_RESULT_BADINPUT;
1856 board_layout_info->num_of_slots = 0;
1858 for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
1859 record_result = get_bracket_layout_record(dcb,
1860 slot_index_to_vbios_id[i],
1861 &board_layout_info->slots[i]);
1863 if (record_result == BP_RESULT_NORECORD && i > 0)
1864 break; /* no more slots present in bios */
1865 else if (record_result != BP_RESULT_OK)
1866 return record_result; /* fail */
1868 ++board_layout_info->num_of_slots;
1871 /* all data is valid */
1872 board_layout_info->is_number_of_slots_valid = 1;
1873 board_layout_info->is_slots_size_valid = 1;
1874 board_layout_info->is_connector_offsets_valid = 1;
1875 board_layout_info->is_connector_lengths_valid = 1;
1877 return BP_RESULT_OK;
1880 static const struct dc_vbios_funcs vbios_funcs = {
1881 .get_connectors_number = bios_parser_get_connectors_number,
1883 .get_connector_id = bios_parser_get_connector_id,
1885 .get_src_obj = bios_parser_get_src_obj,
1887 .get_i2c_info = bios_parser_get_i2c_info,
1889 .get_hpd_info = bios_parser_get_hpd_info,
1891 .get_device_tag = bios_parser_get_device_tag,
1893 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
1895 .get_ss_entry_number = bios_parser_get_ss_entry_number,
1897 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
1899 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
1901 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
1903 .is_device_id_supported = bios_parser_is_device_id_supported,
1905 .is_accelerated_mode = bios_parser_is_accelerated_mode,
1907 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
1911 .encoder_control = bios_parser_encoder_control,
1913 .transmitter_control = bios_parser_transmitter_control,
1915 .enable_crtc = bios_parser_enable_crtc,
1917 .set_pixel_clock = bios_parser_set_pixel_clock,
1919 .set_dce_clock = bios_parser_set_dce_clock,
1921 .program_crtc_timing = bios_parser_program_crtc_timing,
1923 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
1925 .bios_parser_destroy = firmware_parser_destroy,
1927 .get_board_layout_info = bios_get_board_layout_info,
1930 static bool bios_parser_construct(
1931 struct bios_parser *bp,
1932 struct bp_init_data *init,
1933 enum dce_version dce_version)
1935 uint16_t *rom_header_offset = NULL;
1936 struct atom_rom_header_v2_2 *rom_header = NULL;
1937 struct display_object_info_table_v1_4 *object_info_tbl;
1938 struct atom_data_revision tbl_rev = {0};
1946 bp->base.funcs = &vbios_funcs;
1947 bp->base.bios = init->bios;
1948 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
1950 bp->base.ctx = init->ctx;
1952 bp->base.bios_local_image = NULL;
1955 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
1957 if (!rom_header_offset)
1960 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
1965 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
1966 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
1969 bp->master_data_tbl =
1970 GET_IMAGE(struct atom_master_data_table_v2_1,
1971 rom_header->masterdatatable_offset);
1973 if (!bp->master_data_tbl)
1976 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
1978 if (!bp->object_info_tbl_offset)
1982 GET_IMAGE(struct display_object_info_table_v1_4,
1983 bp->object_info_tbl_offset);
1985 if (!object_info_tbl)
1988 get_atom_data_table_revision(&object_info_tbl->table_header,
1989 &bp->object_info_tbl.revision);
1991 if (bp->object_info_tbl.revision.major == 1
1992 && bp->object_info_tbl.revision.minor >= 4) {
1993 struct display_object_info_table_v1_4 *tbl_v1_4;
1995 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
1996 bp->object_info_tbl_offset);
2000 bp->object_info_tbl.v1_4 = tbl_v1_4;
2004 dal_firmware_parser_init_cmd_tbl(bp);
2005 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
2007 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
2008 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2013 struct dc_bios *firmware_parser_create(
2014 struct bp_init_data *init,
2015 enum dce_version dce_version)
2017 struct bios_parser *bp = NULL;
2019 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2023 if (bios_parser_construct(bp, init, dce_version))