drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24 #include <linux/string.h>
  25 #include <linux/acpi.h>
  26
  27 #include <drm/drm_probe_helper.h>
  28 #include <drm/amdgpu_drm.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_irq.h"
  33 #include "amdgpu_pm.h"
  34 #include "dm_pp_smu.h"
  35 #include "amdgpu_smu.h"
  36
  37
  38 bool dm_pp_apply_display_requirements(
  39                 const struct dc_context *ctx,
  40                 const struct dm_pp_display_configuration *pp_display_cfg)
  41 {
  42         struct amdgpu_device *adev = ctx->driver_context;
  43         struct smu_context *smu = &adev->smu;
  44         int i;
  45
  46         if (adev->pm.dpm_enabled) {
  47
  48                 memset(&adev->pm.pm_display_cfg, 0,
  49                                 sizeof(adev->pm.pm_display_cfg));
  50
  51                 adev->pm.pm_display_cfg.cpu_cc6_disable =
  52                         pp_display_cfg->cpu_cc6_disable;
  53
  54                 adev->pm.pm_display_cfg.cpu_pstate_disable =
  55                         pp_display_cfg->cpu_pstate_disable;
  56
  57                 adev->pm.pm_display_cfg.cpu_pstate_separation_time =
  58                         pp_display_cfg->cpu_pstate_separation_time;
  59
  60                 adev->pm.pm_display_cfg.nb_pstate_switch_disable =
  61                         pp_display_cfg->nb_pstate_switch_disable;
  62
  63                 adev->pm.pm_display_cfg.num_display =
  64                                 pp_display_cfg->display_count;
  65                 adev->pm.pm_display_cfg.num_path_including_non_display =
  66                                 pp_display_cfg->display_count;
  67
  68                 adev->pm.pm_display_cfg.min_core_set_clock =
  69                                 pp_display_cfg->min_engine_clock_khz/10;
  70                 adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
  71                                 pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
  72                 adev->pm.pm_display_cfg.min_mem_set_clock =
  73                                 pp_display_cfg->min_memory_clock_khz/10;
  74
  75                 adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk =
  76                                 pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
  77                 adev->pm.pm_display_cfg.min_dcef_set_clk =
  78                                 pp_display_cfg->min_dcfclock_khz/10;
  79
  80                 adev->pm.pm_display_cfg.multi_monitor_in_sync =
  81                                 pp_display_cfg->all_displays_in_sync;
  82                 adev->pm.pm_display_cfg.min_vblank_time =
  83                                 pp_display_cfg->avail_mclk_switch_time_us;
  84
  85                 adev->pm.pm_display_cfg.display_clk =
  86                                 pp_display_cfg->disp_clk_khz/10;
  87
  88                 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
  89                                 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
  90
  91                 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
  92                 adev->pm.pm_display_cfg.line_time_in_us =
  93                                 pp_display_cfg->line_time_in_us;
  94
  95                 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
  96                 adev->pm.pm_display_cfg.crossfire_display_index = -1;
  97                 adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
  98
  99                 for (i = 0; i < pp_display_cfg->display_count; i++) {
 100                         const struct dm_pp_single_disp_config *dc_cfg =
 101                                                 &pp_display_cfg->disp_configs[i];
 102                         adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
 103                 }
 104
 105                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_configuration_change)
 106                         adev->powerplay.pp_funcs->display_configuration_change(
 107                                 adev->powerplay.pp_handle,
 108                                 &adev->pm.pm_display_cfg);
 109                 else if (adev->smu.ppt_funcs)
 110                         smu_display_configuration_change(smu,
 111                                                          &adev->pm.pm_display_cfg);
 112
 113                 amdgpu_pm_compute_clocks(adev);
 114         }
 115
 116         return true;
 117 }
 118
 119 static void get_default_clock_levels(
 120                 enum dm_pp_clock_type clk_type,
 121                 struct dm_pp_clock_levels *clks)
 122 {
 123         uint32_t disp_clks_in_khz[6] = {
 124                         300000, 400000, 496560, 626090, 685720, 757900 };
 125         uint32_t sclks_in_khz[6] = {
 126                         300000, 360000, 423530, 514290, 626090, 720000 };
 127         uint32_t mclks_in_khz[2] = { 333000, 800000 };
 128
 129         switch (clk_type) {
 130         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 131                 clks->num_levels = 6;
 132                 memmove(clks->clocks_in_khz, disp_clks_in_khz,
 133                                 sizeof(disp_clks_in_khz));
 134                 break;
 135         case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 136                 clks->num_levels = 6;
 137                 memmove(clks->clocks_in_khz, sclks_in_khz,
 138                                 sizeof(sclks_in_khz));
 139                 break;
 140         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 141                 clks->num_levels = 2;
 142                 memmove(clks->clocks_in_khz, mclks_in_khz,
 143                                 sizeof(mclks_in_khz));
 144                 break;
 145         default:
 146                 clks->num_levels = 0;
 147                 break;
 148         }
 149 }
 150
 151 static enum smu_clk_type dc_to_smu_clock_type(
 152                 enum dm_pp_clock_type dm_pp_clk_type)
 153 {
 154         enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
 155
 156         switch (dm_pp_clk_type) {
 157         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 158                 smu_clk_type = SMU_DISPCLK;
 159                 break;
 160         case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 161                 smu_clk_type = SMU_GFXCLK;
 162                 break;
 163         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 164                 smu_clk_type = SMU_MCLK;
 165                 break;
 166         case DM_PP_CLOCK_TYPE_DCEFCLK:
 167                 smu_clk_type = SMU_DCEFCLK;
 168                 break;
 169         case DM_PP_CLOCK_TYPE_SOCCLK:
 170                 smu_clk_type = SMU_SOCCLK;
 171                 break;
 172         default:
 173                 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
 174                           dm_pp_clk_type);
 175                 break;
 176         }
 177
 178         return smu_clk_type;
 179 }
 180
 181 static enum amd_pp_clock_type dc_to_pp_clock_type(
 182                 enum dm_pp_clock_type dm_pp_clk_type)
 183 {
 184         enum amd_pp_clock_type amd_pp_clk_type = 0;
 185
 186         switch (dm_pp_clk_type) {
 187         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 188                 amd_pp_clk_type = amd_pp_disp_clock;
 189                 break;
 190         case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 191                 amd_pp_clk_type = amd_pp_sys_clock;
 192                 break;
 193         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 194                 amd_pp_clk_type = amd_pp_mem_clock;
 195                 break;
 196         case DM_PP_CLOCK_TYPE_DCEFCLK:
 197                 amd_pp_clk_type  = amd_pp_dcef_clock;
 198                 break;
 199         case DM_PP_CLOCK_TYPE_DCFCLK:
 200                 amd_pp_clk_type = amd_pp_dcf_clock;
 201                 break;
 202         case DM_PP_CLOCK_TYPE_PIXELCLK:
 203                 amd_pp_clk_type = amd_pp_pixel_clock;
 204                 break;
 205         case DM_PP_CLOCK_TYPE_FCLK:
 206                 amd_pp_clk_type = amd_pp_f_clock;
 207                 break;
 208         case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
 209                 amd_pp_clk_type = amd_pp_phy_clock;
 210                 break;
 211         case DM_PP_CLOCK_TYPE_DPPCLK:
 212                 amd_pp_clk_type = amd_pp_dpp_clock;
 213                 break;
 214         default:
 215                 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
 216                                 dm_pp_clk_type);
 217                 break;
 218         }
 219
 220         return amd_pp_clk_type;
 221 }
 222
 223 static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
 224                         enum PP_DAL_POWERLEVEL max_clocks_state)
 225 {
 226         switch (max_clocks_state) {
 227         case PP_DAL_POWERLEVEL_0:
 228                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;
 229         case PP_DAL_POWERLEVEL_1:
 230                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;
 231         case PP_DAL_POWERLEVEL_2:
 232                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;
 233         case PP_DAL_POWERLEVEL_3:
 234                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;
 235         case PP_DAL_POWERLEVEL_4:
 236                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
 237         case PP_DAL_POWERLEVEL_5:
 238                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
 239         case PP_DAL_POWERLEVEL_6:
 240                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
 241         case PP_DAL_POWERLEVEL_7:
 242                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
 243         default:
 244                 DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",
 245                                 max_clocks_state);
 246                 return DM_PP_CLOCKS_STATE_INVALID;
 247         }
 248 }
 249
 250 static void pp_to_dc_clock_levels(
 251                 const struct amd_pp_clocks *pp_clks,
 252                 struct dm_pp_clock_levels *dc_clks,
 253                 enum dm_pp_clock_type dc_clk_type)
 254 {
 255         uint32_t i;
 256
 257         if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
 258                 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 259                                 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 260                                 pp_clks->count,
 261                                 DM_PP_MAX_CLOCK_LEVELS);
 262
 263                 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 264         } else
 265                 dc_clks->num_levels = pp_clks->count;
 266
 267         DRM_INFO("DM_PPLIB: values for %s clock\n",
 268                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 269
 270         for (i = 0; i < dc_clks->num_levels; i++) {
 271                 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
 272                 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
 273         }
 274 }
 275
 276 static void pp_to_dc_clock_levels_with_latency(
 277                 const struct pp_clock_levels_with_latency *pp_clks,
 278                 struct dm_pp_clock_levels_with_latency *clk_level_info,
 279                 enum dm_pp_clock_type dc_clk_type)
 280 {
 281         uint32_t i;
 282
 283         if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
 284                 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 285                                 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 286                                 pp_clks->num_levels,
 287                                 DM_PP_MAX_CLOCK_LEVELS);
 288
 289                 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 290         } else
 291                 clk_level_info->num_levels = pp_clks->num_levels;
 292
 293         DRM_DEBUG("DM_PPLIB: values for %s clock\n",
 294                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 295
 296         for (i = 0; i < clk_level_info->num_levels; i++) {
 297                 DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
 298                 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
 299                 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
 300         }
 301 }
 302
 303 static void pp_to_dc_clock_levels_with_voltage(
 304                 const struct pp_clock_levels_with_voltage *pp_clks,
 305                 struct dm_pp_clock_levels_with_voltage *clk_level_info,
 306                 enum dm_pp_clock_type dc_clk_type)
 307 {
 308         uint32_t i;
 309
 310         if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
 311                 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 312                                 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 313                                 pp_clks->num_levels,
 314                                 DM_PP_MAX_CLOCK_LEVELS);
 315
 316                 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 317         } else
 318                 clk_level_info->num_levels = pp_clks->num_levels;
 319
 320         DRM_INFO("DM_PPLIB: values for %s clock\n",
 321                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 322
 323         for (i = 0; i < clk_level_info->num_levels; i++) {
 324                 DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
 325                          pp_clks->data[i].voltage_in_mv);
 326                 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
 327                 clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
 328         }
 329 }
 330
 331 bool dm_pp_get_clock_levels_by_type(
 332                 const struct dc_context *ctx,
 333                 enum dm_pp_clock_type clk_type,
 334                 struct dm_pp_clock_levels *dc_clks)
 335 {
 336         struct amdgpu_device *adev = ctx->driver_context;
 337         void *pp_handle = adev->powerplay.pp_handle;
 338         struct amd_pp_clocks pp_clks = { 0 };
 339         struct amd_pp_simple_clock_info validation_clks = { 0 };
 340         uint32_t i;
 341
 342         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {
 343                 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
 344                         dc_to_pp_clock_type(clk_type), &pp_clks)) {
 345                         /* Error in pplib. Provide default values. */
 346                         get_default_clock_levels(clk_type, dc_clks);
 347                         return true;
 348                 }
 349         }
 350
 351         pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
 352
 353         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
 354                 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
 355                                                 pp_handle, &validation_clks)) {
 356                         /* Error in pplib. Provide default values. */
 357                         DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
 358                         validation_clks.engine_max_clock = 72000;
 359                         validation_clks.memory_max_clock = 80000;
 360                         validation_clks.level = 0;
 361                 }
 362         }
 363
 364         DRM_INFO("DM_PPLIB: Validation clocks:\n");
 365         DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
 366                         validation_clks.engine_max_clock);
 367         DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
 368                         validation_clks.memory_max_clock);
 369         DRM_INFO("DM_PPLIB:    level           : %d\n",
 370                         validation_clks.level);
 371
 372         /* Translate 10 kHz to kHz. */
 373         validation_clks.engine_max_clock *= 10;
 374         validation_clks.memory_max_clock *= 10;
 375
 376         /* Determine the highest non-boosted level from the Validation Clocks */
 377         if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
 378                 for (i = 0; i < dc_clks->num_levels; i++) {
 379                         if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
 380                                 /* This clock is higher the validation clock.
 381                                  * Than means the previous one is the highest
 382                                  * non-boosted one. */
 383                                 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
 384                                                 dc_clks->num_levels, i);
 385                                 dc_clks->num_levels = i > 0 ? i : 1;
 386                                 break;
 387                         }
 388                 }
 389         } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
 390                 for (i = 0; i < dc_clks->num_levels; i++) {
 391                         if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
 392                                 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
 393                                                 dc_clks->num_levels, i);
 394                                 dc_clks->num_levels = i > 0 ? i : 1;
 395                                 break;
 396                         }
 397                 }
 398         }
 399
 400         return true;
 401 }
 402
 403 bool dm_pp_get_clock_levels_by_type_with_latency(
 404         const struct dc_context *ctx,
 405         enum dm_pp_clock_type clk_type,
 406         struct dm_pp_clock_levels_with_latency *clk_level_info)
 407 {
 408         struct amdgpu_device *adev = ctx->driver_context;
 409         void *pp_handle = adev->powerplay.pp_handle;
 410         struct pp_clock_levels_with_latency pp_clks = { 0 };
 411         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 412         int ret;
 413
 414         if (pp_funcs && pp_funcs->get_clock_by_type_with_latency) {
 415                 ret = pp_funcs->get_clock_by_type_with_latency(pp_handle,
 416                                                 dc_to_pp_clock_type(clk_type),
 417                                                 &pp_clks);
 418                 if (ret)
 419                         return false;
 420         } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
 421                 if (smu_get_clock_by_type_with_latency(&adev->smu,
 422                                                        dc_to_smu_clock_type(clk_type),
 423                                                        &pp_clks))
 424                         return false;
 425         }
 426
 427
 428         pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
 429
 430         return true;
 431 }
 432
 433 bool dm_pp_get_clock_levels_by_type_with_voltage(
 434         const struct dc_context *ctx,
 435         enum dm_pp_clock_type clk_type,
 436         struct dm_pp_clock_levels_with_voltage *clk_level_info)
 437 {
 438         struct amdgpu_device *adev = ctx->driver_context;
 439         void *pp_handle = adev->powerplay.pp_handle;
 440         struct pp_clock_levels_with_voltage pp_clk_info = {0};
 441         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 442         int ret;
 443
 444         if (pp_funcs && pp_funcs->get_clock_by_type_with_voltage) {
 445                 ret = pp_funcs->get_clock_by_type_with_voltage(pp_handle,
 446                                                 dc_to_pp_clock_type(clk_type),
 447                                                 &pp_clk_info);
 448                 if (ret)
 449                         return false;
 450         }
 451
 452         pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
 453
 454         return true;
 455 }
 456
 457 bool dm_pp_notify_wm_clock_changes(
 458         const struct dc_context *ctx,
 459         struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
 460 {
 461         struct amdgpu_device *adev = ctx->driver_context;
 462         void *pp_handle = adev->powerplay.pp_handle;
 463         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 464
 465         /*
 466          * Limit this watermark setting for Polaris for now
 467          * TODO: expand this to other ASICs
 468          */
 469         if ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_VEGAM)
 470              && pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) {
 471                 if (!pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
 472                                                 (void *)wm_with_clock_ranges))
 473                         return true;
 474         }
 475
 476         return false;
 477 }
 478
 479 bool dm_pp_apply_power_level_change_request(
 480         const struct dc_context *ctx,
 481         struct dm_pp_power_level_change_request *level_change_req)
 482 {
 483         /* TODO: to be implemented */
 484         return false;
 485 }
 486
 487 bool dm_pp_apply_clock_for_voltage_request(
 488         const struct dc_context *ctx,
 489         struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
 490 {
 491         struct amdgpu_device *adev = ctx->driver_context;
 492         struct pp_display_clock_request pp_clock_request = {0};
 493         int ret = 0;
 494
 495         pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
 496         pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
 497
 498         if (!pp_clock_request.clock_type)
 499                 return false;
 500
 501         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_clock_voltage_request)
 502                 ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
 503                         adev->powerplay.pp_handle,
 504                         &pp_clock_request);
 505         else if (adev->smu.ppt_funcs &&
 506                  adev->smu.ppt_funcs->display_clock_voltage_request)
 507                 ret = smu_display_clock_voltage_request(&adev->smu,
 508                                                         &pp_clock_request);
 509         if (ret)
 510                 return false;
 511         return true;
 512 }
 513
 514 bool dm_pp_get_static_clocks(
 515         const struct dc_context *ctx,
 516         struct dm_pp_static_clock_info *static_clk_info)
 517 {
 518         struct amdgpu_device *adev = ctx->driver_context;
 519         struct amd_pp_clock_info pp_clk_info = {0};
 520         int ret = 0;
 521
 522         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_current_clocks)
 523                 ret = adev->powerplay.pp_funcs->get_current_clocks(
 524                         adev->powerplay.pp_handle,
 525                         &pp_clk_info);
 526         else
 527                 return false;
 528         if (ret)
 529                 return false;
 530
 531         static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
 532         static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
 533         static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
 534
 535         return true;
 536 }
 537
 538 static void pp_rv_set_wm_ranges(struct pp_smu *pp,
 539                 struct pp_smu_wm_range_sets *ranges)
 540 {
 541         const struct dc_context *ctx = pp->dm;
 542         struct amdgpu_device *adev = ctx->driver_context;
 543         void *pp_handle = adev->powerplay.pp_handle;
 544         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 545         struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
 546         struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges;
 547         struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges;
 548         int32_t i;
 549
 550         wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
 551         wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
 552
 553         for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
 554                 if (ranges->reader_wm_sets[i].wm_inst > 3)
 555                         wm_dce_clocks[i].wm_set_id = WM_SET_A;
 556                 else
 557                         wm_dce_clocks[i].wm_set_id =
 558                                         ranges->reader_wm_sets[i].wm_inst;
 559                 wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
 560                                 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
 561                 wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
 562                                 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
 563                 wm_dce_clocks[i].wm_max_mem_clk_in_khz =
 564                                 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
 565                 wm_dce_clocks[i].wm_min_mem_clk_in_khz =
 566                                 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
 567         }
 568
 569         for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
 570                 if (ranges->writer_wm_sets[i].wm_inst > 3)
 571                         wm_soc_clocks[i].wm_set_id = WM_SET_A;
 572                 else
 573                         wm_soc_clocks[i].wm_set_id =
 574                                         ranges->writer_wm_sets[i].wm_inst;
 575                 wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
 576                                 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
 577                 wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
 578                                 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
 579                 wm_soc_clocks[i].wm_max_mem_clk_in_khz =
 580                                 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
 581                 wm_soc_clocks[i].wm_min_mem_clk_in_khz =
 582                                 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
 583         }
 584
 585         if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
 586                 pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
 587                                                            &wm_with_clock_ranges);
 588 }
 589
 590 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
 591 {
 592         const struct dc_context *ctx = pp->dm;
 593         struct amdgpu_device *adev = ctx->driver_context;
 594         void *pp_handle = adev->powerplay.pp_handle;
 595         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 596
 597         if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
 598                 pp_funcs->notify_smu_enable_pwe(pp_handle);
 599 }
 600
 601 static void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
 602 {
 603         const struct dc_context *ctx = pp->dm;
 604         struct amdgpu_device *adev = ctx->driver_context;
 605         void *pp_handle = adev->powerplay.pp_handle;
 606         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 607
 608         if (!pp_funcs || !pp_funcs->set_active_display_count)
 609                 return;
 610
 611         pp_funcs->set_active_display_count(pp_handle, count);
 612 }
 613
 614 static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
 615 {
 616         const struct dc_context *ctx = pp->dm;
 617         struct amdgpu_device *adev = ctx->driver_context;
 618         void *pp_handle = adev->powerplay.pp_handle;
 619         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 620
 621         if (!pp_funcs || !pp_funcs->set_min_deep_sleep_dcefclk)
 622                 return;
 623
 624         pp_funcs->set_min_deep_sleep_dcefclk(pp_handle, clock);
 625 }
 626
 627 static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
 628 {
 629         const struct dc_context *ctx = pp->dm;
 630         struct amdgpu_device *adev = ctx->driver_context;
 631         void *pp_handle = adev->powerplay.pp_handle;
 632         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 633
 634         if (!pp_funcs || !pp_funcs->set_hard_min_dcefclk_by_freq)
 635                 return;
 636
 637         pp_funcs->set_hard_min_dcefclk_by_freq(pp_handle, clock);
 638 }
 639
 640 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
 641 {
 642         const struct dc_context *ctx = pp->dm;
 643         struct amdgpu_device *adev = ctx->driver_context;
 644         void *pp_handle = adev->powerplay.pp_handle;
 645         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 646
 647         if (!pp_funcs || !pp_funcs->set_hard_min_fclk_by_freq)
 648                 return;
 649
 650         pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);
 651 }
 652
 653 static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
 654                 struct pp_smu_wm_range_sets *ranges)
 655 {
 656         const struct dc_context *ctx = pp->dm;
 657         struct amdgpu_device *adev = ctx->driver_context;
 658
 659         smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);
 660
 661         return PP_SMU_RESULT_OK;
 662 }
 663
 664 static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
 665 {
 666         const struct dc_context *ctx = pp->dm;
 667         struct amdgpu_device *adev = ctx->driver_context;
 668         struct smu_context *smu = &adev->smu;
 669
 670         if (!smu->ppt_funcs)
 671                 return PP_SMU_RESULT_UNSUPPORTED;
 672
 673         /* 0: successful or smu.ppt_funcs->set_display_count = NULL;  1: fail */
 674         if (smu_set_display_count(smu, count))
 675                 return PP_SMU_RESULT_FAIL;
 676
 677         return PP_SMU_RESULT_OK;
 678 }
 679
 680 static enum pp_smu_status
 681 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
 682 {
 683         const struct dc_context *ctx = pp->dm;
 684         struct amdgpu_device *adev = ctx->driver_context;
 685         struct smu_context *smu = &adev->smu;
 686
 687         if (!smu->ppt_funcs)
 688                 return PP_SMU_RESULT_UNSUPPORTED;
 689
 690         /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
 691         if (smu_set_deep_sleep_dcefclk(smu, mhz))
 692                 return PP_SMU_RESULT_FAIL;
 693
 694         return PP_SMU_RESULT_OK;
 695 }
 696
 697 static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
 698                 struct pp_smu *pp, int mhz)
 699 {
 700         const struct dc_context *ctx = pp->dm;
 701         struct amdgpu_device *adev = ctx->driver_context;
 702         struct smu_context *smu = &adev->smu;
 703         struct pp_display_clock_request clock_req;
 704
 705         if (!smu->ppt_funcs)
 706                 return PP_SMU_RESULT_UNSUPPORTED;
 707
 708         clock_req.clock_type = amd_pp_dcef_clock;
 709         clock_req.clock_freq_in_khz = mhz * 1000;
 710
 711         /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
 712          * 1: fail
 713          */
 714         if (smu_display_clock_voltage_request(smu, &clock_req))
 715                 return PP_SMU_RESULT_FAIL;
 716
 717         return PP_SMU_RESULT_OK;
 718 }
 719
 720 static enum pp_smu_status
 721 pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
 722 {
 723         const struct dc_context *ctx = pp->dm;
 724         struct amdgpu_device *adev = ctx->driver_context;
 725         struct smu_context *smu = &adev->smu;
 726         struct pp_display_clock_request clock_req;
 727
 728         if (!smu->ppt_funcs)
 729                 return PP_SMU_RESULT_UNSUPPORTED;
 730
 731         clock_req.clock_type = amd_pp_mem_clock;
 732         clock_req.clock_freq_in_khz = mhz * 1000;
 733
 734         /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
 735          * 1: fail
 736          */
 737         if (smu_display_clock_voltage_request(smu, &clock_req))
 738                 return PP_SMU_RESULT_FAIL;
 739
 740         return PP_SMU_RESULT_OK;
 741 }
 742
 743 static enum pp_smu_status pp_nv_set_pstate_handshake_support(
 744         struct pp_smu *pp, bool pstate_handshake_supported)
 745 {
 746         const struct dc_context *ctx = pp->dm;
 747         struct amdgpu_device *adev = ctx->driver_context;
 748         struct smu_context *smu = &adev->smu;
 749
 750         if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported))
 751                 return PP_SMU_RESULT_FAIL;
 752
 753         return PP_SMU_RESULT_OK;
 754 }
 755
 756 static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
 757                 enum pp_smu_nv_clock_id clock_id, int mhz)
 758 {
 759         const struct dc_context *ctx = pp->dm;
 760         struct amdgpu_device *adev = ctx->driver_context;
 761         struct smu_context *smu = &adev->smu;
 762         struct pp_display_clock_request clock_req;
 763
 764         if (!smu->ppt_funcs)
 765                 return PP_SMU_RESULT_UNSUPPORTED;
 766
 767         switch (clock_id) {
 768         case PP_SMU_NV_DISPCLK:
 769                 clock_req.clock_type = amd_pp_disp_clock;
 770                 break;
 771         case PP_SMU_NV_PHYCLK:
 772                 clock_req.clock_type = amd_pp_phy_clock;
 773                 break;
 774         case PP_SMU_NV_PIXELCLK:
 775                 clock_req.clock_type = amd_pp_pixel_clock;
 776                 break;
 777         default:
 778                 break;
 779         }
 780         clock_req.clock_freq_in_khz = mhz * 1000;
 781
 782         /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
 783          * 1: fail
 784          */
 785         if (smu_display_clock_voltage_request(smu, &clock_req))
 786                 return PP_SMU_RESULT_FAIL;
 787
 788         return PP_SMU_RESULT_OK;
 789 }
 790
 791 static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
 792                 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks)
 793 {
 794         const struct dc_context *ctx = pp->dm;
 795         struct amdgpu_device *adev = ctx->driver_context;
 796         struct smu_context *smu = &adev->smu;
 797
 798         if (!smu->ppt_funcs)
 799                 return PP_SMU_RESULT_UNSUPPORTED;
 800
 801         if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
 802                 return PP_SMU_RESULT_UNSUPPORTED;
 803
 804         if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
 805                 return PP_SMU_RESULT_OK;
 806
 807         return PP_SMU_RESULT_FAIL;
 808 }
 809
 810 static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
 811                 unsigned int *clock_values_in_khz, unsigned int *num_states)
 812 {
 813         const struct dc_context *ctx = pp->dm;
 814         struct amdgpu_device *adev = ctx->driver_context;
 815         struct smu_context *smu = &adev->smu;
 816
 817         if (!smu->ppt_funcs)
 818                 return PP_SMU_RESULT_UNSUPPORTED;
 819
 820         if (!smu->ppt_funcs->get_uclk_dpm_states)
 821                 return PP_SMU_RESULT_UNSUPPORTED;
 822
 823         if (!smu_get_uclk_dpm_states(smu,
 824                         clock_values_in_khz, num_states))
 825                 return PP_SMU_RESULT_OK;
 826
 827         return PP_SMU_RESULT_FAIL;
 828 }
 829
 830 static enum pp_smu_status pp_rn_get_dpm_clock_table(
 831                 struct pp_smu *pp, struct dpm_clocks *clock_table)
 832 {
 833         const struct dc_context *ctx = pp->dm;
 834         struct amdgpu_device *adev = ctx->driver_context;
 835         struct smu_context *smu = &adev->smu;
 836
 837         if (!smu->ppt_funcs)
 838                 return PP_SMU_RESULT_UNSUPPORTED;
 839
 840         if (!smu->ppt_funcs->get_dpm_clock_table)
 841                 return PP_SMU_RESULT_UNSUPPORTED;
 842
 843         if (!smu_get_dpm_clock_table(smu, clock_table))
 844                 return PP_SMU_RESULT_OK;
 845
 846         return PP_SMU_RESULT_FAIL;
 847 }
 848
 849 static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
 850                 struct pp_smu_wm_range_sets *ranges)
 851 {
 852         const struct dc_context *ctx = pp->dm;
 853         struct amdgpu_device *adev = ctx->driver_context;
 854
 855         smu_set_watermarks_for_clock_ranges(&adev->smu, ranges);
 856
 857         return PP_SMU_RESULT_OK;
 858 }
 859
 860 void dm_pp_get_funcs(
 861                 struct dc_context *ctx,
 862                 struct pp_smu_funcs *funcs)
 863 {
 864         switch (ctx->dce_version) {
 865         case DCN_VERSION_1_0:
 866         case DCN_VERSION_1_01:
 867                 funcs->ctx.ver = PP_SMU_VER_RV;
 868                 funcs->rv_funcs.pp_smu.dm = ctx;
 869                 funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
 870                 funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
 871                 funcs->rv_funcs.set_display_count =
 872                                 pp_rv_set_active_display_count;
 873                 funcs->rv_funcs.set_min_deep_sleep_dcfclk =
 874                                 pp_rv_set_min_deep_sleep_dcfclk;
 875                 funcs->rv_funcs.set_hard_min_dcfclk_by_freq =
 876                                 pp_rv_set_hard_min_dcefclk_by_freq;
 877                 funcs->rv_funcs.set_hard_min_fclk_by_freq =
 878                                 pp_rv_set_hard_min_fclk_by_freq;
 879                 break;
 880         case DCN_VERSION_2_0:
 881                 funcs->ctx.ver = PP_SMU_VER_NV;
 882                 funcs->nv_funcs.pp_smu.dm = ctx;
 883                 funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
 884                 funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
 885                                 pp_nv_set_hard_min_dcefclk_by_freq;
 886                 funcs->nv_funcs.set_min_deep_sleep_dcfclk =
 887                                 pp_nv_set_min_deep_sleep_dcfclk;
 888                 funcs->nv_funcs.set_voltage_by_freq =
 889                                 pp_nv_set_voltage_by_freq;
 890                 funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
 891
 892                 /* todo set_pme_wa_enable cause 4k@6ohz display not light up */
 893                 funcs->nv_funcs.set_pme_wa_enable = NULL;
 894                 /* todo debug waring message */
 895                 funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
 896                 /* todo  compare data with window driver*/
 897                 funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
 898                 /*todo  compare data with window driver */
 899                 funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
 900                 funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
 901                 break;
 902
 903         case DCN_VERSION_2_1:
 904                 funcs->ctx.ver = PP_SMU_VER_RN;
 905                 funcs->rn_funcs.pp_smu.dm = ctx;
 906                 funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;
 907                 funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;
 908                 break;
 909         default:
 910                 DRM_ERROR("smu version is not supported !\n");
 911                 break;
 912         }
 913 }