1 // SPDX-License-Identifier: MIT
3 * Copyright 2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_blend.h>
29 #include <drm/drm_gem_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_fourcc.h>
34 #include "dal_asic_id.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_dm_trace.h"
37 #include "gc/gc_11_0_0_offset.h"
38 #include "gc/gc_11_0_0_sh_mask.h"
41 * TODO: these are currently initialized to rgb formats only.
42 * For future use cases we should either initialize them dynamically based on
43 * plane capabilities, or initialize this array to all formats, so internal drm
44 * check will succeed, and let DC implement proper check
46 static const uint32_t rgb_formats[] = {
50 DRM_FORMAT_XRGB2101010,
51 DRM_FORMAT_XBGR2101010,
52 DRM_FORMAT_ARGB2101010,
53 DRM_FORMAT_ABGR2101010,
54 DRM_FORMAT_XRGB16161616,
55 DRM_FORMAT_XBGR16161616,
56 DRM_FORMAT_ARGB16161616,
57 DRM_FORMAT_ABGR16161616,
63 static const uint32_t overlay_formats[] = {
72 static const u32 cursor_formats[] = {
76 enum dm_micro_swizzle {
83 const struct drm_format_info *amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
85 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
88 void fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
89 bool *per_pixel_alpha, bool *pre_multiplied_alpha,
90 bool *global_alpha, int *global_alpha_value)
92 *per_pixel_alpha = false;
93 *pre_multiplied_alpha = true;
94 *global_alpha = false;
95 *global_alpha_value = 0xff;
97 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
100 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||
101 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
102 static const uint32_t alpha_formats[] = {
107 uint32_t format = plane_state->fb->format->format;
110 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
111 if (format == alpha_formats[i]) {
112 *per_pixel_alpha = true;
117 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
118 *pre_multiplied_alpha = false;
121 if (plane_state->alpha < 0xffff) {
122 *global_alpha = true;
123 *global_alpha_value = plane_state->alpha >> 8;
127 static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
132 if (*cap - *size < 1) {
133 uint64_t new_cap = *cap * 2;
134 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
142 memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
148 (*mods)[*size] = mod;
152 bool modifier_has_dcc(uint64_t modifier)
154 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
157 unsigned modifier_gfx9_swizzle_mode(uint64_t modifier)
159 if (modifier == DRM_FORMAT_MOD_LINEAR)
162 return AMD_FMT_MOD_GET(TILE, modifier);
165 static void fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
166 uint64_t tiling_flags)
168 /* Fill GFX8 params */
169 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
170 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
172 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
173 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
174 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
175 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
176 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
178 /* XXX fix me for VI */
179 tiling_info->gfx8.num_banks = num_banks;
180 tiling_info->gfx8.array_mode =
181 DC_ARRAY_2D_TILED_THIN1;
182 tiling_info->gfx8.tile_split = tile_split;
183 tiling_info->gfx8.bank_width = bankw;
184 tiling_info->gfx8.bank_height = bankh;
185 tiling_info->gfx8.tile_aspect = mtaspect;
186 tiling_info->gfx8.tile_mode =
187 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
188 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
189 == DC_ARRAY_1D_TILED_THIN1) {
190 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
193 tiling_info->gfx8.pipe_config =
194 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
197 static void fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
198 union dc_tiling_info *tiling_info)
200 /* Fill GFX9 params */
201 tiling_info->gfx9.num_pipes =
202 adev->gfx.config.gb_addr_config_fields.num_pipes;
203 tiling_info->gfx9.num_banks =
204 adev->gfx.config.gb_addr_config_fields.num_banks;
205 tiling_info->gfx9.pipe_interleave =
206 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
207 tiling_info->gfx9.num_shader_engines =
208 adev->gfx.config.gb_addr_config_fields.num_se;
209 tiling_info->gfx9.max_compressed_frags =
210 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
211 tiling_info->gfx9.num_rb_per_se =
212 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
213 tiling_info->gfx9.shaderEnable = 1;
214 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
215 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
218 static void fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
219 union dc_tiling_info *tiling_info,
222 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
223 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
224 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
225 unsigned int pipes_log2;
227 pipes_log2 = min(5u, mod_pipe_xor_bits);
229 fill_gfx9_tiling_info_from_device(adev, tiling_info);
231 if (!IS_AMD_FMT_MOD(modifier))
234 tiling_info->gfx9.num_pipes = 1u << pipes_log2;
235 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
237 if (adev->family >= AMDGPU_FAMILY_NV) {
238 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
240 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
242 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
246 static int validate_dcc(struct amdgpu_device *adev,
247 const enum surface_pixel_format format,
248 const enum dc_rotation_angle rotation,
249 const union dc_tiling_info *tiling_info,
250 const struct dc_plane_dcc_param *dcc,
251 const struct dc_plane_address *address,
252 const struct plane_size *plane_size)
254 struct dc *dc = adev->dm.dc;
255 struct dc_dcc_surface_param input;
256 struct dc_surface_dcc_cap output;
258 memset(&input, 0, sizeof(input));
259 memset(&output, 0, sizeof(output));
264 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
265 !dc->cap_funcs.get_dcc_compression_cap)
268 input.format = format;
269 input.surface_size.width = plane_size->surface_size.width;
270 input.surface_size.height = plane_size->surface_size.height;
271 input.swizzle_mode = tiling_info->gfx9.swizzle;
273 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
274 input.scan = SCAN_DIRECTION_HORIZONTAL;
275 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
276 input.scan = SCAN_DIRECTION_VERTICAL;
278 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
284 if (dcc->independent_64b_blks == 0 &&
285 output.grph.rgb.independent_64b_blks != 0)
291 static int fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
292 const struct amdgpu_framebuffer *afb,
293 const enum surface_pixel_format format,
294 const enum dc_rotation_angle rotation,
295 const struct plane_size *plane_size,
296 union dc_tiling_info *tiling_info,
297 struct dc_plane_dcc_param *dcc,
298 struct dc_plane_address *address,
299 const bool force_disable_dcc)
301 const uint64_t modifier = afb->base.modifier;
304 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
305 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
307 if (modifier_has_dcc(modifier) && !force_disable_dcc) {
308 uint64_t dcc_address = afb->address + afb->base.offsets[1];
309 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
310 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
313 dcc->meta_pitch = afb->base.pitches[1];
314 dcc->independent_64b_blks = independent_64b_blks;
315 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
316 if (independent_64b_blks && independent_128b_blks)
317 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl;
318 else if (independent_128b_blks)
319 dcc->dcc_ind_blk = hubp_ind_block_128b;
320 else if (independent_64b_blks && !independent_128b_blks)
321 dcc->dcc_ind_blk = hubp_ind_block_64b;
323 dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
325 if (independent_64b_blks)
326 dcc->dcc_ind_blk = hubp_ind_block_64b;
328 dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
331 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
332 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
335 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
337 drm_dbg_kms(adev_to_drm(adev), "validate_dcc: returned error: %d\n", ret);
342 static void add_gfx10_1_modifiers(const struct amdgpu_device *adev,
343 uint64_t **mods, uint64_t *size, uint64_t *capacity)
345 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
347 add_modifier(mods, size, capacity, AMD_FMT_MOD |
348 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
349 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
350 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
351 AMD_FMT_MOD_SET(DCC, 1) |
352 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
353 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
354 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
356 add_modifier(mods, size, capacity, AMD_FMT_MOD |
357 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
358 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
359 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
360 AMD_FMT_MOD_SET(DCC, 1) |
361 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
362 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
363 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
364 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
366 add_modifier(mods, size, capacity, AMD_FMT_MOD |
367 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
368 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
369 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
371 add_modifier(mods, size, capacity, AMD_FMT_MOD |
372 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
373 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
374 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
377 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
378 add_modifier(mods, size, capacity, AMD_FMT_MOD |
379 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
380 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
382 add_modifier(mods, size, capacity, AMD_FMT_MOD |
383 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
384 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
387 static void add_gfx9_modifiers(const struct amdgpu_device *adev,
388 uint64_t **mods, uint64_t *size, uint64_t *capacity)
390 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
391 int pipe_xor_bits = min(8, pipes +
392 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
393 int bank_xor_bits = min(8 - pipe_xor_bits,
394 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
395 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
396 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
399 if (adev->family == AMDGPU_FAMILY_RV) {
400 /* Raven2 and later */
401 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
404 * No _D DCC swizzles yet because we only allow 32bpp, which
405 * doesn't support _D on DCN
408 if (has_constant_encode) {
409 add_modifier(mods, size, capacity, AMD_FMT_MOD |
410 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
411 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
412 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
413 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
414 AMD_FMT_MOD_SET(DCC, 1) |
415 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
416 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
417 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
420 add_modifier(mods, size, capacity, AMD_FMT_MOD |
421 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
422 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
423 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
424 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
425 AMD_FMT_MOD_SET(DCC, 1) |
426 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
427 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
428 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
430 if (has_constant_encode) {
431 add_modifier(mods, size, capacity, AMD_FMT_MOD |
432 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
433 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
434 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
435 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
436 AMD_FMT_MOD_SET(DCC, 1) |
437 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
438 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
439 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
441 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
442 AMD_FMT_MOD_SET(RB, rb) |
443 AMD_FMT_MOD_SET(PIPE, pipes));
446 add_modifier(mods, size, capacity, AMD_FMT_MOD |
447 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
448 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
449 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
450 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
451 AMD_FMT_MOD_SET(DCC, 1) |
452 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
453 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
454 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
455 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
456 AMD_FMT_MOD_SET(RB, rb) |
457 AMD_FMT_MOD_SET(PIPE, pipes));
461 * Only supported for 64bpp on Raven, will be filtered on format in
462 * dm_plane_format_mod_supported.
464 add_modifier(mods, size, capacity, AMD_FMT_MOD |
465 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
466 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
467 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
468 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
470 if (adev->family == AMDGPU_FAMILY_RV) {
471 add_modifier(mods, size, capacity, AMD_FMT_MOD |
472 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
473 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
474 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
475 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
479 * Only supported for 64bpp on Raven, will be filtered on format in
480 * dm_plane_format_mod_supported.
482 add_modifier(mods, size, capacity, AMD_FMT_MOD |
483 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
484 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
486 if (adev->family == AMDGPU_FAMILY_RV) {
487 add_modifier(mods, size, capacity, AMD_FMT_MOD |
488 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
489 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
493 static void add_gfx10_3_modifiers(const struct amdgpu_device *adev,
494 uint64_t **mods, uint64_t *size, uint64_t *capacity)
496 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
497 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
499 add_modifier(mods, size, capacity, AMD_FMT_MOD |
500 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
501 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
502 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
503 AMD_FMT_MOD_SET(PACKERS, pkrs) |
504 AMD_FMT_MOD_SET(DCC, 1) |
505 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
506 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
507 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
508 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
510 add_modifier(mods, size, capacity, AMD_FMT_MOD |
511 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
512 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
513 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
514 AMD_FMT_MOD_SET(PACKERS, pkrs) |
515 AMD_FMT_MOD_SET(DCC, 1) |
516 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
517 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
518 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
520 add_modifier(mods, size, capacity, AMD_FMT_MOD |
521 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
522 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
523 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
524 AMD_FMT_MOD_SET(PACKERS, pkrs) |
525 AMD_FMT_MOD_SET(DCC, 1) |
526 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
527 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
528 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
529 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
530 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
532 add_modifier(mods, size, capacity, AMD_FMT_MOD |
533 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
534 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
535 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
536 AMD_FMT_MOD_SET(PACKERS, pkrs) |
537 AMD_FMT_MOD_SET(DCC, 1) |
538 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
539 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
540 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
541 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
543 add_modifier(mods, size, capacity, AMD_FMT_MOD |
544 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
545 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
546 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
547 AMD_FMT_MOD_SET(PACKERS, pkrs));
549 add_modifier(mods, size, capacity, AMD_FMT_MOD |
550 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
551 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
552 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
553 AMD_FMT_MOD_SET(PACKERS, pkrs));
555 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
556 add_modifier(mods, size, capacity, AMD_FMT_MOD |
557 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
558 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
560 add_modifier(mods, size, capacity, AMD_FMT_MOD |
561 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
562 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
565 static void add_gfx11_modifiers(struct amdgpu_device *adev,
566 uint64_t **mods, uint64_t *size, uint64_t *capacity)
569 int pipe_xor_bits = 0;
574 unsigned swizzle_r_x;
575 uint64_t modifier_r_x;
576 uint64_t modifier_dcc_best;
577 uint64_t modifier_dcc_4k;
579 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from
580 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes}
582 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
583 ASSERT(gb_addr_config != 0);
585 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
586 pkrs = ilog2(num_pkrs);
587 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES);
588 pipe_xor_bits = ilog2(num_pipes);
590 for (i = 0; i < 2; i++) {
591 /* Insert the best one first. */
592 /* R_X swizzle modes are the best for rendering and DCC requires them. */
594 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X;
596 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X;
598 modifier_r_x = AMD_FMT_MOD |
599 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
600 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
601 AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
602 AMD_FMT_MOD_SET(PACKERS, pkrs);
604 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
605 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
606 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
607 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
608 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
610 /* DCC settings for 4K and greater resolutions. (required by display hw) */
611 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
612 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
613 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
614 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
616 add_modifier(mods, size, capacity, modifier_dcc_best);
617 add_modifier(mods, size, capacity, modifier_dcc_4k);
619 add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
620 add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
622 add_modifier(mods, size, capacity, modifier_r_x);
625 add_modifier(mods, size, capacity, AMD_FMT_MOD |
626 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
627 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
630 static int get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
632 uint64_t size = 0, capacity = 128;
635 /* We have not hooked up any pre-GFX9 modifiers. */
636 if (adev->family < AMDGPU_FAMILY_AI)
639 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
641 if (plane_type == DRM_PLANE_TYPE_CURSOR) {
642 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
643 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
644 return *mods ? 0 : -ENOMEM;
647 switch (adev->family) {
648 case AMDGPU_FAMILY_AI:
649 case AMDGPU_FAMILY_RV:
650 add_gfx9_modifiers(adev, mods, &size, &capacity);
652 case AMDGPU_FAMILY_NV:
653 case AMDGPU_FAMILY_VGH:
654 case AMDGPU_FAMILY_YC:
655 case AMDGPU_FAMILY_GC_10_3_6:
656 case AMDGPU_FAMILY_GC_10_3_7:
657 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
658 add_gfx10_3_modifiers(adev, mods, &size, &capacity);
660 add_gfx10_1_modifiers(adev, mods, &size, &capacity);
662 case AMDGPU_FAMILY_GC_11_0_0:
663 case AMDGPU_FAMILY_GC_11_0_1:
664 add_gfx11_modifiers(adev, mods, &size, &capacity);
668 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
670 /* INVALID marks the end of the list. */
671 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
679 static int get_plane_formats(const struct drm_plane *plane,
680 const struct dc_plane_cap *plane_cap,
681 uint32_t *formats, int max_formats)
683 int i, num_formats = 0;
686 * TODO: Query support for each group of formats directly from
687 * DC plane caps. This will require adding more formats to the
691 switch (plane->type) {
692 case DRM_PLANE_TYPE_PRIMARY:
693 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
694 if (num_formats >= max_formats)
697 formats[num_formats++] = rgb_formats[i];
700 if (plane_cap && plane_cap->pixel_format_support.nv12)
701 formats[num_formats++] = DRM_FORMAT_NV12;
702 if (plane_cap && plane_cap->pixel_format_support.p010)
703 formats[num_formats++] = DRM_FORMAT_P010;
704 if (plane_cap && plane_cap->pixel_format_support.fp16) {
705 formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
706 formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
707 formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
708 formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
712 case DRM_PLANE_TYPE_OVERLAY:
713 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
714 if (num_formats >= max_formats)
717 formats[num_formats++] = overlay_formats[i];
721 case DRM_PLANE_TYPE_CURSOR:
722 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
723 if (num_formats >= max_formats)
726 formats[num_formats++] = cursor_formats[i];
734 #ifdef CONFIG_DRM_AMD_DC_HDR
735 static int attach_color_mgmt_properties(struct amdgpu_display_manager *dm, struct drm_plane *plane)
737 drm_object_attach_property(&plane->base,
738 dm->degamma_lut_property,
740 drm_object_attach_property(&plane->base,
741 dm->degamma_lut_size_property,
742 MAX_COLOR_LUT_ENTRIES);
743 drm_object_attach_property(&plane->base, dm->ctm_property,
745 drm_object_attach_property(&plane->base, dm->sdr_boost_property,
752 int fill_plane_buffer_attributes(struct amdgpu_device *adev,
753 const struct amdgpu_framebuffer *afb,
754 const enum surface_pixel_format format,
755 const enum dc_rotation_angle rotation,
756 const uint64_t tiling_flags,
757 union dc_tiling_info *tiling_info,
758 struct plane_size *plane_size,
759 struct dc_plane_dcc_param *dcc,
760 struct dc_plane_address *address,
762 bool force_disable_dcc)
764 const struct drm_framebuffer *fb = &afb->base;
767 memset(tiling_info, 0, sizeof(*tiling_info));
768 memset(plane_size, 0, sizeof(*plane_size));
769 memset(dcc, 0, sizeof(*dcc));
770 memset(address, 0, sizeof(*address));
772 address->tmz_surface = tmz_surface;
774 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
775 uint64_t addr = afb->address + fb->offsets[0];
777 plane_size->surface_size.x = 0;
778 plane_size->surface_size.y = 0;
779 plane_size->surface_size.width = fb->width;
780 plane_size->surface_size.height = fb->height;
781 plane_size->surface_pitch =
782 fb->pitches[0] / fb->format->cpp[0];
784 address->type = PLN_ADDR_TYPE_GRAPHICS;
785 address->grph.addr.low_part = lower_32_bits(addr);
786 address->grph.addr.high_part = upper_32_bits(addr);
787 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
788 uint64_t luma_addr = afb->address + fb->offsets[0];
789 uint64_t chroma_addr = afb->address + fb->offsets[1];
791 plane_size->surface_size.x = 0;
792 plane_size->surface_size.y = 0;
793 plane_size->surface_size.width = fb->width;
794 plane_size->surface_size.height = fb->height;
795 plane_size->surface_pitch =
796 fb->pitches[0] / fb->format->cpp[0];
798 plane_size->chroma_size.x = 0;
799 plane_size->chroma_size.y = 0;
800 /* TODO: set these based on surface format */
801 plane_size->chroma_size.width = fb->width / 2;
802 plane_size->chroma_size.height = fb->height / 2;
804 plane_size->chroma_pitch =
805 fb->pitches[1] / fb->format->cpp[1];
807 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
808 address->video_progressive.luma_addr.low_part =
809 lower_32_bits(luma_addr);
810 address->video_progressive.luma_addr.high_part =
811 upper_32_bits(luma_addr);
812 address->video_progressive.chroma_addr.low_part =
813 lower_32_bits(chroma_addr);
814 address->video_progressive.chroma_addr.high_part =
815 upper_32_bits(chroma_addr);
818 if (adev->family >= AMDGPU_FAMILY_AI) {
819 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
820 rotation, plane_size,
827 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
833 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
834 struct drm_plane_state *new_state)
836 struct amdgpu_framebuffer *afb;
837 struct drm_gem_object *obj;
838 struct amdgpu_device *adev;
839 struct amdgpu_bo *rbo;
840 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
844 if (!new_state->fb) {
845 DRM_DEBUG_KMS("No FB bound\n");
849 afb = to_amdgpu_framebuffer(new_state->fb);
850 obj = new_state->fb->obj[0];
851 rbo = gem_to_amdgpu_bo(obj);
852 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
854 r = amdgpu_bo_reserve(rbo, true);
856 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
860 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
862 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r);
866 if (plane->type != DRM_PLANE_TYPE_CURSOR)
867 domain = amdgpu_display_supported_domains(adev, rbo->flags);
869 domain = AMDGPU_GEM_DOMAIN_VRAM;
871 r = amdgpu_bo_pin(rbo, domain);
872 if (unlikely(r != 0)) {
873 if (r != -ERESTARTSYS)
874 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
878 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
879 if (unlikely(r != 0)) {
880 DRM_ERROR("%p bind failed\n", rbo);
884 r = drm_gem_plane_helper_prepare_fb(plane, new_state);
885 if (unlikely(r != 0))
888 amdgpu_bo_unreserve(rbo);
890 afb->address = amdgpu_bo_gpu_offset(rbo);
895 * We don't do surface updates on planes that have been newly created,
896 * but we also don't have the afb->address during atomic check.
898 * Fill in buffer attributes depending on the address here, but only on
899 * newly created planes since they're not being used by DC yet and this
900 * won't modify global state.
902 dm_plane_state_old = to_dm_plane_state(plane->state);
903 dm_plane_state_new = to_dm_plane_state(new_state);
905 if (dm_plane_state_new->dc_state &&
906 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
907 struct dc_plane_state *plane_state =
908 dm_plane_state_new->dc_state;
909 bool force_disable_dcc = !plane_state->dcc.enable;
911 fill_plane_buffer_attributes(
912 adev, afb, plane_state->format, plane_state->rotation,
914 &plane_state->tiling_info, &plane_state->plane_size,
915 &plane_state->dcc, &plane_state->address,
916 afb->tmz_surface, force_disable_dcc);
922 amdgpu_bo_unpin(rbo);
925 amdgpu_bo_unreserve(rbo);
929 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
930 struct drm_plane_state *old_state)
932 struct amdgpu_bo *rbo;
938 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
939 r = amdgpu_bo_reserve(rbo, false);
941 DRM_ERROR("failed to reserve rbo before unpin\n");
945 amdgpu_bo_unpin(rbo);
946 amdgpu_bo_unreserve(rbo);
947 amdgpu_bo_unref(&rbo);
950 static void get_min_max_dc_plane_scaling(struct drm_device *dev,
951 struct drm_framebuffer *fb,
952 int *min_downscale, int *max_upscale)
954 struct amdgpu_device *adev = drm_to_adev(dev);
955 struct dc *dc = adev->dm.dc;
956 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
957 struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
959 switch (fb->format->format) {
960 case DRM_FORMAT_P010:
961 case DRM_FORMAT_NV12:
962 case DRM_FORMAT_NV21:
963 *max_upscale = plane_cap->max_upscale_factor.nv12;
964 *min_downscale = plane_cap->max_downscale_factor.nv12;
967 case DRM_FORMAT_XRGB16161616F:
968 case DRM_FORMAT_ARGB16161616F:
969 case DRM_FORMAT_XBGR16161616F:
970 case DRM_FORMAT_ABGR16161616F:
971 *max_upscale = plane_cap->max_upscale_factor.fp16;
972 *min_downscale = plane_cap->max_downscale_factor.fp16;
976 *max_upscale = plane_cap->max_upscale_factor.argb8888;
977 *min_downscale = plane_cap->max_downscale_factor.argb8888;
982 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a
983 * scaling factor of 1.0 == 1000 units.
985 if (*max_upscale == 1)
988 if (*min_downscale == 1)
989 *min_downscale = 1000;
992 int dm_plane_helper_check_state(struct drm_plane_state *state,
993 struct drm_crtc_state *new_crtc_state)
995 struct drm_framebuffer *fb = state->fb;
996 int min_downscale, max_upscale;
998 int max_scale = INT_MAX;
1000 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */
1001 if (fb && state->crtc) {
1002 /* Validate viewport to cover the case when only the position changes */
1003 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {
1004 int viewport_width = state->crtc_w;
1005 int viewport_height = state->crtc_h;
1007 if (state->crtc_x < 0)
1008 viewport_width += state->crtc_x;
1009 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay)
1010 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x;
1012 if (state->crtc_y < 0)
1013 viewport_height += state->crtc_y;
1014 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay)
1015 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
1017 if (viewport_width < 0 || viewport_height < 0) {
1018 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n");
1020 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */
1021 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2);
1023 } else if (viewport_height < MIN_VIEWPORT_SIZE) {
1024 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE);
1030 /* Get min/max allowed scaling factors from plane caps. */
1031 get_min_max_dc_plane_scaling(state->crtc->dev, fb,
1032 &min_downscale, &max_upscale);
1034 * Convert to drm convention: 16.16 fixed point, instead of dc's
1035 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's
1036 * dst/src, so min_scale = 1.0 / max_upscale, etc.
1038 min_scale = (1000 << 16) / max_upscale;
1039 max_scale = (1000 << 16) / min_downscale;
1042 return drm_atomic_helper_check_plane_state(
1043 state, new_crtc_state, min_scale, max_scale, true, true);
1046 int fill_dc_scaling_info(struct amdgpu_device *adev,
1047 const struct drm_plane_state *state,
1048 struct dc_scaling_info *scaling_info)
1050 int scale_w, scale_h, min_downscale, max_upscale;
1052 memset(scaling_info, 0, sizeof(*scaling_info));
1054 /* Source is fixed 16.16 but we ignore mantissa for now... */
1055 scaling_info->src_rect.x = state->src_x >> 16;
1056 scaling_info->src_rect.y = state->src_y >> 16;
1059 * For reasons we don't (yet) fully understand a non-zero
1060 * src_y coordinate into an NV12 buffer can cause a
1061 * system hang on DCN1x.
1062 * To avoid hangs (and maybe be overly cautious)
1063 * let's reject both non-zero src_x and src_y.
1065 * We currently know of only one use-case to reproduce a
1066 * scenario with non-zero src_x and src_y for NV12, which
1067 * is to gesture the YouTube Android app into full screen
1070 if (((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) ||
1071 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) &&
1072 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 &&
1073 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0)))
1076 scaling_info->src_rect.width = state->src_w >> 16;
1077 if (scaling_info->src_rect.width == 0)
1080 scaling_info->src_rect.height = state->src_h >> 16;
1081 if (scaling_info->src_rect.height == 0)
1084 scaling_info->dst_rect.x = state->crtc_x;
1085 scaling_info->dst_rect.y = state->crtc_y;
1087 if (state->crtc_w == 0)
1090 scaling_info->dst_rect.width = state->crtc_w;
1092 if (state->crtc_h == 0)
1095 scaling_info->dst_rect.height = state->crtc_h;
1097 /* DRM doesn't specify clipping on destination output. */
1098 scaling_info->clip_rect = scaling_info->dst_rect;
1100 /* Validate scaling per-format with DC plane caps */
1101 if (state->plane && state->plane->dev && state->fb) {
1102 get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
1103 &min_downscale, &max_upscale);
1105 min_downscale = 250;
1106 max_upscale = 16000;
1109 scale_w = scaling_info->dst_rect.width * 1000 /
1110 scaling_info->src_rect.width;
1112 if (scale_w < min_downscale || scale_w > max_upscale)
1115 scale_h = scaling_info->dst_rect.height * 1000 /
1116 scaling_info->src_rect.height;
1118 if (scale_h < min_downscale || scale_h > max_upscale)
1122 * The "scaling_quality" can be ignored for now, quality = 0 has DC
1123 * assume reasonable defaults based on the format.
1129 static int dm_plane_atomic_check(struct drm_plane *plane,
1130 struct drm_atomic_state *state)
1132 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1134 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1135 struct dc *dc = adev->dm.dc;
1136 struct dm_plane_state *dm_plane_state;
1137 struct dc_scaling_info scaling_info;
1138 struct drm_crtc_state *new_crtc_state;
1141 trace_amdgpu_dm_plane_atomic_check(new_plane_state);
1143 dm_plane_state = to_dm_plane_state(new_plane_state);
1145 if (!dm_plane_state->dc_state)
1149 drm_atomic_get_new_crtc_state(state,
1150 new_plane_state->crtc);
1151 if (!new_crtc_state)
1154 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
1158 ret = fill_dc_scaling_info(adev, new_plane_state, &scaling_info);
1162 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
1168 static int dm_plane_atomic_async_check(struct drm_plane *plane,
1169 struct drm_atomic_state *state)
1171 /* Only support async updates on cursor planes. */
1172 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1178 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
1179 struct dc_cursor_position *position)
1181 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1183 int xorigin = 0, yorigin = 0;
1185 if (!crtc || !plane->state->fb)
1188 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
1189 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
1190 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
1192 plane->state->crtc_w,
1193 plane->state->crtc_h);
1197 x = plane->state->crtc_x;
1198 y = plane->state->crtc_y;
1200 if (x <= -amdgpu_crtc->max_cursor_width ||
1201 y <= -amdgpu_crtc->max_cursor_height)
1205 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1209 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1212 position->enable = true;
1213 position->translate_by_source = true;
1216 position->x_hotspot = xorigin;
1217 position->y_hotspot = yorigin;
1222 void handle_cursor_update(struct drm_plane *plane,
1223 struct drm_plane_state *old_plane_state)
1225 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1226 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
1227 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
1228 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
1229 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1230 uint64_t address = afb ? afb->address : 0;
1231 struct dc_cursor_position position = {0};
1232 struct dc_cursor_attributes attributes;
1235 if (!plane->state->fb && !old_plane_state->fb)
1238 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n",
1240 amdgpu_crtc->crtc_id,
1241 plane->state->crtc_w,
1242 plane->state->crtc_h);
1244 ret = get_cursor_position(plane, crtc, &position);
1248 if (!position.enable) {
1249 /* turn off cursor */
1250 if (crtc_state && crtc_state->stream) {
1251 mutex_lock(&adev->dm.dc_lock);
1252 dc_stream_set_cursor_position(crtc_state->stream,
1254 mutex_unlock(&adev->dm.dc_lock);
1259 amdgpu_crtc->cursor_width = plane->state->crtc_w;
1260 amdgpu_crtc->cursor_height = plane->state->crtc_h;
1262 memset(&attributes, 0, sizeof(attributes));
1263 attributes.address.high_part = upper_32_bits(address);
1264 attributes.address.low_part = lower_32_bits(address);
1265 attributes.width = plane->state->crtc_w;
1266 attributes.height = plane->state->crtc_h;
1267 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
1268 attributes.rotation_angle = 0;
1269 attributes.attribute_flags.value = 0;
1271 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
1273 if (crtc_state->stream) {
1274 mutex_lock(&adev->dm.dc_lock);
1275 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
1277 DRM_ERROR("DC failed to set cursor attributes\n");
1279 if (!dc_stream_set_cursor_position(crtc_state->stream,
1281 DRM_ERROR("DC failed to set cursor position\n");
1282 mutex_unlock(&adev->dm.dc_lock);
1286 static void dm_plane_atomic_async_update(struct drm_plane *plane,
1287 struct drm_atomic_state *state)
1289 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1291 struct drm_plane_state *old_state =
1292 drm_atomic_get_old_plane_state(state, plane);
1294 trace_amdgpu_dm_atomic_update_cursor(new_state);
1296 swap(plane->state->fb, new_state->fb);
1298 plane->state->src_x = new_state->src_x;
1299 plane->state->src_y = new_state->src_y;
1300 plane->state->src_w = new_state->src_w;
1301 plane->state->src_h = new_state->src_h;
1302 plane->state->crtc_x = new_state->crtc_x;
1303 plane->state->crtc_y = new_state->crtc_y;
1304 plane->state->crtc_w = new_state->crtc_w;
1305 plane->state->crtc_h = new_state->crtc_h;
1307 handle_cursor_update(plane, old_state);
1310 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1311 .prepare_fb = dm_plane_helper_prepare_fb,
1312 .cleanup_fb = dm_plane_helper_cleanup_fb,
1313 .atomic_check = dm_plane_atomic_check,
1314 .atomic_async_check = dm_plane_atomic_async_check,
1315 .atomic_async_update = dm_plane_atomic_async_update
1318 static void dm_drm_plane_reset(struct drm_plane *plane)
1320 struct dm_plane_state *amdgpu_state = NULL;
1323 plane->funcs->atomic_destroy_state(plane, plane->state);
1325 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
1326 WARN_ON(amdgpu_state == NULL);
1329 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
1330 #ifdef CONFIG_DRM_AMD_DC_HDR
1332 amdgpu_state->sdr_boost = DEFAULT_SDR_BOOST;
1336 static struct drm_plane_state *
1337 dm_drm_plane_duplicate_state(struct drm_plane *plane)
1339 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
1341 old_dm_plane_state = to_dm_plane_state(plane->state);
1342 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
1343 if (!dm_plane_state)
1346 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
1348 if (old_dm_plane_state->dc_state) {
1349 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
1350 dc_plane_state_retain(dm_plane_state->dc_state);
1353 #ifdef CONFIG_DRM_AMD_DC_HDR
1354 if (dm_plane_state->degamma_lut)
1355 drm_property_blob_get(dm_plane_state->degamma_lut);
1356 if (dm_plane_state->ctm)
1357 drm_property_blob_get(dm_plane_state->ctm);
1359 dm_plane_state->sdr_boost = old_dm_plane_state->sdr_boost;
1362 return &dm_plane_state->base;
1365 static bool dm_plane_format_mod_supported(struct drm_plane *plane,
1369 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1370 const struct drm_format_info *info = drm_format_info(format);
1371 struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
1373 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
1379 * We always have to allow these modifiers:
1380 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers.
1381 * 2. Not passing any modifiers is the same as explicitly passing INVALID.
1383 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1384 modifier == DRM_FORMAT_MOD_INVALID) {
1388 /* check if swizzle mode is supported by this version of DCN */
1389 switch (asic_id.chip_family) {
1395 /* asics before AI does not have modifier support */
1401 case FAMILY_YELLOW_CARP:
1402 case AMDGPU_FAMILY_GC_10_3_6:
1403 case AMDGPU_FAMILY_GC_10_3_7:
1404 switch (AMD_FMT_MOD_GET(TILE, modifier)) {
1405 case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
1406 case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
1407 case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
1408 case AMD_FMT_MOD_TILE_GFX9_64K_D:
1414 case AMDGPU_FAMILY_GC_11_0_0:
1415 case AMDGPU_FAMILY_GC_11_0_1:
1416 switch (AMD_FMT_MOD_GET(TILE, modifier)) {
1417 case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
1418 case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
1419 case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
1420 case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
1421 case AMD_FMT_MOD_TILE_GFX9_64K_D:
1428 ASSERT(0); /* Unknown asic */
1433 * For D swizzle the canonical modifier depends on the bpp, so check
1436 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
1437 adev->family >= AMDGPU_FAMILY_NV) {
1438 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
1442 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
1446 if (modifier_has_dcc(modifier)) {
1447 /* Per radeonsi comments 16/64 bpp are more complicated. */
1448 if (info->cpp[0] != 4)
1450 /* We support multi-planar formats, but not when combined with
1451 * additional DCC metadata planes.
1453 if (info->num_planes > 1)
1460 static void dm_drm_plane_destroy_state(struct drm_plane *plane,
1461 struct drm_plane_state *state)
1463 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1465 #ifdef CONFIG_DRM_AMD_DC_HDR
1466 drm_property_blob_put(dm_plane_state->degamma_lut);
1467 drm_property_blob_put(dm_plane_state->ctm);
1469 if (dm_plane_state->dc_state)
1470 dc_plane_state_release(dm_plane_state->dc_state);
1472 drm_atomic_helper_plane_destroy_state(plane, state);
1475 #ifdef CONFIG_DRM_AMD_DC_HDR
1476 /* copied from drm_atomic_uapi.c */
1477 static int atomic_replace_property_blob_from_id(struct drm_device *dev,
1478 struct drm_property_blob **blob,
1480 ssize_t expected_size,
1481 ssize_t expected_elem_size,
1484 struct drm_property_blob *new_blob = NULL;
1487 new_blob = drm_property_lookup_blob(dev, blob_id);
1488 if (new_blob == NULL)
1491 if (expected_size > 0 &&
1492 new_blob->length != expected_size) {
1493 drm_property_blob_put(new_blob);
1496 if (expected_elem_size > 0 &&
1497 new_blob->length % expected_elem_size != 0) {
1498 drm_property_blob_put(new_blob);
1503 *replaced |= drm_property_replace_blob(blob, new_blob);
1504 drm_property_blob_put(new_blob);
1509 int dm_drm_plane_set_property(struct drm_plane *plane,
1510 struct drm_plane_state *state,
1511 struct drm_property *property,
1514 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1515 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1519 if (property == adev->dm.degamma_lut_property) {
1520 ret = atomic_replace_property_blob_from_id(adev_to_drm(adev),
1521 &dm_plane_state->degamma_lut,
1522 val, -1, sizeof(struct drm_color_lut),
1524 } else if (property == adev->dm.ctm_property) {
1525 ret = atomic_replace_property_blob_from_id(adev_to_drm(adev),
1526 &dm_plane_state->ctm,
1528 sizeof(struct drm_color_ctm), -1,
1530 } else if (property == adev->dm.sdr_boost_property) {
1531 dm_plane_state->sdr_boost = val;
1539 int dm_drm_plane_get_property(struct drm_plane *plane,
1540 const struct drm_plane_state *state,
1541 struct drm_property *property,
1544 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1545 struct amdgpu_device *adev = drm_to_adev(plane->dev);
1547 if (property == adev->dm.degamma_lut_property) {
1548 *val = (dm_plane_state->degamma_lut) ?
1549 dm_plane_state->degamma_lut->base.id : 0;
1550 } else if (property == adev->dm.ctm_property) {
1551 *val = (dm_plane_state->ctm) ? dm_plane_state->ctm->base.id : 0;
1552 } else if (property == adev->dm.sdr_boost_property) {
1553 *val = dm_plane_state->sdr_boost;
1562 static const struct drm_plane_funcs dm_plane_funcs = {
1563 .update_plane = drm_atomic_helper_update_plane,
1564 .disable_plane = drm_atomic_helper_disable_plane,
1565 .destroy = drm_primary_helper_destroy,
1566 .reset = dm_drm_plane_reset,
1567 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
1568 .atomic_destroy_state = dm_drm_plane_destroy_state,
1569 .format_mod_supported = dm_plane_format_mod_supported,
1570 #ifdef CONFIG_DRM_AMD_DC_HDR
1571 .atomic_set_property = dm_drm_plane_set_property,
1572 .atomic_get_property = dm_drm_plane_get_property,
1576 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
1577 struct drm_plane *plane,
1578 unsigned long possible_crtcs,
1579 const struct dc_plane_cap *plane_cap)
1581 uint32_t formats[32];
1584 unsigned int supported_rotations;
1585 uint64_t *modifiers = NULL;
1587 num_formats = get_plane_formats(plane, plane_cap, formats,
1588 ARRAY_SIZE(formats));
1590 res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
1594 if (modifiers == NULL)
1595 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true;
1597 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
1598 &dm_plane_funcs, formats, num_formats,
1599 modifiers, plane->type, NULL);
1604 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
1605 plane_cap && plane_cap->per_pixel_alpha) {
1606 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1607 BIT(DRM_MODE_BLEND_PREMULTI) |
1608 BIT(DRM_MODE_BLEND_COVERAGE);
1610 drm_plane_create_alpha_property(plane);
1611 drm_plane_create_blend_mode_property(plane, blend_caps);
1614 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
1616 (plane_cap->pixel_format_support.nv12 ||
1617 plane_cap->pixel_format_support.p010)) {
1618 /* This only affects YUV formats. */
1619 drm_plane_create_color_properties(
1621 BIT(DRM_COLOR_YCBCR_BT601) |
1622 BIT(DRM_COLOR_YCBCR_BT709) |
1623 BIT(DRM_COLOR_YCBCR_BT2020),
1624 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1625 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1626 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
1629 supported_rotations =
1630 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1631 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1633 if (dm->adev->asic_type >= CHIP_BONAIRE &&
1634 plane->type != DRM_PLANE_TYPE_CURSOR)
1635 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1636 supported_rotations);
1638 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
1640 #ifdef CONFIG_DRM_AMD_DC_HDR
1641 attach_color_mgmt_properties(dm, plane);
1643 /* Create (reset) the plane state */
1644 if (plane->funcs->reset)
1645 plane->funcs->reset(plane);