2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/version.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include "dm_services.h"
31 #include "amdgpu_dm.h"
32 #include "amdgpu_dm_mst_types.h"
35 #include "dm_helpers.h"
37 #include "dc_link_ddc.h"
39 #include "i2caux_interface.h"
40 #if defined(CONFIG_DEBUG_FS)
41 #include "amdgpu_dm_debugfs.h"
45 #if defined(CONFIG_DRM_AMD_DC_DCN)
46 #include "dc/dcn20/dcn20_resource.h"
49 /* #define TRACE_DPCD */
52 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
54 static inline char *side_band_msg_type_to_str(uint32_t address)
56 static char str[10] = {0};
58 if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
59 strcpy(str, "DOWN_REQ");
60 else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
61 strcpy(str, "UP_REP");
62 else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
63 strcpy(str, "DOWN_REP");
65 strcpy(str, "UP_REQ");
70 static void log_dpcd(uint8_t type,
76 DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
77 (type == DP_AUX_NATIVE_READ) ||
78 (type == DP_AUX_I2C_READ) ?
81 SIDE_BAND_MSG(address) ?
82 side_band_msg_type_to_str(address) : "Nop",
86 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
91 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
92 struct drm_dp_aux_msg *msg)
95 struct aux_payload payload;
96 enum aux_channel_operation_result operation_result;
98 if (WARN_ON(msg->size > 16))
101 payload.address = msg->address;
102 payload.data = msg->buffer;
103 payload.length = msg->size;
104 payload.reply = &msg->reply;
105 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
106 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
107 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
108 payload.defer_delay = 0;
110 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
117 switch (operation_result) {
118 case AUX_CHANNEL_OPERATION_SUCCEEDED:
120 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
121 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
124 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
125 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
128 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
137 dm_dp_mst_connector_destroy(struct drm_connector *connector)
139 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
140 struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
142 kfree(amdgpu_dm_connector->edid);
143 amdgpu_dm_connector->edid = NULL;
145 drm_encoder_cleanup(&amdgpu_encoder->base);
146 kfree(amdgpu_encoder);
147 drm_connector_cleanup(connector);
148 drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
149 kfree(amdgpu_dm_connector);
153 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
155 struct amdgpu_dm_connector *amdgpu_dm_connector =
156 to_amdgpu_dm_connector(connector);
159 r = drm_dp_mst_connector_late_register(connector,
160 amdgpu_dm_connector->port);
164 #if defined(CONFIG_DEBUG_FS)
165 connector_debugfs_init(amdgpu_dm_connector);
172 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
174 struct amdgpu_dm_connector *amdgpu_dm_connector =
175 to_amdgpu_dm_connector(connector);
176 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
178 drm_dp_mst_connector_early_unregister(connector, port);
181 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
182 .fill_modes = drm_helper_probe_single_connector_modes,
183 .destroy = dm_dp_mst_connector_destroy,
184 .reset = amdgpu_dm_connector_funcs_reset,
185 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
186 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
187 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
188 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
189 .late_register = amdgpu_dm_mst_connector_late_register,
190 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
193 #if defined(CONFIG_DRM_AMD_DC_DCN)
194 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
196 struct dc_sink *dc_sink = aconnector->dc_sink;
197 struct drm_dp_mst_port *port = aconnector->port;
198 u8 dsc_caps[16] = { 0 };
200 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
202 if (!aconnector->dsc_aux)
205 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
208 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
210 &dc_sink->dsc_caps.dsc_dec_caps))
217 static int dm_dp_mst_get_modes(struct drm_connector *connector)
219 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
223 return drm_add_edid_modes(connector, NULL);
225 if (!aconnector->edid) {
227 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
230 drm_connector_update_edid_property(
236 aconnector->edid = edid;
239 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
240 dc_sink_release(aconnector->dc_sink);
241 aconnector->dc_sink = NULL;
244 if (!aconnector->dc_sink) {
245 struct dc_sink *dc_sink;
246 struct dc_sink_init_data init_params = {
247 .link = aconnector->dc_link,
248 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
249 dc_sink = dc_link_add_remote_sink(
251 (uint8_t *)aconnector->edid,
252 (aconnector->edid->extensions + 1) * EDID_LENGTH,
255 dc_sink->priv = aconnector;
256 /* dc_link_add_remote_sink returns a new reference */
257 aconnector->dc_sink = dc_sink;
259 if (aconnector->dc_sink) {
260 amdgpu_dm_update_freesync_caps(
261 connector, aconnector->edid);
263 #if defined(CONFIG_DRM_AMD_DC_DCN)
264 if (!validate_dsc_caps_on_connector(aconnector))
265 memset(&aconnector->dc_sink->dsc_caps,
266 0, sizeof(aconnector->dc_sink->dsc_caps));
271 drm_connector_update_edid_property(
272 &aconnector->base, aconnector->edid);
274 ret = drm_add_edid_modes(connector, aconnector->edid);
279 static struct drm_encoder *
280 dm_mst_atomic_best_encoder(struct drm_connector *connector,
281 struct drm_connector_state *connector_state)
283 return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
287 dm_dp_mst_detect(struct drm_connector *connector,
288 struct drm_modeset_acquire_ctx *ctx, bool force)
290 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
291 struct amdgpu_dm_connector *master = aconnector->mst_port;
293 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
297 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
298 struct drm_atomic_state *state)
300 struct drm_connector_state *new_conn_state =
301 drm_atomic_get_new_connector_state(state, connector);
302 struct drm_connector_state *old_conn_state =
303 drm_atomic_get_old_connector_state(state, connector);
304 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
305 struct drm_crtc_state *new_crtc_state;
306 struct drm_dp_mst_topology_mgr *mst_mgr;
307 struct drm_dp_mst_port *mst_port;
309 mst_port = aconnector->port;
310 mst_mgr = &aconnector->mst_port->mst_mgr;
312 if (!old_conn_state->crtc)
315 if (new_conn_state->crtc) {
316 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
317 if (!new_crtc_state ||
318 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
319 new_crtc_state->enable)
323 return drm_dp_atomic_release_vcpi_slots(state,
328 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
329 .get_modes = dm_dp_mst_get_modes,
330 .mode_valid = amdgpu_dm_connector_mode_valid,
331 .atomic_best_encoder = dm_mst_atomic_best_encoder,
332 .detect_ctx = dm_dp_mst_detect,
333 .atomic_check = dm_dp_mst_atomic_check,
336 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
338 drm_encoder_cleanup(encoder);
342 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
343 .destroy = amdgpu_dm_encoder_destroy,
346 static struct amdgpu_encoder *
347 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
349 struct drm_device *dev = connector->base.dev;
350 struct amdgpu_device *adev = dev->dev_private;
351 struct amdgpu_encoder *amdgpu_encoder;
352 struct drm_encoder *encoder;
354 amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
358 encoder = &amdgpu_encoder->base;
359 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
363 &amdgpu_encoder->base,
364 &amdgpu_dm_encoder_funcs,
365 DRM_MODE_ENCODER_DPMST,
368 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
370 return amdgpu_encoder;
373 static struct drm_connector *
374 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
375 struct drm_dp_mst_port *port,
376 const char *pathprop)
378 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
379 struct drm_device *dev = master->base.dev;
380 struct amdgpu_device *adev = dev->dev_private;
381 struct amdgpu_dm_connector *aconnector;
382 struct drm_connector *connector;
384 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
388 connector = &aconnector->base;
389 aconnector->port = port;
390 aconnector->mst_port = master;
392 if (drm_connector_init(
395 &dm_dp_mst_connector_funcs,
396 DRM_MODE_CONNECTOR_DisplayPort)) {
400 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
402 amdgpu_dm_connector_init_helper(
405 DRM_MODE_CONNECTOR_DisplayPort,
407 master->connector_id);
409 aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
410 drm_connector_attach_encoder(&aconnector->base,
411 &aconnector->mst_encoder->base);
413 connector->max_bpc_property = master->base.max_bpc_property;
414 if (connector->max_bpc_property)
415 drm_connector_attach_max_bpc_property(connector, 8, 16);
417 connector->vrr_capable_property = master->base.vrr_capable_property;
418 if (connector->vrr_capable_property)
419 drm_connector_attach_vrr_capable_property(connector);
421 drm_object_attach_property(
423 dev->mode_config.path_property,
425 drm_object_attach_property(
427 dev->mode_config.tile_property,
430 drm_connector_set_path_property(connector, pathprop);
433 * Initialize connector state before adding the connectror to drm and
436 amdgpu_dm_connector_funcs_reset(connector);
438 DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
439 aconnector, connector->base.id, aconnector->mst_port);
441 drm_dp_mst_get_port_malloc(port);
443 DRM_DEBUG_KMS(":%d\n", connector->base.id);
448 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
449 struct drm_connector *connector)
451 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
453 DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
454 aconnector, connector->base.id, aconnector->mst_port);
456 if (aconnector->dc_sink) {
457 amdgpu_dm_update_freesync_caps(connector, NULL);
458 dc_link_remove_remote_sink(aconnector->dc_link,
459 aconnector->dc_sink);
460 dc_sink_release(aconnector->dc_sink);
461 aconnector->dc_sink = NULL;
462 aconnector->dc_link->cur_link_settings.lane_count = 0;
465 drm_connector_unregister(connector);
466 drm_connector_put(connector);
469 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
470 .add_connector = dm_dp_add_mst_connector,
471 .destroy_connector = dm_dp_destroy_mst_connector,
474 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
475 struct amdgpu_dm_connector *aconnector,
478 aconnector->dm_dp_aux.aux.name =
479 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
481 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
482 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
484 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
485 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
488 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
491 aconnector->mst_mgr.cbs = &dm_mst_cbs;
492 drm_dp_mst_topology_mgr_init(
493 &aconnector->mst_mgr,
495 &aconnector->dm_dp_aux.aux,
498 aconnector->connector_id);
501 int dm_mst_get_pbn_divider(struct dc_link *link)
506 return dc_link_bandwidth_kbps(link,
507 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
510 #if defined(CONFIG_DRM_AMD_DC_DCN)
512 struct dsc_mst_fairness_params {
513 struct dc_crtc_timing *timing;
514 struct dc_sink *sink;
515 struct dc_dsc_bw_range bw_range;
516 bool compression_possible;
517 struct drm_dp_mst_port *port;
520 struct dsc_mst_fairness_vars {
526 static int kbps_to_peak_pbn(int kbps)
528 u64 peak_kbps = kbps;
531 peak_kbps = div_u64(peak_kbps, 1000);
532 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
535 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
536 struct dsc_mst_fairness_vars *vars,
541 for (i = 0; i < count; i++) {
542 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
543 if (vars[i].dsc_enabled && dc_dsc_compute_config(
544 params[i].sink->ctx->dc->res_pool->dscs[0],
545 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
546 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
549 ¶ms[i].timing->dsc_cfg)) {
550 params[i].timing->flags.DSC = 1;
551 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
553 params[i].timing->flags.DSC = 0;
558 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
560 struct dc_dsc_config dsc_config;
563 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
564 dc_dsc_compute_config(
565 param.sink->ctx->dc->res_pool->dscs[0],
566 ¶m.sink->dsc_caps.dsc_dec_caps,
567 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
568 (int) kbps, param.timing, &dsc_config);
570 return dsc_config.bits_per_pixel;
573 static void increase_dsc_bpp(struct drm_atomic_state *state,
574 struct dc_link *dc_link,
575 struct dsc_mst_fairness_params *params,
576 struct dsc_mst_fairness_vars *vars,
580 bool bpp_increased[MAX_PIPES];
581 int initial_slack[MAX_PIPES];
582 int min_initial_slack;
584 int remaining_to_increase = 0;
585 int pbn_per_timeslot;
586 int link_timeslots_used;
589 for (i = 0; i < count; i++) {
590 if (vars[i].dsc_enabled) {
591 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
592 bpp_increased[i] = false;
593 remaining_to_increase += 1;
595 initial_slack[i] = 0;
596 bpp_increased[i] = true;
600 pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
601 dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
603 while (remaining_to_increase) {
605 min_initial_slack = -1;
606 for (i = 0; i < count; i++) {
607 if (!bpp_increased[i]) {
608 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
609 min_initial_slack = initial_slack[i];
615 if (next_index == -1)
618 link_timeslots_used = 0;
620 for (i = 0; i < count; i++)
621 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
623 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
625 if (initial_slack[next_index] > fair_pbn_alloc) {
626 vars[next_index].pbn += fair_pbn_alloc;
627 if (drm_dp_atomic_find_vcpi_slots(state,
628 params[next_index].port->mgr,
629 params[next_index].port,
630 vars[next_index].pbn,
631 dm_mst_get_pbn_divider(dc_link)) < 0)
633 if (!drm_dp_mst_atomic_check(state)) {
634 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
636 vars[next_index].pbn -= fair_pbn_alloc;
637 if (drm_dp_atomic_find_vcpi_slots(state,
638 params[next_index].port->mgr,
639 params[next_index].port,
640 vars[next_index].pbn,
641 dm_mst_get_pbn_divider(dc_link)) < 0)
645 vars[next_index].pbn += initial_slack[next_index];
646 if (drm_dp_atomic_find_vcpi_slots(state,
647 params[next_index].port->mgr,
648 params[next_index].port,
649 vars[next_index].pbn,
650 dm_mst_get_pbn_divider(dc_link)) < 0)
652 if (!drm_dp_mst_atomic_check(state)) {
653 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
655 vars[next_index].pbn -= initial_slack[next_index];
656 if (drm_dp_atomic_find_vcpi_slots(state,
657 params[next_index].port->mgr,
658 params[next_index].port,
659 vars[next_index].pbn,
660 dm_mst_get_pbn_divider(dc_link)) < 0)
665 bpp_increased[next_index] = true;
666 remaining_to_increase--;
670 static void try_disable_dsc(struct drm_atomic_state *state,
671 struct dc_link *dc_link,
672 struct dsc_mst_fairness_params *params,
673 struct dsc_mst_fairness_vars *vars,
677 bool tried[MAX_PIPES];
678 int kbps_increase[MAX_PIPES];
679 int max_kbps_increase;
681 int remaining_to_try = 0;
683 for (i = 0; i < count; i++) {
684 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
685 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
687 remaining_to_try += 1;
689 kbps_increase[i] = 0;
694 while (remaining_to_try) {
696 max_kbps_increase = -1;
697 for (i = 0; i < count; i++) {
699 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
700 max_kbps_increase = kbps_increase[i];
706 if (next_index == -1)
709 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
710 if (drm_dp_atomic_find_vcpi_slots(state,
711 params[next_index].port->mgr,
712 params[next_index].port,
713 vars[next_index].pbn,
717 if (!drm_dp_mst_atomic_check(state)) {
718 vars[next_index].dsc_enabled = false;
719 vars[next_index].bpp_x16 = 0;
721 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
722 if (drm_dp_atomic_find_vcpi_slots(state,
723 params[next_index].port->mgr,
724 params[next_index].port,
725 vars[next_index].pbn,
726 dm_mst_get_pbn_divider(dc_link)) < 0)
730 tried[next_index] = true;
735 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
736 struct dc_state *dc_state,
737 struct dc_link *dc_link)
740 struct dc_stream_state *stream;
741 struct dsc_mst_fairness_params params[MAX_PIPES];
742 struct dsc_mst_fairness_vars vars[MAX_PIPES];
743 struct amdgpu_dm_connector *aconnector;
746 memset(params, 0, sizeof(params));
749 for (i = 0; i < dc_state->stream_count; i++) {
750 struct dc_dsc_policy dsc_policy = {0};
752 stream = dc_state->streams[i];
754 if (stream->link != dc_link)
757 stream->timing.flags.DSC = 0;
759 params[count].timing = &stream->timing;
760 params[count].sink = stream->sink;
761 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
762 params[count].port = aconnector->port;
763 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
764 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
765 if (!dc_dsc_compute_bandwidth_range(
766 stream->sink->ctx->dc->res_pool->dscs[0],
767 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
768 dsc_policy.min_target_bpp,
769 dsc_policy.max_target_bpp,
770 &stream->sink->dsc_caps.dsc_dec_caps,
771 &stream->timing, ¶ms[count].bw_range))
772 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
776 /* Try no compression */
777 for (i = 0; i < count; i++) {
778 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
779 vars[i].dsc_enabled = false;
781 if (drm_dp_atomic_find_vcpi_slots(state,
788 if (!drm_dp_mst_atomic_check(state)) {
789 set_dsc_configs_from_fairness_vars(params, vars, count);
793 /* Try max compression */
794 for (i = 0; i < count; i++) {
795 if (params[i].compression_possible) {
796 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
797 vars[i].dsc_enabled = true;
798 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
799 if (drm_dp_atomic_find_vcpi_slots(state,
803 dm_mst_get_pbn_divider(dc_link)) < 0)
806 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
807 vars[i].dsc_enabled = false;
809 if (drm_dp_atomic_find_vcpi_slots(state,
817 if (drm_dp_mst_atomic_check(state))
820 /* Optimize degree of compression */
821 increase_dsc_bpp(state, dc_link, params, vars, count);
823 try_disable_dsc(state, dc_link, params, vars, count);
825 set_dsc_configs_from_fairness_vars(params, vars, count);
830 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
831 struct dc_state *dc_state)
834 struct dc_stream_state *stream;
835 bool computed_streams[MAX_PIPES];
836 struct amdgpu_dm_connector *aconnector;
838 for (i = 0; i < dc_state->stream_count; i++)
839 computed_streams[i] = false;
841 for (i = 0; i < dc_state->stream_count; i++) {
842 stream = dc_state->streams[i];
844 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
847 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
849 if (!aconnector || !aconnector->dc_sink)
852 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
855 if (computed_streams[i])
858 mutex_lock(&aconnector->mst_mgr.lock);
859 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
860 mutex_unlock(&aconnector->mst_mgr.lock);
863 mutex_unlock(&aconnector->mst_mgr.lock);
865 for (j = 0; j < dc_state->stream_count; j++) {
866 if (dc_state->streams[j]->link == stream->link)
867 computed_streams[j] = true;
871 for (i = 0; i < dc_state->stream_count; i++) {
872 stream = dc_state->streams[i];
874 if (stream->timing.flags.DSC == 1)
875 dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);