drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include <drm/drm_dp_helper.h>
  30 #include "dm_services.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_mst_types.h"
  34
  35 #include "dc.h"
  36 #include "dm_helpers.h"
  37
  38 #include "dc_link_ddc.h"
  39
  40 #include "i2caux_interface.h"
  41 #include "dmub_cmd.h"
  42 #if defined(CONFIG_DEBUG_FS)
  43 #include "amdgpu_dm_debugfs.h"
  44 #endif
  45
  46 #if defined(CONFIG_DRM_AMD_DC_DCN)
  47 #include "dc/dcn20/dcn20_resource.h"
  48 #endif
  49
  50 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  51                                   struct drm_dp_aux_msg *msg)
  52 {
  53         ssize_t result = 0;
  54         struct aux_payload payload;
  55         enum aux_return_code_type operation_result;
  56
  57         if (WARN_ON(msg->size > 16))
  58                 return -E2BIG;
  59
  60         payload.address = msg->address;
  61         payload.data = msg->buffer;
  62         payload.length = msg->size;
  63         payload.reply = &msg->reply;
  64         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  65         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  66         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  67         payload.write_status_update =
  68                         (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
  69         payload.defer_delay = 0;
  70
  71         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
  72                                       &operation_result);
  73
  74         if (payload.write && result >= 0)
  75                 result = msg->size;
  76
  77         if (result < 0)
  78                 switch (operation_result) {
  79                 case AUX_RET_SUCCESS:
  80                         break;
  81                 case AUX_RET_ERROR_HPD_DISCON:
  82                 case AUX_RET_ERROR_UNKNOWN:
  83                 case AUX_RET_ERROR_INVALID_OPERATION:
  84                 case AUX_RET_ERROR_PROTOCOL_ERROR:
  85                         result = -EIO;
  86                         break;
  87                 case AUX_RET_ERROR_INVALID_REPLY:
  88                 case AUX_RET_ERROR_ENGINE_ACQUIRE:
  89                         result = -EBUSY;
  90                         break;
  91                 case AUX_RET_ERROR_TIMEOUT:
  92                         result = -ETIMEDOUT;
  93                         break;
  94                 }
  95
  96         return result;
  97 }
  98
  99 static void
 100 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 101 {
 102         struct amdgpu_dm_connector *aconnector =
 103                 to_amdgpu_dm_connector(connector);
 104
 105         if (aconnector->dc_sink) {
 106                 dc_link_remove_remote_sink(aconnector->dc_link,
 107                                            aconnector->dc_sink);
 108                 dc_sink_release(aconnector->dc_sink);
 109         }
 110
 111         kfree(aconnector->edid);
 112
 113         drm_connector_cleanup(connector);
 114         drm_dp_mst_put_port_malloc(aconnector->port);
 115         kfree(aconnector);
 116 }
 117
 118 static int
 119 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 120 {
 121         struct amdgpu_dm_connector *amdgpu_dm_connector =
 122                 to_amdgpu_dm_connector(connector);
 123         int r;
 124
 125         r = drm_dp_mst_connector_late_register(connector,
 126                                                amdgpu_dm_connector->port);
 127         if (r < 0)
 128                 return r;
 129
 130 #if defined(CONFIG_DEBUG_FS)
 131         connector_debugfs_init(amdgpu_dm_connector);
 132 #endif
 133
 134         return 0;
 135 }
 136
 137 static void
 138 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 139 {
 140         struct amdgpu_dm_connector *amdgpu_dm_connector =
 141                 to_amdgpu_dm_connector(connector);
 142         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 143
 144         drm_dp_mst_connector_early_unregister(connector, port);
 145 }
 146
 147 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 148         .fill_modes = drm_helper_probe_single_connector_modes,
 149         .destroy = dm_dp_mst_connector_destroy,
 150         .reset = amdgpu_dm_connector_funcs_reset,
 151         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 152         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 153         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 154         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 155         .late_register = amdgpu_dm_mst_connector_late_register,
 156         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 157 };
 158
 159 #if defined(CONFIG_DRM_AMD_DC_DCN)
 160 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 161 {
 162         struct dc_sink *dc_sink = aconnector->dc_sink;
 163         struct drm_dp_mst_port *port = aconnector->port;
 164         u8 dsc_caps[16] = { 0 };
 165         u8 dsc_branch_dec_caps_raw[3] = { 0 };  // DSC branch decoder caps 0xA0 ~ 0xA2
 166         u8 *dsc_branch_dec_caps = NULL;
 167
 168         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 169 #if defined(CONFIG_HP_HOOK_WORKAROUND)
 170         /*
 171          * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
 172          * because it only check the dsc/fec caps of the "port variable" and not the dock
 173          *
 174          * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
 175          *
 176          * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
 177          *
 178          */
 179
 180         if (!aconnector->dsc_aux && !port->parent->port_parent)
 181                 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
 182 #endif
 183         if (!aconnector->dsc_aux)
 184                 return false;
 185
 186         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 187                 return false;
 188
 189         if (drm_dp_dpcd_read(aconnector->dsc_aux,
 190                         DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
 191                 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
 192
 193         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 194                                   dsc_caps, dsc_branch_dec_caps,
 195                                   &dc_sink->dsc_caps.dsc_dec_caps))
 196                 return false;
 197
 198         return true;
 199 }
 200 #endif
 201
 202 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 203 {
 204         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 205         int ret = 0;
 206
 207         if (!aconnector)
 208                 return drm_add_edid_modes(connector, NULL);
 209
 210         if (!aconnector->edid) {
 211                 struct edid *edid;
 212                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 213
 214                 if (!edid) {
 215                         drm_connector_update_edid_property(
 216                                 &aconnector->base,
 217                                 NULL);
 218
 219                         DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
 220                         if (!aconnector->dc_sink) {
 221                                 struct dc_sink *dc_sink;
 222                                 struct dc_sink_init_data init_params = {
 223                                         .link = aconnector->dc_link,
 224                                         .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 225
 226                                 dc_sink = dc_link_add_remote_sink(
 227                                         aconnector->dc_link,
 228                                         NULL,
 229                                         0,
 230                                         &init_params);
 231
 232                                 if (!dc_sink) {
 233                                         DRM_ERROR("Unable to add a remote sink\n");
 234                                         return 0;
 235                                 }
 236
 237                                 dc_sink->priv = aconnector;
 238                                 aconnector->dc_sink = dc_sink;
 239                         }
 240
 241                         return ret;
 242                 }
 243
 244                 aconnector->edid = edid;
 245         }
 246
 247         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 248                 dc_sink_release(aconnector->dc_sink);
 249                 aconnector->dc_sink = NULL;
 250         }
 251
 252         if (!aconnector->dc_sink) {
 253                 struct dc_sink *dc_sink;
 254                 struct dc_sink_init_data init_params = {
 255                                 .link = aconnector->dc_link,
 256                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 257                 dc_sink = dc_link_add_remote_sink(
 258                         aconnector->dc_link,
 259                         (uint8_t *)aconnector->edid,
 260                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 261                         &init_params);
 262
 263                 if (!dc_sink) {
 264                         DRM_ERROR("Unable to add a remote sink\n");
 265                         return 0;
 266                 }
 267
 268                 dc_sink->priv = aconnector;
 269                 /* dc_link_add_remote_sink returns a new reference */
 270                 aconnector->dc_sink = dc_sink;
 271
 272                 if (aconnector->dc_sink) {
 273                         amdgpu_dm_update_freesync_caps(
 274                                         connector, aconnector->edid);
 275
 276 #if defined(CONFIG_DRM_AMD_DC_DCN)
 277                         if (!validate_dsc_caps_on_connector(aconnector))
 278                                 memset(&aconnector->dc_sink->dsc_caps,
 279                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 280 #endif
 281                 }
 282         }
 283
 284         drm_connector_update_edid_property(
 285                                         &aconnector->base, aconnector->edid);
 286
 287         ret = drm_add_edid_modes(connector, aconnector->edid);
 288
 289         return ret;
 290 }
 291
 292 static struct drm_encoder *
 293 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 294                            struct drm_atomic_state *state)
 295 {
 296         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
 297                                                                                          connector);
 298         struct drm_device *dev = connector->dev;
 299         struct amdgpu_device *adev = drm_to_adev(dev);
 300         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
 301
 302         return &adev->dm.mst_encoders[acrtc->crtc_id].base;
 303 }
 304
 305 static int
 306 dm_dp_mst_detect(struct drm_connector *connector,
 307                  struct drm_modeset_acquire_ctx *ctx, bool force)
 308 {
 309         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 310         struct amdgpu_dm_connector *master = aconnector->mst_port;
 311
 312         if (drm_connector_is_unregistered(connector))
 313                 return connector_status_disconnected;
 314
 315         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 316                                       aconnector->port);
 317 }
 318
 319 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 320                                 struct drm_atomic_state *state)
 321 {
 322         struct drm_connector_state *new_conn_state =
 323                         drm_atomic_get_new_connector_state(state, connector);
 324         struct drm_connector_state *old_conn_state =
 325                         drm_atomic_get_old_connector_state(state, connector);
 326         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 327         struct drm_crtc_state *new_crtc_state;
 328         struct drm_dp_mst_topology_mgr *mst_mgr;
 329         struct drm_dp_mst_port *mst_port;
 330
 331         mst_port = aconnector->port;
 332         mst_mgr = &aconnector->mst_port->mst_mgr;
 333
 334         if (!old_conn_state->crtc)
 335                 return 0;
 336
 337         if (new_conn_state->crtc) {
 338                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 339                 if (!new_crtc_state ||
 340                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 341                     new_crtc_state->enable)
 342                         return 0;
 343                 }
 344
 345         return drm_dp_atomic_release_vcpi_slots(state,
 346                                                 mst_mgr,
 347                                                 mst_port);
 348 }
 349
 350 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 351         .get_modes = dm_dp_mst_get_modes,
 352         .mode_valid = amdgpu_dm_connector_mode_valid,
 353         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 354         .detect_ctx = dm_dp_mst_detect,
 355         .atomic_check = dm_dp_mst_atomic_check,
 356 };
 357
 358 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 359 {
 360         drm_encoder_cleanup(encoder);
 361         kfree(encoder);
 362 }
 363
 364 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 365         .destroy = amdgpu_dm_encoder_destroy,
 366 };
 367
 368 void
 369 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
 370 {
 371         struct drm_device *dev = adev_to_drm(adev);
 372         int i;
 373
 374         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 375                 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
 376                 struct drm_encoder *encoder = &amdgpu_encoder->base;
 377
 378                 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 379
 380                 drm_encoder_init(
 381                         dev,
 382                         &amdgpu_encoder->base,
 383                         &amdgpu_dm_encoder_funcs,
 384                         DRM_MODE_ENCODER_DPMST,
 385                         NULL);
 386
 387                 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 388         }
 389 }
 390
 391 static struct drm_connector *
 392 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 393                         struct drm_dp_mst_port *port,
 394                         const char *pathprop)
 395 {
 396         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 397         struct drm_device *dev = master->base.dev;
 398         struct amdgpu_device *adev = drm_to_adev(dev);
 399         struct amdgpu_dm_connector *aconnector;
 400         struct drm_connector *connector;
 401         int i;
 402
 403         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 404         if (!aconnector)
 405                 return NULL;
 406
 407         connector = &aconnector->base;
 408         aconnector->port = port;
 409         aconnector->mst_port = master;
 410
 411         if (drm_connector_init(
 412                 dev,
 413                 connector,
 414                 &dm_dp_mst_connector_funcs,
 415                 DRM_MODE_CONNECTOR_DisplayPort)) {
 416                 kfree(aconnector);
 417                 return NULL;
 418         }
 419         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 420
 421         amdgpu_dm_connector_init_helper(
 422                 &adev->dm,
 423                 aconnector,
 424                 DRM_MODE_CONNECTOR_DisplayPort,
 425                 master->dc_link,
 426                 master->connector_id);
 427
 428         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 429                 drm_connector_attach_encoder(&aconnector->base,
 430                                              &adev->dm.mst_encoders[i].base);
 431         }
 432
 433         connector->max_bpc_property = master->base.max_bpc_property;
 434         if (connector->max_bpc_property)
 435                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 436
 437         connector->vrr_capable_property = master->base.vrr_capable_property;
 438         if (connector->vrr_capable_property)
 439                 drm_connector_attach_vrr_capable_property(connector);
 440
 441         drm_object_attach_property(
 442                 &connector->base,
 443                 dev->mode_config.path_property,
 444                 0);
 445         drm_object_attach_property(
 446                 &connector->base,
 447                 dev->mode_config.tile_property,
 448                 0);
 449
 450         drm_connector_set_path_property(connector, pathprop);
 451
 452         /*
 453          * Initialize connector state before adding the connectror to drm and
 454          * framebuffer lists
 455          */
 456         amdgpu_dm_connector_funcs_reset(connector);
 457
 458         drm_dp_mst_get_port_malloc(port);
 459
 460         return connector;
 461 }
 462
 463 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 464         .add_connector = dm_dp_add_mst_connector,
 465 };
 466
 467 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 468                                        struct amdgpu_dm_connector *aconnector,
 469                                        int link_index)
 470 {
 471         struct dc_link_settings max_link_enc_cap = {0};
 472
 473         aconnector->dm_dp_aux.aux.name =
 474                 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
 475                           link_index);
 476         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 477         aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
 478         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 479
 480         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 481         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 482                                       &aconnector->base);
 483
 484         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 485                 return;
 486
 487         dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
 488         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 489         drm_dp_mst_topology_mgr_init(
 490                 &aconnector->mst_mgr,
 491                 adev_to_drm(dm->adev),
 492                 &aconnector->dm_dp_aux.aux,
 493                 16,
 494                 4,
 495                 max_link_enc_cap.lane_count,
 496                 drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate),
 497                 aconnector->connector_id);
 498
 499         drm_connector_attach_dp_subconnector_property(&aconnector->base);
 500 }
 501
 502 int dm_mst_get_pbn_divider(struct dc_link *link)
 503 {
 504         if (!link)
 505                 return 0;
 506
 507         return dc_link_bandwidth_kbps(link,
 508                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 509 }
 510
 511 #if defined(CONFIG_DRM_AMD_DC_DCN)
 512
 513 struct dsc_mst_fairness_params {
 514         struct dc_crtc_timing *timing;
 515         struct dc_sink *sink;
 516         struct dc_dsc_bw_range bw_range;
 517         bool compression_possible;
 518         struct drm_dp_mst_port *port;
 519         enum dsc_clock_force_state clock_force_enable;
 520         uint32_t num_slices_h;
 521         uint32_t num_slices_v;
 522         uint32_t bpp_overwrite;
 523         struct amdgpu_dm_connector *aconnector;
 524 };
 525
 526 static int kbps_to_peak_pbn(int kbps)
 527 {
 528         u64 peak_kbps = kbps;
 529
 530         peak_kbps *= 1006;
 531         peak_kbps = div_u64(peak_kbps, 1000);
 532         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 533 }
 534
 535 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 536                 struct dsc_mst_fairness_vars *vars,
 537                 int count)
 538 {
 539         int i;
 540
 541         for (i = 0; i < count; i++) {
 542                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 543                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 544                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 545                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 546                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 547                                         params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
 548                                         0,
 549                                         params[i].timing,
 550                                         &params[i].timing->dsc_cfg)) {
 551                         params[i].timing->flags.DSC = 1;
 552
 553                         if (params[i].bpp_overwrite)
 554                                 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
 555                         else
 556                                 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 557
 558                         if (params[i].num_slices_h)
 559                                 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
 560
 561                         if (params[i].num_slices_v)
 562                                 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
 563                 } else {
 564                         params[i].timing->flags.DSC = 0;
 565                 }
 566         }
 567 }
 568
 569 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 570 {
 571         struct dc_dsc_config dsc_config;
 572         u64 kbps;
 573
 574         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 575         dc_dsc_compute_config(
 576                         param.sink->ctx->dc->res_pool->dscs[0],
 577                         &param.sink->dsc_caps.dsc_dec_caps,
 578                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 579                         param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
 580                         (int) kbps, param.timing, &dsc_config);
 581
 582         return dsc_config.bits_per_pixel;
 583 }
 584
 585 static void increase_dsc_bpp(struct drm_atomic_state *state,
 586                              struct dc_link *dc_link,
 587                              struct dsc_mst_fairness_params *params,
 588                              struct dsc_mst_fairness_vars *vars,
 589                              int count)
 590 {
 591         int i;
 592         bool bpp_increased[MAX_PIPES];
 593         int initial_slack[MAX_PIPES];
 594         int min_initial_slack;
 595         int next_index;
 596         int remaining_to_increase = 0;
 597         int pbn_per_timeslot;
 598         int link_timeslots_used;
 599         int fair_pbn_alloc;
 600
 601         pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
 602
 603         for (i = 0; i < count; i++) {
 604                 if (vars[i].dsc_enabled) {
 605                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 606                         bpp_increased[i] = false;
 607                         remaining_to_increase += 1;
 608                 } else {
 609                         initial_slack[i] = 0;
 610                         bpp_increased[i] = true;
 611                 }
 612         }
 613
 614         while (remaining_to_increase) {
 615                 next_index = -1;
 616                 min_initial_slack = -1;
 617                 for (i = 0; i < count; i++) {
 618                         if (!bpp_increased[i]) {
 619                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 620                                         min_initial_slack = initial_slack[i];
 621                                         next_index = i;
 622                                 }
 623                         }
 624                 }
 625
 626                 if (next_index == -1)
 627                         break;
 628
 629                 link_timeslots_used = 0;
 630
 631                 for (i = 0; i < count; i++)
 632                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 633
 634                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 635
 636                 if (initial_slack[next_index] > fair_pbn_alloc) {
 637                         vars[next_index].pbn += fair_pbn_alloc;
 638                         if (drm_dp_atomic_find_vcpi_slots(state,
 639                                                           params[next_index].port->mgr,
 640                                                           params[next_index].port,
 641                                                           vars[next_index].pbn,
 642                                                           pbn_per_timeslot) < 0)
 643                                 return;
 644                         if (!drm_dp_mst_atomic_check(state)) {
 645                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 646                         } else {
 647                                 vars[next_index].pbn -= fair_pbn_alloc;
 648                                 if (drm_dp_atomic_find_vcpi_slots(state,
 649                                                                   params[next_index].port->mgr,
 650                                                                   params[next_index].port,
 651                                                                   vars[next_index].pbn,
 652                                                                   pbn_per_timeslot) < 0)
 653                                         return;
 654                         }
 655                 } else {
 656                         vars[next_index].pbn += initial_slack[next_index];
 657                         if (drm_dp_atomic_find_vcpi_slots(state,
 658                                                           params[next_index].port->mgr,
 659                                                           params[next_index].port,
 660                                                           vars[next_index].pbn,
 661                                                           pbn_per_timeslot) < 0)
 662                                 return;
 663                         if (!drm_dp_mst_atomic_check(state)) {
 664                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 665                         } else {
 666                                 vars[next_index].pbn -= initial_slack[next_index];
 667                                 if (drm_dp_atomic_find_vcpi_slots(state,
 668                                                                   params[next_index].port->mgr,
 669                                                                   params[next_index].port,
 670                                                                   vars[next_index].pbn,
 671                                                                   pbn_per_timeslot) < 0)
 672                                         return;
 673                         }
 674                 }
 675
 676                 bpp_increased[next_index] = true;
 677                 remaining_to_increase--;
 678         }
 679 }
 680
 681 static void try_disable_dsc(struct drm_atomic_state *state,
 682                             struct dc_link *dc_link,
 683                             struct dsc_mst_fairness_params *params,
 684                             struct dsc_mst_fairness_vars *vars,
 685                             int count)
 686 {
 687         int i;
 688         bool tried[MAX_PIPES];
 689         int kbps_increase[MAX_PIPES];
 690         int max_kbps_increase;
 691         int next_index;
 692         int remaining_to_try = 0;
 693
 694         for (i = 0; i < count; i++) {
 695                 if (vars[i].dsc_enabled
 696                                 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
 697                                 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
 698                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 699                         tried[i] = false;
 700                         remaining_to_try += 1;
 701                 } else {
 702                         kbps_increase[i] = 0;
 703                         tried[i] = true;
 704                 }
 705         }
 706
 707         while (remaining_to_try) {
 708                 next_index = -1;
 709                 max_kbps_increase = -1;
 710                 for (i = 0; i < count; i++) {
 711                         if (!tried[i]) {
 712                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 713                                         max_kbps_increase = kbps_increase[i];
 714                                         next_index = i;
 715                                 }
 716                         }
 717                 }
 718
 719                 if (next_index == -1)
 720                         break;
 721
 722                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 723                 if (drm_dp_atomic_find_vcpi_slots(state,
 724                                                   params[next_index].port->mgr,
 725                                                   params[next_index].port,
 726                                                   vars[next_index].pbn,
 727                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 728                         return;
 729
 730                 if (!drm_dp_mst_atomic_check(state)) {
 731                         vars[next_index].dsc_enabled = false;
 732                         vars[next_index].bpp_x16 = 0;
 733                 } else {
 734                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 735                         if (drm_dp_atomic_find_vcpi_slots(state,
 736                                                           params[next_index].port->mgr,
 737                                                           params[next_index].port,
 738                                                           vars[next_index].pbn,
 739                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 740                                 return;
 741                 }
 742
 743                 tried[next_index] = true;
 744                 remaining_to_try--;
 745         }
 746 }
 747
 748 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 749                                              struct dc_state *dc_state,
 750                                              struct dc_link *dc_link,
 751                                              struct dsc_mst_fairness_vars *vars)
 752 {
 753         int i;
 754         struct dc_stream_state *stream;
 755         struct dsc_mst_fairness_params params[MAX_PIPES];
 756         struct amdgpu_dm_connector *aconnector;
 757         int count = 0;
 758         bool debugfs_overwrite = false;
 759
 760         memset(params, 0, sizeof(params));
 761
 762         /* Set up params */
 763         for (i = 0; i < dc_state->stream_count; i++) {
 764                 struct dc_dsc_policy dsc_policy = {0};
 765
 766                 stream = dc_state->streams[i];
 767
 768                 if (stream->link != dc_link)
 769                         continue;
 770
 771                 stream->timing.flags.DSC = 0;
 772
 773                 params[count].timing = &stream->timing;
 774                 params[count].sink = stream->sink;
 775                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 776                 params[count].aconnector = aconnector;
 777                 params[count].port = aconnector->port;
 778                 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
 779                 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
 780                         debugfs_overwrite = true;
 781                 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
 782                 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
 783                 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
 784                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 785                 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
 786                 if (!dc_dsc_compute_bandwidth_range(
 787                                 stream->sink->ctx->dc->res_pool->dscs[0],
 788                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 789                                 dsc_policy.min_target_bpp * 16,
 790                                 dsc_policy.max_target_bpp * 16,
 791                                 &stream->sink->dsc_caps.dsc_dec_caps,
 792                                 &stream->timing, &params[count].bw_range))
 793                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 794
 795                 count++;
 796         }
 797         /* Try no compression */
 798         for (i = 0; i < count; i++) {
 799                 vars[i].aconnector = params[i].aconnector;
 800                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 801                 vars[i].dsc_enabled = false;
 802                 vars[i].bpp_x16 = 0;
 803                 if (drm_dp_atomic_find_vcpi_slots(state,
 804                                                  params[i].port->mgr,
 805                                                  params[i].port,
 806                                                  vars[i].pbn,
 807                                                  dm_mst_get_pbn_divider(dc_link)) < 0)
 808                         return false;
 809         }
 810         if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
 811                 set_dsc_configs_from_fairness_vars(params, vars, count);
 812                 return true;
 813         }
 814
 815         /* Try max compression */
 816         for (i = 0; i < count; i++) {
 817                 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
 818                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 819                         vars[i].dsc_enabled = true;
 820                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 821                         if (drm_dp_atomic_find_vcpi_slots(state,
 822                                                           params[i].port->mgr,
 823                                                           params[i].port,
 824                                                           vars[i].pbn,
 825                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 826                                 return false;
 827                 } else {
 828                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 829                         vars[i].dsc_enabled = false;
 830                         vars[i].bpp_x16 = 0;
 831                         if (drm_dp_atomic_find_vcpi_slots(state,
 832                                                           params[i].port->mgr,
 833                                                           params[i].port,
 834                                                           vars[i].pbn,
 835                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 836                                 return false;
 837                 }
 838         }
 839         if (drm_dp_mst_atomic_check(state))
 840                 return false;
 841
 842         /* Optimize degree of compression */
 843         increase_dsc_bpp(state, dc_link, params, vars, count);
 844
 845         try_disable_dsc(state, dc_link, params, vars, count);
 846
 847         set_dsc_configs_from_fairness_vars(params, vars, count);
 848
 849         return true;
 850 }
 851
 852 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 853                                        struct dc_state *dc_state,
 854                                        struct dsc_mst_fairness_vars *vars)
 855 {
 856         int i, j;
 857         struct dc_stream_state *stream;
 858         bool computed_streams[MAX_PIPES];
 859         struct amdgpu_dm_connector *aconnector;
 860
 861         for (i = 0; i < dc_state->stream_count; i++)
 862                 computed_streams[i] = false;
 863
 864         for (i = 0; i < dc_state->stream_count; i++) {
 865                 stream = dc_state->streams[i];
 866
 867                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 868                         continue;
 869
 870                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 871
 872                 if (!aconnector || !aconnector->dc_sink)
 873                         continue;
 874
 875                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 876                         continue;
 877
 878                 if (computed_streams[i])
 879                         continue;
 880
 881                 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
 882                         return false;
 883
 884                 mutex_lock(&aconnector->mst_mgr.lock);
 885                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars)) {
 886                         mutex_unlock(&aconnector->mst_mgr.lock);
 887                         return false;
 888                 }
 889                 mutex_unlock(&aconnector->mst_mgr.lock);
 890
 891                 for (j = 0; j < dc_state->stream_count; j++) {
 892                         if (dc_state->streams[j]->link == stream->link)
 893                                 computed_streams[j] = true;
 894                 }
 895         }
 896
 897         for (i = 0; i < dc_state->stream_count; i++) {
 898                 stream = dc_state->streams[i];
 899
 900                 if (stream->timing.flags.DSC == 1)
 901                         if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
 902                                 return false;
 903         }
 904
 905         return true;
 906 }
 907
 908 #endif