drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_mst_types.h"
  33
  34 #include "dc.h"
  35 #include "dm_helpers.h"
  36
  37 #include "dc_link_ddc.h"
  38
  39 #include "i2caux_interface.h"
  40 #if defined(CONFIG_DEBUG_FS)
  41 #include "amdgpu_dm_debugfs.h"
  42 #endif
  43
  44 #if defined(CONFIG_DRM_AMD_DC_DCN)
  45 #include "dc/dcn20/dcn20_resource.h"
  46 #endif
  47
  48 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  49                                   struct drm_dp_aux_msg *msg)
  50 {
  51         ssize_t result = 0;
  52         struct aux_payload payload;
  53         enum aux_channel_operation_result operation_result;
  54
  55         if (WARN_ON(msg->size > 16))
  56                 return -E2BIG;
  57
  58         payload.address = msg->address;
  59         payload.data = msg->buffer;
  60         payload.length = msg->size;
  61         payload.reply = &msg->reply;
  62         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  63         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  64         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  65         payload.defer_delay = 0;
  66
  67         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
  68                                       &operation_result);
  69
  70         if (payload.write)
  71                 result = msg->size;
  72
  73         if (result < 0)
  74                 switch (operation_result) {
  75                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
  76                         break;
  77                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
  78                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
  79                         result = -EIO;
  80                         break;
  81                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
  82                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
  83                         result = -EBUSY;
  84                         break;
  85                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
  86                         result = -ETIMEDOUT;
  87                         break;
  88                 }
  89
  90         return result;
  91 }
  92
  93 static void
  94 dm_dp_mst_connector_destroy(struct drm_connector *connector)
  95 {
  96         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
  97         struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
  98
  99         kfree(amdgpu_dm_connector->edid);
 100         amdgpu_dm_connector->edid = NULL;
 101
 102         drm_encoder_cleanup(&amdgpu_encoder->base);
 103         kfree(amdgpu_encoder);
 104         drm_connector_cleanup(connector);
 105         drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
 106         kfree(amdgpu_dm_connector);
 107 }
 108
 109 static int
 110 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 111 {
 112         struct amdgpu_dm_connector *amdgpu_dm_connector =
 113                 to_amdgpu_dm_connector(connector);
 114         int r;
 115
 116         amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
 117         r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
 118         if (r)
 119                 return r;
 120
 121 #if defined(CONFIG_DEBUG_FS)
 122         connector_debugfs_init(amdgpu_dm_connector);
 123 #endif
 124
 125         return r;
 126 }
 127
 128 static void
 129 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 130 {
 131         struct amdgpu_dm_connector *amdgpu_dm_connector =
 132                 to_amdgpu_dm_connector(connector);
 133         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 134
 135         drm_dp_mst_connector_early_unregister(connector, port);
 136 }
 137
 138 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 139         .fill_modes = drm_helper_probe_single_connector_modes,
 140         .destroy = dm_dp_mst_connector_destroy,
 141         .reset = amdgpu_dm_connector_funcs_reset,
 142         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 143         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 144         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 145         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 146         .late_register = amdgpu_dm_mst_connector_late_register,
 147         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 148 };
 149
 150 #if defined(CONFIG_DRM_AMD_DC_DCN)
 151 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 152 {
 153         struct dc_sink *dc_sink = aconnector->dc_sink;
 154         struct drm_dp_mst_port *port = aconnector->port;
 155         u8 dsc_caps[16] = { 0 };
 156
 157         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 158
 159         if (!aconnector->dsc_aux)
 160                 return false;
 161
 162         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 163                 return false;
 164
 165         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 166                                    dsc_caps, NULL,
 167                                    &dc_sink->dsc_caps.dsc_dec_caps))
 168                 return false;
 169
 170         return true;
 171 }
 172 #endif
 173
 174 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 175 {
 176         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 177         int ret = 0;
 178
 179         if (!aconnector)
 180                 return drm_add_edid_modes(connector, NULL);
 181
 182         if (!aconnector->edid) {
 183                 struct edid *edid;
 184                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 185
 186                 if (!edid) {
 187                         drm_connector_update_edid_property(
 188                                 &aconnector->base,
 189                                 NULL);
 190                         return ret;
 191                 }
 192
 193                 aconnector->edid = edid;
 194         }
 195
 196         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 197                 dc_sink_release(aconnector->dc_sink);
 198                 aconnector->dc_sink = NULL;
 199         }
 200
 201         if (!aconnector->dc_sink) {
 202                 struct dc_sink *dc_sink;
 203                 struct dc_sink_init_data init_params = {
 204                                 .link = aconnector->dc_link,
 205                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 206                 dc_sink = dc_link_add_remote_sink(
 207                         aconnector->dc_link,
 208                         (uint8_t *)aconnector->edid,
 209                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 210                         &init_params);
 211
 212                 dc_sink->priv = aconnector;
 213                 /* dc_link_add_remote_sink returns a new reference */
 214                 aconnector->dc_sink = dc_sink;
 215
 216                 if (aconnector->dc_sink) {
 217                         amdgpu_dm_update_freesync_caps(
 218                                         connector, aconnector->edid);
 219
 220 #if defined(CONFIG_DRM_AMD_DC_DCN)
 221                         if (!validate_dsc_caps_on_connector(aconnector))
 222                                 memset(&aconnector->dc_sink->dsc_caps,
 223                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 224 #endif
 225                 }
 226         }
 227
 228         drm_connector_update_edid_property(
 229                                         &aconnector->base, aconnector->edid);
 230
 231         ret = drm_add_edid_modes(connector, aconnector->edid);
 232
 233         return ret;
 234 }
 235
 236 static struct drm_encoder *
 237 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 238                            struct drm_connector_state *connector_state)
 239 {
 240         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 241 }
 242
 243 static int
 244 dm_dp_mst_detect(struct drm_connector *connector,
 245                  struct drm_modeset_acquire_ctx *ctx, bool force)
 246 {
 247         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 248         struct amdgpu_dm_connector *master = aconnector->mst_port;
 249
 250         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 251                                       aconnector->port);
 252 }
 253
 254 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 255                                 struct drm_atomic_state *state)
 256 {
 257         struct drm_connector_state *new_conn_state =
 258                         drm_atomic_get_new_connector_state(state, connector);
 259         struct drm_connector_state *old_conn_state =
 260                         drm_atomic_get_old_connector_state(state, connector);
 261         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 262         struct drm_crtc_state *new_crtc_state;
 263         struct drm_dp_mst_topology_mgr *mst_mgr;
 264         struct drm_dp_mst_port *mst_port;
 265
 266         mst_port = aconnector->port;
 267         mst_mgr = &aconnector->mst_port->mst_mgr;
 268
 269         if (!old_conn_state->crtc)
 270                 return 0;
 271
 272         if (new_conn_state->crtc) {
 273                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 274                 if (!new_crtc_state ||
 275                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 276                     new_crtc_state->enable)
 277                         return 0;
 278                 }
 279
 280         return drm_dp_atomic_release_vcpi_slots(state,
 281                                                 mst_mgr,
 282                                                 mst_port);
 283 }
 284
 285 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 286         .get_modes = dm_dp_mst_get_modes,
 287         .mode_valid = amdgpu_dm_connector_mode_valid,
 288         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 289         .detect_ctx = dm_dp_mst_detect,
 290         .atomic_check = dm_dp_mst_atomic_check,
 291 };
 292
 293 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 294 {
 295         drm_encoder_cleanup(encoder);
 296         kfree(encoder);
 297 }
 298
 299 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 300         .destroy = amdgpu_dm_encoder_destroy,
 301 };
 302
 303 static struct amdgpu_encoder *
 304 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 305 {
 306         struct drm_device *dev = connector->base.dev;
 307         struct amdgpu_device *adev = dev->dev_private;
 308         struct amdgpu_encoder *amdgpu_encoder;
 309         struct drm_encoder *encoder;
 310
 311         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 312         if (!amdgpu_encoder)
 313                 return NULL;
 314
 315         encoder = &amdgpu_encoder->base;
 316         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 317
 318         drm_encoder_init(
 319                 dev,
 320                 &amdgpu_encoder->base,
 321                 &amdgpu_dm_encoder_funcs,
 322                 DRM_MODE_ENCODER_DPMST,
 323                 NULL);
 324
 325         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 326
 327         return amdgpu_encoder;
 328 }
 329
 330 static struct drm_connector *
 331 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 332                         struct drm_dp_mst_port *port,
 333                         const char *pathprop)
 334 {
 335         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 336         struct drm_device *dev = master->base.dev;
 337         struct amdgpu_device *adev = dev->dev_private;
 338         struct amdgpu_dm_connector *aconnector;
 339         struct drm_connector *connector;
 340
 341         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 342         if (!aconnector)
 343                 return NULL;
 344
 345         connector = &aconnector->base;
 346         aconnector->port = port;
 347         aconnector->mst_port = master;
 348
 349         if (drm_connector_init(
 350                 dev,
 351                 connector,
 352                 &dm_dp_mst_connector_funcs,
 353                 DRM_MODE_CONNECTOR_DisplayPort)) {
 354                 kfree(aconnector);
 355                 return NULL;
 356         }
 357         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 358
 359         amdgpu_dm_connector_init_helper(
 360                 &adev->dm,
 361                 aconnector,
 362                 DRM_MODE_CONNECTOR_DisplayPort,
 363                 master->dc_link,
 364                 master->connector_id);
 365
 366         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 367         drm_connector_attach_encoder(&aconnector->base,
 368                                      &aconnector->mst_encoder->base);
 369
 370         drm_object_attach_property(
 371                 &connector->base,
 372                 dev->mode_config.path_property,
 373                 0);
 374         drm_object_attach_property(
 375                 &connector->base,
 376                 dev->mode_config.tile_property,
 377                 0);
 378
 379         drm_connector_set_path_property(connector, pathprop);
 380
 381         /*
 382          * Initialize connector state before adding the connectror to drm and
 383          * framebuffer lists
 384          */
 385         amdgpu_dm_connector_funcs_reset(connector);
 386
 387         DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
 388                  aconnector, connector->base.id, aconnector->mst_port);
 389
 390         drm_dp_mst_get_port_malloc(port);
 391
 392         DRM_DEBUG_KMS(":%d\n", connector->base.id);
 393
 394         return connector;
 395 }
 396
 397 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 398                                         struct drm_connector *connector)
 399 {
 400         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 401
 402         DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
 403                  aconnector, connector->base.id, aconnector->mst_port);
 404
 405         if (aconnector->dc_sink) {
 406                 amdgpu_dm_update_freesync_caps(connector, NULL);
 407                 dc_link_remove_remote_sink(aconnector->dc_link,
 408                                            aconnector->dc_sink);
 409                 dc_sink_release(aconnector->dc_sink);
 410                 aconnector->dc_sink = NULL;
 411                 aconnector->dc_link->cur_link_settings.lane_count = 0;
 412         }
 413
 414         drm_connector_unregister(connector);
 415         drm_connector_put(connector);
 416 }
 417
 418 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 419         .add_connector = dm_dp_add_mst_connector,
 420         .destroy_connector = dm_dp_destroy_mst_connector,
 421 };
 422
 423 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 424                                        struct amdgpu_dm_connector *aconnector)
 425 {
 426         aconnector->dm_dp_aux.aux.name = "dmdc";
 427         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 428         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 429
 430         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 431         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 432                                       &aconnector->base);
 433
 434         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 435                 return;
 436
 437         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 438         drm_dp_mst_topology_mgr_init(
 439                 &aconnector->mst_mgr,
 440                 dm->adev->ddev,
 441                 &aconnector->dm_dp_aux.aux,
 442                 16,
 443                 4,
 444                 aconnector->connector_id);
 445 }
 446
 447 int dm_mst_get_pbn_divider(struct dc_link *link)
 448 {
 449         if (!link)
 450                 return 0;
 451
 452         return dc_link_bandwidth_kbps(link,
 453                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 454 }
 455
 456 #if defined(CONFIG_DRM_AMD_DC_DCN)
 457
 458 struct dsc_mst_fairness_params {
 459         struct dc_crtc_timing *timing;
 460         struct dc_sink *sink;
 461         struct dc_dsc_bw_range bw_range;
 462         bool compression_possible;
 463         struct drm_dp_mst_port *port;
 464 };
 465
 466 struct dsc_mst_fairness_vars {
 467         int pbn;
 468         bool dsc_enabled;
 469         int bpp_x16;
 470 };
 471
 472 static int kbps_to_peak_pbn(int kbps)
 473 {
 474         u64 peak_kbps = kbps;
 475
 476         peak_kbps *= 1006;
 477         peak_kbps = div_u64(peak_kbps, 1000);
 478         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 479 }
 480
 481 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 482                 struct dsc_mst_fairness_vars *vars,
 483                 int count)
 484 {
 485         int i;
 486
 487         for (i = 0; i < count; i++) {
 488                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 489                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 490                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 491                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 492                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 493                                         0,
 494                                         params[i].timing,
 495                                         &params[i].timing->dsc_cfg)) {
 496                         params[i].timing->flags.DSC = 1;
 497                         params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 498                 } else {
 499                         params[i].timing->flags.DSC = 0;
 500                 }
 501         }
 502 }
 503
 504 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 505 {
 506         struct dc_dsc_config dsc_config;
 507         u64 kbps;
 508
 509         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 510         dc_dsc_compute_config(
 511                         param.sink->ctx->dc->res_pool->dscs[0],
 512                         &param.sink->dsc_caps.dsc_dec_caps,
 513                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 514                         (int) kbps, param.timing, &dsc_config);
 515
 516         return dsc_config.bits_per_pixel;
 517 }
 518
 519 static void increase_dsc_bpp(struct drm_atomic_state *state,
 520                              struct dc_link *dc_link,
 521                              struct dsc_mst_fairness_params *params,
 522                              struct dsc_mst_fairness_vars *vars,
 523                              int count)
 524 {
 525         int i;
 526         bool bpp_increased[MAX_PIPES];
 527         int initial_slack[MAX_PIPES];
 528         int min_initial_slack;
 529         int next_index;
 530         int remaining_to_increase = 0;
 531         int pbn_per_timeslot;
 532         int link_timeslots_used;
 533         int fair_pbn_alloc;
 534
 535         for (i = 0; i < count; i++) {
 536                 if (vars[i].dsc_enabled) {
 537                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 538                         bpp_increased[i] = false;
 539                         remaining_to_increase += 1;
 540                 } else {
 541                         initial_slack[i] = 0;
 542                         bpp_increased[i] = true;
 543                 }
 544         }
 545
 546         pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
 547                         dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
 548
 549         while (remaining_to_increase) {
 550                 next_index = -1;
 551                 min_initial_slack = -1;
 552                 for (i = 0; i < count; i++) {
 553                         if (!bpp_increased[i]) {
 554                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 555                                         min_initial_slack = initial_slack[i];
 556                                         next_index = i;
 557                                 }
 558                         }
 559                 }
 560
 561                 if (next_index == -1)
 562                         break;
 563
 564                 link_timeslots_used = 0;
 565
 566                 for (i = 0; i < count; i++)
 567                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 568
 569                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 570
 571                 if (initial_slack[next_index] > fair_pbn_alloc) {
 572                         vars[next_index].pbn += fair_pbn_alloc;
 573                         if (drm_dp_atomic_find_vcpi_slots(state,
 574                                                           params[next_index].port->mgr,
 575                                                           params[next_index].port,
 576                                                           vars[next_index].pbn,
 577                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 578                                 return;
 579                         if (!drm_dp_mst_atomic_check(state)) {
 580                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 581                         } else {
 582                                 vars[next_index].pbn -= fair_pbn_alloc;
 583                                 if (drm_dp_atomic_find_vcpi_slots(state,
 584                                                                   params[next_index].port->mgr,
 585                                                                   params[next_index].port,
 586                                                                   vars[next_index].pbn,
 587                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 588                                         return;
 589                         }
 590                 } else {
 591                         vars[next_index].pbn += initial_slack[next_index];
 592                         if (drm_dp_atomic_find_vcpi_slots(state,
 593                                                           params[next_index].port->mgr,
 594                                                           params[next_index].port,
 595                                                           vars[next_index].pbn,
 596                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 597                                 return;
 598                         if (!drm_dp_mst_atomic_check(state)) {
 599                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 600                         } else {
 601                                 vars[next_index].pbn -= initial_slack[next_index];
 602                                 if (drm_dp_atomic_find_vcpi_slots(state,
 603                                                                   params[next_index].port->mgr,
 604                                                                   params[next_index].port,
 605                                                                   vars[next_index].pbn,
 606                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 607                                         return;
 608                         }
 609                 }
 610
 611                 bpp_increased[next_index] = true;
 612                 remaining_to_increase--;
 613         }
 614 }
 615
 616 static void try_disable_dsc(struct drm_atomic_state *state,
 617                             struct dc_link *dc_link,
 618                             struct dsc_mst_fairness_params *params,
 619                             struct dsc_mst_fairness_vars *vars,
 620                             int count)
 621 {
 622         int i;
 623         bool tried[MAX_PIPES];
 624         int kbps_increase[MAX_PIPES];
 625         int max_kbps_increase;
 626         int next_index;
 627         int remaining_to_try = 0;
 628
 629         for (i = 0; i < count; i++) {
 630                 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
 631                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 632                         tried[i] = false;
 633                         remaining_to_try += 1;
 634                 } else {
 635                         kbps_increase[i] = 0;
 636                         tried[i] = true;
 637                 }
 638         }
 639
 640         while (remaining_to_try) {
 641                 next_index = -1;
 642                 max_kbps_increase = -1;
 643                 for (i = 0; i < count; i++) {
 644                         if (!tried[i]) {
 645                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 646                                         max_kbps_increase = kbps_increase[i];
 647                                         next_index = i;
 648                                 }
 649                         }
 650                 }
 651
 652                 if (next_index == -1)
 653                         break;
 654
 655                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 656                 if (drm_dp_atomic_find_vcpi_slots(state,
 657                                                   params[next_index].port->mgr,
 658                                                   params[next_index].port,
 659                                                   vars[next_index].pbn,
 660                                                   0) < 0)
 661                         return;
 662
 663                 if (!drm_dp_mst_atomic_check(state)) {
 664                         vars[next_index].dsc_enabled = false;
 665                         vars[next_index].bpp_x16 = 0;
 666                 } else {
 667                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 668                         if (drm_dp_atomic_find_vcpi_slots(state,
 669                                                           params[next_index].port->mgr,
 670                                                           params[next_index].port,
 671                                                           vars[next_index].pbn,
 672                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 673                                 return;
 674                 }
 675
 676                 tried[next_index] = true;
 677                 remaining_to_try--;
 678         }
 679 }
 680
 681 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 682                                              struct dc_state *dc_state,
 683                                              struct dc_link *dc_link)
 684 {
 685         int i;
 686         struct dc_stream_state *stream;
 687         struct dsc_mst_fairness_params params[MAX_PIPES];
 688         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 689         struct amdgpu_dm_connector *aconnector;
 690         int count = 0;
 691
 692         memset(params, 0, sizeof(params));
 693
 694         /* Set up params */
 695         for (i = 0; i < dc_state->stream_count; i++) {
 696                 struct dc_dsc_policy dsc_policy = {0};
 697
 698                 stream = dc_state->streams[i];
 699
 700                 if (stream->link != dc_link)
 701                         continue;
 702
 703                 stream->timing.flags.DSC = 0;
 704
 705                 params[count].timing = &stream->timing;
 706                 params[count].sink = stream->sink;
 707                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 708                 params[count].port = aconnector->port;
 709                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 710                 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 711                 if (!dc_dsc_compute_bandwidth_range(
 712                                 stream->sink->ctx->dc->res_pool->dscs[0],
 713                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 714                                 dsc_policy.min_target_bpp,
 715                                 dsc_policy.max_target_bpp,
 716                                 &stream->sink->dsc_caps.dsc_dec_caps,
 717                                 &stream->timing, &params[count].bw_range))
 718                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 719
 720                 count++;
 721         }
 722         /* Try no compression */
 723         for (i = 0; i < count; i++) {
 724                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 725                 vars[i].dsc_enabled = false;
 726                 vars[i].bpp_x16 = 0;
 727                 if (drm_dp_atomic_find_vcpi_slots(state,
 728                                                  params[i].port->mgr,
 729                                                  params[i].port,
 730                                                  vars[i].pbn,
 731                                                  0) < 0)
 732                         return false;
 733         }
 734         if (!drm_dp_mst_atomic_check(state)) {
 735                 set_dsc_configs_from_fairness_vars(params, vars, count);
 736                 return true;
 737         }
 738
 739         /* Try max compression */
 740         for (i = 0; i < count; i++) {
 741                 if (params[i].compression_possible) {
 742                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 743                         vars[i].dsc_enabled = true;
 744                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 745                         if (drm_dp_atomic_find_vcpi_slots(state,
 746                                                           params[i].port->mgr,
 747                                                           params[i].port,
 748                                                           vars[i].pbn,
 749                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 750                                 return false;
 751                 } else {
 752                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 753                         vars[i].dsc_enabled = false;
 754                         vars[i].bpp_x16 = 0;
 755                         if (drm_dp_atomic_find_vcpi_slots(state,
 756                                                           params[i].port->mgr,
 757                                                           params[i].port,
 758                                                           vars[i].pbn,
 759                                                           0) < 0)
 760                                 return false;
 761                 }
 762         }
 763         if (drm_dp_mst_atomic_check(state))
 764                 return false;
 765
 766         /* Optimize degree of compression */
 767         increase_dsc_bpp(state, dc_link, params, vars, count);
 768
 769         try_disable_dsc(state, dc_link, params, vars, count);
 770
 771         set_dsc_configs_from_fairness_vars(params, vars, count);
 772
 773         return true;
 774 }
 775
 776 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 777                                        struct dc_state *dc_state)
 778 {
 779         int i, j;
 780         struct dc_stream_state *stream;
 781         bool computed_streams[MAX_PIPES];
 782         struct amdgpu_dm_connector *aconnector;
 783
 784         for (i = 0; i < dc_state->stream_count; i++)
 785                 computed_streams[i] = false;
 786
 787         for (i = 0; i < dc_state->stream_count; i++) {
 788                 stream = dc_state->streams[i];
 789
 790                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 791                         continue;
 792
 793                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 794
 795                 if (!aconnector || !aconnector->dc_sink)
 796                         continue;
 797
 798                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 799                         continue;
 800
 801                 if (computed_streams[i])
 802                         continue;
 803
 804                 mutex_lock(&aconnector->mst_mgr.lock);
 805                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 806                         mutex_unlock(&aconnector->mst_mgr.lock);
 807                         return false;
 808                 }
 809                 mutex_unlock(&aconnector->mst_mgr.lock);
 810
 811                 for (j = 0; j < dc_state->stream_count; j++) {
 812                         if (dc_state->streams[j]->link == stream->link)
 813                                 computed_streams[j] = true;
 814                 }
 815         }
 816
 817         for (i = 0; i < dc_state->stream_count; i++) {
 818                 stream = dc_state->streams[i];
 819
 820                 if (stream->timing.flags.DSC == 1)
 821                         dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
 822         }
 823
 824         return true;
 825 }
 826
 827 #endif