drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_mst_types.h"
  33
  34 #include "dc.h"
  35 #include "dm_helpers.h"
  36
  37 #include "dc_link_ddc.h"
  38
  39 #include "i2caux_interface.h"
  40 #if defined(CONFIG_DEBUG_FS)
  41 #include "amdgpu_dm_debugfs.h"
  42 #endif
  43
  44
  45 #if defined(CONFIG_DRM_AMD_DC_DCN)
  46 #include "dc/dcn20/dcn20_resource.h"
  47 #endif
  48
  49 /* #define TRACE_DPCD */
  50
  51 #ifdef TRACE_DPCD
  52 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
  53
  54 static inline char *side_band_msg_type_to_str(uint32_t address)
  55 {
  56         static char str[10] = {0};
  57
  58         if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
  59                 strcpy(str, "DOWN_REQ");
  60         else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
  61                 strcpy(str, "UP_REP");
  62         else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
  63                 strcpy(str, "DOWN_REP");
  64         else
  65                 strcpy(str, "UP_REQ");
  66
  67         return str;
  68 }
  69
  70 static void log_dpcd(uint8_t type,
  71                      uint32_t address,
  72                      uint8_t *data,
  73                      uint32_t size,
  74                      bool res)
  75 {
  76         DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
  77                         (type == DP_AUX_NATIVE_READ) ||
  78                         (type == DP_AUX_I2C_READ) ?
  79                                         "Read" : "Write",
  80                         address,
  81                         SIDE_BAND_MSG(address) ?
  82                                         side_band_msg_type_to_str(address) : "Nop",
  83                         res ? "OK" : "Fail");
  84
  85         if (res) {
  86                 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
  87         }
  88 }
  89 #endif
  90
  91 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  92                                   struct drm_dp_aux_msg *msg)
  93 {
  94         ssize_t result = 0;
  95         struct aux_payload payload;
  96         enum aux_channel_operation_result operation_result;
  97
  98         if (WARN_ON(msg->size > 16))
  99                 return -E2BIG;
 100
 101         payload.address = msg->address;
 102         payload.data = msg->buffer;
 103         payload.length = msg->size;
 104         payload.reply = &msg->reply;
 105         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
 106         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
 107         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
 108         payload.defer_delay = 0;
 109
 110         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
 111                                       &operation_result);
 112
 113         if (payload.write)
 114                 result = msg->size;
 115
 116         if (result < 0)
 117                 switch (operation_result) {
 118                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
 119                         break;
 120                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
 121                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
 122                         result = -EIO;
 123                         break;
 124                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
 125                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
 126                         result = -EBUSY;
 127                         break;
 128                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
 129                         result = -ETIMEDOUT;
 130                         break;
 131                 }
 132
 133         return result;
 134 }
 135
 136 static void
 137 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 138 {
 139         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
 140         struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
 141
 142         kfree(amdgpu_dm_connector->edid);
 143
 144         drm_encoder_cleanup(&amdgpu_encoder->base);
 145         kfree(amdgpu_encoder);
 146         drm_connector_cleanup(connector);
 147         drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
 148         kfree(amdgpu_dm_connector);
 149 }
 150
 151 static int
 152 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 153 {
 154         struct amdgpu_dm_connector *amdgpu_dm_connector =
 155                 to_amdgpu_dm_connector(connector);
 156         int r;
 157
 158         amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
 159         r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
 160         if (r)
 161                 return r;
 162
 163 #if defined(CONFIG_DEBUG_FS)
 164         connector_debugfs_init(amdgpu_dm_connector);
 165 #endif
 166
 167         return r;
 168 }
 169
 170 static void
 171 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 172 {
 173         struct amdgpu_dm_connector *amdgpu_dm_connector =
 174                 to_amdgpu_dm_connector(connector);
 175         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 176
 177         drm_dp_mst_connector_early_unregister(connector, port);
 178 }
 179
 180 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 181         .fill_modes = drm_helper_probe_single_connector_modes,
 182         .destroy = dm_dp_mst_connector_destroy,
 183         .reset = amdgpu_dm_connector_funcs_reset,
 184         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 185         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 186         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 187         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 188         .late_register = amdgpu_dm_mst_connector_late_register,
 189         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 190 };
 191
 192 #if defined(CONFIG_DRM_AMD_DC_DCN)
 193 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 194 {
 195         struct dc_sink *dc_sink = aconnector->dc_sink;
 196         struct drm_dp_mst_port *port = aconnector->port;
 197         u8 dsc_caps[16] = { 0 };
 198
 199         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 200
 201         if (!aconnector->dsc_aux)
 202                 return false;
 203
 204         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 205                 return false;
 206
 207         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 208                                    dsc_caps, NULL,
 209                                    &dc_sink->dsc_caps.dsc_dec_caps))
 210                 return false;
 211
 212         return true;
 213 }
 214 #endif
 215
 216 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 217 {
 218         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 219         int ret = 0;
 220
 221         if (!aconnector)
 222                 return drm_add_edid_modes(connector, NULL);
 223
 224         if (!aconnector->edid) {
 225                 struct edid *edid;
 226                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 227
 228                 if (!edid) {
 229                         drm_connector_update_edid_property(
 230                                 &aconnector->base,
 231                                 NULL);
 232                         return ret;
 233                 }
 234
 235                 aconnector->edid = edid;
 236         }
 237
 238         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 239                 dc_sink_release(aconnector->dc_sink);
 240                 aconnector->dc_sink = NULL;
 241         }
 242
 243         if (!aconnector->dc_sink) {
 244                 struct dc_sink *dc_sink;
 245                 struct dc_sink_init_data init_params = {
 246                                 .link = aconnector->dc_link,
 247                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 248                 dc_sink = dc_link_add_remote_sink(
 249                         aconnector->dc_link,
 250                         (uint8_t *)aconnector->edid,
 251                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 252                         &init_params);
 253
 254                 dc_sink->priv = aconnector;
 255                 /* dc_link_add_remote_sink returns a new reference */
 256                 aconnector->dc_sink = dc_sink;
 257
 258                 if (aconnector->dc_sink) {
 259                         amdgpu_dm_update_freesync_caps(
 260                                         connector, aconnector->edid);
 261
 262 #if defined(CONFIG_DRM_AMD_DC_DCN)
 263                         if (!validate_dsc_caps_on_connector(aconnector))
 264                                 memset(&aconnector->dc_sink->dsc_caps,
 265                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 266 #endif
 267                 }
 268         }
 269
 270         drm_connector_update_edid_property(
 271                                         &aconnector->base, aconnector->edid);
 272
 273         ret = drm_add_edid_modes(connector, aconnector->edid);
 274
 275         return ret;
 276 }
 277
 278 static struct drm_encoder *
 279 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 280                            struct drm_connector_state *connector_state)
 281 {
 282         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 283 }
 284
 285 static int
 286 dm_dp_mst_detect(struct drm_connector *connector,
 287                  struct drm_modeset_acquire_ctx *ctx, bool force)
 288 {
 289         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 290         struct amdgpu_dm_connector *master = aconnector->mst_port;
 291
 292         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 293                                       aconnector->port);
 294 }
 295
 296 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 297                                 struct drm_atomic_state *state)
 298 {
 299         struct drm_connector_state *new_conn_state =
 300                         drm_atomic_get_new_connector_state(state, connector);
 301         struct drm_connector_state *old_conn_state =
 302                         drm_atomic_get_old_connector_state(state, connector);
 303         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 304         struct drm_crtc_state *new_crtc_state;
 305         struct drm_dp_mst_topology_mgr *mst_mgr;
 306         struct drm_dp_mst_port *mst_port;
 307
 308         mst_port = aconnector->port;
 309         mst_mgr = &aconnector->mst_port->mst_mgr;
 310
 311         if (!old_conn_state->crtc)
 312                 return 0;
 313
 314         if (new_conn_state->crtc) {
 315                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 316                 if (!new_crtc_state ||
 317                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 318                     new_crtc_state->enable)
 319                         return 0;
 320                 }
 321
 322         return drm_dp_atomic_release_vcpi_slots(state,
 323                                                 mst_mgr,
 324                                                 mst_port);
 325 }
 326
 327 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 328         .get_modes = dm_dp_mst_get_modes,
 329         .mode_valid = amdgpu_dm_connector_mode_valid,
 330         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 331         .detect_ctx = dm_dp_mst_detect,
 332         .atomic_check = dm_dp_mst_atomic_check,
 333 };
 334
 335 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 336 {
 337         drm_encoder_cleanup(encoder);
 338         kfree(encoder);
 339 }
 340
 341 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 342         .destroy = amdgpu_dm_encoder_destroy,
 343 };
 344
 345 static struct amdgpu_encoder *
 346 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 347 {
 348         struct drm_device *dev = connector->base.dev;
 349         struct amdgpu_device *adev = dev->dev_private;
 350         struct amdgpu_encoder *amdgpu_encoder;
 351         struct drm_encoder *encoder;
 352
 353         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 354         if (!amdgpu_encoder)
 355                 return NULL;
 356
 357         encoder = &amdgpu_encoder->base;
 358         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 359
 360         drm_encoder_init(
 361                 dev,
 362                 &amdgpu_encoder->base,
 363                 &amdgpu_dm_encoder_funcs,
 364                 DRM_MODE_ENCODER_DPMST,
 365                 NULL);
 366
 367         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 368
 369         return amdgpu_encoder;
 370 }
 371
 372 static struct drm_connector *
 373 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 374                         struct drm_dp_mst_port *port,
 375                         const char *pathprop)
 376 {
 377         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 378         struct drm_device *dev = master->base.dev;
 379         struct amdgpu_device *adev = dev->dev_private;
 380         struct amdgpu_dm_connector *aconnector;
 381         struct drm_connector *connector;
 382
 383         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 384         if (!aconnector)
 385                 return NULL;
 386
 387         connector = &aconnector->base;
 388         aconnector->port = port;
 389         aconnector->mst_port = master;
 390
 391         if (drm_connector_init(
 392                 dev,
 393                 connector,
 394                 &dm_dp_mst_connector_funcs,
 395                 DRM_MODE_CONNECTOR_DisplayPort)) {
 396                 kfree(aconnector);
 397                 return NULL;
 398         }
 399         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 400
 401         amdgpu_dm_connector_init_helper(
 402                 &adev->dm,
 403                 aconnector,
 404                 DRM_MODE_CONNECTOR_DisplayPort,
 405                 master->dc_link,
 406                 master->connector_id);
 407
 408         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 409         drm_connector_attach_encoder(&aconnector->base,
 410                                      &aconnector->mst_encoder->base);
 411
 412         drm_object_attach_property(
 413                 &connector->base,
 414                 dev->mode_config.path_property,
 415                 0);
 416         drm_object_attach_property(
 417                 &connector->base,
 418                 dev->mode_config.tile_property,
 419                 0);
 420
 421         drm_connector_set_path_property(connector, pathprop);
 422
 423         /*
 424          * Initialize connector state before adding the connectror to drm and
 425          * framebuffer lists
 426          */
 427         amdgpu_dm_connector_funcs_reset(connector);
 428
 429         DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
 430                  aconnector, connector->base.id, aconnector->mst_port);
 431
 432         drm_dp_mst_get_port_malloc(port);
 433
 434         DRM_DEBUG_KMS(":%d\n", connector->base.id);
 435
 436         return connector;
 437 }
 438
 439 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 440                                         struct drm_connector *connector)
 441 {
 442         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 443
 444         DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
 445                  aconnector, connector->base.id, aconnector->mst_port);
 446
 447         if (aconnector->dc_sink) {
 448                 amdgpu_dm_update_freesync_caps(connector, NULL);
 449                 dc_link_remove_remote_sink(aconnector->dc_link,
 450                                            aconnector->dc_sink);
 451                 dc_sink_release(aconnector->dc_sink);
 452                 aconnector->dc_sink = NULL;
 453                 aconnector->dc_link->cur_link_settings.lane_count = 0;
 454         }
 455
 456         drm_connector_unregister(connector);
 457         drm_connector_put(connector);
 458 }
 459
 460 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 461         .add_connector = dm_dp_add_mst_connector,
 462         .destroy_connector = dm_dp_destroy_mst_connector,
 463 };
 464
 465 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 466                                        struct amdgpu_dm_connector *aconnector)
 467 {
 468         aconnector->dm_dp_aux.aux.name = "dmdc";
 469         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 470         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 471
 472         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 473         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 474                                       &aconnector->base);
 475
 476         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 477                 return;
 478
 479         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 480         drm_dp_mst_topology_mgr_init(
 481                 &aconnector->mst_mgr,
 482                 dm->adev->ddev,
 483                 &aconnector->dm_dp_aux.aux,
 484                 16,
 485                 4,
 486                 aconnector->connector_id);
 487 }
 488
 489 int dm_mst_get_pbn_divider(struct dc_link *link)
 490 {
 491         if (!link)
 492                 return 0;
 493
 494         return dc_link_bandwidth_kbps(link,
 495                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 496 }
 497
 498 #if defined(CONFIG_DRM_AMD_DC_DCN)
 499
 500 struct dsc_mst_fairness_params {
 501         struct dc_crtc_timing *timing;
 502         struct dc_sink *sink;
 503         struct dc_dsc_bw_range bw_range;
 504         bool compression_possible;
 505         struct drm_dp_mst_port *port;
 506 };
 507
 508 struct dsc_mst_fairness_vars {
 509         int pbn;
 510         bool dsc_enabled;
 511         int bpp_x16;
 512 };
 513
 514 static int kbps_to_peak_pbn(int kbps)
 515 {
 516         u64 peak_kbps = kbps;
 517
 518         peak_kbps *= 1006;
 519         peak_kbps = div_u64(peak_kbps, 1000);
 520         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 521 }
 522
 523 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 524                 struct dsc_mst_fairness_vars *vars,
 525                 int count)
 526 {
 527         int i;
 528
 529         for (i = 0; i < count; i++) {
 530                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 531                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 532                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 533                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 534                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 535                                         0,
 536                                         params[i].timing,
 537                                         &params[i].timing->dsc_cfg)) {
 538                         params[i].timing->flags.DSC = 1;
 539                         params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 540                 } else {
 541                         params[i].timing->flags.DSC = 0;
 542                 }
 543         }
 544 }
 545
 546 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 547 {
 548         struct dc_dsc_config dsc_config;
 549         u64 kbps;
 550
 551         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 552         dc_dsc_compute_config(
 553                         param.sink->ctx->dc->res_pool->dscs[0],
 554                         &param.sink->dsc_caps.dsc_dec_caps,
 555                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 556                         (int) kbps, param.timing, &dsc_config);
 557
 558         return dsc_config.bits_per_pixel;
 559 }
 560
 561 static void increase_dsc_bpp(struct drm_atomic_state *state,
 562                              struct dc_link *dc_link,
 563                              struct dsc_mst_fairness_params *params,
 564                              struct dsc_mst_fairness_vars *vars,
 565                              int count)
 566 {
 567         int i;
 568         bool bpp_increased[MAX_PIPES];
 569         int initial_slack[MAX_PIPES];
 570         int min_initial_slack;
 571         int next_index;
 572         int remaining_to_increase = 0;
 573         int pbn_per_timeslot;
 574         int link_timeslots_used;
 575         int fair_pbn_alloc;
 576
 577         for (i = 0; i < count; i++) {
 578                 if (vars[i].dsc_enabled) {
 579                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 580                         bpp_increased[i] = false;
 581                         remaining_to_increase += 1;
 582                 } else {
 583                         initial_slack[i] = 0;
 584                         bpp_increased[i] = true;
 585                 }
 586         }
 587
 588         pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
 589                         dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
 590
 591         while (remaining_to_increase) {
 592                 next_index = -1;
 593                 min_initial_slack = -1;
 594                 for (i = 0; i < count; i++) {
 595                         if (!bpp_increased[i]) {
 596                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 597                                         min_initial_slack = initial_slack[i];
 598                                         next_index = i;
 599                                 }
 600                         }
 601                 }
 602
 603                 if (next_index == -1)
 604                         break;
 605
 606                 link_timeslots_used = 0;
 607
 608                 for (i = 0; i < count; i++)
 609                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 610
 611                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 612
 613                 if (initial_slack[next_index] > fair_pbn_alloc) {
 614                         vars[next_index].pbn += fair_pbn_alloc;
 615                         if (drm_dp_atomic_find_vcpi_slots(state,
 616                                                           params[next_index].port->mgr,
 617                                                           params[next_index].port,
 618                                                           vars[next_index].pbn,
 619                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 620                                 return;
 621                         if (!drm_dp_mst_atomic_check(state)) {
 622                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 623                         } else {
 624                                 vars[next_index].pbn -= fair_pbn_alloc;
 625                                 if (drm_dp_atomic_find_vcpi_slots(state,
 626                                                                   params[next_index].port->mgr,
 627                                                                   params[next_index].port,
 628                                                                   vars[next_index].pbn,
 629                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 630                                         return;
 631                         }
 632                 } else {
 633                         vars[next_index].pbn += initial_slack[next_index];
 634                         if (drm_dp_atomic_find_vcpi_slots(state,
 635                                                           params[next_index].port->mgr,
 636                                                           params[next_index].port,
 637                                                           vars[next_index].pbn,
 638                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 639                                 return;
 640                         if (!drm_dp_mst_atomic_check(state)) {
 641                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 642                         } else {
 643                                 vars[next_index].pbn -= initial_slack[next_index];
 644                                 if (drm_dp_atomic_find_vcpi_slots(state,
 645                                                                   params[next_index].port->mgr,
 646                                                                   params[next_index].port,
 647                                                                   vars[next_index].pbn,
 648                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 649                                         return;
 650                         }
 651                 }
 652
 653                 bpp_increased[next_index] = true;
 654                 remaining_to_increase--;
 655         }
 656 }
 657
 658 static void try_disable_dsc(struct drm_atomic_state *state,
 659                             struct dc_link *dc_link,
 660                             struct dsc_mst_fairness_params *params,
 661                             struct dsc_mst_fairness_vars *vars,
 662                             int count)
 663 {
 664         int i;
 665         bool tried[MAX_PIPES];
 666         int kbps_increase[MAX_PIPES];
 667         int max_kbps_increase;
 668         int next_index;
 669         int remaining_to_try = 0;
 670
 671         for (i = 0; i < count; i++) {
 672                 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
 673                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 674                         tried[i] = false;
 675                         remaining_to_try += 1;
 676                 } else {
 677                         kbps_increase[i] = 0;
 678                         tried[i] = true;
 679                 }
 680         }
 681
 682         while (remaining_to_try) {
 683                 next_index = -1;
 684                 max_kbps_increase = -1;
 685                 for (i = 0; i < count; i++) {
 686                         if (!tried[i]) {
 687                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 688                                         max_kbps_increase = kbps_increase[i];
 689                                         next_index = i;
 690                                 }
 691                         }
 692                 }
 693
 694                 if (next_index == -1)
 695                         break;
 696
 697                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 698                 if (drm_dp_atomic_find_vcpi_slots(state,
 699                                                   params[next_index].port->mgr,
 700                                                   params[next_index].port,
 701                                                   vars[next_index].pbn,
 702                                                   0) < 0)
 703                         return;
 704
 705                 if (!drm_dp_mst_atomic_check(state)) {
 706                         vars[next_index].dsc_enabled = false;
 707                         vars[next_index].bpp_x16 = 0;
 708                 } else {
 709                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 710                         if (drm_dp_atomic_find_vcpi_slots(state,
 711                                                           params[next_index].port->mgr,
 712                                                           params[next_index].port,
 713                                                           vars[next_index].pbn,
 714                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 715                                 return;
 716                 }
 717
 718                 tried[next_index] = true;
 719                 remaining_to_try--;
 720         }
 721 }
 722
 723 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 724                                              struct dc_state *dc_state,
 725                                              struct dc_link *dc_link)
 726 {
 727         int i;
 728         struct dc_stream_state *stream;
 729         struct dsc_mst_fairness_params params[MAX_PIPES];
 730         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 731         struct amdgpu_dm_connector *aconnector;
 732         int count = 0;
 733
 734         memset(params, 0, sizeof(params));
 735
 736         /* Set up params */
 737         for (i = 0; i < dc_state->stream_count; i++) {
 738                 struct dc_dsc_policy dsc_policy = {0};
 739
 740                 stream = dc_state->streams[i];
 741
 742                 if (stream->link != dc_link)
 743                         continue;
 744
 745                 stream->timing.flags.DSC = 0;
 746
 747                 params[count].timing = &stream->timing;
 748                 params[count].sink = stream->sink;
 749                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 750                 params[count].port = aconnector->port;
 751                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 752                 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 753                 if (!dc_dsc_compute_bandwidth_range(
 754                                 stream->sink->ctx->dc->res_pool->dscs[0],
 755                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 756                                 dsc_policy.min_target_bpp,
 757                                 dsc_policy.max_target_bpp,
 758                                 &stream->sink->dsc_caps.dsc_dec_caps,
 759                                 &stream->timing, &params[count].bw_range))
 760                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 761
 762                 count++;
 763         }
 764         /* Try no compression */
 765         for (i = 0; i < count; i++) {
 766                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 767                 vars[i].dsc_enabled = false;
 768                 vars[i].bpp_x16 = 0;
 769                 if (drm_dp_atomic_find_vcpi_slots(state,
 770                                                  params[i].port->mgr,
 771                                                  params[i].port,
 772                                                  vars[i].pbn,
 773                                                  0) < 0)
 774                         return false;
 775         }
 776         if (!drm_dp_mst_atomic_check(state)) {
 777                 set_dsc_configs_from_fairness_vars(params, vars, count);
 778                 return true;
 779         }
 780
 781         /* Try max compression */
 782         for (i = 0; i < count; i++) {
 783                 if (params[i].compression_possible) {
 784                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 785                         vars[i].dsc_enabled = true;
 786                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 787                         if (drm_dp_atomic_find_vcpi_slots(state,
 788                                                           params[i].port->mgr,
 789                                                           params[i].port,
 790                                                           vars[i].pbn,
 791                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 792                                 return false;
 793                 } else {
 794                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 795                         vars[i].dsc_enabled = false;
 796                         vars[i].bpp_x16 = 0;
 797                         if (drm_dp_atomic_find_vcpi_slots(state,
 798                                                           params[i].port->mgr,
 799                                                           params[i].port,
 800                                                           vars[i].pbn,
 801                                                           0) < 0)
 802                                 return false;
 803                 }
 804         }
 805         if (drm_dp_mst_atomic_check(state))
 806                 return false;
 807
 808         /* Optimize degree of compression */
 809         increase_dsc_bpp(state, dc_link, params, vars, count);
 810
 811         try_disable_dsc(state, dc_link, params, vars, count);
 812
 813         set_dsc_configs_from_fairness_vars(params, vars, count);
 814
 815         return true;
 816 }
 817
 818 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 819                                        struct dc_state *dc_state)
 820 {
 821         int i, j;
 822         struct dc_stream_state *stream;
 823         bool computed_streams[MAX_PIPES];
 824         struct amdgpu_dm_connector *aconnector;
 825
 826         for (i = 0; i < dc_state->stream_count; i++)
 827                 computed_streams[i] = false;
 828
 829         for (i = 0; i < dc_state->stream_count; i++) {
 830                 stream = dc_state->streams[i];
 831
 832                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 833                         continue;
 834
 835                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 836
 837                 if (!aconnector || !aconnector->dc_sink)
 838                         continue;
 839
 840                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 841                         continue;
 842
 843                 if (computed_streams[i])
 844                         continue;
 845
 846                 mutex_lock(&aconnector->mst_mgr.lock);
 847                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 848                         mutex_unlock(&aconnector->mst_mgr.lock);
 849                         return false;
 850                 }
 851                 mutex_unlock(&aconnector->mst_mgr.lock);
 852
 853                 for (j = 0; j < dc_state->stream_count; j++) {
 854                         if (dc_state->streams[j]->link == stream->link)
 855                                 computed_streams[j] = true;
 856                 }
 857         }
 858
 859         for (i = 0; i < dc_state->stream_count; i++) {
 860                 stream = dc_state->streams[i];
 861
 862                 if (stream->timing.flags.DSC == 1)
 863                         dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
 864         }
 865
 866         return true;
 867 }
 868
 869 #endif