drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_mst_types.h"
  33
  34 #include "dc.h"
  35 #include "dm_helpers.h"
  36
  37 #include "dc_link_ddc.h"
  38
  39 #include "i2caux_interface.h"
  40 #if defined(CONFIG_DEBUG_FS)
  41 #include "amdgpu_dm_debugfs.h"
  42 #endif
  43
  44
  45 #if defined(CONFIG_DRM_AMD_DC_DCN)
  46 #include "dc/dcn20/dcn20_resource.h"
  47 #endif
  48
  49 /* #define TRACE_DPCD */
  50
  51 #ifdef TRACE_DPCD
  52 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
  53
  54 static inline char *side_band_msg_type_to_str(uint32_t address)
  55 {
  56         static char str[10] = {0};
  57
  58         if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
  59                 strcpy(str, "DOWN_REQ");
  60         else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
  61                 strcpy(str, "UP_REP");
  62         else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
  63                 strcpy(str, "DOWN_REP");
  64         else
  65                 strcpy(str, "UP_REQ");
  66
  67         return str;
  68 }
  69
  70 static void log_dpcd(uint8_t type,
  71                      uint32_t address,
  72                      uint8_t *data,
  73                      uint32_t size,
  74                      bool res)
  75 {
  76         DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
  77                         (type == DP_AUX_NATIVE_READ) ||
  78                         (type == DP_AUX_I2C_READ) ?
  79                                         "Read" : "Write",
  80                         address,
  81                         SIDE_BAND_MSG(address) ?
  82                                         side_band_msg_type_to_str(address) : "Nop",
  83                         res ? "OK" : "Fail");
  84
  85         if (res) {
  86                 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
  87         }
  88 }
  89 #endif
  90
  91 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  92                                   struct drm_dp_aux_msg *msg)
  93 {
  94         ssize_t result = 0;
  95         struct aux_payload payload;
  96         enum aux_channel_operation_result operation_result;
  97
  98         if (WARN_ON(msg->size > 16))
  99                 return -E2BIG;
 100
 101         payload.address = msg->address;
 102         payload.data = msg->buffer;
 103         payload.length = msg->size;
 104         payload.reply = &msg->reply;
 105         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
 106         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
 107         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
 108         payload.defer_delay = 0;
 109
 110         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
 111                                       &operation_result);
 112
 113         if (payload.write)
 114                 result = msg->size;
 115
 116         if (result < 0)
 117                 switch (operation_result) {
 118                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
 119                         break;
 120                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
 121                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
 122                         result = -EIO;
 123                         break;
 124                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
 125                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
 126                         result = -EBUSY;
 127                         break;
 128                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
 129                         result = -ETIMEDOUT;
 130                         break;
 131                 }
 132
 133         return result;
 134 }
 135
 136 static void
 137 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 138 {
 139         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
 140         struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
 141
 142         kfree(amdgpu_dm_connector->edid);
 143         amdgpu_dm_connector->edid = NULL;
 144
 145         drm_encoder_cleanup(&amdgpu_encoder->base);
 146         kfree(amdgpu_encoder);
 147         drm_connector_cleanup(connector);
 148         drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
 149         kfree(amdgpu_dm_connector);
 150 }
 151
 152 static int
 153 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 154 {
 155         struct amdgpu_dm_connector *amdgpu_dm_connector =
 156                 to_amdgpu_dm_connector(connector);
 157         int r;
 158
 159         amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
 160         r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
 161         if (r)
 162                 return r;
 163
 164 #if defined(CONFIG_DEBUG_FS)
 165         connector_debugfs_init(amdgpu_dm_connector);
 166 #endif
 167
 168         return r;
 169 }
 170
 171 static void
 172 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 173 {
 174         struct amdgpu_dm_connector *amdgpu_dm_connector =
 175                 to_amdgpu_dm_connector(connector);
 176         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 177
 178         drm_dp_mst_connector_early_unregister(connector, port);
 179 }
 180
 181 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 182         .fill_modes = drm_helper_probe_single_connector_modes,
 183         .destroy = dm_dp_mst_connector_destroy,
 184         .reset = amdgpu_dm_connector_funcs_reset,
 185         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 186         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 187         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 188         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 189         .late_register = amdgpu_dm_mst_connector_late_register,
 190         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 191 };
 192
 193 #if defined(CONFIG_DRM_AMD_DC_DCN)
 194 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 195 {
 196         struct dc_sink *dc_sink = aconnector->dc_sink;
 197         struct drm_dp_mst_port *port = aconnector->port;
 198         u8 dsc_caps[16] = { 0 };
 199
 200         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 201
 202         if (!aconnector->dsc_aux)
 203                 return false;
 204
 205         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 206                 return false;
 207
 208         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 209                                    dsc_caps, NULL,
 210                                    &dc_sink->sink_dsc_caps.dsc_dec_caps))
 211                 return false;
 212
 213         return true;
 214 }
 215 #endif
 216
 217 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 218 {
 219         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 220         int ret = 0;
 221
 222         if (!aconnector)
 223                 return drm_add_edid_modes(connector, NULL);
 224
 225         if (!aconnector->edid) {
 226                 struct edid *edid;
 227                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 228
 229                 if (!edid) {
 230                         drm_connector_update_edid_property(
 231                                 &aconnector->base,
 232                                 NULL);
 233                         return ret;
 234                 }
 235
 236                 aconnector->edid = edid;
 237         }
 238
 239         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 240                 dc_sink_release(aconnector->dc_sink);
 241                 aconnector->dc_sink = NULL;
 242         }
 243
 244         if (!aconnector->dc_sink) {
 245                 struct dc_sink *dc_sink;
 246                 struct dc_sink_init_data init_params = {
 247                                 .link = aconnector->dc_link,
 248                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 249                 dc_sink = dc_link_add_remote_sink(
 250                         aconnector->dc_link,
 251                         (uint8_t *)aconnector->edid,
 252                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 253                         &init_params);
 254
 255                 dc_sink->priv = aconnector;
 256                 /* dc_link_add_remote_sink returns a new reference */
 257                 aconnector->dc_sink = dc_sink;
 258
 259                 if (aconnector->dc_sink) {
 260                         amdgpu_dm_update_freesync_caps(
 261                                         connector, aconnector->edid);
 262
 263 #if defined(CONFIG_DRM_AMD_DC_DCN)
 264                         if (!validate_dsc_caps_on_connector(aconnector))
 265                                 memset(&aconnector->dc_sink->sink_dsc_caps,
 266                                        0, sizeof(aconnector->dc_sink->sink_dsc_caps));
 267 #endif
 268                 }
 269         }
 270
 271         drm_connector_update_edid_property(
 272                                         &aconnector->base, aconnector->edid);
 273
 274         ret = drm_add_edid_modes(connector, aconnector->edid);
 275
 276         return ret;
 277 }
 278
 279 static struct drm_encoder *
 280 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 281                            struct drm_connector_state *connector_state)
 282 {
 283         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 284 }
 285
 286 static int
 287 dm_dp_mst_detect(struct drm_connector *connector,
 288                  struct drm_modeset_acquire_ctx *ctx, bool force)
 289 {
 290         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 291         struct amdgpu_dm_connector *master = aconnector->mst_port;
 292
 293         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 294                                       aconnector->port);
 295 }
 296
 297 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 298                                 struct drm_atomic_state *state)
 299 {
 300         struct drm_connector_state *new_conn_state =
 301                         drm_atomic_get_new_connector_state(state, connector);
 302         struct drm_connector_state *old_conn_state =
 303                         drm_atomic_get_old_connector_state(state, connector);
 304         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 305         struct drm_crtc_state *new_crtc_state;
 306         struct drm_dp_mst_topology_mgr *mst_mgr;
 307         struct drm_dp_mst_port *mst_port;
 308
 309         mst_port = aconnector->port;
 310         mst_mgr = &aconnector->mst_port->mst_mgr;
 311
 312         if (!old_conn_state->crtc)
 313                 return 0;
 314
 315         if (new_conn_state->crtc) {
 316                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 317                 if (!new_crtc_state ||
 318                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 319                     new_crtc_state->enable)
 320                         return 0;
 321                 }
 322
 323         return drm_dp_atomic_release_vcpi_slots(state,
 324                                                 mst_mgr,
 325                                                 mst_port);
 326 }
 327
 328 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 329         .get_modes = dm_dp_mst_get_modes,
 330         .mode_valid = amdgpu_dm_connector_mode_valid,
 331         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 332         .detect_ctx = dm_dp_mst_detect,
 333         .atomic_check = dm_dp_mst_atomic_check,
 334 };
 335
 336 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 337 {
 338         drm_encoder_cleanup(encoder);
 339         kfree(encoder);
 340 }
 341
 342 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 343         .destroy = amdgpu_dm_encoder_destroy,
 344 };
 345
 346 static struct amdgpu_encoder *
 347 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 348 {
 349         struct drm_device *dev = connector->base.dev;
 350         struct amdgpu_device *adev = dev->dev_private;
 351         struct amdgpu_encoder *amdgpu_encoder;
 352         struct drm_encoder *encoder;
 353
 354         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 355         if (!amdgpu_encoder)
 356                 return NULL;
 357
 358         encoder = &amdgpu_encoder->base;
 359         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 360
 361         drm_encoder_init(
 362                 dev,
 363                 &amdgpu_encoder->base,
 364                 &amdgpu_dm_encoder_funcs,
 365                 DRM_MODE_ENCODER_DPMST,
 366                 NULL);
 367
 368         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 369
 370         return amdgpu_encoder;
 371 }
 372
 373 static struct drm_connector *
 374 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 375                         struct drm_dp_mst_port *port,
 376                         const char *pathprop)
 377 {
 378         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 379         struct drm_device *dev = master->base.dev;
 380         struct amdgpu_device *adev = dev->dev_private;
 381         struct amdgpu_dm_connector *aconnector;
 382         struct drm_connector *connector;
 383
 384         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 385         if (!aconnector)
 386                 return NULL;
 387
 388         connector = &aconnector->base;
 389         aconnector->port = port;
 390         aconnector->mst_port = master;
 391
 392         if (drm_connector_init(
 393                 dev,
 394                 connector,
 395                 &dm_dp_mst_connector_funcs,
 396                 DRM_MODE_CONNECTOR_DisplayPort)) {
 397                 kfree(aconnector);
 398                 return NULL;
 399         }
 400         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 401
 402         amdgpu_dm_connector_init_helper(
 403                 &adev->dm,
 404                 aconnector,
 405                 DRM_MODE_CONNECTOR_DisplayPort,
 406                 master->dc_link,
 407                 master->connector_id);
 408
 409         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 410         drm_connector_attach_encoder(&aconnector->base,
 411                                      &aconnector->mst_encoder->base);
 412
 413         drm_object_attach_property(
 414                 &connector->base,
 415                 dev->mode_config.path_property,
 416                 0);
 417         drm_object_attach_property(
 418                 &connector->base,
 419                 dev->mode_config.tile_property,
 420                 0);
 421
 422         drm_connector_set_path_property(connector, pathprop);
 423
 424         /*
 425          * Initialize connector state before adding the connectror to drm and
 426          * framebuffer lists
 427          */
 428         amdgpu_dm_connector_funcs_reset(connector);
 429
 430         DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
 431                  aconnector, connector->base.id, aconnector->mst_port);
 432
 433         drm_dp_mst_get_port_malloc(port);
 434
 435         DRM_DEBUG_KMS(":%d\n", connector->base.id);
 436
 437         return connector;
 438 }
 439
 440 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 441                                         struct drm_connector *connector)
 442 {
 443         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 444
 445         DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
 446                  aconnector, connector->base.id, aconnector->mst_port);
 447
 448         if (aconnector->dc_sink) {
 449                 amdgpu_dm_update_freesync_caps(connector, NULL);
 450                 dc_link_remove_remote_sink(aconnector->dc_link,
 451                                            aconnector->dc_sink);
 452                 dc_sink_release(aconnector->dc_sink);
 453                 aconnector->dc_sink = NULL;
 454                 aconnector->dc_link->cur_link_settings.lane_count = 0;
 455         }
 456
 457         drm_connector_unregister(connector);
 458         drm_connector_put(connector);
 459 }
 460
 461 static void dm_dp_mst_register_connector(struct drm_connector *connector)
 462 {
 463         drm_connector_register(connector);
 464 }
 465
 466 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 467         .add_connector = dm_dp_add_mst_connector,
 468         .destroy_connector = dm_dp_destroy_mst_connector,
 469         .register_connector = dm_dp_mst_register_connector
 470 };
 471
 472 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 473                                        struct amdgpu_dm_connector *aconnector)
 474 {
 475         aconnector->dm_dp_aux.aux.name = "dmdc";
 476         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 477         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 478
 479         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 480         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 481                                       &aconnector->base);
 482
 483         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 484                 return;
 485
 486         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 487         drm_dp_mst_topology_mgr_init(
 488                 &aconnector->mst_mgr,
 489                 dm->adev->ddev,
 490                 &aconnector->dm_dp_aux.aux,
 491                 16,
 492                 4,
 493                 aconnector->connector_id);
 494 }
 495
 496 int dm_mst_get_pbn_divider(struct dc_link *link)
 497 {
 498         if (!link)
 499                 return 0;
 500
 501         return dc_link_bandwidth_kbps(link,
 502                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 503 }
 504
 505 #if defined(CONFIG_DRM_AMD_DC_DCN)
 506
 507 struct dsc_mst_fairness_params {
 508         struct dc_crtc_timing *timing;
 509         struct dc_sink *sink;
 510         struct dc_dsc_bw_range bw_range;
 511         bool compression_possible;
 512         struct drm_dp_mst_port *port;
 513 };
 514
 515 struct dsc_mst_fairness_vars {
 516         int pbn;
 517         bool dsc_enabled;
 518         int bpp_x16;
 519 };
 520
 521 static int kbps_to_peak_pbn(int kbps)
 522 {
 523         u64 peak_kbps = kbps;
 524
 525         peak_kbps *= 1006;
 526         peak_kbps = div_u64(peak_kbps, 1000);
 527         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 528 }
 529
 530 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 531                 struct dsc_mst_fairness_vars *vars,
 532                 int count)
 533 {
 534         int i;
 535
 536         for (i = 0; i < count; i++) {
 537                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 538                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 539                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 540                                         &params[i].sink->sink_dsc_caps.dsc_dec_caps,
 541                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 542                                         0,
 543                                         params[i].timing,
 544                                         &params[i].timing->dsc_cfg)) {
 545                         params[i].timing->flags.DSC = 1;
 546                         params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 547                 } else {
 548                         params[i].timing->flags.DSC = 0;
 549                 }
 550         }
 551 }
 552
 553 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 554 {
 555         struct dc_dsc_config dsc_config;
 556         u64 kbps;
 557
 558         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 559         dc_dsc_compute_config(
 560                         param.sink->ctx->dc->res_pool->dscs[0],
 561                         &param.sink->sink_dsc_caps.dsc_dec_caps,
 562                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 563                         (int) kbps, param.timing, &dsc_config);
 564
 565         return dsc_config.bits_per_pixel;
 566 }
 567
 568 static void increase_dsc_bpp(struct drm_atomic_state *state,
 569                              struct dc_link *dc_link,
 570                              struct dsc_mst_fairness_params *params,
 571                              struct dsc_mst_fairness_vars *vars,
 572                              int count)
 573 {
 574         int i;
 575         bool bpp_increased[MAX_PIPES];
 576         int initial_slack[MAX_PIPES];
 577         int min_initial_slack;
 578         int next_index;
 579         int remaining_to_increase = 0;
 580         int pbn_per_timeslot;
 581         int link_timeslots_used;
 582         int fair_pbn_alloc;
 583
 584         for (i = 0; i < count; i++) {
 585                 if (vars[i].dsc_enabled) {
 586                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 587                         bpp_increased[i] = false;
 588                         remaining_to_increase += 1;
 589                 } else {
 590                         initial_slack[i] = 0;
 591                         bpp_increased[i] = true;
 592                 }
 593         }
 594
 595         pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
 596                         dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
 597
 598         while (remaining_to_increase) {
 599                 next_index = -1;
 600                 min_initial_slack = -1;
 601                 for (i = 0; i < count; i++) {
 602                         if (!bpp_increased[i]) {
 603                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 604                                         min_initial_slack = initial_slack[i];
 605                                         next_index = i;
 606                                 }
 607                         }
 608                 }
 609
 610                 if (next_index == -1)
 611                         break;
 612
 613                 link_timeslots_used = 0;
 614
 615                 for (i = 0; i < count; i++)
 616                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 617
 618                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 619
 620                 if (initial_slack[next_index] > fair_pbn_alloc) {
 621                         vars[next_index].pbn += fair_pbn_alloc;
 622                         if (drm_dp_atomic_find_vcpi_slots(state,
 623                                                           params[next_index].port->mgr,
 624                                                           params[next_index].port,
 625                                                           vars[next_index].pbn,
 626                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 627                                 return;
 628                         if (!drm_dp_mst_atomic_check(state)) {
 629                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 630                         } else {
 631                                 vars[next_index].pbn -= fair_pbn_alloc;
 632                                 if (drm_dp_atomic_find_vcpi_slots(state,
 633                                                                   params[next_index].port->mgr,
 634                                                                   params[next_index].port,
 635                                                                   vars[next_index].pbn,
 636                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 637                                         return;
 638                         }
 639                 } else {
 640                         vars[next_index].pbn += initial_slack[next_index];
 641                         if (drm_dp_atomic_find_vcpi_slots(state,
 642                                                           params[next_index].port->mgr,
 643                                                           params[next_index].port,
 644                                                           vars[next_index].pbn,
 645                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 646                                 return;
 647                         if (!drm_dp_mst_atomic_check(state)) {
 648                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 649                         } else {
 650                                 vars[next_index].pbn -= initial_slack[next_index];
 651                                 if (drm_dp_atomic_find_vcpi_slots(state,
 652                                                                   params[next_index].port->mgr,
 653                                                                   params[next_index].port,
 654                                                                   vars[next_index].pbn,
 655                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 656                                         return;
 657                         }
 658                 }
 659
 660                 bpp_increased[next_index] = true;
 661                 remaining_to_increase--;
 662         }
 663 }
 664
 665 static void try_disable_dsc(struct drm_atomic_state *state,
 666                             struct dc_link *dc_link,
 667                             struct dsc_mst_fairness_params *params,
 668                             struct dsc_mst_fairness_vars *vars,
 669                             int count)
 670 {
 671         int i;
 672         bool tried[MAX_PIPES];
 673         int kbps_increase[MAX_PIPES];
 674         int max_kbps_increase;
 675         int next_index;
 676         int remaining_to_try = 0;
 677
 678         for (i = 0; i < count; i++) {
 679                 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
 680                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 681                         tried[i] = false;
 682                         remaining_to_try += 1;
 683                 } else {
 684                         kbps_increase[i] = 0;
 685                         tried[i] = true;
 686                 }
 687         }
 688
 689         while (remaining_to_try) {
 690                 next_index = -1;
 691                 max_kbps_increase = -1;
 692                 for (i = 0; i < count; i++) {
 693                         if (!tried[i]) {
 694                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 695                                         max_kbps_increase = kbps_increase[i];
 696                                         next_index = i;
 697                                 }
 698                         }
 699                 }
 700
 701                 if (next_index == -1)
 702                         break;
 703
 704                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 705                 if (drm_dp_atomic_find_vcpi_slots(state,
 706                                                   params[next_index].port->mgr,
 707                                                   params[next_index].port,
 708                                                   vars[next_index].pbn,
 709                                                   0) < 0)
 710                         return;
 711
 712                 if (!drm_dp_mst_atomic_check(state)) {
 713                         vars[next_index].dsc_enabled = false;
 714                         vars[next_index].bpp_x16 = 0;
 715                 } else {
 716                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 717                         if (drm_dp_atomic_find_vcpi_slots(state,
 718                                                           params[next_index].port->mgr,
 719                                                           params[next_index].port,
 720                                                           vars[next_index].pbn,
 721                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 722                                 return;
 723                 }
 724
 725                 tried[next_index] = true;
 726                 remaining_to_try--;
 727         }
 728 }
 729
 730 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 731                                              struct dc_state *dc_state,
 732                                              struct dc_link *dc_link)
 733 {
 734         int i;
 735         struct dc_stream_state *stream;
 736         struct dsc_mst_fairness_params params[MAX_PIPES];
 737         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 738         struct amdgpu_dm_connector *aconnector;
 739         int count = 0;
 740
 741         memset(params, 0, sizeof(params));
 742
 743         /* Set up params */
 744         for (i = 0; i < dc_state->stream_count; i++) {
 745                 struct dc_dsc_policy dsc_policy = {0};
 746
 747                 stream = dc_state->streams[i];
 748
 749                 if (stream->link != dc_link)
 750                         continue;
 751
 752                 stream->timing.flags.DSC = 0;
 753
 754                 params[count].timing = &stream->timing;
 755                 params[count].sink = stream->sink;
 756                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 757                 params[count].port = aconnector->port;
 758                 params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
 759                 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 760                 if (!dc_dsc_compute_bandwidth_range(
 761                                 stream->sink->ctx->dc->res_pool->dscs[0],
 762                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 763                                 dsc_policy.min_target_bpp,
 764                                 dsc_policy.max_target_bpp,
 765                                 &stream->sink->sink_dsc_caps.dsc_dec_caps,
 766                                 &stream->timing, &params[count].bw_range))
 767                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 768
 769                 count++;
 770         }
 771         /* Try no compression */
 772         for (i = 0; i < count; i++) {
 773                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 774                 vars[i].dsc_enabled = false;
 775                 vars[i].bpp_x16 = 0;
 776                 if (drm_dp_atomic_find_vcpi_slots(state,
 777                                                  params[i].port->mgr,
 778                                                  params[i].port,
 779                                                  vars[i].pbn,
 780                                                  0) < 0)
 781                         return false;
 782         }
 783         if (!drm_dp_mst_atomic_check(state)) {
 784                 set_dsc_configs_from_fairness_vars(params, vars, count);
 785                 return true;
 786         }
 787
 788         /* Try max compression */
 789         for (i = 0; i < count; i++) {
 790                 if (params[i].compression_possible) {
 791                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 792                         vars[i].dsc_enabled = true;
 793                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 794                         if (drm_dp_atomic_find_vcpi_slots(state,
 795                                                           params[i].port->mgr,
 796                                                           params[i].port,
 797                                                           vars[i].pbn,
 798                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 799                                 return false;
 800                 } else {
 801                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 802                         vars[i].dsc_enabled = false;
 803                         vars[i].bpp_x16 = 0;
 804                         if (drm_dp_atomic_find_vcpi_slots(state,
 805                                                           params[i].port->mgr,
 806                                                           params[i].port,
 807                                                           vars[i].pbn,
 808                                                           0) < 0)
 809                                 return false;
 810                 }
 811         }
 812         if (drm_dp_mst_atomic_check(state))
 813                 return false;
 814
 815         /* Optimize degree of compression */
 816         increase_dsc_bpp(state, dc_link, params, vars, count);
 817
 818         try_disable_dsc(state, dc_link, params, vars, count);
 819
 820         set_dsc_configs_from_fairness_vars(params, vars, count);
 821
 822         return true;
 823 }
 824
 825 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 826                                        struct dc_state *dc_state)
 827 {
 828         int i, j;
 829         struct dc_stream_state *stream;
 830         bool computed_streams[MAX_PIPES];
 831         struct amdgpu_dm_connector *aconnector;
 832
 833         for (i = 0; i < dc_state->stream_count; i++)
 834                 computed_streams[i] = false;
 835
 836         for (i = 0; i < dc_state->stream_count; i++) {
 837                 stream = dc_state->streams[i];
 838
 839                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 840                         continue;
 841
 842                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 843
 844                 if (!aconnector || !aconnector->dc_sink)
 845                         continue;
 846
 847                 if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
 848                         continue;
 849
 850                 if (computed_streams[i])
 851                         continue;
 852
 853                 mutex_lock(&aconnector->mst_mgr.lock);
 854                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 855                         mutex_unlock(&aconnector->mst_mgr.lock);
 856                         return false;
 857                 }
 858                 mutex_unlock(&aconnector->mst_mgr.lock);
 859
 860                 for (j = 0; j < dc_state->stream_count; j++) {
 861                         if (dc_state->streams[j]->link == stream->link)
 862                                 computed_streams[j] = true;
 863                 }
 864         }
 865
 866         for (i = 0; i < dc_state->stream_count; i++) {
 867                 stream = dc_state->streams[i];
 868
 869                 if (stream->timing.flags.DSC == 1)
 870                         dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
 871         }
 872
 873         return true;
 874 }
 875
 876 #endif