drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_fixed.h>
  35
  36 #include "dm_services.h"
  37 #include "amdgpu.h"
  38 #include "dc.h"
  39 #include "amdgpu_dm.h"
  40 #include "amdgpu_dm_irq.h"
  41 #include "amdgpu_dm_mst_types.h"
  42 #include "dpcd_defs.h"
  43 #include "dc/inc/core_types.h"
  44
  45 #include "dm_helpers.h"
  46 #include "ddc_service_types.h"
  47
  48 static u32 edid_extract_panel_id(struct edid *edid)
  49 {
  50         return (u32)edid->mfg_id[0] << 24   |
  51                (u32)edid->mfg_id[1] << 16   |
  52                (u32)EDID_PRODUCT_ID(edid);
  53 }
  54
  55 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
  56 {
  57         uint32_t panel_id = edid_extract_panel_id(edid);
  58
  59         switch (panel_id) {
  60         /* Workaround for some monitors which does not work well with FAMS */
  61         case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  62         case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  63         case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  64                 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
  65                 edid_caps->panel_patch.disable_fams = true;
  66                 break;
  67         default:
  68                 return;
  69         }
  70 }
  71
  72 /**
  73  * dm_helpers_parse_edid_caps() - Parse edid caps
  74  *
  75  * @link: current detected link
  76  * @edid:       [in] pointer to edid
  77  * @edid_caps:  [in] pointer to edid caps
  78  *
  79  * Return: void
  80  */
  81 enum dc_edid_status dm_helpers_parse_edid_caps(
  82                 struct dc_link *link,
  83                 const struct dc_edid *edid,
  84                 struct dc_edid_caps *edid_caps)
  85 {
  86         struct amdgpu_dm_connector *aconnector = link->priv;
  87         struct drm_connector *connector = &aconnector->base;
  88         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  89         struct cea_sad *sads;
  90         int sad_count = -1;
  91         int sadb_count = -1;
  92         int i = 0;
  93         uint8_t *sadb = NULL;
  94
  95         enum dc_edid_status result = EDID_OK;
  96
  97         if (!edid_caps || !edid)
  98                 return EDID_BAD_INPUT;
  99
 100         if (!drm_edid_is_valid(edid_buf))
 101                 result = EDID_BAD_CHECKSUM;
 102
 103         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 104                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
 105         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 106                                         ((uint16_t) edid_buf->prod_code[1])<<8;
 107         edid_caps->serial_number = edid_buf->serial;
 108         edid_caps->manufacture_week = edid_buf->mfg_week;
 109         edid_caps->manufacture_year = edid_buf->mfg_year;
 110
 111         drm_edid_get_monitor_name(edid_buf,
 112                                   edid_caps->display_name,
 113                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 114
 115         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 116
 117         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 118         if (sad_count <= 0)
 119                 return result;
 120
 121         edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 122         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 123                 struct cea_sad *sad = &sads[i];
 124
 125                 edid_caps->audio_modes[i].format_code = sad->format;
 126                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 127                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 128                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 129         }
 130
 131         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 132
 133         if (sadb_count < 0) {
 134                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 135                 sadb_count = 0;
 136         }
 137
 138         if (sadb_count)
 139                 edid_caps->speaker_flags = sadb[0];
 140         else
 141                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 142
 143         apply_edid_quirks(edid_buf, edid_caps);
 144
 145         kfree(sads);
 146         kfree(sadb);
 147
 148         return result;
 149 }
 150
 151 static void
 152 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 153                                    bool enable,
 154                                    struct drm_dp_mst_atomic_payload *target_payload,
 155                                    struct dc_dp_mst_stream_allocation_table *table)
 156 {
 157         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 158         struct dc_dp_mst_stream_allocation *sa;
 159         struct link_mst_stream_allocation_table copy_of_link_table =
 160                                                                                 link->mst_stream_alloc_table;
 161
 162         int i;
 163         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 164         struct link_mst_stream_allocation *dc_alloc;
 165
 166         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 167         if (enable) {
 168                 dc_alloc =
 169                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 170                 dc_alloc->vcp_id = target_payload->vcpi;
 171                 dc_alloc->slot_count = target_payload->time_slots;
 172         } else {
 173                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 174                         dc_alloc =
 175                         &copy_of_link_table.stream_allocations[i];
 176
 177                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 178                                 dc_alloc->vcp_id = 0;
 179                                 dc_alloc->slot_count = 0;
 180                                 break;
 181                         }
 182                 }
 183                 ASSERT(i != copy_of_link_table.stream_count);
 184         }
 185
 186         /* Fill payload info*/
 187         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 188                 dc_alloc =
 189                         &copy_of_link_table.stream_allocations[i];
 190                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 191                         sa = &new_table.stream_allocations[new_table.stream_count];
 192                         sa->slot_count = dc_alloc->slot_count;
 193                         sa->vcp_id = dc_alloc->vcp_id;
 194                         new_table.stream_count++;
 195                 }
 196         }
 197
 198         /* Overwrite the old table */
 199         *table = new_table;
 200 }
 201
 202 void dm_helpers_dp_update_branch_info(
 203         struct dc_context *ctx,
 204         const struct dc_link *link)
 205 {}
 206
 207 static void dm_helpers_construct_old_payload(
 208                         struct drm_dp_mst_topology_mgr *mgr,
 209                         struct drm_dp_mst_topology_state *mst_state,
 210                         struct drm_dp_mst_atomic_payload *new_payload,
 211                         struct drm_dp_mst_atomic_payload *old_payload)
 212 {
 213         struct drm_dp_mst_atomic_payload *pos;
 214         int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);
 215         u8 next_payload_vc_start = mgr->next_start_slot;
 216         u8 payload_vc_start = new_payload->vc_start_slot;
 217         u8 allocated_time_slots;
 218
 219         *old_payload = *new_payload;
 220
 221         /* Set correct time_slots/PBN of old payload.
 222          * other fields (delete & dsc_enabled) in
 223          * struct drm_dp_mst_atomic_payload are don't care fields
 224          * while calling drm_dp_remove_payload_part2()
 225          */
 226         list_for_each_entry(pos, &mst_state->payloads, next) {
 227                 if (pos != new_payload &&
 228                     pos->vc_start_slot > payload_vc_start &&
 229                     pos->vc_start_slot < next_payload_vc_start)
 230                         next_payload_vc_start = pos->vc_start_slot;
 231         }
 232
 233         allocated_time_slots = next_payload_vc_start - payload_vc_start;
 234
 235         old_payload->time_slots = allocated_time_slots;
 236         old_payload->pbn = allocated_time_slots * pbn_per_slot;
 237 }
 238
 239 /*
 240  * Writes payload allocation table in immediate downstream device.
 241  */
 242 bool dm_helpers_dp_mst_write_payload_allocation_table(
 243                 struct dc_context *ctx,
 244                 const struct dc_stream_state *stream,
 245                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 246                 bool enable)
 247 {
 248         struct amdgpu_dm_connector *aconnector;
 249         struct drm_dp_mst_topology_state *mst_state;
 250         struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 251         struct drm_dp_mst_topology_mgr *mst_mgr;
 252
 253         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 254         /* Accessing the connector state is required for vcpi_slots allocation
 255          * and directly relies on behaviour in commit check
 256          * that blocks before commit guaranteeing that the state
 257          * is not gonna be swapped while still in use in commit tail
 258          */
 259
 260         if (!aconnector || !aconnector->mst_root)
 261                 return false;
 262
 263         mst_mgr = &aconnector->mst_root->mst_mgr;
 264         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 265         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 266
 267         if (enable) {
 268                 target_payload = new_payload;
 269
 270                 /* It's OK for this to fail */
 271                 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 272         } else {
 273                 /* construct old payload by VCPI*/
 274                 dm_helpers_construct_old_payload(mst_mgr, mst_state,
 275                                                  new_payload, &old_payload);
 276                 target_payload = &old_payload;
 277
 278                 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
 279         }
 280
 281         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 282          * AUX message. The sequence is slot 1-63 allocated sequence for each
 283          * stream. AMD ASIC stream slot allocation should follow the same
 284          * sequence. copy DRM MST allocation to dc
 285          */
 286         fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 287
 288         return true;
 289 }
 290
 291 /*
 292  * poll pending down reply
 293  */
 294 void dm_helpers_dp_mst_poll_pending_down_reply(
 295         struct dc_context *ctx,
 296         const struct dc_link *link)
 297 {}
 298
 299 /*
 300  * Clear payload allocation table before enable MST DP link.
 301  */
 302 void dm_helpers_dp_mst_clear_payload_allocation_table(
 303         struct dc_context *ctx,
 304         const struct dc_link *link)
 305 {}
 306
 307 /*
 308  * Polls for ACT (allocation change trigger) handled and sends
 309  * ALLOCATE_PAYLOAD message.
 310  */
 311 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 312                 struct dc_context *ctx,
 313                 const struct dc_stream_state *stream)
 314 {
 315         struct amdgpu_dm_connector *aconnector;
 316         struct drm_dp_mst_topology_mgr *mst_mgr;
 317         int ret;
 318
 319         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 320
 321         if (!aconnector || !aconnector->mst_root)
 322                 return ACT_FAILED;
 323
 324         mst_mgr = &aconnector->mst_root->mst_mgr;
 325
 326         if (!mst_mgr->mst_state)
 327                 return ACT_FAILED;
 328
 329         ret = drm_dp_check_act_status(mst_mgr);
 330
 331         if (ret)
 332                 return ACT_FAILED;
 333
 334         return ACT_SUCCESS;
 335 }
 336
 337 bool dm_helpers_dp_mst_send_payload_allocation(
 338                 struct dc_context *ctx,
 339                 const struct dc_stream_state *stream,
 340                 bool enable)
 341 {
 342         struct amdgpu_dm_connector *aconnector;
 343         struct drm_dp_mst_topology_state *mst_state;
 344         struct drm_dp_mst_topology_mgr *mst_mgr;
 345         struct drm_dp_mst_atomic_payload *new_payload, old_payload;
 346         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 347         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 348         int ret = 0;
 349
 350         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 351
 352         if (!aconnector || !aconnector->mst_root)
 353                 return false;
 354
 355         mst_mgr = &aconnector->mst_root->mst_mgr;
 356         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 357
 358         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 359
 360         if (!enable) {
 361                 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 362                 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 363         }
 364
 365         if (enable) {
 366                 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload);
 367         } else {
 368                 dm_helpers_construct_old_payload(mst_mgr, mst_state,
 369                                                  new_payload, &old_payload);
 370                 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);
 371         }
 372
 373         if (ret) {
 374                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 375                         set_flag, false);
 376         } else {
 377                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 378                         set_flag, true);
 379                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 380                         clr_flag, false);
 381         }
 382
 383         return true;
 384 }
 385
 386 void dm_dtn_log_begin(struct dc_context *ctx,
 387         struct dc_log_buffer_ctx *log_ctx)
 388 {
 389         static const char msg[] = "[dtn begin]\n";
 390
 391         if (!log_ctx) {
 392                 pr_info("%s", msg);
 393                 return;
 394         }
 395
 396         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 397 }
 398
 399 __printf(3, 4)
 400 void dm_dtn_log_append_v(struct dc_context *ctx,
 401         struct dc_log_buffer_ctx *log_ctx,
 402         const char *msg, ...)
 403 {
 404         va_list args;
 405         size_t total;
 406         int n;
 407
 408         if (!log_ctx) {
 409                 /* No context, redirect to dmesg. */
 410                 struct va_format vaf;
 411
 412                 vaf.fmt = msg;
 413                 vaf.va = &args;
 414
 415                 va_start(args, msg);
 416                 pr_info("%pV", &vaf);
 417                 va_end(args);
 418
 419                 return;
 420         }
 421
 422         /* Measure the output. */
 423         va_start(args, msg);
 424         n = vsnprintf(NULL, 0, msg, args);
 425         va_end(args);
 426
 427         if (n <= 0)
 428                 return;
 429
 430         /* Reallocate the string buffer as needed. */
 431         total = log_ctx->pos + n + 1;
 432
 433         if (total > log_ctx->size) {
 434                 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 435
 436                 if (buf) {
 437                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 438                         kfree(log_ctx->buf);
 439
 440                         log_ctx->buf = buf;
 441                         log_ctx->size = total;
 442                 }
 443         }
 444
 445         if (!log_ctx->buf)
 446                 return;
 447
 448         /* Write the formatted string to the log buffer. */
 449         va_start(args, msg);
 450         n = vscnprintf(
 451                 log_ctx->buf + log_ctx->pos,
 452                 log_ctx->size - log_ctx->pos,
 453                 msg,
 454                 args);
 455         va_end(args);
 456
 457         if (n > 0)
 458                 log_ctx->pos += n;
 459 }
 460
 461 void dm_dtn_log_end(struct dc_context *ctx,
 462         struct dc_log_buffer_ctx *log_ctx)
 463 {
 464         static const char msg[] = "[dtn end]\n";
 465
 466         if (!log_ctx) {
 467                 pr_info("%s", msg);
 468                 return;
 469         }
 470
 471         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 472 }
 473
 474 bool dm_helpers_dp_mst_start_top_mgr(
 475                 struct dc_context *ctx,
 476                 const struct dc_link *link,
 477                 bool boot)
 478 {
 479         struct amdgpu_dm_connector *aconnector = link->priv;
 480         int ret;
 481
 482         if (!aconnector) {
 483                 DRM_ERROR("Failed to find connector for link!");
 484                 return false;
 485         }
 486
 487         if (boot) {
 488                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 489                                         aconnector, aconnector->base.base.id);
 490                 return true;
 491         }
 492
 493         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 494                         aconnector, aconnector->base.base.id);
 495
 496         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 497         if (ret < 0) {
 498                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 499                 return false;
 500         }
 501
 502         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 503                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 504
 505         return true;
 506 }
 507
 508 bool dm_helpers_dp_mst_stop_top_mgr(
 509                 struct dc_context *ctx,
 510                 struct dc_link *link)
 511 {
 512         struct amdgpu_dm_connector *aconnector = link->priv;
 513
 514         if (!aconnector) {
 515                 DRM_ERROR("Failed to find connector for link!");
 516                 return false;
 517         }
 518
 519         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 520                         aconnector, aconnector->base.base.id);
 521
 522         if (aconnector->mst_mgr.mst_state == true) {
 523                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 524                 link->cur_link_settings.lane_count = 0;
 525         }
 526
 527         return false;
 528 }
 529
 530 bool dm_helpers_dp_read_dpcd(
 531                 struct dc_context *ctx,
 532                 const struct dc_link *link,
 533                 uint32_t address,
 534                 uint8_t *data,
 535                 uint32_t size)
 536 {
 537
 538         struct amdgpu_dm_connector *aconnector = link->priv;
 539
 540         if (!aconnector)
 541                 return false;
 542
 543         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 544                                 size) == size;
 545 }
 546
 547 bool dm_helpers_dp_write_dpcd(
 548                 struct dc_context *ctx,
 549                 const struct dc_link *link,
 550                 uint32_t address,
 551                 const uint8_t *data,
 552                 uint32_t size)
 553 {
 554         struct amdgpu_dm_connector *aconnector = link->priv;
 555
 556         if (!aconnector) {
 557                 DRM_ERROR("Failed to find connector for link!");
 558                 return false;
 559         }
 560
 561         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 562                         address, (uint8_t *)data, size) > 0;
 563 }
 564
 565 bool dm_helpers_submit_i2c(
 566                 struct dc_context *ctx,
 567                 const struct dc_link *link,
 568                 struct i2c_command *cmd)
 569 {
 570         struct amdgpu_dm_connector *aconnector = link->priv;
 571         struct i2c_msg *msgs;
 572         int i = 0;
 573         int num = cmd->number_of_payloads;
 574         bool result;
 575
 576         if (!aconnector) {
 577                 DRM_ERROR("Failed to find connector for link!");
 578                 return false;
 579         }
 580
 581         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 582
 583         if (!msgs)
 584                 return false;
 585
 586         for (i = 0; i < num; i++) {
 587                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 588                 msgs[i].addr = cmd->payloads[i].address;
 589                 msgs[i].len = cmd->payloads[i].length;
 590                 msgs[i].buf = cmd->payloads[i].data;
 591         }
 592
 593         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 594
 595         kfree(msgs);
 596
 597         return result;
 598 }
 599
 600 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 601                 bool is_write_cmd,
 602                 unsigned char cmd,
 603                 unsigned int length,
 604                 unsigned int offset,
 605                 unsigned char *data)
 606 {
 607         bool success = false;
 608         unsigned char rc_data[16] = {0};
 609         unsigned char rc_offset[4] = {0};
 610         unsigned char rc_length[2] = {0};
 611         unsigned char rc_cmd = 0;
 612         unsigned char rc_result = 0xFF;
 613         unsigned char i = 0;
 614         int ret;
 615
 616         if (is_write_cmd) {
 617                 // write rc data
 618                 memmove(rc_data, data, length);
 619                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 620         }
 621
 622         // write rc offset
 623         rc_offset[0] = (unsigned char) offset & 0xFF;
 624         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 625         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 626         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 627         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 628
 629         // write rc length
 630         rc_length[0] = (unsigned char) length & 0xFF;
 631         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 632         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 633
 634         // write rc cmd
 635         rc_cmd = cmd | 0x80;
 636         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 637
 638         if (ret < 0) {
 639                 DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 640                 return false;
 641         }
 642
 643         // poll until active is 0
 644         for (i = 0; i < 10; i++) {
 645                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 646                 if (rc_cmd == cmd)
 647                         // active is 0
 648                         break;
 649                 msleep(10);
 650         }
 651
 652         // read rc result
 653         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 654         success = (rc_result == 0);
 655
 656         if (success && !is_write_cmd) {
 657                 // read rc data
 658                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 659         }
 660
 661         drm_dbg_dp(aux->drm_dev, "success = %d\n", success);
 662
 663         return success;
 664 }
 665
 666 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 667 {
 668         unsigned char data[16] = {0};
 669
 670         drm_dbg_dp(aux->drm_dev, "Start\n");
 671
 672         // Step 2
 673         data[0] = 'P';
 674         data[1] = 'R';
 675         data[2] = 'I';
 676         data[3] = 'U';
 677         data[4] = 'S';
 678
 679         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 680                 return;
 681
 682         // Step 3 and 4
 683         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 684                 return;
 685
 686         data[0] &= (~(1 << 1)); // set bit 1 to 0
 687         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 688                 return;
 689
 690         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 691                 return;
 692
 693         data[0] &= (~(1 << 1)); // set bit 1 to 0
 694         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 695                 return;
 696
 697         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 698                 return;
 699
 700         data[0] &= (~(1 << 1)); // set bit 1 to 0
 701         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 702                 return;
 703
 704         // Step 3 and 5
 705         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 706                 return;
 707
 708         data[0] |= (1 << 1); // set bit 1 to 1
 709         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 710                 return;
 711
 712         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 713                 return;
 714
 715         data[0] |= (1 << 1); // set bit 1 to 1
 716
 717         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 718                 return;
 719
 720         data[0] |= (1 << 1); // set bit 1 to 1
 721         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 722                 return;
 723
 724         // Step 6
 725         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 726                 return;
 727
 728         drm_dbg_dp(aux->drm_dev, "Done\n");
 729 }
 730
 731 /* MST Dock */
 732 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 733
 734 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 735                 struct drm_dp_aux *aux,
 736                 const struct dc_stream_state *stream,
 737                 bool enable)
 738 {
 739         uint8_t ret = 0;
 740
 741         drm_dbg_dp(aux->drm_dev,
 742                    "Configure DSC to non-virtual dpcd synaptics\n");
 743
 744         if (enable) {
 745                 /* When DSC is enabled on previous boot and reboot with the hub,
 746                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 747                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 748                  */
 749                 if (!stream->link->link_status.link_active &&
 750                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 751                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 752                         apply_synaptics_fifo_reset_wa(aux);
 753
 754                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 755                 DRM_INFO("Send DSC enable to synaptics\n");
 756
 757         } else {
 758                 /* Synaptics hub not support virtual dpcd,
 759                  * external monitor occur garbage while disable DSC,
 760                  * Disable DSC only when entire link status turn to false,
 761                  */
 762                 if (!stream->link->link_status.link_active) {
 763                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 764                         DRM_INFO("Send DSC disable to synaptics\n");
 765                 }
 766         }
 767
 768         return ret;
 769 }
 770
 771 bool dm_helpers_dp_write_dsc_enable(
 772                 struct dc_context *ctx,
 773                 const struct dc_stream_state *stream,
 774                 bool enable)
 775 {
 776         static const uint8_t DSC_DISABLE;
 777         static const uint8_t DSC_DECODING = 0x01;
 778         static const uint8_t DSC_PASSTHROUGH = 0x02;
 779
 780         struct amdgpu_dm_connector *aconnector =
 781                 (struct amdgpu_dm_connector *)stream->dm_stream_context;
 782         struct drm_device *dev = aconnector->base.dev;
 783         struct drm_dp_mst_port *port;
 784         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 785         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 786         uint8_t ret = 0;
 787
 788         if (!stream)
 789                 return false;
 790
 791         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 792                 if (!aconnector->dsc_aux)
 793                         return false;
 794
 795                 // apply w/a to synaptics
 796                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 797                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 798                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 799                                 aconnector->dsc_aux, stream, enable_dsc);
 800
 801                 port = aconnector->mst_output_port;
 802
 803                 if (enable) {
 804                         if (port->passthrough_aux) {
 805                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 806                                                         DP_DSC_ENABLE,
 807                                                         &enable_passthrough, 1);
 808                                 drm_dbg_dp(dev,
 809                                            "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 810                                            ret);
 811                         }
 812
 813                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 814                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 815                         drm_dbg_dp(dev,
 816                                    "Sent DSC decoding enable to %s port, ret = %u\n",
 817                                    (port->passthrough_aux) ? "remote RX" :
 818                                    "virtual dpcd",
 819                                    ret);
 820                 } else {
 821                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 822                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 823                         drm_dbg_dp(dev,
 824                                    "Sent DSC decoding disable to %s port, ret = %u\n",
 825                                    (port->passthrough_aux) ? "remote RX" :
 826                                    "virtual dpcd",
 827                                    ret);
 828
 829                         if (port->passthrough_aux) {
 830                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 831                                                         DP_DSC_ENABLE,
 832                                                         &enable_passthrough, 1);
 833                                 drm_dbg_dp(dev,
 834                                            "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 835                                            ret);
 836                         }
 837                 }
 838         }
 839
 840         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 841                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 842                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 843                         drm_dbg_dp(dev,
 844                                    "Send DSC %s to SST RX\n",
 845                                    enable_dsc ? "enable" : "disable");
 846                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 847                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 848                         drm_dbg_dp(dev,
 849                                    "Send DSC %s to DP-HDMI PCON\n",
 850                                    enable_dsc ? "enable" : "disable");
 851                 }
 852         }
 853
 854         return ret;
 855 }
 856
 857 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 858 {
 859         bool dp_sink_present;
 860         struct amdgpu_dm_connector *aconnector = link->priv;
 861
 862         if (!aconnector) {
 863                 BUG_ON("Failed to find connector for link!");
 864                 return true;
 865         }
 866
 867         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 868         dp_sink_present = dc_link_is_dp_sink_present(link);
 869         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 870         return dp_sink_present;
 871 }
 872
 873 enum dc_edid_status dm_helpers_read_local_edid(
 874                 struct dc_context *ctx,
 875                 struct dc_link *link,
 876                 struct dc_sink *sink)
 877 {
 878         struct amdgpu_dm_connector *aconnector = link->priv;
 879         struct drm_connector *connector = &aconnector->base;
 880         struct i2c_adapter *ddc;
 881         int retry = 3;
 882         enum dc_edid_status edid_status;
 883         struct edid *edid;
 884
 885         if (link->aux_mode)
 886                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 887         else
 888                 ddc = &aconnector->i2c->base;
 889
 890         /* some dongles read edid incorrectly the first time,
 891          * do check sum and retry to make sure read correct edid.
 892          */
 893         do {
 894
 895                 edid = drm_get_edid(&aconnector->base, ddc);
 896
 897                 /* DP Compliance Test 4.2.2.6 */
 898                 if (link->aux_mode && connector->edid_corrupt)
 899                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 900
 901                 if (!edid && connector->edid_corrupt) {
 902                         connector->edid_corrupt = false;
 903                         return EDID_BAD_CHECKSUM;
 904                 }
 905
 906                 if (!edid)
 907                         return EDID_NO_RESPONSE;
 908
 909                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 910                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 911
 912                 /* We don't need the original edid anymore */
 913                 kfree(edid);
 914
 915                 edid_status = dm_helpers_parse_edid_caps(
 916                                                 link,
 917                                                 &sink->dc_edid,
 918                                                 &sink->edid_caps);
 919
 920         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 921
 922         if (edid_status != EDID_OK)
 923                 DRM_ERROR("EDID err: %d, on connector: %s",
 924                                 edid_status,
 925                                 aconnector->base.name);
 926         if (link->aux_mode) {
 927                 union test_request test_request = {0};
 928                 union test_response test_response = {0};
 929
 930                 dm_helpers_dp_read_dpcd(ctx,
 931                                         link,
 932                                         DP_TEST_REQUEST,
 933                                         &test_request.raw,
 934                                         sizeof(union test_request));
 935
 936                 if (!test_request.bits.EDID_READ)
 937                         return edid_status;
 938
 939                 test_response.bits.EDID_CHECKSUM_WRITE = 1;
 940
 941                 dm_helpers_dp_write_dpcd(ctx,
 942                                         link,
 943                                         DP_TEST_EDID_CHECKSUM,
 944                                         &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
 945                                         1);
 946
 947                 dm_helpers_dp_write_dpcd(ctx,
 948                                         link,
 949                                         DP_TEST_RESPONSE,
 950                                         &test_response.raw,
 951                                         sizeof(test_response));
 952
 953         }
 954
 955         return edid_status;
 956 }
 957 int dm_helper_dmub_aux_transfer_sync(
 958                 struct dc_context *ctx,
 959                 const struct dc_link *link,
 960                 struct aux_payload *payload,
 961                 enum aux_return_code_type *operation_result)
 962 {
 963         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 964                         operation_result);
 965 }
 966
 967 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 968                 const struct dc_link *link,
 969                 struct set_config_cmd_payload *payload,
 970                 enum set_config_status *operation_result)
 971 {
 972         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
 973                         operation_result);
 974 }
 975
 976 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 977 {
 978         /* TODO: something */
 979 }
 980
 981 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
 982 {
 983         // TODO:
 984         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 985 }
 986
 987 void dm_helpers_init_panel_settings(
 988         struct dc_context *ctx,
 989         struct dc_panel_config *panel_config,
 990         struct dc_sink *sink)
 991 {
 992         // Extra Panel Power Sequence
 993         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 994         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
 995         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
 996         panel_config->pps.extra_post_t7_ms = 0;
 997         panel_config->pps.extra_pre_t11_ms = 0;
 998         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
 999         panel_config->pps.extra_post_OUI_ms = 0;
1000         // Feature DSC
1001         panel_config->dsc.disable_dsc_edp = false;
1002         panel_config->dsc.force_dsc_edp_policy = 0;
1003 }
1004
1005 void dm_helpers_override_panel_settings(
1006         struct dc_context *ctx,
1007         struct dc_panel_config *panel_config)
1008 {
1009         // Feature DSC
1010         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1011                 panel_config->dsc.disable_dsc_edp = true;
1012 }
1013
1014 void *dm_helpers_allocate_gpu_mem(
1015                 struct dc_context *ctx,
1016                 enum dc_gpu_mem_alloc_type type,
1017                 size_t size,
1018                 long long *addr)
1019 {
1020         struct amdgpu_device *adev = ctx->driver_context;
1021         struct dal_allocation *da;
1022         u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1023                 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1024         int ret;
1025
1026         da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1027         if (!da)
1028                 return NULL;
1029
1030         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1031                                       domain, &da->bo,
1032                                       &da->gpu_addr, &da->cpu_ptr);
1033
1034         *addr = da->gpu_addr;
1035
1036         if (ret) {
1037                 kfree(da);
1038                 return NULL;
1039         }
1040
1041         /* add da to list in dm */
1042         list_add(&da->list, &adev->dm.da_list);
1043
1044         return da->cpu_ptr;
1045 }
1046
1047 void dm_helpers_free_gpu_mem(
1048                 struct dc_context *ctx,
1049                 enum dc_gpu_mem_alloc_type type,
1050                 void *pvMem)
1051 {
1052         struct amdgpu_device *adev = ctx->driver_context;
1053         struct dal_allocation *da;
1054
1055         /* walk the da list in DM */
1056         list_for_each_entry(da, &adev->dm.da_list, list) {
1057                 if (pvMem == da->cpu_ptr) {
1058                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1059                         list_del(&da->list);
1060                         kfree(da);
1061                         break;
1062                 }
1063         }
1064 }
1065
1066 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1067 {
1068         enum dc_irq_source irq_source;
1069         bool ret;
1070
1071         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1072
1073         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1074
1075         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1076                          enable ? "en" : "dis", ret);
1077         return ret;
1078 }
1079
1080 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1081 {
1082         /* TODO: virtual DPCD */
1083         struct dc_link *link = stream->link;
1084         union down_spread_ctrl old_downspread;
1085         union down_spread_ctrl new_downspread;
1086
1087         if (link->aux_access_disabled)
1088                 return;
1089
1090         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1091                                      &old_downspread.raw,
1092                                      sizeof(old_downspread)))
1093                 return;
1094
1095         new_downspread.raw = old_downspread.raw;
1096         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1097                 (stream->ignore_msa_timing_param) ? 1 : 0;
1098
1099         if (new_downspread.raw != old_downspread.raw)
1100                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1101                                          &new_downspread.raw,
1102                                          sizeof(new_downspread));
1103 }
1104
1105 bool dm_helpers_dp_handle_test_pattern_request(
1106                 struct dc_context *ctx,
1107                 const struct dc_link *link,
1108                 union link_test_pattern dpcd_test_pattern,
1109                 union test_misc dpcd_test_params)
1110 {
1111         enum dp_test_pattern test_pattern;
1112         enum dp_test_pattern_color_space test_pattern_color_space =
1113                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1114         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1115         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1116         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1117         struct pipe_ctx *pipe_ctx = NULL;
1118         struct amdgpu_dm_connector *aconnector = link->priv;
1119         struct drm_device *dev = aconnector->base.dev;
1120         int i;
1121
1122         for (i = 0; i < MAX_PIPES; i++) {
1123                 if (pipes[i].stream == NULL)
1124                         continue;
1125
1126                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1127                         !pipes[i].prev_odm_pipe) {
1128                         pipe_ctx = &pipes[i];
1129                         break;
1130                 }
1131         }
1132
1133         if (pipe_ctx == NULL)
1134                 return false;
1135
1136         switch (dpcd_test_pattern.bits.PATTERN) {
1137         case LINK_TEST_PATTERN_COLOR_RAMP:
1138                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1139         break;
1140         case LINK_TEST_PATTERN_VERTICAL_BARS:
1141                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1142         break; /* black and white */
1143         case LINK_TEST_PATTERN_COLOR_SQUARES:
1144                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1145                                 TEST_DYN_RANGE_VESA ?
1146                                 DP_TEST_PATTERN_COLOR_SQUARES :
1147                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1148         break;
1149         default:
1150                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1151         break;
1152         }
1153
1154         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1155                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1156         else
1157                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1158                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1159                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1160
1161         switch (dpcd_test_params.bits.BPC) {
1162         case 0: // 6 bits
1163                 requestColorDepth = COLOR_DEPTH_666;
1164                 break;
1165         case 1: // 8 bits
1166                 requestColorDepth = COLOR_DEPTH_888;
1167                 break;
1168         case 2: // 10 bits
1169                 requestColorDepth = COLOR_DEPTH_101010;
1170                 break;
1171         case 3: // 12 bits
1172                 requestColorDepth = COLOR_DEPTH_121212;
1173                 break;
1174         default:
1175                 break;
1176         }
1177
1178         switch (dpcd_test_params.bits.CLR_FORMAT) {
1179         case 0:
1180                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1181                 break;
1182         case 1:
1183                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1184                 break;
1185         case 2:
1186                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1187                 break;
1188         default:
1189                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1190                 break;
1191         }
1192
1193         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1194                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1195                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1196                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1197                 drm_dbg(dev,
1198                         "original bpc %d pix encoding %d, changing to %d  %d\n",
1199                         pipe_ctx->stream->timing.display_color_depth,
1200                         pipe_ctx->stream->timing.pixel_encoding,
1201                         requestColorDepth,
1202                         requestPixelEncoding);
1203                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1204                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1205
1206                 dc_link_update_dsc_config(pipe_ctx);
1207
1208                 aconnector->timing_changed = true;
1209                 /* store current timing */
1210                 if (aconnector->timing_requested)
1211                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1212                 else
1213                         drm_err(dev, "timing storage failed\n");
1214
1215         }
1216
1217         pipe_ctx->stream->test_pattern.type = test_pattern;
1218         pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
1219
1220         dc_link_dp_set_test_pattern(
1221                 (struct dc_link *) link,
1222                 test_pattern,
1223                 test_pattern_color_space,
1224                 NULL,
1225                 NULL,
1226                 0);
1227
1228         return false;
1229 }
1230
1231 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1232 {
1233        // TODO
1234 }
1235
1236 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1237 {
1238         /* TODO: add periodic detection implementation */
1239 }
1240
1241 void dm_helpers_dp_mst_update_branch_bandwidth(
1242                 struct dc_context *ctx,
1243                 struct dc_link *link)
1244 {
1245         // TODO
1246 }
1247
1248 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1249 {
1250         bool ret_val = false;
1251
1252         switch (branch_dev_id) {
1253         case DP_BRANCH_DEVICE_ID_0060AD:
1254         case DP_BRANCH_DEVICE_ID_00E04C:
1255         case DP_BRANCH_DEVICE_ID_90CC24:
1256                 ret_val = true;
1257                 break;
1258         default:
1259                 break;
1260         }
1261
1262         return ret_val;
1263 }
1264
1265 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1266 {
1267         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1268         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1269
1270         switch (dpcd_caps->dongle_type) {
1271         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1272                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1273                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1274                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1275                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1276                 break;
1277         default:
1278                 break;
1279         }
1280
1281         return as_type;
1282 }