drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/uaccess.h>
  27
  28 #include <drm/drm_debugfs.h>
  29
  30 #include "dc.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_debugfs.h"
  34 #include "dm_helpers.h"
  35 #include "dmub/dmub_srv.h"
  36 #include "resource.h"
  37 #include "dsc.h"
  38 #include "dc_link_dp.h"
  39
  40 struct dmub_debugfs_trace_header {
  41         uint32_t entry_count;
  42         uint32_t reserved[3];
  43 };
  44
  45 struct dmub_debugfs_trace_entry {
  46         uint32_t trace_code;
  47         uint32_t tick_count;
  48         uint32_t param0;
  49         uint32_t param1;
  50 };
  51
  52
  53 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  54  *
  55  * Function takes in attributes passed to debugfs write entry
  56  * and writes into param array.
  57  * The user passes max_param_num to identify maximum number of
  58  * parameters that could be parsed.
  59  *
  60  */
  61 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  62                                           long *param, const char __user *buf,
  63                                           int max_param_num,
  64                                           uint8_t *param_nums)
  65 {
  66         char *wr_buf_ptr = NULL;
  67         uint32_t wr_buf_count = 0;
  68         int r;
  69         char *sub_str = NULL;
  70         const char delimiter[3] = {' ', '\n', '\0'};
  71         uint8_t param_index = 0;
  72
  73         *param_nums = 0;
  74
  75         wr_buf_ptr = wr_buf;
  76
  77         r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
  78
  79                 /* r is bytes not be copied */
  80         if (r >= wr_buf_size) {
  81                 DRM_DEBUG_DRIVER("user data not be read\n");
  82                 return -EINVAL;
  83         }
  84
  85         /* check number of parameters. isspace could not differ space and \n */
  86         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  87                 /* skip space*/
  88                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  89                         wr_buf_ptr++;
  90                         wr_buf_count++;
  91                         }
  92
  93                 if (wr_buf_count == wr_buf_size)
  94                         break;
  95
  96                 /* skip non-space*/
  97                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
  98                         wr_buf_ptr++;
  99                         wr_buf_count++;
 100                 }
 101
 102                 (*param_nums)++;
 103
 104                 if (wr_buf_count == wr_buf_size)
 105                         break;
 106         }
 107
 108         if (*param_nums > max_param_num)
 109                 *param_nums = max_param_num;
 110 ;
 111
 112         wr_buf_ptr = wr_buf; /* reset buf pointer */
 113         wr_buf_count = 0; /* number of char already checked */
 114
 115         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 116                 wr_buf_ptr++;
 117                 wr_buf_count++;
 118         }
 119
 120         while (param_index < *param_nums) {
 121                 /* after strsep, wr_buf_ptr will be moved to after space */
 122                 sub_str = strsep(&wr_buf_ptr, delimiter);
 123
 124                 r = kstrtol(sub_str, 16, &(param[param_index]));
 125
 126                 if (r)
 127                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 128
 129                 param_index++;
 130         }
 131
 132         return 0;
 133 }
 134
 135 /* function description
 136  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 137  *
 138  * valid lane count value: 1, 2, 4
 139  * valid link rate value:
 140  * 06h = 1.62Gbps per lane
 141  * 0Ah = 2.7Gbps per lane
 142  * 0Ch = 3.24Gbps per lane
 143  * 14h = 5.4Gbps per lane
 144  * 1Eh = 8.1Gbps per lane
 145  *
 146  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 147  *
 148  * --- to get dp configuration
 149  *
 150  * cat link_settings
 151  *
 152  * It will list current, verified, reported, preferred dp configuration.
 153  * current -- for current video mode
 154  * verified --- maximum configuration which pass link training
 155  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 156  * preferred --- user force settings
 157  *
 158  * --- set (or force) dp configuration
 159  *
 160  * echo <lane_count>  <link_rate> > link_settings
 161  *
 162  * for example, to force to  2 lane, 2.7GHz,
 163  * echo 4 0xa > link_settings
 164  *
 165  * spread_spectrum could not be changed dynamically.
 166  *
 167  * in case invalid lane count, link rate are force, no hw programming will be
 168  * done. please check link settings after force operation to see if HW get
 169  * programming.
 170  *
 171  * cat link_settings
 172  *
 173  * check current and preferred settings.
 174  *
 175  */
 176 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 177                                  size_t size, loff_t *pos)
 178 {
 179         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 180         struct dc_link *link = connector->dc_link;
 181         char *rd_buf = NULL;
 182         char *rd_buf_ptr = NULL;
 183         const uint32_t rd_buf_size = 100;
 184         uint32_t result = 0;
 185         uint8_t str_len = 0;
 186         int r;
 187
 188         if (*pos & 3 || size & 3)
 189                 return -EINVAL;
 190
 191         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 192         if (!rd_buf)
 193                 return 0;
 194
 195         rd_buf_ptr = rd_buf;
 196
 197         str_len = strlen("Current:  %d  %d  %d  ");
 198         snprintf(rd_buf_ptr, str_len, "Current:  %d  %d  %d  ",
 199                         link->cur_link_settings.lane_count,
 200                         link->cur_link_settings.link_rate,
 201                         link->cur_link_settings.link_spread);
 202         rd_buf_ptr += str_len;
 203
 204         str_len = strlen("Verified:  %d  %d  %d  ");
 205         snprintf(rd_buf_ptr, str_len, "Verified:  %d  %d  %d  ",
 206                         link->verified_link_cap.lane_count,
 207                         link->verified_link_cap.link_rate,
 208                         link->verified_link_cap.link_spread);
 209         rd_buf_ptr += str_len;
 210
 211         str_len = strlen("Reported:  %d  %d  %d  ");
 212         snprintf(rd_buf_ptr, str_len, "Reported:  %d  %d  %d  ",
 213                         link->reported_link_cap.lane_count,
 214                         link->reported_link_cap.link_rate,
 215                         link->reported_link_cap.link_spread);
 216         rd_buf_ptr += str_len;
 217
 218         str_len = strlen("Preferred:  %d  %d  %d  ");
 219         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  %d  %d\n",
 220                         link->preferred_link_setting.lane_count,
 221                         link->preferred_link_setting.link_rate,
 222                         link->preferred_link_setting.link_spread);
 223
 224         while (size) {
 225                 if (*pos >= rd_buf_size)
 226                         break;
 227
 228                 r = put_user(*(rd_buf + result), buf);
 229                 if (r)
 230                         return r; /* r = -EFAULT */
 231
 232                 buf += 1;
 233                 size -= 1;
 234                 *pos += 1;
 235                 result += 1;
 236         }
 237
 238         kfree(rd_buf);
 239         return result;
 240 }
 241
 242 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 243                                  size_t size, loff_t *pos)
 244 {
 245         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 246         struct dc_link *link = connector->dc_link;
 247         struct dc *dc = (struct dc *)link->dc;
 248         struct dc_link_settings prefer_link_settings;
 249         char *wr_buf = NULL;
 250         const uint32_t wr_buf_size = 40;
 251         /* 0: lane_count; 1: link_rate */
 252         int max_param_num = 2;
 253         uint8_t param_nums = 0;
 254         long param[2];
 255         bool valid_input = false;
 256
 257         if (size == 0)
 258                 return -EINVAL;
 259
 260         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 261         if (!wr_buf)
 262                 return -ENOSPC;
 263
 264         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 265                                            (long *)param, buf,
 266                                            max_param_num,
 267                                            &param_nums)) {
 268                 kfree(wr_buf);
 269                 return -EINVAL;
 270         }
 271
 272         if (param_nums <= 0) {
 273                 kfree(wr_buf);
 274                 DRM_DEBUG_DRIVER("user data not be read\n");
 275                 return -EINVAL;
 276         }
 277
 278         switch (param[0]) {
 279         case LANE_COUNT_ONE:
 280         case LANE_COUNT_TWO:
 281         case LANE_COUNT_FOUR:
 282                 valid_input = true;
 283                 break;
 284         default:
 285                 break;
 286         }
 287
 288         switch (param[1]) {
 289         case LINK_RATE_LOW:
 290         case LINK_RATE_HIGH:
 291         case LINK_RATE_RBR2:
 292         case LINK_RATE_HIGH2:
 293         case LINK_RATE_HIGH3:
 294                 valid_input = true;
 295                 break;
 296         default:
 297                 break;
 298         }
 299
 300         if (!valid_input) {
 301                 kfree(wr_buf);
 302                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 303                 return size;
 304         }
 305
 306         /* save user force lane_count, link_rate to preferred settings
 307          * spread spectrum will not be changed
 308          */
 309         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 310         prefer_link_settings.lane_count = param[0];
 311         prefer_link_settings.link_rate = param[1];
 312
 313         dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link);
 314
 315         kfree(wr_buf);
 316         return size;
 317 }
 318
 319 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 320  * post-cursor2 (defined by VESA DP specification)
 321  *
 322  * valid values
 323  * voltage swing: 0,1,2,3
 324  * pre-emphasis : 0,1,2,3
 325  * post cursor2 : 0,1,2,3
 326  *
 327  *
 328  * how to use this debugfs
 329  *
 330  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 331  *
 332  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 333  *
 334  * To figure out which DP-x is the display for DP to be check,
 335  * cd DP-x
 336  * ls -ll
 337  * There should be debugfs file, like link_settings, phy_settings.
 338  * cat link_settings
 339  * from lane_count, link_rate to figure which DP-x is for display to be worked
 340  * on
 341  *
 342  * To get current DP PHY settings,
 343  * cat phy_settings
 344  *
 345  * To change DP PHY settings,
 346  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 347  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 348  * 0,
 349  * echo 2 3 0 > phy_settings
 350  *
 351  * To check if change be applied, get current phy settings by
 352  * cat phy_settings
 353  *
 354  * In case invalid values are set by user, like
 355  * echo 1 4 0 > phy_settings
 356  *
 357  * HW will NOT be programmed by these settings.
 358  * cat phy_settings will show the previous valid settings.
 359  */
 360 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 361                                  size_t size, loff_t *pos)
 362 {
 363         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 364         struct dc_link *link = connector->dc_link;
 365         char *rd_buf = NULL;
 366         const uint32_t rd_buf_size = 20;
 367         uint32_t result = 0;
 368         int r;
 369
 370         if (*pos & 3 || size & 3)
 371                 return -EINVAL;
 372
 373         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 374         if (!rd_buf)
 375                 return -EINVAL;
 376
 377         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d  ",
 378                         link->cur_lane_setting.VOLTAGE_SWING,
 379                         link->cur_lane_setting.PRE_EMPHASIS,
 380                         link->cur_lane_setting.POST_CURSOR2);
 381
 382         while (size) {
 383                 if (*pos >= rd_buf_size)
 384                         break;
 385
 386                 r = put_user((*(rd_buf + result)), buf);
 387                 if (r)
 388                         return r; /* r = -EFAULT */
 389
 390                 buf += 1;
 391                 size -= 1;
 392                 *pos += 1;
 393                 result += 1;
 394         }
 395
 396         kfree(rd_buf);
 397         return result;
 398 }
 399
 400 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 401                                  size_t size, loff_t *pos)
 402 {
 403         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 404         struct dc_link *link = connector->dc_link;
 405         struct dc *dc = (struct dc *)link->dc;
 406         char *wr_buf = NULL;
 407         uint32_t wr_buf_size = 40;
 408         long param[3];
 409         bool use_prefer_link_setting;
 410         struct link_training_settings link_lane_settings;
 411         int max_param_num = 3;
 412         uint8_t param_nums = 0;
 413         int r = 0;
 414
 415
 416         if (size == 0)
 417                 return -EINVAL;
 418
 419         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 420         if (!wr_buf)
 421                 return -ENOSPC;
 422
 423         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 424                                            (long *)param, buf,
 425                                            max_param_num,
 426                                            &param_nums)) {
 427                 kfree(wr_buf);
 428                 return -EINVAL;
 429         }
 430
 431         if (param_nums <= 0) {
 432                 kfree(wr_buf);
 433                 DRM_DEBUG_DRIVER("user data not be read\n");
 434                 return -EINVAL;
 435         }
 436
 437         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 438                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 439                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 440                 kfree(wr_buf);
 441                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 442                 return size;
 443         }
 444
 445         /* get link settings: lane count, link rate */
 446         use_prefer_link_setting =
 447                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 448                 (link->test_pattern_enabled));
 449
 450         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 451
 452         if (use_prefer_link_setting) {
 453                 link_lane_settings.link_settings.lane_count =
 454                                 link->preferred_link_setting.lane_count;
 455                 link_lane_settings.link_settings.link_rate =
 456                                 link->preferred_link_setting.link_rate;
 457                 link_lane_settings.link_settings.link_spread =
 458                                 link->preferred_link_setting.link_spread;
 459         } else {
 460                 link_lane_settings.link_settings.lane_count =
 461                                 link->cur_link_settings.lane_count;
 462                 link_lane_settings.link_settings.link_rate =
 463                                 link->cur_link_settings.link_rate;
 464                 link_lane_settings.link_settings.link_spread =
 465                                 link->cur_link_settings.link_spread;
 466         }
 467
 468         /* apply phy settings from user */
 469         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 470                 link_lane_settings.lane_settings[r].VOLTAGE_SWING =
 471                                 (enum dc_voltage_swing) (param[0]);
 472                 link_lane_settings.lane_settings[r].PRE_EMPHASIS =
 473                                 (enum dc_pre_emphasis) (param[1]);
 474                 link_lane_settings.lane_settings[r].POST_CURSOR2 =
 475                                 (enum dc_post_cursor2) (param[2]);
 476         }
 477
 478         /* program ASIC registers and DPCD registers */
 479         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 480
 481         kfree(wr_buf);
 482         return size;
 483 }
 484
 485 /* function description
 486  *
 487  * set PHY layer or Link layer test pattern
 488  * PHY test pattern is used for PHY SI check.
 489  * Link layer test will not affect PHY SI.
 490  *
 491  * Reset Test Pattern:
 492  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 493  *
 494  * PHY test pattern supported:
 495  * 1 = DP_TEST_PATTERN_D102
 496  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 497  * 3 = DP_TEST_PATTERN_PRBS7
 498  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 499  * 5 = DP_TEST_PATTERN_CP2520_1
 500  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 501  * 7 = DP_TEST_PATTERN_CP2520_3
 502  *
 503  * DP PHY Link Training Patterns
 504  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 505  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 506  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 507  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 508  *
 509  * DP Link Layer Test pattern
 510  * c = DP_TEST_PATTERN_COLOR_SQUARES
 511  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 512  * e = DP_TEST_PATTERN_VERTICAL_BARS
 513  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 514  * 10= DP_TEST_PATTERN_COLOR_RAMP
 515  *
 516  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 517  *
 518  * --- set test pattern
 519  * echo <test pattern #> > test_pattern
 520  *
 521  * If test pattern # is not supported, NO HW programming will be done.
 522  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 523  * for the user pattern. input 10 bytes data are separated by space
 524  *
 525  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 526  *
 527  * --- reset test pattern
 528  * echo 0 > test_pattern
 529  *
 530  * --- HPD detection is disabled when set PHY test pattern
 531  *
 532  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 533  * is disable. User could unplug DP display from DP connected and plug scope to
 534  * check test pattern PHY SI.
 535  * If there is need unplug scope and plug DP display back, do steps below:
 536  * echo 0 > phy_test_pattern
 537  * unplug scope
 538  * plug DP display.
 539  *
 540  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 541  * driver could detect "unplug scope" and "plug DP display"
 542  */
 543 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 544                                  size_t size, loff_t *pos)
 545 {
 546         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 547         struct dc_link *link = connector->dc_link;
 548         char *wr_buf = NULL;
 549         uint32_t wr_buf_size = 100;
 550         long param[11] = {0x0};
 551         int max_param_num = 11;
 552         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 553         bool disable_hpd = false;
 554         bool valid_test_pattern = false;
 555         uint8_t param_nums = 0;
 556         /* init with defalut 80bit custom pattern */
 557         uint8_t custom_pattern[10] = {
 558                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 559                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 560                         };
 561         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 562                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 563         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 564                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 565         struct link_training_settings link_training_settings;
 566         int i;
 567
 568         if (size == 0)
 569                 return -EINVAL;
 570
 571         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 572         if (!wr_buf)
 573                 return -ENOSPC;
 574
 575         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 576                                            (long *)param, buf,
 577                                            max_param_num,
 578                                            &param_nums)) {
 579                 kfree(wr_buf);
 580                 return -EINVAL;
 581         }
 582
 583         if (param_nums <= 0) {
 584                 kfree(wr_buf);
 585                 DRM_DEBUG_DRIVER("user data not be read\n");
 586                 return -EINVAL;
 587         }
 588
 589
 590         test_pattern = param[0];
 591
 592         switch (test_pattern) {
 593         case DP_TEST_PATTERN_VIDEO_MODE:
 594         case DP_TEST_PATTERN_COLOR_SQUARES:
 595         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 596         case DP_TEST_PATTERN_VERTICAL_BARS:
 597         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 598         case DP_TEST_PATTERN_COLOR_RAMP:
 599                 valid_test_pattern = true;
 600                 break;
 601
 602         case DP_TEST_PATTERN_D102:
 603         case DP_TEST_PATTERN_SYMBOL_ERROR:
 604         case DP_TEST_PATTERN_PRBS7:
 605         case DP_TEST_PATTERN_80BIT_CUSTOM:
 606         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 607         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 608                 disable_hpd = true;
 609                 valid_test_pattern = true;
 610                 break;
 611
 612         default:
 613                 valid_test_pattern = false;
 614                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 615                 break;
 616         }
 617
 618         if (!valid_test_pattern) {
 619                 kfree(wr_buf);
 620                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 621                 return size;
 622         }
 623
 624         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 625                 for (i = 0; i < 10; i++) {
 626                         if ((uint8_t) param[i + 1] != 0x0)
 627                                 break;
 628                 }
 629
 630                 if (i < 10) {
 631                         /* not use default value */
 632                         for (i = 0; i < 10; i++)
 633                                 custom_pattern[i] = (uint8_t) param[i + 1];
 634                 }
 635         }
 636
 637         /* Usage: set DP physical test pattern using debugfs with normal DP
 638          * panel. Then plug out DP panel and connect a scope to measure
 639          * For normal video mode and test pattern generated from CRCT,
 640          * they are visibile to user. So do not disable HPD.
 641          * Video Mode is also set to clear the test pattern, so enable HPD
 642          * because it might have been disabled after a test pattern was set.
 643          * AUX depends on HPD * sequence dependent, do not move!
 644          */
 645         if (!disable_hpd)
 646                 dc_link_enable_hpd(link);
 647
 648         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 649         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 650         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 651
 652         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 653         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 654         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 655
 656         link_training_settings.link_settings = cur_link_settings;
 657
 658
 659         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 660                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 661                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 662                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 663                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 664                         link_training_settings.link_settings = prefer_link_settings;
 665         }
 666
 667         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 668                 link_training_settings.lane_settings[i] = link->cur_lane_setting;
 669
 670         dc_link_set_test_pattern(
 671                 link,
 672                 test_pattern,
 673                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 674                 &link_training_settings,
 675                 custom_pattern,
 676                 10);
 677
 678         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 679          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 680          * Need disable interrupt to avoid SW driver disable DP output. This is
 681          * done after the test pattern is set.
 682          */
 683         if (valid_test_pattern && disable_hpd)
 684                 dc_link_disable_hpd(link);
 685
 686         kfree(wr_buf);
 687
 688         return size;
 689 }
 690
 691 /**
 692  * Returns the DMCUB tracebuffer contents.
 693  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 694  */
 695 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 696 {
 697         struct amdgpu_device *adev = m->private;
 698         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 699         struct dmub_debugfs_trace_entry *entries;
 700         uint8_t *tbuf_base;
 701         uint32_t tbuf_size, max_entries, num_entries, i;
 702
 703         if (!fb_info)
 704                 return 0;
 705
 706         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 707         if (!tbuf_base)
 708                 return 0;
 709
 710         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 711         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 712                       sizeof(struct dmub_debugfs_trace_entry);
 713
 714         num_entries =
 715                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 716
 717         num_entries = min(num_entries, max_entries);
 718
 719         entries = (struct dmub_debugfs_trace_entry
 720                            *)(tbuf_base +
 721                               sizeof(struct dmub_debugfs_trace_header));
 722
 723         for (i = 0; i < num_entries; ++i) {
 724                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 725
 726                 seq_printf(m,
 727                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 728                            entry->trace_code, entry->tick_count, entry->param0,
 729                            entry->param1);
 730         }
 731
 732         return 0;
 733 }
 734
 735 /**
 736  * Returns the DMCUB firmware state contents.
 737  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 738  */
 739 static int dmub_fw_state_show(struct seq_file *m, void *data)
 740 {
 741         struct amdgpu_device *adev = m->private;
 742         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 743         uint8_t *state_base;
 744         uint32_t state_size;
 745
 746         if (!fb_info)
 747                 return 0;
 748
 749         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 750         if (!state_base)
 751                 return 0;
 752
 753         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 754
 755         return seq_write(m, state_base, state_size);
 756 }
 757
 758 /*
 759  * Returns the current and maximum output bpc for the connector.
 760  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
 761  */
 762 static int output_bpc_show(struct seq_file *m, void *data)
 763 {
 764         struct drm_connector *connector = m->private;
 765         struct drm_device *dev = connector->dev;
 766         struct drm_crtc *crtc = NULL;
 767         struct dm_crtc_state *dm_crtc_state = NULL;
 768         int res = -ENODEV;
 769         unsigned int bpc;
 770
 771         mutex_lock(&dev->mode_config.mutex);
 772         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 773
 774         if (connector->state == NULL)
 775                 goto unlock;
 776
 777         crtc = connector->state->crtc;
 778         if (crtc == NULL)
 779                 goto unlock;
 780
 781         drm_modeset_lock(&crtc->mutex, NULL);
 782         if (crtc->state == NULL)
 783                 goto unlock;
 784
 785         dm_crtc_state = to_dm_crtc_state(crtc->state);
 786         if (dm_crtc_state->stream == NULL)
 787                 goto unlock;
 788
 789         switch (dm_crtc_state->stream->timing.display_color_depth) {
 790         case COLOR_DEPTH_666:
 791                 bpc = 6;
 792                 break;
 793         case COLOR_DEPTH_888:
 794                 bpc = 8;
 795                 break;
 796         case COLOR_DEPTH_101010:
 797                 bpc = 10;
 798                 break;
 799         case COLOR_DEPTH_121212:
 800                 bpc = 12;
 801                 break;
 802         case COLOR_DEPTH_161616:
 803                 bpc = 16;
 804                 break;
 805         default:
 806                 goto unlock;
 807         }
 808
 809         seq_printf(m, "Current: %u\n", bpc);
 810         seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
 811         res = 0;
 812
 813 unlock:
 814         if (crtc)
 815                 drm_modeset_unlock(&crtc->mutex);
 816
 817         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 818         mutex_unlock(&dev->mode_config.mutex);
 819
 820         return res;
 821 }
 822
 823 #ifdef CONFIG_DRM_AMD_DC_HDCP
 824 /*
 825  * Returns the HDCP capability of the Display (1.4 for now).
 826  *
 827  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 828  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 829  *
 830  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 831  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 832  */
 833 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 834 {
 835         struct drm_connector *connector = m->private;
 836         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 837         bool hdcp_cap, hdcp2_cap;
 838
 839         if (connector->status != connector_status_connected)
 840                 return -ENODEV;
 841
 842         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 843
 844         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 845         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 846
 847
 848         if (hdcp_cap)
 849                 seq_printf(m, "%s ", "HDCP1.4");
 850         if (hdcp2_cap)
 851                 seq_printf(m, "%s ", "HDCP2.2");
 852
 853         if (!hdcp_cap && !hdcp2_cap)
 854                 seq_printf(m, "%s ", "None");
 855
 856         seq_puts(m, "\n");
 857
 858         return 0;
 859 }
 860 #endif
 861 /* function description
 862  *
 863  * generic SDP message access for testing
 864  *
 865  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
 866  *
 867  * SDP header
 868  * Hb0 : Secondary-Data Packet ID
 869  * Hb1 : Secondary-Data Packet type
 870  * Hb2 : Secondary-Data-packet-specific header, Byte 0
 871  * Hb3 : Secondary-Data-packet-specific header, Byte 1
 872  *
 873  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
 874  */
 875 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
 876                                  size_t size, loff_t *pos)
 877 {
 878         int r;
 879         uint8_t data[36];
 880         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 881         struct dm_crtc_state *acrtc_state;
 882         uint32_t write_size = 36;
 883
 884         if (connector->base.status != connector_status_connected)
 885                 return -ENODEV;
 886
 887         if (size == 0)
 888                 return 0;
 889
 890         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
 891
 892         r = copy_from_user(data, buf, write_size);
 893
 894         write_size -= r;
 895
 896         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
 897
 898         return write_size;
 899 }
 900
 901 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
 902                                  size_t size, loff_t *pos)
 903 {
 904         int r;
 905         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 906
 907         if (size < sizeof(connector->debugfs_dpcd_address))
 908                 return 0;
 909
 910         r = copy_from_user(&connector->debugfs_dpcd_address,
 911                         buf, sizeof(connector->debugfs_dpcd_address));
 912
 913         return size - r;
 914 }
 915
 916 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
 917                                  size_t size, loff_t *pos)
 918 {
 919         int r;
 920         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 921
 922         if (size < sizeof(connector->debugfs_dpcd_size))
 923                 return 0;
 924
 925         r = copy_from_user(&connector->debugfs_dpcd_size,
 926                         buf, sizeof(connector->debugfs_dpcd_size));
 927
 928         if (connector->debugfs_dpcd_size > 256)
 929                 connector->debugfs_dpcd_size = 0;
 930
 931         return size - r;
 932 }
 933
 934 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
 935                                  size_t size, loff_t *pos)
 936 {
 937         int r;
 938         char *data;
 939         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 940         struct dc_link *link = connector->dc_link;
 941         uint32_t write_size = connector->debugfs_dpcd_size;
 942
 943         if (size < write_size)
 944                 return 0;
 945
 946         data = kzalloc(write_size, GFP_KERNEL);
 947         if (!data)
 948                 return 0;
 949
 950         r = copy_from_user(data, buf, write_size);
 951
 952         dm_helpers_dp_write_dpcd(link->ctx, link,
 953                         connector->debugfs_dpcd_address, data, write_size - r);
 954         kfree(data);
 955         return write_size - r;
 956 }
 957
 958 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
 959                                  size_t size, loff_t *pos)
 960 {
 961         int r;
 962         char *data;
 963         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 964         struct dc_link *link = connector->dc_link;
 965         uint32_t read_size = connector->debugfs_dpcd_size;
 966
 967         if (size < read_size)
 968                 return 0;
 969
 970         data = kzalloc(read_size, GFP_KERNEL);
 971         if (!data)
 972                 return 0;
 973
 974         dm_helpers_dp_read_dpcd(link->ctx, link,
 975                         connector->debugfs_dpcd_address, data, read_size);
 976
 977         r = copy_to_user(buf, data, read_size);
 978
 979         kfree(data);
 980         return read_size - r;
 981 }
 982
 983 /* function: read DSC status on the connector
 984  *
 985  * The read function: dp_dsc_clock_en_read
 986  * returns current status of DSC clock on the connector.
 987  * The return is a boolean flag: 1 or 0.
 988  *
 989  * Access it with the following command (you need to specify
 990  * connector like DP-1):
 991  *
 992  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
 993  *
 994  * Expected output:
 995  * 1 - means that DSC is currently enabled
 996  * 0 - means that DSC is disabled
 997  */
 998 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
 999                                     size_t size, loff_t *pos)
1000 {
1001         char *rd_buf = NULL;
1002         char *rd_buf_ptr = NULL;
1003         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1004         struct display_stream_compressor *dsc;
1005         struct dcn_dsc_state dsc_state = {0};
1006         const uint32_t rd_buf_size = 10;
1007         struct pipe_ctx *pipe_ctx;
1008         ssize_t result = 0;
1009         int i, r, str_len = 30;
1010
1011         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1012
1013         if (!rd_buf)
1014                 return -ENOMEM;
1015
1016         rd_buf_ptr = rd_buf;
1017
1018         for (i = 0; i < MAX_PIPES; i++) {
1019                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1020                         if (pipe_ctx && pipe_ctx->stream &&
1021                             pipe_ctx->stream->link == aconnector->dc_link)
1022                                 break;
1023         }
1024
1025         if (!pipe_ctx)
1026                 return -ENXIO;
1027
1028         dsc = pipe_ctx->stream_res.dsc;
1029         if (dsc)
1030                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1031
1032         snprintf(rd_buf_ptr, str_len,
1033                 "%d\n",
1034                 dsc_state.dsc_clock_en);
1035         rd_buf_ptr += str_len;
1036
1037         while (size) {
1038                 if (*pos >= rd_buf_size)
1039                         break;
1040
1041                 r = put_user(*(rd_buf + result), buf);
1042                 if (r)
1043                         return r; /* r = -EFAULT */
1044
1045                 buf += 1;
1046                 size -= 1;
1047                 *pos += 1;
1048                 result += 1;
1049         }
1050
1051         kfree(rd_buf);
1052         return result;
1053 }
1054
1055 /* function: write force DSC on the connector
1056  *
1057  * The write function: dp_dsc_clock_en_write
1058  * enables to force DSC on the connector.
1059  * User can write to either force enable DSC
1060  * on the next modeset or set it to driver default
1061  *
1062  * Writing DSC settings is done with the following command:
1063  * - To force enable DSC (you need to specify
1064  * connector like DP-1):
1065  *
1066  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1067  *
1068  * - To return to default state set the flag to zero and
1069  * let driver deal with DSC automatically
1070  * (you need to specify connector like DP-1):
1071  *
1072  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1073  *
1074  */
1075 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1076                                      size_t size, loff_t *pos)
1077 {
1078         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1079         struct pipe_ctx *pipe_ctx;
1080         int i;
1081         char *wr_buf = NULL;
1082         uint32_t wr_buf_size = 42;
1083         int max_param_num = 1;
1084         long param[1] = {0};
1085         uint8_t param_nums = 0;
1086
1087         if (size == 0)
1088                 return -EINVAL;
1089
1090         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1091
1092         if (!wr_buf) {
1093                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1094                 return -ENOSPC;
1095         }
1096
1097         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1098                                             (long *)param, buf,
1099                                             max_param_num,
1100                                             &param_nums)) {
1101                 kfree(wr_buf);
1102                 return -EINVAL;
1103         }
1104
1105         if (param_nums <= 0) {
1106                 DRM_DEBUG_DRIVER("user data not be read\n");
1107                 kfree(wr_buf);
1108                 return -EINVAL;
1109         }
1110
1111         for (i = 0; i < MAX_PIPES; i++) {
1112                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1113                         if (pipe_ctx && pipe_ctx->stream &&
1114                             pipe_ctx->stream->link == aconnector->dc_link)
1115                                 break;
1116         }
1117
1118         if (!pipe_ctx || !pipe_ctx->stream)
1119                 goto done;
1120
1121         aconnector->dsc_settings.dsc_clock_en = param[0];
1122
1123 done:
1124         kfree(wr_buf);
1125         return size;
1126 }
1127
1128 /* function: read DSC slice width parameter on the connector
1129  *
1130  * The read function: dp_dsc_slice_width_read
1131  * returns dsc slice width used in the current configuration
1132  * The return is an integer: 0 or other positive number
1133  *
1134  * Access the status with the following command:
1135  *
1136  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1137  *
1138  * 0 - means that DSC is disabled
1139  *
1140  * Any other number more than zero represents the
1141  * slice width currently used by DSC in pixels
1142  *
1143  */
1144 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1145                                     size_t size, loff_t *pos)
1146 {
1147         char *rd_buf = NULL;
1148         char *rd_buf_ptr = NULL;
1149         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1150         struct display_stream_compressor *dsc;
1151         struct dcn_dsc_state dsc_state = {0};
1152         const uint32_t rd_buf_size = 100;
1153         struct pipe_ctx *pipe_ctx;
1154         ssize_t result = 0;
1155         int i, r, str_len = 30;
1156
1157         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1158
1159         if (!rd_buf)
1160                 return -ENOMEM;
1161
1162         rd_buf_ptr = rd_buf;
1163
1164         for (i = 0; i < MAX_PIPES; i++) {
1165                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1166                         if (pipe_ctx && pipe_ctx->stream &&
1167                             pipe_ctx->stream->link == aconnector->dc_link)
1168                                 break;
1169         }
1170
1171         if (!pipe_ctx)
1172                 return -ENXIO;
1173
1174         dsc = pipe_ctx->stream_res.dsc;
1175         if (dsc)
1176                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1177
1178         snprintf(rd_buf_ptr, str_len,
1179                 "%d\n",
1180                 dsc_state.dsc_slice_width);
1181         rd_buf_ptr += str_len;
1182
1183         while (size) {
1184                 if (*pos >= rd_buf_size)
1185                         break;
1186
1187                 r = put_user(*(rd_buf + result), buf);
1188                 if (r)
1189                         return r; /* r = -EFAULT */
1190
1191                 buf += 1;
1192                 size -= 1;
1193                 *pos += 1;
1194                 result += 1;
1195         }
1196
1197         kfree(rd_buf);
1198         return result;
1199 }
1200
1201 /* function: write DSC slice width parameter
1202  *
1203  * The write function: dp_dsc_slice_width_write
1204  * overwrites automatically generated DSC configuration
1205  * of slice width.
1206  *
1207  * The user has to write the slice width divisible by the
1208  * picture width.
1209  *
1210  * Also the user has to write width in hexidecimal
1211  * rather than in decimal.
1212  *
1213  * Writing DSC settings is done with the following command:
1214  * - To force overwrite slice width: (example sets to 1920 pixels)
1215  *
1216  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1217  *
1218  *  - To stop overwriting and let driver find the optimal size,
1219  * set the width to zero:
1220  *
1221  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1222  *
1223  */
1224 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1225                                      size_t size, loff_t *pos)
1226 {
1227         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1228         struct pipe_ctx *pipe_ctx;
1229         int i;
1230         char *wr_buf = NULL;
1231         uint32_t wr_buf_size = 42;
1232         int max_param_num = 1;
1233         long param[1] = {0};
1234         uint8_t param_nums = 0;
1235
1236         if (size == 0)
1237                 return -EINVAL;
1238
1239         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1240
1241         if (!wr_buf) {
1242                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1243                 return -ENOSPC;
1244         }
1245
1246         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1247                                             (long *)param, buf,
1248                                             max_param_num,
1249                                             &param_nums)) {
1250                 kfree(wr_buf);
1251                 return -EINVAL;
1252         }
1253
1254         if (param_nums <= 0) {
1255                 DRM_DEBUG_DRIVER("user data not be read\n");
1256                 kfree(wr_buf);
1257                 return -EINVAL;
1258         }
1259
1260         for (i = 0; i < MAX_PIPES; i++) {
1261                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1262                         if (pipe_ctx && pipe_ctx->stream &&
1263                             pipe_ctx->stream->link == aconnector->dc_link)
1264                                 break;
1265         }
1266
1267         if (!pipe_ctx || !pipe_ctx->stream)
1268                 goto done;
1269
1270         aconnector->dsc_settings.dsc_slice_width = param[0];
1271
1272 done:
1273         kfree(wr_buf);
1274         return size;
1275 }
1276
1277 /* function: read DSC slice height parameter on the connector
1278  *
1279  * The read function: dp_dsc_slice_height_read
1280  * returns dsc slice height used in the current configuration
1281  * The return is an integer: 0 or other positive number
1282  *
1283  * Access the status with the following command:
1284  *
1285  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1286  *
1287  * 0 - means that DSC is disabled
1288  *
1289  * Any other number more than zero represents the
1290  * slice height currently used by DSC in pixels
1291  *
1292  */
1293 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1294                                     size_t size, loff_t *pos)
1295 {
1296         char *rd_buf = NULL;
1297         char *rd_buf_ptr = NULL;
1298         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1299         struct display_stream_compressor *dsc;
1300         struct dcn_dsc_state dsc_state = {0};
1301         const uint32_t rd_buf_size = 100;
1302         struct pipe_ctx *pipe_ctx;
1303         ssize_t result = 0;
1304         int i, r, str_len = 30;
1305
1306         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1307
1308         if (!rd_buf)
1309                 return -ENOMEM;
1310
1311         rd_buf_ptr = rd_buf;
1312
1313         for (i = 0; i < MAX_PIPES; i++) {
1314                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1315                         if (pipe_ctx && pipe_ctx->stream &&
1316                             pipe_ctx->stream->link == aconnector->dc_link)
1317                                 break;
1318         }
1319
1320         if (!pipe_ctx)
1321                 return -ENXIO;
1322
1323         dsc = pipe_ctx->stream_res.dsc;
1324         if (dsc)
1325                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1326
1327         snprintf(rd_buf_ptr, str_len,
1328                 "%d\n",
1329                 dsc_state.dsc_slice_height);
1330         rd_buf_ptr += str_len;
1331
1332         while (size) {
1333                 if (*pos >= rd_buf_size)
1334                         break;
1335
1336                 r = put_user(*(rd_buf + result), buf);
1337                 if (r)
1338                         return r; /* r = -EFAULT */
1339
1340                 buf += 1;
1341                 size -= 1;
1342                 *pos += 1;
1343                 result += 1;
1344         }
1345
1346         kfree(rd_buf);
1347         return result;
1348 }
1349
1350 /* function: write DSC slice height parameter
1351  *
1352  * The write function: dp_dsc_slice_height_write
1353  * overwrites automatically generated DSC configuration
1354  * of slice height.
1355  *
1356  * The user has to write the slice height divisible by the
1357  * picture height.
1358  *
1359  * Also the user has to write height in hexidecimal
1360  * rather than in decimal.
1361  *
1362  * Writing DSC settings is done with the following command:
1363  * - To force overwrite slice height (example sets to 128 pixels):
1364  *
1365  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1366  *
1367  *  - To stop overwriting and let driver find the optimal size,
1368  * set the height to zero:
1369  *
1370  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1371  *
1372  */
1373 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1374                                      size_t size, loff_t *pos)
1375 {
1376         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1377         struct pipe_ctx *pipe_ctx;
1378         int i;
1379         char *wr_buf = NULL;
1380         uint32_t wr_buf_size = 42;
1381         int max_param_num = 1;
1382         uint8_t param_nums = 0;
1383         long param[1] = {0};
1384
1385         if (size == 0)
1386                 return -EINVAL;
1387
1388         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1389
1390         if (!wr_buf) {
1391                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1392                 return -ENOSPC;
1393         }
1394
1395         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1396                                             (long *)param, buf,
1397                                             max_param_num,
1398                                             &param_nums)) {
1399                 kfree(wr_buf);
1400                 return -EINVAL;
1401         }
1402
1403         if (param_nums <= 0) {
1404                 DRM_DEBUG_DRIVER("user data not be read\n");
1405                 kfree(wr_buf);
1406                 return -EINVAL;
1407         }
1408
1409         for (i = 0; i < MAX_PIPES; i++) {
1410                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1411                         if (pipe_ctx && pipe_ctx->stream &&
1412                             pipe_ctx->stream->link == aconnector->dc_link)
1413                                 break;
1414         }
1415
1416         if (!pipe_ctx || !pipe_ctx->stream)
1417                 goto done;
1418
1419         aconnector->dsc_settings.dsc_slice_height = param[0];
1420
1421 done:
1422         kfree(wr_buf);
1423         return size;
1424 }
1425
1426 /* function: read DSC target rate on the connector in bits per pixel
1427  *
1428  * The read function: dp_dsc_bits_per_pixel_read
1429  * returns target rate of compression in bits per pixel
1430  * The return is an integer: 0 or other positive integer
1431  *
1432  * Access it with the following command:
1433  *
1434  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1435  *
1436  *  0 - means that DSC is disabled
1437  */
1438 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1439                                     size_t size, loff_t *pos)
1440 {
1441         char *rd_buf = NULL;
1442         char *rd_buf_ptr = NULL;
1443         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1444         struct display_stream_compressor *dsc;
1445         struct dcn_dsc_state dsc_state = {0};
1446         const uint32_t rd_buf_size = 100;
1447         struct pipe_ctx *pipe_ctx;
1448         ssize_t result = 0;
1449         int i, r, str_len = 30;
1450
1451         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1452
1453         if (!rd_buf)
1454                 return -ENOMEM;
1455
1456         rd_buf_ptr = rd_buf;
1457
1458         for (i = 0; i < MAX_PIPES; i++) {
1459                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1460                         if (pipe_ctx && pipe_ctx->stream &&
1461                             pipe_ctx->stream->link == aconnector->dc_link)
1462                                 break;
1463         }
1464
1465         if (!pipe_ctx)
1466                 return -ENXIO;
1467
1468         dsc = pipe_ctx->stream_res.dsc;
1469         if (dsc)
1470                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1471
1472         snprintf(rd_buf_ptr, str_len,
1473                 "%d\n",
1474                 dsc_state.dsc_bits_per_pixel);
1475         rd_buf_ptr += str_len;
1476
1477         while (size) {
1478                 if (*pos >= rd_buf_size)
1479                         break;
1480
1481                 r = put_user(*(rd_buf + result), buf);
1482                 if (r)
1483                         return r; /* r = -EFAULT */
1484
1485                 buf += 1;
1486                 size -= 1;
1487                 *pos += 1;
1488                 result += 1;
1489         }
1490
1491         kfree(rd_buf);
1492         return result;
1493 }
1494
1495 /* function: write DSC target rate in bits per pixel
1496  *
1497  * The write function: dp_dsc_bits_per_pixel_write
1498  * overwrites automatically generated DSC configuration
1499  * of DSC target bit rate.
1500  *
1501  * Also the user has to write bpp in hexidecimal
1502  * rather than in decimal.
1503  *
1504  * Writing DSC settings is done with the following command:
1505  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1506  *
1507  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1508  *
1509  *  - To stop overwriting and let driver find the optimal rate,
1510  * set the rate to zero:
1511  *
1512  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1513  *
1514  */
1515 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1516                                      size_t size, loff_t *pos)
1517 {
1518         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1519         struct pipe_ctx *pipe_ctx;
1520         int i;
1521         char *wr_buf = NULL;
1522         uint32_t wr_buf_size = 42;
1523         int max_param_num = 1;
1524         uint8_t param_nums = 0;
1525         long param[1] = {0};
1526
1527         if (size == 0)
1528                 return -EINVAL;
1529
1530         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1531
1532         if (!wr_buf) {
1533                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1534                 return -ENOSPC;
1535         }
1536
1537         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1538                                             (long *)param, buf,
1539                                             max_param_num,
1540                                             &param_nums)) {
1541                 kfree(wr_buf);
1542                 return -EINVAL;
1543         }
1544
1545         if (param_nums <= 0) {
1546                 DRM_DEBUG_DRIVER("user data not be read\n");
1547                 kfree(wr_buf);
1548                 return -EINVAL;
1549         }
1550
1551         for (i = 0; i < MAX_PIPES; i++) {
1552                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1553                         if (pipe_ctx && pipe_ctx->stream &&
1554                             pipe_ctx->stream->link == aconnector->dc_link)
1555                                 break;
1556         }
1557
1558         if (!pipe_ctx || !pipe_ctx->stream)
1559                 goto done;
1560
1561         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
1562
1563 done:
1564         kfree(wr_buf);
1565         return size;
1566 }
1567
1568 /* function: read DSC picture width parameter on the connector
1569  *
1570  * The read function: dp_dsc_pic_width_read
1571  * returns dsc picture width used in the current configuration
1572  * It is the same as h_addressable of the current
1573  * display's timing
1574  * The return is an integer: 0 or other positive integer
1575  * If 0 then DSC is disabled.
1576  *
1577  * Access it with the following command:
1578  *
1579  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
1580  *
1581  * 0 - means that DSC is disabled
1582  */
1583 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
1584                                     size_t size, loff_t *pos)
1585 {
1586         char *rd_buf = NULL;
1587         char *rd_buf_ptr = NULL;
1588         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1589         struct display_stream_compressor *dsc;
1590         struct dcn_dsc_state dsc_state = {0};
1591         const uint32_t rd_buf_size = 100;
1592         struct pipe_ctx *pipe_ctx;
1593         ssize_t result = 0;
1594         int i, r, str_len = 30;
1595
1596         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1597
1598         if (!rd_buf)
1599                 return -ENOMEM;
1600
1601         rd_buf_ptr = rd_buf;
1602
1603         for (i = 0; i < MAX_PIPES; i++) {
1604                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1605                         if (pipe_ctx && pipe_ctx->stream &&
1606                             pipe_ctx->stream->link == aconnector->dc_link)
1607                                 break;
1608         }
1609
1610         if (!pipe_ctx)
1611                 return -ENXIO;
1612
1613         dsc = pipe_ctx->stream_res.dsc;
1614         if (dsc)
1615                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1616
1617         snprintf(rd_buf_ptr, str_len,
1618                 "%d\n",
1619                 dsc_state.dsc_pic_width);
1620         rd_buf_ptr += str_len;
1621
1622         while (size) {
1623                 if (*pos >= rd_buf_size)
1624                         break;
1625
1626                 r = put_user(*(rd_buf + result), buf);
1627                 if (r)
1628                         return r; /* r = -EFAULT */
1629
1630                 buf += 1;
1631                 size -= 1;
1632                 *pos += 1;
1633                 result += 1;
1634         }
1635
1636         kfree(rd_buf);
1637         return result;
1638 }
1639
1640 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
1641                                     size_t size, loff_t *pos)
1642 {
1643         char *rd_buf = NULL;
1644         char *rd_buf_ptr = NULL;
1645         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1646         struct display_stream_compressor *dsc;
1647         struct dcn_dsc_state dsc_state = {0};
1648         const uint32_t rd_buf_size = 100;
1649         struct pipe_ctx *pipe_ctx;
1650         ssize_t result = 0;
1651         int i, r, str_len = 30;
1652
1653         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1654
1655         if (!rd_buf)
1656                 return -ENOMEM;
1657
1658         rd_buf_ptr = rd_buf;
1659
1660         for (i = 0; i < MAX_PIPES; i++) {
1661                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1662                         if (pipe_ctx && pipe_ctx->stream &&
1663                             pipe_ctx->stream->link == aconnector->dc_link)
1664                                 break;
1665         }
1666
1667         if (!pipe_ctx)
1668                 return -ENXIO;
1669
1670         dsc = pipe_ctx->stream_res.dsc;
1671         if (dsc)
1672                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1673
1674         snprintf(rd_buf_ptr, str_len,
1675                 "%d\n",
1676                 dsc_state.dsc_pic_height);
1677         rd_buf_ptr += str_len;
1678
1679         while (size) {
1680                 if (*pos >= rd_buf_size)
1681                         break;
1682
1683                 r = put_user(*(rd_buf + result), buf);
1684                 if (r)
1685                         return r; /* r = -EFAULT */
1686
1687                 buf += 1;
1688                 size -= 1;
1689                 *pos += 1;
1690                 result += 1;
1691         }
1692
1693         kfree(rd_buf);
1694         return result;
1695 }
1696
1697 /* function: read DSC chunk size parameter on the connector
1698  *
1699  * The read function: dp_dsc_chunk_size_read
1700  * returns dsc chunk size set in the current configuration
1701  * The value is calculated automatically by DSC code
1702  * and depends on slice parameters and bpp target rate
1703  * The return is an integer: 0 or other positive integer
1704  * If 0 then DSC is disabled.
1705  *
1706  * Access it with the following command:
1707  *
1708  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
1709  *
1710  * 0 - means that DSC is disabled
1711  */
1712 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
1713                                     size_t size, loff_t *pos)
1714 {
1715         char *rd_buf = NULL;
1716         char *rd_buf_ptr = NULL;
1717         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1718         struct display_stream_compressor *dsc;
1719         struct dcn_dsc_state dsc_state = {0};
1720         const uint32_t rd_buf_size = 100;
1721         struct pipe_ctx *pipe_ctx;
1722         ssize_t result = 0;
1723         int i, r, str_len = 30;
1724
1725         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1726
1727         if (!rd_buf)
1728                 return -ENOMEM;
1729
1730         rd_buf_ptr = rd_buf;
1731
1732         for (i = 0; i < MAX_PIPES; i++) {
1733                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1734                         if (pipe_ctx && pipe_ctx->stream &&
1735                             pipe_ctx->stream->link == aconnector->dc_link)
1736                                 break;
1737         }
1738
1739         if (!pipe_ctx)
1740                 return -ENXIO;
1741
1742         dsc = pipe_ctx->stream_res.dsc;
1743         if (dsc)
1744                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1745
1746         snprintf(rd_buf_ptr, str_len,
1747                 "%d\n",
1748                 dsc_state.dsc_chunk_size);
1749         rd_buf_ptr += str_len;
1750
1751         while (size) {
1752                 if (*pos >= rd_buf_size)
1753                         break;
1754
1755                 r = put_user(*(rd_buf + result), buf);
1756                 if (r)
1757                         return r; /* r = -EFAULT */
1758
1759                 buf += 1;
1760                 size -= 1;
1761                 *pos += 1;
1762                 result += 1;
1763         }
1764
1765         kfree(rd_buf);
1766         return result;
1767 }
1768
1769 /* function: read DSC slice bpg offset on the connector
1770  *
1771  * The read function: dp_dsc_slice_bpg_offset_read
1772  * returns dsc bpg slice offset set in the current configuration
1773  * The value is calculated automatically by DSC code
1774  * and depends on slice parameters and bpp target rate
1775  * The return is an integer: 0 or other positive integer
1776  * If 0 then DSC is disabled.
1777  *
1778  * Access it with the following command:
1779  *
1780  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
1781  *
1782  * 0 - means that DSC is disabled
1783  */
1784 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
1785                                     size_t size, loff_t *pos)
1786 {
1787         char *rd_buf = NULL;
1788         char *rd_buf_ptr = NULL;
1789         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1790         struct display_stream_compressor *dsc;
1791         struct dcn_dsc_state dsc_state = {0};
1792         const uint32_t rd_buf_size = 100;
1793         struct pipe_ctx *pipe_ctx;
1794         ssize_t result = 0;
1795         int i, r, str_len = 30;
1796
1797         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1798
1799         if (!rd_buf)
1800                 return -ENOMEM;
1801
1802         rd_buf_ptr = rd_buf;
1803
1804         for (i = 0; i < MAX_PIPES; i++) {
1805                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1806                         if (pipe_ctx && pipe_ctx->stream &&
1807                             pipe_ctx->stream->link == aconnector->dc_link)
1808                                 break;
1809         }
1810
1811         if (!pipe_ctx)
1812                 return -ENXIO;
1813
1814         dsc = pipe_ctx->stream_res.dsc;
1815         if (dsc)
1816                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1817
1818         snprintf(rd_buf_ptr, str_len,
1819                 "%d\n",
1820                 dsc_state.dsc_slice_bpg_offset);
1821         rd_buf_ptr += str_len;
1822
1823         while (size) {
1824                 if (*pos >= rd_buf_size)
1825                         break;
1826
1827                 r = put_user(*(rd_buf + result), buf);
1828                 if (r)
1829                         return r; /* r = -EFAULT */
1830
1831                 buf += 1;
1832                 size -= 1;
1833                 *pos += 1;
1834                 result += 1;
1835         }
1836
1837         kfree(rd_buf);
1838         return result;
1839 }
1840
1841 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
1842 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
1843 DEFINE_SHOW_ATTRIBUTE(output_bpc);
1844 #ifdef CONFIG_DRM_AMD_DC_HDCP
1845 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
1846 #endif
1847
1848 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
1849         .owner = THIS_MODULE,
1850         .read = dp_dsc_clock_en_read,
1851         .write = dp_dsc_clock_en_write,
1852         .llseek = default_llseek
1853 };
1854
1855 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
1856         .owner = THIS_MODULE,
1857         .read = dp_dsc_slice_width_read,
1858         .write = dp_dsc_slice_width_write,
1859         .llseek = default_llseek
1860 };
1861
1862 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
1863         .owner = THIS_MODULE,
1864         .read = dp_dsc_slice_height_read,
1865         .write = dp_dsc_slice_height_write,
1866         .llseek = default_llseek
1867 };
1868
1869 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
1870         .owner = THIS_MODULE,
1871         .read = dp_dsc_bits_per_pixel_read,
1872         .write = dp_dsc_bits_per_pixel_write,
1873         .llseek = default_llseek
1874 };
1875
1876 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
1877         .owner = THIS_MODULE,
1878         .read = dp_dsc_pic_width_read,
1879         .llseek = default_llseek
1880 };
1881
1882 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
1883         .owner = THIS_MODULE,
1884         .read = dp_dsc_pic_height_read,
1885         .llseek = default_llseek
1886 };
1887
1888 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
1889         .owner = THIS_MODULE,
1890         .read = dp_dsc_chunk_size_read,
1891         .llseek = default_llseek
1892 };
1893
1894 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
1895         .owner = THIS_MODULE,
1896         .read = dp_dsc_slice_bpg_offset_read,
1897         .llseek = default_llseek
1898 };
1899
1900 static const struct file_operations dp_link_settings_debugfs_fops = {
1901         .owner = THIS_MODULE,
1902         .read = dp_link_settings_read,
1903         .write = dp_link_settings_write,
1904         .llseek = default_llseek
1905 };
1906
1907 static const struct file_operations dp_phy_settings_debugfs_fop = {
1908         .owner = THIS_MODULE,
1909         .read = dp_phy_settings_read,
1910         .write = dp_phy_settings_write,
1911         .llseek = default_llseek
1912 };
1913
1914 static const struct file_operations dp_phy_test_pattern_fops = {
1915         .owner = THIS_MODULE,
1916         .write = dp_phy_test_pattern_debugfs_write,
1917         .llseek = default_llseek
1918 };
1919
1920 static const struct file_operations sdp_message_fops = {
1921         .owner = THIS_MODULE,
1922         .write = dp_sdp_message_debugfs_write,
1923         .llseek = default_llseek
1924 };
1925
1926 static const struct file_operations dp_dpcd_address_debugfs_fops = {
1927         .owner = THIS_MODULE,
1928         .write = dp_dpcd_address_write,
1929         .llseek = default_llseek
1930 };
1931
1932 static const struct file_operations dp_dpcd_size_debugfs_fops = {
1933         .owner = THIS_MODULE,
1934         .write = dp_dpcd_size_write,
1935         .llseek = default_llseek
1936 };
1937
1938 static const struct file_operations dp_dpcd_data_debugfs_fops = {
1939         .owner = THIS_MODULE,
1940         .read = dp_dpcd_data_read,
1941         .write = dp_dpcd_data_write,
1942         .llseek = default_llseek
1943 };
1944
1945 static const struct {
1946         char *name;
1947         const struct file_operations *fops;
1948 } dp_debugfs_entries[] = {
1949                 {"link_settings", &dp_link_settings_debugfs_fops},
1950                 {"phy_settings", &dp_phy_settings_debugfs_fop},
1951                 {"test_pattern", &dp_phy_test_pattern_fops},
1952 #ifdef CONFIG_DRM_AMD_DC_HDCP
1953                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
1954 #endif
1955                 {"sdp_message", &sdp_message_fops},
1956                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
1957                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
1958                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
1959                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
1960                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
1961                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
1962                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
1963                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
1964                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
1965                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
1966                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}
1967 };
1968
1969 #ifdef CONFIG_DRM_AMD_DC_HDCP
1970 static const struct {
1971         char *name;
1972         const struct file_operations *fops;
1973 } hdmi_debugfs_entries[] = {
1974                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
1975 };
1976 #endif
1977 /*
1978  * Force YUV420 output if available from the given mode
1979  */
1980 static int force_yuv420_output_set(void *data, u64 val)
1981 {
1982         struct amdgpu_dm_connector *connector = data;
1983
1984         connector->force_yuv420_output = (bool)val;
1985
1986         return 0;
1987 }
1988
1989 /*
1990  * Check if YUV420 is forced when available from the given mode
1991  */
1992 static int force_yuv420_output_get(void *data, u64 *val)
1993 {
1994         struct amdgpu_dm_connector *connector = data;
1995
1996         *val = connector->force_yuv420_output;
1997
1998         return 0;
1999 }
2000
2001 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2002                          force_yuv420_output_set, "%llu\n");
2003
2004 /*
2005  *  Read PSR state
2006  */
2007 static int psr_get(void *data, u64 *val)
2008 {
2009         struct amdgpu_dm_connector *connector = data;
2010         struct dc_link *link = connector->dc_link;
2011         uint32_t psr_state = 0;
2012
2013         dc_link_get_psr_state(link, &psr_state);
2014
2015         *val = psr_state;
2016
2017         return 0;
2018 }
2019
2020
2021 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2022
2023 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2024 {
2025         int i;
2026         struct dentry *dir = connector->base.debugfs_entry;
2027
2028         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2029             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2030                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2031                         debugfs_create_file(dp_debugfs_entries[i].name,
2032                                             0644, dir, connector,
2033                                             dp_debugfs_entries[i].fops);
2034                 }
2035         }
2036         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2037                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2038
2039         debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector,
2040                                    &force_yuv420_output_fops);
2041
2042         debugfs_create_file("output_bpc", 0644, dir, connector,
2043                             &output_bpc_fops);
2044
2045         connector->debugfs_dpcd_address = 0;
2046         connector->debugfs_dpcd_size = 0;
2047
2048 #ifdef CONFIG_DRM_AMD_DC_HDCP
2049         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2050                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2051                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2052                                             0644, dir, connector,
2053                                             hdmi_debugfs_entries[i].fops);
2054                 }
2055         }
2056 #endif
2057 }
2058
2059 /*
2060  * Writes DTN log state to the user supplied buffer.
2061  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
2062  */
2063 static ssize_t dtn_log_read(
2064         struct file *f,
2065         char __user *buf,
2066         size_t size,
2067         loff_t *pos)
2068 {
2069         struct amdgpu_device *adev = file_inode(f)->i_private;
2070         struct dc *dc = adev->dm.dc;
2071         struct dc_log_buffer_ctx log_ctx = { 0 };
2072         ssize_t result = 0;
2073
2074         if (!buf || !size)
2075                 return -EINVAL;
2076
2077         if (!dc->hwss.log_hw_state)
2078                 return 0;
2079
2080         dc->hwss.log_hw_state(dc, &log_ctx);
2081
2082         if (*pos < log_ctx.pos) {
2083                 size_t to_copy = log_ctx.pos - *pos;
2084
2085                 to_copy = min(to_copy, size);
2086
2087                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
2088                         *pos += to_copy;
2089                         result = to_copy;
2090                 }
2091         }
2092
2093         kfree(log_ctx.buf);
2094
2095         return result;
2096 }
2097
2098 /*
2099  * Writes DTN log state to dmesg when triggered via a write.
2100  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
2101  */
2102 static ssize_t dtn_log_write(
2103         struct file *f,
2104         const char __user *buf,
2105         size_t size,
2106         loff_t *pos)
2107 {
2108         struct amdgpu_device *adev = file_inode(f)->i_private;
2109         struct dc *dc = adev->dm.dc;
2110
2111         /* Write triggers log output via dmesg. */
2112         if (size == 0)
2113                 return 0;
2114
2115         if (dc->hwss.log_hw_state)
2116                 dc->hwss.log_hw_state(dc, NULL);
2117
2118         return size;
2119 }
2120
2121 /*
2122  * Backlight at this moment.  Read only.
2123  * As written to display, taking ABM and backlight lut into account.
2124  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2125  */
2126 static int current_backlight_read(struct seq_file *m, void *data)
2127 {
2128         struct drm_info_node *node = (struct drm_info_node *)m->private;
2129         struct drm_device *dev = node->minor->dev;
2130         struct amdgpu_device *adev = drm_to_adev(dev);
2131         struct amdgpu_display_manager *dm = &adev->dm;
2132
2133         unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link);
2134
2135         seq_printf(m, "0x%x\n", backlight);
2136         return 0;
2137 }
2138
2139 /*
2140  * Backlight value that is being approached.  Read only.
2141  * As written to display, taking ABM and backlight lut into account.
2142  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2143  */
2144 static int target_backlight_read(struct seq_file *m, void *data)
2145 {
2146         struct drm_info_node *node = (struct drm_info_node *)m->private;
2147         struct drm_device *dev = node->minor->dev;
2148         struct amdgpu_device *adev = drm_to_adev(dev);
2149         struct amdgpu_display_manager *dm = &adev->dm;
2150
2151         unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link);
2152
2153         seq_printf(m, "0x%x\n", backlight);
2154         return 0;
2155 }
2156
2157 static int mst_topo(struct seq_file *m, void *unused)
2158 {
2159         struct drm_info_node *node = (struct drm_info_node *)m->private;
2160         struct drm_device *dev = node->minor->dev;
2161         struct drm_connector *connector;
2162         struct drm_connector_list_iter conn_iter;
2163         struct amdgpu_dm_connector *aconnector;
2164
2165         drm_connector_list_iter_begin(dev, &conn_iter);
2166         drm_for_each_connector_iter(connector, &conn_iter) {
2167                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
2168                         continue;
2169
2170                 aconnector = to_amdgpu_dm_connector(connector);
2171
2172                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
2173                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
2174         }
2175         drm_connector_list_iter_end(&conn_iter);
2176
2177         return 0;
2178 }
2179
2180 static const struct drm_info_list amdgpu_dm_debugfs_list[] = {
2181         {"amdgpu_current_backlight_pwm", &current_backlight_read},
2182         {"amdgpu_target_backlight_pwm", &target_backlight_read},
2183         {"amdgpu_mst_topology", &mst_topo},
2184 };
2185
2186 /*
2187  * Sets the force_timing_sync debug optino from the given string.
2188  * All connected displays will be force synchronized immediately.
2189  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
2190  */
2191 static int force_timing_sync_set(void *data, u64 val)
2192 {
2193         struct amdgpu_device *adev = data;
2194
2195         adev->dm.force_timing_sync = (bool)val;
2196
2197         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
2198
2199         return 0;
2200 }
2201
2202 /*
2203  * Gets the force_timing_sync debug option value into the given buffer.
2204  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
2205  */
2206 static int force_timing_sync_get(void *data, u64 *val)
2207 {
2208         struct amdgpu_device *adev = data;
2209
2210         *val = adev->dm.force_timing_sync;
2211
2212         return 0;
2213 }
2214
2215 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
2216                          force_timing_sync_set, "%llu\n");
2217
2218 /*
2219  * Sets the DC visual confirm debug option from the given string.
2220  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
2221  */
2222 static int visual_confirm_set(void *data, u64 val)
2223 {
2224         struct amdgpu_device *adev = data;
2225
2226         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
2227
2228         return 0;
2229 }
2230
2231 /*
2232  * Reads the DC visual confirm debug option value into the given buffer.
2233  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
2234  */
2235 static int visual_confirm_get(void *data, u64 *val)
2236 {
2237         struct amdgpu_device *adev = data;
2238
2239         *val = adev->dm.dc->debug.visual_confirm;
2240
2241         return 0;
2242 }
2243
2244 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
2245                          visual_confirm_set, "%llu\n");
2246
2247 int dtn_debugfs_init(struct amdgpu_device *adev)
2248 {
2249         static const struct file_operations dtn_log_fops = {
2250                 .owner = THIS_MODULE,
2251                 .read = dtn_log_read,
2252                 .write = dtn_log_write,
2253                 .llseek = default_llseek
2254         };
2255
2256         struct drm_minor *minor = adev_to_drm(adev)->primary;
2257         struct dentry *root = minor->debugfs_root;
2258         int ret;
2259
2260         ret = amdgpu_debugfs_add_files(adev, amdgpu_dm_debugfs_list,
2261                                 ARRAY_SIZE(amdgpu_dm_debugfs_list));
2262         if (ret)
2263                 return ret;
2264
2265         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
2266                             &dtn_log_fops);
2267
2268         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
2269                                    &visual_confirm_fops);
2270
2271         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
2272                                    adev, &dmub_tracebuffer_fops);
2273
2274         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
2275                                    adev, &dmub_fw_state_fops);
2276
2277         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
2278                                    adev, &force_timing_sync_ops);
2279
2280         return 0;
2281 }