drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string_helpers.h>
  27 #include <linux/uaccess.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_debugfs.h"
  33 #include "dm_helpers.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "resource.h"
  36 #include "dsc.h"
  37 #include "dc_link_dp.h"
  38 #include "link_hwss.h"
  39 #include "dc/dc_dmub_srv.h"
  40
  41 struct dmub_debugfs_trace_header {
  42         uint32_t entry_count;
  43         uint32_t reserved[3];
  44 };
  45
  46 struct dmub_debugfs_trace_entry {
  47         uint32_t trace_code;
  48         uint32_t tick_count;
  49         uint32_t param0;
  50         uint32_t param1;
  51 };
  52
  53 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  54  *
  55  * Function takes in attributes passed to debugfs write entry
  56  * and writes into param array.
  57  * The user passes max_param_num to identify maximum number of
  58  * parameters that could be parsed.
  59  *
  60  */
  61 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  62                                           long *param, const char __user *buf,
  63                                           int max_param_num,
  64                                           uint8_t *param_nums)
  65 {
  66         char *wr_buf_ptr = NULL;
  67         uint32_t wr_buf_count = 0;
  68         int r;
  69         char *sub_str = NULL;
  70         const char delimiter[3] = {' ', '\n', '\0'};
  71         uint8_t param_index = 0;
  72
  73         *param_nums = 0;
  74
  75         wr_buf_ptr = wr_buf;
  76
  77         /* r is bytes not be copied */
  78         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  79                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  80                 return -EFAULT;
  81         }
  82
  83         /* check number of parameters. isspace could not differ space and \n */
  84         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  85                 /* skip space*/
  86                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  87                         wr_buf_ptr++;
  88                         wr_buf_count++;
  89                         }
  90
  91                 if (wr_buf_count == wr_buf_size)
  92                         break;
  93
  94                 /* skip non-space*/
  95                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
  96                         wr_buf_ptr++;
  97                         wr_buf_count++;
  98                 }
  99
 100                 (*param_nums)++;
 101
 102                 if (wr_buf_count == wr_buf_size)
 103                         break;
 104         }
 105
 106         if (*param_nums > max_param_num)
 107                 *param_nums = max_param_num;
 108
 109         wr_buf_ptr = wr_buf; /* reset buf pointer */
 110         wr_buf_count = 0; /* number of char already checked */
 111
 112         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 113                 wr_buf_ptr++;
 114                 wr_buf_count++;
 115         }
 116
 117         while (param_index < *param_nums) {
 118                 /* after strsep, wr_buf_ptr will be moved to after space */
 119                 sub_str = strsep(&wr_buf_ptr, delimiter);
 120
 121                 r = kstrtol(sub_str, 16, &(param[param_index]));
 122
 123                 if (r)
 124                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 125
 126                 param_index++;
 127         }
 128
 129         return 0;
 130 }
 131
 132 /* function description
 133  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 134  *
 135  * valid lane count value: 1, 2, 4
 136  * valid link rate value:
 137  * 06h = 1.62Gbps per lane
 138  * 0Ah = 2.7Gbps per lane
 139  * 0Ch = 3.24Gbps per lane
 140  * 14h = 5.4Gbps per lane
 141  * 1Eh = 8.1Gbps per lane
 142  *
 143  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 144  *
 145  * --- to get dp configuration
 146  *
 147  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 148  *
 149  * It will list current, verified, reported, preferred dp configuration.
 150  * current -- for current video mode
 151  * verified --- maximum configuration which pass link training
 152  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 153  * preferred --- user force settings
 154  *
 155  * --- set (or force) dp configuration
 156  *
 157  * echo <lane_count>  <link_rate> > link_settings
 158  *
 159  * for example, to force to  2 lane, 2.7GHz,
 160  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 161  *
 162  * spread_spectrum could not be changed dynamically.
 163  *
 164  * in case invalid lane count, link rate are force, no hw programming will be
 165  * done. please check link settings after force operation to see if HW get
 166  * programming.
 167  *
 168  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 169  *
 170  * check current and preferred settings.
 171  *
 172  */
 173 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 174                                  size_t size, loff_t *pos)
 175 {
 176         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 177         struct dc_link *link = connector->dc_link;
 178         char *rd_buf = NULL;
 179         char *rd_buf_ptr = NULL;
 180         const uint32_t rd_buf_size = 100;
 181         uint32_t result = 0;
 182         uint8_t str_len = 0;
 183         int r;
 184
 185         if (*pos & 3 || size & 3)
 186                 return -EINVAL;
 187
 188         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 189         if (!rd_buf)
 190                 return 0;
 191
 192         rd_buf_ptr = rd_buf;
 193
 194         str_len = strlen("Current:  %d  0x%x  %d  ");
 195         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 196                         link->cur_link_settings.lane_count,
 197                         link->cur_link_settings.link_rate,
 198                         link->cur_link_settings.link_spread);
 199         rd_buf_ptr += str_len;
 200
 201         str_len = strlen("Verified:  %d  0x%x  %d  ");
 202         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 203                         link->verified_link_cap.lane_count,
 204                         link->verified_link_cap.link_rate,
 205                         link->verified_link_cap.link_spread);
 206         rd_buf_ptr += str_len;
 207
 208         str_len = strlen("Reported:  %d  0x%x  %d  ");
 209         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 210                         link->reported_link_cap.lane_count,
 211                         link->reported_link_cap.link_rate,
 212                         link->reported_link_cap.link_spread);
 213         rd_buf_ptr += str_len;
 214
 215         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 216         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 217                         link->preferred_link_setting.lane_count,
 218                         link->preferred_link_setting.link_rate,
 219                         link->preferred_link_setting.link_spread);
 220
 221         while (size) {
 222                 if (*pos >= rd_buf_size)
 223                         break;
 224
 225                 r = put_user(*(rd_buf + result), buf);
 226                 if (r) {
 227                         kfree(rd_buf);
 228                         return r; /* r = -EFAULT */
 229                 }
 230
 231                 buf += 1;
 232                 size -= 1;
 233                 *pos += 1;
 234                 result += 1;
 235         }
 236
 237         kfree(rd_buf);
 238         return result;
 239 }
 240
 241 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 242                                  size_t size, loff_t *pos)
 243 {
 244         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 245         struct dc_link *link = connector->dc_link;
 246         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 247         struct dc *dc = (struct dc *)link->dc;
 248         struct dc_link_settings prefer_link_settings;
 249         char *wr_buf = NULL;
 250         const uint32_t wr_buf_size = 40;
 251         /* 0: lane_count; 1: link_rate */
 252         int max_param_num = 2;
 253         uint8_t param_nums = 0;
 254         long param[2];
 255         bool valid_input = true;
 256
 257         if (size == 0)
 258                 return -EINVAL;
 259
 260         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 261         if (!wr_buf)
 262                 return -ENOSPC;
 263
 264         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 265                                            (long *)param, buf,
 266                                            max_param_num,
 267                                            &param_nums)) {
 268                 kfree(wr_buf);
 269                 return -EINVAL;
 270         }
 271
 272         if (param_nums <= 0) {
 273                 kfree(wr_buf);
 274                 DRM_DEBUG_DRIVER("user data not be read\n");
 275                 return -EINVAL;
 276         }
 277
 278         switch (param[0]) {
 279         case LANE_COUNT_ONE:
 280         case LANE_COUNT_TWO:
 281         case LANE_COUNT_FOUR:
 282                 break;
 283         default:
 284                 valid_input = false;
 285                 break;
 286         }
 287
 288         switch (param[1]) {
 289         case LINK_RATE_LOW:
 290         case LINK_RATE_HIGH:
 291         case LINK_RATE_RBR2:
 292         case LINK_RATE_HIGH2:
 293         case LINK_RATE_HIGH3:
 294         case LINK_RATE_UHBR10:
 295                 break;
 296         default:
 297                 valid_input = false;
 298                 break;
 299         }
 300
 301         if (!valid_input) {
 302                 kfree(wr_buf);
 303                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 304                 mutex_lock(&adev->dm.dc_lock);
 305                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 306                 mutex_unlock(&adev->dm.dc_lock);
 307                 return size;
 308         }
 309
 310         /* save user force lane_count, link_rate to preferred settings
 311          * spread spectrum will not be changed
 312          */
 313         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 314         prefer_link_settings.use_link_rate_set = false;
 315         prefer_link_settings.lane_count = param[0];
 316         prefer_link_settings.link_rate = param[1];
 317
 318         mutex_lock(&adev->dm.dc_lock);
 319         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 320         mutex_unlock(&adev->dm.dc_lock);
 321
 322         kfree(wr_buf);
 323         return size;
 324 }
 325
 326 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 327  * post-cursor2 (defined by VESA DP specification)
 328  *
 329  * valid values
 330  * voltage swing: 0,1,2,3
 331  * pre-emphasis : 0,1,2,3
 332  * post cursor2 : 0,1,2,3
 333  *
 334  *
 335  * how to use this debugfs
 336  *
 337  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 338  *
 339  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 340  *
 341  * To figure out which DP-x is the display for DP to be check,
 342  * cd DP-x
 343  * ls -ll
 344  * There should be debugfs file, like link_settings, phy_settings.
 345  * cat link_settings
 346  * from lane_count, link_rate to figure which DP-x is for display to be worked
 347  * on
 348  *
 349  * To get current DP PHY settings,
 350  * cat phy_settings
 351  *
 352  * To change DP PHY settings,
 353  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 354  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 355  * 0,
 356  * echo 2 3 0 > phy_settings
 357  *
 358  * To check if change be applied, get current phy settings by
 359  * cat phy_settings
 360  *
 361  * In case invalid values are set by user, like
 362  * echo 1 4 0 > phy_settings
 363  *
 364  * HW will NOT be programmed by these settings.
 365  * cat phy_settings will show the previous valid settings.
 366  */
 367 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 368                                  size_t size, loff_t *pos)
 369 {
 370         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 371         struct dc_link *link = connector->dc_link;
 372         char *rd_buf = NULL;
 373         const uint32_t rd_buf_size = 20;
 374         uint32_t result = 0;
 375         int r;
 376
 377         if (*pos & 3 || size & 3)
 378                 return -EINVAL;
 379
 380         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 381         if (!rd_buf)
 382                 return -EINVAL;
 383
 384         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 385                         link->cur_lane_setting[0].VOLTAGE_SWING,
 386                         link->cur_lane_setting[0].PRE_EMPHASIS,
 387                         link->cur_lane_setting[0].POST_CURSOR2);
 388
 389         while (size) {
 390                 if (*pos >= rd_buf_size)
 391                         break;
 392
 393                 r = put_user((*(rd_buf + result)), buf);
 394                 if (r) {
 395                         kfree(rd_buf);
 396                         return r; /* r = -EFAULT */
 397                 }
 398
 399                 buf += 1;
 400                 size -= 1;
 401                 *pos += 1;
 402                 result += 1;
 403         }
 404
 405         kfree(rd_buf);
 406         return result;
 407 }
 408
 409 static int dp_lttpr_status_show(struct seq_file *m, void *d)
 410 {
 411         char *data;
 412         struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
 413         struct dc_link *link = connector->dc_link;
 414         uint32_t read_size = 1;
 415         uint8_t repeater_count = 0;
 416
 417         data = kzalloc(read_size, GFP_KERNEL);
 418         if (!data)
 419                 return 0;
 420
 421         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
 422
 423         switch ((uint8_t)*data) {
 424         case 0x80:
 425                 repeater_count = 1;
 426                 break;
 427         case 0x40:
 428                 repeater_count = 2;
 429                 break;
 430         case 0x20:
 431                 repeater_count = 3;
 432                 break;
 433         case 0x10:
 434                 repeater_count = 4;
 435                 break;
 436         case 0x8:
 437                 repeater_count = 5;
 438                 break;
 439         case 0x4:
 440                 repeater_count = 6;
 441                 break;
 442         case 0x2:
 443                 repeater_count = 7;
 444                 break;
 445         case 0x1:
 446                 repeater_count = 8;
 447                 break;
 448         case 0x0:
 449                 repeater_count = 0;
 450                 break;
 451         default:
 452                 repeater_count = (uint8_t)*data;
 453                 break;
 454         }
 455
 456         seq_printf(m, "phy repeater count: %d\n", repeater_count);
 457
 458         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
 459
 460         if ((uint8_t)*data == 0x55)
 461                 seq_printf(m, "phy repeater mode: transparent\n");
 462         else if ((uint8_t)*data == 0xAA)
 463                 seq_printf(m, "phy repeater mode: non-transparent\n");
 464         else if ((uint8_t)*data == 0x00)
 465                 seq_printf(m, "phy repeater mode: non lttpr\n");
 466         else
 467                 seq_printf(m, "phy repeater mode: read error\n");
 468
 469         kfree(data);
 470         return 0;
 471 }
 472
 473 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 474                                  size_t size, loff_t *pos)
 475 {
 476         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 477         struct dc_link *link = connector->dc_link;
 478         struct dc *dc = (struct dc *)link->dc;
 479         char *wr_buf = NULL;
 480         uint32_t wr_buf_size = 40;
 481         long param[3];
 482         bool use_prefer_link_setting;
 483         struct link_training_settings link_lane_settings;
 484         int max_param_num = 3;
 485         uint8_t param_nums = 0;
 486         int r = 0;
 487
 488
 489         if (size == 0)
 490                 return -EINVAL;
 491
 492         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 493         if (!wr_buf)
 494                 return -ENOSPC;
 495
 496         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 497                                            (long *)param, buf,
 498                                            max_param_num,
 499                                            &param_nums)) {
 500                 kfree(wr_buf);
 501                 return -EINVAL;
 502         }
 503
 504         if (param_nums <= 0) {
 505                 kfree(wr_buf);
 506                 DRM_DEBUG_DRIVER("user data not be read\n");
 507                 return -EINVAL;
 508         }
 509
 510         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 511                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 512                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 513                 kfree(wr_buf);
 514                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 515                 return size;
 516         }
 517
 518         /* get link settings: lane count, link rate */
 519         use_prefer_link_setting =
 520                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 521                 (link->test_pattern_enabled));
 522
 523         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 524
 525         if (use_prefer_link_setting) {
 526                 link_lane_settings.link_settings.lane_count =
 527                                 link->preferred_link_setting.lane_count;
 528                 link_lane_settings.link_settings.link_rate =
 529                                 link->preferred_link_setting.link_rate;
 530                 link_lane_settings.link_settings.link_spread =
 531                                 link->preferred_link_setting.link_spread;
 532         } else {
 533                 link_lane_settings.link_settings.lane_count =
 534                                 link->cur_link_settings.lane_count;
 535                 link_lane_settings.link_settings.link_rate =
 536                                 link->cur_link_settings.link_rate;
 537                 link_lane_settings.link_settings.link_spread =
 538                                 link->cur_link_settings.link_spread;
 539         }
 540
 541         /* apply phy settings from user */
 542         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 543                 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 544                                 (enum dc_voltage_swing) (param[0]);
 545                 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 546                                 (enum dc_pre_emphasis) (param[1]);
 547                 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 548                                 (enum dc_post_cursor2) (param[2]);
 549         }
 550
 551         /* program ASIC registers and DPCD registers */
 552         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 553
 554         kfree(wr_buf);
 555         return size;
 556 }
 557
 558 /* function description
 559  *
 560  * set PHY layer or Link layer test pattern
 561  * PHY test pattern is used for PHY SI check.
 562  * Link layer test will not affect PHY SI.
 563  *
 564  * Reset Test Pattern:
 565  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 566  *
 567  * PHY test pattern supported:
 568  * 1 = DP_TEST_PATTERN_D102
 569  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 570  * 3 = DP_TEST_PATTERN_PRBS7
 571  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 572  * 5 = DP_TEST_PATTERN_CP2520_1
 573  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 574  * 7 = DP_TEST_PATTERN_CP2520_3
 575  *
 576  * DP PHY Link Training Patterns
 577  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 578  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 579  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 580  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 581  *
 582  * DP Link Layer Test pattern
 583  * c = DP_TEST_PATTERN_COLOR_SQUARES
 584  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 585  * e = DP_TEST_PATTERN_VERTICAL_BARS
 586  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 587  * 10= DP_TEST_PATTERN_COLOR_RAMP
 588  *
 589  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 590  *
 591  * --- set test pattern
 592  * echo <test pattern #> > test_pattern
 593  *
 594  * If test pattern # is not supported, NO HW programming will be done.
 595  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 596  * for the user pattern. input 10 bytes data are separated by space
 597  *
 598  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 599  *
 600  * --- reset test pattern
 601  * echo 0 > test_pattern
 602  *
 603  * --- HPD detection is disabled when set PHY test pattern
 604  *
 605  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 606  * is disable. User could unplug DP display from DP connected and plug scope to
 607  * check test pattern PHY SI.
 608  * If there is need unplug scope and plug DP display back, do steps below:
 609  * echo 0 > phy_test_pattern
 610  * unplug scope
 611  * plug DP display.
 612  *
 613  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 614  * driver could detect "unplug scope" and "plug DP display"
 615  */
 616 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 617                                  size_t size, loff_t *pos)
 618 {
 619         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 620         struct dc_link *link = connector->dc_link;
 621         char *wr_buf = NULL;
 622         uint32_t wr_buf_size = 100;
 623         long param[11] = {0x0};
 624         int max_param_num = 11;
 625         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 626         bool disable_hpd = false;
 627         bool valid_test_pattern = false;
 628         uint8_t param_nums = 0;
 629         /* init with default 80bit custom pattern */
 630         uint8_t custom_pattern[10] = {
 631                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 632                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 633                         };
 634         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 635                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 636         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 637                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 638         struct link_training_settings link_training_settings;
 639         int i;
 640
 641         if (size == 0)
 642                 return -EINVAL;
 643
 644         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 645         if (!wr_buf)
 646                 return -ENOSPC;
 647
 648         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 649                                            (long *)param, buf,
 650                                            max_param_num,
 651                                            &param_nums)) {
 652                 kfree(wr_buf);
 653                 return -EINVAL;
 654         }
 655
 656         if (param_nums <= 0) {
 657                 kfree(wr_buf);
 658                 DRM_DEBUG_DRIVER("user data not be read\n");
 659                 return -EINVAL;
 660         }
 661
 662
 663         test_pattern = param[0];
 664
 665         switch (test_pattern) {
 666         case DP_TEST_PATTERN_VIDEO_MODE:
 667         case DP_TEST_PATTERN_COLOR_SQUARES:
 668         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 669         case DP_TEST_PATTERN_VERTICAL_BARS:
 670         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 671         case DP_TEST_PATTERN_COLOR_RAMP:
 672                 valid_test_pattern = true;
 673                 break;
 674
 675         case DP_TEST_PATTERN_D102:
 676         case DP_TEST_PATTERN_SYMBOL_ERROR:
 677         case DP_TEST_PATTERN_PRBS7:
 678         case DP_TEST_PATTERN_80BIT_CUSTOM:
 679         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 680         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 681                 disable_hpd = true;
 682                 valid_test_pattern = true;
 683                 break;
 684
 685         default:
 686                 valid_test_pattern = false;
 687                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 688                 break;
 689         }
 690
 691         if (!valid_test_pattern) {
 692                 kfree(wr_buf);
 693                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 694                 return size;
 695         }
 696
 697         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 698                 for (i = 0; i < 10; i++) {
 699                         if ((uint8_t) param[i + 1] != 0x0)
 700                                 break;
 701                 }
 702
 703                 if (i < 10) {
 704                         /* not use default value */
 705                         for (i = 0; i < 10; i++)
 706                                 custom_pattern[i] = (uint8_t) param[i + 1];
 707                 }
 708         }
 709
 710         /* Usage: set DP physical test pattern using debugfs with normal DP
 711          * panel. Then plug out DP panel and connect a scope to measure
 712          * For normal video mode and test pattern generated from CRCT,
 713          * they are visibile to user. So do not disable HPD.
 714          * Video Mode is also set to clear the test pattern, so enable HPD
 715          * because it might have been disabled after a test pattern was set.
 716          * AUX depends on HPD * sequence dependent, do not move!
 717          */
 718         if (!disable_hpd)
 719                 dc_link_enable_hpd(link);
 720
 721         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 722         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 723         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 724
 725         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 726         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 727         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 728
 729         link_training_settings.link_settings = cur_link_settings;
 730
 731
 732         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 733                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 734                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 735                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 736                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 737                         link_training_settings.link_settings = prefer_link_settings;
 738         }
 739
 740         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 741                 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 742
 743         dc_link_set_test_pattern(
 744                 link,
 745                 test_pattern,
 746                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 747                 &link_training_settings,
 748                 custom_pattern,
 749                 10);
 750
 751         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 752          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 753          * Need disable interrupt to avoid SW driver disable DP output. This is
 754          * done after the test pattern is set.
 755          */
 756         if (valid_test_pattern && disable_hpd)
 757                 dc_link_disable_hpd(link);
 758
 759         kfree(wr_buf);
 760
 761         return size;
 762 }
 763
 764 /*
 765  * Returns the DMCUB tracebuffer contents.
 766  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 767  */
 768 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 769 {
 770         struct amdgpu_device *adev = m->private;
 771         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 772         struct dmub_debugfs_trace_entry *entries;
 773         uint8_t *tbuf_base;
 774         uint32_t tbuf_size, max_entries, num_entries, i;
 775
 776         if (!fb_info)
 777                 return 0;
 778
 779         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 780         if (!tbuf_base)
 781                 return 0;
 782
 783         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 784         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 785                       sizeof(struct dmub_debugfs_trace_entry);
 786
 787         num_entries =
 788                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 789
 790         num_entries = min(num_entries, max_entries);
 791
 792         entries = (struct dmub_debugfs_trace_entry
 793                            *)(tbuf_base +
 794                               sizeof(struct dmub_debugfs_trace_header));
 795
 796         for (i = 0; i < num_entries; ++i) {
 797                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 798
 799                 seq_printf(m,
 800                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 801                            entry->trace_code, entry->tick_count, entry->param0,
 802                            entry->param1);
 803         }
 804
 805         return 0;
 806 }
 807
 808 /*
 809  * Returns the DMCUB firmware state contents.
 810  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 811  */
 812 static int dmub_fw_state_show(struct seq_file *m, void *data)
 813 {
 814         struct amdgpu_device *adev = m->private;
 815         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 816         uint8_t *state_base;
 817         uint32_t state_size;
 818
 819         if (!fb_info)
 820                 return 0;
 821
 822         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 823         if (!state_base)
 824                 return 0;
 825
 826         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 827
 828         return seq_write(m, state_base, state_size);
 829 }
 830
 831 /* psr_capability_show() - show eDP panel PSR capability
 832  *
 833  * The read function: sink_psr_capability_show
 834  * Shows if sink has PSR capability or not.
 835  * If yes - the PSR version is appended
 836  *
 837  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 838  *
 839  * Expected output:
 840  * "Sink support: no\n" - if panel doesn't support PSR
 841  * "Sink support: yes [0x01]\n" - if panel supports PSR1
 842  * "Driver support: no\n" - if driver doesn't support PSR
 843  * "Driver support: yes [0x01]\n" - if driver supports PSR1
 844  */
 845 static int psr_capability_show(struct seq_file *m, void *data)
 846 {
 847         struct drm_connector *connector = m->private;
 848         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 849         struct dc_link *link = aconnector->dc_link;
 850
 851         if (!link)
 852                 return -ENODEV;
 853
 854         if (link->type == dc_connection_none)
 855                 return -ENODEV;
 856
 857         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 858                 return -ENODEV;
 859
 860         seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
 861         if (link->dpcd_caps.psr_info.psr_version)
 862                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
 863         seq_puts(m, "\n");
 864
 865         seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
 866         if (link->psr_settings.psr_version)
 867                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
 868         seq_puts(m, "\n");
 869
 870         return 0;
 871 }
 872
 873 /*
 874  * Returns the current bpc for the crtc.
 875  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
 876  */
 877 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
 878 {
 879         struct drm_crtc *crtc = m->private;
 880         struct drm_device *dev = crtc->dev;
 881         struct dm_crtc_state *dm_crtc_state = NULL;
 882         int res = -ENODEV;
 883         unsigned int bpc;
 884
 885         mutex_lock(&dev->mode_config.mutex);
 886         drm_modeset_lock(&crtc->mutex, NULL);
 887         if (crtc->state == NULL)
 888                 goto unlock;
 889
 890         dm_crtc_state = to_dm_crtc_state(crtc->state);
 891         if (dm_crtc_state->stream == NULL)
 892                 goto unlock;
 893
 894         switch (dm_crtc_state->stream->timing.display_color_depth) {
 895         case COLOR_DEPTH_666:
 896                 bpc = 6;
 897                 break;
 898         case COLOR_DEPTH_888:
 899                 bpc = 8;
 900                 break;
 901         case COLOR_DEPTH_101010:
 902                 bpc = 10;
 903                 break;
 904         case COLOR_DEPTH_121212:
 905                 bpc = 12;
 906                 break;
 907         case COLOR_DEPTH_161616:
 908                 bpc = 16;
 909                 break;
 910         default:
 911                 goto unlock;
 912         }
 913
 914         seq_printf(m, "Current: %u\n", bpc);
 915         res = 0;
 916
 917 unlock:
 918         drm_modeset_unlock(&crtc->mutex);
 919         mutex_unlock(&dev->mode_config.mutex);
 920
 921         return res;
 922 }
 923 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
 924
 925 /*
 926  * Example usage:
 927  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 928  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 929  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 930  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 931  */
 932 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 933                                  size_t size, loff_t *pos)
 934 {
 935         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 936         char *wr_buf = NULL;
 937         uint32_t wr_buf_size = 42;
 938         int max_param_num = 1;
 939         long param;
 940         uint8_t param_nums = 0;
 941
 942         if (size == 0)
 943                 return -EINVAL;
 944
 945         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 946
 947         if (!wr_buf) {
 948                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 949                 return -ENOSPC;
 950         }
 951
 952         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 953                                            &param, buf,
 954                                            max_param_num,
 955                                            &param_nums)) {
 956                 kfree(wr_buf);
 957                 return -EINVAL;
 958         }
 959
 960         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 961
 962         kfree(wr_buf);
 963         return 0;
 964 }
 965
 966 #ifdef CONFIG_DRM_AMD_DC_HDCP
 967 /*
 968  * Returns the HDCP capability of the Display (1.4 for now).
 969  *
 970  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 971  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 972  *
 973  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 974  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 975  */
 976 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 977 {
 978         struct drm_connector *connector = m->private;
 979         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 980         bool hdcp_cap, hdcp2_cap;
 981
 982         if (connector->status != connector_status_connected)
 983                 return -ENODEV;
 984
 985         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 986
 987         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 988         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 989
 990
 991         if (hdcp_cap)
 992                 seq_printf(m, "%s ", "HDCP1.4");
 993         if (hdcp2_cap)
 994                 seq_printf(m, "%s ", "HDCP2.2");
 995
 996         if (!hdcp_cap && !hdcp2_cap)
 997                 seq_printf(m, "%s ", "None");
 998
 999         seq_puts(m, "\n");
1000
1001         return 0;
1002 }
1003 #endif
1004
1005 /*
1006  * Returns whether the connected display is internal and not hotpluggable.
1007  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1008  */
1009 static int internal_display_show(struct seq_file *m, void *data)
1010 {
1011         struct drm_connector *connector = m->private;
1012         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1013         struct dc_link *link = aconnector->dc_link;
1014
1015         seq_printf(m, "Internal: %u\n", link->is_internal_display);
1016
1017         return 0;
1018 }
1019
1020 /* function description
1021  *
1022  * generic SDP message access for testing
1023  *
1024  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1025  *
1026  * SDP header
1027  * Hb0 : Secondary-Data Packet ID
1028  * Hb1 : Secondary-Data Packet type
1029  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1030  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1031  *
1032  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1033  */
1034 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1035                                  size_t size, loff_t *pos)
1036 {
1037         int r;
1038         uint8_t data[36];
1039         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1040         struct dm_crtc_state *acrtc_state;
1041         uint32_t write_size = 36;
1042
1043         if (connector->base.status != connector_status_connected)
1044                 return -ENODEV;
1045
1046         if (size == 0)
1047                 return 0;
1048
1049         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1050
1051         r = copy_from_user(data, buf, write_size);
1052
1053         write_size -= r;
1054
1055         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1056
1057         return write_size;
1058 }
1059
1060 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1061                                  size_t size, loff_t *pos)
1062 {
1063         int r;
1064         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1065
1066         if (size < sizeof(connector->debugfs_dpcd_address))
1067                 return -EINVAL;
1068
1069         r = copy_from_user(&connector->debugfs_dpcd_address,
1070                         buf, sizeof(connector->debugfs_dpcd_address));
1071
1072         return size - r;
1073 }
1074
1075 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1076                                  size_t size, loff_t *pos)
1077 {
1078         int r;
1079         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1080
1081         if (size < sizeof(connector->debugfs_dpcd_size))
1082                 return -EINVAL;
1083
1084         r = copy_from_user(&connector->debugfs_dpcd_size,
1085                         buf, sizeof(connector->debugfs_dpcd_size));
1086
1087         if (connector->debugfs_dpcd_size > 256)
1088                 connector->debugfs_dpcd_size = 0;
1089
1090         return size - r;
1091 }
1092
1093 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1094                                  size_t size, loff_t *pos)
1095 {
1096         int r;
1097         char *data;
1098         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1099         struct dc_link *link = connector->dc_link;
1100         uint32_t write_size = connector->debugfs_dpcd_size;
1101
1102         if (!write_size || size < write_size)
1103                 return -EINVAL;
1104
1105         data = kzalloc(write_size, GFP_KERNEL);
1106         if (!data)
1107                 return 0;
1108
1109         r = copy_from_user(data, buf, write_size);
1110
1111         dm_helpers_dp_write_dpcd(link->ctx, link,
1112                         connector->debugfs_dpcd_address, data, write_size - r);
1113         kfree(data);
1114         return write_size - r;
1115 }
1116
1117 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1118                                  size_t size, loff_t *pos)
1119 {
1120         int r;
1121         char *data;
1122         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1123         struct dc_link *link = connector->dc_link;
1124         uint32_t read_size = connector->debugfs_dpcd_size;
1125
1126         if (!read_size || size < read_size)
1127                 return 0;
1128
1129         data = kzalloc(read_size, GFP_KERNEL);
1130         if (!data)
1131                 return 0;
1132
1133         dm_helpers_dp_read_dpcd(link->ctx, link,
1134                         connector->debugfs_dpcd_address, data, read_size);
1135
1136         r = copy_to_user(buf, data, read_size);
1137
1138         kfree(data);
1139         return read_size - r;
1140 }
1141
1142 /* function: Read link's DSC & FEC capabilities
1143  *
1144  *
1145  * Access it with the following command (you need to specify
1146  * connector like DP-1):
1147  *
1148  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1149  *
1150  */
1151 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1152 {
1153         struct drm_connector *connector = m->private;
1154         struct drm_modeset_acquire_ctx ctx;
1155         struct drm_device *dev = connector->dev;
1156         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1157         int ret = 0;
1158         bool try_again = false;
1159         bool is_fec_supported = false;
1160         bool is_dsc_supported = false;
1161         struct dpcd_caps dpcd_caps;
1162
1163         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1164         do {
1165                 try_again = false;
1166                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1167                 if (ret) {
1168                         if (ret == -EDEADLK) {
1169                                 ret = drm_modeset_backoff(&ctx);
1170                                 if (!ret) {
1171                                         try_again = true;
1172                                         continue;
1173                                 }
1174                         }
1175                         break;
1176                 }
1177                 if (connector->status != connector_status_connected) {
1178                         ret = -ENODEV;
1179                         break;
1180                 }
1181                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1182                 if (aconnector->port) {
1183                         /* aconnector sets dsc_aux during get_modes call
1184                          * if MST connector has it means it can either
1185                          * enable DSC on the sink device or on MST branch
1186                          * its connected to.
1187                          */
1188                         if (aconnector->dsc_aux) {
1189                                 is_fec_supported = true;
1190                                 is_dsc_supported = true;
1191                         }
1192                 } else {
1193                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1194                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1195                 }
1196         } while (try_again);
1197
1198         drm_modeset_drop_locks(&ctx);
1199         drm_modeset_acquire_fini(&ctx);
1200
1201         seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1202         seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1203
1204         return ret;
1205 }
1206
1207 /* function: Trigger virtual HPD redetection on connector
1208  *
1209  * This function will perform link rediscovery, link disable
1210  * and enable, and dm connector state update.
1211  *
1212  * Retrigger HPD on an existing connector by echoing 1 into
1213  * its respectful "trigger_hotplug" debugfs entry:
1214  *
1215  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1216  *
1217  * This function can perform HPD unplug:
1218  *
1219  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1220  *
1221  */
1222 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1223                                                         size_t size, loff_t *pos)
1224 {
1225         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1226         struct drm_connector *connector = &aconnector->base;
1227         struct dc_link *link = NULL;
1228         struct drm_device *dev = connector->dev;
1229         struct amdgpu_device *adev = drm_to_adev(dev);
1230         enum dc_connection_type new_connection_type = dc_connection_none;
1231         char *wr_buf = NULL;
1232         uint32_t wr_buf_size = 42;
1233         int max_param_num = 1;
1234         long param[1] = {0};
1235         uint8_t param_nums = 0;
1236         bool ret = false;
1237
1238         if (!aconnector || !aconnector->dc_link)
1239                 return -EINVAL;
1240
1241         if (size == 0)
1242                 return -EINVAL;
1243
1244         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1245
1246         if (!wr_buf) {
1247                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1248                 return -ENOSPC;
1249         }
1250
1251         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1252                                                 (long *)param, buf,
1253                                                 max_param_num,
1254                                                 &param_nums)) {
1255                 kfree(wr_buf);
1256                 return -EINVAL;
1257         }
1258
1259         if (param_nums <= 0) {
1260                 DRM_DEBUG_DRIVER("user data not be read\n");
1261                 kfree(wr_buf);
1262                 return -EINVAL;
1263         }
1264
1265         if (param[0] == 1) {
1266                 mutex_lock(&aconnector->hpd_lock);
1267
1268                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1269                         new_connection_type != dc_connection_none)
1270                         goto unlock;
1271
1272                 mutex_lock(&adev->dm.dc_lock);
1273                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1274                 mutex_unlock(&adev->dm.dc_lock);
1275
1276                 if (!ret)
1277                         goto unlock;
1278
1279                 amdgpu_dm_update_connector_after_detect(aconnector);
1280
1281                 drm_modeset_lock_all(dev);
1282                 dm_restore_drm_connector_state(dev, connector);
1283                 drm_modeset_unlock_all(dev);
1284
1285                 drm_kms_helper_connector_hotplug_event(connector);
1286         } else if (param[0] == 0) {
1287                 if (!aconnector->dc_link)
1288                         goto unlock;
1289
1290                 link = aconnector->dc_link;
1291
1292                 if (link->local_sink) {
1293                         dc_sink_release(link->local_sink);
1294                         link->local_sink = NULL;
1295                 }
1296
1297                 link->dpcd_sink_count = 0;
1298                 link->type = dc_connection_none;
1299                 link->dongle_max_pix_clk = 0;
1300
1301                 amdgpu_dm_update_connector_after_detect(aconnector);
1302
1303                 drm_modeset_lock_all(dev);
1304                 dm_restore_drm_connector_state(dev, connector);
1305                 drm_modeset_unlock_all(dev);
1306
1307                 drm_kms_helper_connector_hotplug_event(connector);
1308         }
1309
1310 unlock:
1311         mutex_unlock(&aconnector->hpd_lock);
1312
1313         kfree(wr_buf);
1314         return size;
1315 }
1316
1317 /* function: read DSC status on the connector
1318  *
1319  * The read function: dp_dsc_clock_en_read
1320  * returns current status of DSC clock on the connector.
1321  * The return is a boolean flag: 1 or 0.
1322  *
1323  * Access it with the following command (you need to specify
1324  * connector like DP-1):
1325  *
1326  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1327  *
1328  * Expected output:
1329  * 1 - means that DSC is currently enabled
1330  * 0 - means that DSC is disabled
1331  */
1332 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1333                                     size_t size, loff_t *pos)
1334 {
1335         char *rd_buf = NULL;
1336         char *rd_buf_ptr = NULL;
1337         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1338         struct display_stream_compressor *dsc;
1339         struct dcn_dsc_state dsc_state = {0};
1340         const uint32_t rd_buf_size = 10;
1341         struct pipe_ctx *pipe_ctx;
1342         ssize_t result = 0;
1343         int i, r, str_len = 30;
1344
1345         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1346
1347         if (!rd_buf)
1348                 return -ENOMEM;
1349
1350         rd_buf_ptr = rd_buf;
1351
1352         for (i = 0; i < MAX_PIPES; i++) {
1353                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1354                         if (pipe_ctx && pipe_ctx->stream &&
1355                             pipe_ctx->stream->link == aconnector->dc_link)
1356                                 break;
1357         }
1358
1359         if (!pipe_ctx) {
1360                 kfree(rd_buf);
1361                 return -ENXIO;
1362         }
1363
1364         dsc = pipe_ctx->stream_res.dsc;
1365         if (dsc)
1366                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1367
1368         snprintf(rd_buf_ptr, str_len,
1369                 "%d\n",
1370                 dsc_state.dsc_clock_en);
1371         rd_buf_ptr += str_len;
1372
1373         while (size) {
1374                 if (*pos >= rd_buf_size)
1375                         break;
1376
1377                 r = put_user(*(rd_buf + result), buf);
1378                 if (r) {
1379                         kfree(rd_buf);
1380                         return r; /* r = -EFAULT */
1381                 }
1382
1383                 buf += 1;
1384                 size -= 1;
1385                 *pos += 1;
1386                 result += 1;
1387         }
1388
1389         kfree(rd_buf);
1390         return result;
1391 }
1392
1393 /* function: write force DSC on the connector
1394  *
1395  * The write function: dp_dsc_clock_en_write
1396  * enables to force DSC on the connector.
1397  * User can write to either force enable or force disable DSC
1398  * on the next modeset or set it to driver default
1399  *
1400  * Accepted inputs:
1401  * 0 - default DSC enablement policy
1402  * 1 - force enable DSC on the connector
1403  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1404  *
1405  * Writing DSC settings is done with the following command:
1406  * - To force enable DSC (you need to specify
1407  * connector like DP-1):
1408  *
1409  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1410  *
1411  * - To return to default state set the flag to zero and
1412  * let driver deal with DSC automatically
1413  * (you need to specify connector like DP-1):
1414  *
1415  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1416  *
1417  */
1418 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1419                                      size_t size, loff_t *pos)
1420 {
1421         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1422         struct drm_connector *connector = &aconnector->base;
1423         struct drm_device *dev = connector->dev;
1424         struct drm_crtc *crtc = NULL;
1425         struct dm_crtc_state *dm_crtc_state = NULL;
1426         struct pipe_ctx *pipe_ctx;
1427         int i;
1428         char *wr_buf = NULL;
1429         uint32_t wr_buf_size = 42;
1430         int max_param_num = 1;
1431         long param[1] = {0};
1432         uint8_t param_nums = 0;
1433
1434         if (size == 0)
1435                 return -EINVAL;
1436
1437         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1438
1439         if (!wr_buf) {
1440                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1441                 return -ENOSPC;
1442         }
1443
1444         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1445                                             (long *)param, buf,
1446                                             max_param_num,
1447                                             &param_nums)) {
1448                 kfree(wr_buf);
1449                 return -EINVAL;
1450         }
1451
1452         if (param_nums <= 0) {
1453                 DRM_DEBUG_DRIVER("user data not be read\n");
1454                 kfree(wr_buf);
1455                 return -EINVAL;
1456         }
1457
1458         for (i = 0; i < MAX_PIPES; i++) {
1459                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1460                         if (pipe_ctx && pipe_ctx->stream &&
1461                             pipe_ctx->stream->link == aconnector->dc_link)
1462                                 break;
1463         }
1464
1465         if (!pipe_ctx || !pipe_ctx->stream)
1466                 goto done;
1467
1468         // Get CRTC state
1469         mutex_lock(&dev->mode_config.mutex);
1470         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1471
1472         if (connector->state == NULL)
1473                 goto unlock;
1474
1475         crtc = connector->state->crtc;
1476         if (crtc == NULL)
1477                 goto unlock;
1478
1479         drm_modeset_lock(&crtc->mutex, NULL);
1480         if (crtc->state == NULL)
1481                 goto unlock;
1482
1483         dm_crtc_state = to_dm_crtc_state(crtc->state);
1484         if (dm_crtc_state->stream == NULL)
1485                 goto unlock;
1486
1487         if (param[0] == 1)
1488                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1489         else if (param[0] == 2)
1490                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1491         else
1492                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1493
1494         dm_crtc_state->dsc_force_changed = true;
1495
1496 unlock:
1497         if (crtc)
1498                 drm_modeset_unlock(&crtc->mutex);
1499         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1500         mutex_unlock(&dev->mode_config.mutex);
1501
1502 done:
1503         kfree(wr_buf);
1504         return size;
1505 }
1506
1507 /* function: read DSC slice width parameter on the connector
1508  *
1509  * The read function: dp_dsc_slice_width_read
1510  * returns dsc slice width used in the current configuration
1511  * The return is an integer: 0 or other positive number
1512  *
1513  * Access the status with the following command:
1514  *
1515  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1516  *
1517  * 0 - means that DSC is disabled
1518  *
1519  * Any other number more than zero represents the
1520  * slice width currently used by DSC in pixels
1521  *
1522  */
1523 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1524                                     size_t size, loff_t *pos)
1525 {
1526         char *rd_buf = NULL;
1527         char *rd_buf_ptr = NULL;
1528         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1529         struct display_stream_compressor *dsc;
1530         struct dcn_dsc_state dsc_state = {0};
1531         const uint32_t rd_buf_size = 100;
1532         struct pipe_ctx *pipe_ctx;
1533         ssize_t result = 0;
1534         int i, r, str_len = 30;
1535
1536         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1537
1538         if (!rd_buf)
1539                 return -ENOMEM;
1540
1541         rd_buf_ptr = rd_buf;
1542
1543         for (i = 0; i < MAX_PIPES; i++) {
1544                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1545                         if (pipe_ctx && pipe_ctx->stream &&
1546                             pipe_ctx->stream->link == aconnector->dc_link)
1547                                 break;
1548         }
1549
1550         if (!pipe_ctx) {
1551                 kfree(rd_buf);
1552                 return -ENXIO;
1553         }
1554
1555         dsc = pipe_ctx->stream_res.dsc;
1556         if (dsc)
1557                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1558
1559         snprintf(rd_buf_ptr, str_len,
1560                 "%d\n",
1561                 dsc_state.dsc_slice_width);
1562         rd_buf_ptr += str_len;
1563
1564         while (size) {
1565                 if (*pos >= rd_buf_size)
1566                         break;
1567
1568                 r = put_user(*(rd_buf + result), buf);
1569                 if (r) {
1570                         kfree(rd_buf);
1571                         return r; /* r = -EFAULT */
1572                 }
1573
1574                 buf += 1;
1575                 size -= 1;
1576                 *pos += 1;
1577                 result += 1;
1578         }
1579
1580         kfree(rd_buf);
1581         return result;
1582 }
1583
1584 /* function: write DSC slice width parameter
1585  *
1586  * The write function: dp_dsc_slice_width_write
1587  * overwrites automatically generated DSC configuration
1588  * of slice width.
1589  *
1590  * The user has to write the slice width divisible by the
1591  * picture width.
1592  *
1593  * Also the user has to write width in hexidecimal
1594  * rather than in decimal.
1595  *
1596  * Writing DSC settings is done with the following command:
1597  * - To force overwrite slice width: (example sets to 1920 pixels)
1598  *
1599  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1600  *
1601  *  - To stop overwriting and let driver find the optimal size,
1602  * set the width to zero:
1603  *
1604  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1605  *
1606  */
1607 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1608                                      size_t size, loff_t *pos)
1609 {
1610         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1611         struct pipe_ctx *pipe_ctx;
1612         struct drm_connector *connector = &aconnector->base;
1613         struct drm_device *dev = connector->dev;
1614         struct drm_crtc *crtc = NULL;
1615         struct dm_crtc_state *dm_crtc_state = NULL;
1616         int i;
1617         char *wr_buf = NULL;
1618         uint32_t wr_buf_size = 42;
1619         int max_param_num = 1;
1620         long param[1] = {0};
1621         uint8_t param_nums = 0;
1622
1623         if (size == 0)
1624                 return -EINVAL;
1625
1626         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1627
1628         if (!wr_buf) {
1629                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1630                 return -ENOSPC;
1631         }
1632
1633         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1634                                             (long *)param, buf,
1635                                             max_param_num,
1636                                             &param_nums)) {
1637                 kfree(wr_buf);
1638                 return -EINVAL;
1639         }
1640
1641         if (param_nums <= 0) {
1642                 DRM_DEBUG_DRIVER("user data not be read\n");
1643                 kfree(wr_buf);
1644                 return -EINVAL;
1645         }
1646
1647         for (i = 0; i < MAX_PIPES; i++) {
1648                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1649                         if (pipe_ctx && pipe_ctx->stream &&
1650                             pipe_ctx->stream->link == aconnector->dc_link)
1651                                 break;
1652         }
1653
1654         if (!pipe_ctx || !pipe_ctx->stream)
1655                 goto done;
1656
1657         // Safely get CRTC state
1658         mutex_lock(&dev->mode_config.mutex);
1659         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1660
1661         if (connector->state == NULL)
1662                 goto unlock;
1663
1664         crtc = connector->state->crtc;
1665         if (crtc == NULL)
1666                 goto unlock;
1667
1668         drm_modeset_lock(&crtc->mutex, NULL);
1669         if (crtc->state == NULL)
1670                 goto unlock;
1671
1672         dm_crtc_state = to_dm_crtc_state(crtc->state);
1673         if (dm_crtc_state->stream == NULL)
1674                 goto unlock;
1675
1676         if (param[0] > 0)
1677                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1678                                         pipe_ctx->stream->timing.h_addressable,
1679                                         param[0]);
1680         else
1681                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1682
1683         dm_crtc_state->dsc_force_changed = true;
1684
1685 unlock:
1686         if (crtc)
1687                 drm_modeset_unlock(&crtc->mutex);
1688         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1689         mutex_unlock(&dev->mode_config.mutex);
1690
1691 done:
1692         kfree(wr_buf);
1693         return size;
1694 }
1695
1696 /* function: read DSC slice height parameter on the connector
1697  *
1698  * The read function: dp_dsc_slice_height_read
1699  * returns dsc slice height used in the current configuration
1700  * The return is an integer: 0 or other positive number
1701  *
1702  * Access the status with the following command:
1703  *
1704  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1705  *
1706  * 0 - means that DSC is disabled
1707  *
1708  * Any other number more than zero represents the
1709  * slice height currently used by DSC in pixels
1710  *
1711  */
1712 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1713                                     size_t size, loff_t *pos)
1714 {
1715         char *rd_buf = NULL;
1716         char *rd_buf_ptr = NULL;
1717         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1718         struct display_stream_compressor *dsc;
1719         struct dcn_dsc_state dsc_state = {0};
1720         const uint32_t rd_buf_size = 100;
1721         struct pipe_ctx *pipe_ctx;
1722         ssize_t result = 0;
1723         int i, r, str_len = 30;
1724
1725         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1726
1727         if (!rd_buf)
1728                 return -ENOMEM;
1729
1730         rd_buf_ptr = rd_buf;
1731
1732         for (i = 0; i < MAX_PIPES; i++) {
1733                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1734                         if (pipe_ctx && pipe_ctx->stream &&
1735                             pipe_ctx->stream->link == aconnector->dc_link)
1736                                 break;
1737         }
1738
1739         if (!pipe_ctx) {
1740                 kfree(rd_buf);
1741                 return -ENXIO;
1742         }
1743
1744         dsc = pipe_ctx->stream_res.dsc;
1745         if (dsc)
1746                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1747
1748         snprintf(rd_buf_ptr, str_len,
1749                 "%d\n",
1750                 dsc_state.dsc_slice_height);
1751         rd_buf_ptr += str_len;
1752
1753         while (size) {
1754                 if (*pos >= rd_buf_size)
1755                         break;
1756
1757                 r = put_user(*(rd_buf + result), buf);
1758                 if (r) {
1759                         kfree(rd_buf);
1760                         return r; /* r = -EFAULT */
1761                 }
1762
1763                 buf += 1;
1764                 size -= 1;
1765                 *pos += 1;
1766                 result += 1;
1767         }
1768
1769         kfree(rd_buf);
1770         return result;
1771 }
1772
1773 /* function: write DSC slice height parameter
1774  *
1775  * The write function: dp_dsc_slice_height_write
1776  * overwrites automatically generated DSC configuration
1777  * of slice height.
1778  *
1779  * The user has to write the slice height divisible by the
1780  * picture height.
1781  *
1782  * Also the user has to write height in hexidecimal
1783  * rather than in decimal.
1784  *
1785  * Writing DSC settings is done with the following command:
1786  * - To force overwrite slice height (example sets to 128 pixels):
1787  *
1788  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1789  *
1790  *  - To stop overwriting and let driver find the optimal size,
1791  * set the height to zero:
1792  *
1793  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1794  *
1795  */
1796 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1797                                      size_t size, loff_t *pos)
1798 {
1799         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1800         struct drm_connector *connector = &aconnector->base;
1801         struct drm_device *dev = connector->dev;
1802         struct drm_crtc *crtc = NULL;
1803         struct dm_crtc_state *dm_crtc_state = NULL;
1804         struct pipe_ctx *pipe_ctx;
1805         int i;
1806         char *wr_buf = NULL;
1807         uint32_t wr_buf_size = 42;
1808         int max_param_num = 1;
1809         uint8_t param_nums = 0;
1810         long param[1] = {0};
1811
1812         if (size == 0)
1813                 return -EINVAL;
1814
1815         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1816
1817         if (!wr_buf) {
1818                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1819                 return -ENOSPC;
1820         }
1821
1822         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1823                                             (long *)param, buf,
1824                                             max_param_num,
1825                                             &param_nums)) {
1826                 kfree(wr_buf);
1827                 return -EINVAL;
1828         }
1829
1830         if (param_nums <= 0) {
1831                 DRM_DEBUG_DRIVER("user data not be read\n");
1832                 kfree(wr_buf);
1833                 return -EINVAL;
1834         }
1835
1836         for (i = 0; i < MAX_PIPES; i++) {
1837                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1838                         if (pipe_ctx && pipe_ctx->stream &&
1839                             pipe_ctx->stream->link == aconnector->dc_link)
1840                                 break;
1841         }
1842
1843         if (!pipe_ctx || !pipe_ctx->stream)
1844                 goto done;
1845
1846         // Get CRTC state
1847         mutex_lock(&dev->mode_config.mutex);
1848         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1849
1850         if (connector->state == NULL)
1851                 goto unlock;
1852
1853         crtc = connector->state->crtc;
1854         if (crtc == NULL)
1855                 goto unlock;
1856
1857         drm_modeset_lock(&crtc->mutex, NULL);
1858         if (crtc->state == NULL)
1859                 goto unlock;
1860
1861         dm_crtc_state = to_dm_crtc_state(crtc->state);
1862         if (dm_crtc_state->stream == NULL)
1863                 goto unlock;
1864
1865         if (param[0] > 0)
1866                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1867                                         pipe_ctx->stream->timing.v_addressable,
1868                                         param[0]);
1869         else
1870                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1871
1872         dm_crtc_state->dsc_force_changed = true;
1873
1874 unlock:
1875         if (crtc)
1876                 drm_modeset_unlock(&crtc->mutex);
1877         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1878         mutex_unlock(&dev->mode_config.mutex);
1879
1880 done:
1881         kfree(wr_buf);
1882         return size;
1883 }
1884
1885 /* function: read DSC target rate on the connector in bits per pixel
1886  *
1887  * The read function: dp_dsc_bits_per_pixel_read
1888  * returns target rate of compression in bits per pixel
1889  * The return is an integer: 0 or other positive integer
1890  *
1891  * Access it with the following command:
1892  *
1893  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1894  *
1895  *  0 - means that DSC is disabled
1896  */
1897 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1898                                     size_t size, loff_t *pos)
1899 {
1900         char *rd_buf = NULL;
1901         char *rd_buf_ptr = NULL;
1902         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1903         struct display_stream_compressor *dsc;
1904         struct dcn_dsc_state dsc_state = {0};
1905         const uint32_t rd_buf_size = 100;
1906         struct pipe_ctx *pipe_ctx;
1907         ssize_t result = 0;
1908         int i, r, str_len = 30;
1909
1910         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1911
1912         if (!rd_buf)
1913                 return -ENOMEM;
1914
1915         rd_buf_ptr = rd_buf;
1916
1917         for (i = 0; i < MAX_PIPES; i++) {
1918                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1919                         if (pipe_ctx && pipe_ctx->stream &&
1920                             pipe_ctx->stream->link == aconnector->dc_link)
1921                                 break;
1922         }
1923
1924         if (!pipe_ctx) {
1925                 kfree(rd_buf);
1926                 return -ENXIO;
1927         }
1928
1929         dsc = pipe_ctx->stream_res.dsc;
1930         if (dsc)
1931                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1932
1933         snprintf(rd_buf_ptr, str_len,
1934                 "%d\n",
1935                 dsc_state.dsc_bits_per_pixel);
1936         rd_buf_ptr += str_len;
1937
1938         while (size) {
1939                 if (*pos >= rd_buf_size)
1940                         break;
1941
1942                 r = put_user(*(rd_buf + result), buf);
1943                 if (r) {
1944                         kfree(rd_buf);
1945                         return r; /* r = -EFAULT */
1946                 }
1947
1948                 buf += 1;
1949                 size -= 1;
1950                 *pos += 1;
1951                 result += 1;
1952         }
1953
1954         kfree(rd_buf);
1955         return result;
1956 }
1957
1958 /* function: write DSC target rate in bits per pixel
1959  *
1960  * The write function: dp_dsc_bits_per_pixel_write
1961  * overwrites automatically generated DSC configuration
1962  * of DSC target bit rate.
1963  *
1964  * Also the user has to write bpp in hexidecimal
1965  * rather than in decimal.
1966  *
1967  * Writing DSC settings is done with the following command:
1968  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1969  *
1970  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1971  *
1972  *  - To stop overwriting and let driver find the optimal rate,
1973  * set the rate to zero:
1974  *
1975  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1976  *
1977  */
1978 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1979                                      size_t size, loff_t *pos)
1980 {
1981         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1982         struct drm_connector *connector = &aconnector->base;
1983         struct drm_device *dev = connector->dev;
1984         struct drm_crtc *crtc = NULL;
1985         struct dm_crtc_state *dm_crtc_state = NULL;
1986         struct pipe_ctx *pipe_ctx;
1987         int i;
1988         char *wr_buf = NULL;
1989         uint32_t wr_buf_size = 42;
1990         int max_param_num = 1;
1991         uint8_t param_nums = 0;
1992         long param[1] = {0};
1993
1994         if (size == 0)
1995                 return -EINVAL;
1996
1997         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1998
1999         if (!wr_buf) {
2000                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2001                 return -ENOSPC;
2002         }
2003
2004         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2005                                             (long *)param, buf,
2006                                             max_param_num,
2007                                             &param_nums)) {
2008                 kfree(wr_buf);
2009                 return -EINVAL;
2010         }
2011
2012         if (param_nums <= 0) {
2013                 DRM_DEBUG_DRIVER("user data not be read\n");
2014                 kfree(wr_buf);
2015                 return -EINVAL;
2016         }
2017
2018         for (i = 0; i < MAX_PIPES; i++) {
2019                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2020                         if (pipe_ctx && pipe_ctx->stream &&
2021                             pipe_ctx->stream->link == aconnector->dc_link)
2022                                 break;
2023         }
2024
2025         if (!pipe_ctx || !pipe_ctx->stream)
2026                 goto done;
2027
2028         // Get CRTC state
2029         mutex_lock(&dev->mode_config.mutex);
2030         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2031
2032         if (connector->state == NULL)
2033                 goto unlock;
2034
2035         crtc = connector->state->crtc;
2036         if (crtc == NULL)
2037                 goto unlock;
2038
2039         drm_modeset_lock(&crtc->mutex, NULL);
2040         if (crtc->state == NULL)
2041                 goto unlock;
2042
2043         dm_crtc_state = to_dm_crtc_state(crtc->state);
2044         if (dm_crtc_state->stream == NULL)
2045                 goto unlock;
2046
2047         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2048
2049         dm_crtc_state->dsc_force_changed = true;
2050
2051 unlock:
2052         if (crtc)
2053                 drm_modeset_unlock(&crtc->mutex);
2054         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2055         mutex_unlock(&dev->mode_config.mutex);
2056
2057 done:
2058         kfree(wr_buf);
2059         return size;
2060 }
2061
2062 /* function: read DSC picture width parameter on the connector
2063  *
2064  * The read function: dp_dsc_pic_width_read
2065  * returns dsc picture width used in the current configuration
2066  * It is the same as h_addressable of the current
2067  * display's timing
2068  * The return is an integer: 0 or other positive integer
2069  * If 0 then DSC is disabled.
2070  *
2071  * Access it with the following command:
2072  *
2073  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2074  *
2075  * 0 - means that DSC is disabled
2076  */
2077 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2078                                     size_t size, loff_t *pos)
2079 {
2080         char *rd_buf = NULL;
2081         char *rd_buf_ptr = NULL;
2082         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2083         struct display_stream_compressor *dsc;
2084         struct dcn_dsc_state dsc_state = {0};
2085         const uint32_t rd_buf_size = 100;
2086         struct pipe_ctx *pipe_ctx;
2087         ssize_t result = 0;
2088         int i, r, str_len = 30;
2089
2090         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2091
2092         if (!rd_buf)
2093                 return -ENOMEM;
2094
2095         rd_buf_ptr = rd_buf;
2096
2097         for (i = 0; i < MAX_PIPES; i++) {
2098                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2099                         if (pipe_ctx && pipe_ctx->stream &&
2100                             pipe_ctx->stream->link == aconnector->dc_link)
2101                                 break;
2102         }
2103
2104         if (!pipe_ctx) {
2105                 kfree(rd_buf);
2106                 return -ENXIO;
2107         }
2108
2109         dsc = pipe_ctx->stream_res.dsc;
2110         if (dsc)
2111                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2112
2113         snprintf(rd_buf_ptr, str_len,
2114                 "%d\n",
2115                 dsc_state.dsc_pic_width);
2116         rd_buf_ptr += str_len;
2117
2118         while (size) {
2119                 if (*pos >= rd_buf_size)
2120                         break;
2121
2122                 r = put_user(*(rd_buf + result), buf);
2123                 if (r) {
2124                         kfree(rd_buf);
2125                         return r; /* r = -EFAULT */
2126                 }
2127
2128                 buf += 1;
2129                 size -= 1;
2130                 *pos += 1;
2131                 result += 1;
2132         }
2133
2134         kfree(rd_buf);
2135         return result;
2136 }
2137
2138 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2139                                     size_t size, loff_t *pos)
2140 {
2141         char *rd_buf = NULL;
2142         char *rd_buf_ptr = NULL;
2143         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2144         struct display_stream_compressor *dsc;
2145         struct dcn_dsc_state dsc_state = {0};
2146         const uint32_t rd_buf_size = 100;
2147         struct pipe_ctx *pipe_ctx;
2148         ssize_t result = 0;
2149         int i, r, str_len = 30;
2150
2151         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2152
2153         if (!rd_buf)
2154                 return -ENOMEM;
2155
2156         rd_buf_ptr = rd_buf;
2157
2158         for (i = 0; i < MAX_PIPES; i++) {
2159                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2160                         if (pipe_ctx && pipe_ctx->stream &&
2161                             pipe_ctx->stream->link == aconnector->dc_link)
2162                                 break;
2163         }
2164
2165         if (!pipe_ctx) {
2166                 kfree(rd_buf);
2167                 return -ENXIO;
2168         }
2169
2170         dsc = pipe_ctx->stream_res.dsc;
2171         if (dsc)
2172                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2173
2174         snprintf(rd_buf_ptr, str_len,
2175                 "%d\n",
2176                 dsc_state.dsc_pic_height);
2177         rd_buf_ptr += str_len;
2178
2179         while (size) {
2180                 if (*pos >= rd_buf_size)
2181                         break;
2182
2183                 r = put_user(*(rd_buf + result), buf);
2184                 if (r) {
2185                         kfree(rd_buf);
2186                         return r; /* r = -EFAULT */
2187                 }
2188
2189                 buf += 1;
2190                 size -= 1;
2191                 *pos += 1;
2192                 result += 1;
2193         }
2194
2195         kfree(rd_buf);
2196         return result;
2197 }
2198
2199 /* function: read DSC chunk size parameter on the connector
2200  *
2201  * The read function: dp_dsc_chunk_size_read
2202  * returns dsc chunk size set in the current configuration
2203  * The value is calculated automatically by DSC code
2204  * and depends on slice parameters and bpp target rate
2205  * The return is an integer: 0 or other positive integer
2206  * If 0 then DSC is disabled.
2207  *
2208  * Access it with the following command:
2209  *
2210  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2211  *
2212  * 0 - means that DSC is disabled
2213  */
2214 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2215                                     size_t size, loff_t *pos)
2216 {
2217         char *rd_buf = NULL;
2218         char *rd_buf_ptr = NULL;
2219         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2220         struct display_stream_compressor *dsc;
2221         struct dcn_dsc_state dsc_state = {0};
2222         const uint32_t rd_buf_size = 100;
2223         struct pipe_ctx *pipe_ctx;
2224         ssize_t result = 0;
2225         int i, r, str_len = 30;
2226
2227         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2228
2229         if (!rd_buf)
2230                 return -ENOMEM;
2231
2232         rd_buf_ptr = rd_buf;
2233
2234         for (i = 0; i < MAX_PIPES; i++) {
2235                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2236                         if (pipe_ctx && pipe_ctx->stream &&
2237                             pipe_ctx->stream->link == aconnector->dc_link)
2238                                 break;
2239         }
2240
2241         if (!pipe_ctx) {
2242                 kfree(rd_buf);
2243                 return -ENXIO;
2244         }
2245
2246         dsc = pipe_ctx->stream_res.dsc;
2247         if (dsc)
2248                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2249
2250         snprintf(rd_buf_ptr, str_len,
2251                 "%d\n",
2252                 dsc_state.dsc_chunk_size);
2253         rd_buf_ptr += str_len;
2254
2255         while (size) {
2256                 if (*pos >= rd_buf_size)
2257                         break;
2258
2259                 r = put_user(*(rd_buf + result), buf);
2260                 if (r) {
2261                         kfree(rd_buf);
2262                         return r; /* r = -EFAULT */
2263                 }
2264
2265                 buf += 1;
2266                 size -= 1;
2267                 *pos += 1;
2268                 result += 1;
2269         }
2270
2271         kfree(rd_buf);
2272         return result;
2273 }
2274
2275 /* function: read DSC slice bpg offset on the connector
2276  *
2277  * The read function: dp_dsc_slice_bpg_offset_read
2278  * returns dsc bpg slice offset set in the current configuration
2279  * The value is calculated automatically by DSC code
2280  * and depends on slice parameters and bpp target rate
2281  * The return is an integer: 0 or other positive integer
2282  * If 0 then DSC is disabled.
2283  *
2284  * Access it with the following command:
2285  *
2286  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2287  *
2288  * 0 - means that DSC is disabled
2289  */
2290 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2291                                     size_t size, loff_t *pos)
2292 {
2293         char *rd_buf = NULL;
2294         char *rd_buf_ptr = NULL;
2295         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2296         struct display_stream_compressor *dsc;
2297         struct dcn_dsc_state dsc_state = {0};
2298         const uint32_t rd_buf_size = 100;
2299         struct pipe_ctx *pipe_ctx;
2300         ssize_t result = 0;
2301         int i, r, str_len = 30;
2302
2303         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2304
2305         if (!rd_buf)
2306                 return -ENOMEM;
2307
2308         rd_buf_ptr = rd_buf;
2309
2310         for (i = 0; i < MAX_PIPES; i++) {
2311                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2312                         if (pipe_ctx && pipe_ctx->stream &&
2313                             pipe_ctx->stream->link == aconnector->dc_link)
2314                                 break;
2315         }
2316
2317         if (!pipe_ctx) {
2318                 kfree(rd_buf);
2319                 return -ENXIO;
2320         }
2321
2322         dsc = pipe_ctx->stream_res.dsc;
2323         if (dsc)
2324                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2325
2326         snprintf(rd_buf_ptr, str_len,
2327                 "%d\n",
2328                 dsc_state.dsc_slice_bpg_offset);
2329         rd_buf_ptr += str_len;
2330
2331         while (size) {
2332                 if (*pos >= rd_buf_size)
2333                         break;
2334
2335                 r = put_user(*(rd_buf + result), buf);
2336                 if (r) {
2337                         kfree(rd_buf);
2338                         return r; /* r = -EFAULT */
2339                 }
2340
2341                 buf += 1;
2342                 size -= 1;
2343                 *pos += 1;
2344                 result += 1;
2345         }
2346
2347         kfree(rd_buf);
2348         return result;
2349 }
2350
2351
2352 /*
2353  * function description: Read max_requested_bpc property from the connector
2354  *
2355  * Access it with the following command:
2356  *
2357  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2358  *
2359  */
2360 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2361                 size_t size, loff_t *pos)
2362 {
2363         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2364         struct drm_connector *connector = &aconnector->base;
2365         struct drm_device *dev = connector->dev;
2366         struct dm_connector_state *state;
2367         ssize_t result = 0;
2368         char *rd_buf = NULL;
2369         char *rd_buf_ptr = NULL;
2370         const uint32_t rd_buf_size = 10;
2371         int r;
2372
2373         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2374
2375         if (!rd_buf)
2376                 return -ENOMEM;
2377
2378         mutex_lock(&dev->mode_config.mutex);
2379         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2380
2381         if (connector->state == NULL)
2382                 goto unlock;
2383
2384         state = to_dm_connector_state(connector->state);
2385
2386         rd_buf_ptr = rd_buf;
2387         snprintf(rd_buf_ptr, rd_buf_size,
2388                 "%u\n",
2389                 state->base.max_requested_bpc);
2390
2391         while (size) {
2392                 if (*pos >= rd_buf_size)
2393                         break;
2394
2395                 r = put_user(*(rd_buf + result), buf);
2396                 if (r) {
2397                         result = r; /* r = -EFAULT */
2398                         goto unlock;
2399                 }
2400                 buf += 1;
2401                 size -= 1;
2402                 *pos += 1;
2403                 result += 1;
2404         }
2405 unlock:
2406         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2407         mutex_unlock(&dev->mode_config.mutex);
2408         kfree(rd_buf);
2409         return result;
2410 }
2411
2412
2413 /*
2414  * function description: Set max_requested_bpc property on the connector
2415  *
2416  * This function will not force the input BPC on connector, it will only
2417  * change the max value. This is equivalent to setting max_bpc through
2418  * xrandr.
2419  *
2420  * The BPC value written must be >= 6 and <= 16. Values outside of this
2421  * range will result in errors.
2422  *
2423  * BPC values:
2424  *      0x6 - 6 BPC
2425  *      0x8 - 8 BPC
2426  *      0xa - 10 BPC
2427  *      0xc - 12 BPC
2428  *      0x10 - 16 BPC
2429  *
2430  * Write the max_bpc in the following way:
2431  *
2432  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2433  *
2434  */
2435 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2436                                      size_t size, loff_t *pos)
2437 {
2438         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2439         struct drm_connector *connector = &aconnector->base;
2440         struct dm_connector_state *state;
2441         struct drm_device *dev = connector->dev;
2442         char *wr_buf = NULL;
2443         uint32_t wr_buf_size = 42;
2444         int max_param_num = 1;
2445         long param[1] = {0};
2446         uint8_t param_nums = 0;
2447
2448         if (size == 0)
2449                 return -EINVAL;
2450
2451         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2452
2453         if (!wr_buf) {
2454                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2455                 return -ENOSPC;
2456         }
2457
2458         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2459                                            (long *)param, buf,
2460                                            max_param_num,
2461                                            &param_nums)) {
2462                 kfree(wr_buf);
2463                 return -EINVAL;
2464         }
2465
2466         if (param_nums <= 0) {
2467                 DRM_DEBUG_DRIVER("user data not be read\n");
2468                 kfree(wr_buf);
2469                 return -EINVAL;
2470         }
2471
2472         if (param[0] < 6 || param[0] > 16) {
2473                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2474                 kfree(wr_buf);
2475                 return -EINVAL;
2476         }
2477
2478         mutex_lock(&dev->mode_config.mutex);
2479         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2480
2481         if (connector->state == NULL)
2482                 goto unlock;
2483
2484         state = to_dm_connector_state(connector->state);
2485         state->base.max_requested_bpc = param[0];
2486 unlock:
2487         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2488         mutex_unlock(&dev->mode_config.mutex);
2489
2490         kfree(wr_buf);
2491         return size;
2492 }
2493
2494 /*
2495  * Backlight at this moment.  Read only.
2496  * As written to display, taking ABM and backlight lut into account.
2497  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2498  *
2499  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2500  */
2501 static int current_backlight_show(struct seq_file *m, void *unused)
2502 {
2503         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2504         struct dc_link *link = aconnector->dc_link;
2505         unsigned int backlight;
2506
2507         backlight = dc_link_get_backlight_level(link);
2508         seq_printf(m, "0x%x\n", backlight);
2509
2510         return 0;
2511 }
2512
2513 /*
2514  * Backlight value that is being approached.  Read only.
2515  * As written to display, taking ABM and backlight lut into account.
2516  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2517  *
2518  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2519  */
2520 static int target_backlight_show(struct seq_file *m, void *unused)
2521 {
2522         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2523         struct dc_link *link = aconnector->dc_link;
2524         unsigned int backlight;
2525
2526         backlight = dc_link_get_target_backlight_pwm(link);
2527         seq_printf(m, "0x%x\n", backlight);
2528
2529         return 0;
2530 }
2531
2532 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2533 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2534 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2535 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2536 #ifdef CONFIG_DRM_AMD_DC_HDCP
2537 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2538 #endif
2539 DEFINE_SHOW_ATTRIBUTE(internal_display);
2540 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2541
2542 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2543         .owner = THIS_MODULE,
2544         .read = dp_dsc_clock_en_read,
2545         .write = dp_dsc_clock_en_write,
2546         .llseek = default_llseek
2547 };
2548
2549 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2550         .owner = THIS_MODULE,
2551         .read = dp_dsc_slice_width_read,
2552         .write = dp_dsc_slice_width_write,
2553         .llseek = default_llseek
2554 };
2555
2556 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2557         .owner = THIS_MODULE,
2558         .read = dp_dsc_slice_height_read,
2559         .write = dp_dsc_slice_height_write,
2560         .llseek = default_llseek
2561 };
2562
2563 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2564         .owner = THIS_MODULE,
2565         .read = dp_dsc_bits_per_pixel_read,
2566         .write = dp_dsc_bits_per_pixel_write,
2567         .llseek = default_llseek
2568 };
2569
2570 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2571         .owner = THIS_MODULE,
2572         .read = dp_dsc_pic_width_read,
2573         .llseek = default_llseek
2574 };
2575
2576 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2577         .owner = THIS_MODULE,
2578         .read = dp_dsc_pic_height_read,
2579         .llseek = default_llseek
2580 };
2581
2582 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2583         .owner = THIS_MODULE,
2584         .read = dp_dsc_chunk_size_read,
2585         .llseek = default_llseek
2586 };
2587
2588 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2589         .owner = THIS_MODULE,
2590         .read = dp_dsc_slice_bpg_offset_read,
2591         .llseek = default_llseek
2592 };
2593
2594 static const struct file_operations trigger_hotplug_debugfs_fops = {
2595         .owner = THIS_MODULE,
2596         .write = trigger_hotplug,
2597         .llseek = default_llseek
2598 };
2599
2600 static const struct file_operations dp_link_settings_debugfs_fops = {
2601         .owner = THIS_MODULE,
2602         .read = dp_link_settings_read,
2603         .write = dp_link_settings_write,
2604         .llseek = default_llseek
2605 };
2606
2607 static const struct file_operations dp_phy_settings_debugfs_fop = {
2608         .owner = THIS_MODULE,
2609         .read = dp_phy_settings_read,
2610         .write = dp_phy_settings_write,
2611         .llseek = default_llseek
2612 };
2613
2614 static const struct file_operations dp_phy_test_pattern_fops = {
2615         .owner = THIS_MODULE,
2616         .write = dp_phy_test_pattern_debugfs_write,
2617         .llseek = default_llseek
2618 };
2619
2620 static const struct file_operations sdp_message_fops = {
2621         .owner = THIS_MODULE,
2622         .write = dp_sdp_message_debugfs_write,
2623         .llseek = default_llseek
2624 };
2625
2626 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2627         .owner = THIS_MODULE,
2628         .write = dp_dpcd_address_write,
2629         .llseek = default_llseek
2630 };
2631
2632 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2633         .owner = THIS_MODULE,
2634         .write = dp_dpcd_size_write,
2635         .llseek = default_llseek
2636 };
2637
2638 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2639         .owner = THIS_MODULE,
2640         .read = dp_dpcd_data_read,
2641         .write = dp_dpcd_data_write,
2642         .llseek = default_llseek
2643 };
2644
2645 static const struct file_operations dp_max_bpc_debugfs_fops = {
2646         .owner = THIS_MODULE,
2647         .read = dp_max_bpc_read,
2648         .write = dp_max_bpc_write,
2649         .llseek = default_llseek
2650 };
2651
2652 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2653         .owner = THIS_MODULE,
2654         .write = dp_dsc_passthrough_set,
2655         .llseek = default_llseek
2656 };
2657
2658 static const struct {
2659         char *name;
2660         const struct file_operations *fops;
2661 } dp_debugfs_entries[] = {
2662                 {"link_settings", &dp_link_settings_debugfs_fops},
2663                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2664                 {"lttpr_status", &dp_lttpr_status_fops},
2665                 {"test_pattern", &dp_phy_test_pattern_fops},
2666 #ifdef CONFIG_DRM_AMD_DC_HDCP
2667                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2668 #endif
2669                 {"sdp_message", &sdp_message_fops},
2670                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2671                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2672                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2673                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2674                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2675                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2676                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2677                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2678                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2679                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2680                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2681                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2682                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2683                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2684 };
2685
2686 #ifdef CONFIG_DRM_AMD_DC_HDCP
2687 static const struct {
2688         char *name;
2689         const struct file_operations *fops;
2690 } hdmi_debugfs_entries[] = {
2691                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2692 };
2693 #endif
2694 /*
2695  * Force YUV420 output if available from the given mode
2696  */
2697 static int force_yuv420_output_set(void *data, u64 val)
2698 {
2699         struct amdgpu_dm_connector *connector = data;
2700
2701         connector->force_yuv420_output = (bool)val;
2702
2703         return 0;
2704 }
2705
2706 /*
2707  * Check if YUV420 is forced when available from the given mode
2708  */
2709 static int force_yuv420_output_get(void *data, u64 *val)
2710 {
2711         struct amdgpu_dm_connector *connector = data;
2712
2713         *val = connector->force_yuv420_output;
2714
2715         return 0;
2716 }
2717
2718 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2719                          force_yuv420_output_set, "%llu\n");
2720
2721 /*
2722  *  Read PSR state
2723  */
2724 static int psr_get(void *data, u64 *val)
2725 {
2726         struct amdgpu_dm_connector *connector = data;
2727         struct dc_link *link = connector->dc_link;
2728         enum dc_psr_state state = PSR_STATE0;
2729
2730         dc_link_get_psr_state(link, &state);
2731
2732         *val = state;
2733
2734         return 0;
2735 }
2736
2737 /*
2738  * Set dmcub trace event IRQ enable or disable.
2739  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2740  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2741  */
2742 static int dmcub_trace_event_state_set(void *data, u64 val)
2743 {
2744         struct amdgpu_device *adev = data;
2745
2746         if (val == 1 || val == 0) {
2747                 dc_dmub_trace_event_control(adev->dm.dc, val);
2748                 adev->dm.dmcub_trace_event_en = (bool)val;
2749         } else
2750                 return 0;
2751
2752         return 0;
2753 }
2754
2755 /*
2756  * The interface doesn't need get function, so it will return the
2757  * value of zero
2758  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2759  */
2760 static int dmcub_trace_event_state_get(void *data, u64 *val)
2761 {
2762         struct amdgpu_device *adev = data;
2763
2764         *val = adev->dm.dmcub_trace_event_en;
2765         return 0;
2766 }
2767
2768 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2769                          dmcub_trace_event_state_set, "%llu\n");
2770
2771 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2772
2773 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2774 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2775
2776 static const struct {
2777         char *name;
2778         const struct file_operations *fops;
2779 } connector_debugfs_entries[] = {
2780                 {"force_yuv420_output", &force_yuv420_output_fops},
2781                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2782                 {"internal_display", &internal_display_fops}
2783 };
2784
2785 /*
2786  * Returns supported customized link rates by this eDP panel.
2787  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2788  */
2789 static int edp_ilr_show(struct seq_file *m, void *unused)
2790 {
2791         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2792         struct dc_link *link = aconnector->dc_link;
2793         uint8_t supported_link_rates[16];
2794         uint32_t link_rate_in_khz;
2795         uint32_t entry = 0;
2796         uint8_t dpcd_rev;
2797
2798         memset(supported_link_rates, 0, sizeof(supported_link_rates));
2799         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
2800                 supported_link_rates, sizeof(supported_link_rates));
2801
2802         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
2803
2804         if (dpcd_rev >= DP_DPCD_REV_13 &&
2805                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
2806
2807                 for (entry = 0; entry < 16; entry += 2) {
2808                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2809                                                                                 supported_link_rates[entry]) * 200;
2810                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
2811                 }
2812         } else {
2813                 seq_printf(m, "ILR is not supported by this eDP panel.\n");
2814         }
2815
2816         return 0;
2817 }
2818
2819 /*
2820  * Set supported customized link rate to eDP panel.
2821  *
2822  * echo <lane_count>  <link_rate option> > ilr_setting
2823  *
2824  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
2825  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2826  * to set 4 lanes and 2.16 GHz
2827  */
2828 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
2829                                  size_t size, loff_t *pos)
2830 {
2831         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
2832         struct dc_link *link = connector->dc_link;
2833         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
2834         struct dc *dc = (struct dc *)link->dc;
2835         struct dc_link_settings prefer_link_settings;
2836         char *wr_buf = NULL;
2837         const uint32_t wr_buf_size = 40;
2838         /* 0: lane_count; 1: link_rate */
2839         int max_param_num = 2;
2840         uint8_t param_nums = 0;
2841         long param[2];
2842         bool valid_input = true;
2843
2844         if (size == 0)
2845                 return -EINVAL;
2846
2847         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2848         if (!wr_buf)
2849                 return -ENOMEM;
2850
2851         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2852                                            (long *)param, buf,
2853                                            max_param_num,
2854                                            &param_nums)) {
2855                 kfree(wr_buf);
2856                 return -EINVAL;
2857         }
2858
2859         if (param_nums <= 0) {
2860                 kfree(wr_buf);
2861                 return -EINVAL;
2862         }
2863
2864         switch (param[0]) {
2865         case LANE_COUNT_ONE:
2866         case LANE_COUNT_TWO:
2867         case LANE_COUNT_FOUR:
2868                 break;
2869         default:
2870                 valid_input = false;
2871                 break;
2872         }
2873
2874         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
2875                 valid_input = false;
2876
2877         if (!valid_input) {
2878                 kfree(wr_buf);
2879                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
2880                 prefer_link_settings.use_link_rate_set = false;
2881                 mutex_lock(&adev->dm.dc_lock);
2882                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
2883                 mutex_unlock(&adev->dm.dc_lock);
2884                 return size;
2885         }
2886
2887         /* save user force lane_count, link_rate to preferred settings
2888          * spread spectrum will not be changed
2889          */
2890         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
2891         prefer_link_settings.lane_count = param[0];
2892         prefer_link_settings.use_link_rate_set = true;
2893         prefer_link_settings.link_rate_set = param[1];
2894         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
2895
2896         mutex_lock(&adev->dm.dc_lock);
2897         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
2898                                                 NULL, link, false);
2899         mutex_unlock(&adev->dm.dc_lock);
2900
2901         kfree(wr_buf);
2902         return size;
2903 }
2904
2905 static int edp_ilr_open(struct inode *inode, struct file *file)
2906 {
2907         return single_open(file, edp_ilr_show, inode->i_private);
2908 }
2909
2910 static const struct file_operations edp_ilr_debugfs_fops = {
2911         .owner = THIS_MODULE,
2912         .open = edp_ilr_open,
2913         .read = seq_read,
2914         .llseek = seq_lseek,
2915         .release = single_release,
2916         .write = edp_ilr_write
2917 };
2918
2919 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2920 {
2921         int i;
2922         struct dentry *dir = connector->base.debugfs_entry;
2923
2924         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2925             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2926                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2927                         debugfs_create_file(dp_debugfs_entries[i].name,
2928                                             0644, dir, connector,
2929                                             dp_debugfs_entries[i].fops);
2930                 }
2931         }
2932         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2933                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
2934                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2935                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
2936                                     &current_backlight_fops);
2937                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
2938                                     &target_backlight_fops);
2939                 debugfs_create_file("ilr_setting", 0644, dir, connector,
2940                                         &edp_ilr_debugfs_fops);
2941         }
2942
2943         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
2944                 debugfs_create_file(connector_debugfs_entries[i].name,
2945                                     0644, dir, connector,
2946                                     connector_debugfs_entries[i].fops);
2947         }
2948
2949         connector->debugfs_dpcd_address = 0;
2950         connector->debugfs_dpcd_size = 0;
2951
2952 #ifdef CONFIG_DRM_AMD_DC_HDCP
2953         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2954                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2955                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2956                                             0644, dir, connector,
2957                                             hdmi_debugfs_entries[i].fops);
2958                 }
2959         }
2960 #endif
2961 }
2962
2963 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2964 /*
2965  * Set crc window coordinate x start
2966  */
2967 static int crc_win_x_start_set(void *data, u64 val)
2968 {
2969         struct drm_crtc *crtc = data;
2970         struct drm_device *drm_dev = crtc->dev;
2971         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2972
2973         spin_lock_irq(&drm_dev->event_lock);
2974         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
2975         acrtc->dm_irq_params.crc_window.update_win = false;
2976         spin_unlock_irq(&drm_dev->event_lock);
2977
2978         return 0;
2979 }
2980
2981 /*
2982  * Get crc window coordinate x start
2983  */
2984 static int crc_win_x_start_get(void *data, u64 *val)
2985 {
2986         struct drm_crtc *crtc = data;
2987         struct drm_device *drm_dev = crtc->dev;
2988         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2989
2990         spin_lock_irq(&drm_dev->event_lock);
2991         *val = acrtc->dm_irq_params.crc_window.x_start;
2992         spin_unlock_irq(&drm_dev->event_lock);
2993
2994         return 0;
2995 }
2996
2997 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
2998                          crc_win_x_start_set, "%llu\n");
2999
3000
3001 /*
3002  * Set crc window coordinate y start
3003  */
3004 static int crc_win_y_start_set(void *data, u64 val)
3005 {
3006         struct drm_crtc *crtc = data;
3007         struct drm_device *drm_dev = crtc->dev;
3008         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3009
3010         spin_lock_irq(&drm_dev->event_lock);
3011         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
3012         acrtc->dm_irq_params.crc_window.update_win = false;
3013         spin_unlock_irq(&drm_dev->event_lock);
3014
3015         return 0;
3016 }
3017
3018 /*
3019  * Get crc window coordinate y start
3020  */
3021 static int crc_win_y_start_get(void *data, u64 *val)
3022 {
3023         struct drm_crtc *crtc = data;
3024         struct drm_device *drm_dev = crtc->dev;
3025         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3026
3027         spin_lock_irq(&drm_dev->event_lock);
3028         *val = acrtc->dm_irq_params.crc_window.y_start;
3029         spin_unlock_irq(&drm_dev->event_lock);
3030
3031         return 0;
3032 }
3033
3034 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3035                          crc_win_y_start_set, "%llu\n");
3036
3037 /*
3038  * Set crc window coordinate x end
3039  */
3040 static int crc_win_x_end_set(void *data, u64 val)
3041 {
3042         struct drm_crtc *crtc = data;
3043         struct drm_device *drm_dev = crtc->dev;
3044         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3045
3046         spin_lock_irq(&drm_dev->event_lock);
3047         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
3048         acrtc->dm_irq_params.crc_window.update_win = false;
3049         spin_unlock_irq(&drm_dev->event_lock);
3050
3051         return 0;
3052 }
3053
3054 /*
3055  * Get crc window coordinate x end
3056  */
3057 static int crc_win_x_end_get(void *data, u64 *val)
3058 {
3059         struct drm_crtc *crtc = data;
3060         struct drm_device *drm_dev = crtc->dev;
3061         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3062
3063         spin_lock_irq(&drm_dev->event_lock);
3064         *val = acrtc->dm_irq_params.crc_window.x_end;
3065         spin_unlock_irq(&drm_dev->event_lock);
3066
3067         return 0;
3068 }
3069
3070 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3071                          crc_win_x_end_set, "%llu\n");
3072
3073 /*
3074  * Set crc window coordinate y end
3075  */
3076 static int crc_win_y_end_set(void *data, u64 val)
3077 {
3078         struct drm_crtc *crtc = data;
3079         struct drm_device *drm_dev = crtc->dev;
3080         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3081
3082         spin_lock_irq(&drm_dev->event_lock);
3083         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
3084         acrtc->dm_irq_params.crc_window.update_win = false;
3085         spin_unlock_irq(&drm_dev->event_lock);
3086
3087         return 0;
3088 }
3089
3090 /*
3091  * Get crc window coordinate y end
3092  */
3093 static int crc_win_y_end_get(void *data, u64 *val)
3094 {
3095         struct drm_crtc *crtc = data;
3096         struct drm_device *drm_dev = crtc->dev;
3097         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3098
3099         spin_lock_irq(&drm_dev->event_lock);
3100         *val = acrtc->dm_irq_params.crc_window.y_end;
3101         spin_unlock_irq(&drm_dev->event_lock);
3102
3103         return 0;
3104 }
3105
3106 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3107                          crc_win_y_end_set, "%llu\n");
3108 /*
3109  * Trigger to commit crc window
3110  */
3111 static int crc_win_update_set(void *data, u64 val)
3112 {
3113         struct drm_crtc *new_crtc = data;
3114         struct drm_crtc *old_crtc = NULL;
3115         struct amdgpu_crtc *new_acrtc, *old_acrtc;
3116         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
3117         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
3118
3119         if (!crc_rd_wrk)
3120                 return 0;
3121
3122         if (val) {
3123                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3124                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
3125                 if (crc_rd_wrk->crtc) {
3126                         old_crtc = crc_rd_wrk->crtc;
3127                         old_acrtc = to_amdgpu_crtc(old_crtc);
3128                 }
3129                 new_acrtc = to_amdgpu_crtc(new_crtc);
3130
3131                 if (old_crtc && old_crtc != new_crtc) {
3132                         old_acrtc->dm_irq_params.crc_window.activated = false;
3133                         old_acrtc->dm_irq_params.crc_window.update_win = false;
3134                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3135
3136                         new_acrtc->dm_irq_params.crc_window.activated = true;
3137                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3138                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3139                         crc_rd_wrk->crtc = new_crtc;
3140                 } else {
3141                         new_acrtc->dm_irq_params.crc_window.activated = true;
3142                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3143                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3144                         crc_rd_wrk->crtc = new_crtc;
3145                 }
3146                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
3147                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3148         }
3149
3150         return 0;
3151 }
3152
3153 /*
3154  * Get crc window update flag
3155  */
3156 static int crc_win_update_get(void *data, u64 *val)
3157 {
3158         *val = 0;
3159         return 0;
3160 }
3161
3162 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3163                          crc_win_update_set, "%llu\n");
3164 #endif
3165 void crtc_debugfs_init(struct drm_crtc *crtc)
3166 {
3167 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3168         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3169
3170         if (!dir)
3171                 return;
3172
3173         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3174                                    &crc_win_x_start_fops);
3175         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3176                                    &crc_win_y_start_fops);
3177         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3178                                    &crc_win_x_end_fops);
3179         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3180                                    &crc_win_y_end_fops);
3181         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3182                                    &crc_win_update_fops);
3183 #endif
3184         debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3185                             crtc, &amdgpu_current_bpc_fops);
3186 }
3187
3188 /*
3189  * Writes DTN log state to the user supplied buffer.
3190  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3191  */
3192 static ssize_t dtn_log_read(
3193         struct file *f,
3194         char __user *buf,
3195         size_t size,
3196         loff_t *pos)
3197 {
3198         struct amdgpu_device *adev = file_inode(f)->i_private;
3199         struct dc *dc = adev->dm.dc;
3200         struct dc_log_buffer_ctx log_ctx = { 0 };
3201         ssize_t result = 0;
3202
3203         if (!buf || !size)
3204                 return -EINVAL;
3205
3206         if (!dc->hwss.log_hw_state)
3207                 return 0;
3208
3209         dc->hwss.log_hw_state(dc, &log_ctx);
3210
3211         if (*pos < log_ctx.pos) {
3212                 size_t to_copy = log_ctx.pos - *pos;
3213
3214                 to_copy = min(to_copy, size);
3215
3216                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3217                         *pos += to_copy;
3218                         result = to_copy;
3219                 }
3220         }
3221
3222         kfree(log_ctx.buf);
3223
3224         return result;
3225 }
3226
3227 /*
3228  * Writes DTN log state to dmesg when triggered via a write.
3229  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3230  */
3231 static ssize_t dtn_log_write(
3232         struct file *f,
3233         const char __user *buf,
3234         size_t size,
3235         loff_t *pos)
3236 {
3237         struct amdgpu_device *adev = file_inode(f)->i_private;
3238         struct dc *dc = adev->dm.dc;
3239
3240         /* Write triggers log output via dmesg. */
3241         if (size == 0)
3242                 return 0;
3243
3244         if (dc->hwss.log_hw_state)
3245                 dc->hwss.log_hw_state(dc, NULL);
3246
3247         return size;
3248 }
3249
3250 static int mst_topo_show(struct seq_file *m, void *unused)
3251 {
3252         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3253         struct drm_device *dev = adev_to_drm(adev);
3254         struct drm_connector *connector;
3255         struct drm_connector_list_iter conn_iter;
3256         struct amdgpu_dm_connector *aconnector;
3257
3258         drm_connector_list_iter_begin(dev, &conn_iter);
3259         drm_for_each_connector_iter(connector, &conn_iter) {
3260                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3261                         continue;
3262
3263                 aconnector = to_amdgpu_dm_connector(connector);
3264
3265                 /* Ensure we're only dumping the topology of a root mst node */
3266                 if (!aconnector->mst_mgr.mst_state)
3267                         continue;
3268
3269                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3270                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3271         }
3272         drm_connector_list_iter_end(&conn_iter);
3273
3274         return 0;
3275 }
3276
3277 /*
3278  * Sets trigger hpd for MST topologies.
3279  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3280  * All topologies will be disconnected if val of 0 is set .
3281  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3282  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3283  */
3284 static int trigger_hpd_mst_set(void *data, u64 val)
3285 {
3286         struct amdgpu_device *adev = data;
3287         struct drm_device *dev = adev_to_drm(adev);
3288         struct drm_connector_list_iter iter;
3289         struct amdgpu_dm_connector *aconnector;
3290         struct drm_connector *connector;
3291         struct dc_link *link = NULL;
3292
3293         if (val == 1) {
3294                 drm_connector_list_iter_begin(dev, &iter);
3295                 drm_for_each_connector_iter(connector, &iter) {
3296                         aconnector = to_amdgpu_dm_connector(connector);
3297                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3298                             aconnector->mst_mgr.aux) {
3299                                 mutex_lock(&adev->dm.dc_lock);
3300                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3301                                 mutex_unlock(&adev->dm.dc_lock);
3302
3303                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3304                         }
3305                 }
3306         } else if (val == 0) {
3307                 drm_connector_list_iter_begin(dev, &iter);
3308                 drm_for_each_connector_iter(connector, &iter) {
3309                         aconnector = to_amdgpu_dm_connector(connector);
3310                         if (!aconnector->dc_link)
3311                                 continue;
3312
3313                         if (!aconnector->mst_port)
3314                                 continue;
3315
3316                         link = aconnector->dc_link;
3317                         dp_receiver_power_ctrl(link, false);
3318                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false);
3319                         link->mst_stream_alloc_table.stream_count = 0;
3320                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3321                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3322                 }
3323         } else {
3324                 return 0;
3325         }
3326         drm_kms_helper_hotplug_event(dev);
3327
3328         return 0;
3329 }
3330
3331 /*
3332  * The interface doesn't need get function, so it will return the
3333  * value of zero
3334  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3335  */
3336 static int trigger_hpd_mst_get(void *data, u64 *val)
3337 {
3338         *val = 0;
3339         return 0;
3340 }
3341
3342 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3343                          trigger_hpd_mst_set, "%llu\n");
3344
3345
3346 /*
3347  * Sets the force_timing_sync debug option from the given string.
3348  * All connected displays will be force synchronized immediately.
3349  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3350  */
3351 static int force_timing_sync_set(void *data, u64 val)
3352 {
3353         struct amdgpu_device *adev = data;
3354
3355         adev->dm.force_timing_sync = (bool)val;
3356
3357         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3358
3359         return 0;
3360 }
3361
3362 /*
3363  * Gets the force_timing_sync debug option value into the given buffer.
3364  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3365  */
3366 static int force_timing_sync_get(void *data, u64 *val)
3367 {
3368         struct amdgpu_device *adev = data;
3369
3370         *val = adev->dm.force_timing_sync;
3371
3372         return 0;
3373 }
3374
3375 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3376                          force_timing_sync_set, "%llu\n");
3377
3378
3379 /*
3380  * Disables all HPD and HPD RX interrupt handling in the
3381  * driver when set to 1. Default is 0.
3382  */
3383 static int disable_hpd_set(void *data, u64 val)
3384 {
3385         struct amdgpu_device *adev = data;
3386
3387         adev->dm.disable_hpd_irq = (bool)val;
3388
3389         return 0;
3390 }
3391
3392
3393 /*
3394  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3395  * 0 otherwise.
3396  */
3397 static int disable_hpd_get(void *data, u64 *val)
3398 {
3399         struct amdgpu_device *adev = data;
3400
3401         *val = adev->dm.disable_hpd_irq;
3402
3403         return 0;
3404 }
3405
3406 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3407                          disable_hpd_set, "%llu\n");
3408
3409 /*
3410  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3411  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3412  */
3413 static int dp_force_sst_set(void *data, u64 val)
3414 {
3415         struct amdgpu_device *adev = data;
3416
3417         adev->dm.dc->debug.set_mst_en_for_sst = val;
3418
3419         return 0;
3420 }
3421
3422 static int dp_force_sst_get(void *data, u64 *val)
3423 {
3424         struct amdgpu_device *adev = data;
3425
3426         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3427
3428         return 0;
3429 }
3430 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3431                          dp_force_sst_set, "%llu\n");
3432
3433 /*
3434  * Force DP2 sequence without VESA certified cable.
3435  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3436  */
3437 static int dp_ignore_cable_id_set(void *data, u64 val)
3438 {
3439         struct amdgpu_device *adev = data;
3440
3441         adev->dm.dc->debug.ignore_cable_id = val;
3442
3443         return 0;
3444 }
3445
3446 static int dp_ignore_cable_id_get(void *data, u64 *val)
3447 {
3448         struct amdgpu_device *adev = data;
3449
3450         *val = adev->dm.dc->debug.ignore_cable_id;
3451
3452         return 0;
3453 }
3454 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3455                          dp_ignore_cable_id_set, "%llu\n");
3456
3457 /*
3458  * Sets the DC visual confirm debug option from the given string.
3459  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3460  */
3461 static int visual_confirm_set(void *data, u64 val)
3462 {
3463         struct amdgpu_device *adev = data;
3464
3465         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3466
3467         return 0;
3468 }
3469
3470 /*
3471  * Reads the DC visual confirm debug option value into the given buffer.
3472  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3473  */
3474 static int visual_confirm_get(void *data, u64 *val)
3475 {
3476         struct amdgpu_device *adev = data;
3477
3478         *val = adev->dm.dc->debug.visual_confirm;
3479
3480         return 0;
3481 }
3482
3483 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3484 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3485                          visual_confirm_set, "%llu\n");
3486
3487
3488 /*
3489  * Sets the DC skip_detection_link_training debug option from the given string.
3490  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
3491  */
3492 static int skip_detection_link_training_set(void *data, u64 val)
3493 {
3494         struct amdgpu_device *adev = data;
3495
3496         if (val == 0)
3497                 adev->dm.dc->debug.skip_detection_link_training = false;
3498         else
3499                 adev->dm.dc->debug.skip_detection_link_training = true;
3500
3501         return 0;
3502 }
3503
3504 /*
3505  * Reads the DC skip_detection_link_training debug option value into the given buffer.
3506  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
3507  */
3508 static int skip_detection_link_training_get(void *data, u64 *val)
3509 {
3510         struct amdgpu_device *adev = data;
3511
3512         *val = adev->dm.dc->debug.skip_detection_link_training;
3513
3514         return 0;
3515 }
3516
3517 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
3518                          skip_detection_link_training_get,
3519                          skip_detection_link_training_set, "%llu\n");
3520
3521 /*
3522  * Dumps the DCC_EN bit for each pipe.
3523  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3524  */
3525 static ssize_t dcc_en_bits_read(
3526         struct file *f,
3527         char __user *buf,
3528         size_t size,
3529         loff_t *pos)
3530 {
3531         struct amdgpu_device *adev = file_inode(f)->i_private;
3532         struct dc *dc = adev->dm.dc;
3533         char *rd_buf = NULL;
3534         const uint32_t rd_buf_size = 32;
3535         uint32_t result = 0;
3536         int offset = 0;
3537         int num_pipes = dc->res_pool->pipe_count;
3538         int *dcc_en_bits;
3539         int i, r;
3540
3541         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3542         if (!dcc_en_bits)
3543                 return -ENOMEM;
3544
3545         if (!dc->hwss.get_dcc_en_bits) {
3546                 kfree(dcc_en_bits);
3547                 return 0;
3548         }
3549
3550         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3551
3552         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3553         if (!rd_buf) {
3554                 kfree(dcc_en_bits);
3555                 return -ENOMEM;
3556         }
3557
3558         for (i = 0; i < num_pipes; i++)
3559                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3560                                    "%d  ", dcc_en_bits[i]);
3561         rd_buf[strlen(rd_buf)] = '\n';
3562
3563         kfree(dcc_en_bits);
3564
3565         while (size) {
3566                 if (*pos >= rd_buf_size)
3567                         break;
3568                 r = put_user(*(rd_buf + result), buf);
3569                 if (r) {
3570                         kfree(rd_buf);
3571                         return r; /* r = -EFAULT */
3572                 }
3573                 buf += 1;
3574                 size -= 1;
3575                 *pos += 1;
3576                 result += 1;
3577         }
3578
3579         kfree(rd_buf);
3580         return result;
3581 }
3582
3583 void dtn_debugfs_init(struct amdgpu_device *adev)
3584 {
3585         static const struct file_operations dtn_log_fops = {
3586                 .owner = THIS_MODULE,
3587                 .read = dtn_log_read,
3588                 .write = dtn_log_write,
3589                 .llseek = default_llseek
3590         };
3591         static const struct file_operations dcc_en_bits_fops = {
3592                 .owner = THIS_MODULE,
3593                 .read = dcc_en_bits_read,
3594                 .llseek = default_llseek
3595         };
3596
3597         struct drm_minor *minor = adev_to_drm(adev)->primary;
3598         struct dentry *root = minor->debugfs_root;
3599
3600         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3601                             adev, &mst_topo_fops);
3602         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3603                             &dtn_log_fops);
3604         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
3605                                 &dp_set_mst_en_for_sst_ops);
3606         debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
3607                                 &dp_ignore_cable_id_ops);
3608
3609         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3610                                    &visual_confirm_fops);
3611
3612         debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
3613                                    &skip_detection_link_training_fops);
3614
3615         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3616                                    adev, &dmub_tracebuffer_fops);
3617
3618         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3619                                    adev, &dmub_fw_state_fops);
3620
3621         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3622                                    adev, &force_timing_sync_ops);
3623
3624         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3625                                    adev, &dmcub_trace_event_state_fops);
3626
3627         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3628                                    adev, &trigger_hpd_mst_ops);
3629
3630         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3631                                    &dcc_en_bits_fops);
3632
3633         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3634                                    &disable_hpd_ops);
3635
3636 }