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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/dp/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
47 #define AMDGPU_DM_MAX_CRTC 6
49 #define AMDGPU_DM_MAX_NUM_EDP 2
51 #define AMDGPU_DMUB_NOTIFICATION_MAX 5
54 * DMUB Async to Sync Mechanism Status
56 #define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1
57 #define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2
58 #define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3
60 #include "include/amdgpu_dal_power_if.h"
61 #include "amdgpu_dm_irq.h"
64 #include "irq_types.h"
65 #include "signal_types.h"
66 #include "amdgpu_dm_crc.h"
68 enum aux_return_code_type;
70 /* Forward declarations */
77 struct dc_plane_state;
78 struct dmub_notification;
80 struct common_irq_params {
81 struct amdgpu_device *adev;
82 enum dc_irq_source irq_src;
83 atomic64_t previous_timestamp;
87 * struct dm_compressor_info - Buffer info used by frame buffer compression
88 * @cpu_addr: MMIO cpu addr
89 * @bo_ptr: Pointer to the buffer object
90 * @gpu_addr: MMIO gpu addr
92 struct dm_compressor_info {
94 struct amdgpu_bo *bo_ptr;
98 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
101 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
103 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq
104 * @dmub_notify: notification for callback function
105 * @adev: amdgpu_device pointer
107 struct dmub_hpd_work {
108 struct work_struct handle_hpd_work;
109 struct dmub_notification *dmub_notify;
110 struct amdgpu_device *adev;
114 * struct vblank_control_work - Work data for vblank control
115 * @work: Kernel work data for the work event
116 * @dm: amdgpu display manager device
117 * @acrtc: amdgpu CRTC instance for which the event has occurred
118 * @stream: DC stream for which the event has occurred
119 * @enable: true if enabling vblank
121 struct vblank_control_work {
122 struct work_struct work;
123 struct amdgpu_display_manager *dm;
124 struct amdgpu_crtc *acrtc;
125 struct dc_stream_state *stream;
130 * struct amdgpu_dm_backlight_caps - Information about backlight
132 * Describe the backlight support for ACPI or eDP AUX.
134 struct amdgpu_dm_backlight_caps {
136 * @ext_caps: Keep the data struct with all the information about the
137 * display support for HDR.
139 union dpcd_sink_ext_caps *ext_caps;
141 * @aux_min_input_signal: Min brightness value supported by the display
143 u32 aux_min_input_signal;
145 * @aux_max_input_signal: Max brightness value supported by the display
148 u32 aux_max_input_signal;
150 * @min_input_signal: minimum possible input in range 0-255.
152 int min_input_signal;
154 * @max_input_signal: maximum possible input in range 0-255.
156 int max_input_signal;
158 * @caps_valid: true if these values are from the ACPI interface.
162 * @aux_support: Describes if the display supports AUX backlight.
168 * struct dal_allocation - Tracks mapped FB memory for SMU communication
169 * @list: list of dal allocations
170 * @bo: GPU buffer object
171 * @cpu_ptr: CPU virtual address of the GPU buffer object
172 * @gpu_addr: GPU virtual address of the GPU buffer object
174 struct dal_allocation {
175 struct list_head list;
176 struct amdgpu_bo *bo;
182 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
185 struct hpd_rx_irq_offload_work_queue {
187 * @wq: workqueue structure to queue offload work.
189 struct workqueue_struct *wq;
191 * @offload_lock: To protect fields of offload work queue.
193 spinlock_t offload_lock;
195 * @is_handling_link_loss: Used to prevent inserting link loss event when
196 * we're handling link loss
198 bool is_handling_link_loss;
200 * @aconnector: The aconnector that this work queue is attached to
202 struct amdgpu_dm_connector *aconnector;
206 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure
208 struct hpd_rx_irq_offload_work {
210 * @work: offload work
212 struct work_struct work;
214 * @data: reference irq data which is used while handling offload work
216 union hpd_irq_data data;
218 * @offload_wq: offload work queue that this work is queued to
220 struct hpd_rx_irq_offload_work_queue *offload_wq;
224 * struct amdgpu_display_manager - Central amdgpu display manager device
226 * @dc: Display Core control structure
227 * @adev: AMDGPU base driver structure
228 * @ddev: DRM base driver structure
229 * @display_indexes_num: Max number of display streams supported
230 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
231 * @backlight_dev: Backlight control device
232 * @backlight_link: Link on which to control backlight
233 * @backlight_caps: Capabilities of the backlight device
234 * @freesync_module: Module handling freesync calculations
235 * @hdcp_workqueue: AMDGPU content protection queue
236 * @fw_dmcu: Reference to DMCU firmware
237 * @dmcu_fw_version: Version of the DMCU firmware
238 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
239 * @cached_state: Caches device atomic state for suspend/resume
240 * @cached_dc_state: Cached state of content streams
241 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
242 * @force_timing_sync: set via debugfs. When set, indicates that all connected
243 * displays will be forced to synchronize.
244 * @dmcub_trace_event_en: enable dmcub trace events
246 struct amdgpu_display_manager {
253 * DMUB service, used for controlling the DMUB on hardware
254 * that supports it. The pointer to the dmub_srv will be
255 * NULL on hardware that does not support it.
257 struct dmub_srv *dmub_srv;
262 * Notification from DMUB.
265 struct dmub_notification *dmub_notify;
270 * Callback functions to handle notification from DMUB.
273 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
276 * @dmub_thread_offload:
278 * Flag to indicate if callback is offload.
281 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
286 * Framebuffer regions for the DMUB.
288 struct dmub_srv_fb_info *dmub_fb_info;
293 * DMUB firmware, required on hardware that has DMUB support.
295 const struct firmware *dmub_fw;
300 * Buffer object for the DMUB.
302 struct amdgpu_bo *dmub_bo;
307 * GPU virtual address for the DMUB buffer object.
309 u64 dmub_bo_gpu_addr;
314 * CPU address for the DMUB buffer object.
316 void *dmub_bo_cpu_addr;
321 * DMCUB firmware version.
323 uint32_t dmcub_fw_version;
328 * The Common Graphics Services device. It provides an interface for
329 * accessing registers.
331 struct cgs_device *cgs_device;
333 struct amdgpu_device *adev;
334 struct drm_device *ddev;
335 u16 display_indexes_num;
340 * In combination with &dm_atomic_state it helps manage
341 * global atomic state that doesn't map cleanly into existing
342 * drm resources, like &dc_context.
344 struct drm_private_obj atomic_obj;
349 * Guards access to DC functions that can issue register write
352 struct mutex dc_lock;
357 * Guards access to audio instance changes.
359 struct mutex audio_lock;
361 #if defined(CONFIG_DRM_AMD_DC_DCN)
365 * Guards access to deferred vblank work state.
367 spinlock_t vblank_lock;
373 * Used to notify ELD changes to sound driver.
375 struct drm_audio_component *audio_component;
380 * True if the audio component has been registered
381 * successfully, false otherwise.
383 bool audio_registered;
386 * @irq_handler_list_low_tab:
388 * Low priority IRQ handler table.
390 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
391 * source. Low priority IRQ handlers are deferred to a workqueue to be
392 * processed. Hence, they can sleep.
394 * Note that handlers are called in the same order as they were
397 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
400 * @irq_handler_list_high_tab:
402 * High priority IRQ handler table.
404 * It is a n*m table, same as &irq_handler_list_low_tab. However,
405 * handlers in this table are not deferred and are called immediately.
407 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
412 * Page flip IRQ parameters, passed to registered handlers when
415 struct common_irq_params
416 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
421 * Vertical blanking IRQ parameters, passed to registered handlers when
424 struct common_irq_params
425 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
430 * OTG vertical interrupt0 IRQ parameters, passed to registered
431 * handlers when triggered.
433 struct common_irq_params
434 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
439 * Vertical update IRQ parameters, passed to registered handlers when
442 struct common_irq_params
443 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
446 * @dmub_trace_params:
448 * DMUB trace event IRQ parameters, passed to registered handlers when
451 struct common_irq_params
452 dmub_trace_params[1];
454 struct common_irq_params
455 dmub_outbox_params[1];
457 spinlock_t irq_handler_list_table_lock;
459 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
461 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
465 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
467 struct mod_freesync *freesync_module;
468 #ifdef CONFIG_DRM_AMD_DC_HDCP
469 struct hdcp_workqueue *hdcp_workqueue;
472 #if defined(CONFIG_DRM_AMD_DC_DCN)
474 * @vblank_control_workqueue:
476 * Deferred work for vblank control events.
478 struct workqueue_struct *vblank_control_workqueue;
481 struct drm_atomic_state *cached_state;
482 struct dc_state *cached_dc_state;
484 struct dm_compressor_info compressor;
486 const struct firmware *fw_dmcu;
487 uint32_t dmcu_fw_version;
491 * gpu_info FW provided soc bounding box struct or 0 if not
494 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
496 #if defined(CONFIG_DRM_AMD_DC_DCN)
498 * @active_vblank_irq_count:
500 * number of currently active vblank irqs
502 uint32_t active_vblank_irq_count;
505 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
509 * Work to be executed in a separate thread to communicate with PSP.
511 struct crc_rd_work *crc_rd_wrk;
514 * @hpd_rx_offload_wq:
516 * Work queue to offload works of hpd_rx_irq
518 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
522 * fake encoders used for DP MST.
524 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
525 bool force_timing_sync;
526 bool disable_hpd_irq;
527 bool dmcub_trace_event_en;
531 * DAL fb memory allocation list, for communication with SMU.
533 struct list_head da_list;
534 struct completion dmub_aux_transfer_done;
535 struct workqueue_struct *delayed_hpd_wq;
540 * cached backlight values.
542 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
545 enum dsc_clock_force_state {
546 DSC_CLK_FORCE_DEFAULT = 0,
547 DSC_CLK_FORCE_ENABLE,
548 DSC_CLK_FORCE_DISABLE,
551 struct dsc_preferred_settings {
552 enum dsc_clock_force_state dsc_force_enable;
553 uint32_t dsc_num_slices_v;
554 uint32_t dsc_num_slices_h;
555 uint32_t dsc_bits_per_pixel;
556 bool dsc_force_disable_passthrough;
559 struct amdgpu_dm_connector {
561 struct drm_connector base;
562 uint32_t connector_id;
564 /* we need to mind the EDID between detect
565 and get modes due to analog/digital/tvencoder */
568 /* shared with amdgpu */
569 struct amdgpu_hpd hpd;
571 /* number of modes generated from EDID at 'dc_sink' */
574 /* The 'old' sink - before an HPD.
575 * The 'current' sink is in dc_link->sink. */
576 struct dc_sink *dc_sink;
577 struct dc_link *dc_link;
578 struct dc_sink *dc_em_sink;
581 struct drm_dp_mst_topology_mgr mst_mgr;
582 struct amdgpu_dm_dp_aux dm_dp_aux;
583 struct drm_dp_mst_port *port;
584 struct amdgpu_dm_connector *mst_port;
585 struct drm_dp_aux *dsc_aux;
587 /* TODO see if we can merge with ddc_bus or make a dm_connector */
588 struct amdgpu_i2c_adapter *i2c;
590 /* Monitor range limits */
595 /* Audio instance - protected by audio_lock. */
598 struct mutex hpd_lock;
601 #ifdef CONFIG_DEBUG_FS
602 uint32_t debugfs_dpcd_address;
603 uint32_t debugfs_dpcd_size;
605 bool force_yuv420_output;
606 struct dsc_preferred_settings dsc_settings;
607 union dp_downstream_port_present mst_downstream_port_present;
608 /* Cached display modes */
609 struct drm_display_mode freesync_vid_base;
614 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
616 extern const struct amdgpu_ip_block_version dm_ip_block;
618 struct dm_plane_state {
619 struct drm_plane_state base;
620 struct dc_plane_state *dc_state;
623 struct dm_crtc_state {
624 struct drm_crtc_state base;
625 struct dc_stream_state *stream;
628 bool cm_is_degamma_srgb;
637 bool freesync_timing_changed;
638 bool freesync_vrr_info_changed;
640 bool dsc_force_changed;
644 struct mod_freesync_config freesync_config;
645 struct dc_info_packet vrr_infopacket;
650 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
652 struct dm_atomic_state {
653 struct drm_private_state base;
655 struct dc_state *context;
658 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
660 struct dm_connector_state {
661 struct drm_connector_state base;
663 enum amdgpu_rmx_type scaling;
664 uint8_t underscan_vborder;
665 uint8_t underscan_hborder;
666 bool underscan_enable;
667 bool freesync_capable;
668 #ifdef CONFIG_DRM_AMD_DC_HDCP
676 struct amdgpu_hdmi_vsdb_info {
677 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */
678 bool freesync_supported; /* FreeSync Supported */
679 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */
680 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */
684 #define to_dm_connector_state(x)\
685 container_of((x), struct dm_connector_state, base)
687 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
688 struct drm_connector_state *
689 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
690 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
691 struct drm_connector_state *state,
692 struct drm_property *property,
695 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
696 const struct drm_connector_state *state,
697 struct drm_property *property,
700 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
702 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
703 struct amdgpu_dm_connector *aconnector,
705 struct dc_link *link,
708 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
709 struct drm_display_mode *mode);
711 void dm_restore_drm_connector_state(struct drm_device *dev,
712 struct drm_connector *connector);
714 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
717 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
719 #define MAX_COLOR_LUT_ENTRIES 4096
720 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
721 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
723 void amdgpu_dm_init_color_mod(void);
724 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
725 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
726 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
727 struct dc_plane_state *dc_plane_state);
729 void amdgpu_dm_update_connector_after_detect(
730 struct amdgpu_dm_connector *aconnector);
732 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
734 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux,
735 struct dc_context *ctx, unsigned int link_index,
736 void *payload, void *operation_result);
738 bool check_seamless_boot_capability(struct amdgpu_device *adev);
740 struct dc_stream_state *
741 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
742 const struct drm_display_mode *drm_mode,
743 const struct dm_connector_state *dm_state,
744 const struct dc_stream_state *old_stream);
746 int dm_atomic_get_state(struct drm_atomic_state *state,
747 struct dm_atomic_state **dm_state);
749 struct amdgpu_dm_connector *
750 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
751 struct drm_crtc *crtc);
752 #endif /* __AMDGPU_DM_H__ */