2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
47 #include "include/amdgpu_dal_power_if.h"
48 #include "amdgpu_dm_irq.h"
51 #include "irq_types.h"
52 #include "signal_types.h"
53 #include "amdgpu_dm_crc.h"
55 /* Forward declarations */
58 struct amdgpu_dm_irq_handler_data;
63 struct common_irq_params {
64 struct amdgpu_device *adev;
65 enum dc_irq_source irq_src;
69 * struct irq_list_head - Linked-list for low context IRQ handlers.
71 * @head: The list_head within &struct handler_data
72 * @work: A work_struct containing the deferred handler work
74 struct irq_list_head {
75 struct list_head head;
76 /* In case this interrupt needs post-processing, 'work' will be queued*/
77 struct work_struct work;
81 * struct dm_compressor_info - Buffer info used by frame buffer compression
82 * @cpu_addr: MMIO cpu addr
83 * @bo_ptr: Pointer to the buffer object
84 * @gpu_addr: MMIO gpu addr
86 struct dm_comressor_info {
88 struct amdgpu_bo *bo_ptr;
93 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI
94 * @min_input_signal: minimum possible input in range 0-255
95 * @max_input_signal: maximum possible input in range 0-255
96 * @caps_valid: true if these values are from the ACPI interface
98 struct amdgpu_dm_backlight_caps {
100 int max_input_signal;
105 * struct amdgpu_display_manager - Central amdgpu display manager device
107 * @dc: Display Core control structure
108 * @adev: AMDGPU base driver structure
109 * @ddev: DRM base driver structure
110 * @display_indexes_num: Max number of display streams supported
111 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
112 * @backlight_dev: Backlight control device
113 * @backlight_link: Link on which to control backlight
114 * @backlight_caps: Capabilities of the backlight device
115 * @freesync_module: Module handling freesync calculations
116 * @fw_dmcu: Reference to DMCU firmware
117 * @dmcu_fw_version: Version of the DMCU firmware
118 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
119 * @cached_state: Caches device atomic state for suspend/resume
120 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
122 struct amdgpu_display_manager {
129 * DMUB service, used for controlling the DMUB on hardware
130 * that supports it. The pointer to the dmub_srv will be
131 * NULL on hardware that does not support it.
133 struct dmub_srv *dmub_srv;
138 * DMUB firmware, required on hardware that has DMUB support.
140 const struct firmware *dmub_fw;
145 * Buffer object for the DMUB.
147 struct amdgpu_bo *dmub_bo;
152 * GPU virtual address for the DMUB buffer object.
154 u64 dmub_bo_gpu_addr;
159 * CPU address for the DMUB buffer object.
161 void *dmub_bo_cpu_addr;
166 * DMCUB firmware version.
168 uint32_t dmcub_fw_version;
173 * The Common Graphics Services device. It provides an interface for
174 * accessing registers.
176 struct cgs_device *cgs_device;
178 struct amdgpu_device *adev;
179 struct drm_device *ddev;
180 u16 display_indexes_num;
185 * In combination with &dm_atomic_state it helps manage
186 * global atomic state that doesn't map cleanly into existing
187 * drm resources, like &dc_context.
189 struct drm_private_obj atomic_obj;
194 * Guards access to DC functions that can issue register write
197 struct mutex dc_lock;
202 * Guards access to audio instance changes.
204 struct mutex audio_lock;
209 * Used to notify ELD changes to sound driver.
211 struct drm_audio_component *audio_component;
216 * True if the audio component has been registered
217 * successfully, false otherwise.
219 bool audio_registered;
222 * @irq_handler_list_low_tab:
224 * Low priority IRQ handler table.
226 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
227 * source. Low priority IRQ handlers are deferred to a workqueue to be
228 * processed. Hence, they can sleep.
230 * Note that handlers are called in the same order as they were
233 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
236 * @irq_handler_list_high_tab:
238 * High priority IRQ handler table.
240 * It is a n*m table, same as &irq_handler_list_low_tab. However,
241 * handlers in this table are not deferred and are called immediately.
243 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
248 * Page flip IRQ parameters, passed to registered handlers when
251 struct common_irq_params
252 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
257 * Vertical blanking IRQ parameters, passed to registered handlers when
260 struct common_irq_params
261 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
266 * Vertical update IRQ parameters, passed to registered handlers when
269 struct common_irq_params
270 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
272 spinlock_t irq_handler_list_table_lock;
274 struct backlight_device *backlight_dev;
276 const struct dc_link *backlight_link;
277 struct amdgpu_dm_backlight_caps backlight_caps;
279 struct mod_freesync *freesync_module;
280 #ifdef CONFIG_DRM_AMD_DC_HDCP
281 struct hdcp_workqueue *hdcp_workqueue;
284 struct drm_atomic_state *cached_state;
286 struct dm_comressor_info compressor;
288 const struct firmware *fw_dmcu;
289 uint32_t dmcu_fw_version;
290 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
294 * gpu_info FW provided soc bounding box struct or 0 if not
297 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
301 struct amdgpu_dm_connector {
303 struct drm_connector base;
304 uint32_t connector_id;
306 /* we need to mind the EDID between detect
307 and get modes due to analog/digital/tvencoder */
310 /* shared with amdgpu */
311 struct amdgpu_hpd hpd;
313 /* number of modes generated from EDID at 'dc_sink' */
316 /* The 'old' sink - before an HPD.
317 * The 'current' sink is in dc_link->sink. */
318 struct dc_sink *dc_sink;
319 struct dc_link *dc_link;
320 struct dc_sink *dc_em_sink;
323 struct drm_dp_mst_topology_mgr mst_mgr;
324 struct amdgpu_dm_dp_aux dm_dp_aux;
325 struct drm_dp_mst_port *port;
326 struct amdgpu_dm_connector *mst_port;
327 struct amdgpu_encoder *mst_encoder;
329 /* TODO see if we can merge with ddc_bus or make a dm_connector */
330 struct amdgpu_i2c_adapter *i2c;
332 /* Monitor range limits */
337 /* Audio instance - protected by audio_lock. */
340 struct mutex hpd_lock;
343 #ifdef CONFIG_DEBUG_FS
344 uint32_t debugfs_dpcd_address;
345 uint32_t debugfs_dpcd_size;
347 bool force_yuv420_output;
350 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
352 extern const struct amdgpu_ip_block_version dm_ip_block;
354 struct amdgpu_framebuffer;
355 struct amdgpu_display_manager;
356 struct dc_validation_set;
357 struct dc_plane_state;
359 struct dm_plane_state {
360 struct drm_plane_state base;
361 struct dc_plane_state *dc_state;
364 struct dm_crtc_state {
365 struct drm_crtc_state base;
366 struct dc_stream_state *stream;
369 bool cm_is_degamma_srgb;
373 bool interrupts_enabled;
376 enum amdgpu_dm_pipe_crc_source crc_src;
378 bool freesync_timing_changed;
379 bool freesync_vrr_info_changed;
382 struct mod_freesync_config freesync_config;
383 struct mod_vrr_params vrr_params;
384 struct dc_info_packet vrr_infopacket;
389 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
391 struct dm_atomic_state {
392 struct drm_private_state base;
394 struct dc_state *context;
397 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
399 struct dm_connector_state {
400 struct drm_connector_state base;
402 enum amdgpu_rmx_type scaling;
403 uint8_t underscan_vborder;
404 uint8_t underscan_hborder;
405 bool underscan_enable;
406 bool freesync_capable;
412 #define to_dm_connector_state(x)\
413 container_of((x), struct dm_connector_state, base)
415 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
416 struct drm_connector_state *
417 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
418 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
419 struct drm_connector_state *state,
420 struct drm_property *property,
423 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
424 const struct drm_connector_state *state,
425 struct drm_property *property,
428 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
430 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
431 struct amdgpu_dm_connector *aconnector,
433 struct dc_link *link,
436 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
437 struct drm_display_mode *mode);
439 void dm_restore_drm_connector_state(struct drm_device *dev,
440 struct drm_connector *connector);
442 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
445 #define MAX_COLOR_LUT_ENTRIES 4096
446 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
447 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
449 void amdgpu_dm_init_color_mod(void);
450 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
451 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
452 struct dc_plane_state *dc_plane_state);
454 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
456 #endif /* __AMDGPU_DM_H__ */