drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc_link_dp.h"
  32 #include "link_enc_cfg.h"
  33 #include "dc/inc/core_types.h"
  34 #include "dal_asic_id.h"
  35 #include "dmub/dmub_srv.h"
  36 #include "dc/inc/hw/dmcu.h"
  37 #include "dc/inc/hw/abm.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "dc/dc_edid_parser.h"
  40 #include "dc/dc_stat.h"
  41 #include "amdgpu_dm_trace.h"
  42
  43 #include "vid.h"
  44 #include "amdgpu.h"
  45 #include "amdgpu_display.h"
  46 #include "amdgpu_ucode.h"
  47 #include "atom.h"
  48 #include "amdgpu_dm.h"
  49 #include "amdgpu_dm_plane.h"
  50 #include "amdgpu_dm_crtc.h"
  51 #ifdef CONFIG_DRM_AMD_DC_HDCP
  52 #include "amdgpu_dm_hdcp.h"
  53 #include <drm/display/drm_hdcp_helper.h>
  54 #endif
  55 #include "amdgpu_pm.h"
  56 #include "amdgpu_atombios.h"
  57
  58 #include "amd_shared.h"
  59 #include "amdgpu_dm_irq.h"
  60 #include "dm_helpers.h"
  61 #include "amdgpu_dm_mst_types.h"
  62 #if defined(CONFIG_DEBUG_FS)
  63 #include "amdgpu_dm_debugfs.h"
  64 #endif
  65 #include "amdgpu_dm_psr.h"
  66
  67 #include "ivsrcid/ivsrcid_vislands30.h"
  68
  69 #include "i2caux_interface.h"
  70 #include <linux/module.h>
  71 #include <linux/moduleparam.h>
  72 #include <linux/types.h>
  73 #include <linux/pm_runtime.h>
  74 #include <linux/pci.h>
  75 #include <linux/firmware.h>
  76 #include <linux/component.h>
  77 #include <linux/dmi.h>
  78
  79 #include <drm/display/drm_dp_mst_helper.h>
  80 #include <drm/display/drm_hdmi_helper.h>
  81 #include <drm/drm_atomic.h>
  82 #include <drm/drm_atomic_uapi.h>
  83 #include <drm/drm_atomic_helper.h>
  84 #include <drm/drm_blend.h>
  85 #include <drm/drm_fourcc.h>
  86 #include <drm/drm_edid.h>
  87 #include <drm/drm_vblank.h>
  88 #include <drm/drm_audio_component.h>
  89 #include <drm/drm_gem_atomic_helper.h>
  90 #include <drm/drm_plane_helper.h>
  91
  92 #include <acpi/video.h>
  93
  94 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  95
  96 #include "dcn/dcn_1_0_offset.h"
  97 #include "dcn/dcn_1_0_sh_mask.h"
  98 #include "soc15_hw_ip.h"
  99 #include "soc15_common.h"
 100 #include "vega10_ip_offset.h"
 101
 102 #include "gc/gc_11_0_0_offset.h"
 103 #include "gc/gc_11_0_0_sh_mask.h"
 104
 105 #include "modules/inc/mod_freesync.h"
 106 #include "modules/power/power_helpers.h"
 107 #include "modules/inc/mod_info_packet.h"
 108
 109 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 110 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 111 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 112 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 113 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 115 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 117 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 119 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 121 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 123 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 125 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 127 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 129 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 131
 132 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 134 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 136
 137 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 138 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 139
 140 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 141 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 142
 143 /* Number of bytes in PSP header for firmware. */
 144 #define PSP_HEADER_BYTES 0x100
 145
 146 /* Number of bytes in PSP footer for firmware. */
 147 #define PSP_FOOTER_BYTES 0x100
 148
 149 /**
 150  * DOC: overview
 151  *
 152  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 153  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 154  * requests into DC requests, and DC responses into DRM responses.
 155  *
 156  * The root control structure is &struct amdgpu_display_manager.
 157  */
 158
 159 /* basic init/fini API */
 160 static int amdgpu_dm_init(struct amdgpu_device *adev);
 161 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 162 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 163
 164 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 165 {
 166         switch (link->dpcd_caps.dongle_type) {
 167         case DISPLAY_DONGLE_NONE:
 168                 return DRM_MODE_SUBCONNECTOR_Native;
 169         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 170                 return DRM_MODE_SUBCONNECTOR_VGA;
 171         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 172         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 173                 return DRM_MODE_SUBCONNECTOR_DVID;
 174         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 175         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 176                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 177         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 178         default:
 179                 return DRM_MODE_SUBCONNECTOR_Unknown;
 180         }
 181 }
 182
 183 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 184 {
 185         struct dc_link *link = aconnector->dc_link;
 186         struct drm_connector *connector = &aconnector->base;
 187         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 188
 189         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 190                 return;
 191
 192         if (aconnector->dc_sink)
 193                 subconnector = get_subconnector_type(link);
 194
 195         drm_object_property_set_value(&connector->base,
 196                         connector->dev->mode_config.dp_subconnector_property,
 197                         subconnector);
 198 }
 199
 200 /*
 201  * initializes drm_device display related structures, based on the information
 202  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 203  * drm_encoder, drm_mode_config
 204  *
 205  * Returns 0 on success
 206  */
 207 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 208 /* removes and deallocates the drm structures, created by the above function */
 209 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 210
 211 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 212                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 213                                     uint32_t link_index,
 214                                     struct amdgpu_encoder *amdgpu_encoder);
 215 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 216                                   struct amdgpu_encoder *aencoder,
 217                                   uint32_t link_index);
 218
 219 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 220
 221 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 222
 223 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 224                                   struct drm_atomic_state *state);
 225
 226 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 227 static void handle_hpd_rx_irq(void *param);
 228
 229 static bool
 230 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 231                                  struct drm_crtc_state *new_crtc_state);
 232 /*
 233  * dm_vblank_get_counter
 234  *
 235  * @brief
 236  * Get counter for number of vertical blanks
 237  *
 238  * @param
 239  * struct amdgpu_device *adev - [in] desired amdgpu device
 240  * int disp_idx - [in] which CRTC to get the counter from
 241  *
 242  * @return
 243  * Counter for vertical blanks
 244  */
 245 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 246 {
 247         if (crtc >= adev->mode_info.num_crtc)
 248                 return 0;
 249         else {
 250                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 251
 252                 if (acrtc->dm_irq_params.stream == NULL) {
 253                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 254                                   crtc);
 255                         return 0;
 256                 }
 257
 258                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 259         }
 260 }
 261
 262 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 263                                   u32 *vbl, u32 *position)
 264 {
 265         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 266
 267         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 268                 return -EINVAL;
 269         else {
 270                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 271
 272                 if (acrtc->dm_irq_params.stream ==  NULL) {
 273                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 274                                   crtc);
 275                         return 0;
 276                 }
 277
 278                 /*
 279                  * TODO rework base driver to use values directly.
 280                  * for now parse it back into reg-format
 281                  */
 282                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 283                                          &v_blank_start,
 284                                          &v_blank_end,
 285                                          &h_position,
 286                                          &v_position);
 287
 288                 *position = v_position | (h_position << 16);
 289                 *vbl = v_blank_start | (v_blank_end << 16);
 290         }
 291
 292         return 0;
 293 }
 294
 295 static bool dm_is_idle(void *handle)
 296 {
 297         /* XXX todo */
 298         return true;
 299 }
 300
 301 static int dm_wait_for_idle(void *handle)
 302 {
 303         /* XXX todo */
 304         return 0;
 305 }
 306
 307 static bool dm_check_soft_reset(void *handle)
 308 {
 309         return false;
 310 }
 311
 312 static int dm_soft_reset(void *handle)
 313 {
 314         /* XXX todo */
 315         return 0;
 316 }
 317
 318 static struct amdgpu_crtc *
 319 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 320                      int otg_inst)
 321 {
 322         struct drm_device *dev = adev_to_drm(adev);
 323         struct drm_crtc *crtc;
 324         struct amdgpu_crtc *amdgpu_crtc;
 325
 326         if (WARN_ON(otg_inst == -1))
 327                 return adev->mode_info.crtcs[0];
 328
 329         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 330                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 331
 332                 if (amdgpu_crtc->otg_inst == otg_inst)
 333                         return amdgpu_crtc;
 334         }
 335
 336         return NULL;
 337 }
 338
 339 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 340                                               struct dm_crtc_state *new_state)
 341 {
 342         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 343                 return true;
 344         else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
 345                 return true;
 346         else
 347                 return false;
 348 }
 349
 350 /**
 351  * dm_pflip_high_irq() - Handle pageflip interrupt
 352  * @interrupt_params: ignored
 353  *
 354  * Handles the pageflip interrupt by notifying all interested parties
 355  * that the pageflip has been completed.
 356  */
 357 static void dm_pflip_high_irq(void *interrupt_params)
 358 {
 359         struct amdgpu_crtc *amdgpu_crtc;
 360         struct common_irq_params *irq_params = interrupt_params;
 361         struct amdgpu_device *adev = irq_params->adev;
 362         unsigned long flags;
 363         struct drm_pending_vblank_event *e;
 364         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 365         bool vrr_active;
 366
 367         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 368
 369         /* IRQ could occur when in initial stage */
 370         /* TODO work and BO cleanup */
 371         if (amdgpu_crtc == NULL) {
 372                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 373                 return;
 374         }
 375
 376         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 377
 378         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 379                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 380                                                  amdgpu_crtc->pflip_status,
 381                                                  AMDGPU_FLIP_SUBMITTED,
 382                                                  amdgpu_crtc->crtc_id,
 383                                                  amdgpu_crtc);
 384                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 385                 return;
 386         }
 387
 388         /* page flip completed. */
 389         e = amdgpu_crtc->event;
 390         amdgpu_crtc->event = NULL;
 391
 392         WARN_ON(!e);
 393
 394         vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
 395
 396         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 397         if (!vrr_active ||
 398             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 399                                       &v_blank_end, &hpos, &vpos) ||
 400             (vpos < v_blank_start)) {
 401                 /* Update to correct count and vblank timestamp if racing with
 402                  * vblank irq. This also updates to the correct vblank timestamp
 403                  * even in VRR mode, as scanout is past the front-porch atm.
 404                  */
 405                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 406
 407                 /* Wake up userspace by sending the pageflip event with proper
 408                  * count and timestamp of vblank of flip completion.
 409                  */
 410                 if (e) {
 411                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 412
 413                         /* Event sent, so done with vblank for this flip */
 414                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 415                 }
 416         } else if (e) {
 417                 /* VRR active and inside front-porch: vblank count and
 418                  * timestamp for pageflip event will only be up to date after
 419                  * drm_crtc_handle_vblank() has been executed from late vblank
 420                  * irq handler after start of back-porch (vline 0). We queue the
 421                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 422                  * updated timestamp and count, once it runs after us.
 423                  *
 424                  * We need to open-code this instead of using the helper
 425                  * drm_crtc_arm_vblank_event(), as that helper would
 426                  * call drm_crtc_accurate_vblank_count(), which we must
 427                  * not call in VRR mode while we are in front-porch!
 428                  */
 429
 430                 /* sequence will be replaced by real count during send-out. */
 431                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 432                 e->pipe = amdgpu_crtc->crtc_id;
 433
 434                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 435                 e = NULL;
 436         }
 437
 438         /* Keep track of vblank of this flip for flip throttling. We use the
 439          * cooked hw counter, as that one incremented at start of this vblank
 440          * of pageflip completion, so last_flip_vblank is the forbidden count
 441          * for queueing new pageflips if vsync + VRR is enabled.
 442          */
 443         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 444                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 445
 446         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 447         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 448
 449         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 450                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 451                      vrr_active, (int) !e);
 452 }
 453
 454 static void dm_vupdate_high_irq(void *interrupt_params)
 455 {
 456         struct common_irq_params *irq_params = interrupt_params;
 457         struct amdgpu_device *adev = irq_params->adev;
 458         struct amdgpu_crtc *acrtc;
 459         struct drm_device *drm_dev;
 460         struct drm_vblank_crtc *vblank;
 461         ktime_t frame_duration_ns, previous_timestamp;
 462         unsigned long flags;
 463         int vrr_active;
 464
 465         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 466
 467         if (acrtc) {
 468                 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 469                 drm_dev = acrtc->base.dev;
 470                 vblank = &drm_dev->vblank[acrtc->base.index];
 471                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 472                 frame_duration_ns = vblank->time - previous_timestamp;
 473
 474                 if (frame_duration_ns > 0) {
 475                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 476                                                 frame_duration_ns,
 477                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 478                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 479                 }
 480
 481                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 482                               acrtc->crtc_id,
 483                               vrr_active);
 484
 485                 /* Core vblank handling is done here after end of front-porch in
 486                  * vrr mode, as vblank timestamping will give valid results
 487                  * while now done after front-porch. This will also deliver
 488                  * page-flip completion events that have been queued to us
 489                  * if a pageflip happened inside front-porch.
 490                  */
 491                 if (vrr_active) {
 492                         dm_crtc_handle_vblank(acrtc);
 493
 494                         /* BTR processing for pre-DCE12 ASICs */
 495                         if (acrtc->dm_irq_params.stream &&
 496                             adev->family < AMDGPU_FAMILY_AI) {
 497                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 498                                 mod_freesync_handle_v_update(
 499                                     adev->dm.freesync_module,
 500                                     acrtc->dm_irq_params.stream,
 501                                     &acrtc->dm_irq_params.vrr_params);
 502
 503                                 dc_stream_adjust_vmin_vmax(
 504                                     adev->dm.dc,
 505                                     acrtc->dm_irq_params.stream,
 506                                     &acrtc->dm_irq_params.vrr_params.adjust);
 507                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 508                         }
 509                 }
 510         }
 511 }
 512
 513 /**
 514  * dm_crtc_high_irq() - Handles CRTC interrupt
 515  * @interrupt_params: used for determining the CRTC instance
 516  *
 517  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 518  * event handler.
 519  */
 520 static void dm_crtc_high_irq(void *interrupt_params)
 521 {
 522         struct common_irq_params *irq_params = interrupt_params;
 523         struct amdgpu_device *adev = irq_params->adev;
 524         struct amdgpu_crtc *acrtc;
 525         unsigned long flags;
 526         int vrr_active;
 527
 528         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 529         if (!acrtc)
 530                 return;
 531
 532         vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 533
 534         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 535                       vrr_active, acrtc->dm_irq_params.active_planes);
 536
 537         /**
 538          * Core vblank handling at start of front-porch is only possible
 539          * in non-vrr mode, as only there vblank timestamping will give
 540          * valid results while done in front-porch. Otherwise defer it
 541          * to dm_vupdate_high_irq after end of front-porch.
 542          */
 543         if (!vrr_active)
 544                 dm_crtc_handle_vblank(acrtc);
 545
 546         /**
 547          * Following stuff must happen at start of vblank, for crc
 548          * computation and below-the-range btr support in vrr mode.
 549          */
 550         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 551
 552         /* BTR updates need to happen before VUPDATE on Vega and above. */
 553         if (adev->family < AMDGPU_FAMILY_AI)
 554                 return;
 555
 556         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 557
 558         if (acrtc->dm_irq_params.stream &&
 559             acrtc->dm_irq_params.vrr_params.supported &&
 560             acrtc->dm_irq_params.freesync_config.state ==
 561                     VRR_STATE_ACTIVE_VARIABLE) {
 562                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 563                                              acrtc->dm_irq_params.stream,
 564                                              &acrtc->dm_irq_params.vrr_params);
 565
 566                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 567                                            &acrtc->dm_irq_params.vrr_params.adjust);
 568         }
 569
 570         /*
 571          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 572          * In that case, pageflip completion interrupts won't fire and pageflip
 573          * completion events won't get delivered. Prevent this by sending
 574          * pending pageflip events from here if a flip is still pending.
 575          *
 576          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 577          * avoid race conditions between flip programming and completion,
 578          * which could cause too early flip completion events.
 579          */
 580         if (adev->family >= AMDGPU_FAMILY_RV &&
 581             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 582             acrtc->dm_irq_params.active_planes == 0) {
 583                 if (acrtc->event) {
 584                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 585                         acrtc->event = NULL;
 586                         drm_crtc_vblank_put(&acrtc->base);
 587                 }
 588                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 589         }
 590
 591         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 592 }
 593
 594 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 595 /**
 596  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 597  * DCN generation ASICs
 598  * @interrupt_params: interrupt parameters
 599  *
 600  * Used to set crc window/read out crc value at vertical line 0 position
 601  */
 602 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 603 {
 604         struct common_irq_params *irq_params = interrupt_params;
 605         struct amdgpu_device *adev = irq_params->adev;
 606         struct amdgpu_crtc *acrtc;
 607
 608         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 609
 610         if (!acrtc)
 611                 return;
 612
 613         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 614 }
 615 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 616
 617 /**
 618  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 619  * @adev: amdgpu_device pointer
 620  * @notify: dmub notification structure
 621  *
 622  * Dmub AUX or SET_CONFIG command completion processing callback
 623  * Copies dmub notification to DM which is to be read by AUX command.
 624  * issuing thread and also signals the event to wake up the thread.
 625  */
 626 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 627                                         struct dmub_notification *notify)
 628 {
 629         if (adev->dm.dmub_notify)
 630                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 631         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 632                 complete(&adev->dm.dmub_aux_transfer_done);
 633 }
 634
 635 /**
 636  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 637  * @adev: amdgpu_device pointer
 638  * @notify: dmub notification structure
 639  *
 640  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 641  * ink index and calls helper to do the processing.
 642  */
 643 static void dmub_hpd_callback(struct amdgpu_device *adev,
 644                               struct dmub_notification *notify)
 645 {
 646         struct amdgpu_dm_connector *aconnector;
 647         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 648         struct drm_connector *connector;
 649         struct drm_connector_list_iter iter;
 650         struct dc_link *link;
 651         uint8_t link_index = 0;
 652         struct drm_device *dev;
 653
 654         if (adev == NULL)
 655                 return;
 656
 657         if (notify == NULL) {
 658                 DRM_ERROR("DMUB HPD callback notification was NULL");
 659                 return;
 660         }
 661
 662         if (notify->link_index > adev->dm.dc->link_count) {
 663                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 664                 return;
 665         }
 666
 667         link_index = notify->link_index;
 668         link = adev->dm.dc->links[link_index];
 669         dev = adev->dm.ddev;
 670
 671         drm_connector_list_iter_begin(dev, &iter);
 672         drm_for_each_connector_iter(connector, &iter) {
 673                 aconnector = to_amdgpu_dm_connector(connector);
 674                 if (link && aconnector->dc_link == link) {
 675                         DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 676                         hpd_aconnector = aconnector;
 677                         break;
 678                 }
 679         }
 680         drm_connector_list_iter_end(&iter);
 681
 682         if (hpd_aconnector) {
 683                 if (notify->type == DMUB_NOTIFICATION_HPD)
 684                         handle_hpd_irq_helper(hpd_aconnector);
 685                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 686                         handle_hpd_rx_irq(hpd_aconnector);
 687         }
 688 }
 689
 690 /**
 691  * register_dmub_notify_callback - Sets callback for DMUB notify
 692  * @adev: amdgpu_device pointer
 693  * @type: Type of dmub notification
 694  * @callback: Dmub interrupt callback function
 695  * @dmub_int_thread_offload: offload indicator
 696  *
 697  * API to register a dmub callback handler for a dmub notification
 698  * Also sets indicator whether callback processing to be offloaded.
 699  * to dmub interrupt handling thread
 700  * Return: true if successfully registered, false if there is existing registration
 701  */
 702 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 703                                           enum dmub_notification_type type,
 704                                           dmub_notify_interrupt_callback_t callback,
 705                                           bool dmub_int_thread_offload)
 706 {
 707         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 708                 adev->dm.dmub_callback[type] = callback;
 709                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 710         } else
 711                 return false;
 712
 713         return true;
 714 }
 715
 716 static void dm_handle_hpd_work(struct work_struct *work)
 717 {
 718         struct dmub_hpd_work *dmub_hpd_wrk;
 719
 720         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 721
 722         if (!dmub_hpd_wrk->dmub_notify) {
 723                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 724                 return;
 725         }
 726
 727         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 728                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 729                 dmub_hpd_wrk->dmub_notify);
 730         }
 731
 732         kfree(dmub_hpd_wrk->dmub_notify);
 733         kfree(dmub_hpd_wrk);
 734
 735 }
 736
 737 #define DMUB_TRACE_MAX_READ 64
 738 /**
 739  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 740  * @interrupt_params: used for determining the Outbox instance
 741  *
 742  * Handles the Outbox Interrupt
 743  * event handler.
 744  */
 745 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 746 {
 747         struct dmub_notification notify;
 748         struct common_irq_params *irq_params = interrupt_params;
 749         struct amdgpu_device *adev = irq_params->adev;
 750         struct amdgpu_display_manager *dm = &adev->dm;
 751         struct dmcub_trace_buf_entry entry = { 0 };
 752         uint32_t count = 0;
 753         struct dmub_hpd_work *dmub_hpd_wrk;
 754         struct dc_link *plink = NULL;
 755
 756         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 757                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 758
 759                 do {
 760                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 761                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 762                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 763                                 continue;
 764                         }
 765                         if (!dm->dmub_callback[notify.type]) {
 766                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 767                                 continue;
 768                         }
 769                         if (dm->dmub_thread_offload[notify.type] == true) {
 770                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 771                                 if (!dmub_hpd_wrk) {
 772                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 773                                         return;
 774                                 }
 775                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 776                                 if (!dmub_hpd_wrk->dmub_notify) {
 777                                         kfree(dmub_hpd_wrk);
 778                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 779                                         return;
 780                                 }
 781                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 782                                 if (dmub_hpd_wrk->dmub_notify)
 783                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 784                                 dmub_hpd_wrk->adev = adev;
 785                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 786                                         plink = adev->dm.dc->links[notify.link_index];
 787                                         if (plink) {
 788                                                 plink->hpd_status =
 789                                                         notify.hpd_status == DP_HPD_PLUG;
 790                                         }
 791                                 }
 792                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 793                         } else {
 794                                 dm->dmub_callback[notify.type](adev, &notify);
 795                         }
 796                 } while (notify.pending_notification);
 797         }
 798
 799
 800         do {
 801                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 802                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 803                                                         entry.param0, entry.param1);
 804
 805                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 806                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 807                 } else
 808                         break;
 809
 810                 count++;
 811
 812         } while (count <= DMUB_TRACE_MAX_READ);
 813
 814         if (count > DMUB_TRACE_MAX_READ)
 815                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 816 }
 817
 818 static int dm_set_clockgating_state(void *handle,
 819                   enum amd_clockgating_state state)
 820 {
 821         return 0;
 822 }
 823
 824 static int dm_set_powergating_state(void *handle,
 825                   enum amd_powergating_state state)
 826 {
 827         return 0;
 828 }
 829
 830 /* Prototypes of private functions */
 831 static int dm_early_init(void* handle);
 832
 833 /* Allocate memory for FBC compressed data  */
 834 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 835 {
 836         struct drm_device *dev = connector->dev;
 837         struct amdgpu_device *adev = drm_to_adev(dev);
 838         struct dm_compressor_info *compressor = &adev->dm.compressor;
 839         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 840         struct drm_display_mode *mode;
 841         unsigned long max_size = 0;
 842
 843         if (adev->dm.dc->fbc_compressor == NULL)
 844                 return;
 845
 846         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 847                 return;
 848
 849         if (compressor->bo_ptr)
 850                 return;
 851
 852
 853         list_for_each_entry(mode, &connector->modes, head) {
 854                 if (max_size < mode->htotal * mode->vtotal)
 855                         max_size = mode->htotal * mode->vtotal;
 856         }
 857
 858         if (max_size) {
 859                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 860                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 861                             &compressor->gpu_addr, &compressor->cpu_addr);
 862
 863                 if (r)
 864                         DRM_ERROR("DM: Failed to initialize FBC\n");
 865                 else {
 866                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 867                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 868                 }
 869
 870         }
 871
 872 }
 873
 874 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 875                                           int pipe, bool *enabled,
 876                                           unsigned char *buf, int max_bytes)
 877 {
 878         struct drm_device *dev = dev_get_drvdata(kdev);
 879         struct amdgpu_device *adev = drm_to_adev(dev);
 880         struct drm_connector *connector;
 881         struct drm_connector_list_iter conn_iter;
 882         struct amdgpu_dm_connector *aconnector;
 883         int ret = 0;
 884
 885         *enabled = false;
 886
 887         mutex_lock(&adev->dm.audio_lock);
 888
 889         drm_connector_list_iter_begin(dev, &conn_iter);
 890         drm_for_each_connector_iter(connector, &conn_iter) {
 891                 aconnector = to_amdgpu_dm_connector(connector);
 892                 if (aconnector->audio_inst != port)
 893                         continue;
 894
 895                 *enabled = true;
 896                 ret = drm_eld_size(connector->eld);
 897                 memcpy(buf, connector->eld, min(max_bytes, ret));
 898
 899                 break;
 900         }
 901         drm_connector_list_iter_end(&conn_iter);
 902
 903         mutex_unlock(&adev->dm.audio_lock);
 904
 905         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 906
 907         return ret;
 908 }
 909
 910 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 911         .get_eld = amdgpu_dm_audio_component_get_eld,
 912 };
 913
 914 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 915                                        struct device *hda_kdev, void *data)
 916 {
 917         struct drm_device *dev = dev_get_drvdata(kdev);
 918         struct amdgpu_device *adev = drm_to_adev(dev);
 919         struct drm_audio_component *acomp = data;
 920
 921         acomp->ops = &amdgpu_dm_audio_component_ops;
 922         acomp->dev = kdev;
 923         adev->dm.audio_component = acomp;
 924
 925         return 0;
 926 }
 927
 928 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 929                                           struct device *hda_kdev, void *data)
 930 {
 931         struct drm_device *dev = dev_get_drvdata(kdev);
 932         struct amdgpu_device *adev = drm_to_adev(dev);
 933         struct drm_audio_component *acomp = data;
 934
 935         acomp->ops = NULL;
 936         acomp->dev = NULL;
 937         adev->dm.audio_component = NULL;
 938 }
 939
 940 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 941         .bind   = amdgpu_dm_audio_component_bind,
 942         .unbind = amdgpu_dm_audio_component_unbind,
 943 };
 944
 945 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 946 {
 947         int i, ret;
 948
 949         if (!amdgpu_audio)
 950                 return 0;
 951
 952         adev->mode_info.audio.enabled = true;
 953
 954         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 955
 956         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 957                 adev->mode_info.audio.pin[i].channels = -1;
 958                 adev->mode_info.audio.pin[i].rate = -1;
 959                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 960                 adev->mode_info.audio.pin[i].status_bits = 0;
 961                 adev->mode_info.audio.pin[i].category_code = 0;
 962                 adev->mode_info.audio.pin[i].connected = false;
 963                 adev->mode_info.audio.pin[i].id =
 964                         adev->dm.dc->res_pool->audios[i]->inst;
 965                 adev->mode_info.audio.pin[i].offset = 0;
 966         }
 967
 968         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 969         if (ret < 0)
 970                 return ret;
 971
 972         adev->dm.audio_registered = true;
 973
 974         return 0;
 975 }
 976
 977 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 978 {
 979         if (!amdgpu_audio)
 980                 return;
 981
 982         if (!adev->mode_info.audio.enabled)
 983                 return;
 984
 985         if (adev->dm.audio_registered) {
 986                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 987                 adev->dm.audio_registered = false;
 988         }
 989
 990         /* TODO: Disable audio? */
 991
 992         adev->mode_info.audio.enabled = false;
 993 }
 994
 995 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 996 {
 997         struct drm_audio_component *acomp = adev->dm.audio_component;
 998
 999         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1000                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1001
1002                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1003                                                  pin, -1);
1004         }
1005 }
1006
1007 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1008 {
1009         const struct dmcub_firmware_header_v1_0 *hdr;
1010         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1011         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1012         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1013         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1014         struct abm *abm = adev->dm.dc->res_pool->abm;
1015         struct dmub_srv_hw_params hw_params;
1016         enum dmub_status status;
1017         const unsigned char *fw_inst_const, *fw_bss_data;
1018         uint32_t i, fw_inst_const_size, fw_bss_data_size;
1019         bool has_hw_support;
1020
1021         if (!dmub_srv)
1022                 /* DMUB isn't supported on the ASIC. */
1023                 return 0;
1024
1025         if (!fb_info) {
1026                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1027                 return -EINVAL;
1028         }
1029
1030         if (!dmub_fw) {
1031                 /* Firmware required for DMUB support. */
1032                 DRM_ERROR("No firmware provided for DMUB.\n");
1033                 return -EINVAL;
1034         }
1035
1036         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1037         if (status != DMUB_STATUS_OK) {
1038                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1039                 return -EINVAL;
1040         }
1041
1042         if (!has_hw_support) {
1043                 DRM_INFO("DMUB unsupported on ASIC\n");
1044                 return 0;
1045         }
1046
1047         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1048         status = dmub_srv_hw_reset(dmub_srv);
1049         if (status != DMUB_STATUS_OK)
1050                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1051
1052         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1053
1054         fw_inst_const = dmub_fw->data +
1055                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1056                         PSP_HEADER_BYTES;
1057
1058         fw_bss_data = dmub_fw->data +
1059                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1060                       le32_to_cpu(hdr->inst_const_bytes);
1061
1062         /* Copy firmware and bios info into FB memory. */
1063         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1064                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1065
1066         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1067
1068         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1069          * amdgpu_ucode_init_single_fw will load dmub firmware
1070          * fw_inst_const part to cw0; otherwise, the firmware back door load
1071          * will be done by dm_dmub_hw_init
1072          */
1073         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1074                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1075                                 fw_inst_const_size);
1076         }
1077
1078         if (fw_bss_data_size)
1079                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1080                        fw_bss_data, fw_bss_data_size);
1081
1082         /* Copy firmware bios info into FB memory. */
1083         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1084                adev->bios_size);
1085
1086         /* Reset regions that need to be reset. */
1087         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1088         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1089
1090         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1091                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1092
1093         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1094                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1095
1096         /* Initialize hardware. */
1097         memset(&hw_params, 0, sizeof(hw_params));
1098         hw_params.fb_base = adev->gmc.fb_start;
1099         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1100
1101         /* backdoor load firmware and trigger dmub running */
1102         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1103                 hw_params.load_inst_const = true;
1104
1105         if (dmcu)
1106                 hw_params.psp_version = dmcu->psp_version;
1107
1108         for (i = 0; i < fb_info->num_fb; ++i)
1109                 hw_params.fb[i] = &fb_info->fb[i];
1110
1111         switch (adev->ip_versions[DCE_HWIP][0]) {
1112         case IP_VERSION(3, 1, 3):
1113         case IP_VERSION(3, 1, 4):
1114                 hw_params.dpia_supported = true;
1115                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1116                 break;
1117         default:
1118                 break;
1119         }
1120
1121         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1122         if (status != DMUB_STATUS_OK) {
1123                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1124                 return -EINVAL;
1125         }
1126
1127         /* Wait for firmware load to finish. */
1128         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1129         if (status != DMUB_STATUS_OK)
1130                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1131
1132         /* Init DMCU and ABM if available. */
1133         if (dmcu && abm) {
1134                 dmcu->funcs->dmcu_init(dmcu);
1135                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1136         }
1137
1138         if (!adev->dm.dc->ctx->dmub_srv)
1139                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1140         if (!adev->dm.dc->ctx->dmub_srv) {
1141                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1142                 return -ENOMEM;
1143         }
1144
1145         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1146                  adev->dm.dmcub_fw_version);
1147
1148         return 0;
1149 }
1150
1151 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1152 {
1153         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1154         enum dmub_status status;
1155         bool init;
1156
1157         if (!dmub_srv) {
1158                 /* DMUB isn't supported on the ASIC. */
1159                 return;
1160         }
1161
1162         status = dmub_srv_is_hw_init(dmub_srv, &init);
1163         if (status != DMUB_STATUS_OK)
1164                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1165
1166         if (status == DMUB_STATUS_OK && init) {
1167                 /* Wait for firmware load to finish. */
1168                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1169                 if (status != DMUB_STATUS_OK)
1170                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1171         } else {
1172                 /* Perform the full hardware initialization. */
1173                 dm_dmub_hw_init(adev);
1174         }
1175 }
1176
1177 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1178 {
1179         uint64_t pt_base;
1180         uint32_t logical_addr_low;
1181         uint32_t logical_addr_high;
1182         uint32_t agp_base, agp_bot, agp_top;
1183         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1184
1185         memset(pa_config, 0, sizeof(*pa_config));
1186
1187         logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1188         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1189
1190         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1191                 /*
1192                  * Raven2 has a HW issue that it is unable to use the vram which
1193                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1194                  * workaround that increase system aperture high address (add 1)
1195                  * to get rid of the VM fault and hardware hang.
1196                  */
1197                 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1198         else
1199                 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1200
1201         agp_base = 0;
1202         agp_bot = adev->gmc.agp_start >> 24;
1203         agp_top = adev->gmc.agp_end >> 24;
1204
1205
1206         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1207         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1208         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1209         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1210         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1211         page_table_base.low_part = lower_32_bits(pt_base);
1212
1213         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1214         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1215
1216         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1217         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1218         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1219
1220         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1221         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1222         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1223
1224         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1225         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1226         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1227
1228         pa_config->is_hvm_enabled = 0;
1229
1230 }
1231
1232 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1233 {
1234         struct hpd_rx_irq_offload_work *offload_work;
1235         struct amdgpu_dm_connector *aconnector;
1236         struct dc_link *dc_link;
1237         struct amdgpu_device *adev;
1238         enum dc_connection_type new_connection_type = dc_connection_none;
1239         unsigned long flags;
1240
1241         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1242         aconnector = offload_work->offload_wq->aconnector;
1243
1244         if (!aconnector) {
1245                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1246                 goto skip;
1247         }
1248
1249         adev = drm_to_adev(aconnector->base.dev);
1250         dc_link = aconnector->dc_link;
1251
1252         mutex_lock(&aconnector->hpd_lock);
1253         if (!dc_link_detect_sink(dc_link, &new_connection_type))
1254                 DRM_ERROR("KMS: Failed to detect connector\n");
1255         mutex_unlock(&aconnector->hpd_lock);
1256
1257         if (new_connection_type == dc_connection_none)
1258                 goto skip;
1259
1260         if (amdgpu_in_reset(adev))
1261                 goto skip;
1262
1263         mutex_lock(&adev->dm.dc_lock);
1264         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST)
1265                 dc_link_dp_handle_automated_test(dc_link);
1266         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1267                         hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
1268                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1269                 dc_link_dp_handle_link_loss(dc_link);
1270                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1271                 offload_work->offload_wq->is_handling_link_loss = false;
1272                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1273         }
1274         mutex_unlock(&adev->dm.dc_lock);
1275
1276 skip:
1277         kfree(offload_work);
1278
1279 }
1280
1281 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1282 {
1283         int max_caps = dc->caps.max_links;
1284         int i = 0;
1285         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1286
1287         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1288
1289         if (!hpd_rx_offload_wq)
1290                 return NULL;
1291
1292
1293         for (i = 0; i < max_caps; i++) {
1294                 hpd_rx_offload_wq[i].wq =
1295                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1296
1297                 if (hpd_rx_offload_wq[i].wq == NULL) {
1298                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1299                         goto out_err;
1300                 }
1301
1302                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1303         }
1304
1305         return hpd_rx_offload_wq;
1306
1307 out_err:
1308         for (i = 0; i < max_caps; i++) {
1309                 if (hpd_rx_offload_wq[i].wq)
1310                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1311         }
1312         kfree(hpd_rx_offload_wq);
1313         return NULL;
1314 }
1315
1316 struct amdgpu_stutter_quirk {
1317         u16 chip_vendor;
1318         u16 chip_device;
1319         u16 subsys_vendor;
1320         u16 subsys_device;
1321         u8 revision;
1322 };
1323
1324 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1325         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1326         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1327         { 0, 0, 0, 0, 0 },
1328 };
1329
1330 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1331 {
1332         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1333
1334         while (p && p->chip_device != 0) {
1335                 if (pdev->vendor == p->chip_vendor &&
1336                     pdev->device == p->chip_device &&
1337                     pdev->subsystem_vendor == p->subsys_vendor &&
1338                     pdev->subsystem_device == p->subsys_device &&
1339                     pdev->revision == p->revision) {
1340                         return true;
1341                 }
1342                 ++p;
1343         }
1344         return false;
1345 }
1346
1347 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1348         {
1349                 .matches = {
1350                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1351                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1352                 },
1353         },
1354         {
1355                 .matches = {
1356                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1357                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1358                 },
1359         },
1360         {
1361                 .matches = {
1362                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1363                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1364                 },
1365         },
1366         {
1367                 .matches = {
1368                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1369                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1370                 },
1371         },
1372         {
1373                 .matches = {
1374                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1375                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1376                 },
1377         },
1378         {
1379                 .matches = {
1380                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1381                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1382                 },
1383         },
1384         {
1385                 .matches = {
1386                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1387                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1388                 },
1389         },
1390         {
1391                 .matches = {
1392                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1393                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1394                 },
1395         },
1396         {
1397                 .matches = {
1398                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1399                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1400                 },
1401         },
1402         {}
1403         /* TODO: refactor this from a fixed table to a dynamic option */
1404 };
1405
1406 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1407 {
1408         const struct dmi_system_id *dmi_id;
1409
1410         dm->aux_hpd_discon_quirk = false;
1411
1412         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1413         if (dmi_id) {
1414                 dm->aux_hpd_discon_quirk = true;
1415                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1416         }
1417 }
1418
1419 static int amdgpu_dm_init(struct amdgpu_device *adev)
1420 {
1421         struct dc_init_data init_data;
1422 #ifdef CONFIG_DRM_AMD_DC_HDCP
1423         struct dc_callback_init init_params;
1424 #endif
1425         int r;
1426
1427         adev->dm.ddev = adev_to_drm(adev);
1428         adev->dm.adev = adev;
1429
1430         /* Zero all the fields */
1431         memset(&init_data, 0, sizeof(init_data));
1432 #ifdef CONFIG_DRM_AMD_DC_HDCP
1433         memset(&init_params, 0, sizeof(init_params));
1434 #endif
1435
1436         mutex_init(&adev->dm.dpia_aux_lock);
1437         mutex_init(&adev->dm.dc_lock);
1438         mutex_init(&adev->dm.audio_lock);
1439
1440         if(amdgpu_dm_irq_init(adev)) {
1441                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1442                 goto error;
1443         }
1444
1445         init_data.asic_id.chip_family = adev->family;
1446
1447         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1448         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1449         init_data.asic_id.chip_id = adev->pdev->device;
1450
1451         init_data.asic_id.vram_width = adev->gmc.vram_width;
1452         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1453         init_data.asic_id.atombios_base_address =
1454                 adev->mode_info.atom_context->bios;
1455
1456         init_data.driver = adev;
1457
1458         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1459
1460         if (!adev->dm.cgs_device) {
1461                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1462                 goto error;
1463         }
1464
1465         init_data.cgs_device = adev->dm.cgs_device;
1466
1467         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1468
1469         switch (adev->ip_versions[DCE_HWIP][0]) {
1470         case IP_VERSION(2, 1, 0):
1471                 switch (adev->dm.dmcub_fw_version) {
1472                 case 0: /* development */
1473                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1474                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1475                         init_data.flags.disable_dmcu = false;
1476                         break;
1477                 default:
1478                         init_data.flags.disable_dmcu = true;
1479                 }
1480                 break;
1481         case IP_VERSION(2, 0, 3):
1482                 init_data.flags.disable_dmcu = true;
1483                 break;
1484         default:
1485                 break;
1486         }
1487
1488         switch (adev->asic_type) {
1489         case CHIP_CARRIZO:
1490         case CHIP_STONEY:
1491                 init_data.flags.gpu_vm_support = true;
1492                 break;
1493         default:
1494                 switch (adev->ip_versions[DCE_HWIP][0]) {
1495                 case IP_VERSION(1, 0, 0):
1496                 case IP_VERSION(1, 0, 1):
1497                         /* enable S/G on PCO and RV2 */
1498                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1499                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1500                                 init_data.flags.gpu_vm_support = true;
1501                         break;
1502                 case IP_VERSION(2, 1, 0):
1503                 case IP_VERSION(3, 0, 1):
1504                 case IP_VERSION(3, 1, 2):
1505                 case IP_VERSION(3, 1, 3):
1506                 case IP_VERSION(3, 1, 4):
1507                 case IP_VERSION(3, 1, 5):
1508                 case IP_VERSION(3, 1, 6):
1509                         init_data.flags.gpu_vm_support = true;
1510                         break;
1511                 default:
1512                         break;
1513                 }
1514                 break;
1515         }
1516
1517         if (init_data.flags.gpu_vm_support)
1518                 adev->mode_info.gpu_vm_support = true;
1519
1520         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1521                 init_data.flags.fbc_support = true;
1522
1523         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1524                 init_data.flags.multi_mon_pp_mclk_switch = true;
1525
1526         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1527                 init_data.flags.disable_fractional_pwm = true;
1528
1529         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1530                 init_data.flags.edp_no_power_sequencing = true;
1531
1532         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1533                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1534         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1535                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1536
1537         init_data.flags.seamless_boot_edp_requested = false;
1538
1539         if (check_seamless_boot_capability(adev)) {
1540                 init_data.flags.seamless_boot_edp_requested = true;
1541                 init_data.flags.allow_seamless_boot_optimization = true;
1542                 DRM_INFO("Seamless boot condition check passed\n");
1543         }
1544
1545         init_data.flags.enable_mipi_converter_optimization = true;
1546
1547         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1548         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1549
1550         INIT_LIST_HEAD(&adev->dm.da_list);
1551
1552         retrieve_dmi_info(&adev->dm);
1553
1554         /* Display Core create. */
1555         adev->dm.dc = dc_create(&init_data);
1556
1557         if (adev->dm.dc) {
1558                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1559         } else {
1560                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1561                 goto error;
1562         }
1563
1564         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1565                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1566                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1567         }
1568
1569         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1570                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1571         if (dm_should_disable_stutter(adev->pdev))
1572                 adev->dm.dc->debug.disable_stutter = true;
1573
1574         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1575                 adev->dm.dc->debug.disable_stutter = true;
1576
1577         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1578                 adev->dm.dc->debug.disable_dsc = true;
1579         }
1580
1581         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1582                 adev->dm.dc->debug.disable_clock_gate = true;
1583
1584         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1585                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1586
1587         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1588
1589         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1590         adev->dm.dc->debug.ignore_cable_id = true;
1591
1592         r = dm_dmub_hw_init(adev);
1593         if (r) {
1594                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1595                 goto error;
1596         }
1597
1598         dc_hardware_init(adev->dm.dc);
1599
1600         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1601         if (!adev->dm.hpd_rx_offload_wq) {
1602                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1603                 goto error;
1604         }
1605
1606         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1607                 struct dc_phy_addr_space_config pa_config;
1608
1609                 mmhub_read_system_context(adev, &pa_config);
1610
1611                 // Call the DC init_memory func
1612                 dc_setup_system_context(adev->dm.dc, &pa_config);
1613         }
1614
1615         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1616         if (!adev->dm.freesync_module) {
1617                 DRM_ERROR(
1618                 "amdgpu: failed to initialize freesync_module.\n");
1619         } else
1620                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1621                                 adev->dm.freesync_module);
1622
1623         amdgpu_dm_init_color_mod();
1624
1625         if (adev->dm.dc->caps.max_links > 0) {
1626                 adev->dm.vblank_control_workqueue =
1627                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1628                 if (!adev->dm.vblank_control_workqueue)
1629                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1630         }
1631
1632 #ifdef CONFIG_DRM_AMD_DC_HDCP
1633         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1634                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1635
1636                 if (!adev->dm.hdcp_workqueue)
1637                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1638                 else
1639                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1640
1641                 dc_init_callbacks(adev->dm.dc, &init_params);
1642         }
1643 #endif
1644 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1645         adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1646 #endif
1647         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1648                 init_completion(&adev->dm.dmub_aux_transfer_done);
1649                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1650                 if (!adev->dm.dmub_notify) {
1651                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1652                         goto error;
1653                 }
1654
1655                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1656                 if (!adev->dm.delayed_hpd_wq) {
1657                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1658                         goto error;
1659                 }
1660
1661                 amdgpu_dm_outbox_init(adev);
1662                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1663                         dmub_aux_setconfig_callback, false)) {
1664                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1665                         goto error;
1666                 }
1667                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1668                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1669                         goto error;
1670                 }
1671                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1672                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1673                         goto error;
1674                 }
1675         }
1676
1677         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1678          * It is expected that DMUB will resend any pending notifications at this point, for
1679          * example HPD from DPIA.
1680          */
1681         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1682                 dc_enable_dmub_outbox(adev->dm.dc);
1683
1684         if (amdgpu_dm_initialize_drm_device(adev)) {
1685                 DRM_ERROR(
1686                 "amdgpu: failed to initialize sw for display support.\n");
1687                 goto error;
1688         }
1689
1690         /* create fake encoders for MST */
1691         dm_dp_create_fake_mst_encoders(adev);
1692
1693         /* TODO: Add_display_info? */
1694
1695         /* TODO use dynamic cursor width */
1696         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1697         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1698
1699         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1700                 DRM_ERROR(
1701                 "amdgpu: failed to initialize sw for display support.\n");
1702                 goto error;
1703         }
1704
1705
1706         DRM_DEBUG_DRIVER("KMS initialized.\n");
1707
1708         return 0;
1709 error:
1710         amdgpu_dm_fini(adev);
1711
1712         return -EINVAL;
1713 }
1714
1715 static int amdgpu_dm_early_fini(void *handle)
1716 {
1717         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1718
1719         amdgpu_dm_audio_fini(adev);
1720
1721         return 0;
1722 }
1723
1724 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1725 {
1726         int i;
1727
1728         if (adev->dm.vblank_control_workqueue) {
1729                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1730                 adev->dm.vblank_control_workqueue = NULL;
1731         }
1732
1733         for (i = 0; i < adev->dm.display_indexes_num; i++) {
1734                 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1735         }
1736
1737         amdgpu_dm_destroy_drm_device(&adev->dm);
1738
1739 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1740         if (adev->dm.crc_rd_wrk) {
1741                 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1742                 kfree(adev->dm.crc_rd_wrk);
1743                 adev->dm.crc_rd_wrk = NULL;
1744         }
1745 #endif
1746 #ifdef CONFIG_DRM_AMD_DC_HDCP
1747         if (adev->dm.hdcp_workqueue) {
1748                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1749                 adev->dm.hdcp_workqueue = NULL;
1750         }
1751
1752         if (adev->dm.dc)
1753                 dc_deinit_callbacks(adev->dm.dc);
1754 #endif
1755
1756         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1757
1758         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1759                 kfree(adev->dm.dmub_notify);
1760                 adev->dm.dmub_notify = NULL;
1761                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1762                 adev->dm.delayed_hpd_wq = NULL;
1763         }
1764
1765         if (adev->dm.dmub_bo)
1766                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1767                                       &adev->dm.dmub_bo_gpu_addr,
1768                                       &adev->dm.dmub_bo_cpu_addr);
1769
1770         if (adev->dm.hpd_rx_offload_wq) {
1771                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1772                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1773                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1774                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1775                         }
1776                 }
1777
1778                 kfree(adev->dm.hpd_rx_offload_wq);
1779                 adev->dm.hpd_rx_offload_wq = NULL;
1780         }
1781
1782         /* DC Destroy TODO: Replace destroy DAL */
1783         if (adev->dm.dc)
1784                 dc_destroy(&adev->dm.dc);
1785         /*
1786          * TODO: pageflip, vlank interrupt
1787          *
1788          * amdgpu_dm_irq_fini(adev);
1789          */
1790
1791         if (adev->dm.cgs_device) {
1792                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1793                 adev->dm.cgs_device = NULL;
1794         }
1795         if (adev->dm.freesync_module) {
1796                 mod_freesync_destroy(adev->dm.freesync_module);
1797                 adev->dm.freesync_module = NULL;
1798         }
1799
1800         mutex_destroy(&adev->dm.audio_lock);
1801         mutex_destroy(&adev->dm.dc_lock);
1802         mutex_destroy(&adev->dm.dpia_aux_lock);
1803
1804         return;
1805 }
1806
1807 static int load_dmcu_fw(struct amdgpu_device *adev)
1808 {
1809         const char *fw_name_dmcu = NULL;
1810         int r;
1811         const struct dmcu_firmware_header_v1_0 *hdr;
1812
1813         switch(adev->asic_type) {
1814 #if defined(CONFIG_DRM_AMD_DC_SI)
1815         case CHIP_TAHITI:
1816         case CHIP_PITCAIRN:
1817         case CHIP_VERDE:
1818         case CHIP_OLAND:
1819 #endif
1820         case CHIP_BONAIRE:
1821         case CHIP_HAWAII:
1822         case CHIP_KAVERI:
1823         case CHIP_KABINI:
1824         case CHIP_MULLINS:
1825         case CHIP_TONGA:
1826         case CHIP_FIJI:
1827         case CHIP_CARRIZO:
1828         case CHIP_STONEY:
1829         case CHIP_POLARIS11:
1830         case CHIP_POLARIS10:
1831         case CHIP_POLARIS12:
1832         case CHIP_VEGAM:
1833         case CHIP_VEGA10:
1834         case CHIP_VEGA12:
1835         case CHIP_VEGA20:
1836                 return 0;
1837         case CHIP_NAVI12:
1838                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1839                 break;
1840         case CHIP_RAVEN:
1841                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1842                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1843                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1844                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1845                 else
1846                         return 0;
1847                 break;
1848         default:
1849                 switch (adev->ip_versions[DCE_HWIP][0]) {
1850                 case IP_VERSION(2, 0, 2):
1851                 case IP_VERSION(2, 0, 3):
1852                 case IP_VERSION(2, 0, 0):
1853                 case IP_VERSION(2, 1, 0):
1854                 case IP_VERSION(3, 0, 0):
1855                 case IP_VERSION(3, 0, 2):
1856                 case IP_VERSION(3, 0, 3):
1857                 case IP_VERSION(3, 0, 1):
1858                 case IP_VERSION(3, 1, 2):
1859                 case IP_VERSION(3, 1, 3):
1860                 case IP_VERSION(3, 1, 4):
1861                 case IP_VERSION(3, 1, 5):
1862                 case IP_VERSION(3, 1, 6):
1863                 case IP_VERSION(3, 2, 0):
1864                 case IP_VERSION(3, 2, 1):
1865                         return 0;
1866                 default:
1867                         break;
1868                 }
1869                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1870                 return -EINVAL;
1871         }
1872
1873         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1874                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1875                 return 0;
1876         }
1877
1878         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1879         if (r == -ENOENT) {
1880                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1881                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1882                 adev->dm.fw_dmcu = NULL;
1883                 return 0;
1884         }
1885         if (r) {
1886                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1887                         fw_name_dmcu);
1888                 return r;
1889         }
1890
1891         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1892         if (r) {
1893                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1894                         fw_name_dmcu);
1895                 release_firmware(adev->dm.fw_dmcu);
1896                 adev->dm.fw_dmcu = NULL;
1897                 return r;
1898         }
1899
1900         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1901         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1902         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1903         adev->firmware.fw_size +=
1904                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1905
1906         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1907         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1908         adev->firmware.fw_size +=
1909                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1910
1911         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1912
1913         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1914
1915         return 0;
1916 }
1917
1918 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1919 {
1920         struct amdgpu_device *adev = ctx;
1921
1922         return dm_read_reg(adev->dm.dc->ctx, address);
1923 }
1924
1925 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1926                                      uint32_t value)
1927 {
1928         struct amdgpu_device *adev = ctx;
1929
1930         return dm_write_reg(adev->dm.dc->ctx, address, value);
1931 }
1932
1933 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1934 {
1935         struct dmub_srv_create_params create_params;
1936         struct dmub_srv_region_params region_params;
1937         struct dmub_srv_region_info region_info;
1938         struct dmub_srv_fb_params fb_params;
1939         struct dmub_srv_fb_info *fb_info;
1940         struct dmub_srv *dmub_srv;
1941         const struct dmcub_firmware_header_v1_0 *hdr;
1942         const char *fw_name_dmub;
1943         enum dmub_asic dmub_asic;
1944         enum dmub_status status;
1945         int r;
1946
1947         switch (adev->ip_versions[DCE_HWIP][0]) {
1948         case IP_VERSION(2, 1, 0):
1949                 dmub_asic = DMUB_ASIC_DCN21;
1950                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1951                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1952                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1953                 break;
1954         case IP_VERSION(3, 0, 0):
1955                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
1956                         dmub_asic = DMUB_ASIC_DCN30;
1957                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1958                 } else {
1959                         dmub_asic = DMUB_ASIC_DCN30;
1960                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1961                 }
1962                 break;
1963         case IP_VERSION(3, 0, 1):
1964                 dmub_asic = DMUB_ASIC_DCN301;
1965                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1966                 break;
1967         case IP_VERSION(3, 0, 2):
1968                 dmub_asic = DMUB_ASIC_DCN302;
1969                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1970                 break;
1971         case IP_VERSION(3, 0, 3):
1972                 dmub_asic = DMUB_ASIC_DCN303;
1973                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
1974                 break;
1975         case IP_VERSION(3, 1, 2):
1976         case IP_VERSION(3, 1, 3):
1977                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1978                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
1979                 break;
1980         case IP_VERSION(3, 1, 4):
1981                 dmub_asic = DMUB_ASIC_DCN314;
1982                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
1983                 break;
1984         case IP_VERSION(3, 1, 5):
1985                 dmub_asic = DMUB_ASIC_DCN315;
1986                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
1987                 break;
1988         case IP_VERSION(3, 1, 6):
1989                 dmub_asic = DMUB_ASIC_DCN316;
1990                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
1991                 break;
1992         case IP_VERSION(3, 2, 0):
1993                 dmub_asic = DMUB_ASIC_DCN32;
1994                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
1995                 break;
1996         case IP_VERSION(3, 2, 1):
1997                 dmub_asic = DMUB_ASIC_DCN321;
1998                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
1999                 break;
2000         default:
2001                 /* ASIC doesn't support DMUB. */
2002                 return 0;
2003         }
2004
2005         r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
2006         if (r) {
2007                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
2008                 return 0;
2009         }
2010
2011         r = amdgpu_ucode_validate(adev->dm.dmub_fw);
2012         if (r) {
2013                 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
2014                 return 0;
2015         }
2016
2017         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2018         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2019
2020         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2021                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2022                         AMDGPU_UCODE_ID_DMCUB;
2023                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2024                         adev->dm.dmub_fw;
2025                 adev->firmware.fw_size +=
2026                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2027
2028                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2029                          adev->dm.dmcub_fw_version);
2030         }
2031
2032
2033         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2034         dmub_srv = adev->dm.dmub_srv;
2035
2036         if (!dmub_srv) {
2037                 DRM_ERROR("Failed to allocate DMUB service!\n");
2038                 return -ENOMEM;
2039         }
2040
2041         memset(&create_params, 0, sizeof(create_params));
2042         create_params.user_ctx = adev;
2043         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2044         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2045         create_params.asic = dmub_asic;
2046
2047         /* Create the DMUB service. */
2048         status = dmub_srv_create(dmub_srv, &create_params);
2049         if (status != DMUB_STATUS_OK) {
2050                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2051                 return -EINVAL;
2052         }
2053
2054         /* Calculate the size of all the regions for the DMUB service. */
2055         memset(&region_params, 0, sizeof(region_params));
2056
2057         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2058                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2059         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2060         region_params.vbios_size = adev->bios_size;
2061         region_params.fw_bss_data = region_params.bss_data_size ?
2062                 adev->dm.dmub_fw->data +
2063                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2064                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2065         region_params.fw_inst_const =
2066                 adev->dm.dmub_fw->data +
2067                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2068                 PSP_HEADER_BYTES;
2069
2070         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2071                                            &region_info);
2072
2073         if (status != DMUB_STATUS_OK) {
2074                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2075                 return -EINVAL;
2076         }
2077
2078         /*
2079          * Allocate a framebuffer based on the total size of all the regions.
2080          * TODO: Move this into GART.
2081          */
2082         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2083                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
2084                                     &adev->dm.dmub_bo_gpu_addr,
2085                                     &adev->dm.dmub_bo_cpu_addr);
2086         if (r)
2087                 return r;
2088
2089         /* Rebase the regions on the framebuffer address. */
2090         memset(&fb_params, 0, sizeof(fb_params));
2091         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2092         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2093         fb_params.region_info = &region_info;
2094
2095         adev->dm.dmub_fb_info =
2096                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2097         fb_info = adev->dm.dmub_fb_info;
2098
2099         if (!fb_info) {
2100                 DRM_ERROR(
2101                         "Failed to allocate framebuffer info for DMUB service!\n");
2102                 return -ENOMEM;
2103         }
2104
2105         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2106         if (status != DMUB_STATUS_OK) {
2107                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2108                 return -EINVAL;
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int dm_sw_init(void *handle)
2115 {
2116         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2117         int r;
2118
2119         r = dm_dmub_sw_init(adev);
2120         if (r)
2121                 return r;
2122
2123         return load_dmcu_fw(adev);
2124 }
2125
2126 static int dm_sw_fini(void *handle)
2127 {
2128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2129
2130         kfree(adev->dm.dmub_fb_info);
2131         adev->dm.dmub_fb_info = NULL;
2132
2133         if (adev->dm.dmub_srv) {
2134                 dmub_srv_destroy(adev->dm.dmub_srv);
2135                 adev->dm.dmub_srv = NULL;
2136         }
2137
2138         release_firmware(adev->dm.dmub_fw);
2139         adev->dm.dmub_fw = NULL;
2140
2141         release_firmware(adev->dm.fw_dmcu);
2142         adev->dm.fw_dmcu = NULL;
2143
2144         return 0;
2145 }
2146
2147 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2148 {
2149         struct amdgpu_dm_connector *aconnector;
2150         struct drm_connector *connector;
2151         struct drm_connector_list_iter iter;
2152         int ret = 0;
2153
2154         drm_connector_list_iter_begin(dev, &iter);
2155         drm_for_each_connector_iter(connector, &iter) {
2156                 aconnector = to_amdgpu_dm_connector(connector);
2157                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2158                     aconnector->mst_mgr.aux) {
2159                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2160                                          aconnector,
2161                                          aconnector->base.base.id);
2162
2163                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2164                         if (ret < 0) {
2165                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2166                                 aconnector->dc_link->type =
2167                                         dc_connection_single;
2168                                 break;
2169                         }
2170                 }
2171         }
2172         drm_connector_list_iter_end(&iter);
2173
2174         return ret;
2175 }
2176
2177 static int dm_late_init(void *handle)
2178 {
2179         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2180
2181         struct dmcu_iram_parameters params;
2182         unsigned int linear_lut[16];
2183         int i;
2184         struct dmcu *dmcu = NULL;
2185
2186         dmcu = adev->dm.dc->res_pool->dmcu;
2187
2188         for (i = 0; i < 16; i++)
2189                 linear_lut[i] = 0xFFFF * i / 15;
2190
2191         params.set = 0;
2192         params.backlight_ramping_override = false;
2193         params.backlight_ramping_start = 0xCCCC;
2194         params.backlight_ramping_reduction = 0xCCCCCCCC;
2195         params.backlight_lut_array_size = 16;
2196         params.backlight_lut_array = linear_lut;
2197
2198         /* Min backlight level after ABM reduction,  Don't allow below 1%
2199          * 0xFFFF x 0.01 = 0x28F
2200          */
2201         params.min_abm_backlight = 0x28F;
2202         /* In the case where abm is implemented on dmcub,
2203         * dmcu object will be null.
2204         * ABM 2.4 and up are implemented on dmcub.
2205         */
2206         if (dmcu) {
2207                 if (!dmcu_load_iram(dmcu, params))
2208                         return -EINVAL;
2209         } else if (adev->dm.dc->ctx->dmub_srv) {
2210                 struct dc_link *edp_links[MAX_NUM_EDP];
2211                 int edp_num;
2212
2213                 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2214                 for (i = 0; i < edp_num; i++) {
2215                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2216                                 return -EINVAL;
2217                 }
2218         }
2219
2220         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2221 }
2222
2223 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2224 {
2225         struct amdgpu_dm_connector *aconnector;
2226         struct drm_connector *connector;
2227         struct drm_connector_list_iter iter;
2228         struct drm_dp_mst_topology_mgr *mgr;
2229         int ret;
2230         bool need_hotplug = false;
2231
2232         drm_connector_list_iter_begin(dev, &iter);
2233         drm_for_each_connector_iter(connector, &iter) {
2234                 aconnector = to_amdgpu_dm_connector(connector);
2235                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2236                     aconnector->mst_port)
2237                         continue;
2238
2239                 mgr = &aconnector->mst_mgr;
2240
2241                 if (suspend) {
2242                         drm_dp_mst_topology_mgr_suspend(mgr);
2243                 } else {
2244                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2245                         if (ret < 0) {
2246                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2247                                         aconnector->dc_link);
2248                                 need_hotplug = true;
2249                         }
2250                 }
2251         }
2252         drm_connector_list_iter_end(&iter);
2253
2254         if (need_hotplug)
2255                 drm_kms_helper_hotplug_event(dev);
2256 }
2257
2258 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2259 {
2260         int ret = 0;
2261
2262         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2263          * on window driver dc implementation.
2264          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2265          * should be passed to smu during boot up and resume from s3.
2266          * boot up: dc calculate dcn watermark clock settings within dc_create,
2267          * dcn20_resource_construct
2268          * then call pplib functions below to pass the settings to smu:
2269          * smu_set_watermarks_for_clock_ranges
2270          * smu_set_watermarks_table
2271          * navi10_set_watermarks_table
2272          * smu_write_watermarks_table
2273          *
2274          * For Renoir, clock settings of dcn watermark are also fixed values.
2275          * dc has implemented different flow for window driver:
2276          * dc_hardware_init / dc_set_power_state
2277          * dcn10_init_hw
2278          * notify_wm_ranges
2279          * set_wm_ranges
2280          * -- Linux
2281          * smu_set_watermarks_for_clock_ranges
2282          * renoir_set_watermarks_table
2283          * smu_write_watermarks_table
2284          *
2285          * For Linux,
2286          * dc_hardware_init -> amdgpu_dm_init
2287          * dc_set_power_state --> dm_resume
2288          *
2289          * therefore, this function apply to navi10/12/14 but not Renoir
2290          * *
2291          */
2292         switch (adev->ip_versions[DCE_HWIP][0]) {
2293         case IP_VERSION(2, 0, 2):
2294         case IP_VERSION(2, 0, 0):
2295                 break;
2296         default:
2297                 return 0;
2298         }
2299
2300         ret = amdgpu_dpm_write_watermarks_table(adev);
2301         if (ret) {
2302                 DRM_ERROR("Failed to update WMTABLE!\n");
2303                 return ret;
2304         }
2305
2306         return 0;
2307 }
2308
2309 /**
2310  * dm_hw_init() - Initialize DC device
2311  * @handle: The base driver device containing the amdgpu_dm device.
2312  *
2313  * Initialize the &struct amdgpu_display_manager device. This involves calling
2314  * the initializers of each DM component, then populating the struct with them.
2315  *
2316  * Although the function implies hardware initialization, both hardware and
2317  * software are initialized here. Splitting them out to their relevant init
2318  * hooks is a future TODO item.
2319  *
2320  * Some notable things that are initialized here:
2321  *
2322  * - Display Core, both software and hardware
2323  * - DC modules that we need (freesync and color management)
2324  * - DRM software states
2325  * - Interrupt sources and handlers
2326  * - Vblank support
2327  * - Debug FS entries, if enabled
2328  */
2329 static int dm_hw_init(void *handle)
2330 {
2331         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2332         /* Create DAL display manager */
2333         amdgpu_dm_init(adev);
2334         amdgpu_dm_hpd_init(adev);
2335
2336         return 0;
2337 }
2338
2339 /**
2340  * dm_hw_fini() - Teardown DC device
2341  * @handle: The base driver device containing the amdgpu_dm device.
2342  *
2343  * Teardown components within &struct amdgpu_display_manager that require
2344  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2345  * were loaded. Also flush IRQ workqueues and disable them.
2346  */
2347 static int dm_hw_fini(void *handle)
2348 {
2349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2350
2351         amdgpu_dm_hpd_fini(adev);
2352
2353         amdgpu_dm_irq_fini(adev);
2354         amdgpu_dm_fini(adev);
2355         return 0;
2356 }
2357
2358
2359 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2360                                  struct dc_state *state, bool enable)
2361 {
2362         enum dc_irq_source irq_source;
2363         struct amdgpu_crtc *acrtc;
2364         int rc = -EBUSY;
2365         int i = 0;
2366
2367         for (i = 0; i < state->stream_count; i++) {
2368                 acrtc = get_crtc_by_otg_inst(
2369                                 adev, state->stream_status[i].primary_otg_inst);
2370
2371                 if (acrtc && state->stream_status[i].plane_count != 0) {
2372                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2373                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2374                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2375                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2376                         if (rc)
2377                                 DRM_WARN("Failed to %s pflip interrupts\n",
2378                                          enable ? "enable" : "disable");
2379
2380                         if (enable) {
2381                                 rc = dm_enable_vblank(&acrtc->base);
2382                                 if (rc)
2383                                         DRM_WARN("Failed to enable vblank interrupts\n");
2384                         } else {
2385                                 dm_disable_vblank(&acrtc->base);
2386                         }
2387
2388                 }
2389         }
2390
2391 }
2392
2393 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2394 {
2395         struct dc_state *context = NULL;
2396         enum dc_status res = DC_ERROR_UNEXPECTED;
2397         int i;
2398         struct dc_stream_state *del_streams[MAX_PIPES];
2399         int del_streams_count = 0;
2400
2401         memset(del_streams, 0, sizeof(del_streams));
2402
2403         context = dc_create_state(dc);
2404         if (context == NULL)
2405                 goto context_alloc_fail;
2406
2407         dc_resource_state_copy_construct_current(dc, context);
2408
2409         /* First remove from context all streams */
2410         for (i = 0; i < context->stream_count; i++) {
2411                 struct dc_stream_state *stream = context->streams[i];
2412
2413                 del_streams[del_streams_count++] = stream;
2414         }
2415
2416         /* Remove all planes for removed streams and then remove the streams */
2417         for (i = 0; i < del_streams_count; i++) {
2418                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2419                         res = DC_FAIL_DETACH_SURFACES;
2420                         goto fail;
2421                 }
2422
2423                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2424                 if (res != DC_OK)
2425                         goto fail;
2426         }
2427
2428         res = dc_commit_state(dc, context);
2429
2430 fail:
2431         dc_release_state(context);
2432
2433 context_alloc_fail:
2434         return res;
2435 }
2436
2437 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2438 {
2439         int i;
2440
2441         if (dm->hpd_rx_offload_wq) {
2442                 for (i = 0; i < dm->dc->caps.max_links; i++)
2443                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2444         }
2445 }
2446
2447 static int dm_suspend(void *handle)
2448 {
2449         struct amdgpu_device *adev = handle;
2450         struct amdgpu_display_manager *dm = &adev->dm;
2451         int ret = 0;
2452
2453         if (amdgpu_in_reset(adev)) {
2454                 mutex_lock(&dm->dc_lock);
2455
2456                 dc_allow_idle_optimizations(adev->dm.dc, false);
2457
2458                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2459
2460                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2461
2462                 amdgpu_dm_commit_zero_streams(dm->dc);
2463
2464                 amdgpu_dm_irq_suspend(adev);
2465
2466                 hpd_rx_irq_work_suspend(dm);
2467
2468                 return ret;
2469         }
2470
2471         WARN_ON(adev->dm.cached_state);
2472         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2473
2474         s3_handle_mst(adev_to_drm(adev), true);
2475
2476         amdgpu_dm_irq_suspend(adev);
2477
2478         hpd_rx_irq_work_suspend(dm);
2479
2480         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2481
2482         return 0;
2483 }
2484
2485 struct amdgpu_dm_connector *
2486 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2487                                              struct drm_crtc *crtc)
2488 {
2489         uint32_t i;
2490         struct drm_connector_state *new_con_state;
2491         struct drm_connector *connector;
2492         struct drm_crtc *crtc_from_state;
2493
2494         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2495                 crtc_from_state = new_con_state->crtc;
2496
2497                 if (crtc_from_state == crtc)
2498                         return to_amdgpu_dm_connector(connector);
2499         }
2500
2501         return NULL;
2502 }
2503
2504 static void emulated_link_detect(struct dc_link *link)
2505 {
2506         struct dc_sink_init_data sink_init_data = { 0 };
2507         struct display_sink_capability sink_caps = { 0 };
2508         enum dc_edid_status edid_status;
2509         struct dc_context *dc_ctx = link->ctx;
2510         struct dc_sink *sink = NULL;
2511         struct dc_sink *prev_sink = NULL;
2512
2513         link->type = dc_connection_none;
2514         prev_sink = link->local_sink;
2515
2516         if (prev_sink)
2517                 dc_sink_release(prev_sink);
2518
2519         switch (link->connector_signal) {
2520         case SIGNAL_TYPE_HDMI_TYPE_A: {
2521                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2522                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2523                 break;
2524         }
2525
2526         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2527                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2528                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2529                 break;
2530         }
2531
2532         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2533                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2534                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2535                 break;
2536         }
2537
2538         case SIGNAL_TYPE_LVDS: {
2539                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2540                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2541                 break;
2542         }
2543
2544         case SIGNAL_TYPE_EDP: {
2545                 sink_caps.transaction_type =
2546                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2547                 sink_caps.signal = SIGNAL_TYPE_EDP;
2548                 break;
2549         }
2550
2551         case SIGNAL_TYPE_DISPLAY_PORT: {
2552                 sink_caps.transaction_type =
2553                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2554                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2555                 break;
2556         }
2557
2558         default:
2559                 DC_ERROR("Invalid connector type! signal:%d\n",
2560                         link->connector_signal);
2561                 return;
2562         }
2563
2564         sink_init_data.link = link;
2565         sink_init_data.sink_signal = sink_caps.signal;
2566
2567         sink = dc_sink_create(&sink_init_data);
2568         if (!sink) {
2569                 DC_ERROR("Failed to create sink!\n");
2570                 return;
2571         }
2572
2573         /* dc_sink_create returns a new reference */
2574         link->local_sink = sink;
2575
2576         edid_status = dm_helpers_read_local_edid(
2577                         link->ctx,
2578                         link,
2579                         sink);
2580
2581         if (edid_status != EDID_OK)
2582                 DC_ERROR("Failed to read EDID");
2583
2584 }
2585
2586 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2587                                      struct amdgpu_display_manager *dm)
2588 {
2589         struct {
2590                 struct dc_surface_update surface_updates[MAX_SURFACES];
2591                 struct dc_plane_info plane_infos[MAX_SURFACES];
2592                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2593                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2594                 struct dc_stream_update stream_update;
2595         } * bundle;
2596         int k, m;
2597
2598         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2599
2600         if (!bundle) {
2601                 dm_error("Failed to allocate update bundle\n");
2602                 goto cleanup;
2603         }
2604
2605         for (k = 0; k < dc_state->stream_count; k++) {
2606                 bundle->stream_update.stream = dc_state->streams[k];
2607
2608                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2609                         bundle->surface_updates[m].surface =
2610                                 dc_state->stream_status->plane_states[m];
2611                         bundle->surface_updates[m].surface->force_full_update =
2612                                 true;
2613                 }
2614                 dc_commit_updates_for_stream(
2615                         dm->dc, bundle->surface_updates,
2616                         dc_state->stream_status->plane_count,
2617                         dc_state->streams[k], &bundle->stream_update, dc_state);
2618         }
2619
2620 cleanup:
2621         kfree(bundle);
2622
2623         return;
2624 }
2625
2626 static int dm_resume(void *handle)
2627 {
2628         struct amdgpu_device *adev = handle;
2629         struct drm_device *ddev = adev_to_drm(adev);
2630         struct amdgpu_display_manager *dm = &adev->dm;
2631         struct amdgpu_dm_connector *aconnector;
2632         struct drm_connector *connector;
2633         struct drm_connector_list_iter iter;
2634         struct drm_crtc *crtc;
2635         struct drm_crtc_state *new_crtc_state;
2636         struct dm_crtc_state *dm_new_crtc_state;
2637         struct drm_plane *plane;
2638         struct drm_plane_state *new_plane_state;
2639         struct dm_plane_state *dm_new_plane_state;
2640         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2641         enum dc_connection_type new_connection_type = dc_connection_none;
2642         struct dc_state *dc_state;
2643         int i, r, j;
2644
2645         if (amdgpu_in_reset(adev)) {
2646                 dc_state = dm->cached_dc_state;
2647
2648                 /*
2649                  * The dc->current_state is backed up into dm->cached_dc_state
2650                  * before we commit 0 streams.
2651                  *
2652                  * DC will clear link encoder assignments on the real state
2653                  * but the changes won't propagate over to the copy we made
2654                  * before the 0 streams commit.
2655                  *
2656                  * DC expects that link encoder assignments are *not* valid
2657                  * when committing a state, so as a workaround we can copy
2658                  * off of the current state.
2659                  *
2660                  * We lose the previous assignments, but we had already
2661                  * commit 0 streams anyway.
2662                  */
2663                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2664
2665                 r = dm_dmub_hw_init(adev);
2666                 if (r)
2667                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2668
2669                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2670                 dc_resume(dm->dc);
2671
2672                 amdgpu_dm_irq_resume_early(adev);
2673
2674                 for (i = 0; i < dc_state->stream_count; i++) {
2675                         dc_state->streams[i]->mode_changed = true;
2676                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2677                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2678                                         = 0xffffffff;
2679                         }
2680                 }
2681
2682                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2683                         amdgpu_dm_outbox_init(adev);
2684                         dc_enable_dmub_outbox(adev->dm.dc);
2685                 }
2686
2687                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2688
2689                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2690
2691                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2692
2693                 dc_release_state(dm->cached_dc_state);
2694                 dm->cached_dc_state = NULL;
2695
2696                 amdgpu_dm_irq_resume_late(adev);
2697
2698                 mutex_unlock(&dm->dc_lock);
2699
2700                 return 0;
2701         }
2702         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2703         dc_release_state(dm_state->context);
2704         dm_state->context = dc_create_state(dm->dc);
2705         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2706         dc_resource_state_construct(dm->dc, dm_state->context);
2707
2708         /* Before powering on DC we need to re-initialize DMUB. */
2709         dm_dmub_hw_resume(adev);
2710
2711         /* Re-enable outbox interrupts for DPIA. */
2712         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2713                 amdgpu_dm_outbox_init(adev);
2714                 dc_enable_dmub_outbox(adev->dm.dc);
2715         }
2716
2717         /* power on hardware */
2718         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2719
2720         /* program HPD filter */
2721         dc_resume(dm->dc);
2722
2723         /*
2724          * early enable HPD Rx IRQ, should be done before set mode as short
2725          * pulse interrupts are used for MST
2726          */
2727         amdgpu_dm_irq_resume_early(adev);
2728
2729         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2730         s3_handle_mst(ddev, false);
2731
2732         /* Do detection*/
2733         drm_connector_list_iter_begin(ddev, &iter);
2734         drm_for_each_connector_iter(connector, &iter) {
2735                 aconnector = to_amdgpu_dm_connector(connector);
2736
2737                 /*
2738                  * this is the case when traversing through already created
2739                  * MST connectors, should be skipped
2740                  */
2741                 if (aconnector->dc_link &&
2742                     aconnector->dc_link->type == dc_connection_mst_branch)
2743                         continue;
2744
2745                 mutex_lock(&aconnector->hpd_lock);
2746                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2747                         DRM_ERROR("KMS: Failed to detect connector\n");
2748
2749                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2750                         emulated_link_detect(aconnector->dc_link);
2751                 } else {
2752                         mutex_lock(&dm->dc_lock);
2753                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2754                         mutex_unlock(&dm->dc_lock);
2755                 }
2756
2757                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2758                         aconnector->fake_enable = false;
2759
2760                 if (aconnector->dc_sink)
2761                         dc_sink_release(aconnector->dc_sink);
2762                 aconnector->dc_sink = NULL;
2763                 amdgpu_dm_update_connector_after_detect(aconnector);
2764                 mutex_unlock(&aconnector->hpd_lock);
2765         }
2766         drm_connector_list_iter_end(&iter);
2767
2768         /* Force mode set in atomic commit */
2769         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2770                 new_crtc_state->active_changed = true;
2771
2772         /*
2773          * atomic_check is expected to create the dc states. We need to release
2774          * them here, since they were duplicated as part of the suspend
2775          * procedure.
2776          */
2777         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2778                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2779                 if (dm_new_crtc_state->stream) {
2780                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2781                         dc_stream_release(dm_new_crtc_state->stream);
2782                         dm_new_crtc_state->stream = NULL;
2783                 }
2784         }
2785
2786         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2787                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2788                 if (dm_new_plane_state->dc_state) {
2789                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2790                         dc_plane_state_release(dm_new_plane_state->dc_state);
2791                         dm_new_plane_state->dc_state = NULL;
2792                 }
2793         }
2794
2795         drm_atomic_helper_resume(ddev, dm->cached_state);
2796
2797         dm->cached_state = NULL;
2798
2799         amdgpu_dm_irq_resume_late(adev);
2800
2801         amdgpu_dm_smu_write_watermarks_table(adev);
2802
2803         return 0;
2804 }
2805
2806 /**
2807  * DOC: DM Lifecycle
2808  *
2809  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2810  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2811  * the base driver's device list to be initialized and torn down accordingly.
2812  *
2813  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2814  */
2815
2816 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2817         .name = "dm",
2818         .early_init = dm_early_init,
2819         .late_init = dm_late_init,
2820         .sw_init = dm_sw_init,
2821         .sw_fini = dm_sw_fini,
2822         .early_fini = amdgpu_dm_early_fini,
2823         .hw_init = dm_hw_init,
2824         .hw_fini = dm_hw_fini,
2825         .suspend = dm_suspend,
2826         .resume = dm_resume,
2827         .is_idle = dm_is_idle,
2828         .wait_for_idle = dm_wait_for_idle,
2829         .check_soft_reset = dm_check_soft_reset,
2830         .soft_reset = dm_soft_reset,
2831         .set_clockgating_state = dm_set_clockgating_state,
2832         .set_powergating_state = dm_set_powergating_state,
2833 };
2834
2835 const struct amdgpu_ip_block_version dm_ip_block =
2836 {
2837         .type = AMD_IP_BLOCK_TYPE_DCE,
2838         .major = 1,
2839         .minor = 0,
2840         .rev = 0,
2841         .funcs = &amdgpu_dm_funcs,
2842 };
2843
2844
2845 /**
2846  * DOC: atomic
2847  *
2848  * *WIP*
2849  */
2850
2851 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2852         .fb_create = amdgpu_display_user_framebuffer_create,
2853         .get_format_info = amd_get_format_info,
2854         .atomic_check = amdgpu_dm_atomic_check,
2855         .atomic_commit = drm_atomic_helper_commit,
2856 };
2857
2858 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2859         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2860         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2861 };
2862
2863 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2864 {
2865         struct amdgpu_dm_backlight_caps *caps;
2866         struct amdgpu_display_manager *dm;
2867         struct drm_connector *conn_base;
2868         struct amdgpu_device *adev;
2869         struct dc_link *link = NULL;
2870         struct drm_luminance_range_info *luminance_range;
2871         int i;
2872
2873         if (!aconnector || !aconnector->dc_link)
2874                 return;
2875
2876         link = aconnector->dc_link;
2877         if (link->connector_signal != SIGNAL_TYPE_EDP)
2878                 return;
2879
2880         conn_base = &aconnector->base;
2881         adev = drm_to_adev(conn_base->dev);
2882         dm = &adev->dm;
2883         for (i = 0; i < dm->num_of_edps; i++) {
2884                 if (link == dm->backlight_link[i])
2885                         break;
2886         }
2887         if (i >= dm->num_of_edps)
2888                 return;
2889         caps = &dm->backlight_caps[i];
2890         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2891         caps->aux_support = false;
2892
2893         if (caps->ext_caps->bits.oled == 1 /*||
2894             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2895             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2896                 caps->aux_support = true;
2897
2898         if (amdgpu_backlight == 0)
2899                 caps->aux_support = false;
2900         else if (amdgpu_backlight == 1)
2901                 caps->aux_support = true;
2902
2903         luminance_range = &conn_base->display_info.luminance_range;
2904         caps->aux_min_input_signal = luminance_range->min_luminance;
2905         caps->aux_max_input_signal = luminance_range->max_luminance;
2906 }
2907
2908 void amdgpu_dm_update_connector_after_detect(
2909                 struct amdgpu_dm_connector *aconnector)
2910 {
2911         struct drm_connector *connector = &aconnector->base;
2912         struct drm_device *dev = connector->dev;
2913         struct dc_sink *sink;
2914
2915         /* MST handled by drm_mst framework */
2916         if (aconnector->mst_mgr.mst_state == true)
2917                 return;
2918
2919         sink = aconnector->dc_link->local_sink;
2920         if (sink)
2921                 dc_sink_retain(sink);
2922
2923         /*
2924          * Edid mgmt connector gets first update only in mode_valid hook and then
2925          * the connector sink is set to either fake or physical sink depends on link status.
2926          * Skip if already done during boot.
2927          */
2928         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2929                         && aconnector->dc_em_sink) {
2930
2931                 /*
2932                  * For S3 resume with headless use eml_sink to fake stream
2933                  * because on resume connector->sink is set to NULL
2934                  */
2935                 mutex_lock(&dev->mode_config.mutex);
2936
2937                 if (sink) {
2938                         if (aconnector->dc_sink) {
2939                                 amdgpu_dm_update_freesync_caps(connector, NULL);
2940                                 /*
2941                                  * retain and release below are used to
2942                                  * bump up refcount for sink because the link doesn't point
2943                                  * to it anymore after disconnect, so on next crtc to connector
2944                                  * reshuffle by UMD we will get into unwanted dc_sink release
2945                                  */
2946                                 dc_sink_release(aconnector->dc_sink);
2947                         }
2948                         aconnector->dc_sink = sink;
2949                         dc_sink_retain(aconnector->dc_sink);
2950                         amdgpu_dm_update_freesync_caps(connector,
2951                                         aconnector->edid);
2952                 } else {
2953                         amdgpu_dm_update_freesync_caps(connector, NULL);
2954                         if (!aconnector->dc_sink) {
2955                                 aconnector->dc_sink = aconnector->dc_em_sink;
2956                                 dc_sink_retain(aconnector->dc_sink);
2957                         }
2958                 }
2959
2960                 mutex_unlock(&dev->mode_config.mutex);
2961
2962                 if (sink)
2963                         dc_sink_release(sink);
2964                 return;
2965         }
2966
2967         /*
2968          * TODO: temporary guard to look for proper fix
2969          * if this sink is MST sink, we should not do anything
2970          */
2971         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2972                 dc_sink_release(sink);
2973                 return;
2974         }
2975
2976         if (aconnector->dc_sink == sink) {
2977                 /*
2978                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
2979                  * Do nothing!!
2980                  */
2981                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2982                                 aconnector->connector_id);
2983                 if (sink)
2984                         dc_sink_release(sink);
2985                 return;
2986         }
2987
2988         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2989                 aconnector->connector_id, aconnector->dc_sink, sink);
2990
2991         mutex_lock(&dev->mode_config.mutex);
2992
2993         /*
2994          * 1. Update status of the drm connector
2995          * 2. Send an event and let userspace tell us what to do
2996          */
2997         if (sink) {
2998                 /*
2999                  * TODO: check if we still need the S3 mode update workaround.
3000                  * If yes, put it here.
3001                  */
3002                 if (aconnector->dc_sink) {
3003                         amdgpu_dm_update_freesync_caps(connector, NULL);
3004                         dc_sink_release(aconnector->dc_sink);
3005                 }
3006
3007                 aconnector->dc_sink = sink;
3008                 dc_sink_retain(aconnector->dc_sink);
3009                 if (sink->dc_edid.length == 0) {
3010                         aconnector->edid = NULL;
3011                         if (aconnector->dc_link->aux_mode) {
3012                                 drm_dp_cec_unset_edid(
3013                                         &aconnector->dm_dp_aux.aux);
3014                         }
3015                 } else {
3016                         aconnector->edid =
3017                                 (struct edid *)sink->dc_edid.raw_edid;
3018
3019                         if (aconnector->dc_link->aux_mode)
3020                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3021                                                     aconnector->edid);
3022                 }
3023
3024                 drm_connector_update_edid_property(connector, aconnector->edid);
3025                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3026                 update_connector_ext_caps(aconnector);
3027         } else {
3028                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3029                 amdgpu_dm_update_freesync_caps(connector, NULL);
3030                 drm_connector_update_edid_property(connector, NULL);
3031                 aconnector->num_modes = 0;
3032                 dc_sink_release(aconnector->dc_sink);
3033                 aconnector->dc_sink = NULL;
3034                 aconnector->edid = NULL;
3035 #ifdef CONFIG_DRM_AMD_DC_HDCP
3036                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3037                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3038                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3039 #endif
3040         }
3041
3042         mutex_unlock(&dev->mode_config.mutex);
3043
3044         update_subconnector_property(aconnector);
3045
3046         if (sink)
3047                 dc_sink_release(sink);
3048 }
3049
3050 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3051 {
3052         struct drm_connector *connector = &aconnector->base;
3053         struct drm_device *dev = connector->dev;
3054         enum dc_connection_type new_connection_type = dc_connection_none;
3055         struct amdgpu_device *adev = drm_to_adev(dev);
3056 #ifdef CONFIG_DRM_AMD_DC_HDCP
3057         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3058 #endif
3059         bool ret = false;
3060
3061         if (adev->dm.disable_hpd_irq)
3062                 return;
3063
3064         /*
3065          * In case of failure or MST no need to update connector status or notify the OS
3066          * since (for MST case) MST does this in its own context.
3067          */
3068         mutex_lock(&aconnector->hpd_lock);
3069
3070 #ifdef CONFIG_DRM_AMD_DC_HDCP
3071         if (adev->dm.hdcp_workqueue) {
3072                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3073                 dm_con_state->update_hdcp = true;
3074         }
3075 #endif
3076         if (aconnector->fake_enable)
3077                 aconnector->fake_enable = false;
3078
3079         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3080                 DRM_ERROR("KMS: Failed to detect connector\n");
3081
3082         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3083                 emulated_link_detect(aconnector->dc_link);
3084
3085                 drm_modeset_lock_all(dev);
3086                 dm_restore_drm_connector_state(dev, connector);
3087                 drm_modeset_unlock_all(dev);
3088
3089                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3090                         drm_kms_helper_connector_hotplug_event(connector);
3091         } else {
3092                 mutex_lock(&adev->dm.dc_lock);
3093                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3094                 mutex_unlock(&adev->dm.dc_lock);
3095                 if (ret) {
3096                         amdgpu_dm_update_connector_after_detect(aconnector);
3097
3098                         drm_modeset_lock_all(dev);
3099                         dm_restore_drm_connector_state(dev, connector);
3100                         drm_modeset_unlock_all(dev);
3101
3102                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3103                                 drm_kms_helper_connector_hotplug_event(connector);
3104                 }
3105         }
3106         mutex_unlock(&aconnector->hpd_lock);
3107
3108 }
3109
3110 static void handle_hpd_irq(void *param)
3111 {
3112         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3113
3114         handle_hpd_irq_helper(aconnector);
3115
3116 }
3117
3118 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3119 {
3120         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3121         uint8_t dret;
3122         bool new_irq_handled = false;
3123         int dpcd_addr;
3124         int dpcd_bytes_to_read;
3125
3126         const int max_process_count = 30;
3127         int process_count = 0;
3128
3129         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3130
3131         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3132                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3133                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3134                 dpcd_addr = DP_SINK_COUNT;
3135         } else {
3136                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3137                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3138                 dpcd_addr = DP_SINK_COUNT_ESI;
3139         }
3140
3141         dret = drm_dp_dpcd_read(
3142                 &aconnector->dm_dp_aux.aux,
3143                 dpcd_addr,
3144                 esi,
3145                 dpcd_bytes_to_read);
3146
3147         while (dret == dpcd_bytes_to_read &&
3148                 process_count < max_process_count) {
3149                 uint8_t retry;
3150                 dret = 0;
3151
3152                 process_count++;
3153
3154                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3155                 /* handle HPD short pulse irq */
3156                 if (aconnector->mst_mgr.mst_state)
3157                         drm_dp_mst_hpd_irq(
3158                                 &aconnector->mst_mgr,
3159                                 esi,
3160                                 &new_irq_handled);
3161
3162                 if (new_irq_handled) {
3163                         /* ACK at DPCD to notify down stream */
3164                         const int ack_dpcd_bytes_to_write =
3165                                 dpcd_bytes_to_read - 1;
3166
3167                         for (retry = 0; retry < 3; retry++) {
3168                                 uint8_t wret;
3169
3170                                 wret = drm_dp_dpcd_write(
3171                                         &aconnector->dm_dp_aux.aux,
3172                                         dpcd_addr + 1,
3173                                         &esi[1],
3174                                         ack_dpcd_bytes_to_write);
3175                                 if (wret == ack_dpcd_bytes_to_write)
3176                                         break;
3177                         }
3178
3179                         /* check if there is new irq to be handled */
3180                         dret = drm_dp_dpcd_read(
3181                                 &aconnector->dm_dp_aux.aux,
3182                                 dpcd_addr,
3183                                 esi,
3184                                 dpcd_bytes_to_read);
3185
3186                         new_irq_handled = false;
3187                 } else {
3188                         break;
3189                 }
3190         }
3191
3192         if (process_count == max_process_count)
3193                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3194 }
3195
3196 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3197                                                         union hpd_irq_data hpd_irq_data)
3198 {
3199         struct hpd_rx_irq_offload_work *offload_work =
3200                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3201
3202         if (!offload_work) {
3203                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3204                 return;
3205         }
3206
3207         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3208         offload_work->data = hpd_irq_data;
3209         offload_work->offload_wq = offload_wq;
3210
3211         queue_work(offload_wq->wq, &offload_work->work);
3212         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3213 }
3214
3215 static void handle_hpd_rx_irq(void *param)
3216 {
3217         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3218         struct drm_connector *connector = &aconnector->base;
3219         struct drm_device *dev = connector->dev;
3220         struct dc_link *dc_link = aconnector->dc_link;
3221         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3222         bool result = false;
3223         enum dc_connection_type new_connection_type = dc_connection_none;
3224         struct amdgpu_device *adev = drm_to_adev(dev);
3225         union hpd_irq_data hpd_irq_data;
3226         bool link_loss = false;
3227         bool has_left_work = false;
3228         int idx = aconnector->base.index;
3229         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3230
3231         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3232
3233         if (adev->dm.disable_hpd_irq)
3234                 return;
3235
3236         /*
3237          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3238          * conflict, after implement i2c helper, this mutex should be
3239          * retired.
3240          */
3241         mutex_lock(&aconnector->hpd_lock);
3242
3243         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3244                                                 &link_loss, true, &has_left_work);
3245
3246         if (!has_left_work)
3247                 goto out;
3248
3249         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3250                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3251                 goto out;
3252         }
3253
3254         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3255                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3256                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3257                         dm_handle_mst_sideband_msg(aconnector);
3258                         goto out;
3259                 }
3260
3261                 if (link_loss) {
3262                         bool skip = false;
3263
3264                         spin_lock(&offload_wq->offload_lock);
3265                         skip = offload_wq->is_handling_link_loss;
3266
3267                         if (!skip)
3268                                 offload_wq->is_handling_link_loss = true;
3269
3270                         spin_unlock(&offload_wq->offload_lock);
3271
3272                         if (!skip)
3273                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3274
3275                         goto out;
3276                 }
3277         }
3278
3279 out:
3280         if (result && !is_mst_root_connector) {
3281                 /* Downstream Port status changed. */
3282                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3283                         DRM_ERROR("KMS: Failed to detect connector\n");
3284
3285                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3286                         emulated_link_detect(dc_link);
3287
3288                         if (aconnector->fake_enable)
3289                                 aconnector->fake_enable = false;
3290
3291                         amdgpu_dm_update_connector_after_detect(aconnector);
3292
3293
3294                         drm_modeset_lock_all(dev);
3295                         dm_restore_drm_connector_state(dev, connector);
3296                         drm_modeset_unlock_all(dev);
3297
3298                         drm_kms_helper_connector_hotplug_event(connector);
3299                 } else {
3300                         bool ret = false;
3301
3302                         mutex_lock(&adev->dm.dc_lock);
3303                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3304                         mutex_unlock(&adev->dm.dc_lock);
3305
3306                         if (ret) {
3307                                 if (aconnector->fake_enable)
3308                                         aconnector->fake_enable = false;
3309
3310                                 amdgpu_dm_update_connector_after_detect(aconnector);
3311
3312                                 drm_modeset_lock_all(dev);
3313                                 dm_restore_drm_connector_state(dev, connector);
3314                                 drm_modeset_unlock_all(dev);
3315
3316                                 drm_kms_helper_connector_hotplug_event(connector);
3317                         }
3318                 }
3319         }
3320 #ifdef CONFIG_DRM_AMD_DC_HDCP
3321         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3322                 if (adev->dm.hdcp_workqueue)
3323                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3324         }
3325 #endif
3326
3327         if (dc_link->type != dc_connection_mst_branch)
3328                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3329
3330         mutex_unlock(&aconnector->hpd_lock);
3331 }
3332
3333 static void register_hpd_handlers(struct amdgpu_device *adev)
3334 {
3335         struct drm_device *dev = adev_to_drm(adev);
3336         struct drm_connector *connector;
3337         struct amdgpu_dm_connector *aconnector;
3338         const struct dc_link *dc_link;
3339         struct dc_interrupt_params int_params = {0};
3340
3341         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3342         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3343
3344         list_for_each_entry(connector,
3345                         &dev->mode_config.connector_list, head) {
3346
3347                 aconnector = to_amdgpu_dm_connector(connector);
3348                 dc_link = aconnector->dc_link;
3349
3350                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3351                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3352                         int_params.irq_source = dc_link->irq_source_hpd;
3353
3354                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3355                                         handle_hpd_irq,
3356                                         (void *) aconnector);
3357                 }
3358
3359                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3360
3361                         /* Also register for DP short pulse (hpd_rx). */
3362                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3363                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3364
3365                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3366                                         handle_hpd_rx_irq,
3367                                         (void *) aconnector);
3368
3369                         if (adev->dm.hpd_rx_offload_wq)
3370                                 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3371                                         aconnector;
3372                 }
3373         }
3374 }
3375
3376 #if defined(CONFIG_DRM_AMD_DC_SI)
3377 /* Register IRQ sources and initialize IRQ callbacks */
3378 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3379 {
3380         struct dc *dc = adev->dm.dc;
3381         struct common_irq_params *c_irq_params;
3382         struct dc_interrupt_params int_params = {0};
3383         int r;
3384         int i;
3385         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3386
3387         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3388         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3389
3390         /*
3391          * Actions of amdgpu_irq_add_id():
3392          * 1. Register a set() function with base driver.
3393          *    Base driver will call set() function to enable/disable an
3394          *    interrupt in DC hardware.
3395          * 2. Register amdgpu_dm_irq_handler().
3396          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3397          *    coming from DC hardware.
3398          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3399          *    for acknowledging and handling. */
3400
3401         /* Use VBLANK interrupt */
3402         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3403                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3404                 if (r) {
3405                         DRM_ERROR("Failed to add crtc irq id!\n");
3406                         return r;
3407                 }
3408
3409                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3410                 int_params.irq_source =
3411                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3412
3413                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3414
3415                 c_irq_params->adev = adev;
3416                 c_irq_params->irq_src = int_params.irq_source;
3417
3418                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3419                                 dm_crtc_high_irq, c_irq_params);
3420         }
3421
3422         /* Use GRPH_PFLIP interrupt */
3423         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3424                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3425                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3426                 if (r) {
3427                         DRM_ERROR("Failed to add page flip irq id!\n");
3428                         return r;
3429                 }
3430
3431                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3432                 int_params.irq_source =
3433                         dc_interrupt_to_irq_source(dc, i, 0);
3434
3435                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3436
3437                 c_irq_params->adev = adev;
3438                 c_irq_params->irq_src = int_params.irq_source;
3439
3440                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3441                                 dm_pflip_high_irq, c_irq_params);
3442
3443         }
3444
3445         /* HPD */
3446         r = amdgpu_irq_add_id(adev, client_id,
3447                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3448         if (r) {
3449                 DRM_ERROR("Failed to add hpd irq id!\n");
3450                 return r;
3451         }
3452
3453         register_hpd_handlers(adev);
3454
3455         return 0;
3456 }
3457 #endif
3458
3459 /* Register IRQ sources and initialize IRQ callbacks */
3460 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3461 {
3462         struct dc *dc = adev->dm.dc;
3463         struct common_irq_params *c_irq_params;
3464         struct dc_interrupt_params int_params = {0};
3465         int r;
3466         int i;
3467         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3468
3469         if (adev->family >= AMDGPU_FAMILY_AI)
3470                 client_id = SOC15_IH_CLIENTID_DCE;
3471
3472         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3473         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3474
3475         /*
3476          * Actions of amdgpu_irq_add_id():
3477          * 1. Register a set() function with base driver.
3478          *    Base driver will call set() function to enable/disable an
3479          *    interrupt in DC hardware.
3480          * 2. Register amdgpu_dm_irq_handler().
3481          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3482          *    coming from DC hardware.
3483          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3484          *    for acknowledging and handling. */
3485
3486         /* Use VBLANK interrupt */
3487         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3488                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3489                 if (r) {
3490                         DRM_ERROR("Failed to add crtc irq id!\n");
3491                         return r;
3492                 }
3493
3494                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3495                 int_params.irq_source =
3496                         dc_interrupt_to_irq_source(dc, i, 0);
3497
3498                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3499
3500                 c_irq_params->adev = adev;
3501                 c_irq_params->irq_src = int_params.irq_source;
3502
3503                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3504                                 dm_crtc_high_irq, c_irq_params);
3505         }
3506
3507         /* Use VUPDATE interrupt */
3508         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3509                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3510                 if (r) {
3511                         DRM_ERROR("Failed to add vupdate irq id!\n");
3512                         return r;
3513                 }
3514
3515                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3516                 int_params.irq_source =
3517                         dc_interrupt_to_irq_source(dc, i, 0);
3518
3519                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3520
3521                 c_irq_params->adev = adev;
3522                 c_irq_params->irq_src = int_params.irq_source;
3523
3524                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3525                                 dm_vupdate_high_irq, c_irq_params);
3526         }
3527
3528         /* Use GRPH_PFLIP interrupt */
3529         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3530                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3531                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3532                 if (r) {
3533                         DRM_ERROR("Failed to add page flip irq id!\n");
3534                         return r;
3535                 }
3536
3537                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3538                 int_params.irq_source =
3539                         dc_interrupt_to_irq_source(dc, i, 0);
3540
3541                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3542
3543                 c_irq_params->adev = adev;
3544                 c_irq_params->irq_src = int_params.irq_source;
3545
3546                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3547                                 dm_pflip_high_irq, c_irq_params);
3548
3549         }
3550
3551         /* HPD */
3552         r = amdgpu_irq_add_id(adev, client_id,
3553                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3554         if (r) {
3555                 DRM_ERROR("Failed to add hpd irq id!\n");
3556                 return r;
3557         }
3558
3559         register_hpd_handlers(adev);
3560
3561         return 0;
3562 }
3563
3564 /* Register IRQ sources and initialize IRQ callbacks */
3565 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3566 {
3567         struct dc *dc = adev->dm.dc;
3568         struct common_irq_params *c_irq_params;
3569         struct dc_interrupt_params int_params = {0};
3570         int r;
3571         int i;
3572 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3573         static const unsigned int vrtl_int_srcid[] = {
3574                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3575                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3576                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3577                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3578                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3579                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3580         };
3581 #endif
3582
3583         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3584         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3585
3586         /*
3587          * Actions of amdgpu_irq_add_id():
3588          * 1. Register a set() function with base driver.
3589          *    Base driver will call set() function to enable/disable an
3590          *    interrupt in DC hardware.
3591          * 2. Register amdgpu_dm_irq_handler().
3592          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3593          *    coming from DC hardware.
3594          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3595          *    for acknowledging and handling.
3596          */
3597
3598         /* Use VSTARTUP interrupt */
3599         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3600                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3601                         i++) {
3602                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3603
3604                 if (r) {
3605                         DRM_ERROR("Failed to add crtc irq id!\n");
3606                         return r;
3607                 }
3608
3609                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3610                 int_params.irq_source =
3611                         dc_interrupt_to_irq_source(dc, i, 0);
3612
3613                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3614
3615                 c_irq_params->adev = adev;
3616                 c_irq_params->irq_src = int_params.irq_source;
3617
3618                 amdgpu_dm_irq_register_interrupt(
3619                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3620         }
3621
3622         /* Use otg vertical line interrupt */
3623 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3624         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3625                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3626                                 vrtl_int_srcid[i], &adev->vline0_irq);
3627
3628                 if (r) {
3629                         DRM_ERROR("Failed to add vline0 irq id!\n");
3630                         return r;
3631                 }
3632
3633                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3634                 int_params.irq_source =
3635                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3636
3637                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3638                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3639                         break;
3640                 }
3641
3642                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3643                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3644
3645                 c_irq_params->adev = adev;
3646                 c_irq_params->irq_src = int_params.irq_source;
3647
3648                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3649                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3650         }
3651 #endif
3652
3653         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3654          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3655          * to trigger at end of each vblank, regardless of state of the lock,
3656          * matching DCE behaviour.
3657          */
3658         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3659              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3660              i++) {
3661                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3662
3663                 if (r) {
3664                         DRM_ERROR("Failed to add vupdate irq id!\n");
3665                         return r;
3666                 }
3667
3668                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3669                 int_params.irq_source =
3670                         dc_interrupt_to_irq_source(dc, i, 0);
3671
3672                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3673
3674                 c_irq_params->adev = adev;
3675                 c_irq_params->irq_src = int_params.irq_source;
3676
3677                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3678                                 dm_vupdate_high_irq, c_irq_params);
3679         }
3680
3681         /* Use GRPH_PFLIP interrupt */
3682         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3683                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3684                         i++) {
3685                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3686                 if (r) {
3687                         DRM_ERROR("Failed to add page flip irq id!\n");
3688                         return r;
3689                 }
3690
3691                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3692                 int_params.irq_source =
3693                         dc_interrupt_to_irq_source(dc, i, 0);
3694
3695                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3696
3697                 c_irq_params->adev = adev;
3698                 c_irq_params->irq_src = int_params.irq_source;
3699
3700                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3701                                 dm_pflip_high_irq, c_irq_params);
3702
3703         }
3704
3705         /* HPD */
3706         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3707                         &adev->hpd_irq);
3708         if (r) {
3709                 DRM_ERROR("Failed to add hpd irq id!\n");
3710                 return r;
3711         }
3712
3713         register_hpd_handlers(adev);
3714
3715         return 0;
3716 }
3717 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3718 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3719 {
3720         struct dc *dc = adev->dm.dc;
3721         struct common_irq_params *c_irq_params;
3722         struct dc_interrupt_params int_params = {0};
3723         int r, i;
3724
3725         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3726         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3727
3728         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3729                         &adev->dmub_outbox_irq);
3730         if (r) {
3731                 DRM_ERROR("Failed to add outbox irq id!\n");
3732                 return r;
3733         }
3734
3735         if (dc->ctx->dmub_srv) {
3736                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3737                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3738                 int_params.irq_source =
3739                 dc_interrupt_to_irq_source(dc, i, 0);
3740
3741                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3742
3743                 c_irq_params->adev = adev;
3744                 c_irq_params->irq_src = int_params.irq_source;
3745
3746                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3747                                 dm_dmub_outbox1_low_irq, c_irq_params);
3748         }
3749
3750         return 0;
3751 }
3752
3753 /*
3754  * Acquires the lock for the atomic state object and returns
3755  * the new atomic state.
3756  *
3757  * This should only be called during atomic check.
3758  */
3759 int dm_atomic_get_state(struct drm_atomic_state *state,
3760                         struct dm_atomic_state **dm_state)
3761 {
3762         struct drm_device *dev = state->dev;
3763         struct amdgpu_device *adev = drm_to_adev(dev);
3764         struct amdgpu_display_manager *dm = &adev->dm;
3765         struct drm_private_state *priv_state;
3766
3767         if (*dm_state)
3768                 return 0;
3769
3770         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3771         if (IS_ERR(priv_state))
3772                 return PTR_ERR(priv_state);
3773
3774         *dm_state = to_dm_atomic_state(priv_state);
3775
3776         return 0;
3777 }
3778
3779 static struct dm_atomic_state *
3780 dm_atomic_get_new_state(struct drm_atomic_state *state)
3781 {
3782         struct drm_device *dev = state->dev;
3783         struct amdgpu_device *adev = drm_to_adev(dev);
3784         struct amdgpu_display_manager *dm = &adev->dm;
3785         struct drm_private_obj *obj;
3786         struct drm_private_state *new_obj_state;
3787         int i;
3788
3789         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3790                 if (obj->funcs == dm->atomic_obj.funcs)
3791                         return to_dm_atomic_state(new_obj_state);
3792         }
3793
3794         return NULL;
3795 }
3796
3797 static struct drm_private_state *
3798 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3799 {
3800         struct dm_atomic_state *old_state, *new_state;
3801
3802         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3803         if (!new_state)
3804                 return NULL;
3805
3806         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3807
3808         old_state = to_dm_atomic_state(obj->state);
3809
3810         if (old_state && old_state->context)
3811                 new_state->context = dc_copy_state(old_state->context);
3812
3813         if (!new_state->context) {
3814                 kfree(new_state);
3815                 return NULL;
3816         }
3817
3818         return &new_state->base;
3819 }
3820
3821 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3822                                     struct drm_private_state *state)
3823 {
3824         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3825
3826         if (dm_state && dm_state->context)
3827                 dc_release_state(dm_state->context);
3828
3829         kfree(dm_state);
3830 }
3831
3832 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3833         .atomic_duplicate_state = dm_atomic_duplicate_state,
3834         .atomic_destroy_state = dm_atomic_destroy_state,
3835 };
3836
3837 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3838 {
3839         struct dm_atomic_state *state;
3840         int r;
3841
3842         adev->mode_info.mode_config_initialized = true;
3843
3844         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3845         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3846
3847         adev_to_drm(adev)->mode_config.max_width = 16384;
3848         adev_to_drm(adev)->mode_config.max_height = 16384;
3849
3850         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3851         if (adev->asic_type == CHIP_HAWAII)
3852                 /* disable prefer shadow for now due to hibernation issues */
3853                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3854         else
3855                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3856         /* indicates support for immediate flip */
3857         adev_to_drm(adev)->mode_config.async_page_flip = true;
3858
3859         state = kzalloc(sizeof(*state), GFP_KERNEL);
3860         if (!state)
3861                 return -ENOMEM;
3862
3863         state->context = dc_create_state(adev->dm.dc);
3864         if (!state->context) {
3865                 kfree(state);
3866                 return -ENOMEM;
3867         }
3868
3869         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3870
3871         drm_atomic_private_obj_init(adev_to_drm(adev),
3872                                     &adev->dm.atomic_obj,
3873                                     &state->base,
3874                                     &dm_atomic_state_funcs);
3875
3876         r = amdgpu_display_modeset_create_props(adev);
3877         if (r) {
3878                 dc_release_state(state->context);
3879                 kfree(state);
3880                 return r;
3881         }
3882
3883         r = amdgpu_dm_audio_init(adev);
3884         if (r) {
3885                 dc_release_state(state->context);
3886                 kfree(state);
3887                 return r;
3888         }
3889
3890         return 0;
3891 }
3892
3893 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3894 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3895 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3896
3897 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3898                                             int bl_idx)
3899 {
3900 #if defined(CONFIG_ACPI)
3901         struct amdgpu_dm_backlight_caps caps;
3902
3903         memset(&caps, 0, sizeof(caps));
3904
3905         if (dm->backlight_caps[bl_idx].caps_valid)
3906                 return;
3907
3908         amdgpu_acpi_get_backlight_caps(&caps);
3909         if (caps.caps_valid) {
3910                 dm->backlight_caps[bl_idx].caps_valid = true;
3911                 if (caps.aux_support)
3912                         return;
3913                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3914                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3915         } else {
3916                 dm->backlight_caps[bl_idx].min_input_signal =
3917                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3918                 dm->backlight_caps[bl_idx].max_input_signal =
3919                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3920         }
3921 #else
3922         if (dm->backlight_caps[bl_idx].aux_support)
3923                 return;
3924
3925         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3926         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3927 #endif
3928 }
3929
3930 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3931                                 unsigned *min, unsigned *max)
3932 {
3933         if (!caps)
3934                 return 0;
3935
3936         if (caps->aux_support) {
3937                 // Firmware limits are in nits, DC API wants millinits.
3938                 *max = 1000 * caps->aux_max_input_signal;
3939                 *min = 1000 * caps->aux_min_input_signal;
3940         } else {
3941                 // Firmware limits are 8-bit, PWM control is 16-bit.
3942                 *max = 0x101 * caps->max_input_signal;
3943                 *min = 0x101 * caps->min_input_signal;
3944         }
3945         return 1;
3946 }
3947
3948 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3949                                         uint32_t brightness)
3950 {
3951         unsigned min, max;
3952
3953         if (!get_brightness_range(caps, &min, &max))
3954                 return brightness;
3955
3956         // Rescale 0..255 to min..max
3957         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3958                                        AMDGPU_MAX_BL_LEVEL);
3959 }
3960
3961 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3962                                       uint32_t brightness)
3963 {
3964         unsigned min, max;
3965
3966         if (!get_brightness_range(caps, &min, &max))
3967                 return brightness;
3968
3969         if (brightness < min)
3970                 return 0;
3971         // Rescale min..max to 0..255
3972         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3973                                  max - min);
3974 }
3975
3976 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
3977                                          int bl_idx,
3978                                          u32 user_brightness)
3979 {
3980         struct amdgpu_dm_backlight_caps caps;
3981         struct dc_link *link;
3982         u32 brightness;
3983         bool rc;
3984
3985         amdgpu_dm_update_backlight_caps(dm, bl_idx);
3986         caps = dm->backlight_caps[bl_idx];
3987
3988         dm->brightness[bl_idx] = user_brightness;
3989         /* update scratch register */
3990         if (bl_idx == 0)
3991                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
3992         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
3993         link = (struct dc_link *)dm->backlight_link[bl_idx];
3994
3995         /* Change brightness based on AUX property */
3996         if (caps.aux_support) {
3997                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3998                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3999                 if (!rc)
4000                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4001         } else {
4002                 rc = dc_link_set_backlight_level(link, brightness, 0);
4003                 if (!rc)
4004                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4005         }
4006
4007         if (rc)
4008                 dm->actual_brightness[bl_idx] = user_brightness;
4009 }
4010
4011 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4012 {
4013         struct amdgpu_display_manager *dm = bl_get_data(bd);
4014         int i;
4015
4016         for (i = 0; i < dm->num_of_edps; i++) {
4017                 if (bd == dm->backlight_dev[i])
4018                         break;
4019         }
4020         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4021                 i = 0;
4022         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4023
4024         return 0;
4025 }
4026
4027 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4028                                          int bl_idx)
4029 {
4030         struct amdgpu_dm_backlight_caps caps;
4031         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4032
4033         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4034         caps = dm->backlight_caps[bl_idx];
4035
4036         if (caps.aux_support) {
4037                 u32 avg, peak;
4038                 bool rc;
4039
4040                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4041                 if (!rc)
4042                         return dm->brightness[bl_idx];
4043                 return convert_brightness_to_user(&caps, avg);
4044         } else {
4045                 int ret = dc_link_get_backlight_level(link);
4046
4047                 if (ret == DC_ERROR_UNEXPECTED)
4048                         return dm->brightness[bl_idx];
4049                 return convert_brightness_to_user(&caps, ret);
4050         }
4051 }
4052
4053 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4054 {
4055         struct amdgpu_display_manager *dm = bl_get_data(bd);
4056         int i;
4057
4058         for (i = 0; i < dm->num_of_edps; i++) {
4059                 if (bd == dm->backlight_dev[i])
4060                         break;
4061         }
4062         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4063                 i = 0;
4064         return amdgpu_dm_backlight_get_level(dm, i);
4065 }
4066
4067 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4068         .options = BL_CORE_SUSPENDRESUME,
4069         .get_brightness = amdgpu_dm_backlight_get_brightness,
4070         .update_status  = amdgpu_dm_backlight_update_status,
4071 };
4072
4073 static void
4074 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4075 {
4076         char bl_name[16];
4077         struct backlight_properties props = { 0 };
4078
4079         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4080         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4081
4082         if (!acpi_video_backlight_use_native()) {
4083                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4084                 /* Try registering an ACPI video backlight device instead. */
4085                 acpi_video_register_backlight();
4086                 return;
4087         }
4088
4089         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4090         props.brightness = AMDGPU_MAX_BL_LEVEL;
4091         props.type = BACKLIGHT_RAW;
4092
4093         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4094                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4095
4096         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4097                                                                        adev_to_drm(dm->adev)->dev,
4098                                                                        dm,
4099                                                                        &amdgpu_dm_backlight_ops,
4100                                                                        &props);
4101
4102         if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4103                 DRM_ERROR("DM: Backlight registration failed!\n");
4104         else
4105                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4106 }
4107
4108 static int initialize_plane(struct amdgpu_display_manager *dm,
4109                             struct amdgpu_mode_info *mode_info, int plane_id,
4110                             enum drm_plane_type plane_type,
4111                             const struct dc_plane_cap *plane_cap)
4112 {
4113         struct drm_plane *plane;
4114         unsigned long possible_crtcs;
4115         int ret = 0;
4116
4117         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4118         if (!plane) {
4119                 DRM_ERROR("KMS: Failed to allocate plane\n");
4120                 return -ENOMEM;
4121         }
4122         plane->type = plane_type;
4123
4124         /*
4125          * HACK: IGT tests expect that the primary plane for a CRTC
4126          * can only have one possible CRTC. Only expose support for
4127          * any CRTC if they're not going to be used as a primary plane
4128          * for a CRTC - like overlay or underlay planes.
4129          */
4130         possible_crtcs = 1 << plane_id;
4131         if (plane_id >= dm->dc->caps.max_streams)
4132                 possible_crtcs = 0xff;
4133
4134         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4135
4136         if (ret) {
4137                 DRM_ERROR("KMS: Failed to initialize plane\n");
4138                 kfree(plane);
4139                 return ret;
4140         }
4141
4142         if (mode_info)
4143                 mode_info->planes[plane_id] = plane;
4144
4145         return ret;
4146 }
4147
4148
4149 static void register_backlight_device(struct amdgpu_display_manager *dm,
4150                                       struct dc_link *link)
4151 {
4152         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4153             link->type != dc_connection_none) {
4154                 /*
4155                  * Event if registration failed, we should continue with
4156                  * DM initialization because not having a backlight control
4157                  * is better then a black screen.
4158                  */
4159                 if (!dm->backlight_dev[dm->num_of_edps])
4160                         amdgpu_dm_register_backlight_device(dm);
4161
4162                 if (dm->backlight_dev[dm->num_of_edps]) {
4163                         dm->backlight_link[dm->num_of_edps] = link;
4164                         dm->num_of_edps++;
4165                 }
4166         }
4167 }
4168
4169 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4170
4171 /*
4172  * In this architecture, the association
4173  * connector -> encoder -> crtc
4174  * id not really requried. The crtc and connector will hold the
4175  * display_index as an abstraction to use with DAL component
4176  *
4177  * Returns 0 on success
4178  */
4179 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4180 {
4181         struct amdgpu_display_manager *dm = &adev->dm;
4182         int32_t i;
4183         struct amdgpu_dm_connector *aconnector = NULL;
4184         struct amdgpu_encoder *aencoder = NULL;
4185         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4186         uint32_t link_cnt;
4187         int32_t primary_planes;
4188         enum dc_connection_type new_connection_type = dc_connection_none;
4189         const struct dc_plane_cap *plane;
4190         bool psr_feature_enabled = false;
4191
4192         dm->display_indexes_num = dm->dc->caps.max_streams;
4193         /* Update the actual used number of crtc */
4194         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4195
4196         link_cnt = dm->dc->caps.max_links;
4197         if (amdgpu_dm_mode_config_init(dm->adev)) {
4198                 DRM_ERROR("DM: Failed to initialize mode config\n");
4199                 return -EINVAL;
4200         }
4201
4202         /* There is one primary plane per CRTC */
4203         primary_planes = dm->dc->caps.max_streams;
4204         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4205
4206         /*
4207          * Initialize primary planes, implicit planes for legacy IOCTLS.
4208          * Order is reversed to match iteration order in atomic check.
4209          */
4210         for (i = (primary_planes - 1); i >= 0; i--) {
4211                 plane = &dm->dc->caps.planes[i];
4212
4213                 if (initialize_plane(dm, mode_info, i,
4214                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4215                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4216                         goto fail;
4217                 }
4218         }
4219
4220         /*
4221          * Initialize overlay planes, index starting after primary planes.
4222          * These planes have a higher DRM index than the primary planes since
4223          * they should be considered as having a higher z-order.
4224          * Order is reversed to match iteration order in atomic check.
4225          *
4226          * Only support DCN for now, and only expose one so we don't encourage
4227          * userspace to use up all the pipes.
4228          */
4229         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4230                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4231
4232                 /* Do not create overlay if MPO disabled */
4233                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4234                         break;
4235
4236                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4237                         continue;
4238
4239                 if (!plane->blends_with_above || !plane->blends_with_below)
4240                         continue;
4241
4242                 if (!plane->pixel_format_support.argb8888)
4243                         continue;
4244
4245                 if (initialize_plane(dm, NULL, primary_planes + i,
4246                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4247                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4248                         goto fail;
4249                 }
4250
4251                 /* Only create one overlay plane. */
4252                 break;
4253         }
4254
4255         for (i = 0; i < dm->dc->caps.max_streams; i++)
4256                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4257                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4258                         goto fail;
4259                 }
4260
4261         /* Use Outbox interrupt */
4262         switch (adev->ip_versions[DCE_HWIP][0]) {
4263         case IP_VERSION(3, 0, 0):
4264         case IP_VERSION(3, 1, 2):
4265         case IP_VERSION(3, 1, 3):
4266         case IP_VERSION(3, 1, 4):
4267         case IP_VERSION(3, 1, 5):
4268         case IP_VERSION(3, 1, 6):
4269         case IP_VERSION(3, 2, 0):
4270         case IP_VERSION(3, 2, 1):
4271         case IP_VERSION(2, 1, 0):
4272                 if (register_outbox_irq_handlers(dm->adev)) {
4273                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4274                         goto fail;
4275                 }
4276                 break;
4277         default:
4278                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4279                               adev->ip_versions[DCE_HWIP][0]);
4280         }
4281
4282         /* Determine whether to enable PSR support by default. */
4283         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4284                 switch (adev->ip_versions[DCE_HWIP][0]) {
4285                 case IP_VERSION(3, 1, 2):
4286                 case IP_VERSION(3, 1, 3):
4287                 case IP_VERSION(3, 1, 4):
4288                 case IP_VERSION(3, 1, 5):
4289                 case IP_VERSION(3, 1, 6):
4290                 case IP_VERSION(3, 2, 0):
4291                 case IP_VERSION(3, 2, 1):
4292                         psr_feature_enabled = true;
4293                         break;
4294                 default:
4295                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4296                         break;
4297                 }
4298         }
4299
4300         /* loops over all connectors on the board */
4301         for (i = 0; i < link_cnt; i++) {
4302                 struct dc_link *link = NULL;
4303
4304                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4305                         DRM_ERROR(
4306                                 "KMS: Cannot support more than %d display indexes\n",
4307                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4308                         continue;
4309                 }
4310
4311                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4312                 if (!aconnector)
4313                         goto fail;
4314
4315                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4316                 if (!aencoder)
4317                         goto fail;
4318
4319                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4320                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4321                         goto fail;
4322                 }
4323
4324                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4325                         DRM_ERROR("KMS: Failed to initialize connector\n");
4326                         goto fail;
4327                 }
4328
4329                 link = dc_get_link_at_index(dm->dc, i);
4330
4331                 if (!dc_link_detect_sink(link, &new_connection_type))
4332                         DRM_ERROR("KMS: Failed to detect connector\n");
4333
4334                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4335                         emulated_link_detect(link);
4336                         amdgpu_dm_update_connector_after_detect(aconnector);
4337                 } else {
4338                         bool ret = false;
4339
4340                         mutex_lock(&dm->dc_lock);
4341                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4342                         mutex_unlock(&dm->dc_lock);
4343
4344                         if (ret) {
4345                                 amdgpu_dm_update_connector_after_detect(aconnector);
4346                                 register_backlight_device(dm, link);
4347
4348                                 if (dm->num_of_edps)
4349                                         update_connector_ext_caps(aconnector);
4350
4351                                 if (psr_feature_enabled)
4352                                         amdgpu_dm_set_psr_caps(link);
4353
4354                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4355                                  * PSR is also supported.
4356                                  */
4357                                 if (link->psr_settings.psr_feature_enabled)
4358                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4359                         }
4360                 }
4361                 amdgpu_set_panel_orientation(&aconnector->base);
4362         }
4363
4364         /* If we didn't find a panel, notify the acpi video detection */
4365         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4366                 acpi_video_report_nolcd();
4367
4368         /* Software is initialized. Now we can register interrupt handlers. */
4369         switch (adev->asic_type) {
4370 #if defined(CONFIG_DRM_AMD_DC_SI)
4371         case CHIP_TAHITI:
4372         case CHIP_PITCAIRN:
4373         case CHIP_VERDE:
4374         case CHIP_OLAND:
4375                 if (dce60_register_irq_handlers(dm->adev)) {
4376                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4377                         goto fail;
4378                 }
4379                 break;
4380 #endif
4381         case CHIP_BONAIRE:
4382         case CHIP_HAWAII:
4383         case CHIP_KAVERI:
4384         case CHIP_KABINI:
4385         case CHIP_MULLINS:
4386         case CHIP_TONGA:
4387         case CHIP_FIJI:
4388         case CHIP_CARRIZO:
4389         case CHIP_STONEY:
4390         case CHIP_POLARIS11:
4391         case CHIP_POLARIS10:
4392         case CHIP_POLARIS12:
4393         case CHIP_VEGAM:
4394         case CHIP_VEGA10:
4395         case CHIP_VEGA12:
4396         case CHIP_VEGA20:
4397                 if (dce110_register_irq_handlers(dm->adev)) {
4398                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4399                         goto fail;
4400                 }
4401                 break;
4402         default:
4403                 switch (adev->ip_versions[DCE_HWIP][0]) {
4404                 case IP_VERSION(1, 0, 0):
4405                 case IP_VERSION(1, 0, 1):
4406                 case IP_VERSION(2, 0, 2):
4407                 case IP_VERSION(2, 0, 3):
4408                 case IP_VERSION(2, 0, 0):
4409                 case IP_VERSION(2, 1, 0):
4410                 case IP_VERSION(3, 0, 0):
4411                 case IP_VERSION(3, 0, 2):
4412                 case IP_VERSION(3, 0, 3):
4413                 case IP_VERSION(3, 0, 1):
4414                 case IP_VERSION(3, 1, 2):
4415                 case IP_VERSION(3, 1, 3):
4416                 case IP_VERSION(3, 1, 4):
4417                 case IP_VERSION(3, 1, 5):
4418                 case IP_VERSION(3, 1, 6):
4419                 case IP_VERSION(3, 2, 0):
4420                 case IP_VERSION(3, 2, 1):
4421                         if (dcn10_register_irq_handlers(dm->adev)) {
4422                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4423                                 goto fail;
4424                         }
4425                         break;
4426                 default:
4427                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4428                                         adev->ip_versions[DCE_HWIP][0]);
4429                         goto fail;
4430                 }
4431                 break;
4432         }
4433
4434         return 0;
4435 fail:
4436         kfree(aencoder);
4437         kfree(aconnector);
4438
4439         return -EINVAL;
4440 }
4441
4442 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4443 {
4444         drm_atomic_private_obj_fini(&dm->atomic_obj);
4445         return;
4446 }
4447
4448 /******************************************************************************
4449  * amdgpu_display_funcs functions
4450  *****************************************************************************/
4451
4452 /*
4453  * dm_bandwidth_update - program display watermarks
4454  *
4455  * @adev: amdgpu_device pointer
4456  *
4457  * Calculate and program the display watermarks and line buffer allocation.
4458  */
4459 static void dm_bandwidth_update(struct amdgpu_device *adev)
4460 {
4461         /* TODO: implement later */
4462 }
4463
4464 static const struct amdgpu_display_funcs dm_display_funcs = {
4465         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4466         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4467         .backlight_set_level = NULL, /* never called for DC */
4468         .backlight_get_level = NULL, /* never called for DC */
4469         .hpd_sense = NULL,/* called unconditionally */
4470         .hpd_set_polarity = NULL, /* called unconditionally */
4471         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4472         .page_flip_get_scanoutpos =
4473                 dm_crtc_get_scanoutpos,/* called unconditionally */
4474         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4475         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4476 };
4477
4478 #if defined(CONFIG_DEBUG_KERNEL_DC)
4479
4480 static ssize_t s3_debug_store(struct device *device,
4481                               struct device_attribute *attr,
4482                               const char *buf,
4483                               size_t count)
4484 {
4485         int ret;
4486         int s3_state;
4487         struct drm_device *drm_dev = dev_get_drvdata(device);
4488         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4489
4490         ret = kstrtoint(buf, 0, &s3_state);
4491
4492         if (ret == 0) {
4493                 if (s3_state) {
4494                         dm_resume(adev);
4495                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4496                 } else
4497                         dm_suspend(adev);
4498         }
4499
4500         return ret == 0 ? count : 0;
4501 }
4502
4503 DEVICE_ATTR_WO(s3_debug);
4504
4505 #endif
4506
4507 static int dm_early_init(void *handle)
4508 {
4509         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4510
4511         switch (adev->asic_type) {
4512 #if defined(CONFIG_DRM_AMD_DC_SI)
4513         case CHIP_TAHITI:
4514         case CHIP_PITCAIRN:
4515         case CHIP_VERDE:
4516                 adev->mode_info.num_crtc = 6;
4517                 adev->mode_info.num_hpd = 6;
4518                 adev->mode_info.num_dig = 6;
4519                 break;
4520         case CHIP_OLAND:
4521                 adev->mode_info.num_crtc = 2;
4522                 adev->mode_info.num_hpd = 2;
4523                 adev->mode_info.num_dig = 2;
4524                 break;
4525 #endif
4526         case CHIP_BONAIRE:
4527         case CHIP_HAWAII:
4528                 adev->mode_info.num_crtc = 6;
4529                 adev->mode_info.num_hpd = 6;
4530                 adev->mode_info.num_dig = 6;
4531                 break;
4532         case CHIP_KAVERI:
4533                 adev->mode_info.num_crtc = 4;
4534                 adev->mode_info.num_hpd = 6;
4535                 adev->mode_info.num_dig = 7;
4536                 break;
4537         case CHIP_KABINI:
4538         case CHIP_MULLINS:
4539                 adev->mode_info.num_crtc = 2;
4540                 adev->mode_info.num_hpd = 6;
4541                 adev->mode_info.num_dig = 6;
4542                 break;
4543         case CHIP_FIJI:
4544         case CHIP_TONGA:
4545                 adev->mode_info.num_crtc = 6;
4546                 adev->mode_info.num_hpd = 6;
4547                 adev->mode_info.num_dig = 7;
4548                 break;
4549         case CHIP_CARRIZO:
4550                 adev->mode_info.num_crtc = 3;
4551                 adev->mode_info.num_hpd = 6;
4552                 adev->mode_info.num_dig = 9;
4553                 break;
4554         case CHIP_STONEY:
4555                 adev->mode_info.num_crtc = 2;
4556                 adev->mode_info.num_hpd = 6;
4557                 adev->mode_info.num_dig = 9;
4558                 break;
4559         case CHIP_POLARIS11:
4560         case CHIP_POLARIS12:
4561                 adev->mode_info.num_crtc = 5;
4562                 adev->mode_info.num_hpd = 5;
4563                 adev->mode_info.num_dig = 5;
4564                 break;
4565         case CHIP_POLARIS10:
4566         case CHIP_VEGAM:
4567                 adev->mode_info.num_crtc = 6;
4568                 adev->mode_info.num_hpd = 6;
4569                 adev->mode_info.num_dig = 6;
4570                 break;
4571         case CHIP_VEGA10:
4572         case CHIP_VEGA12:
4573         case CHIP_VEGA20:
4574                 adev->mode_info.num_crtc = 6;
4575                 adev->mode_info.num_hpd = 6;
4576                 adev->mode_info.num_dig = 6;
4577                 break;
4578         default:
4579
4580                 switch (adev->ip_versions[DCE_HWIP][0]) {
4581                 case IP_VERSION(2, 0, 2):
4582                 case IP_VERSION(3, 0, 0):
4583                         adev->mode_info.num_crtc = 6;
4584                         adev->mode_info.num_hpd = 6;
4585                         adev->mode_info.num_dig = 6;
4586                         break;
4587                 case IP_VERSION(2, 0, 0):
4588                 case IP_VERSION(3, 0, 2):
4589                         adev->mode_info.num_crtc = 5;
4590                         adev->mode_info.num_hpd = 5;
4591                         adev->mode_info.num_dig = 5;
4592                         break;
4593                 case IP_VERSION(2, 0, 3):
4594                 case IP_VERSION(3, 0, 3):
4595                         adev->mode_info.num_crtc = 2;
4596                         adev->mode_info.num_hpd = 2;
4597                         adev->mode_info.num_dig = 2;
4598                         break;
4599                 case IP_VERSION(1, 0, 0):
4600                 case IP_VERSION(1, 0, 1):
4601                 case IP_VERSION(3, 0, 1):
4602                 case IP_VERSION(2, 1, 0):
4603                 case IP_VERSION(3, 1, 2):
4604                 case IP_VERSION(3, 1, 3):
4605                 case IP_VERSION(3, 1, 4):
4606                 case IP_VERSION(3, 1, 5):
4607                 case IP_VERSION(3, 1, 6):
4608                 case IP_VERSION(3, 2, 0):
4609                 case IP_VERSION(3, 2, 1):
4610                         adev->mode_info.num_crtc = 4;
4611                         adev->mode_info.num_hpd = 4;
4612                         adev->mode_info.num_dig = 4;
4613                         break;
4614                 default:
4615                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4616                                         adev->ip_versions[DCE_HWIP][0]);
4617                         return -EINVAL;
4618                 }
4619                 break;
4620         }
4621
4622         amdgpu_dm_set_irq_funcs(adev);
4623
4624         if (adev->mode_info.funcs == NULL)
4625                 adev->mode_info.funcs = &dm_display_funcs;
4626
4627         /*
4628          * Note: Do NOT change adev->audio_endpt_rreg and
4629          * adev->audio_endpt_wreg because they are initialised in
4630          * amdgpu_device_init()
4631          */
4632 #if defined(CONFIG_DEBUG_KERNEL_DC)
4633         device_create_file(
4634                 adev_to_drm(adev)->dev,
4635                 &dev_attr_s3_debug);
4636 #endif
4637         adev->dc_enabled = true;
4638
4639         return 0;
4640 }
4641
4642 static bool modereset_required(struct drm_crtc_state *crtc_state)
4643 {
4644         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4645 }
4646
4647 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4648 {
4649         drm_encoder_cleanup(encoder);
4650         kfree(encoder);
4651 }
4652
4653 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4654         .destroy = amdgpu_dm_encoder_destroy,
4655 };
4656
4657 static int
4658 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4659                             const enum surface_pixel_format format,
4660                             enum dc_color_space *color_space)
4661 {
4662         bool full_range;
4663
4664         *color_space = COLOR_SPACE_SRGB;
4665
4666         /* DRM color properties only affect non-RGB formats. */
4667         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4668                 return 0;
4669
4670         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4671
4672         switch (plane_state->color_encoding) {
4673         case DRM_COLOR_YCBCR_BT601:
4674                 if (full_range)
4675                         *color_space = COLOR_SPACE_YCBCR601;
4676                 else
4677                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4678                 break;
4679
4680         case DRM_COLOR_YCBCR_BT709:
4681                 if (full_range)
4682                         *color_space = COLOR_SPACE_YCBCR709;
4683                 else
4684                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4685                 break;
4686
4687         case DRM_COLOR_YCBCR_BT2020:
4688                 if (full_range)
4689                         *color_space = COLOR_SPACE_2020_YCBCR;
4690                 else
4691                         return -EINVAL;
4692                 break;
4693
4694         default:
4695                 return -EINVAL;
4696         }
4697
4698         return 0;
4699 }
4700
4701 static int
4702 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4703                             const struct drm_plane_state *plane_state,
4704                             const uint64_t tiling_flags,
4705                             struct dc_plane_info *plane_info,
4706                             struct dc_plane_address *address,
4707                             bool tmz_surface,
4708                             bool force_disable_dcc)
4709 {
4710         const struct drm_framebuffer *fb = plane_state->fb;
4711         const struct amdgpu_framebuffer *afb =
4712                 to_amdgpu_framebuffer(plane_state->fb);
4713         int ret;
4714
4715         memset(plane_info, 0, sizeof(*plane_info));
4716
4717         switch (fb->format->format) {
4718         case DRM_FORMAT_C8:
4719                 plane_info->format =
4720                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4721                 break;
4722         case DRM_FORMAT_RGB565:
4723                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4724                 break;
4725         case DRM_FORMAT_XRGB8888:
4726         case DRM_FORMAT_ARGB8888:
4727                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4728                 break;
4729         case DRM_FORMAT_XRGB2101010:
4730         case DRM_FORMAT_ARGB2101010:
4731                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4732                 break;
4733         case DRM_FORMAT_XBGR2101010:
4734         case DRM_FORMAT_ABGR2101010:
4735                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4736                 break;
4737         case DRM_FORMAT_XBGR8888:
4738         case DRM_FORMAT_ABGR8888:
4739                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4740                 break;
4741         case DRM_FORMAT_NV21:
4742                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4743                 break;
4744         case DRM_FORMAT_NV12:
4745                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4746                 break;
4747         case DRM_FORMAT_P010:
4748                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4749                 break;
4750         case DRM_FORMAT_XRGB16161616F:
4751         case DRM_FORMAT_ARGB16161616F:
4752                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4753                 break;
4754         case DRM_FORMAT_XBGR16161616F:
4755         case DRM_FORMAT_ABGR16161616F:
4756                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4757                 break;
4758         case DRM_FORMAT_XRGB16161616:
4759         case DRM_FORMAT_ARGB16161616:
4760                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4761                 break;
4762         case DRM_FORMAT_XBGR16161616:
4763         case DRM_FORMAT_ABGR16161616:
4764                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4765                 break;
4766         default:
4767                 DRM_ERROR(
4768                         "Unsupported screen format %p4cc\n",
4769                         &fb->format->format);
4770                 return -EINVAL;
4771         }
4772
4773         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4774         case DRM_MODE_ROTATE_0:
4775                 plane_info->rotation = ROTATION_ANGLE_0;
4776                 break;
4777         case DRM_MODE_ROTATE_90:
4778                 plane_info->rotation = ROTATION_ANGLE_90;
4779                 break;
4780         case DRM_MODE_ROTATE_180:
4781                 plane_info->rotation = ROTATION_ANGLE_180;
4782                 break;
4783         case DRM_MODE_ROTATE_270:
4784                 plane_info->rotation = ROTATION_ANGLE_270;
4785                 break;
4786         default:
4787                 plane_info->rotation = ROTATION_ANGLE_0;
4788                 break;
4789         }
4790
4791
4792         plane_info->visible = true;
4793         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4794
4795         plane_info->layer_index = plane_state->normalized_zpos;
4796
4797         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4798                                           &plane_info->color_space);
4799         if (ret)
4800                 return ret;
4801
4802         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4803                                            plane_info->rotation, tiling_flags,
4804                                            &plane_info->tiling_info,
4805                                            &plane_info->plane_size,
4806                                            &plane_info->dcc, address,
4807                                            tmz_surface, force_disable_dcc);
4808         if (ret)
4809                 return ret;
4810
4811         fill_blending_from_plane_state(
4812                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4813                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4814
4815         return 0;
4816 }
4817
4818 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4819                                     struct dc_plane_state *dc_plane_state,
4820                                     struct drm_plane_state *plane_state,
4821                                     struct drm_crtc_state *crtc_state)
4822 {
4823         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4824         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4825         struct dc_scaling_info scaling_info;
4826         struct dc_plane_info plane_info;
4827         int ret;
4828         bool force_disable_dcc = false;
4829
4830         ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4831         if (ret)
4832                 return ret;
4833
4834         dc_plane_state->src_rect = scaling_info.src_rect;
4835         dc_plane_state->dst_rect = scaling_info.dst_rect;
4836         dc_plane_state->clip_rect = scaling_info.clip_rect;
4837         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4838
4839         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4840         ret = fill_dc_plane_info_and_addr(adev, plane_state,
4841                                           afb->tiling_flags,
4842                                           &plane_info,
4843                                           &dc_plane_state->address,
4844                                           afb->tmz_surface,
4845                                           force_disable_dcc);
4846         if (ret)
4847                 return ret;
4848
4849         dc_plane_state->format = plane_info.format;
4850         dc_plane_state->color_space = plane_info.color_space;
4851         dc_plane_state->format = plane_info.format;
4852         dc_plane_state->plane_size = plane_info.plane_size;
4853         dc_plane_state->rotation = plane_info.rotation;
4854         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4855         dc_plane_state->stereo_format = plane_info.stereo_format;
4856         dc_plane_state->tiling_info = plane_info.tiling_info;
4857         dc_plane_state->visible = plane_info.visible;
4858         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4859         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4860         dc_plane_state->global_alpha = plane_info.global_alpha;
4861         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4862         dc_plane_state->dcc = plane_info.dcc;
4863         dc_plane_state->layer_index = plane_info.layer_index;
4864         dc_plane_state->flip_int_enabled = true;
4865
4866         /*
4867          * Always set input transfer function, since plane state is refreshed
4868          * every time.
4869          */
4870         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4871         if (ret)
4872                 return ret;
4873
4874         return 0;
4875 }
4876
4877 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
4878                                       struct rect *dirty_rect, int32_t x,
4879                                       int32_t y, int32_t width, int32_t height,
4880                                       int *i, bool ffu)
4881 {
4882         if (*i > DC_MAX_DIRTY_RECTS)
4883                 return;
4884
4885         if (*i == DC_MAX_DIRTY_RECTS)
4886                 goto out;
4887
4888         dirty_rect->x = x;
4889         dirty_rect->y = y;
4890         dirty_rect->width = width;
4891         dirty_rect->height = height;
4892
4893         if (ffu)
4894                 drm_dbg(plane->dev,
4895                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4896                         plane->base.id, width, height);
4897         else
4898                 drm_dbg(plane->dev,
4899                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
4900                         plane->base.id, x, y, width, height);
4901
4902 out:
4903         (*i)++;
4904 }
4905
4906 /**
4907  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4908  *
4909  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4910  *         remote fb
4911  * @old_plane_state: Old state of @plane
4912  * @new_plane_state: New state of @plane
4913  * @crtc_state: New state of CRTC connected to the @plane
4914  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4915  *
4916  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4917  * (referred to as "damage clips" in DRM nomenclature) that require updating on
4918  * the eDP remote buffer. The responsibility of specifying the dirty regions is
4919  * amdgpu_dm's.
4920  *
4921  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4922  * plane with regions that require flushing to the eDP remote buffer. In
4923  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4924  * implicitly provide damage clips without any client support via the plane
4925  * bounds.
4926  */
4927 static void fill_dc_dirty_rects(struct drm_plane *plane,
4928                                 struct drm_plane_state *old_plane_state,
4929                                 struct drm_plane_state *new_plane_state,
4930                                 struct drm_crtc_state *crtc_state,
4931                                 struct dc_flip_addrs *flip_addrs)
4932 {
4933         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4934         struct rect *dirty_rects = flip_addrs->dirty_rects;
4935         uint32_t num_clips;
4936         struct drm_mode_rect *clips;
4937         bool bb_changed;
4938         bool fb_changed;
4939         uint32_t i = 0;
4940
4941         /*
4942          * Cursor plane has it's own dirty rect update interface. See
4943          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
4944          */
4945         if (plane->type == DRM_PLANE_TYPE_CURSOR)
4946                 return;
4947
4948         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
4949         clips = drm_plane_get_damage_clips(new_plane_state);
4950
4951         if (!dm_crtc_state->mpo_requested) {
4952                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
4953                         goto ffu;
4954
4955                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
4956                         fill_dc_dirty_rect(new_plane_state->plane,
4957                                            &dirty_rects[i], clips->x1,
4958                                            clips->y1, clips->x2 - clips->x1,
4959                                            clips->y2 - clips->y1,
4960                                            &flip_addrs->dirty_rect_count,
4961                                            false);
4962                 return;
4963         }
4964
4965         /*
4966          * MPO is requested. Add entire plane bounding box to dirty rects if
4967          * flipped to or damaged.
4968          *
4969          * If plane is moved or resized, also add old bounding box to dirty
4970          * rects.
4971          */
4972         fb_changed = old_plane_state->fb->base.id !=
4973                      new_plane_state->fb->base.id;
4974         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
4975                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
4976                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
4977                       old_plane_state->crtc_h != new_plane_state->crtc_h);
4978
4979         drm_dbg(plane->dev,
4980                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
4981                 new_plane_state->plane->base.id,
4982                 bb_changed, fb_changed, num_clips);
4983
4984         if (bb_changed) {
4985                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
4986                                    new_plane_state->crtc_x,
4987                                    new_plane_state->crtc_y,
4988                                    new_plane_state->crtc_w,
4989                                    new_plane_state->crtc_h, &i, false);
4990
4991                 /* Add old plane bounding-box if plane is moved or resized */
4992                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
4993                                    old_plane_state->crtc_x,
4994                                    old_plane_state->crtc_y,
4995                                    old_plane_state->crtc_w,
4996                                    old_plane_state->crtc_h, &i, false);
4997         }
4998
4999         if (num_clips) {
5000                 for (; i < num_clips; clips++)
5001                         fill_dc_dirty_rect(new_plane_state->plane,
5002                                            &dirty_rects[i], clips->x1,
5003                                            clips->y1, clips->x2 - clips->x1,
5004                                            clips->y2 - clips->y1, &i, false);
5005         } else if (fb_changed && !bb_changed) {
5006                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5007                                    new_plane_state->crtc_x,
5008                                    new_plane_state->crtc_y,
5009                                    new_plane_state->crtc_w,
5010                                    new_plane_state->crtc_h, &i, false);
5011         }
5012
5013         if (i > DC_MAX_DIRTY_RECTS)
5014                 goto ffu;
5015
5016         flip_addrs->dirty_rect_count = i;
5017         return;
5018
5019 ffu:
5020         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5021                            dm_crtc_state->base.mode.crtc_hdisplay,
5022                            dm_crtc_state->base.mode.crtc_vdisplay,
5023                            &flip_addrs->dirty_rect_count, true);
5024 }
5025
5026 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5027                                            const struct dm_connector_state *dm_state,
5028                                            struct dc_stream_state *stream)
5029 {
5030         enum amdgpu_rmx_type rmx_type;
5031
5032         struct rect src = { 0 }; /* viewport in composition space*/
5033         struct rect dst = { 0 }; /* stream addressable area */
5034
5035         /* no mode. nothing to be done */
5036         if (!mode)
5037                 return;
5038
5039         /* Full screen scaling by default */
5040         src.width = mode->hdisplay;
5041         src.height = mode->vdisplay;
5042         dst.width = stream->timing.h_addressable;
5043         dst.height = stream->timing.v_addressable;
5044
5045         if (dm_state) {
5046                 rmx_type = dm_state->scaling;
5047                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5048                         if (src.width * dst.height <
5049                                         src.height * dst.width) {
5050                                 /* height needs less upscaling/more downscaling */
5051                                 dst.width = src.width *
5052                                                 dst.height / src.height;
5053                         } else {
5054                                 /* width needs less upscaling/more downscaling */
5055                                 dst.height = src.height *
5056                                                 dst.width / src.width;
5057                         }
5058                 } else if (rmx_type == RMX_CENTER) {
5059                         dst = src;
5060                 }
5061
5062                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5063                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5064
5065                 if (dm_state->underscan_enable) {
5066                         dst.x += dm_state->underscan_hborder / 2;
5067                         dst.y += dm_state->underscan_vborder / 2;
5068                         dst.width -= dm_state->underscan_hborder;
5069                         dst.height -= dm_state->underscan_vborder;
5070                 }
5071         }
5072
5073         stream->src = src;
5074         stream->dst = dst;
5075
5076         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5077                       dst.x, dst.y, dst.width, dst.height);
5078
5079 }
5080
5081 static enum dc_color_depth
5082 convert_color_depth_from_display_info(const struct drm_connector *connector,
5083                                       bool is_y420, int requested_bpc)
5084 {
5085         uint8_t bpc;
5086
5087         if (is_y420) {
5088                 bpc = 8;
5089
5090                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5091                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5092                         bpc = 16;
5093                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5094                         bpc = 12;
5095                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5096                         bpc = 10;
5097         } else {
5098                 bpc = (uint8_t)connector->display_info.bpc;
5099                 /* Assume 8 bpc by default if no bpc is specified. */
5100                 bpc = bpc ? bpc : 8;
5101         }
5102
5103         if (requested_bpc > 0) {
5104                 /*
5105                  * Cap display bpc based on the user requested value.
5106                  *
5107                  * The value for state->max_bpc may not correctly updated
5108                  * depending on when the connector gets added to the state
5109                  * or if this was called outside of atomic check, so it
5110                  * can't be used directly.
5111                  */
5112                 bpc = min_t(u8, bpc, requested_bpc);
5113
5114                 /* Round down to the nearest even number. */
5115                 bpc = bpc - (bpc & 1);
5116         }
5117
5118         switch (bpc) {
5119         case 0:
5120                 /*
5121                  * Temporary Work around, DRM doesn't parse color depth for
5122                  * EDID revision before 1.4
5123                  * TODO: Fix edid parsing
5124                  */
5125                 return COLOR_DEPTH_888;
5126         case 6:
5127                 return COLOR_DEPTH_666;
5128         case 8:
5129                 return COLOR_DEPTH_888;
5130         case 10:
5131                 return COLOR_DEPTH_101010;
5132         case 12:
5133                 return COLOR_DEPTH_121212;
5134         case 14:
5135                 return COLOR_DEPTH_141414;
5136         case 16:
5137                 return COLOR_DEPTH_161616;
5138         default:
5139                 return COLOR_DEPTH_UNDEFINED;
5140         }
5141 }
5142
5143 static enum dc_aspect_ratio
5144 get_aspect_ratio(const struct drm_display_mode *mode_in)
5145 {
5146         /* 1-1 mapping, since both enums follow the HDMI spec. */
5147         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5148 }
5149
5150 static enum dc_color_space
5151 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5152 {
5153         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5154
5155         switch (dc_crtc_timing->pixel_encoding) {
5156         case PIXEL_ENCODING_YCBCR422:
5157         case PIXEL_ENCODING_YCBCR444:
5158         case PIXEL_ENCODING_YCBCR420:
5159         {
5160                 /*
5161                  * 27030khz is the separation point between HDTV and SDTV
5162                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5163                  * respectively
5164                  */
5165                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5166                         if (dc_crtc_timing->flags.Y_ONLY)
5167                                 color_space =
5168                                         COLOR_SPACE_YCBCR709_LIMITED;
5169                         else
5170                                 color_space = COLOR_SPACE_YCBCR709;
5171                 } else {
5172                         if (dc_crtc_timing->flags.Y_ONLY)
5173                                 color_space =
5174                                         COLOR_SPACE_YCBCR601_LIMITED;
5175                         else
5176                                 color_space = COLOR_SPACE_YCBCR601;
5177                 }
5178
5179         }
5180         break;
5181         case PIXEL_ENCODING_RGB:
5182                 color_space = COLOR_SPACE_SRGB;
5183                 break;
5184
5185         default:
5186                 WARN_ON(1);
5187                 break;
5188         }
5189
5190         return color_space;
5191 }
5192
5193 static bool adjust_colour_depth_from_display_info(
5194         struct dc_crtc_timing *timing_out,
5195         const struct drm_display_info *info)
5196 {
5197         enum dc_color_depth depth = timing_out->display_color_depth;
5198         int normalized_clk;
5199         do {
5200                 normalized_clk = timing_out->pix_clk_100hz / 10;
5201                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5202                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5203                         normalized_clk /= 2;
5204                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5205                 switch (depth) {
5206                 case COLOR_DEPTH_888:
5207                         break;
5208                 case COLOR_DEPTH_101010:
5209                         normalized_clk = (normalized_clk * 30) / 24;
5210                         break;
5211                 case COLOR_DEPTH_121212:
5212                         normalized_clk = (normalized_clk * 36) / 24;
5213                         break;
5214                 case COLOR_DEPTH_161616:
5215                         normalized_clk = (normalized_clk * 48) / 24;
5216                         break;
5217                 default:
5218                         /* The above depths are the only ones valid for HDMI. */
5219                         return false;
5220                 }
5221                 if (normalized_clk <= info->max_tmds_clock) {
5222                         timing_out->display_color_depth = depth;
5223                         return true;
5224                 }
5225         } while (--depth > COLOR_DEPTH_666);
5226         return false;
5227 }
5228
5229 static void fill_stream_properties_from_drm_display_mode(
5230         struct dc_stream_state *stream,
5231         const struct drm_display_mode *mode_in,
5232         const struct drm_connector *connector,
5233         const struct drm_connector_state *connector_state,
5234         const struct dc_stream_state *old_stream,
5235         int requested_bpc)
5236 {
5237         struct dc_crtc_timing *timing_out = &stream->timing;
5238         const struct drm_display_info *info = &connector->display_info;
5239         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5240         struct hdmi_vendor_infoframe hv_frame;
5241         struct hdmi_avi_infoframe avi_frame;
5242
5243         memset(&hv_frame, 0, sizeof(hv_frame));
5244         memset(&avi_frame, 0, sizeof(avi_frame));
5245
5246         timing_out->h_border_left = 0;
5247         timing_out->h_border_right = 0;
5248         timing_out->v_border_top = 0;
5249         timing_out->v_border_bottom = 0;
5250         /* TODO: un-hardcode */
5251         if (drm_mode_is_420_only(info, mode_in)
5252                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5253                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5254         else if (drm_mode_is_420_also(info, mode_in)
5255                         && aconnector->force_yuv420_output)
5256                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5257         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5258                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5259                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5260         else
5261                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5262
5263         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5264         timing_out->display_color_depth = convert_color_depth_from_display_info(
5265                 connector,
5266                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5267                 requested_bpc);
5268         timing_out->scan_type = SCANNING_TYPE_NODATA;
5269         timing_out->hdmi_vic = 0;
5270
5271         if (old_stream) {
5272                 timing_out->vic = old_stream->timing.vic;
5273                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5274                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5275         } else {
5276                 timing_out->vic = drm_match_cea_mode(mode_in);
5277                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5278                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5279                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5280                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5281         }
5282
5283         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5284                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5285                 timing_out->vic = avi_frame.video_code;
5286                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5287                 timing_out->hdmi_vic = hv_frame.vic;
5288         }
5289
5290         if (is_freesync_video_mode(mode_in, aconnector)) {
5291                 timing_out->h_addressable = mode_in->hdisplay;
5292                 timing_out->h_total = mode_in->htotal;
5293                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5294                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5295                 timing_out->v_total = mode_in->vtotal;
5296                 timing_out->v_addressable = mode_in->vdisplay;
5297                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5298                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5299                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5300         } else {
5301                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5302                 timing_out->h_total = mode_in->crtc_htotal;
5303                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5304                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5305                 timing_out->v_total = mode_in->crtc_vtotal;
5306                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5307                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5308                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5309                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5310         }
5311
5312         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5313
5314         stream->output_color_space = get_output_color_space(timing_out);
5315
5316         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5317         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5318         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5319                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5320                     drm_mode_is_420_also(info, mode_in) &&
5321                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5322                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5323                         adjust_colour_depth_from_display_info(timing_out, info);
5324                 }
5325         }
5326 }
5327
5328 static void fill_audio_info(struct audio_info *audio_info,
5329                             const struct drm_connector *drm_connector,
5330                             const struct dc_sink *dc_sink)
5331 {
5332         int i = 0;
5333         int cea_revision = 0;
5334         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5335
5336         audio_info->manufacture_id = edid_caps->manufacturer_id;
5337         audio_info->product_id = edid_caps->product_id;
5338
5339         cea_revision = drm_connector->display_info.cea_rev;
5340
5341         strscpy(audio_info->display_name,
5342                 edid_caps->display_name,
5343                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5344
5345         if (cea_revision >= 3) {
5346                 audio_info->mode_count = edid_caps->audio_mode_count;
5347
5348                 for (i = 0; i < audio_info->mode_count; ++i) {
5349                         audio_info->modes[i].format_code =
5350                                         (enum audio_format_code)
5351                                         (edid_caps->audio_modes[i].format_code);
5352                         audio_info->modes[i].channel_count =
5353                                         edid_caps->audio_modes[i].channel_count;
5354                         audio_info->modes[i].sample_rates.all =
5355                                         edid_caps->audio_modes[i].sample_rate;
5356                         audio_info->modes[i].sample_size =
5357                                         edid_caps->audio_modes[i].sample_size;
5358                 }
5359         }
5360
5361         audio_info->flags.all = edid_caps->speaker_flags;
5362
5363         /* TODO: We only check for the progressive mode, check for interlace mode too */
5364         if (drm_connector->latency_present[0]) {
5365                 audio_info->video_latency = drm_connector->video_latency[0];
5366                 audio_info->audio_latency = drm_connector->audio_latency[0];
5367         }
5368
5369         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5370
5371 }
5372
5373 static void
5374 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5375                                       struct drm_display_mode *dst_mode)
5376 {
5377         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5378         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5379         dst_mode->crtc_clock = src_mode->crtc_clock;
5380         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5381         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5382         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5383         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5384         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5385         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5386         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5387         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5388         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5389         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5390         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5391 }
5392
5393 static void
5394 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5395                                         const struct drm_display_mode *native_mode,
5396                                         bool scale_enabled)
5397 {
5398         if (scale_enabled) {
5399                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5400         } else if (native_mode->clock == drm_mode->clock &&
5401                         native_mode->htotal == drm_mode->htotal &&
5402                         native_mode->vtotal == drm_mode->vtotal) {
5403                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5404         } else {
5405                 /* no scaling nor amdgpu inserted, no need to patch */
5406         }
5407 }
5408
5409 static struct dc_sink *
5410 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5411 {
5412         struct dc_sink_init_data sink_init_data = { 0 };
5413         struct dc_sink *sink = NULL;
5414         sink_init_data.link = aconnector->dc_link;
5415         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5416
5417         sink = dc_sink_create(&sink_init_data);
5418         if (!sink) {
5419                 DRM_ERROR("Failed to create sink!\n");
5420                 return NULL;
5421         }
5422         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5423
5424         return sink;
5425 }
5426
5427 static void set_multisync_trigger_params(
5428                 struct dc_stream_state *stream)
5429 {
5430         struct dc_stream_state *master = NULL;
5431
5432         if (stream->triggered_crtc_reset.enabled) {
5433                 master = stream->triggered_crtc_reset.event_source;
5434                 stream->triggered_crtc_reset.event =
5435                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5436                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5437                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5438         }
5439 }
5440
5441 static void set_master_stream(struct dc_stream_state *stream_set[],
5442                               int stream_count)
5443 {
5444         int j, highest_rfr = 0, master_stream = 0;
5445
5446         for (j = 0;  j < stream_count; j++) {
5447                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5448                         int refresh_rate = 0;
5449
5450                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5451                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5452                         if (refresh_rate > highest_rfr) {
5453                                 highest_rfr = refresh_rate;
5454                                 master_stream = j;
5455                         }
5456                 }
5457         }
5458         for (j = 0;  j < stream_count; j++) {
5459                 if (stream_set[j])
5460                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5461         }
5462 }
5463
5464 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5465 {
5466         int i = 0;
5467         struct dc_stream_state *stream;
5468
5469         if (context->stream_count < 2)
5470                 return;
5471         for (i = 0; i < context->stream_count ; i++) {
5472                 if (!context->streams[i])
5473                         continue;
5474                 /*
5475                  * TODO: add a function to read AMD VSDB bits and set
5476                  * crtc_sync_master.multi_sync_enabled flag
5477                  * For now it's set to false
5478                  */
5479         }
5480
5481         set_master_stream(context->streams, context->stream_count);
5482
5483         for (i = 0; i < context->stream_count ; i++) {
5484                 stream = context->streams[i];
5485
5486                 if (!stream)
5487                         continue;
5488
5489                 set_multisync_trigger_params(stream);
5490         }
5491 }
5492
5493 /**
5494  * DOC: FreeSync Video
5495  *
5496  * When a userspace application wants to play a video, the content follows a
5497  * standard format definition that usually specifies the FPS for that format.
5498  * The below list illustrates some video format and the expected FPS,
5499  * respectively:
5500  *
5501  * - TV/NTSC (23.976 FPS)
5502  * - Cinema (24 FPS)
5503  * - TV/PAL (25 FPS)
5504  * - TV/NTSC (29.97 FPS)
5505  * - TV/NTSC (30 FPS)
5506  * - Cinema HFR (48 FPS)
5507  * - TV/PAL (50 FPS)
5508  * - Commonly used (60 FPS)
5509  * - Multiples of 24 (48,72,96 FPS)
5510  *
5511  * The list of standards video format is not huge and can be added to the
5512  * connector modeset list beforehand. With that, userspace can leverage
5513  * FreeSync to extends the front porch in order to attain the target refresh
5514  * rate. Such a switch will happen seamlessly, without screen blanking or
5515  * reprogramming of the output in any other way. If the userspace requests a
5516  * modesetting change compatible with FreeSync modes that only differ in the
5517  * refresh rate, DC will skip the full update and avoid blink during the
5518  * transition. For example, the video player can change the modesetting from
5519  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5520  * causing any display blink. This same concept can be applied to a mode
5521  * setting change.
5522  */
5523 static struct drm_display_mode *
5524 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5525                 bool use_probed_modes)
5526 {
5527         struct drm_display_mode *m, *m_pref = NULL;
5528         u16 current_refresh, highest_refresh;
5529         struct list_head *list_head = use_probed_modes ?
5530                 &aconnector->base.probed_modes :
5531                 &aconnector->base.modes;
5532
5533         if (aconnector->freesync_vid_base.clock != 0)
5534                 return &aconnector->freesync_vid_base;
5535
5536         /* Find the preferred mode */
5537         list_for_each_entry (m, list_head, head) {
5538                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5539                         m_pref = m;
5540                         break;
5541                 }
5542         }
5543
5544         if (!m_pref) {
5545                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5546                 m_pref = list_first_entry_or_null(
5547                                 &aconnector->base.modes, struct drm_display_mode, head);
5548                 if (!m_pref) {
5549                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5550                         return NULL;
5551                 }
5552         }
5553
5554         highest_refresh = drm_mode_vrefresh(m_pref);
5555
5556         /*
5557          * Find the mode with highest refresh rate with same resolution.
5558          * For some monitors, preferred mode is not the mode with highest
5559          * supported refresh rate.
5560          */
5561         list_for_each_entry (m, list_head, head) {
5562                 current_refresh  = drm_mode_vrefresh(m);
5563
5564                 if (m->hdisplay == m_pref->hdisplay &&
5565                     m->vdisplay == m_pref->vdisplay &&
5566                     highest_refresh < current_refresh) {
5567                         highest_refresh = current_refresh;
5568                         m_pref = m;
5569                 }
5570         }
5571
5572         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5573         return m_pref;
5574 }
5575
5576 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5577                 struct amdgpu_dm_connector *aconnector)
5578 {
5579         struct drm_display_mode *high_mode;
5580         int timing_diff;
5581
5582         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5583         if (!high_mode || !mode)
5584                 return false;
5585
5586         timing_diff = high_mode->vtotal - mode->vtotal;
5587
5588         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5589             high_mode->hdisplay != mode->hdisplay ||
5590             high_mode->vdisplay != mode->vdisplay ||
5591             high_mode->hsync_start != mode->hsync_start ||
5592             high_mode->hsync_end != mode->hsync_end ||
5593             high_mode->htotal != mode->htotal ||
5594             high_mode->hskew != mode->hskew ||
5595             high_mode->vscan != mode->vscan ||
5596             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5597             high_mode->vsync_end - mode->vsync_end != timing_diff)
5598                 return false;
5599         else
5600                 return true;
5601 }
5602
5603 #if defined(CONFIG_DRM_AMD_DC_DCN)
5604 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5605                             struct dc_sink *sink, struct dc_stream_state *stream,
5606                             struct dsc_dec_dpcd_caps *dsc_caps)
5607 {
5608         stream->timing.flags.DSC = 0;
5609         dsc_caps->is_dsc_supported = false;
5610
5611         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5612             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5613                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5614                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5615                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5616                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5617                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5618                                 dsc_caps);
5619         }
5620 }
5621
5622
5623 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5624                                     struct dc_sink *sink, struct dc_stream_state *stream,
5625                                     struct dsc_dec_dpcd_caps *dsc_caps,
5626                                     uint32_t max_dsc_target_bpp_limit_override)
5627 {
5628         const struct dc_link_settings *verified_link_cap = NULL;
5629         uint32_t link_bw_in_kbps;
5630         uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
5631         struct dc *dc = sink->ctx->dc;
5632         struct dc_dsc_bw_range bw_range = {0};
5633         struct dc_dsc_config dsc_cfg = {0};
5634
5635         verified_link_cap = dc_link_get_link_cap(stream->link);
5636         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5637         edp_min_bpp_x16 = 8 * 16;
5638         edp_max_bpp_x16 = 8 * 16;
5639
5640         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5641                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5642
5643         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5644                 edp_min_bpp_x16 = edp_max_bpp_x16;
5645
5646         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5647                                 dc->debug.dsc_min_slice_height_override,
5648                                 edp_min_bpp_x16, edp_max_bpp_x16,
5649                                 dsc_caps,
5650                                 &stream->timing,
5651                                 &bw_range)) {
5652
5653                 if (bw_range.max_kbps < link_bw_in_kbps) {
5654                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5655                                         dsc_caps,
5656                                         dc->debug.dsc_min_slice_height_override,
5657                                         max_dsc_target_bpp_limit_override,
5658                                         0,
5659                                         &stream->timing,
5660                                         &dsc_cfg)) {
5661                                 stream->timing.dsc_cfg = dsc_cfg;
5662                                 stream->timing.flags.DSC = 1;
5663                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5664                         }
5665                         return;
5666                 }
5667         }
5668
5669         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5670                                 dsc_caps,
5671                                 dc->debug.dsc_min_slice_height_override,
5672                                 max_dsc_target_bpp_limit_override,
5673                                 link_bw_in_kbps,
5674                                 &stream->timing,
5675                                 &dsc_cfg)) {
5676                 stream->timing.dsc_cfg = dsc_cfg;
5677                 stream->timing.flags.DSC = 1;
5678         }
5679 }
5680
5681
5682 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5683                                         struct dc_sink *sink, struct dc_stream_state *stream,
5684                                         struct dsc_dec_dpcd_caps *dsc_caps)
5685 {
5686         struct drm_connector *drm_connector = &aconnector->base;
5687         uint32_t link_bandwidth_kbps;
5688         struct dc *dc = sink->ctx->dc;
5689         uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
5690         uint32_t dsc_max_supported_bw_in_kbps;
5691         uint32_t max_dsc_target_bpp_limit_override =
5692                 drm_connector->display_info.max_dsc_bpp;
5693
5694         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5695                                                         dc_link_get_link_cap(aconnector->dc_link));
5696
5697         /* Set DSC policy according to dsc_clock_en */
5698         dc_dsc_policy_set_enable_dsc_when_not_needed(
5699                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5700
5701         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5702             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5703             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5704
5705                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5706
5707         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5708                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5709                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5710                                                 dsc_caps,
5711                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5712                                                 max_dsc_target_bpp_limit_override,
5713                                                 link_bandwidth_kbps,
5714                                                 &stream->timing,
5715                                                 &stream->timing.dsc_cfg)) {
5716                                 stream->timing.flags.DSC = 1;
5717                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5718                         }
5719                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5720                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5721                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5722                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5723
5724                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5725                                         max_supported_bw_in_kbps > 0 &&
5726                                         dsc_max_supported_bw_in_kbps > 0)
5727                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5728                                                 dsc_caps,
5729                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5730                                                 max_dsc_target_bpp_limit_override,
5731                                                 dsc_max_supported_bw_in_kbps,
5732                                                 &stream->timing,
5733                                                 &stream->timing.dsc_cfg)) {
5734                                         stream->timing.flags.DSC = 1;
5735                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5736                                                                          __func__, drm_connector->name);
5737                                 }
5738                 }
5739         }
5740
5741         /* Overwrite the stream flag if DSC is enabled through debugfs */
5742         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5743                 stream->timing.flags.DSC = 1;
5744
5745         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5746                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5747
5748         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5749                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5750
5751         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5752                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5753 }
5754 #endif /* CONFIG_DRM_AMD_DC_DCN */
5755
5756 static struct dc_stream_state *
5757 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5758                        const struct drm_display_mode *drm_mode,
5759                        const struct dm_connector_state *dm_state,
5760                        const struct dc_stream_state *old_stream,
5761                        int requested_bpc)
5762 {
5763         struct drm_display_mode *preferred_mode = NULL;
5764         struct drm_connector *drm_connector;
5765         const struct drm_connector_state *con_state =
5766                 dm_state ? &dm_state->base : NULL;
5767         struct dc_stream_state *stream = NULL;
5768         struct drm_display_mode mode;
5769         struct drm_display_mode saved_mode;
5770         struct drm_display_mode *freesync_mode = NULL;
5771         bool native_mode_found = false;
5772         bool recalculate_timing = false;
5773         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5774         int mode_refresh;
5775         int preferred_refresh = 0;
5776         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5777 #if defined(CONFIG_DRM_AMD_DC_DCN)
5778         struct dsc_dec_dpcd_caps dsc_caps;
5779 #endif
5780
5781         struct dc_sink *sink = NULL;
5782
5783         drm_mode_init(&mode, drm_mode);
5784         memset(&saved_mode, 0, sizeof(saved_mode));
5785
5786         if (aconnector == NULL) {
5787                 DRM_ERROR("aconnector is NULL!\n");
5788                 return stream;
5789         }
5790
5791         drm_connector = &aconnector->base;
5792
5793         if (!aconnector->dc_sink) {
5794                 sink = create_fake_sink(aconnector);
5795                 if (!sink)
5796                         return stream;
5797         } else {
5798                 sink = aconnector->dc_sink;
5799                 dc_sink_retain(sink);
5800         }
5801
5802         stream = dc_create_stream_for_sink(sink);
5803
5804         if (stream == NULL) {
5805                 DRM_ERROR("Failed to create stream for sink!\n");
5806                 goto finish;
5807         }
5808
5809         stream->dm_stream_context = aconnector;
5810
5811         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5812                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5813
5814         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5815                 /* Search for preferred mode */
5816                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5817                         native_mode_found = true;
5818                         break;
5819                 }
5820         }
5821         if (!native_mode_found)
5822                 preferred_mode = list_first_entry_or_null(
5823                                 &aconnector->base.modes,
5824                                 struct drm_display_mode,
5825                                 head);
5826
5827         mode_refresh = drm_mode_vrefresh(&mode);
5828
5829         if (preferred_mode == NULL) {
5830                 /*
5831                  * This may not be an error, the use case is when we have no
5832                  * usermode calls to reset and set mode upon hotplug. In this
5833                  * case, we call set mode ourselves to restore the previous mode
5834                  * and the modelist may not be filled in in time.
5835                  */
5836                 DRM_DEBUG_DRIVER("No preferred mode found\n");
5837         } else {
5838                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
5839                 if (recalculate_timing) {
5840                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5841                         drm_mode_copy(&saved_mode, &mode);
5842                         drm_mode_copy(&mode, freesync_mode);
5843                 } else {
5844                         decide_crtc_timing_for_drm_display_mode(
5845                                         &mode, preferred_mode, scale);
5846
5847                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
5848                 }
5849         }
5850
5851         if (recalculate_timing)
5852                 drm_mode_set_crtcinfo(&saved_mode, 0);
5853         else if (!dm_state)
5854                 drm_mode_set_crtcinfo(&mode, 0);
5855
5856         /*
5857         * If scaling is enabled and refresh rate didn't change
5858         * we copy the vic and polarities of the old timings
5859         */
5860         if (!scale || mode_refresh != preferred_refresh)
5861                 fill_stream_properties_from_drm_display_mode(
5862                         stream, &mode, &aconnector->base, con_state, NULL,
5863                         requested_bpc);
5864         else
5865                 fill_stream_properties_from_drm_display_mode(
5866                         stream, &mode, &aconnector->base, con_state, old_stream,
5867                         requested_bpc);
5868
5869 #if defined(CONFIG_DRM_AMD_DC_DCN)
5870         /* SST DSC determination policy */
5871         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5872         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5873                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
5874 #endif
5875
5876         update_stream_scaling_settings(&mode, dm_state, stream);
5877
5878         fill_audio_info(
5879                 &stream->audio_info,
5880                 drm_connector,
5881                 sink);
5882
5883         update_stream_signal(stream, sink);
5884
5885         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5886                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5887
5888         if (stream->link->psr_settings.psr_feature_enabled) {
5889                 //
5890                 // should decide stream support vsc sdp colorimetry capability
5891                 // before building vsc info packet
5892                 //
5893                 stream->use_vsc_sdp_for_colorimetry = false;
5894                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5895                         stream->use_vsc_sdp_for_colorimetry =
5896                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5897                 } else {
5898                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5899                                 stream->use_vsc_sdp_for_colorimetry = true;
5900                 }
5901                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
5902                         tf = TRANSFER_FUNC_GAMMA_22;
5903                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
5904                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5905
5906         }
5907 finish:
5908         dc_sink_release(sink);
5909
5910         return stream;
5911 }
5912
5913 static enum drm_connector_status
5914 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5915 {
5916         bool connected;
5917         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5918
5919         /*
5920          * Notes:
5921          * 1. This interface is NOT called in context of HPD irq.
5922          * 2. This interface *is called* in context of user-mode ioctl. Which
5923          * makes it a bad place for *any* MST-related activity.
5924          */
5925
5926         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5927             !aconnector->fake_enable)
5928                 connected = (aconnector->dc_sink != NULL);
5929         else
5930                 connected = (aconnector->base.force == DRM_FORCE_ON ||
5931                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
5932
5933         update_subconnector_property(aconnector);
5934
5935         return (connected ? connector_status_connected :
5936                         connector_status_disconnected);
5937 }
5938
5939 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5940                                             struct drm_connector_state *connector_state,
5941                                             struct drm_property *property,
5942                                             uint64_t val)
5943 {
5944         struct drm_device *dev = connector->dev;
5945         struct amdgpu_device *adev = drm_to_adev(dev);
5946         struct dm_connector_state *dm_old_state =
5947                 to_dm_connector_state(connector->state);
5948         struct dm_connector_state *dm_new_state =
5949                 to_dm_connector_state(connector_state);
5950
5951         int ret = -EINVAL;
5952
5953         if (property == dev->mode_config.scaling_mode_property) {
5954                 enum amdgpu_rmx_type rmx_type;
5955
5956                 switch (val) {
5957                 case DRM_MODE_SCALE_CENTER:
5958                         rmx_type = RMX_CENTER;
5959                         break;
5960                 case DRM_MODE_SCALE_ASPECT:
5961                         rmx_type = RMX_ASPECT;
5962                         break;
5963                 case DRM_MODE_SCALE_FULLSCREEN:
5964                         rmx_type = RMX_FULL;
5965                         break;
5966                 case DRM_MODE_SCALE_NONE:
5967                 default:
5968                         rmx_type = RMX_OFF;
5969                         break;
5970                 }
5971
5972                 if (dm_old_state->scaling == rmx_type)
5973                         return 0;
5974
5975                 dm_new_state->scaling = rmx_type;
5976                 ret = 0;
5977         } else if (property == adev->mode_info.underscan_hborder_property) {
5978                 dm_new_state->underscan_hborder = val;
5979                 ret = 0;
5980         } else if (property == adev->mode_info.underscan_vborder_property) {
5981                 dm_new_state->underscan_vborder = val;
5982                 ret = 0;
5983         } else if (property == adev->mode_info.underscan_property) {
5984                 dm_new_state->underscan_enable = val;
5985                 ret = 0;
5986         } else if (property == adev->mode_info.abm_level_property) {
5987                 dm_new_state->abm_level = val;
5988                 ret = 0;
5989         }
5990
5991         return ret;
5992 }
5993
5994 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5995                                             const struct drm_connector_state *state,
5996                                             struct drm_property *property,
5997                                             uint64_t *val)
5998 {
5999         struct drm_device *dev = connector->dev;
6000         struct amdgpu_device *adev = drm_to_adev(dev);
6001         struct dm_connector_state *dm_state =
6002                 to_dm_connector_state(state);
6003         int ret = -EINVAL;
6004
6005         if (property == dev->mode_config.scaling_mode_property) {
6006                 switch (dm_state->scaling) {
6007                 case RMX_CENTER:
6008                         *val = DRM_MODE_SCALE_CENTER;
6009                         break;
6010                 case RMX_ASPECT:
6011                         *val = DRM_MODE_SCALE_ASPECT;
6012                         break;
6013                 case RMX_FULL:
6014                         *val = DRM_MODE_SCALE_FULLSCREEN;
6015                         break;
6016                 case RMX_OFF:
6017                 default:
6018                         *val = DRM_MODE_SCALE_NONE;
6019                         break;
6020                 }
6021                 ret = 0;
6022         } else if (property == adev->mode_info.underscan_hborder_property) {
6023                 *val = dm_state->underscan_hborder;
6024                 ret = 0;
6025         } else if (property == adev->mode_info.underscan_vborder_property) {
6026                 *val = dm_state->underscan_vborder;
6027                 ret = 0;
6028         } else if (property == adev->mode_info.underscan_property) {
6029                 *val = dm_state->underscan_enable;
6030                 ret = 0;
6031         } else if (property == adev->mode_info.abm_level_property) {
6032                 *val = dm_state->abm_level;
6033                 ret = 0;
6034         }
6035
6036         return ret;
6037 }
6038
6039 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6040 {
6041         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6042
6043         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6044 }
6045
6046 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6047 {
6048         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6049         const struct dc_link *link = aconnector->dc_link;
6050         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6051         struct amdgpu_display_manager *dm = &adev->dm;
6052         int i;
6053
6054         /*
6055          * Call only if mst_mgr was initialized before since it's not done
6056          * for all connector types.
6057          */
6058         if (aconnector->mst_mgr.dev)
6059                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6060
6061 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
6062         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
6063         for (i = 0; i < dm->num_of_edps; i++) {
6064                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6065                         backlight_device_unregister(dm->backlight_dev[i]);
6066                         dm->backlight_dev[i] = NULL;
6067                 }
6068         }
6069 #endif
6070
6071         if (aconnector->dc_em_sink)
6072                 dc_sink_release(aconnector->dc_em_sink);
6073         aconnector->dc_em_sink = NULL;
6074         if (aconnector->dc_sink)
6075                 dc_sink_release(aconnector->dc_sink);
6076         aconnector->dc_sink = NULL;
6077
6078         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6079         drm_connector_unregister(connector);
6080         drm_connector_cleanup(connector);
6081         if (aconnector->i2c) {
6082                 i2c_del_adapter(&aconnector->i2c->base);
6083                 kfree(aconnector->i2c);
6084         }
6085         kfree(aconnector->dm_dp_aux.aux.name);
6086
6087         kfree(connector);
6088 }
6089
6090 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6091 {
6092         struct dm_connector_state *state =
6093                 to_dm_connector_state(connector->state);
6094
6095         if (connector->state)
6096                 __drm_atomic_helper_connector_destroy_state(connector->state);
6097
6098         kfree(state);
6099
6100         state = kzalloc(sizeof(*state), GFP_KERNEL);
6101
6102         if (state) {
6103                 state->scaling = RMX_OFF;
6104                 state->underscan_enable = false;
6105                 state->underscan_hborder = 0;
6106                 state->underscan_vborder = 0;
6107                 state->base.max_requested_bpc = 8;
6108                 state->vcpi_slots = 0;
6109                 state->pbn = 0;
6110
6111                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6112                         state->abm_level = amdgpu_dm_abm_level;
6113
6114                 __drm_atomic_helper_connector_reset(connector, &state->base);
6115         }
6116 }
6117
6118 struct drm_connector_state *
6119 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6120 {
6121         struct dm_connector_state *state =
6122                 to_dm_connector_state(connector->state);
6123
6124         struct dm_connector_state *new_state =
6125                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6126
6127         if (!new_state)
6128                 return NULL;
6129
6130         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6131
6132         new_state->freesync_capable = state->freesync_capable;
6133         new_state->abm_level = state->abm_level;
6134         new_state->scaling = state->scaling;
6135         new_state->underscan_enable = state->underscan_enable;
6136         new_state->underscan_hborder = state->underscan_hborder;
6137         new_state->underscan_vborder = state->underscan_vborder;
6138         new_state->vcpi_slots = state->vcpi_slots;
6139         new_state->pbn = state->pbn;
6140         return &new_state->base;
6141 }
6142
6143 static int
6144 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6145 {
6146         struct amdgpu_dm_connector *amdgpu_dm_connector =
6147                 to_amdgpu_dm_connector(connector);
6148         int r;
6149
6150         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6151             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6152                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6153                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6154                 if (r)
6155                         return r;
6156         }
6157
6158 #if defined(CONFIG_DEBUG_FS)
6159         connector_debugfs_init(amdgpu_dm_connector);
6160 #endif
6161
6162         return 0;
6163 }
6164
6165 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6166         .reset = amdgpu_dm_connector_funcs_reset,
6167         .detect = amdgpu_dm_connector_detect,
6168         .fill_modes = drm_helper_probe_single_connector_modes,
6169         .destroy = amdgpu_dm_connector_destroy,
6170         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6171         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6172         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6173         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6174         .late_register = amdgpu_dm_connector_late_register,
6175         .early_unregister = amdgpu_dm_connector_unregister
6176 };
6177
6178 static int get_modes(struct drm_connector *connector)
6179 {
6180         return amdgpu_dm_connector_get_modes(connector);
6181 }
6182
6183 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6184 {
6185         struct dc_sink_init_data init_params = {
6186                         .link = aconnector->dc_link,
6187                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6188         };
6189         struct edid *edid;
6190
6191         if (!aconnector->base.edid_blob_ptr) {
6192                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6193                                 aconnector->base.name);
6194
6195                 aconnector->base.force = DRM_FORCE_OFF;
6196                 return;
6197         }
6198
6199         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6200
6201         aconnector->edid = edid;
6202
6203         aconnector->dc_em_sink = dc_link_add_remote_sink(
6204                 aconnector->dc_link,
6205                 (uint8_t *)edid,
6206                 (edid->extensions + 1) * EDID_LENGTH,
6207                 &init_params);
6208
6209         if (aconnector->base.force == DRM_FORCE_ON) {
6210                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6211                 aconnector->dc_link->local_sink :
6212                 aconnector->dc_em_sink;
6213                 dc_sink_retain(aconnector->dc_sink);
6214         }
6215 }
6216
6217 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6218 {
6219         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6220
6221         /*
6222          * In case of headless boot with force on for DP managed connector
6223          * Those settings have to be != 0 to get initial modeset
6224          */
6225         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6226                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6227                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6228         }
6229
6230         create_eml_sink(aconnector);
6231 }
6232
6233 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6234                                                 struct dc_stream_state *stream)
6235 {
6236         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6237         struct dc_plane_state *dc_plane_state = NULL;
6238         struct dc_state *dc_state = NULL;
6239
6240         if (!stream)
6241                 goto cleanup;
6242
6243         dc_plane_state = dc_create_plane_state(dc);
6244         if (!dc_plane_state)
6245                 goto cleanup;
6246
6247         dc_state = dc_create_state(dc);
6248         if (!dc_state)
6249                 goto cleanup;
6250
6251         /* populate stream to plane */
6252         dc_plane_state->src_rect.height  = stream->src.height;
6253         dc_plane_state->src_rect.width   = stream->src.width;
6254         dc_plane_state->dst_rect.height  = stream->src.height;
6255         dc_plane_state->dst_rect.width   = stream->src.width;
6256         dc_plane_state->clip_rect.height = stream->src.height;
6257         dc_plane_state->clip_rect.width  = stream->src.width;
6258         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6259         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6260         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6261         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6262         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6263         dc_plane_state->tiling_info.gfx9.swizzle =  DC_SW_UNKNOWN;
6264         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6265         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6266         dc_plane_state->rotation = ROTATION_ANGLE_0;
6267         dc_plane_state->is_tiling_rotated = false;
6268         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6269
6270         dc_result = dc_validate_stream(dc, stream);
6271         if (dc_result == DC_OK)
6272                 dc_result = dc_validate_plane(dc, dc_plane_state);
6273
6274         if (dc_result == DC_OK)
6275                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6276
6277         if (dc_result == DC_OK && !dc_add_plane_to_context(
6278                                                 dc,
6279                                                 stream,
6280                                                 dc_plane_state,
6281                                                 dc_state))
6282                 dc_result = DC_FAIL_ATTACH_SURFACES;
6283
6284         if (dc_result == DC_OK)
6285                 dc_result = dc_validate_global_state(dc, dc_state, true);
6286
6287 cleanup:
6288         if (dc_state)
6289                 dc_release_state(dc_state);
6290
6291         if (dc_plane_state)
6292                 dc_plane_state_release(dc_plane_state);
6293
6294         return dc_result;
6295 }
6296
6297 struct dc_stream_state *
6298 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6299                                 const struct drm_display_mode *drm_mode,
6300                                 const struct dm_connector_state *dm_state,
6301                                 const struct dc_stream_state *old_stream)
6302 {
6303         struct drm_connector *connector = &aconnector->base;
6304         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6305         struct dc_stream_state *stream;
6306         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6307         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6308         enum dc_status dc_result = DC_OK;
6309
6310         do {
6311                 stream = create_stream_for_sink(aconnector, drm_mode,
6312                                                 dm_state, old_stream,
6313                                                 requested_bpc);
6314                 if (stream == NULL) {
6315                         DRM_ERROR("Failed to create stream for sink!\n");
6316                         break;
6317                 }
6318
6319                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6320                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6321                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6322
6323                 if (dc_result == DC_OK)
6324                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6325
6326                 if (dc_result != DC_OK) {
6327                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6328                                       drm_mode->hdisplay,
6329                                       drm_mode->vdisplay,
6330                                       drm_mode->clock,
6331                                       dc_result,
6332                                       dc_status_to_str(dc_result));
6333
6334                         dc_stream_release(stream);
6335                         stream = NULL;
6336                         requested_bpc -= 2; /* lower bpc to retry validation */
6337                 }
6338
6339         } while (stream == NULL && requested_bpc >= 6);
6340
6341         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6342                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6343
6344                 aconnector->force_yuv420_output = true;
6345                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6346                                                 dm_state, old_stream);
6347                 aconnector->force_yuv420_output = false;
6348         }
6349
6350         return stream;
6351 }
6352
6353 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6354                                    struct drm_display_mode *mode)
6355 {
6356         int result = MODE_ERROR;
6357         struct dc_sink *dc_sink;
6358         /* TODO: Unhardcode stream count */
6359         struct dc_stream_state *stream;
6360         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6361
6362         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6363                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6364                 return result;
6365
6366         /*
6367          * Only run this the first time mode_valid is called to initilialize
6368          * EDID mgmt
6369          */
6370         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6371                 !aconnector->dc_em_sink)
6372                 handle_edid_mgmt(aconnector);
6373
6374         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6375
6376         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6377                                 aconnector->base.force != DRM_FORCE_ON) {
6378                 DRM_ERROR("dc_sink is NULL!\n");
6379                 goto fail;
6380         }
6381
6382         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6383         if (stream) {
6384                 dc_stream_release(stream);
6385                 result = MODE_OK;
6386         }
6387
6388 fail:
6389         /* TODO: error handling*/
6390         return result;
6391 }
6392
6393 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6394                                 struct dc_info_packet *out)
6395 {
6396         struct hdmi_drm_infoframe frame;
6397         unsigned char buf[30]; /* 26 + 4 */
6398         ssize_t len;
6399         int ret, i;
6400
6401         memset(out, 0, sizeof(*out));
6402
6403         if (!state->hdr_output_metadata)
6404                 return 0;
6405
6406         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6407         if (ret)
6408                 return ret;
6409
6410         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6411         if (len < 0)
6412                 return (int)len;
6413
6414         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6415         if (len != 30)
6416                 return -EINVAL;
6417
6418         /* Prepare the infopacket for DC. */
6419         switch (state->connector->connector_type) {
6420         case DRM_MODE_CONNECTOR_HDMIA:
6421                 out->hb0 = 0x87; /* type */
6422                 out->hb1 = 0x01; /* version */
6423                 out->hb2 = 0x1A; /* length */
6424                 out->sb[0] = buf[3]; /* checksum */
6425                 i = 1;
6426                 break;
6427
6428         case DRM_MODE_CONNECTOR_DisplayPort:
6429         case DRM_MODE_CONNECTOR_eDP:
6430                 out->hb0 = 0x00; /* sdp id, zero */
6431                 out->hb1 = 0x87; /* type */
6432                 out->hb2 = 0x1D; /* payload len - 1 */
6433                 out->hb3 = (0x13 << 2); /* sdp version */
6434                 out->sb[0] = 0x01; /* version */
6435                 out->sb[1] = 0x1A; /* length */
6436                 i = 2;
6437                 break;
6438
6439         default:
6440                 return -EINVAL;
6441         }
6442
6443         memcpy(&out->sb[i], &buf[4], 26);
6444         out->valid = true;
6445
6446         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6447                        sizeof(out->sb), false);
6448
6449         return 0;
6450 }
6451
6452 static int
6453 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6454                                  struct drm_atomic_state *state)
6455 {
6456         struct drm_connector_state *new_con_state =
6457                 drm_atomic_get_new_connector_state(state, conn);
6458         struct drm_connector_state *old_con_state =
6459                 drm_atomic_get_old_connector_state(state, conn);
6460         struct drm_crtc *crtc = new_con_state->crtc;
6461         struct drm_crtc_state *new_crtc_state;
6462         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6463         int ret;
6464
6465         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6466
6467         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6468                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6469                 if (ret < 0)
6470                         return ret;
6471         }
6472
6473         if (!crtc)
6474                 return 0;
6475
6476         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6477                 struct dc_info_packet hdr_infopacket;
6478
6479                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6480                 if (ret)
6481                         return ret;
6482
6483                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6484                 if (IS_ERR(new_crtc_state))
6485                         return PTR_ERR(new_crtc_state);
6486
6487                 /*
6488                  * DC considers the stream backends changed if the
6489                  * static metadata changes. Forcing the modeset also
6490                  * gives a simple way for userspace to switch from
6491                  * 8bpc to 10bpc when setting the metadata to enter
6492                  * or exit HDR.
6493                  *
6494                  * Changing the static metadata after it's been
6495                  * set is permissible, however. So only force a
6496                  * modeset if we're entering or exiting HDR.
6497                  */
6498                 new_crtc_state->mode_changed =
6499                         !old_con_state->hdr_output_metadata ||
6500                         !new_con_state->hdr_output_metadata;
6501         }
6502
6503         return 0;
6504 }
6505
6506 static const struct drm_connector_helper_funcs
6507 amdgpu_dm_connector_helper_funcs = {
6508         /*
6509          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6510          * modes will be filtered by drm_mode_validate_size(), and those modes
6511          * are missing after user start lightdm. So we need to renew modes list.
6512          * in get_modes call back, not just return the modes count
6513          */
6514         .get_modes = get_modes,
6515         .mode_valid = amdgpu_dm_connector_mode_valid,
6516         .atomic_check = amdgpu_dm_connector_atomic_check,
6517 };
6518
6519 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6520 {
6521
6522 }
6523
6524 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6525 {
6526         switch (display_color_depth) {
6527         case COLOR_DEPTH_666:
6528                 return 6;
6529         case COLOR_DEPTH_888:
6530                 return 8;
6531         case COLOR_DEPTH_101010:
6532                 return 10;
6533         case COLOR_DEPTH_121212:
6534                 return 12;
6535         case COLOR_DEPTH_141414:
6536                 return 14;
6537         case COLOR_DEPTH_161616:
6538                 return 16;
6539         default:
6540                 break;
6541         }
6542         return 0;
6543 }
6544
6545 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6546                                           struct drm_crtc_state *crtc_state,
6547                                           struct drm_connector_state *conn_state)
6548 {
6549         struct drm_atomic_state *state = crtc_state->state;
6550         struct drm_connector *connector = conn_state->connector;
6551         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6552         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6553         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6554         struct drm_dp_mst_topology_mgr *mst_mgr;
6555         struct drm_dp_mst_port *mst_port;
6556         struct drm_dp_mst_topology_state *mst_state;
6557         enum dc_color_depth color_depth;
6558         int clock, bpp = 0;
6559         bool is_y420 = false;
6560
6561         if (!aconnector->port || !aconnector->dc_sink)
6562                 return 0;
6563
6564         mst_port = aconnector->port;
6565         mst_mgr = &aconnector->mst_port->mst_mgr;
6566
6567         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6568                 return 0;
6569
6570         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6571         if (IS_ERR(mst_state))
6572                 return PTR_ERR(mst_state);
6573
6574         if (!mst_state->pbn_div)
6575                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
6576
6577         if (!state->duplicated) {
6578                 int max_bpc = conn_state->max_requested_bpc;
6579                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6580                           aconnector->force_yuv420_output;
6581                 color_depth = convert_color_depth_from_display_info(connector,
6582                                                                     is_y420,
6583                                                                     max_bpc);
6584                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6585                 clock = adjusted_mode->clock;
6586                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6587         }
6588
6589         dm_new_connector_state->vcpi_slots =
6590                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6591                                               dm_new_connector_state->pbn);
6592         if (dm_new_connector_state->vcpi_slots < 0) {
6593                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6594                 return dm_new_connector_state->vcpi_slots;
6595         }
6596         return 0;
6597 }
6598
6599 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6600         .disable = dm_encoder_helper_disable,
6601         .atomic_check = dm_encoder_helper_atomic_check
6602 };
6603
6604 #if defined(CONFIG_DRM_AMD_DC_DCN)
6605 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6606                                             struct dc_state *dc_state,
6607                                             struct dsc_mst_fairness_vars *vars)
6608 {
6609         struct dc_stream_state *stream = NULL;
6610         struct drm_connector *connector;
6611         struct drm_connector_state *new_con_state;
6612         struct amdgpu_dm_connector *aconnector;
6613         struct dm_connector_state *dm_conn_state;
6614         int i, j, ret;
6615         int vcpi, pbn_div, pbn, slot_num = 0;
6616
6617         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6618
6619                 aconnector = to_amdgpu_dm_connector(connector);
6620
6621                 if (!aconnector->port)
6622                         continue;
6623
6624                 if (!new_con_state || !new_con_state->crtc)
6625                         continue;
6626
6627                 dm_conn_state = to_dm_connector_state(new_con_state);
6628
6629                 for (j = 0; j < dc_state->stream_count; j++) {
6630                         stream = dc_state->streams[j];
6631                         if (!stream)
6632                                 continue;
6633
6634                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6635                                 break;
6636
6637                         stream = NULL;
6638                 }
6639
6640                 if (!stream)
6641                         continue;
6642
6643                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6644                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6645                 for (j = 0; j < dc_state->stream_count; j++) {
6646                         if (vars[j].aconnector == aconnector) {
6647                                 pbn = vars[j].pbn;
6648                                 break;
6649                         }
6650                 }
6651
6652                 if (j == dc_state->stream_count)
6653                         continue;
6654
6655                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6656
6657                 if (stream->timing.flags.DSC != 1) {
6658                         dm_conn_state->pbn = pbn;
6659                         dm_conn_state->vcpi_slots = slot_num;
6660
6661                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->port,
6662                                                            dm_conn_state->pbn, false);
6663                         if (ret < 0)
6664                                 return ret;
6665
6666                         continue;
6667                 }
6668
6669                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
6670                 if (vcpi < 0)
6671                         return vcpi;
6672
6673                 dm_conn_state->pbn = pbn;
6674                 dm_conn_state->vcpi_slots = vcpi;
6675         }
6676         return 0;
6677 }
6678 #endif
6679
6680 static int to_drm_connector_type(enum signal_type st)
6681 {
6682         switch (st) {
6683         case SIGNAL_TYPE_HDMI_TYPE_A:
6684                 return DRM_MODE_CONNECTOR_HDMIA;
6685         case SIGNAL_TYPE_EDP:
6686                 return DRM_MODE_CONNECTOR_eDP;
6687         case SIGNAL_TYPE_LVDS:
6688                 return DRM_MODE_CONNECTOR_LVDS;
6689         case SIGNAL_TYPE_RGB:
6690                 return DRM_MODE_CONNECTOR_VGA;
6691         case SIGNAL_TYPE_DISPLAY_PORT:
6692         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6693                 return DRM_MODE_CONNECTOR_DisplayPort;
6694         case SIGNAL_TYPE_DVI_DUAL_LINK:
6695         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6696                 return DRM_MODE_CONNECTOR_DVID;
6697         case SIGNAL_TYPE_VIRTUAL:
6698                 return DRM_MODE_CONNECTOR_VIRTUAL;
6699
6700         default:
6701                 return DRM_MODE_CONNECTOR_Unknown;
6702         }
6703 }
6704
6705 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6706 {
6707         struct drm_encoder *encoder;
6708
6709         /* There is only one encoder per connector */
6710         drm_connector_for_each_possible_encoder(connector, encoder)
6711                 return encoder;
6712
6713         return NULL;
6714 }
6715
6716 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6717 {
6718         struct drm_encoder *encoder;
6719         struct amdgpu_encoder *amdgpu_encoder;
6720
6721         encoder = amdgpu_dm_connector_to_encoder(connector);
6722
6723         if (encoder == NULL)
6724                 return;
6725
6726         amdgpu_encoder = to_amdgpu_encoder(encoder);
6727
6728         amdgpu_encoder->native_mode.clock = 0;
6729
6730         if (!list_empty(&connector->probed_modes)) {
6731                 struct drm_display_mode *preferred_mode = NULL;
6732
6733                 list_for_each_entry(preferred_mode,
6734                                     &connector->probed_modes,
6735                                     head) {
6736                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6737                                 amdgpu_encoder->native_mode = *preferred_mode;
6738
6739                         break;
6740                 }
6741
6742         }
6743 }
6744
6745 static struct drm_display_mode *
6746 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6747                              char *name,
6748                              int hdisplay, int vdisplay)
6749 {
6750         struct drm_device *dev = encoder->dev;
6751         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6752         struct drm_display_mode *mode = NULL;
6753         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6754
6755         mode = drm_mode_duplicate(dev, native_mode);
6756
6757         if (mode == NULL)
6758                 return NULL;
6759
6760         mode->hdisplay = hdisplay;
6761         mode->vdisplay = vdisplay;
6762         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6763         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6764
6765         return mode;
6766
6767 }
6768
6769 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6770                                                  struct drm_connector *connector)
6771 {
6772         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6773         struct drm_display_mode *mode = NULL;
6774         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6775         struct amdgpu_dm_connector *amdgpu_dm_connector =
6776                                 to_amdgpu_dm_connector(connector);
6777         int i;
6778         int n;
6779         struct mode_size {
6780                 char name[DRM_DISPLAY_MODE_LEN];
6781                 int w;
6782                 int h;
6783         } common_modes[] = {
6784                 {  "640x480",  640,  480},
6785                 {  "800x600",  800,  600},
6786                 { "1024x768", 1024,  768},
6787                 { "1280x720", 1280,  720},
6788                 { "1280x800", 1280,  800},
6789                 {"1280x1024", 1280, 1024},
6790                 { "1440x900", 1440,  900},
6791                 {"1680x1050", 1680, 1050},
6792                 {"1600x1200", 1600, 1200},
6793                 {"1920x1080", 1920, 1080},
6794                 {"1920x1200", 1920, 1200}
6795         };
6796
6797         n = ARRAY_SIZE(common_modes);
6798
6799         for (i = 0; i < n; i++) {
6800                 struct drm_display_mode *curmode = NULL;
6801                 bool mode_existed = false;
6802
6803                 if (common_modes[i].w > native_mode->hdisplay ||
6804                     common_modes[i].h > native_mode->vdisplay ||
6805                    (common_modes[i].w == native_mode->hdisplay &&
6806                     common_modes[i].h == native_mode->vdisplay))
6807                         continue;
6808
6809                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6810                         if (common_modes[i].w == curmode->hdisplay &&
6811                             common_modes[i].h == curmode->vdisplay) {
6812                                 mode_existed = true;
6813                                 break;
6814                         }
6815                 }
6816
6817                 if (mode_existed)
6818                         continue;
6819
6820                 mode = amdgpu_dm_create_common_mode(encoder,
6821                                 common_modes[i].name, common_modes[i].w,
6822                                 common_modes[i].h);
6823                 if (!mode)
6824                         continue;
6825
6826                 drm_mode_probed_add(connector, mode);
6827                 amdgpu_dm_connector->num_modes++;
6828         }
6829 }
6830
6831 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6832 {
6833         struct drm_encoder *encoder;
6834         struct amdgpu_encoder *amdgpu_encoder;
6835         const struct drm_display_mode *native_mode;
6836
6837         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6838             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6839                 return;
6840
6841         mutex_lock(&connector->dev->mode_config.mutex);
6842         amdgpu_dm_connector_get_modes(connector);
6843         mutex_unlock(&connector->dev->mode_config.mutex);
6844
6845         encoder = amdgpu_dm_connector_to_encoder(connector);
6846         if (!encoder)
6847                 return;
6848
6849         amdgpu_encoder = to_amdgpu_encoder(encoder);
6850
6851         native_mode = &amdgpu_encoder->native_mode;
6852         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6853                 return;
6854
6855         drm_connector_set_panel_orientation_with_quirk(connector,
6856                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6857                                                        native_mode->hdisplay,
6858                                                        native_mode->vdisplay);
6859 }
6860
6861 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6862                                               struct edid *edid)
6863 {
6864         struct amdgpu_dm_connector *amdgpu_dm_connector =
6865                         to_amdgpu_dm_connector(connector);
6866
6867         if (edid) {
6868                 /* empty probed_modes */
6869                 INIT_LIST_HEAD(&connector->probed_modes);
6870                 amdgpu_dm_connector->num_modes =
6871                                 drm_add_edid_modes(connector, edid);
6872
6873                 /* sorting the probed modes before calling function
6874                  * amdgpu_dm_get_native_mode() since EDID can have
6875                  * more than one preferred mode. The modes that are
6876                  * later in the probed mode list could be of higher
6877                  * and preferred resolution. For example, 3840x2160
6878                  * resolution in base EDID preferred timing and 4096x2160
6879                  * preferred resolution in DID extension block later.
6880                  */
6881                 drm_mode_sort(&connector->probed_modes);
6882                 amdgpu_dm_get_native_mode(connector);
6883
6884                 /* Freesync capabilities are reset by calling
6885                  * drm_add_edid_modes() and need to be
6886                  * restored here.
6887                  */
6888                 amdgpu_dm_update_freesync_caps(connector, edid);
6889         } else {
6890                 amdgpu_dm_connector->num_modes = 0;
6891         }
6892 }
6893
6894 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6895                               struct drm_display_mode *mode)
6896 {
6897         struct drm_display_mode *m;
6898
6899         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6900                 if (drm_mode_equal(m, mode))
6901                         return true;
6902         }
6903
6904         return false;
6905 }
6906
6907 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6908 {
6909         const struct drm_display_mode *m;
6910         struct drm_display_mode *new_mode;
6911         uint i;
6912         uint32_t new_modes_count = 0;
6913
6914         /* Standard FPS values
6915          *
6916          * 23.976       - TV/NTSC
6917          * 24           - Cinema
6918          * 25           - TV/PAL
6919          * 29.97        - TV/NTSC
6920          * 30           - TV/NTSC
6921          * 48           - Cinema HFR
6922          * 50           - TV/PAL
6923          * 60           - Commonly used
6924          * 48,72,96,120 - Multiples of 24
6925          */
6926         static const uint32_t common_rates[] = {
6927                 23976, 24000, 25000, 29970, 30000,
6928                 48000, 50000, 60000, 72000, 96000, 120000
6929         };
6930
6931         /*
6932          * Find mode with highest refresh rate with the same resolution
6933          * as the preferred mode. Some monitors report a preferred mode
6934          * with lower resolution than the highest refresh rate supported.
6935          */
6936
6937         m = get_highest_refresh_rate_mode(aconnector, true);
6938         if (!m)
6939                 return 0;
6940
6941         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
6942                 uint64_t target_vtotal, target_vtotal_diff;
6943                 uint64_t num, den;
6944
6945                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
6946                         continue;
6947
6948                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
6949                     common_rates[i] > aconnector->max_vfreq * 1000)
6950                         continue;
6951
6952                 num = (unsigned long long)m->clock * 1000 * 1000;
6953                 den = common_rates[i] * (unsigned long long)m->htotal;
6954                 target_vtotal = div_u64(num, den);
6955                 target_vtotal_diff = target_vtotal - m->vtotal;
6956
6957                 /* Check for illegal modes */
6958                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
6959                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
6960                     m->vtotal + target_vtotal_diff < m->vsync_end)
6961                         continue;
6962
6963                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
6964                 if (!new_mode)
6965                         goto out;
6966
6967                 new_mode->vtotal += (u16)target_vtotal_diff;
6968                 new_mode->vsync_start += (u16)target_vtotal_diff;
6969                 new_mode->vsync_end += (u16)target_vtotal_diff;
6970                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6971                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
6972
6973                 if (!is_duplicate_mode(aconnector, new_mode)) {
6974                         drm_mode_probed_add(&aconnector->base, new_mode);
6975                         new_modes_count += 1;
6976                 } else
6977                         drm_mode_destroy(aconnector->base.dev, new_mode);
6978         }
6979  out:
6980         return new_modes_count;
6981 }
6982
6983 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
6984                                                    struct edid *edid)
6985 {
6986         struct amdgpu_dm_connector *amdgpu_dm_connector =
6987                 to_amdgpu_dm_connector(connector);
6988
6989         if (!edid)
6990                 return;
6991
6992         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
6993                 amdgpu_dm_connector->num_modes +=
6994                         add_fs_modes(amdgpu_dm_connector);
6995 }
6996
6997 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6998 {
6999         struct amdgpu_dm_connector *amdgpu_dm_connector =
7000                         to_amdgpu_dm_connector(connector);
7001         struct drm_encoder *encoder;
7002         struct edid *edid = amdgpu_dm_connector->edid;
7003
7004         encoder = amdgpu_dm_connector_to_encoder(connector);
7005
7006         if (!drm_edid_is_valid(edid)) {
7007                 amdgpu_dm_connector->num_modes =
7008                                 drm_add_modes_noedid(connector, 640, 480);
7009         } else {
7010                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7011                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7012                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7013         }
7014         amdgpu_dm_fbc_init(connector);
7015
7016         return amdgpu_dm_connector->num_modes;
7017 }
7018
7019 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7020                                      struct amdgpu_dm_connector *aconnector,
7021                                      int connector_type,
7022                                      struct dc_link *link,
7023                                      int link_index)
7024 {
7025         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7026
7027         /*
7028          * Some of the properties below require access to state, like bpc.
7029          * Allocate some default initial connector state with our reset helper.
7030          */
7031         if (aconnector->base.funcs->reset)
7032                 aconnector->base.funcs->reset(&aconnector->base);
7033
7034         aconnector->connector_id = link_index;
7035         aconnector->dc_link = link;
7036         aconnector->base.interlace_allowed = false;
7037         aconnector->base.doublescan_allowed = false;
7038         aconnector->base.stereo_allowed = false;
7039         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7040         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7041         aconnector->audio_inst = -1;
7042         mutex_init(&aconnector->hpd_lock);
7043
7044         /*
7045          * configure support HPD hot plug connector_>polled default value is 0
7046          * which means HPD hot plug not supported
7047          */
7048         switch (connector_type) {
7049         case DRM_MODE_CONNECTOR_HDMIA:
7050                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7051                 aconnector->base.ycbcr_420_allowed =
7052                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7053                 break;
7054         case DRM_MODE_CONNECTOR_DisplayPort:
7055                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7056                 link->link_enc = link_enc_cfg_get_link_enc(link);
7057                 ASSERT(link->link_enc);
7058                 if (link->link_enc)
7059                         aconnector->base.ycbcr_420_allowed =
7060                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7061                 break;
7062         case DRM_MODE_CONNECTOR_DVID:
7063                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7064                 break;
7065         default:
7066                 break;
7067         }
7068
7069         drm_object_attach_property(&aconnector->base.base,
7070                                 dm->ddev->mode_config.scaling_mode_property,
7071                                 DRM_MODE_SCALE_NONE);
7072
7073         drm_object_attach_property(&aconnector->base.base,
7074                                 adev->mode_info.underscan_property,
7075                                 UNDERSCAN_OFF);
7076         drm_object_attach_property(&aconnector->base.base,
7077                                 adev->mode_info.underscan_hborder_property,
7078                                 0);
7079         drm_object_attach_property(&aconnector->base.base,
7080                                 adev->mode_info.underscan_vborder_property,
7081                                 0);
7082
7083         if (!aconnector->mst_port)
7084                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7085
7086         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7087         aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7088         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7089
7090         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7091             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7092                 drm_object_attach_property(&aconnector->base.base,
7093                                 adev->mode_info.abm_level_property, 0);
7094         }
7095
7096         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7097             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7098             connector_type == DRM_MODE_CONNECTOR_eDP) {
7099                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7100
7101                 if (!aconnector->mst_port)
7102                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7103
7104 #ifdef CONFIG_DRM_AMD_DC_HDCP
7105                 if (adev->dm.hdcp_workqueue)
7106                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7107 #endif
7108         }
7109 }
7110
7111 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7112                               struct i2c_msg *msgs, int num)
7113 {
7114         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7115         struct ddc_service *ddc_service = i2c->ddc_service;
7116         struct i2c_command cmd;
7117         int i;
7118         int result = -EIO;
7119
7120         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7121
7122         if (!cmd.payloads)
7123                 return result;
7124
7125         cmd.number_of_payloads = num;
7126         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7127         cmd.speed = 100;
7128
7129         for (i = 0; i < num; i++) {
7130                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7131                 cmd.payloads[i].address = msgs[i].addr;
7132                 cmd.payloads[i].length = msgs[i].len;
7133                 cmd.payloads[i].data = msgs[i].buf;
7134         }
7135
7136         if (dc_submit_i2c(
7137                         ddc_service->ctx->dc,
7138                         ddc_service->link->link_index,
7139                         &cmd))
7140                 result = num;
7141
7142         kfree(cmd.payloads);
7143         return result;
7144 }
7145
7146 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7147 {
7148         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7149 }
7150
7151 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7152         .master_xfer = amdgpu_dm_i2c_xfer,
7153         .functionality = amdgpu_dm_i2c_func,
7154 };
7155
7156 static struct amdgpu_i2c_adapter *
7157 create_i2c(struct ddc_service *ddc_service,
7158            int link_index,
7159            int *res)
7160 {
7161         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7162         struct amdgpu_i2c_adapter *i2c;
7163
7164         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7165         if (!i2c)
7166                 return NULL;
7167         i2c->base.owner = THIS_MODULE;
7168         i2c->base.class = I2C_CLASS_DDC;
7169         i2c->base.dev.parent = &adev->pdev->dev;
7170         i2c->base.algo = &amdgpu_dm_i2c_algo;
7171         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7172         i2c_set_adapdata(&i2c->base, i2c);
7173         i2c->ddc_service = ddc_service;
7174
7175         return i2c;
7176 }
7177
7178
7179 /*
7180  * Note: this function assumes that dc_link_detect() was called for the
7181  * dc_link which will be represented by this aconnector.
7182  */
7183 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7184                                     struct amdgpu_dm_connector *aconnector,
7185                                     uint32_t link_index,
7186                                     struct amdgpu_encoder *aencoder)
7187 {
7188         int res = 0;
7189         int connector_type;
7190         struct dc *dc = dm->dc;
7191         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7192         struct amdgpu_i2c_adapter *i2c;
7193
7194         link->priv = aconnector;
7195
7196         DRM_DEBUG_DRIVER("%s()\n", __func__);
7197
7198         i2c = create_i2c(link->ddc, link->link_index, &res);
7199         if (!i2c) {
7200                 DRM_ERROR("Failed to create i2c adapter data\n");
7201                 return -ENOMEM;
7202         }
7203
7204         aconnector->i2c = i2c;
7205         res = i2c_add_adapter(&i2c->base);
7206
7207         if (res) {
7208                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7209                 goto out_free;
7210         }
7211
7212         connector_type = to_drm_connector_type(link->connector_signal);
7213
7214         res = drm_connector_init_with_ddc(
7215                         dm->ddev,
7216                         &aconnector->base,
7217                         &amdgpu_dm_connector_funcs,
7218                         connector_type,
7219                         &i2c->base);
7220
7221         if (res) {
7222                 DRM_ERROR("connector_init failed\n");
7223                 aconnector->connector_id = -1;
7224                 goto out_free;
7225         }
7226
7227         drm_connector_helper_add(
7228                         &aconnector->base,
7229                         &amdgpu_dm_connector_helper_funcs);
7230
7231         amdgpu_dm_connector_init_helper(
7232                 dm,
7233                 aconnector,
7234                 connector_type,
7235                 link,
7236                 link_index);
7237
7238         drm_connector_attach_encoder(
7239                 &aconnector->base, &aencoder->base);
7240
7241         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7242                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7243                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7244
7245 out_free:
7246         if (res) {
7247                 kfree(i2c);
7248                 aconnector->i2c = NULL;
7249         }
7250         return res;
7251 }
7252
7253 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7254 {
7255         switch (adev->mode_info.num_crtc) {
7256         case 1:
7257                 return 0x1;
7258         case 2:
7259                 return 0x3;
7260         case 3:
7261                 return 0x7;
7262         case 4:
7263                 return 0xf;
7264         case 5:
7265                 return 0x1f;
7266         case 6:
7267         default:
7268                 return 0x3f;
7269         }
7270 }
7271
7272 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7273                                   struct amdgpu_encoder *aencoder,
7274                                   uint32_t link_index)
7275 {
7276         struct amdgpu_device *adev = drm_to_adev(dev);
7277
7278         int res = drm_encoder_init(dev,
7279                                    &aencoder->base,
7280                                    &amdgpu_dm_encoder_funcs,
7281                                    DRM_MODE_ENCODER_TMDS,
7282                                    NULL);
7283
7284         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7285
7286         if (!res)
7287                 aencoder->encoder_id = link_index;
7288         else
7289                 aencoder->encoder_id = -1;
7290
7291         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7292
7293         return res;
7294 }
7295
7296 static void manage_dm_interrupts(struct amdgpu_device *adev,
7297                                  struct amdgpu_crtc *acrtc,
7298                                  bool enable)
7299 {
7300         /*
7301          * We have no guarantee that the frontend index maps to the same
7302          * backend index - some even map to more than one.
7303          *
7304          * TODO: Use a different interrupt or check DC itself for the mapping.
7305          */
7306         int irq_type =
7307                 amdgpu_display_crtc_idx_to_irq_type(
7308                         adev,
7309                         acrtc->crtc_id);
7310
7311         if (enable) {
7312                 drm_crtc_vblank_on(&acrtc->base);
7313                 amdgpu_irq_get(
7314                         adev,
7315                         &adev->pageflip_irq,
7316                         irq_type);
7317 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7318                 amdgpu_irq_get(
7319                         adev,
7320                         &adev->vline0_irq,
7321                         irq_type);
7322 #endif
7323         } else {
7324 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7325                 amdgpu_irq_put(
7326                         adev,
7327                         &adev->vline0_irq,
7328                         irq_type);
7329 #endif
7330                 amdgpu_irq_put(
7331                         adev,
7332                         &adev->pageflip_irq,
7333                         irq_type);
7334                 drm_crtc_vblank_off(&acrtc->base);
7335         }
7336 }
7337
7338 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7339                                       struct amdgpu_crtc *acrtc)
7340 {
7341         int irq_type =
7342                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7343
7344         /**
7345          * This reads the current state for the IRQ and force reapplies
7346          * the setting to hardware.
7347          */
7348         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7349 }
7350
7351 static bool
7352 is_scaling_state_different(const struct dm_connector_state *dm_state,
7353                            const struct dm_connector_state *old_dm_state)
7354 {
7355         if (dm_state->scaling != old_dm_state->scaling)
7356                 return true;
7357         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7358                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7359                         return true;
7360         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7361                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7362                         return true;
7363         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7364                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7365                 return true;
7366         return false;
7367 }
7368
7369 #ifdef CONFIG_DRM_AMD_DC_HDCP
7370 static bool is_content_protection_different(struct drm_connector_state *state,
7371                                             const struct drm_connector_state *old_state,
7372                                             const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7373 {
7374         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7375         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7376
7377         /* Handle: Type0/1 change */
7378         if (old_state->hdcp_content_type != state->hdcp_content_type &&
7379             state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7380                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7381                 return true;
7382         }
7383
7384         /* CP is being re enabled, ignore this
7385          *
7386          * Handles:     ENABLED -> DESIRED
7387          */
7388         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7389             state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7390                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7391                 return false;
7392         }
7393
7394         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7395          *
7396          * Handles:     UNDESIRED -> ENABLED
7397          */
7398         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7399             state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7400                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7401
7402         /* Stream removed and re-enabled
7403          *
7404          * Can sometimes overlap with the HPD case,
7405          * thus set update_hdcp to false to avoid
7406          * setting HDCP multiple times.
7407          *
7408          * Handles:     DESIRED -> DESIRED (Special case)
7409          */
7410         if (!(old_state->crtc && old_state->crtc->enabled) &&
7411                 state->crtc && state->crtc->enabled &&
7412                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7413                 dm_con_state->update_hdcp = false;
7414                 return true;
7415         }
7416
7417         /* Hot-plug, headless s3, dpms
7418          *
7419          * Only start HDCP if the display is connected/enabled.
7420          * update_hdcp flag will be set to false until the next
7421          * HPD comes in.
7422          *
7423          * Handles:     DESIRED -> DESIRED (Special case)
7424          */
7425         if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7426             connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7427                 dm_con_state->update_hdcp = false;
7428                 return true;
7429         }
7430
7431         /*
7432          * Handles:     UNDESIRED -> UNDESIRED
7433          *              DESIRED -> DESIRED
7434          *              ENABLED -> ENABLED
7435          */
7436         if (old_state->content_protection == state->content_protection)
7437                 return false;
7438
7439         /*
7440          * Handles:     UNDESIRED -> DESIRED
7441          *              DESIRED -> UNDESIRED
7442          *              ENABLED -> UNDESIRED
7443          */
7444         if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7445                 return true;
7446
7447         /*
7448          * Handles:     DESIRED -> ENABLED
7449          */
7450         return false;
7451 }
7452
7453 #endif
7454 static void remove_stream(struct amdgpu_device *adev,
7455                           struct amdgpu_crtc *acrtc,
7456                           struct dc_stream_state *stream)
7457 {
7458         /* this is the update mode case */
7459
7460         acrtc->otg_inst = -1;
7461         acrtc->enabled = false;
7462 }
7463
7464 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7465 {
7466
7467         assert_spin_locked(&acrtc->base.dev->event_lock);
7468         WARN_ON(acrtc->event);
7469
7470         acrtc->event = acrtc->base.state->event;
7471
7472         /* Set the flip status */
7473         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7474
7475         /* Mark this event as consumed */
7476         acrtc->base.state->event = NULL;
7477
7478         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7479                      acrtc->crtc_id);
7480 }
7481
7482 static void update_freesync_state_on_stream(
7483         struct amdgpu_display_manager *dm,
7484         struct dm_crtc_state *new_crtc_state,
7485         struct dc_stream_state *new_stream,
7486         struct dc_plane_state *surface,
7487         u32 flip_timestamp_in_us)
7488 {
7489         struct mod_vrr_params vrr_params;
7490         struct dc_info_packet vrr_infopacket = {0};
7491         struct amdgpu_device *adev = dm->adev;
7492         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7493         unsigned long flags;
7494         bool pack_sdp_v1_3 = false;
7495
7496         if (!new_stream)
7497                 return;
7498
7499         /*
7500          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7501          * For now it's sufficient to just guard against these conditions.
7502          */
7503
7504         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7505                 return;
7506
7507         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7508         vrr_params = acrtc->dm_irq_params.vrr_params;
7509
7510         if (surface) {
7511                 mod_freesync_handle_preflip(
7512                         dm->freesync_module,
7513                         surface,
7514                         new_stream,
7515                         flip_timestamp_in_us,
7516                         &vrr_params);
7517
7518                 if (adev->family < AMDGPU_FAMILY_AI &&
7519                     amdgpu_dm_vrr_active(new_crtc_state)) {
7520                         mod_freesync_handle_v_update(dm->freesync_module,
7521                                                      new_stream, &vrr_params);
7522
7523                         /* Need to call this before the frame ends. */
7524                         dc_stream_adjust_vmin_vmax(dm->dc,
7525                                                    new_crtc_state->stream,
7526                                                    &vrr_params.adjust);
7527                 }
7528         }
7529
7530         mod_freesync_build_vrr_infopacket(
7531                 dm->freesync_module,
7532                 new_stream,
7533                 &vrr_params,
7534                 PACKET_TYPE_VRR,
7535                 TRANSFER_FUNC_UNKNOWN,
7536                 &vrr_infopacket,
7537                 pack_sdp_v1_3);
7538
7539         new_crtc_state->freesync_vrr_info_changed |=
7540                 (memcmp(&new_crtc_state->vrr_infopacket,
7541                         &vrr_infopacket,
7542                         sizeof(vrr_infopacket)) != 0);
7543
7544         acrtc->dm_irq_params.vrr_params = vrr_params;
7545         new_crtc_state->vrr_infopacket = vrr_infopacket;
7546
7547         new_stream->vrr_infopacket = vrr_infopacket;
7548
7549         if (new_crtc_state->freesync_vrr_info_changed)
7550                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7551                               new_crtc_state->base.crtc->base.id,
7552                               (int)new_crtc_state->base.vrr_enabled,
7553                               (int)vrr_params.state);
7554
7555         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7556 }
7557
7558 static void update_stream_irq_parameters(
7559         struct amdgpu_display_manager *dm,
7560         struct dm_crtc_state *new_crtc_state)
7561 {
7562         struct dc_stream_state *new_stream = new_crtc_state->stream;
7563         struct mod_vrr_params vrr_params;
7564         struct mod_freesync_config config = new_crtc_state->freesync_config;
7565         struct amdgpu_device *adev = dm->adev;
7566         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7567         unsigned long flags;
7568
7569         if (!new_stream)
7570                 return;
7571
7572         /*
7573          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7574          * For now it's sufficient to just guard against these conditions.
7575          */
7576         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7577                 return;
7578
7579         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7580         vrr_params = acrtc->dm_irq_params.vrr_params;
7581
7582         if (new_crtc_state->vrr_supported &&
7583             config.min_refresh_in_uhz &&
7584             config.max_refresh_in_uhz) {
7585                 /*
7586                  * if freesync compatible mode was set, config.state will be set
7587                  * in atomic check
7588                  */
7589                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7590                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7591                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7592                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7593                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7594                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7595                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7596                 } else {
7597                         config.state = new_crtc_state->base.vrr_enabled ?
7598                                                      VRR_STATE_ACTIVE_VARIABLE :
7599                                                      VRR_STATE_INACTIVE;
7600                 }
7601         } else {
7602                 config.state = VRR_STATE_UNSUPPORTED;
7603         }
7604
7605         mod_freesync_build_vrr_params(dm->freesync_module,
7606                                       new_stream,
7607                                       &config, &vrr_params);
7608
7609         new_crtc_state->freesync_config = config;
7610         /* Copy state for access from DM IRQ handler */
7611         acrtc->dm_irq_params.freesync_config = config;
7612         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7613         acrtc->dm_irq_params.vrr_params = vrr_params;
7614         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7615 }
7616
7617 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7618                                             struct dm_crtc_state *new_state)
7619 {
7620         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7621         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7622
7623         if (!old_vrr_active && new_vrr_active) {
7624                 /* Transition VRR inactive -> active:
7625                  * While VRR is active, we must not disable vblank irq, as a
7626                  * reenable after disable would compute bogus vblank/pflip
7627                  * timestamps if it likely happened inside display front-porch.
7628                  *
7629                  * We also need vupdate irq for the actual core vblank handling
7630                  * at end of vblank.
7631                  */
7632                 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
7633                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7634                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7635                                  __func__, new_state->base.crtc->base.id);
7636         } else if (old_vrr_active && !new_vrr_active) {
7637                 /* Transition VRR active -> inactive:
7638                  * Allow vblank irq disable again for fixed refresh rate.
7639                  */
7640                 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
7641                 drm_crtc_vblank_put(new_state->base.crtc);
7642                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7643                                  __func__, new_state->base.crtc->base.id);
7644         }
7645 }
7646
7647 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7648 {
7649         struct drm_plane *plane;
7650         struct drm_plane_state *old_plane_state;
7651         int i;
7652
7653         /*
7654          * TODO: Make this per-stream so we don't issue redundant updates for
7655          * commits with multiple streams.
7656          */
7657         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7658                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7659                         handle_cursor_update(plane, old_plane_state);
7660 }
7661
7662 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7663                                     struct dc_state *dc_state,
7664                                     struct drm_device *dev,
7665                                     struct amdgpu_display_manager *dm,
7666                                     struct drm_crtc *pcrtc,
7667                                     bool wait_for_vblank)
7668 {
7669         uint32_t i;
7670         uint64_t timestamp_ns;
7671         struct drm_plane *plane;
7672         struct drm_plane_state *old_plane_state, *new_plane_state;
7673         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7674         struct drm_crtc_state *new_pcrtc_state =
7675                         drm_atomic_get_new_crtc_state(state, pcrtc);
7676         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7677         struct dm_crtc_state *dm_old_crtc_state =
7678                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7679         int planes_count = 0, vpos, hpos;
7680         unsigned long flags;
7681         uint32_t target_vblank, last_flip_vblank;
7682         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7683         bool cursor_update = false;
7684         bool pflip_present = false;
7685         struct {
7686                 struct dc_surface_update surface_updates[MAX_SURFACES];
7687                 struct dc_plane_info plane_infos[MAX_SURFACES];
7688                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7689                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7690                 struct dc_stream_update stream_update;
7691         } *bundle;
7692
7693         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7694
7695         if (!bundle) {
7696                 dm_error("Failed to allocate update bundle\n");
7697                 goto cleanup;
7698         }
7699
7700         /*
7701          * Disable the cursor first if we're disabling all the planes.
7702          * It'll remain on the screen after the planes are re-enabled
7703          * if we don't.
7704          */
7705         if (acrtc_state->active_planes == 0)
7706                 amdgpu_dm_commit_cursors(state);
7707
7708         /* update planes when needed */
7709         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7710                 struct drm_crtc *crtc = new_plane_state->crtc;
7711                 struct drm_crtc_state *new_crtc_state;
7712                 struct drm_framebuffer *fb = new_plane_state->fb;
7713                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7714                 bool plane_needs_flip;
7715                 struct dc_plane_state *dc_plane;
7716                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7717
7718                 /* Cursor plane is handled after stream updates */
7719                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7720                         if ((fb && crtc == pcrtc) ||
7721                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7722                                 cursor_update = true;
7723
7724                         continue;
7725                 }
7726
7727                 if (!fb || !crtc || pcrtc != crtc)
7728                         continue;
7729
7730                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7731                 if (!new_crtc_state->active)
7732                         continue;
7733
7734                 dc_plane = dm_new_plane_state->dc_state;
7735
7736                 bundle->surface_updates[planes_count].surface = dc_plane;
7737                 if (new_pcrtc_state->color_mgmt_changed) {
7738                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7739                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7740                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7741                 }
7742
7743                 fill_dc_scaling_info(dm->adev, new_plane_state,
7744                                      &bundle->scaling_infos[planes_count]);
7745
7746                 bundle->surface_updates[planes_count].scaling_info =
7747                         &bundle->scaling_infos[planes_count];
7748
7749                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7750
7751                 pflip_present = pflip_present || plane_needs_flip;
7752
7753                 if (!plane_needs_flip) {
7754                         planes_count += 1;
7755                         continue;
7756                 }
7757
7758                 fill_dc_plane_info_and_addr(
7759                         dm->adev, new_plane_state,
7760                         afb->tiling_flags,
7761                         &bundle->plane_infos[planes_count],
7762                         &bundle->flip_addrs[planes_count].address,
7763                         afb->tmz_surface, false);
7764
7765                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
7766                                  new_plane_state->plane->index,
7767                                  bundle->plane_infos[planes_count].dcc.enable);
7768
7769                 bundle->surface_updates[planes_count].plane_info =
7770                         &bundle->plane_infos[planes_count];
7771
7772                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7773                         fill_dc_dirty_rects(plane, old_plane_state,
7774                                             new_plane_state, new_crtc_state,
7775                                             &bundle->flip_addrs[planes_count]);
7776
7777                 /*
7778                  * Only allow immediate flips for fast updates that don't
7779                  * change FB pitch, DCC state, rotation or mirroing.
7780                  */
7781                 bundle->flip_addrs[planes_count].flip_immediate =
7782                         crtc->state->async_flip &&
7783                         acrtc_state->update_type == UPDATE_TYPE_FAST;
7784
7785                 timestamp_ns = ktime_get_ns();
7786                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7787                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7788                 bundle->surface_updates[planes_count].surface = dc_plane;
7789
7790                 if (!bundle->surface_updates[planes_count].surface) {
7791                         DRM_ERROR("No surface for CRTC: id=%d\n",
7792                                         acrtc_attach->crtc_id);
7793                         continue;
7794                 }
7795
7796                 if (plane == pcrtc->primary)
7797                         update_freesync_state_on_stream(
7798                                 dm,
7799                                 acrtc_state,
7800                                 acrtc_state->stream,
7801                                 dc_plane,
7802                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7803
7804                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
7805                                  __func__,
7806                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7807                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7808
7809                 planes_count += 1;
7810
7811         }
7812
7813         if (pflip_present) {
7814                 if (!vrr_active) {
7815                         /* Use old throttling in non-vrr fixed refresh rate mode
7816                          * to keep flip scheduling based on target vblank counts
7817                          * working in a backwards compatible way, e.g., for
7818                          * clients using the GLX_OML_sync_control extension or
7819                          * DRI3/Present extension with defined target_msc.
7820                          */
7821                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7822                 }
7823                 else {
7824                         /* For variable refresh rate mode only:
7825                          * Get vblank of last completed flip to avoid > 1 vrr
7826                          * flips per video frame by use of throttling, but allow
7827                          * flip programming anywhere in the possibly large
7828                          * variable vrr vblank interval for fine-grained flip
7829                          * timing control and more opportunity to avoid stutter
7830                          * on late submission of flips.
7831                          */
7832                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7833                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7834                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7835                 }
7836
7837                 target_vblank = last_flip_vblank + wait_for_vblank;
7838
7839                 /*
7840                  * Wait until we're out of the vertical blank period before the one
7841                  * targeted by the flip
7842                  */
7843                 while ((acrtc_attach->enabled &&
7844                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7845                                                             0, &vpos, &hpos, NULL,
7846                                                             NULL, &pcrtc->hwmode)
7847                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7848                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7849                         (int)(target_vblank -
7850                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7851                         usleep_range(1000, 1100);
7852                 }
7853
7854                 /**
7855                  * Prepare the flip event for the pageflip interrupt to handle.
7856                  *
7857                  * This only works in the case where we've already turned on the
7858                  * appropriate hardware blocks (eg. HUBP) so in the transition case
7859                  * from 0 -> n planes we have to skip a hardware generated event
7860                  * and rely on sending it from software.
7861                  */
7862                 if (acrtc_attach->base.state->event &&
7863                     acrtc_state->active_planes > 0) {
7864                         drm_crtc_vblank_get(pcrtc);
7865
7866                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7867
7868                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7869                         prepare_flip_isr(acrtc_attach);
7870
7871                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7872                 }
7873
7874                 if (acrtc_state->stream) {
7875                         if (acrtc_state->freesync_vrr_info_changed)
7876                                 bundle->stream_update.vrr_infopacket =
7877                                         &acrtc_state->stream->vrr_infopacket;
7878                 }
7879         } else if (cursor_update && acrtc_state->active_planes > 0 &&
7880                    acrtc_attach->base.state->event) {
7881                 drm_crtc_vblank_get(pcrtc);
7882
7883                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7884
7885                 acrtc_attach->event = acrtc_attach->base.state->event;
7886                 acrtc_attach->base.state->event = NULL;
7887
7888                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7889         }
7890
7891         /* Update the planes if changed or disable if we don't have any. */
7892         if ((planes_count || acrtc_state->active_planes == 0) &&
7893                 acrtc_state->stream) {
7894                 /*
7895                  * If PSR or idle optimizations are enabled then flush out
7896                  * any pending work before hardware programming.
7897                  */
7898                 if (dm->vblank_control_workqueue)
7899                         flush_workqueue(dm->vblank_control_workqueue);
7900
7901                 bundle->stream_update.stream = acrtc_state->stream;
7902                 if (new_pcrtc_state->mode_changed) {
7903                         bundle->stream_update.src = acrtc_state->stream->src;
7904                         bundle->stream_update.dst = acrtc_state->stream->dst;
7905                 }
7906
7907                 if (new_pcrtc_state->color_mgmt_changed) {
7908                         /*
7909                          * TODO: This isn't fully correct since we've actually
7910                          * already modified the stream in place.
7911                          */
7912                         bundle->stream_update.gamut_remap =
7913                                 &acrtc_state->stream->gamut_remap_matrix;
7914                         bundle->stream_update.output_csc_transform =
7915                                 &acrtc_state->stream->csc_color_matrix;
7916                         bundle->stream_update.out_transfer_func =
7917                                 acrtc_state->stream->out_transfer_func;
7918                 }
7919
7920                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
7921                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7922                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
7923
7924                 /*
7925                  * If FreeSync state on the stream has changed then we need to
7926                  * re-adjust the min/max bounds now that DC doesn't handle this
7927                  * as part of commit.
7928                  */
7929                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
7930                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7931                         dc_stream_adjust_vmin_vmax(
7932                                 dm->dc, acrtc_state->stream,
7933                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
7934                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7935                 }
7936                 mutex_lock(&dm->dc_lock);
7937                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7938                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
7939                         amdgpu_dm_psr_disable(acrtc_state->stream);
7940
7941                 dc_commit_updates_for_stream(dm->dc,
7942                                                      bundle->surface_updates,
7943                                                      planes_count,
7944                                                      acrtc_state->stream,
7945                                                      &bundle->stream_update,
7946                                                      dc_state);
7947
7948                 /**
7949                  * Enable or disable the interrupts on the backend.
7950                  *
7951                  * Most pipes are put into power gating when unused.
7952                  *
7953                  * When power gating is enabled on a pipe we lose the
7954                  * interrupt enablement state when power gating is disabled.
7955                  *
7956                  * So we need to update the IRQ control state in hardware
7957                  * whenever the pipe turns on (since it could be previously
7958                  * power gated) or off (since some pipes can't be power gated
7959                  * on some ASICs).
7960                  */
7961                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
7962                         dm_update_pflip_irq_state(drm_to_adev(dev),
7963                                                   acrtc_attach);
7964
7965                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7966                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
7967                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7968                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
7969
7970                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
7971                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
7972                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
7973                         struct amdgpu_dm_connector *aconn =
7974                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
7975
7976                         if (aconn->psr_skip_count > 0)
7977                                 aconn->psr_skip_count--;
7978
7979                         /* Allow PSR when skip count is 0. */
7980                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7981
7982                         /*
7983                          * If sink supports PSR SU, there is no need to rely on
7984                          * a vblank event disable request to enable PSR. PSR SU
7985                          * can be enabled immediately once OS demonstrates an
7986                          * adequate number of fast atomic commits to notify KMD
7987                          * of update events. See `vblank_control_worker()`.
7988                          */
7989                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
7990                             acrtc_attach->dm_irq_params.allow_psr_entry &&
7991 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
7992                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
7993 #endif
7994                             !acrtc_state->stream->link->psr_settings.psr_allow_active)
7995                                 amdgpu_dm_psr_enable(acrtc_state->stream);
7996                 } else {
7997                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
7998                 }
7999
8000                 mutex_unlock(&dm->dc_lock);
8001         }
8002
8003         /*
8004          * Update cursor state *after* programming all the planes.
8005          * This avoids redundant programming in the case where we're going
8006          * to be disabling a single plane - those pipes are being disabled.
8007          */
8008         if (acrtc_state->active_planes)
8009                 amdgpu_dm_commit_cursors(state);
8010
8011 cleanup:
8012         kfree(bundle);
8013 }
8014
8015 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8016                                    struct drm_atomic_state *state)
8017 {
8018         struct amdgpu_device *adev = drm_to_adev(dev);
8019         struct amdgpu_dm_connector *aconnector;
8020         struct drm_connector *connector;
8021         struct drm_connector_state *old_con_state, *new_con_state;
8022         struct drm_crtc_state *new_crtc_state;
8023         struct dm_crtc_state *new_dm_crtc_state;
8024         const struct dc_stream_status *status;
8025         int i, inst;
8026
8027         /* Notify device removals. */
8028         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8029                 if (old_con_state->crtc != new_con_state->crtc) {
8030                         /* CRTC changes require notification. */
8031                         goto notify;
8032                 }
8033
8034                 if (!new_con_state->crtc)
8035                         continue;
8036
8037                 new_crtc_state = drm_atomic_get_new_crtc_state(
8038                         state, new_con_state->crtc);
8039
8040                 if (!new_crtc_state)
8041                         continue;
8042
8043                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8044                         continue;
8045
8046         notify:
8047                 aconnector = to_amdgpu_dm_connector(connector);
8048
8049                 mutex_lock(&adev->dm.audio_lock);
8050                 inst = aconnector->audio_inst;
8051                 aconnector->audio_inst = -1;
8052                 mutex_unlock(&adev->dm.audio_lock);
8053
8054                 amdgpu_dm_audio_eld_notify(adev, inst);
8055         }
8056
8057         /* Notify audio device additions. */
8058         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8059                 if (!new_con_state->crtc)
8060                         continue;
8061
8062                 new_crtc_state = drm_atomic_get_new_crtc_state(
8063                         state, new_con_state->crtc);
8064
8065                 if (!new_crtc_state)
8066                         continue;
8067
8068                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8069                         continue;
8070
8071                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8072                 if (!new_dm_crtc_state->stream)
8073                         continue;
8074
8075                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8076                 if (!status)
8077                         continue;
8078
8079                 aconnector = to_amdgpu_dm_connector(connector);
8080
8081                 mutex_lock(&adev->dm.audio_lock);
8082                 inst = status->audio_inst;
8083                 aconnector->audio_inst = inst;
8084                 mutex_unlock(&adev->dm.audio_lock);
8085
8086                 amdgpu_dm_audio_eld_notify(adev, inst);
8087         }
8088 }
8089
8090 /*
8091  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8092  * @crtc_state: the DRM CRTC state
8093  * @stream_state: the DC stream state.
8094  *
8095  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8096  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8097  */
8098 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8099                                                 struct dc_stream_state *stream_state)
8100 {
8101         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8102 }
8103
8104 /**
8105  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8106  * @state: The atomic state to commit
8107  *
8108  * This will tell DC to commit the constructed DC state from atomic_check,
8109  * programming the hardware. Any failures here implies a hardware failure, since
8110  * atomic check should have filtered anything non-kosher.
8111  */
8112 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8113 {
8114         struct drm_device *dev = state->dev;
8115         struct amdgpu_device *adev = drm_to_adev(dev);
8116         struct amdgpu_display_manager *dm = &adev->dm;
8117         struct dm_atomic_state *dm_state;
8118         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8119         uint32_t i, j;
8120         struct drm_crtc *crtc;
8121         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8122         unsigned long flags;
8123         bool wait_for_vblank = true;
8124         struct drm_connector *connector;
8125         struct drm_connector_state *old_con_state, *new_con_state;
8126         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8127         int crtc_disable_count = 0;
8128         bool mode_set_reset_required = false;
8129         int r;
8130
8131         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8132
8133         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8134         if (unlikely(r))
8135                 DRM_ERROR("Waiting for fences timed out!");
8136
8137         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8138         drm_dp_mst_atomic_wait_for_dependencies(state);
8139
8140         dm_state = dm_atomic_get_new_state(state);
8141         if (dm_state && dm_state->context) {
8142                 dc_state = dm_state->context;
8143         } else {
8144                 /* No state changes, retain current state. */
8145                 dc_state_temp = dc_create_state(dm->dc);
8146                 ASSERT(dc_state_temp);
8147                 dc_state = dc_state_temp;
8148                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8149         }
8150
8151         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8152                                        new_crtc_state, i) {
8153                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8154
8155                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8156
8157                 if (old_crtc_state->active &&
8158                     (!new_crtc_state->active ||
8159                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8160                         manage_dm_interrupts(adev, acrtc, false);
8161                         dc_stream_release(dm_old_crtc_state->stream);
8162                 }
8163         }
8164
8165         drm_atomic_helper_calc_timestamping_constants(state);
8166
8167         /* update changed items */
8168         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8169                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8170
8171                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8172                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8173
8174                 drm_dbg_state(state->dev,
8175                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8176                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8177                         "connectors_changed:%d\n",
8178                         acrtc->crtc_id,
8179                         new_crtc_state->enable,
8180                         new_crtc_state->active,
8181                         new_crtc_state->planes_changed,
8182                         new_crtc_state->mode_changed,
8183                         new_crtc_state->active_changed,
8184                         new_crtc_state->connectors_changed);
8185
8186                 /* Disable cursor if disabling crtc */
8187                 if (old_crtc_state->active && !new_crtc_state->active) {
8188                         struct dc_cursor_position position;
8189
8190                         memset(&position, 0, sizeof(position));
8191                         mutex_lock(&dm->dc_lock);
8192                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8193                         mutex_unlock(&dm->dc_lock);
8194                 }
8195
8196                 /* Copy all transient state flags into dc state */
8197                 if (dm_new_crtc_state->stream) {
8198                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8199                                                             dm_new_crtc_state->stream);
8200                 }
8201
8202                 /* handles headless hotplug case, updating new_state and
8203                  * aconnector as needed
8204                  */
8205
8206                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8207
8208                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8209
8210                         if (!dm_new_crtc_state->stream) {
8211                                 /*
8212                                  * this could happen because of issues with
8213                                  * userspace notifications delivery.
8214                                  * In this case userspace tries to set mode on
8215                                  * display which is disconnected in fact.
8216                                  * dc_sink is NULL in this case on aconnector.
8217                                  * We expect reset mode will come soon.
8218                                  *
8219                                  * This can also happen when unplug is done
8220                                  * during resume sequence ended
8221                                  *
8222                                  * In this case, we want to pretend we still
8223                                  * have a sink to keep the pipe running so that
8224                                  * hw state is consistent with the sw state
8225                                  */
8226                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8227                                                 __func__, acrtc->base.base.id);
8228                                 continue;
8229                         }
8230
8231                         if (dm_old_crtc_state->stream)
8232                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8233
8234                         pm_runtime_get_noresume(dev->dev);
8235
8236                         acrtc->enabled = true;
8237                         acrtc->hw_mode = new_crtc_state->mode;
8238                         crtc->hwmode = new_crtc_state->mode;
8239                         mode_set_reset_required = true;
8240                 } else if (modereset_required(new_crtc_state)) {
8241                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8242                         /* i.e. reset mode */
8243                         if (dm_old_crtc_state->stream)
8244                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8245
8246                         mode_set_reset_required = true;
8247                 }
8248         } /* for_each_crtc_in_state() */
8249
8250         if (dc_state) {
8251                 /* if there mode set or reset, disable eDP PSR */
8252                 if (mode_set_reset_required) {
8253                         if (dm->vblank_control_workqueue)
8254                                 flush_workqueue(dm->vblank_control_workqueue);
8255
8256                         amdgpu_dm_psr_disable_all(dm);
8257                 }
8258
8259                 dm_enable_per_frame_crtc_master_sync(dc_state);
8260                 mutex_lock(&dm->dc_lock);
8261                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8262
8263                 /* Allow idle optimization when vblank count is 0 for display off */
8264                 if (dm->active_vblank_irq_count == 0)
8265                         dc_allow_idle_optimizations(dm->dc, true);
8266                 mutex_unlock(&dm->dc_lock);
8267         }
8268
8269         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8270                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8271
8272                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8273
8274                 if (dm_new_crtc_state->stream != NULL) {
8275                         const struct dc_stream_status *status =
8276                                         dc_stream_get_status(dm_new_crtc_state->stream);
8277
8278                         if (!status)
8279                                 status = dc_stream_get_status_from_state(dc_state,
8280                                                                          dm_new_crtc_state->stream);
8281                         if (!status)
8282                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8283                         else
8284                                 acrtc->otg_inst = status->primary_otg_inst;
8285                 }
8286         }
8287 #ifdef CONFIG_DRM_AMD_DC_HDCP
8288         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8289                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8290                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8291                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8292
8293                 new_crtc_state = NULL;
8294
8295                 if (acrtc)
8296                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8297
8298                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8299
8300                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8301                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8302                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8303                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8304                         dm_new_con_state->update_hdcp = true;
8305                         continue;
8306                 }
8307
8308                 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8309                         hdcp_update_display(
8310                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8311                                 new_con_state->hdcp_content_type,
8312                                 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8313         }
8314 #endif
8315
8316         /* Handle connector state changes */
8317         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8318                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8319                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8320                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8321                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8322                 struct dc_stream_update stream_update;
8323                 struct dc_info_packet hdr_packet;
8324                 struct dc_stream_status *status = NULL;
8325                 bool abm_changed, hdr_changed, scaling_changed;
8326
8327                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8328                 memset(&stream_update, 0, sizeof(stream_update));
8329
8330                 if (acrtc) {
8331                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8332                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8333                 }
8334
8335                 /* Skip any modesets/resets */
8336                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8337                         continue;
8338
8339                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8340                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8341
8342                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8343                                                              dm_old_con_state);
8344
8345                 abm_changed = dm_new_crtc_state->abm_level !=
8346                               dm_old_crtc_state->abm_level;
8347
8348                 hdr_changed =
8349                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8350
8351                 if (!scaling_changed && !abm_changed && !hdr_changed)
8352                         continue;
8353
8354                 stream_update.stream = dm_new_crtc_state->stream;
8355                 if (scaling_changed) {
8356                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8357                                         dm_new_con_state, dm_new_crtc_state->stream);
8358
8359                         stream_update.src = dm_new_crtc_state->stream->src;
8360                         stream_update.dst = dm_new_crtc_state->stream->dst;
8361                 }
8362
8363                 if (abm_changed) {
8364                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8365
8366                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8367                 }
8368
8369                 if (hdr_changed) {
8370                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8371                         stream_update.hdr_static_metadata = &hdr_packet;
8372                 }
8373
8374                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8375
8376                 if (WARN_ON(!status))
8377                         continue;
8378
8379                 WARN_ON(!status->plane_count);
8380
8381                 /*
8382                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8383                  * Here we create an empty update on each plane.
8384                  * To fix this, DC should permit updating only stream properties.
8385                  */
8386                 for (j = 0; j < status->plane_count; j++)
8387                         dummy_updates[j].surface = status->plane_states[0];
8388
8389
8390                 mutex_lock(&dm->dc_lock);
8391                 dc_commit_updates_for_stream(dm->dc,
8392                                                      dummy_updates,
8393                                                      status->plane_count,
8394                                                      dm_new_crtc_state->stream,
8395                                                      &stream_update,
8396                                                      dc_state);
8397                 mutex_unlock(&dm->dc_lock);
8398         }
8399
8400         /**
8401          * Enable interrupts for CRTCs that are newly enabled or went through
8402          * a modeset. It was intentionally deferred until after the front end
8403          * state was modified to wait until the OTG was on and so the IRQ
8404          * handlers didn't access stale or invalid state.
8405          */
8406         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8407                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8408 #ifdef CONFIG_DEBUG_FS
8409                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8410 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8411                 struct crc_rd_work *crc_rd_wrk;
8412 #endif
8413 #endif
8414                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8415                 if (old_crtc_state->active && !new_crtc_state->active)
8416                         crtc_disable_count++;
8417
8418                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8419                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8420
8421                 /* For freesync config update on crtc state and params for irq */
8422                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8423
8424 #ifdef CONFIG_DEBUG_FS
8425 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8426                 crc_rd_wrk = dm->crc_rd_wrk;
8427 #endif
8428                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8429                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8430                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8431 #endif
8432
8433                 if (new_crtc_state->active &&
8434                     (!old_crtc_state->active ||
8435                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8436                         dc_stream_retain(dm_new_crtc_state->stream);
8437                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8438                         manage_dm_interrupts(adev, acrtc, true);
8439                 }
8440                 /* Handle vrr on->off / off->on transitions */
8441                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8442
8443 #ifdef CONFIG_DEBUG_FS
8444                 if (new_crtc_state->active &&
8445                     (!old_crtc_state->active ||
8446                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8447                         /**
8448                          * Frontend may have changed so reapply the CRC capture
8449                          * settings for the stream.
8450                          */
8451                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8452 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8453                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8454                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8455                                         acrtc->dm_irq_params.window_param.update_win = true;
8456                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8457                                         spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
8458                                         crc_rd_wrk->crtc = crtc;
8459                                         spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
8460                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8461                                 }
8462 #endif
8463                                 if (amdgpu_dm_crtc_configure_crc_source(
8464                                         crtc, dm_new_crtc_state, cur_crc_src))
8465                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8466                         }
8467                 }
8468 #endif
8469         }
8470
8471         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8472                 if (new_crtc_state->async_flip)
8473                         wait_for_vblank = false;
8474
8475         /* update planes when needed per crtc*/
8476         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8477                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8478
8479                 if (dm_new_crtc_state->stream)
8480                         amdgpu_dm_commit_planes(state, dc_state, dev,
8481                                                 dm, crtc, wait_for_vblank);
8482         }
8483
8484         /* Update audio instances for each connector. */
8485         amdgpu_dm_commit_audio(dev, state);
8486
8487         /* restore the backlight level */
8488         for (i = 0; i < dm->num_of_edps; i++) {
8489                 if (dm->backlight_dev[i] &&
8490                     (dm->actual_brightness[i] != dm->brightness[i]))
8491                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8492         }
8493
8494         /*
8495          * send vblank event on all events not handled in flip and
8496          * mark consumed event for drm_atomic_helper_commit_hw_done
8497          */
8498         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8499         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8500
8501                 if (new_crtc_state->event)
8502                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8503
8504                 new_crtc_state->event = NULL;
8505         }
8506         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8507
8508         /* Signal HW programming completion */
8509         drm_atomic_helper_commit_hw_done(state);
8510
8511         if (wait_for_vblank)
8512                 drm_atomic_helper_wait_for_flip_done(dev, state);
8513
8514         drm_atomic_helper_cleanup_planes(dev, state);
8515
8516         /* return the stolen vga memory back to VRAM */
8517         if (!adev->mman.keep_stolen_vga_memory)
8518                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8519         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8520
8521         /*
8522          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8523          * so we can put the GPU into runtime suspend if we're not driving any
8524          * displays anymore
8525          */
8526         for (i = 0; i < crtc_disable_count; i++)
8527                 pm_runtime_put_autosuspend(dev->dev);
8528         pm_runtime_mark_last_busy(dev->dev);
8529
8530         if (dc_state_temp)
8531                 dc_release_state(dc_state_temp);
8532 }
8533
8534 static int dm_force_atomic_commit(struct drm_connector *connector)
8535 {
8536         int ret = 0;
8537         struct drm_device *ddev = connector->dev;
8538         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8539         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8540         struct drm_plane *plane = disconnected_acrtc->base.primary;
8541         struct drm_connector_state *conn_state;
8542         struct drm_crtc_state *crtc_state;
8543         struct drm_plane_state *plane_state;
8544
8545         if (!state)
8546                 return -ENOMEM;
8547
8548         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8549
8550         /* Construct an atomic state to restore previous display setting */
8551
8552         /*
8553          * Attach connectors to drm_atomic_state
8554          */
8555         conn_state = drm_atomic_get_connector_state(state, connector);
8556
8557         ret = PTR_ERR_OR_ZERO(conn_state);
8558         if (ret)
8559                 goto out;
8560
8561         /* Attach crtc to drm_atomic_state*/
8562         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8563
8564         ret = PTR_ERR_OR_ZERO(crtc_state);
8565         if (ret)
8566                 goto out;
8567
8568         /* force a restore */
8569         crtc_state->mode_changed = true;
8570
8571         /* Attach plane to drm_atomic_state */
8572         plane_state = drm_atomic_get_plane_state(state, plane);
8573
8574         ret = PTR_ERR_OR_ZERO(plane_state);
8575         if (ret)
8576                 goto out;
8577
8578         /* Call commit internally with the state we just constructed */
8579         ret = drm_atomic_commit(state);
8580
8581 out:
8582         drm_atomic_state_put(state);
8583         if (ret)
8584                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8585
8586         return ret;
8587 }
8588
8589 /*
8590  * This function handles all cases when set mode does not come upon hotplug.
8591  * This includes when a display is unplugged then plugged back into the
8592  * same port and when running without usermode desktop manager supprot
8593  */
8594 void dm_restore_drm_connector_state(struct drm_device *dev,
8595                                     struct drm_connector *connector)
8596 {
8597         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8598         struct amdgpu_crtc *disconnected_acrtc;
8599         struct dm_crtc_state *acrtc_state;
8600
8601         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8602                 return;
8603
8604         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8605         if (!disconnected_acrtc)
8606                 return;
8607
8608         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8609         if (!acrtc_state->stream)
8610                 return;
8611
8612         /*
8613          * If the previous sink is not released and different from the current,
8614          * we deduce we are in a state where we can not rely on usermode call
8615          * to turn on the display, so we do it here
8616          */
8617         if (acrtc_state->stream->sink != aconnector->dc_sink)
8618                 dm_force_atomic_commit(&aconnector->base);
8619 }
8620
8621 /*
8622  * Grabs all modesetting locks to serialize against any blocking commits,
8623  * Waits for completion of all non blocking commits.
8624  */
8625 static int do_aquire_global_lock(struct drm_device *dev,
8626                                  struct drm_atomic_state *state)
8627 {
8628         struct drm_crtc *crtc;
8629         struct drm_crtc_commit *commit;
8630         long ret;
8631
8632         /*
8633          * Adding all modeset locks to aquire_ctx will
8634          * ensure that when the framework release it the
8635          * extra locks we are locking here will get released to
8636          */
8637         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8638         if (ret)
8639                 return ret;
8640
8641         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8642                 spin_lock(&crtc->commit_lock);
8643                 commit = list_first_entry_or_null(&crtc->commit_list,
8644                                 struct drm_crtc_commit, commit_entry);
8645                 if (commit)
8646                         drm_crtc_commit_get(commit);
8647                 spin_unlock(&crtc->commit_lock);
8648
8649                 if (!commit)
8650                         continue;
8651
8652                 /*
8653                  * Make sure all pending HW programming completed and
8654                  * page flips done
8655                  */
8656                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8657
8658                 if (ret > 0)
8659                         ret = wait_for_completion_interruptible_timeout(
8660                                         &commit->flip_done, 10*HZ);
8661
8662                 if (ret == 0)
8663                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8664                                   "timed out\n", crtc->base.id, crtc->name);
8665
8666                 drm_crtc_commit_put(commit);
8667         }
8668
8669         return ret < 0 ? ret : 0;
8670 }
8671
8672 static void get_freesync_config_for_crtc(
8673         struct dm_crtc_state *new_crtc_state,
8674         struct dm_connector_state *new_con_state)
8675 {
8676         struct mod_freesync_config config = {0};
8677         struct amdgpu_dm_connector *aconnector =
8678                         to_amdgpu_dm_connector(new_con_state->base.connector);
8679         struct drm_display_mode *mode = &new_crtc_state->base.mode;
8680         int vrefresh = drm_mode_vrefresh(mode);
8681         bool fs_vid_mode = false;
8682
8683         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8684                                         vrefresh >= aconnector->min_vfreq &&
8685                                         vrefresh <= aconnector->max_vfreq;
8686
8687         if (new_crtc_state->vrr_supported) {
8688                 new_crtc_state->stream->ignore_msa_timing_param = true;
8689                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
8690
8691                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8692                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
8693                 config.vsif_supported = true;
8694                 config.btr = true;
8695
8696                 if (fs_vid_mode) {
8697                         config.state = VRR_STATE_ACTIVE_FIXED;
8698                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8699                         goto out;
8700                 } else if (new_crtc_state->base.vrr_enabled) {
8701                         config.state = VRR_STATE_ACTIVE_VARIABLE;
8702                 } else {
8703                         config.state = VRR_STATE_INACTIVE;
8704                 }
8705         }
8706 out:
8707         new_crtc_state->freesync_config = config;
8708 }
8709
8710 static void reset_freesync_config_for_crtc(
8711         struct dm_crtc_state *new_crtc_state)
8712 {
8713         new_crtc_state->vrr_supported = false;
8714
8715         memset(&new_crtc_state->vrr_infopacket, 0,
8716                sizeof(new_crtc_state->vrr_infopacket));
8717 }
8718
8719 static bool
8720 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8721                                  struct drm_crtc_state *new_crtc_state)
8722 {
8723         const struct drm_display_mode *old_mode, *new_mode;
8724
8725         if (!old_crtc_state || !new_crtc_state)
8726                 return false;
8727
8728         old_mode = &old_crtc_state->mode;
8729         new_mode = &new_crtc_state->mode;
8730
8731         if (old_mode->clock       == new_mode->clock &&
8732             old_mode->hdisplay    == new_mode->hdisplay &&
8733             old_mode->vdisplay    == new_mode->vdisplay &&
8734             old_mode->htotal      == new_mode->htotal &&
8735             old_mode->vtotal      != new_mode->vtotal &&
8736             old_mode->hsync_start == new_mode->hsync_start &&
8737             old_mode->vsync_start != new_mode->vsync_start &&
8738             old_mode->hsync_end   == new_mode->hsync_end &&
8739             old_mode->vsync_end   != new_mode->vsync_end &&
8740             old_mode->hskew       == new_mode->hskew &&
8741             old_mode->vscan       == new_mode->vscan &&
8742             (old_mode->vsync_end - old_mode->vsync_start) ==
8743             (new_mode->vsync_end - new_mode->vsync_start))
8744                 return true;
8745
8746         return false;
8747 }
8748
8749 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
8750         uint64_t num, den, res;
8751         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8752
8753         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8754
8755         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8756         den = (unsigned long long)new_crtc_state->mode.htotal *
8757               (unsigned long long)new_crtc_state->mode.vtotal;
8758
8759         res = div_u64(num, den);
8760         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8761 }
8762
8763 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8764                          struct drm_atomic_state *state,
8765                          struct drm_crtc *crtc,
8766                          struct drm_crtc_state *old_crtc_state,
8767                          struct drm_crtc_state *new_crtc_state,
8768                          bool enable,
8769                          bool *lock_and_validation_needed)
8770 {
8771         struct dm_atomic_state *dm_state = NULL;
8772         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8773         struct dc_stream_state *new_stream;
8774         int ret = 0;
8775
8776         /*
8777          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8778          * update changed items
8779          */
8780         struct amdgpu_crtc *acrtc = NULL;
8781         struct amdgpu_dm_connector *aconnector = NULL;
8782         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8783         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8784
8785         new_stream = NULL;
8786
8787         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8788         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8789         acrtc = to_amdgpu_crtc(crtc);
8790         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8791
8792         /* TODO This hack should go away */
8793         if (aconnector && enable) {
8794                 /* Make sure fake sink is created in plug-in scenario */
8795                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8796                                                             &aconnector->base);
8797                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8798                                                             &aconnector->base);
8799
8800                 if (IS_ERR(drm_new_conn_state)) {
8801                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8802                         goto fail;
8803                 }
8804
8805                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8806                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
8807
8808                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8809                         goto skip_modeset;
8810
8811                 new_stream = create_validate_stream_for_sink(aconnector,
8812                                                              &new_crtc_state->mode,
8813                                                              dm_new_conn_state,
8814                                                              dm_old_crtc_state->stream);
8815
8816                 /*
8817                  * we can have no stream on ACTION_SET if a display
8818                  * was disconnected during S3, in this case it is not an
8819                  * error, the OS will be updated after detection, and
8820                  * will do the right thing on next atomic commit
8821                  */
8822
8823                 if (!new_stream) {
8824                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8825                                         __func__, acrtc->base.base.id);
8826                         ret = -ENOMEM;
8827                         goto fail;
8828                 }
8829
8830                 /*
8831                  * TODO: Check VSDB bits to decide whether this should
8832                  * be enabled or not.
8833                  */
8834                 new_stream->triggered_crtc_reset.enabled =
8835                         dm->force_timing_sync;
8836
8837                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8838
8839                 ret = fill_hdr_info_packet(drm_new_conn_state,
8840                                            &new_stream->hdr_static_metadata);
8841                 if (ret)
8842                         goto fail;
8843
8844                 /*
8845                  * If we already removed the old stream from the context
8846                  * (and set the new stream to NULL) then we can't reuse
8847                  * the old stream even if the stream and scaling are unchanged.
8848                  * We'll hit the BUG_ON and black screen.
8849                  *
8850                  * TODO: Refactor this function to allow this check to work
8851                  * in all conditions.
8852                  */
8853                 if (dm_new_crtc_state->stream &&
8854                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
8855                         goto skip_modeset;
8856
8857                 if (dm_new_crtc_state->stream &&
8858                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
8859                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
8860                         new_crtc_state->mode_changed = false;
8861                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
8862                                          new_crtc_state->mode_changed);
8863                 }
8864         }
8865
8866         /* mode_changed flag may get updated above, need to check again */
8867         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8868                 goto skip_modeset;
8869
8870         drm_dbg_state(state->dev,
8871                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8872                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8873                 "connectors_changed:%d\n",
8874                 acrtc->crtc_id,
8875                 new_crtc_state->enable,
8876                 new_crtc_state->active,
8877                 new_crtc_state->planes_changed,
8878                 new_crtc_state->mode_changed,
8879                 new_crtc_state->active_changed,
8880                 new_crtc_state->connectors_changed);
8881
8882         /* Remove stream for any changed/disabled CRTC */
8883         if (!enable) {
8884
8885                 if (!dm_old_crtc_state->stream)
8886                         goto skip_modeset;
8887
8888                 if (dm_new_crtc_state->stream &&
8889                     is_timing_unchanged_for_freesync(new_crtc_state,
8890                                                      old_crtc_state)) {
8891                         new_crtc_state->mode_changed = false;
8892                         DRM_DEBUG_DRIVER(
8893                                 "Mode change not required for front porch change, "
8894                                 "setting mode_changed to %d",
8895                                 new_crtc_state->mode_changed);
8896
8897                         set_freesync_fixed_config(dm_new_crtc_state);
8898
8899                         goto skip_modeset;
8900                 } else if (aconnector &&
8901                            is_freesync_video_mode(&new_crtc_state->mode,
8902                                                   aconnector)) {
8903                         struct drm_display_mode *high_mode;
8904
8905                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
8906                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
8907                                 set_freesync_fixed_config(dm_new_crtc_state);
8908                         }
8909                 }
8910
8911                 ret = dm_atomic_get_state(state, &dm_state);
8912                 if (ret)
8913                         goto fail;
8914
8915                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
8916                                 crtc->base.id);
8917
8918                 /* i.e. reset mode */
8919                 if (dc_remove_stream_from_ctx(
8920                                 dm->dc,
8921                                 dm_state->context,
8922                                 dm_old_crtc_state->stream) != DC_OK) {
8923                         ret = -EINVAL;
8924                         goto fail;
8925                 }
8926
8927                 dc_stream_release(dm_old_crtc_state->stream);
8928                 dm_new_crtc_state->stream = NULL;
8929
8930                 reset_freesync_config_for_crtc(dm_new_crtc_state);
8931
8932                 *lock_and_validation_needed = true;
8933
8934         } else {/* Add stream for any updated/enabled CRTC */
8935                 /*
8936                  * Quick fix to prevent NULL pointer on new_stream when
8937                  * added MST connectors not found in existing crtc_state in the chained mode
8938                  * TODO: need to dig out the root cause of that
8939                  */
8940                 if (!aconnector)
8941                         goto skip_modeset;
8942
8943                 if (modereset_required(new_crtc_state))
8944                         goto skip_modeset;
8945
8946                 if (modeset_required(new_crtc_state, new_stream,
8947                                      dm_old_crtc_state->stream)) {
8948
8949                         WARN_ON(dm_new_crtc_state->stream);
8950
8951                         ret = dm_atomic_get_state(state, &dm_state);
8952                         if (ret)
8953                                 goto fail;
8954
8955                         dm_new_crtc_state->stream = new_stream;
8956
8957                         dc_stream_retain(new_stream);
8958
8959                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
8960                                          crtc->base.id);
8961
8962                         if (dc_add_stream_to_ctx(
8963                                         dm->dc,
8964                                         dm_state->context,
8965                                         dm_new_crtc_state->stream) != DC_OK) {
8966                                 ret = -EINVAL;
8967                                 goto fail;
8968                         }
8969
8970                         *lock_and_validation_needed = true;
8971                 }
8972         }
8973
8974 skip_modeset:
8975         /* Release extra reference */
8976         if (new_stream)
8977                  dc_stream_release(new_stream);
8978
8979         /*
8980          * We want to do dc stream updates that do not require a
8981          * full modeset below.
8982          */
8983         if (!(enable && aconnector && new_crtc_state->active))
8984                 return 0;
8985         /*
8986          * Given above conditions, the dc state cannot be NULL because:
8987          * 1. We're in the process of enabling CRTCs (just been added
8988          *    to the dc context, or already is on the context)
8989          * 2. Has a valid connector attached, and
8990          * 3. Is currently active and enabled.
8991          * => The dc stream state currently exists.
8992          */
8993         BUG_ON(dm_new_crtc_state->stream == NULL);
8994
8995         /* Scaling or underscan settings */
8996         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
8997                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
8998                 update_stream_scaling_settings(
8999                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9000
9001         /* ABM settings */
9002         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9003
9004         /*
9005          * Color management settings. We also update color properties
9006          * when a modeset is needed, to ensure it gets reprogrammed.
9007          */
9008         if (dm_new_crtc_state->base.color_mgmt_changed ||
9009             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9010                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9011                 if (ret)
9012                         goto fail;
9013         }
9014
9015         /* Update Freesync settings. */
9016         get_freesync_config_for_crtc(dm_new_crtc_state,
9017                                      dm_new_conn_state);
9018
9019         return ret;
9020
9021 fail:
9022         if (new_stream)
9023                 dc_stream_release(new_stream);
9024         return ret;
9025 }
9026
9027 static bool should_reset_plane(struct drm_atomic_state *state,
9028                                struct drm_plane *plane,
9029                                struct drm_plane_state *old_plane_state,
9030                                struct drm_plane_state *new_plane_state)
9031 {
9032         struct drm_plane *other;
9033         struct drm_plane_state *old_other_state, *new_other_state;
9034         struct drm_crtc_state *new_crtc_state;
9035         int i;
9036
9037         /*
9038          * TODO: Remove this hack once the checks below are sufficient
9039          * enough to determine when we need to reset all the planes on
9040          * the stream.
9041          */
9042         if (state->allow_modeset)
9043                 return true;
9044
9045         /* Exit early if we know that we're adding or removing the plane. */
9046         if (old_plane_state->crtc != new_plane_state->crtc)
9047                 return true;
9048
9049         /* old crtc == new_crtc == NULL, plane not in context. */
9050         if (!new_plane_state->crtc)
9051                 return false;
9052
9053         new_crtc_state =
9054                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9055
9056         if (!new_crtc_state)
9057                 return true;
9058
9059         /* CRTC Degamma changes currently require us to recreate planes. */
9060         if (new_crtc_state->color_mgmt_changed)
9061                 return true;
9062
9063         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9064                 return true;
9065
9066         /*
9067          * If there are any new primary or overlay planes being added or
9068          * removed then the z-order can potentially change. To ensure
9069          * correct z-order and pipe acquisition the current DC architecture
9070          * requires us to remove and recreate all existing planes.
9071          *
9072          * TODO: Come up with a more elegant solution for this.
9073          */
9074         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9075                 struct amdgpu_framebuffer *old_afb, *new_afb;
9076                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9077                         continue;
9078
9079                 if (old_other_state->crtc != new_plane_state->crtc &&
9080                     new_other_state->crtc != new_plane_state->crtc)
9081                         continue;
9082
9083                 if (old_other_state->crtc != new_other_state->crtc)
9084                         return true;
9085
9086                 /* Src/dst size and scaling updates. */
9087                 if (old_other_state->src_w != new_other_state->src_w ||
9088                     old_other_state->src_h != new_other_state->src_h ||
9089                     old_other_state->crtc_w != new_other_state->crtc_w ||
9090                     old_other_state->crtc_h != new_other_state->crtc_h)
9091                         return true;
9092
9093                 /* Rotation / mirroring updates. */
9094                 if (old_other_state->rotation != new_other_state->rotation)
9095                         return true;
9096
9097                 /* Blending updates. */
9098                 if (old_other_state->pixel_blend_mode !=
9099                     new_other_state->pixel_blend_mode)
9100                         return true;
9101
9102                 /* Alpha updates. */
9103                 if (old_other_state->alpha != new_other_state->alpha)
9104                         return true;
9105
9106                 /* Colorspace changes. */
9107                 if (old_other_state->color_range != new_other_state->color_range ||
9108                     old_other_state->color_encoding != new_other_state->color_encoding)
9109                         return true;
9110
9111                 /* Framebuffer checks fall at the end. */
9112                 if (!old_other_state->fb || !new_other_state->fb)
9113                         continue;
9114
9115                 /* Pixel format changes can require bandwidth updates. */
9116                 if (old_other_state->fb->format != new_other_state->fb->format)
9117                         return true;
9118
9119                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9120                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9121
9122                 /* Tiling and DCC changes also require bandwidth updates. */
9123                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9124                     old_afb->base.modifier != new_afb->base.modifier)
9125                         return true;
9126         }
9127
9128         return false;
9129 }
9130
9131 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9132                               struct drm_plane_state *new_plane_state,
9133                               struct drm_framebuffer *fb)
9134 {
9135         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9136         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9137         unsigned int pitch;
9138         bool linear;
9139
9140         if (fb->width > new_acrtc->max_cursor_width ||
9141             fb->height > new_acrtc->max_cursor_height) {
9142                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9143                                  new_plane_state->fb->width,
9144                                  new_plane_state->fb->height);
9145                 return -EINVAL;
9146         }
9147         if (new_plane_state->src_w != fb->width << 16 ||
9148             new_plane_state->src_h != fb->height << 16) {
9149                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9150                 return -EINVAL;
9151         }
9152
9153         /* Pitch in pixels */
9154         pitch = fb->pitches[0] / fb->format->cpp[0];
9155
9156         if (fb->width != pitch) {
9157                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9158                                  fb->width, pitch);
9159                 return -EINVAL;
9160         }
9161
9162         switch (pitch) {
9163         case 64:
9164         case 128:
9165         case 256:
9166                 /* FB pitch is supported by cursor plane */
9167                 break;
9168         default:
9169                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9170                 return -EINVAL;
9171         }
9172
9173         /* Core DRM takes care of checking FB modifiers, so we only need to
9174          * check tiling flags when the FB doesn't have a modifier. */
9175         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9176                 if (adev->family < AMDGPU_FAMILY_AI) {
9177                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9178                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9179                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9180                 } else {
9181                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9182                 }
9183                 if (!linear) {
9184                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9185                         return -EINVAL;
9186                 }
9187         }
9188
9189         return 0;
9190 }
9191
9192 static int dm_update_plane_state(struct dc *dc,
9193                                  struct drm_atomic_state *state,
9194                                  struct drm_plane *plane,
9195                                  struct drm_plane_state *old_plane_state,
9196                                  struct drm_plane_state *new_plane_state,
9197                                  bool enable,
9198                                  bool *lock_and_validation_needed)
9199 {
9200
9201         struct dm_atomic_state *dm_state = NULL;
9202         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9203         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9204         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9205         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9206         struct amdgpu_crtc *new_acrtc;
9207         bool needs_reset;
9208         int ret = 0;
9209
9210
9211         new_plane_crtc = new_plane_state->crtc;
9212         old_plane_crtc = old_plane_state->crtc;
9213         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9214         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9215
9216         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9217                 if (!enable || !new_plane_crtc ||
9218                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9219                         return 0;
9220
9221                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9222
9223                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9224                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9225                         return -EINVAL;
9226                 }
9227
9228                 if (new_plane_state->fb) {
9229                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9230                                                  new_plane_state->fb);
9231                         if (ret)
9232                                 return ret;
9233                 }
9234
9235                 return 0;
9236         }
9237
9238         needs_reset = should_reset_plane(state, plane, old_plane_state,
9239                                          new_plane_state);
9240
9241         /* Remove any changed/removed planes */
9242         if (!enable) {
9243                 if (!needs_reset)
9244                         return 0;
9245
9246                 if (!old_plane_crtc)
9247                         return 0;
9248
9249                 old_crtc_state = drm_atomic_get_old_crtc_state(
9250                                 state, old_plane_crtc);
9251                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9252
9253                 if (!dm_old_crtc_state->stream)
9254                         return 0;
9255
9256                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9257                                 plane->base.id, old_plane_crtc->base.id);
9258
9259                 ret = dm_atomic_get_state(state, &dm_state);
9260                 if (ret)
9261                         return ret;
9262
9263                 if (!dc_remove_plane_from_context(
9264                                 dc,
9265                                 dm_old_crtc_state->stream,
9266                                 dm_old_plane_state->dc_state,
9267                                 dm_state->context)) {
9268
9269                         return -EINVAL;
9270                 }
9271
9272
9273                 dc_plane_state_release(dm_old_plane_state->dc_state);
9274                 dm_new_plane_state->dc_state = NULL;
9275
9276                 *lock_and_validation_needed = true;
9277
9278         } else { /* Add new planes */
9279                 struct dc_plane_state *dc_new_plane_state;
9280
9281                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9282                         return 0;
9283
9284                 if (!new_plane_crtc)
9285                         return 0;
9286
9287                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9288                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9289
9290                 if (!dm_new_crtc_state->stream)
9291                         return 0;
9292
9293                 if (!needs_reset)
9294                         return 0;
9295
9296                 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9297                 if (ret)
9298                         return ret;
9299
9300                 WARN_ON(dm_new_plane_state->dc_state);
9301
9302                 dc_new_plane_state = dc_create_plane_state(dc);
9303                 if (!dc_new_plane_state)
9304                         return -ENOMEM;
9305
9306                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9307                                  plane->base.id, new_plane_crtc->base.id);
9308
9309                 ret = fill_dc_plane_attributes(
9310                         drm_to_adev(new_plane_crtc->dev),
9311                         dc_new_plane_state,
9312                         new_plane_state,
9313                         new_crtc_state);
9314                 if (ret) {
9315                         dc_plane_state_release(dc_new_plane_state);
9316                         return ret;
9317                 }
9318
9319                 ret = dm_atomic_get_state(state, &dm_state);
9320                 if (ret) {
9321                         dc_plane_state_release(dc_new_plane_state);
9322                         return ret;
9323                 }
9324
9325                 /*
9326                  * Any atomic check errors that occur after this will
9327                  * not need a release. The plane state will be attached
9328                  * to the stream, and therefore part of the atomic
9329                  * state. It'll be released when the atomic state is
9330                  * cleaned.
9331                  */
9332                 if (!dc_add_plane_to_context(
9333                                 dc,
9334                                 dm_new_crtc_state->stream,
9335                                 dc_new_plane_state,
9336                                 dm_state->context)) {
9337
9338                         dc_plane_state_release(dc_new_plane_state);
9339                         return -EINVAL;
9340                 }
9341
9342                 dm_new_plane_state->dc_state = dc_new_plane_state;
9343
9344                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9345
9346                 /* Tell DC to do a full surface update every time there
9347                  * is a plane change. Inefficient, but works for now.
9348                  */
9349                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9350
9351                 *lock_and_validation_needed = true;
9352         }
9353
9354
9355         return ret;
9356 }
9357
9358 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9359                                        int *src_w, int *src_h)
9360 {
9361         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9362         case DRM_MODE_ROTATE_90:
9363         case DRM_MODE_ROTATE_270:
9364                 *src_w = plane_state->src_h >> 16;
9365                 *src_h = plane_state->src_w >> 16;
9366                 break;
9367         case DRM_MODE_ROTATE_0:
9368         case DRM_MODE_ROTATE_180:
9369         default:
9370                 *src_w = plane_state->src_w >> 16;
9371                 *src_h = plane_state->src_h >> 16;
9372                 break;
9373         }
9374 }
9375
9376 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9377                                 struct drm_crtc *crtc,
9378                                 struct drm_crtc_state *new_crtc_state)
9379 {
9380         struct drm_plane *cursor = crtc->cursor, *underlying;
9381         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9382         int i;
9383         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9384         int cursor_src_w, cursor_src_h;
9385         int underlying_src_w, underlying_src_h;
9386
9387         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9388          * cursor per pipe but it's going to inherit the scaling and
9389          * positioning from the underlying pipe. Check the cursor plane's
9390          * blending properties match the underlying planes'. */
9391
9392         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9393         if (!new_cursor_state || !new_cursor_state->fb) {
9394                 return 0;
9395         }
9396
9397         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9398         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9399         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9400
9401         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9402                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9403                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9404                         continue;
9405
9406                 /* Ignore disabled planes */
9407                 if (!new_underlying_state->fb)
9408                         continue;
9409
9410                 dm_get_oriented_plane_size(new_underlying_state,
9411                                            &underlying_src_w, &underlying_src_h);
9412                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9413                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9414
9415                 if (cursor_scale_w != underlying_scale_w ||
9416                     cursor_scale_h != underlying_scale_h) {
9417                         drm_dbg_atomic(crtc->dev,
9418                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9419                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9420                         return -EINVAL;
9421                 }
9422
9423                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9424                 if (new_underlying_state->crtc_x <= 0 &&
9425                     new_underlying_state->crtc_y <= 0 &&
9426                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9427                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9428                         break;
9429         }
9430
9431         return 0;
9432 }
9433
9434 #if defined(CONFIG_DRM_AMD_DC_DCN)
9435 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9436 {
9437         struct drm_connector *connector;
9438         struct drm_connector_state *conn_state, *old_conn_state;
9439         struct amdgpu_dm_connector *aconnector = NULL;
9440         int i;
9441         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9442                 if (!conn_state->crtc)
9443                         conn_state = old_conn_state;
9444
9445                 if (conn_state->crtc != crtc)
9446                         continue;
9447
9448                 aconnector = to_amdgpu_dm_connector(connector);
9449                 if (!aconnector->port || !aconnector->mst_port)
9450                         aconnector = NULL;
9451                 else
9452                         break;
9453         }
9454
9455         if (!aconnector)
9456                 return 0;
9457
9458         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9459 }
9460 #endif
9461
9462 /**
9463  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9464  *
9465  * @dev: The DRM device
9466  * @state: The atomic state to commit
9467  *
9468  * Validate that the given atomic state is programmable by DC into hardware.
9469  * This involves constructing a &struct dc_state reflecting the new hardware
9470  * state we wish to commit, then querying DC to see if it is programmable. It's
9471  * important not to modify the existing DC state. Otherwise, atomic_check
9472  * may unexpectedly commit hardware changes.
9473  *
9474  * When validating the DC state, it's important that the right locks are
9475  * acquired. For full updates case which removes/adds/updates streams on one
9476  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9477  * that any such full update commit will wait for completion of any outstanding
9478  * flip using DRMs synchronization events.
9479  *
9480  * Note that DM adds the affected connectors for all CRTCs in state, when that
9481  * might not seem necessary. This is because DC stream creation requires the
9482  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9483  * be possible but non-trivial - a possible TODO item.
9484  *
9485  * Return: -Error code if validation failed.
9486  */
9487 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9488                                   struct drm_atomic_state *state)
9489 {
9490         struct amdgpu_device *adev = drm_to_adev(dev);
9491         struct dm_atomic_state *dm_state = NULL;
9492         struct dc *dc = adev->dm.dc;
9493         struct drm_connector *connector;
9494         struct drm_connector_state *old_con_state, *new_con_state;
9495         struct drm_crtc *crtc;
9496         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9497         struct drm_plane *plane;
9498         struct drm_plane_state *old_plane_state, *new_plane_state;
9499         enum dc_status status;
9500         int ret, i;
9501         bool lock_and_validation_needed = false;
9502         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9503 #if defined(CONFIG_DRM_AMD_DC_DCN)
9504         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9505 #endif
9506
9507         trace_amdgpu_dm_atomic_check_begin(state);
9508
9509         ret = drm_atomic_helper_check_modeset(dev, state);
9510         if (ret) {
9511                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9512                 goto fail;
9513         }
9514
9515         /* Check connector changes */
9516         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9517                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9518                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9519
9520                 /* Skip connectors that are disabled or part of modeset already. */
9521                 if (!new_con_state->crtc)
9522                         continue;
9523
9524                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9525                 if (IS_ERR(new_crtc_state)) {
9526                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9527                         ret = PTR_ERR(new_crtc_state);
9528                         goto fail;
9529                 }
9530
9531                 if (dm_old_con_state->abm_level !=
9532                     dm_new_con_state->abm_level)
9533                         new_crtc_state->connectors_changed = true;
9534         }
9535
9536 #if defined(CONFIG_DRM_AMD_DC_DCN)
9537         if (dc_resource_is_dsc_encoding_supported(dc)) {
9538                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9539                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9540                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9541                                 if (ret) {
9542                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9543                                         goto fail;
9544                                 }
9545                         }
9546                 }
9547         }
9548 #endif
9549         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9550                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9551
9552                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9553                     !new_crtc_state->color_mgmt_changed &&
9554                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9555                         dm_old_crtc_state->dsc_force_changed == false)
9556                         continue;
9557
9558                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9559                 if (ret) {
9560                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9561                         goto fail;
9562                 }
9563
9564                 if (!new_crtc_state->enable)
9565                         continue;
9566
9567                 ret = drm_atomic_add_affected_connectors(state, crtc);
9568                 if (ret) {
9569                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9570                         goto fail;
9571                 }
9572
9573                 ret = drm_atomic_add_affected_planes(state, crtc);
9574                 if (ret) {
9575                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9576                         goto fail;
9577                 }
9578
9579                 if (dm_old_crtc_state->dsc_force_changed)
9580                         new_crtc_state->mode_changed = true;
9581         }
9582
9583         /*
9584          * Add all primary and overlay planes on the CRTC to the state
9585          * whenever a plane is enabled to maintain correct z-ordering
9586          * and to enable fast surface updates.
9587          */
9588         drm_for_each_crtc(crtc, dev) {
9589                 bool modified = false;
9590
9591                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9592                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9593                                 continue;
9594
9595                         if (new_plane_state->crtc == crtc ||
9596                             old_plane_state->crtc == crtc) {
9597                                 modified = true;
9598                                 break;
9599                         }
9600                 }
9601
9602                 if (!modified)
9603                         continue;
9604
9605                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9606                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9607                                 continue;
9608
9609                         new_plane_state =
9610                                 drm_atomic_get_plane_state(state, plane);
9611
9612                         if (IS_ERR(new_plane_state)) {
9613                                 ret = PTR_ERR(new_plane_state);
9614                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9615                                 goto fail;
9616                         }
9617                 }
9618         }
9619
9620         /*
9621          * DC consults the zpos (layer_index in DC terminology) to determine the
9622          * hw plane on which to enable the hw cursor (see
9623          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9624          * atomic state, so call drm helper to normalize zpos.
9625          */
9626         drm_atomic_normalize_zpos(dev, state);
9627
9628         /* Remove exiting planes if they are modified */
9629         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9630                 ret = dm_update_plane_state(dc, state, plane,
9631                                             old_plane_state,
9632                                             new_plane_state,
9633                                             false,
9634                                             &lock_and_validation_needed);
9635                 if (ret) {
9636                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9637                         goto fail;
9638                 }
9639         }
9640
9641         /* Disable all crtcs which require disable */
9642         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9643                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9644                                            old_crtc_state,
9645                                            new_crtc_state,
9646                                            false,
9647                                            &lock_and_validation_needed);
9648                 if (ret) {
9649                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
9650                         goto fail;
9651                 }
9652         }
9653
9654         /* Enable all crtcs which require enable */
9655         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9656                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9657                                            old_crtc_state,
9658                                            new_crtc_state,
9659                                            true,
9660                                            &lock_and_validation_needed);
9661                 if (ret) {
9662                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
9663                         goto fail;
9664                 }
9665         }
9666
9667         /* Add new/modified planes */
9668         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9669                 ret = dm_update_plane_state(dc, state, plane,
9670                                             old_plane_state,
9671                                             new_plane_state,
9672                                             true,
9673                                             &lock_and_validation_needed);
9674                 if (ret) {
9675                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9676                         goto fail;
9677                 }
9678         }
9679
9680 #if defined(CONFIG_DRM_AMD_DC_DCN)
9681         if (dc_resource_is_dsc_encoding_supported(dc)) {
9682                 ret = pre_validate_dsc(state, &dm_state, vars);
9683                 if (ret != 0)
9684                         goto fail;
9685         }
9686 #endif
9687
9688         /* Run this here since we want to validate the streams we created */
9689         ret = drm_atomic_helper_check_planes(dev, state);
9690         if (ret) {
9691                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
9692                 goto fail;
9693         }
9694
9695         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9696                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9697                 if (dm_new_crtc_state->mpo_requested)
9698                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9699         }
9700
9701         /* Check cursor planes scaling */
9702         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9703                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9704                 if (ret) {
9705                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
9706                         goto fail;
9707                 }
9708         }
9709
9710         if (state->legacy_cursor_update) {
9711                 /*
9712                  * This is a fast cursor update coming from the plane update
9713                  * helper, check if it can be done asynchronously for better
9714                  * performance.
9715                  */
9716                 state->async_update =
9717                         !drm_atomic_helper_async_check(dev, state);
9718
9719                 /*
9720                  * Skip the remaining global validation if this is an async
9721                  * update. Cursor updates can be done without affecting
9722                  * state or bandwidth calcs and this avoids the performance
9723                  * penalty of locking the private state object and
9724                  * allocating a new dc_state.
9725                  */
9726                 if (state->async_update)
9727                         return 0;
9728         }
9729
9730         /* Check scaling and underscan changes*/
9731         /* TODO Removed scaling changes validation due to inability to commit
9732          * new stream into context w\o causing full reset. Need to
9733          * decide how to handle.
9734          */
9735         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9736                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9737                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9738                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9739
9740                 /* Skip any modesets/resets */
9741                 if (!acrtc || drm_atomic_crtc_needs_modeset(
9742                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9743                         continue;
9744
9745                 /* Skip any thing not scale or underscan changes */
9746                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9747                         continue;
9748
9749                 lock_and_validation_needed = true;
9750         }
9751
9752         /**
9753          * Streams and planes are reset when there are changes that affect
9754          * bandwidth. Anything that affects bandwidth needs to go through
9755          * DC global validation to ensure that the configuration can be applied
9756          * to hardware.
9757          *
9758          * We have to currently stall out here in atomic_check for outstanding
9759          * commits to finish in this case because our IRQ handlers reference
9760          * DRM state directly - we can end up disabling interrupts too early
9761          * if we don't.
9762          *
9763          * TODO: Remove this stall and drop DM state private objects.
9764          */
9765         if (lock_and_validation_needed) {
9766                 ret = dm_atomic_get_state(state, &dm_state);
9767                 if (ret) {
9768                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
9769                         goto fail;
9770                 }
9771
9772                 ret = do_aquire_global_lock(dev, state);
9773                 if (ret) {
9774                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
9775                         goto fail;
9776                 }
9777
9778 #if defined(CONFIG_DRM_AMD_DC_DCN)
9779                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
9780                 if (ret) {
9781                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
9782                         goto fail;
9783                 }
9784
9785                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
9786                 if (ret) {
9787                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
9788                         goto fail;
9789                 }
9790 #endif
9791
9792                 /*
9793                  * Perform validation of MST topology in the state:
9794                  * We need to perform MST atomic check before calling
9795                  * dc_validate_global_state(), or there is a chance
9796                  * to get stuck in an infinite loop and hang eventually.
9797                  */
9798                 ret = drm_dp_mst_atomic_check(state);
9799                 if (ret) {
9800                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
9801                         goto fail;
9802                 }
9803                 status = dc_validate_global_state(dc, dm_state->context, true);
9804                 if (status != DC_OK) {
9805                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
9806                                        dc_status_to_str(status), status);
9807                         ret = -EINVAL;
9808                         goto fail;
9809                 }
9810         } else {
9811                 /*
9812                  * The commit is a fast update. Fast updates shouldn't change
9813                  * the DC context, affect global validation, and can have their
9814                  * commit work done in parallel with other commits not touching
9815                  * the same resource. If we have a new DC context as part of
9816                  * the DM atomic state from validation we need to free it and
9817                  * retain the existing one instead.
9818                  *
9819                  * Furthermore, since the DM atomic state only contains the DC
9820                  * context and can safely be annulled, we can free the state
9821                  * and clear the associated private object now to free
9822                  * some memory and avoid a possible use-after-free later.
9823                  */
9824
9825                 for (i = 0; i < state->num_private_objs; i++) {
9826                         struct drm_private_obj *obj = state->private_objs[i].ptr;
9827
9828                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
9829                                 int j = state->num_private_objs-1;
9830
9831                                 dm_atomic_destroy_state(obj,
9832                                                 state->private_objs[i].state);
9833
9834                                 /* If i is not at the end of the array then the
9835                                  * last element needs to be moved to where i was
9836                                  * before the array can safely be truncated.
9837                                  */
9838                                 if (i != j)
9839                                         state->private_objs[i] =
9840                                                 state->private_objs[j];
9841
9842                                 state->private_objs[j].ptr = NULL;
9843                                 state->private_objs[j].state = NULL;
9844                                 state->private_objs[j].old_state = NULL;
9845                                 state->private_objs[j].new_state = NULL;
9846
9847                                 state->num_private_objs = j;
9848                                 break;
9849                         }
9850                 }
9851         }
9852
9853         /* Store the overall update type for use later in atomic check. */
9854         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
9855                 struct dm_crtc_state *dm_new_crtc_state =
9856                         to_dm_crtc_state(new_crtc_state);
9857
9858                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
9859                                                          UPDATE_TYPE_FULL :
9860                                                          UPDATE_TYPE_FAST;
9861         }
9862
9863         /* Must be success */
9864         WARN_ON(ret);
9865
9866         trace_amdgpu_dm_atomic_check_finish(state, ret);
9867
9868         return ret;
9869
9870 fail:
9871         if (ret == -EDEADLK)
9872                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
9873         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
9874                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
9875         else
9876                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
9877
9878         trace_amdgpu_dm_atomic_check_finish(state, ret);
9879
9880         return ret;
9881 }
9882
9883 static bool is_dp_capable_without_timing_msa(struct dc *dc,
9884                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
9885 {
9886         uint8_t dpcd_data;
9887         bool capable = false;
9888
9889         if (amdgpu_dm_connector->dc_link &&
9890                 dm_helpers_dp_read_dpcd(
9891                                 NULL,
9892                                 amdgpu_dm_connector->dc_link,
9893                                 DP_DOWN_STREAM_PORT_COUNT,
9894                                 &dpcd_data,
9895                                 sizeof(dpcd_data))) {
9896                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
9897         }
9898
9899         return capable;
9900 }
9901
9902 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
9903                 unsigned int offset,
9904                 unsigned int total_length,
9905                 uint8_t *data,
9906                 unsigned int length,
9907                 struct amdgpu_hdmi_vsdb_info *vsdb)
9908 {
9909         bool res;
9910         union dmub_rb_cmd cmd;
9911         struct dmub_cmd_send_edid_cea *input;
9912         struct dmub_cmd_edid_cea_output *output;
9913
9914         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
9915                 return false;
9916
9917         memset(&cmd, 0, sizeof(cmd));
9918
9919         input = &cmd.edid_cea.data.input;
9920
9921         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
9922         cmd.edid_cea.header.sub_type = 0;
9923         cmd.edid_cea.header.payload_bytes =
9924                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
9925         input->offset = offset;
9926         input->length = length;
9927         input->cea_total_length = total_length;
9928         memcpy(input->payload, data, length);
9929
9930         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
9931         if (!res) {
9932                 DRM_ERROR("EDID CEA parser failed\n");
9933                 return false;
9934         }
9935
9936         output = &cmd.edid_cea.data.output;
9937
9938         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
9939                 if (!output->ack.success) {
9940                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
9941                                         output->ack.offset);
9942                 }
9943         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
9944                 if (!output->amd_vsdb.vsdb_found)
9945                         return false;
9946
9947                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
9948                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
9949                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
9950                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
9951         } else {
9952                 DRM_WARN("Unknown EDID CEA parser results\n");
9953                 return false;
9954         }
9955
9956         return true;
9957 }
9958
9959 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
9960                 uint8_t *edid_ext, int len,
9961                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9962 {
9963         int i;
9964
9965         /* send extension block to DMCU for parsing */
9966         for (i = 0; i < len; i += 8) {
9967                 bool res;
9968                 int offset;
9969
9970                 /* send 8 bytes a time */
9971                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
9972                         return false;
9973
9974                 if (i+8 == len) {
9975                         /* EDID block sent completed, expect result */
9976                         int version, min_rate, max_rate;
9977
9978                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
9979                         if (res) {
9980                                 /* amd vsdb found */
9981                                 vsdb_info->freesync_supported = 1;
9982                                 vsdb_info->amd_vsdb_version = version;
9983                                 vsdb_info->min_refresh_rate_hz = min_rate;
9984                                 vsdb_info->max_refresh_rate_hz = max_rate;
9985                                 return true;
9986                         }
9987                         /* not amd vsdb */
9988                         return false;
9989                 }
9990
9991                 /* check for ack*/
9992                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
9993                 if (!res)
9994                         return false;
9995         }
9996
9997         return false;
9998 }
9999
10000 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10001                 uint8_t *edid_ext, int len,
10002                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10003 {
10004         int i;
10005
10006         /* send extension block to DMCU for parsing */
10007         for (i = 0; i < len; i += 8) {
10008                 /* send 8 bytes a time */
10009                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10010                         return false;
10011         }
10012
10013         return vsdb_info->freesync_supported;
10014 }
10015
10016 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10017                 uint8_t *edid_ext, int len,
10018                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10019 {
10020         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10021
10022         if (adev->dm.dmub_srv)
10023                 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10024         else
10025                 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10026 }
10027
10028 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10029                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10030 {
10031         uint8_t *edid_ext = NULL;
10032         int i;
10033         bool valid_vsdb_found = false;
10034
10035         /*----- drm_find_cea_extension() -----*/
10036         /* No EDID or EDID extensions */
10037         if (edid == NULL || edid->extensions == 0)
10038                 return -ENODEV;
10039
10040         /* Find CEA extension */
10041         for (i = 0; i < edid->extensions; i++) {
10042                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10043                 if (edid_ext[0] == CEA_EXT)
10044                         break;
10045         }
10046
10047         if (i == edid->extensions)
10048                 return -ENODEV;
10049
10050         /*----- cea_db_offsets() -----*/
10051         if (edid_ext[0] != CEA_EXT)
10052                 return -ENODEV;
10053
10054         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10055
10056         return valid_vsdb_found ? i : -ENODEV;
10057 }
10058
10059 /**
10060  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10061  *
10062  * @connector: Connector to query.
10063  * @edid: EDID from monitor
10064  *
10065  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10066  * track of some of the display information in the internal data struct used by
10067  * amdgpu_dm. This function checks which type of connector we need to set the
10068  * FreeSync parameters.
10069  */
10070 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10071                                     struct edid *edid)
10072 {
10073         int i = 0;
10074         struct detailed_timing *timing;
10075         struct detailed_non_pixel *data;
10076         struct detailed_data_monitor_range *range;
10077         struct amdgpu_dm_connector *amdgpu_dm_connector =
10078                         to_amdgpu_dm_connector(connector);
10079         struct dm_connector_state *dm_con_state = NULL;
10080         struct dc_sink *sink;
10081
10082         struct drm_device *dev = connector->dev;
10083         struct amdgpu_device *adev = drm_to_adev(dev);
10084         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10085         bool freesync_capable = false;
10086
10087         if (!connector->state) {
10088                 DRM_ERROR("%s - Connector has no state", __func__);
10089                 goto update;
10090         }
10091
10092         sink = amdgpu_dm_connector->dc_sink ?
10093                 amdgpu_dm_connector->dc_sink :
10094                 amdgpu_dm_connector->dc_em_sink;
10095
10096         if (!edid || !sink) {
10097                 dm_con_state = to_dm_connector_state(connector->state);
10098
10099                 amdgpu_dm_connector->min_vfreq = 0;
10100                 amdgpu_dm_connector->max_vfreq = 0;
10101                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10102                 connector->display_info.monitor_range.min_vfreq = 0;
10103                 connector->display_info.monitor_range.max_vfreq = 0;
10104                 freesync_capable = false;
10105
10106                 goto update;
10107         }
10108
10109         dm_con_state = to_dm_connector_state(connector->state);
10110
10111         if (!adev->dm.freesync_module)
10112                 goto update;
10113
10114         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10115                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10116                 bool edid_check_required = false;
10117
10118                 if (edid) {
10119                         edid_check_required = is_dp_capable_without_timing_msa(
10120                                                 adev->dm.dc,
10121                                                 amdgpu_dm_connector);
10122                 }
10123
10124                 if (edid_check_required == true && (edid->version > 1 ||
10125                    (edid->version == 1 && edid->revision > 1))) {
10126                         for (i = 0; i < 4; i++) {
10127
10128                                 timing  = &edid->detailed_timings[i];
10129                                 data    = &timing->data.other_data;
10130                                 range   = &data->data.range;
10131                                 /*
10132                                  * Check if monitor has continuous frequency mode
10133                                  */
10134                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10135                                         continue;
10136                                 /*
10137                                  * Check for flag range limits only. If flag == 1 then
10138                                  * no additional timing information provided.
10139                                  * Default GTF, GTF Secondary curve and CVT are not
10140                                  * supported
10141                                  */
10142                                 if (range->flags != 1)
10143                                         continue;
10144
10145                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10146                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10147                                 amdgpu_dm_connector->pixel_clock_mhz =
10148                                         range->pixel_clock_mhz * 10;
10149
10150                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10151                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10152
10153                                 break;
10154                         }
10155
10156                         if (amdgpu_dm_connector->max_vfreq -
10157                             amdgpu_dm_connector->min_vfreq > 10) {
10158
10159                                 freesync_capable = true;
10160                         }
10161                 }
10162         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10163                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10164                 if (i >= 0 && vsdb_info.freesync_supported) {
10165                         timing  = &edid->detailed_timings[i];
10166                         data    = &timing->data.other_data;
10167
10168                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10169                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10170                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10171                                 freesync_capable = true;
10172
10173                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10174                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10175                 }
10176         }
10177
10178 update:
10179         if (dm_con_state)
10180                 dm_con_state->freesync_capable = freesync_capable;
10181
10182         if (connector->vrr_capable_property)
10183                 drm_connector_set_vrr_capable_property(connector,
10184                                                        freesync_capable);
10185 }
10186
10187 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10188 {
10189         struct amdgpu_device *adev = drm_to_adev(dev);
10190         struct dc *dc = adev->dm.dc;
10191         int i;
10192
10193         mutex_lock(&adev->dm.dc_lock);
10194         if (dc->current_state) {
10195                 for (i = 0; i < dc->current_state->stream_count; ++i)
10196                         dc->current_state->streams[i]
10197                                 ->triggered_crtc_reset.enabled =
10198                                 adev->dm.force_timing_sync;
10199
10200                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10201                 dc_trigger_sync(dc, dc->current_state);
10202         }
10203         mutex_unlock(&adev->dm.dc_lock);
10204 }
10205
10206 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10207                        uint32_t value, const char *func_name)
10208 {
10209 #ifdef DM_CHECK_ADDR_0
10210         if (address == 0) {
10211                 DC_ERR("invalid register write. address = 0");
10212                 return;
10213         }
10214 #endif
10215         cgs_write_register(ctx->cgs_device, address, value);
10216         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10217 }
10218
10219 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10220                           const char *func_name)
10221 {
10222         uint32_t value;
10223 #ifdef DM_CHECK_ADDR_0
10224         if (address == 0) {
10225                 DC_ERR("invalid register read; address = 0\n");
10226                 return 0;
10227         }
10228 #endif
10229
10230         if (ctx->dmub_srv &&
10231             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10232             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10233                 ASSERT(false);
10234                 return 0;
10235         }
10236
10237         value = cgs_read_register(ctx->cgs_device, address);
10238
10239         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10240
10241         return value;
10242 }
10243
10244 int amdgpu_dm_process_dmub_aux_transfer_sync(
10245                 struct dc_context *ctx,
10246                 unsigned int link_index,
10247                 struct aux_payload *payload,
10248                 enum aux_return_code_type *operation_result)
10249 {
10250         struct amdgpu_device *adev = ctx->driver_context;
10251         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10252         int ret = -1;
10253
10254         mutex_lock(&adev->dm.dpia_aux_lock);
10255         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10256                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10257                 goto out;
10258         }
10259
10260         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10261                 DRM_ERROR("wait_for_completion_timeout timeout!");
10262                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10263                 goto out;
10264         }
10265
10266         if (p_notify->result != AUX_RET_SUCCESS) {
10267                 /*
10268                  * Transient states before tunneling is enabled could
10269                  * lead to this error. We can ignore this for now.
10270                  */
10271                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10272                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10273                                         payload->address, payload->length,
10274                                         p_notify->result);
10275                 }
10276                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10277                 goto out;
10278         }
10279
10280
10281         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10282         if (!payload->write && p_notify->aux_reply.length &&
10283                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10284
10285                 if (payload->length != p_notify->aux_reply.length) {
10286                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10287                                 p_notify->aux_reply.length,
10288                                         payload->address, payload->length);
10289                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10290                         goto out;
10291                 }
10292
10293                 memcpy(payload->data, p_notify->aux_reply.data,
10294                                 p_notify->aux_reply.length);
10295         }
10296
10297         /* success */
10298         ret = p_notify->aux_reply.length;
10299         *operation_result = p_notify->result;
10300 out:
10301         mutex_unlock(&adev->dm.dpia_aux_lock);
10302         return ret;
10303 }
10304
10305 int amdgpu_dm_process_dmub_set_config_sync(
10306                 struct dc_context *ctx,
10307                 unsigned int link_index,
10308                 struct set_config_cmd_payload *payload,
10309                 enum set_config_status *operation_result)
10310 {
10311         struct amdgpu_device *adev = ctx->driver_context;
10312         bool is_cmd_complete;
10313         int ret;
10314
10315         mutex_lock(&adev->dm.dpia_aux_lock);
10316         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10317                         link_index, payload, adev->dm.dmub_notify);
10318
10319         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10320                 ret = 0;
10321                 *operation_result = adev->dm.dmub_notify->sc_status;
10322         } else {
10323                 DRM_ERROR("wait_for_completion_timeout timeout!");
10324                 ret = -1;
10325                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10326         }
10327
10328         mutex_unlock(&adev->dm.dpia_aux_lock);
10329         return ret;
10330 }
10331
10332 /*
10333  * Check whether seamless boot is supported.
10334  *
10335  * So far we only support seamless boot on CHIP_VANGOGH.
10336  * If everything goes well, we may consider expanding
10337  * seamless boot to other ASICs.
10338  */
10339 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10340 {
10341         switch (adev->ip_versions[DCE_HWIP][0]) {
10342         case IP_VERSION(3, 0, 1):
10343                 if (!adev->mman.keep_stolen_vga_memory)
10344                         return true;
10345                 break;
10346         default:
10347                 break;
10348         }
10349
10350         return false;
10351 }