drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  */
 369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 370                                                     int update_type,
 371                                                     int planes_count,
 372                                                     struct dc_stream_state *stream,
 373                                                     struct dc_stream_update *stream_update,
 374                                                     struct dc_surface_update *array_of_surface_update)
 375 {
 376         reverse_planes_order(array_of_surface_update, planes_count);
 377
 378         /*
 379          * Previous frame finished and HW is ready for optimization.
 380          */
 381         if (update_type == UPDATE_TYPE_FAST)
 382                 dc_post_update_surfaces_to_stream(dc);
 383
 384         return dc_update_planes_and_stream(dc,
 385                                            array_of_surface_update,
 386                                            planes_count,
 387                                            stream,
 388                                            stream_update);
 389 }
 390
 391 /**
 392  * dm_pflip_high_irq() - Handle pageflip interrupt
 393  * @interrupt_params: ignored
 394  *
 395  * Handles the pageflip interrupt by notifying all interested parties
 396  * that the pageflip has been completed.
 397  */
 398 static void dm_pflip_high_irq(void *interrupt_params)
 399 {
 400         struct amdgpu_crtc *amdgpu_crtc;
 401         struct common_irq_params *irq_params = interrupt_params;
 402         struct amdgpu_device *adev = irq_params->adev;
 403         unsigned long flags;
 404         struct drm_pending_vblank_event *e;
 405         u32 vpos, hpos, v_blank_start, v_blank_end;
 406         bool vrr_active;
 407
 408         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 409
 410         /* IRQ could occur when in initial stage */
 411         /* TODO work and BO cleanup */
 412         if (amdgpu_crtc == NULL) {
 413                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 414                 return;
 415         }
 416
 417         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 418
 419         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 420                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 421                                                  amdgpu_crtc->pflip_status,
 422                                                  AMDGPU_FLIP_SUBMITTED,
 423                                                  amdgpu_crtc->crtc_id,
 424                                                  amdgpu_crtc);
 425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 426                 return;
 427         }
 428
 429         /* page flip completed. */
 430         e = amdgpu_crtc->event;
 431         amdgpu_crtc->event = NULL;
 432
 433         WARN_ON(!e);
 434
 435         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 436
 437         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 438         if (!vrr_active ||
 439             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 440                                       &v_blank_end, &hpos, &vpos) ||
 441             (vpos < v_blank_start)) {
 442                 /* Update to correct count and vblank timestamp if racing with
 443                  * vblank irq. This also updates to the correct vblank timestamp
 444                  * even in VRR mode, as scanout is past the front-porch atm.
 445                  */
 446                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 447
 448                 /* Wake up userspace by sending the pageflip event with proper
 449                  * count and timestamp of vblank of flip completion.
 450                  */
 451                 if (e) {
 452                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 453
 454                         /* Event sent, so done with vblank for this flip */
 455                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 456                 }
 457         } else if (e) {
 458                 /* VRR active and inside front-porch: vblank count and
 459                  * timestamp for pageflip event will only be up to date after
 460                  * drm_crtc_handle_vblank() has been executed from late vblank
 461                  * irq handler after start of back-porch (vline 0). We queue the
 462                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 463                  * updated timestamp and count, once it runs after us.
 464                  *
 465                  * We need to open-code this instead of using the helper
 466                  * drm_crtc_arm_vblank_event(), as that helper would
 467                  * call drm_crtc_accurate_vblank_count(), which we must
 468                  * not call in VRR mode while we are in front-porch!
 469                  */
 470
 471                 /* sequence will be replaced by real count during send-out. */
 472                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 473                 e->pipe = amdgpu_crtc->crtc_id;
 474
 475                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 476                 e = NULL;
 477         }
 478
 479         /* Keep track of vblank of this flip for flip throttling. We use the
 480          * cooked hw counter, as that one incremented at start of this vblank
 481          * of pageflip completion, so last_flip_vblank is the forbidden count
 482          * for queueing new pageflips if vsync + VRR is enabled.
 483          */
 484         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 485                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 486
 487         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 488         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 489
 490         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 491                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 492                      vrr_active, (int) !e);
 493 }
 494
 495 static void dm_vupdate_high_irq(void *interrupt_params)
 496 {
 497         struct common_irq_params *irq_params = interrupt_params;
 498         struct amdgpu_device *adev = irq_params->adev;
 499         struct amdgpu_crtc *acrtc;
 500         struct drm_device *drm_dev;
 501         struct drm_vblank_crtc *vblank;
 502         ktime_t frame_duration_ns, previous_timestamp;
 503         unsigned long flags;
 504         int vrr_active;
 505
 506         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 507
 508         if (acrtc) {
 509                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 510                 drm_dev = acrtc->base.dev;
 511                 vblank = &drm_dev->vblank[acrtc->base.index];
 512                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 513                 frame_duration_ns = vblank->time - previous_timestamp;
 514
 515                 if (frame_duration_ns > 0) {
 516                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 517                                                 frame_duration_ns,
 518                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 519                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 520                 }
 521
 522                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 523                               acrtc->crtc_id,
 524                               vrr_active);
 525
 526                 /* Core vblank handling is done here after end of front-porch in
 527                  * vrr mode, as vblank timestamping will give valid results
 528                  * while now done after front-porch. This will also deliver
 529                  * page-flip completion events that have been queued to us
 530                  * if a pageflip happened inside front-porch.
 531                  */
 532                 if (vrr_active) {
 533                         amdgpu_dm_crtc_handle_vblank(acrtc);
 534
 535                         /* BTR processing for pre-DCE12 ASICs */
 536                         if (acrtc->dm_irq_params.stream &&
 537                             adev->family < AMDGPU_FAMILY_AI) {
 538                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 539                                 mod_freesync_handle_v_update(
 540                                     adev->dm.freesync_module,
 541                                     acrtc->dm_irq_params.stream,
 542                                     &acrtc->dm_irq_params.vrr_params);
 543
 544                                 dc_stream_adjust_vmin_vmax(
 545                                     adev->dm.dc,
 546                                     acrtc->dm_irq_params.stream,
 547                                     &acrtc->dm_irq_params.vrr_params.adjust);
 548                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 549                         }
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * dm_crtc_high_irq() - Handles CRTC interrupt
 556  * @interrupt_params: used for determining the CRTC instance
 557  *
 558  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 559  * event handler.
 560  */
 561 static void dm_crtc_high_irq(void *interrupt_params)
 562 {
 563         struct common_irq_params *irq_params = interrupt_params;
 564         struct amdgpu_device *adev = irq_params->adev;
 565         struct amdgpu_crtc *acrtc;
 566         unsigned long flags;
 567         int vrr_active;
 568
 569         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 570         if (!acrtc)
 571                 return;
 572
 573         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 574
 575         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 576                       vrr_active, acrtc->dm_irq_params.active_planes);
 577
 578         /**
 579          * Core vblank handling at start of front-porch is only possible
 580          * in non-vrr mode, as only there vblank timestamping will give
 581          * valid results while done in front-porch. Otherwise defer it
 582          * to dm_vupdate_high_irq after end of front-porch.
 583          */
 584         if (!vrr_active)
 585                 amdgpu_dm_crtc_handle_vblank(acrtc);
 586
 587         /**
 588          * Following stuff must happen at start of vblank, for crc
 589          * computation and below-the-range btr support in vrr mode.
 590          */
 591         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 592
 593         /* BTR updates need to happen before VUPDATE on Vega and above. */
 594         if (adev->family < AMDGPU_FAMILY_AI)
 595                 return;
 596
 597         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 598
 599         if (acrtc->dm_irq_params.stream &&
 600             acrtc->dm_irq_params.vrr_params.supported &&
 601             acrtc->dm_irq_params.freesync_config.state ==
 602                     VRR_STATE_ACTIVE_VARIABLE) {
 603                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 604                                              acrtc->dm_irq_params.stream,
 605                                              &acrtc->dm_irq_params.vrr_params);
 606
 607                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 608                                            &acrtc->dm_irq_params.vrr_params.adjust);
 609         }
 610
 611         /*
 612          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 613          * In that case, pageflip completion interrupts won't fire and pageflip
 614          * completion events won't get delivered. Prevent this by sending
 615          * pending pageflip events from here if a flip is still pending.
 616          *
 617          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 618          * avoid race conditions between flip programming and completion,
 619          * which could cause too early flip completion events.
 620          */
 621         if (adev->family >= AMDGPU_FAMILY_RV &&
 622             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 623             acrtc->dm_irq_params.active_planes == 0) {
 624                 if (acrtc->event) {
 625                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 626                         acrtc->event = NULL;
 627                         drm_crtc_vblank_put(&acrtc->base);
 628                 }
 629                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 630         }
 631
 632         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 633 }
 634
 635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 636 /**
 637  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 638  * DCN generation ASICs
 639  * @interrupt_params: interrupt parameters
 640  *
 641  * Used to set crc window/read out crc value at vertical line 0 position
 642  */
 643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 644 {
 645         struct common_irq_params *irq_params = interrupt_params;
 646         struct amdgpu_device *adev = irq_params->adev;
 647         struct amdgpu_crtc *acrtc;
 648
 649         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 650
 651         if (!acrtc)
 652                 return;
 653
 654         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 655 }
 656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 657
 658 /**
 659  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 660  * @adev: amdgpu_device pointer
 661  * @notify: dmub notification structure
 662  *
 663  * Dmub AUX or SET_CONFIG command completion processing callback
 664  * Copies dmub notification to DM which is to be read by AUX command.
 665  * issuing thread and also signals the event to wake up the thread.
 666  */
 667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 668                                         struct dmub_notification *notify)
 669 {
 670         if (adev->dm.dmub_notify)
 671                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 672         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 673                 complete(&adev->dm.dmub_aux_transfer_done);
 674 }
 675
 676 /**
 677  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 678  * @adev: amdgpu_device pointer
 679  * @notify: dmub notification structure
 680  *
 681  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 682  * ink index and calls helper to do the processing.
 683  */
 684 static void dmub_hpd_callback(struct amdgpu_device *adev,
 685                               struct dmub_notification *notify)
 686 {
 687         struct amdgpu_dm_connector *aconnector;
 688         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 689         struct drm_connector *connector;
 690         struct drm_connector_list_iter iter;
 691         struct dc_link *link;
 692         u8 link_index = 0;
 693         struct drm_device *dev;
 694
 695         if (adev == NULL)
 696                 return;
 697
 698         if (notify == NULL) {
 699                 DRM_ERROR("DMUB HPD callback notification was NULL");
 700                 return;
 701         }
 702
 703         if (notify->link_index > adev->dm.dc->link_count) {
 704                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 705                 return;
 706         }
 707
 708         link_index = notify->link_index;
 709         link = adev->dm.dc->links[link_index];
 710         dev = adev->dm.ddev;
 711
 712         drm_connector_list_iter_begin(dev, &iter);
 713         drm_for_each_connector_iter(connector, &iter) {
 714                 aconnector = to_amdgpu_dm_connector(connector);
 715                 if (link && aconnector->dc_link == link) {
 716                         DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 717                         hpd_aconnector = aconnector;
 718                         break;
 719                 }
 720         }
 721         drm_connector_list_iter_end(&iter);
 722
 723         if (hpd_aconnector) {
 724                 if (notify->type == DMUB_NOTIFICATION_HPD)
 725                         handle_hpd_irq_helper(hpd_aconnector);
 726                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 727                         handle_hpd_rx_irq(hpd_aconnector);
 728         }
 729 }
 730
 731 /**
 732  * register_dmub_notify_callback - Sets callback for DMUB notify
 733  * @adev: amdgpu_device pointer
 734  * @type: Type of dmub notification
 735  * @callback: Dmub interrupt callback function
 736  * @dmub_int_thread_offload: offload indicator
 737  *
 738  * API to register a dmub callback handler for a dmub notification
 739  * Also sets indicator whether callback processing to be offloaded.
 740  * to dmub interrupt handling thread
 741  * Return: true if successfully registered, false if there is existing registration
 742  */
 743 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 744                                           enum dmub_notification_type type,
 745                                           dmub_notify_interrupt_callback_t callback,
 746                                           bool dmub_int_thread_offload)
 747 {
 748         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 749                 adev->dm.dmub_callback[type] = callback;
 750                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 751         } else
 752                 return false;
 753
 754         return true;
 755 }
 756
 757 static void dm_handle_hpd_work(struct work_struct *work)
 758 {
 759         struct dmub_hpd_work *dmub_hpd_wrk;
 760
 761         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 762
 763         if (!dmub_hpd_wrk->dmub_notify) {
 764                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 765                 return;
 766         }
 767
 768         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 769                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 770                 dmub_hpd_wrk->dmub_notify);
 771         }
 772
 773         kfree(dmub_hpd_wrk->dmub_notify);
 774         kfree(dmub_hpd_wrk);
 775
 776 }
 777
 778 #define DMUB_TRACE_MAX_READ 64
 779 /**
 780  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 781  * @interrupt_params: used for determining the Outbox instance
 782  *
 783  * Handles the Outbox Interrupt
 784  * event handler.
 785  */
 786 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 787 {
 788         struct dmub_notification notify;
 789         struct common_irq_params *irq_params = interrupt_params;
 790         struct amdgpu_device *adev = irq_params->adev;
 791         struct amdgpu_display_manager *dm = &adev->dm;
 792         struct dmcub_trace_buf_entry entry = { 0 };
 793         u32 count = 0;
 794         struct dmub_hpd_work *dmub_hpd_wrk;
 795         struct dc_link *plink = NULL;
 796
 797         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 798                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 799
 800                 do {
 801                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 802                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 803                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 804                                 continue;
 805                         }
 806                         if (!dm->dmub_callback[notify.type]) {
 807                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 808                                 continue;
 809                         }
 810                         if (dm->dmub_thread_offload[notify.type] == true) {
 811                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 812                                 if (!dmub_hpd_wrk) {
 813                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 814                                         return;
 815                                 }
 816                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 817                                 if (!dmub_hpd_wrk->dmub_notify) {
 818                                         kfree(dmub_hpd_wrk);
 819                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 820                                         return;
 821                                 }
 822                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 823                                 if (dmub_hpd_wrk->dmub_notify)
 824                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 825                                 dmub_hpd_wrk->adev = adev;
 826                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 827                                         plink = adev->dm.dc->links[notify.link_index];
 828                                         if (plink) {
 829                                                 plink->hpd_status =
 830                                                         notify.hpd_status == DP_HPD_PLUG;
 831                                         }
 832                                 }
 833                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 834                         } else {
 835                                 dm->dmub_callback[notify.type](adev, &notify);
 836                         }
 837                 } while (notify.pending_notification);
 838         }
 839
 840
 841         do {
 842                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 843                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 844                                                         entry.param0, entry.param1);
 845
 846                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 847                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 848                 } else
 849                         break;
 850
 851                 count++;
 852
 853         } while (count <= DMUB_TRACE_MAX_READ);
 854
 855         if (count > DMUB_TRACE_MAX_READ)
 856                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 857 }
 858
 859 static int dm_set_clockgating_state(void *handle,
 860                   enum amd_clockgating_state state)
 861 {
 862         return 0;
 863 }
 864
 865 static int dm_set_powergating_state(void *handle,
 866                   enum amd_powergating_state state)
 867 {
 868         return 0;
 869 }
 870
 871 /* Prototypes of private functions */
 872 static int dm_early_init(void* handle);
 873
 874 /* Allocate memory for FBC compressed data  */
 875 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 876 {
 877         struct drm_device *dev = connector->dev;
 878         struct amdgpu_device *adev = drm_to_adev(dev);
 879         struct dm_compressor_info *compressor = &adev->dm.compressor;
 880         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 881         struct drm_display_mode *mode;
 882         unsigned long max_size = 0;
 883
 884         if (adev->dm.dc->fbc_compressor == NULL)
 885                 return;
 886
 887         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 888                 return;
 889
 890         if (compressor->bo_ptr)
 891                 return;
 892
 893
 894         list_for_each_entry(mode, &connector->modes, head) {
 895                 if (max_size < mode->htotal * mode->vtotal)
 896                         max_size = mode->htotal * mode->vtotal;
 897         }
 898
 899         if (max_size) {
 900                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 901                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 902                             &compressor->gpu_addr, &compressor->cpu_addr);
 903
 904                 if (r)
 905                         DRM_ERROR("DM: Failed to initialize FBC\n");
 906                 else {
 907                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 908                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 909                 }
 910
 911         }
 912
 913 }
 914
 915 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 916                                           int pipe, bool *enabled,
 917                                           unsigned char *buf, int max_bytes)
 918 {
 919         struct drm_device *dev = dev_get_drvdata(kdev);
 920         struct amdgpu_device *adev = drm_to_adev(dev);
 921         struct drm_connector *connector;
 922         struct drm_connector_list_iter conn_iter;
 923         struct amdgpu_dm_connector *aconnector;
 924         int ret = 0;
 925
 926         *enabled = false;
 927
 928         mutex_lock(&adev->dm.audio_lock);
 929
 930         drm_connector_list_iter_begin(dev, &conn_iter);
 931         drm_for_each_connector_iter(connector, &conn_iter) {
 932                 aconnector = to_amdgpu_dm_connector(connector);
 933                 if (aconnector->audio_inst != port)
 934                         continue;
 935
 936                 *enabled = true;
 937                 ret = drm_eld_size(connector->eld);
 938                 memcpy(buf, connector->eld, min(max_bytes, ret));
 939
 940                 break;
 941         }
 942         drm_connector_list_iter_end(&conn_iter);
 943
 944         mutex_unlock(&adev->dm.audio_lock);
 945
 946         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 947
 948         return ret;
 949 }
 950
 951 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 952         .get_eld = amdgpu_dm_audio_component_get_eld,
 953 };
 954
 955 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 956                                        struct device *hda_kdev, void *data)
 957 {
 958         struct drm_device *dev = dev_get_drvdata(kdev);
 959         struct amdgpu_device *adev = drm_to_adev(dev);
 960         struct drm_audio_component *acomp = data;
 961
 962         acomp->ops = &amdgpu_dm_audio_component_ops;
 963         acomp->dev = kdev;
 964         adev->dm.audio_component = acomp;
 965
 966         return 0;
 967 }
 968
 969 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 970                                           struct device *hda_kdev, void *data)
 971 {
 972         struct drm_device *dev = dev_get_drvdata(kdev);
 973         struct amdgpu_device *adev = drm_to_adev(dev);
 974         struct drm_audio_component *acomp = data;
 975
 976         acomp->ops = NULL;
 977         acomp->dev = NULL;
 978         adev->dm.audio_component = NULL;
 979 }
 980
 981 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 982         .bind   = amdgpu_dm_audio_component_bind,
 983         .unbind = amdgpu_dm_audio_component_unbind,
 984 };
 985
 986 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 987 {
 988         int i, ret;
 989
 990         if (!amdgpu_audio)
 991                 return 0;
 992
 993         adev->mode_info.audio.enabled = true;
 994
 995         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 996
 997         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 998                 adev->mode_info.audio.pin[i].channels = -1;
 999                 adev->mode_info.audio.pin[i].rate = -1;
1000                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1001                 adev->mode_info.audio.pin[i].status_bits = 0;
1002                 adev->mode_info.audio.pin[i].category_code = 0;
1003                 adev->mode_info.audio.pin[i].connected = false;
1004                 adev->mode_info.audio.pin[i].id =
1005                         adev->dm.dc->res_pool->audios[i]->inst;
1006                 adev->mode_info.audio.pin[i].offset = 0;
1007         }
1008
1009         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1010         if (ret < 0)
1011                 return ret;
1012
1013         adev->dm.audio_registered = true;
1014
1015         return 0;
1016 }
1017
1018 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1019 {
1020         if (!amdgpu_audio)
1021                 return;
1022
1023         if (!adev->mode_info.audio.enabled)
1024                 return;
1025
1026         if (adev->dm.audio_registered) {
1027                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1028                 adev->dm.audio_registered = false;
1029         }
1030
1031         /* TODO: Disable audio? */
1032
1033         adev->mode_info.audio.enabled = false;
1034 }
1035
1036 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1037 {
1038         struct drm_audio_component *acomp = adev->dm.audio_component;
1039
1040         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1041                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1042
1043                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1044                                                  pin, -1);
1045         }
1046 }
1047
1048 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1049 {
1050         const struct dmcub_firmware_header_v1_0 *hdr;
1051         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1052         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1053         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1054         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1055         struct abm *abm = adev->dm.dc->res_pool->abm;
1056         struct dmub_srv_hw_params hw_params;
1057         enum dmub_status status;
1058         const unsigned char *fw_inst_const, *fw_bss_data;
1059         u32 i, fw_inst_const_size, fw_bss_data_size;
1060         bool has_hw_support;
1061
1062         if (!dmub_srv)
1063                 /* DMUB isn't supported on the ASIC. */
1064                 return 0;
1065
1066         if (!fb_info) {
1067                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1068                 return -EINVAL;
1069         }
1070
1071         if (!dmub_fw) {
1072                 /* Firmware required for DMUB support. */
1073                 DRM_ERROR("No firmware provided for DMUB.\n");
1074                 return -EINVAL;
1075         }
1076
1077         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1078         if (status != DMUB_STATUS_OK) {
1079                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1080                 return -EINVAL;
1081         }
1082
1083         if (!has_hw_support) {
1084                 DRM_INFO("DMUB unsupported on ASIC\n");
1085                 return 0;
1086         }
1087
1088         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1089         status = dmub_srv_hw_reset(dmub_srv);
1090         if (status != DMUB_STATUS_OK)
1091                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1092
1093         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1094
1095         fw_inst_const = dmub_fw->data +
1096                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1097                         PSP_HEADER_BYTES;
1098
1099         fw_bss_data = dmub_fw->data +
1100                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1101                       le32_to_cpu(hdr->inst_const_bytes);
1102
1103         /* Copy firmware and bios info into FB memory. */
1104         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1105                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1106
1107         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1108
1109         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1110          * amdgpu_ucode_init_single_fw will load dmub firmware
1111          * fw_inst_const part to cw0; otherwise, the firmware back door load
1112          * will be done by dm_dmub_hw_init
1113          */
1114         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1115                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1116                                 fw_inst_const_size);
1117         }
1118
1119         if (fw_bss_data_size)
1120                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1121                        fw_bss_data, fw_bss_data_size);
1122
1123         /* Copy firmware bios info into FB memory. */
1124         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1125                adev->bios_size);
1126
1127         /* Reset regions that need to be reset. */
1128         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1129         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1130
1131         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1132                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1133
1134         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1135                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1136
1137         /* Initialize hardware. */
1138         memset(&hw_params, 0, sizeof(hw_params));
1139         hw_params.fb_base = adev->gmc.fb_start;
1140         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1141
1142         /* backdoor load firmware and trigger dmub running */
1143         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1144                 hw_params.load_inst_const = true;
1145
1146         if (dmcu)
1147                 hw_params.psp_version = dmcu->psp_version;
1148
1149         for (i = 0; i < fb_info->num_fb; ++i)
1150                 hw_params.fb[i] = &fb_info->fb[i];
1151
1152         switch (adev->ip_versions[DCE_HWIP][0]) {
1153         case IP_VERSION(3, 1, 3):
1154         case IP_VERSION(3, 1, 4):
1155                 hw_params.dpia_supported = true;
1156                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1157                 break;
1158         default:
1159                 break;
1160         }
1161
1162         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1163         if (status != DMUB_STATUS_OK) {
1164                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1165                 return -EINVAL;
1166         }
1167
1168         /* Wait for firmware load to finish. */
1169         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1170         if (status != DMUB_STATUS_OK)
1171                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1172
1173         /* Init DMCU and ABM if available. */
1174         if (dmcu && abm) {
1175                 dmcu->funcs->dmcu_init(dmcu);
1176                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1177         }
1178
1179         if (!adev->dm.dc->ctx->dmub_srv)
1180                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1181         if (!adev->dm.dc->ctx->dmub_srv) {
1182                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1183                 return -ENOMEM;
1184         }
1185
1186         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1187                  adev->dm.dmcub_fw_version);
1188
1189         return 0;
1190 }
1191
1192 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1193 {
1194         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1195         enum dmub_status status;
1196         bool init;
1197
1198         if (!dmub_srv) {
1199                 /* DMUB isn't supported on the ASIC. */
1200                 return;
1201         }
1202
1203         status = dmub_srv_is_hw_init(dmub_srv, &init);
1204         if (status != DMUB_STATUS_OK)
1205                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1206
1207         if (status == DMUB_STATUS_OK && init) {
1208                 /* Wait for firmware load to finish. */
1209                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1210                 if (status != DMUB_STATUS_OK)
1211                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1212         } else {
1213                 /* Perform the full hardware initialization. */
1214                 dm_dmub_hw_init(adev);
1215         }
1216 }
1217
1218 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1219 {
1220         u64 pt_base;
1221         u32 logical_addr_low;
1222         u32 logical_addr_high;
1223         u32 agp_base, agp_bot, agp_top;
1224         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1225
1226         memset(pa_config, 0, sizeof(*pa_config));
1227
1228         agp_base = 0;
1229         agp_bot = adev->gmc.agp_start >> 24;
1230         agp_top = adev->gmc.agp_end >> 24;
1231
1232         /* AGP aperture is disabled */
1233         if (agp_bot == agp_top) {
1234                 logical_addr_low = adev->gmc.fb_start >> 18;
1235                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1236                         /*
1237                          * Raven2 has a HW issue that it is unable to use the vram which
1238                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1239                          * workaround that increase system aperture high address (add 1)
1240                          * to get rid of the VM fault and hardware hang.
1241                          */
1242                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1243                 else
1244                         logical_addr_high = adev->gmc.fb_end >> 18;
1245         } else {
1246                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1247                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1248                         /*
1249                          * Raven2 has a HW issue that it is unable to use the vram which
1250                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1251                          * workaround that increase system aperture high address (add 1)
1252                          * to get rid of the VM fault and hardware hang.
1253                          */
1254                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1255                 else
1256                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1257         }
1258
1259         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1260
1261         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1262         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1263         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1264         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1265         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1266         page_table_base.low_part = lower_32_bits(pt_base);
1267
1268         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1269         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1270
1271         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1272         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1273         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1274
1275         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1276         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1277         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1278
1279         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1280         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1281         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1282
1283         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1284
1285 }
1286
1287 static void force_connector_state(
1288         struct amdgpu_dm_connector *aconnector,
1289         enum drm_connector_force force_state)
1290 {
1291         struct drm_connector *connector = &aconnector->base;
1292
1293         mutex_lock(&connector->dev->mode_config.mutex);
1294         aconnector->base.force = force_state;
1295         mutex_unlock(&connector->dev->mode_config.mutex);
1296
1297         mutex_lock(&aconnector->hpd_lock);
1298         drm_kms_helper_connector_hotplug_event(connector);
1299         mutex_unlock(&aconnector->hpd_lock);
1300 }
1301
1302 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1303 {
1304         struct hpd_rx_irq_offload_work *offload_work;
1305         struct amdgpu_dm_connector *aconnector;
1306         struct dc_link *dc_link;
1307         struct amdgpu_device *adev;
1308         enum dc_connection_type new_connection_type = dc_connection_none;
1309         unsigned long flags;
1310         union test_response test_response;
1311
1312         memset(&test_response, 0, sizeof(test_response));
1313
1314         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1315         aconnector = offload_work->offload_wq->aconnector;
1316
1317         if (!aconnector) {
1318                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1319                 goto skip;
1320         }
1321
1322         adev = drm_to_adev(aconnector->base.dev);
1323         dc_link = aconnector->dc_link;
1324
1325         mutex_lock(&aconnector->hpd_lock);
1326         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1327                 DRM_ERROR("KMS: Failed to detect connector\n");
1328         mutex_unlock(&aconnector->hpd_lock);
1329
1330         if (new_connection_type == dc_connection_none)
1331                 goto skip;
1332
1333         if (amdgpu_in_reset(adev))
1334                 goto skip;
1335
1336         mutex_lock(&adev->dm.dc_lock);
1337         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1338                 dc_link_dp_handle_automated_test(dc_link);
1339
1340                 if (aconnector->timing_changed) {
1341                         /* force connector disconnect and reconnect */
1342                         force_connector_state(aconnector, DRM_FORCE_OFF);
1343                         msleep(100);
1344                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1345                 }
1346
1347                 test_response.bits.ACK = 1;
1348
1349                 core_link_write_dpcd(
1350                 dc_link,
1351                 DP_TEST_RESPONSE,
1352                 &test_response.raw,
1353                 sizeof(test_response));
1354         }
1355         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1356                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1357                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1358                 /* offload_work->data is from handle_hpd_rx_irq->
1359                  * schedule_hpd_rx_offload_work.this is defer handle
1360                  * for hpd short pulse. upon here, link status may be
1361                  * changed, need get latest link status from dpcd
1362                  * registers. if link status is good, skip run link
1363                  * training again.
1364                  */
1365                 union hpd_irq_data irq_data;
1366
1367                 memset(&irq_data, 0, sizeof(irq_data));
1368
1369                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1370                  * request be added to work queue if link lost at end of dc_link_
1371                  * dp_handle_link_loss
1372                  */
1373                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1374                 offload_work->offload_wq->is_handling_link_loss = false;
1375                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1376
1377                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1378                         dc_link_check_link_loss_status(dc_link, &irq_data))
1379                         dc_link_dp_handle_link_loss(dc_link);
1380         }
1381         mutex_unlock(&adev->dm.dc_lock);
1382
1383 skip:
1384         kfree(offload_work);
1385
1386 }
1387
1388 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1389 {
1390         int max_caps = dc->caps.max_links;
1391         int i = 0;
1392         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1393
1394         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1395
1396         if (!hpd_rx_offload_wq)
1397                 return NULL;
1398
1399
1400         for (i = 0; i < max_caps; i++) {
1401                 hpd_rx_offload_wq[i].wq =
1402                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1403
1404                 if (hpd_rx_offload_wq[i].wq == NULL) {
1405                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1406                         goto out_err;
1407                 }
1408
1409                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1410         }
1411
1412         return hpd_rx_offload_wq;
1413
1414 out_err:
1415         for (i = 0; i < max_caps; i++) {
1416                 if (hpd_rx_offload_wq[i].wq)
1417                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1418         }
1419         kfree(hpd_rx_offload_wq);
1420         return NULL;
1421 }
1422
1423 struct amdgpu_stutter_quirk {
1424         u16 chip_vendor;
1425         u16 chip_device;
1426         u16 subsys_vendor;
1427         u16 subsys_device;
1428         u8 revision;
1429 };
1430
1431 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1432         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1433         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1434         { 0, 0, 0, 0, 0 },
1435 };
1436
1437 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1438 {
1439         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1440
1441         while (p && p->chip_device != 0) {
1442                 if (pdev->vendor == p->chip_vendor &&
1443                     pdev->device == p->chip_device &&
1444                     pdev->subsystem_vendor == p->subsys_vendor &&
1445                     pdev->subsystem_device == p->subsys_device &&
1446                     pdev->revision == p->revision) {
1447                         return true;
1448                 }
1449                 ++p;
1450         }
1451         return false;
1452 }
1453
1454 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1455         {
1456                 .matches = {
1457                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1458                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1459                 },
1460         },
1461         {
1462                 .matches = {
1463                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1465                 },
1466         },
1467         {
1468                 .matches = {
1469                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1471                 },
1472         },
1473         {
1474                 .matches = {
1475                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1477                 },
1478         },
1479         {
1480                 .matches = {
1481                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1483                 },
1484         },
1485         {
1486                 .matches = {
1487                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1489                 },
1490         },
1491         {
1492                 .matches = {
1493                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1495                 },
1496         },
1497         {
1498                 .matches = {
1499                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1501                 },
1502         },
1503         {
1504                 .matches = {
1505                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1507                 },
1508         },
1509         {}
1510         /* TODO: refactor this from a fixed table to a dynamic option */
1511 };
1512
1513 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1514 {
1515         const struct dmi_system_id *dmi_id;
1516
1517         dm->aux_hpd_discon_quirk = false;
1518
1519         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1520         if (dmi_id) {
1521                 dm->aux_hpd_discon_quirk = true;
1522                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1523         }
1524 }
1525
1526 static int amdgpu_dm_init(struct amdgpu_device *adev)
1527 {
1528         struct dc_init_data init_data;
1529         struct dc_callback_init init_params;
1530         int r;
1531
1532         adev->dm.ddev = adev_to_drm(adev);
1533         adev->dm.adev = adev;
1534
1535         /* Zero all the fields */
1536         memset(&init_data, 0, sizeof(init_data));
1537         memset(&init_params, 0, sizeof(init_params));
1538
1539         mutex_init(&adev->dm.dpia_aux_lock);
1540         mutex_init(&adev->dm.dc_lock);
1541         mutex_init(&adev->dm.audio_lock);
1542
1543         if(amdgpu_dm_irq_init(adev)) {
1544                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1545                 goto error;
1546         }
1547
1548         init_data.asic_id.chip_family = adev->family;
1549
1550         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1551         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1552         init_data.asic_id.chip_id = adev->pdev->device;
1553
1554         init_data.asic_id.vram_width = adev->gmc.vram_width;
1555         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1556         init_data.asic_id.atombios_base_address =
1557                 adev->mode_info.atom_context->bios;
1558
1559         init_data.driver = adev;
1560
1561         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1562
1563         if (!adev->dm.cgs_device) {
1564                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1565                 goto error;
1566         }
1567
1568         init_data.cgs_device = adev->dm.cgs_device;
1569
1570         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1571
1572         switch (adev->ip_versions[DCE_HWIP][0]) {
1573         case IP_VERSION(2, 1, 0):
1574                 switch (adev->dm.dmcub_fw_version) {
1575                 case 0: /* development */
1576                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1577                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1578                         init_data.flags.disable_dmcu = false;
1579                         break;
1580                 default:
1581                         init_data.flags.disable_dmcu = true;
1582                 }
1583                 break;
1584         case IP_VERSION(2, 0, 3):
1585                 init_data.flags.disable_dmcu = true;
1586                 break;
1587         default:
1588                 break;
1589         }
1590
1591         switch (adev->asic_type) {
1592         case CHIP_CARRIZO:
1593         case CHIP_STONEY:
1594                 init_data.flags.gpu_vm_support = true;
1595                 break;
1596         default:
1597                 switch (adev->ip_versions[DCE_HWIP][0]) {
1598                 case IP_VERSION(1, 0, 0):
1599                 case IP_VERSION(1, 0, 1):
1600                         /* enable S/G on PCO and RV2 */
1601                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1602                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1603                                 init_data.flags.gpu_vm_support = true;
1604                         break;
1605                 case IP_VERSION(2, 1, 0):
1606                 case IP_VERSION(3, 0, 1):
1607                 case IP_VERSION(3, 1, 2):
1608                 case IP_VERSION(3, 1, 3):
1609                 case IP_VERSION(3, 1, 4):
1610                 case IP_VERSION(3, 1, 5):
1611                 case IP_VERSION(3, 1, 6):
1612                         init_data.flags.gpu_vm_support = true;
1613                         break;
1614                 default:
1615                         break;
1616                 }
1617                 break;
1618         }
1619         if (init_data.flags.gpu_vm_support &&
1620             (amdgpu_sg_display == 0))
1621                 init_data.flags.gpu_vm_support = false;
1622
1623         if (init_data.flags.gpu_vm_support)
1624                 adev->mode_info.gpu_vm_support = true;
1625
1626         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1627                 init_data.flags.fbc_support = true;
1628
1629         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1630                 init_data.flags.multi_mon_pp_mclk_switch = true;
1631
1632         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1633                 init_data.flags.disable_fractional_pwm = true;
1634
1635         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1636                 init_data.flags.edp_no_power_sequencing = true;
1637
1638         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1639                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1640         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1641                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1642
1643         /* Disable SubVP + DRR config by default */
1644         init_data.flags.disable_subvp_drr = true;
1645         if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1646                 init_data.flags.disable_subvp_drr = false;
1647
1648         init_data.flags.seamless_boot_edp_requested = false;
1649
1650         if (check_seamless_boot_capability(adev)) {
1651                 init_data.flags.seamless_boot_edp_requested = true;
1652                 init_data.flags.allow_seamless_boot_optimization = true;
1653                 DRM_INFO("Seamless boot condition check passed\n");
1654         }
1655
1656         init_data.flags.enable_mipi_converter_optimization = true;
1657
1658         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1659         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1660
1661         INIT_LIST_HEAD(&adev->dm.da_list);
1662
1663         retrieve_dmi_info(&adev->dm);
1664
1665         /* Display Core create. */
1666         adev->dm.dc = dc_create(&init_data);
1667
1668         if (adev->dm.dc) {
1669                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1670         } else {
1671                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1672                 goto error;
1673         }
1674
1675         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1676                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1677                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1678         }
1679
1680         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1681                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1682         if (dm_should_disable_stutter(adev->pdev))
1683                 adev->dm.dc->debug.disable_stutter = true;
1684
1685         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1686                 adev->dm.dc->debug.disable_stutter = true;
1687
1688         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1689                 adev->dm.dc->debug.disable_dsc = true;
1690         }
1691
1692         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1693                 adev->dm.dc->debug.disable_clock_gate = true;
1694
1695         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1696                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1697
1698         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1699
1700         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1701         adev->dm.dc->debug.ignore_cable_id = true;
1702
1703         /* TODO: There is a new drm mst change where the freedom of
1704          * vc_next_start_slot update is revoked/moved into drm, instead of in
1705          * driver. This forces us to make sure to get vc_next_start_slot updated
1706          * in drm function each time without considering if mst_state is active
1707          * or not. Otherwise, next time hotplug will give wrong start_slot
1708          * number. We are implementing a temporary solution to even notify drm
1709          * mst deallocation when link is no longer of MST type when uncommitting
1710          * the stream so we will have more time to work on a proper solution.
1711          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1712          * should notify drm to do a complete "reset" of its states and stop
1713          * calling further drm mst functions when link is no longer of an MST
1714          * type. This could happen when we unplug an MST hubs/displays. When
1715          * uncommit stream comes later after unplug, we should just reset
1716          * hardware states only.
1717          */
1718         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1719
1720         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1721                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1722
1723         r = dm_dmub_hw_init(adev);
1724         if (r) {
1725                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1726                 goto error;
1727         }
1728
1729         dc_hardware_init(adev->dm.dc);
1730
1731         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1732         if (!adev->dm.hpd_rx_offload_wq) {
1733                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1734                 goto error;
1735         }
1736
1737         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1738                 struct dc_phy_addr_space_config pa_config;
1739
1740                 mmhub_read_system_context(adev, &pa_config);
1741
1742                 // Call the DC init_memory func
1743                 dc_setup_system_context(adev->dm.dc, &pa_config);
1744         }
1745
1746         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1747         if (!adev->dm.freesync_module) {
1748                 DRM_ERROR(
1749                 "amdgpu: failed to initialize freesync_module.\n");
1750         } else
1751                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1752                                 adev->dm.freesync_module);
1753
1754         amdgpu_dm_init_color_mod();
1755
1756         if (adev->dm.dc->caps.max_links > 0) {
1757                 adev->dm.vblank_control_workqueue =
1758                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1759                 if (!adev->dm.vblank_control_workqueue)
1760                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1761         }
1762
1763         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1764                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1765
1766                 if (!adev->dm.hdcp_workqueue)
1767                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1768                 else
1769                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1770
1771                 dc_init_callbacks(adev->dm.dc, &init_params);
1772         }
1773 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1774         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1775         if (!adev->dm.secure_display_ctxs) {
1776                 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1777         }
1778 #endif
1779         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1780                 init_completion(&adev->dm.dmub_aux_transfer_done);
1781                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1782                 if (!adev->dm.dmub_notify) {
1783                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1784                         goto error;
1785                 }
1786
1787                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1788                 if (!adev->dm.delayed_hpd_wq) {
1789                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1790                         goto error;
1791                 }
1792
1793                 amdgpu_dm_outbox_init(adev);
1794                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1795                         dmub_aux_setconfig_callback, false)) {
1796                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1797                         goto error;
1798                 }
1799                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1800                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1801                         goto error;
1802                 }
1803                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1804                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1805                         goto error;
1806                 }
1807         }
1808
1809         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1810          * It is expected that DMUB will resend any pending notifications at this point, for
1811          * example HPD from DPIA.
1812          */
1813         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1814                 dc_enable_dmub_outbox(adev->dm.dc);
1815
1816         if (amdgpu_dm_initialize_drm_device(adev)) {
1817                 DRM_ERROR(
1818                 "amdgpu: failed to initialize sw for display support.\n");
1819                 goto error;
1820         }
1821
1822         /* create fake encoders for MST */
1823         dm_dp_create_fake_mst_encoders(adev);
1824
1825         /* TODO: Add_display_info? */
1826
1827         /* TODO use dynamic cursor width */
1828         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1829         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1830
1831         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1832                 DRM_ERROR(
1833                 "amdgpu: failed to initialize sw for display support.\n");
1834                 goto error;
1835         }
1836
1837
1838         DRM_DEBUG_DRIVER("KMS initialized.\n");
1839
1840         return 0;
1841 error:
1842         amdgpu_dm_fini(adev);
1843
1844         return -EINVAL;
1845 }
1846
1847 static int amdgpu_dm_early_fini(void *handle)
1848 {
1849         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1850
1851         amdgpu_dm_audio_fini(adev);
1852
1853         return 0;
1854 }
1855
1856 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1857 {
1858         int i;
1859
1860         if (adev->dm.vblank_control_workqueue) {
1861                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1862                 adev->dm.vblank_control_workqueue = NULL;
1863         }
1864
1865         amdgpu_dm_destroy_drm_device(&adev->dm);
1866
1867 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1868         if (adev->dm.secure_display_ctxs) {
1869                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1870                         if (adev->dm.secure_display_ctxs[i].crtc) {
1871                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1872                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1873                         }
1874                 }
1875                 kfree(adev->dm.secure_display_ctxs);
1876                 adev->dm.secure_display_ctxs = NULL;
1877         }
1878 #endif
1879         if (adev->dm.hdcp_workqueue) {
1880                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1881                 adev->dm.hdcp_workqueue = NULL;
1882         }
1883
1884         if (adev->dm.dc)
1885                 dc_deinit_callbacks(adev->dm.dc);
1886
1887         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1888
1889         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1890                 kfree(adev->dm.dmub_notify);
1891                 adev->dm.dmub_notify = NULL;
1892                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1893                 adev->dm.delayed_hpd_wq = NULL;
1894         }
1895
1896         if (adev->dm.dmub_bo)
1897                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1898                                       &adev->dm.dmub_bo_gpu_addr,
1899                                       &adev->dm.dmub_bo_cpu_addr);
1900
1901         if (adev->dm.hpd_rx_offload_wq) {
1902                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1903                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1904                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1905                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1906                         }
1907                 }
1908
1909                 kfree(adev->dm.hpd_rx_offload_wq);
1910                 adev->dm.hpd_rx_offload_wq = NULL;
1911         }
1912
1913         /* DC Destroy TODO: Replace destroy DAL */
1914         if (adev->dm.dc)
1915                 dc_destroy(&adev->dm.dc);
1916         /*
1917          * TODO: pageflip, vlank interrupt
1918          *
1919          * amdgpu_dm_irq_fini(adev);
1920          */
1921
1922         if (adev->dm.cgs_device) {
1923                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1924                 adev->dm.cgs_device = NULL;
1925         }
1926         if (adev->dm.freesync_module) {
1927                 mod_freesync_destroy(adev->dm.freesync_module);
1928                 adev->dm.freesync_module = NULL;
1929         }
1930
1931         mutex_destroy(&adev->dm.audio_lock);
1932         mutex_destroy(&adev->dm.dc_lock);
1933         mutex_destroy(&adev->dm.dpia_aux_lock);
1934
1935         return;
1936 }
1937
1938 static int load_dmcu_fw(struct amdgpu_device *adev)
1939 {
1940         const char *fw_name_dmcu = NULL;
1941         int r;
1942         const struct dmcu_firmware_header_v1_0 *hdr;
1943
1944         switch(adev->asic_type) {
1945 #if defined(CONFIG_DRM_AMD_DC_SI)
1946         case CHIP_TAHITI:
1947         case CHIP_PITCAIRN:
1948         case CHIP_VERDE:
1949         case CHIP_OLAND:
1950 #endif
1951         case CHIP_BONAIRE:
1952         case CHIP_HAWAII:
1953         case CHIP_KAVERI:
1954         case CHIP_KABINI:
1955         case CHIP_MULLINS:
1956         case CHIP_TONGA:
1957         case CHIP_FIJI:
1958         case CHIP_CARRIZO:
1959         case CHIP_STONEY:
1960         case CHIP_POLARIS11:
1961         case CHIP_POLARIS10:
1962         case CHIP_POLARIS12:
1963         case CHIP_VEGAM:
1964         case CHIP_VEGA10:
1965         case CHIP_VEGA12:
1966         case CHIP_VEGA20:
1967                 return 0;
1968         case CHIP_NAVI12:
1969                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1970                 break;
1971         case CHIP_RAVEN:
1972                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1973                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1974                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1975                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1976                 else
1977                         return 0;
1978                 break;
1979         default:
1980                 switch (adev->ip_versions[DCE_HWIP][0]) {
1981                 case IP_VERSION(2, 0, 2):
1982                 case IP_VERSION(2, 0, 3):
1983                 case IP_VERSION(2, 0, 0):
1984                 case IP_VERSION(2, 1, 0):
1985                 case IP_VERSION(3, 0, 0):
1986                 case IP_VERSION(3, 0, 2):
1987                 case IP_VERSION(3, 0, 3):
1988                 case IP_VERSION(3, 0, 1):
1989                 case IP_VERSION(3, 1, 2):
1990                 case IP_VERSION(3, 1, 3):
1991                 case IP_VERSION(3, 1, 4):
1992                 case IP_VERSION(3, 1, 5):
1993                 case IP_VERSION(3, 1, 6):
1994                 case IP_VERSION(3, 2, 0):
1995                 case IP_VERSION(3, 2, 1):
1996                         return 0;
1997                 default:
1998                         break;
1999                 }
2000                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2001                 return -EINVAL;
2002         }
2003
2004         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2005                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2006                 return 0;
2007         }
2008
2009         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2010         if (r == -ENODEV) {
2011                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2012                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2013                 adev->dm.fw_dmcu = NULL;
2014                 return 0;
2015         }
2016         if (r) {
2017                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2018                         fw_name_dmcu);
2019                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2020                 return r;
2021         }
2022
2023         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2024         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2025         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2026         adev->firmware.fw_size +=
2027                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2028
2029         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2030         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2031         adev->firmware.fw_size +=
2032                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2033
2034         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2035
2036         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2037
2038         return 0;
2039 }
2040
2041 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2042 {
2043         struct amdgpu_device *adev = ctx;
2044
2045         return dm_read_reg(adev->dm.dc->ctx, address);
2046 }
2047
2048 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2049                                      uint32_t value)
2050 {
2051         struct amdgpu_device *adev = ctx;
2052
2053         return dm_write_reg(adev->dm.dc->ctx, address, value);
2054 }
2055
2056 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2057 {
2058         struct dmub_srv_create_params create_params;
2059         struct dmub_srv_region_params region_params;
2060         struct dmub_srv_region_info region_info;
2061         struct dmub_srv_fb_params fb_params;
2062         struct dmub_srv_fb_info *fb_info;
2063         struct dmub_srv *dmub_srv;
2064         const struct dmcub_firmware_header_v1_0 *hdr;
2065         enum dmub_asic dmub_asic;
2066         enum dmub_status status;
2067         int r;
2068
2069         switch (adev->ip_versions[DCE_HWIP][0]) {
2070         case IP_VERSION(2, 1, 0):
2071                 dmub_asic = DMUB_ASIC_DCN21;
2072                 break;
2073         case IP_VERSION(3, 0, 0):
2074                 dmub_asic = DMUB_ASIC_DCN30;
2075                 break;
2076         case IP_VERSION(3, 0, 1):
2077                 dmub_asic = DMUB_ASIC_DCN301;
2078                 break;
2079         case IP_VERSION(3, 0, 2):
2080                 dmub_asic = DMUB_ASIC_DCN302;
2081                 break;
2082         case IP_VERSION(3, 0, 3):
2083                 dmub_asic = DMUB_ASIC_DCN303;
2084                 break;
2085         case IP_VERSION(3, 1, 2):
2086         case IP_VERSION(3, 1, 3):
2087                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2088                 break;
2089         case IP_VERSION(3, 1, 4):
2090                 dmub_asic = DMUB_ASIC_DCN314;
2091                 break;
2092         case IP_VERSION(3, 1, 5):
2093                 dmub_asic = DMUB_ASIC_DCN315;
2094                 break;
2095         case IP_VERSION(3, 1, 6):
2096                 dmub_asic = DMUB_ASIC_DCN316;
2097                 break;
2098         case IP_VERSION(3, 2, 0):
2099                 dmub_asic = DMUB_ASIC_DCN32;
2100                 break;
2101         case IP_VERSION(3, 2, 1):
2102                 dmub_asic = DMUB_ASIC_DCN321;
2103                 break;
2104         default:
2105                 /* ASIC doesn't support DMUB. */
2106                 return 0;
2107         }
2108
2109         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2110         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2111
2112         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2113                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2114                         AMDGPU_UCODE_ID_DMCUB;
2115                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2116                         adev->dm.dmub_fw;
2117                 adev->firmware.fw_size +=
2118                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2119
2120                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2121                          adev->dm.dmcub_fw_version);
2122         }
2123
2124
2125         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2126         dmub_srv = adev->dm.dmub_srv;
2127
2128         if (!dmub_srv) {
2129                 DRM_ERROR("Failed to allocate DMUB service!\n");
2130                 return -ENOMEM;
2131         }
2132
2133         memset(&create_params, 0, sizeof(create_params));
2134         create_params.user_ctx = adev;
2135         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2136         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2137         create_params.asic = dmub_asic;
2138
2139         /* Create the DMUB service. */
2140         status = dmub_srv_create(dmub_srv, &create_params);
2141         if (status != DMUB_STATUS_OK) {
2142                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2143                 return -EINVAL;
2144         }
2145
2146         /* Calculate the size of all the regions for the DMUB service. */
2147         memset(&region_params, 0, sizeof(region_params));
2148
2149         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2150                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2151         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2152         region_params.vbios_size = adev->bios_size;
2153         region_params.fw_bss_data = region_params.bss_data_size ?
2154                 adev->dm.dmub_fw->data +
2155                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2156                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2157         region_params.fw_inst_const =
2158                 adev->dm.dmub_fw->data +
2159                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2160                 PSP_HEADER_BYTES;
2161
2162         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2163                                            &region_info);
2164
2165         if (status != DMUB_STATUS_OK) {
2166                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2167                 return -EINVAL;
2168         }
2169
2170         /*
2171          * Allocate a framebuffer based on the total size of all the regions.
2172          * TODO: Move this into GART.
2173          */
2174         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2175                                     AMDGPU_GEM_DOMAIN_VRAM |
2176                                     AMDGPU_GEM_DOMAIN_GTT,
2177                                     &adev->dm.dmub_bo,
2178                                     &adev->dm.dmub_bo_gpu_addr,
2179                                     &adev->dm.dmub_bo_cpu_addr);
2180         if (r)
2181                 return r;
2182
2183         /* Rebase the regions on the framebuffer address. */
2184         memset(&fb_params, 0, sizeof(fb_params));
2185         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2186         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2187         fb_params.region_info = &region_info;
2188
2189         adev->dm.dmub_fb_info =
2190                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2191         fb_info = adev->dm.dmub_fb_info;
2192
2193         if (!fb_info) {
2194                 DRM_ERROR(
2195                         "Failed to allocate framebuffer info for DMUB service!\n");
2196                 return -ENOMEM;
2197         }
2198
2199         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2200         if (status != DMUB_STATUS_OK) {
2201                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2202                 return -EINVAL;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int dm_sw_init(void *handle)
2209 {
2210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2211         int r;
2212
2213         r = dm_dmub_sw_init(adev);
2214         if (r)
2215                 return r;
2216
2217         return load_dmcu_fw(adev);
2218 }
2219
2220 static int dm_sw_fini(void *handle)
2221 {
2222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2223
2224         kfree(adev->dm.dmub_fb_info);
2225         adev->dm.dmub_fb_info = NULL;
2226
2227         if (adev->dm.dmub_srv) {
2228                 dmub_srv_destroy(adev->dm.dmub_srv);
2229                 adev->dm.dmub_srv = NULL;
2230         }
2231
2232         amdgpu_ucode_release(&adev->dm.dmub_fw);
2233         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2234
2235         return 0;
2236 }
2237
2238 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2239 {
2240         struct amdgpu_dm_connector *aconnector;
2241         struct drm_connector *connector;
2242         struct drm_connector_list_iter iter;
2243         int ret = 0;
2244
2245         drm_connector_list_iter_begin(dev, &iter);
2246         drm_for_each_connector_iter(connector, &iter) {
2247                 aconnector = to_amdgpu_dm_connector(connector);
2248                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2249                     aconnector->mst_mgr.aux) {
2250                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2251                                          aconnector,
2252                                          aconnector->base.base.id);
2253
2254                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2255                         if (ret < 0) {
2256                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2257                                 aconnector->dc_link->type =
2258                                         dc_connection_single;
2259                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2260                                                                      aconnector->dc_link);
2261                                 break;
2262                         }
2263                 }
2264         }
2265         drm_connector_list_iter_end(&iter);
2266
2267         return ret;
2268 }
2269
2270 static int dm_late_init(void *handle)
2271 {
2272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2273
2274         struct dmcu_iram_parameters params;
2275         unsigned int linear_lut[16];
2276         int i;
2277         struct dmcu *dmcu = NULL;
2278
2279         dmcu = adev->dm.dc->res_pool->dmcu;
2280
2281         for (i = 0; i < 16; i++)
2282                 linear_lut[i] = 0xFFFF * i / 15;
2283
2284         params.set = 0;
2285         params.backlight_ramping_override = false;
2286         params.backlight_ramping_start = 0xCCCC;
2287         params.backlight_ramping_reduction = 0xCCCCCCCC;
2288         params.backlight_lut_array_size = 16;
2289         params.backlight_lut_array = linear_lut;
2290
2291         /* Min backlight level after ABM reduction,  Don't allow below 1%
2292          * 0xFFFF x 0.01 = 0x28F
2293          */
2294         params.min_abm_backlight = 0x28F;
2295         /* In the case where abm is implemented on dmcub,
2296         * dmcu object will be null.
2297         * ABM 2.4 and up are implemented on dmcub.
2298         */
2299         if (dmcu) {
2300                 if (!dmcu_load_iram(dmcu, params))
2301                         return -EINVAL;
2302         } else if (adev->dm.dc->ctx->dmub_srv) {
2303                 struct dc_link *edp_links[MAX_NUM_EDP];
2304                 int edp_num;
2305
2306                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2307                 for (i = 0; i < edp_num; i++) {
2308                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2309                                 return -EINVAL;
2310                 }
2311         }
2312
2313         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2314 }
2315
2316 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2317 {
2318         struct amdgpu_dm_connector *aconnector;
2319         struct drm_connector *connector;
2320         struct drm_connector_list_iter iter;
2321         struct drm_dp_mst_topology_mgr *mgr;
2322         int ret;
2323         bool need_hotplug = false;
2324
2325         drm_connector_list_iter_begin(dev, &iter);
2326         drm_for_each_connector_iter(connector, &iter) {
2327                 aconnector = to_amdgpu_dm_connector(connector);
2328                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2329                     aconnector->mst_root)
2330                         continue;
2331
2332                 mgr = &aconnector->mst_mgr;
2333
2334                 if (suspend) {
2335                         drm_dp_mst_topology_mgr_suspend(mgr);
2336                 } else {
2337                         /* if extended timeout is supported in hardware,
2338                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2339                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2340                          */
2341                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2342                         if (!dp_is_lttpr_present(aconnector->dc_link))
2343                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2344
2345                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2346                         if (ret < 0) {
2347                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2348                                         aconnector->dc_link);
2349                                 need_hotplug = true;
2350                         }
2351                 }
2352         }
2353         drm_connector_list_iter_end(&iter);
2354
2355         if (need_hotplug)
2356                 drm_kms_helper_hotplug_event(dev);
2357 }
2358
2359 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2360 {
2361         int ret = 0;
2362
2363         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2364          * on window driver dc implementation.
2365          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2366          * should be passed to smu during boot up and resume from s3.
2367          * boot up: dc calculate dcn watermark clock settings within dc_create,
2368          * dcn20_resource_construct
2369          * then call pplib functions below to pass the settings to smu:
2370          * smu_set_watermarks_for_clock_ranges
2371          * smu_set_watermarks_table
2372          * navi10_set_watermarks_table
2373          * smu_write_watermarks_table
2374          *
2375          * For Renoir, clock settings of dcn watermark are also fixed values.
2376          * dc has implemented different flow for window driver:
2377          * dc_hardware_init / dc_set_power_state
2378          * dcn10_init_hw
2379          * notify_wm_ranges
2380          * set_wm_ranges
2381          * -- Linux
2382          * smu_set_watermarks_for_clock_ranges
2383          * renoir_set_watermarks_table
2384          * smu_write_watermarks_table
2385          *
2386          * For Linux,
2387          * dc_hardware_init -> amdgpu_dm_init
2388          * dc_set_power_state --> dm_resume
2389          *
2390          * therefore, this function apply to navi10/12/14 but not Renoir
2391          * *
2392          */
2393         switch (adev->ip_versions[DCE_HWIP][0]) {
2394         case IP_VERSION(2, 0, 2):
2395         case IP_VERSION(2, 0, 0):
2396                 break;
2397         default:
2398                 return 0;
2399         }
2400
2401         ret = amdgpu_dpm_write_watermarks_table(adev);
2402         if (ret) {
2403                 DRM_ERROR("Failed to update WMTABLE!\n");
2404                 return ret;
2405         }
2406
2407         return 0;
2408 }
2409
2410 /**
2411  * dm_hw_init() - Initialize DC device
2412  * @handle: The base driver device containing the amdgpu_dm device.
2413  *
2414  * Initialize the &struct amdgpu_display_manager device. This involves calling
2415  * the initializers of each DM component, then populating the struct with them.
2416  *
2417  * Although the function implies hardware initialization, both hardware and
2418  * software are initialized here. Splitting them out to their relevant init
2419  * hooks is a future TODO item.
2420  *
2421  * Some notable things that are initialized here:
2422  *
2423  * - Display Core, both software and hardware
2424  * - DC modules that we need (freesync and color management)
2425  * - DRM software states
2426  * - Interrupt sources and handlers
2427  * - Vblank support
2428  * - Debug FS entries, if enabled
2429  */
2430 static int dm_hw_init(void *handle)
2431 {
2432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2433         /* Create DAL display manager */
2434         amdgpu_dm_init(adev);
2435         amdgpu_dm_hpd_init(adev);
2436
2437         return 0;
2438 }
2439
2440 /**
2441  * dm_hw_fini() - Teardown DC device
2442  * @handle: The base driver device containing the amdgpu_dm device.
2443  *
2444  * Teardown components within &struct amdgpu_display_manager that require
2445  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2446  * were loaded. Also flush IRQ workqueues and disable them.
2447  */
2448 static int dm_hw_fini(void *handle)
2449 {
2450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2451
2452         amdgpu_dm_hpd_fini(adev);
2453
2454         amdgpu_dm_irq_fini(adev);
2455         amdgpu_dm_fini(adev);
2456         return 0;
2457 }
2458
2459
2460 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2461                                  struct dc_state *state, bool enable)
2462 {
2463         enum dc_irq_source irq_source;
2464         struct amdgpu_crtc *acrtc;
2465         int rc = -EBUSY;
2466         int i = 0;
2467
2468         for (i = 0; i < state->stream_count; i++) {
2469                 acrtc = get_crtc_by_otg_inst(
2470                                 adev, state->stream_status[i].primary_otg_inst);
2471
2472                 if (acrtc && state->stream_status[i].plane_count != 0) {
2473                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2474                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2475                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2476                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2477                         if (rc)
2478                                 DRM_WARN("Failed to %s pflip interrupts\n",
2479                                          enable ? "enable" : "disable");
2480
2481                         if (enable) {
2482                                 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2483                                 if (rc)
2484                                         DRM_WARN("Failed to enable vblank interrupts\n");
2485                         } else {
2486                                 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2487                         }
2488
2489                 }
2490         }
2491
2492 }
2493
2494 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2495 {
2496         struct dc_state *context = NULL;
2497         enum dc_status res = DC_ERROR_UNEXPECTED;
2498         int i;
2499         struct dc_stream_state *del_streams[MAX_PIPES];
2500         int del_streams_count = 0;
2501
2502         memset(del_streams, 0, sizeof(del_streams));
2503
2504         context = dc_create_state(dc);
2505         if (context == NULL)
2506                 goto context_alloc_fail;
2507
2508         dc_resource_state_copy_construct_current(dc, context);
2509
2510         /* First remove from context all streams */
2511         for (i = 0; i < context->stream_count; i++) {
2512                 struct dc_stream_state *stream = context->streams[i];
2513
2514                 del_streams[del_streams_count++] = stream;
2515         }
2516
2517         /* Remove all planes for removed streams and then remove the streams */
2518         for (i = 0; i < del_streams_count; i++) {
2519                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2520                         res = DC_FAIL_DETACH_SURFACES;
2521                         goto fail;
2522                 }
2523
2524                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2525                 if (res != DC_OK)
2526                         goto fail;
2527         }
2528
2529         res = dc_commit_streams(dc, context->streams, context->stream_count);
2530
2531 fail:
2532         dc_release_state(context);
2533
2534 context_alloc_fail:
2535         return res;
2536 }
2537
2538 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2539 {
2540         int i;
2541
2542         if (dm->hpd_rx_offload_wq) {
2543                 for (i = 0; i < dm->dc->caps.max_links; i++)
2544                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2545         }
2546 }
2547
2548 static int dm_suspend(void *handle)
2549 {
2550         struct amdgpu_device *adev = handle;
2551         struct amdgpu_display_manager *dm = &adev->dm;
2552         int ret = 0;
2553
2554         if (amdgpu_in_reset(adev)) {
2555                 mutex_lock(&dm->dc_lock);
2556
2557                 dc_allow_idle_optimizations(adev->dm.dc, false);
2558
2559                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2560
2561                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2562
2563                 amdgpu_dm_commit_zero_streams(dm->dc);
2564
2565                 amdgpu_dm_irq_suspend(adev);
2566
2567                 hpd_rx_irq_work_suspend(dm);
2568
2569                 return ret;
2570         }
2571
2572         WARN_ON(adev->dm.cached_state);
2573         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2574
2575         s3_handle_mst(adev_to_drm(adev), true);
2576
2577         amdgpu_dm_irq_suspend(adev);
2578
2579         hpd_rx_irq_work_suspend(dm);
2580
2581         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2582
2583         return 0;
2584 }
2585
2586 struct amdgpu_dm_connector *
2587 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2588                                              struct drm_crtc *crtc)
2589 {
2590         u32 i;
2591         struct drm_connector_state *new_con_state;
2592         struct drm_connector *connector;
2593         struct drm_crtc *crtc_from_state;
2594
2595         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2596                 crtc_from_state = new_con_state->crtc;
2597
2598                 if (crtc_from_state == crtc)
2599                         return to_amdgpu_dm_connector(connector);
2600         }
2601
2602         return NULL;
2603 }
2604
2605 static void emulated_link_detect(struct dc_link *link)
2606 {
2607         struct dc_sink_init_data sink_init_data = { 0 };
2608         struct display_sink_capability sink_caps = { 0 };
2609         enum dc_edid_status edid_status;
2610         struct dc_context *dc_ctx = link->ctx;
2611         struct dc_sink *sink = NULL;
2612         struct dc_sink *prev_sink = NULL;
2613
2614         link->type = dc_connection_none;
2615         prev_sink = link->local_sink;
2616
2617         if (prev_sink)
2618                 dc_sink_release(prev_sink);
2619
2620         switch (link->connector_signal) {
2621         case SIGNAL_TYPE_HDMI_TYPE_A: {
2622                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2623                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2624                 break;
2625         }
2626
2627         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2628                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2629                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2630                 break;
2631         }
2632
2633         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2634                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2635                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2636                 break;
2637         }
2638
2639         case SIGNAL_TYPE_LVDS: {
2640                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2641                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2642                 break;
2643         }
2644
2645         case SIGNAL_TYPE_EDP: {
2646                 sink_caps.transaction_type =
2647                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2648                 sink_caps.signal = SIGNAL_TYPE_EDP;
2649                 break;
2650         }
2651
2652         case SIGNAL_TYPE_DISPLAY_PORT: {
2653                 sink_caps.transaction_type =
2654                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2655                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2656                 break;
2657         }
2658
2659         default:
2660                 DC_ERROR("Invalid connector type! signal:%d\n",
2661                         link->connector_signal);
2662                 return;
2663         }
2664
2665         sink_init_data.link = link;
2666         sink_init_data.sink_signal = sink_caps.signal;
2667
2668         sink = dc_sink_create(&sink_init_data);
2669         if (!sink) {
2670                 DC_ERROR("Failed to create sink!\n");
2671                 return;
2672         }
2673
2674         /* dc_sink_create returns a new reference */
2675         link->local_sink = sink;
2676
2677         edid_status = dm_helpers_read_local_edid(
2678                         link->ctx,
2679                         link,
2680                         sink);
2681
2682         if (edid_status != EDID_OK)
2683                 DC_ERROR("Failed to read EDID");
2684
2685 }
2686
2687 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2688                                      struct amdgpu_display_manager *dm)
2689 {
2690         struct {
2691                 struct dc_surface_update surface_updates[MAX_SURFACES];
2692                 struct dc_plane_info plane_infos[MAX_SURFACES];
2693                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2694                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2695                 struct dc_stream_update stream_update;
2696         } * bundle;
2697         int k, m;
2698
2699         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2700
2701         if (!bundle) {
2702                 dm_error("Failed to allocate update bundle\n");
2703                 goto cleanup;
2704         }
2705
2706         for (k = 0; k < dc_state->stream_count; k++) {
2707                 bundle->stream_update.stream = dc_state->streams[k];
2708
2709                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2710                         bundle->surface_updates[m].surface =
2711                                 dc_state->stream_status->plane_states[m];
2712                         bundle->surface_updates[m].surface->force_full_update =
2713                                 true;
2714                 }
2715
2716                 update_planes_and_stream_adapter(dm->dc,
2717                                          UPDATE_TYPE_FULL,
2718                                          dc_state->stream_status->plane_count,
2719                                          dc_state->streams[k],
2720                                          &bundle->stream_update,
2721                                          bundle->surface_updates);
2722         }
2723
2724 cleanup:
2725         kfree(bundle);
2726
2727         return;
2728 }
2729
2730 static int dm_resume(void *handle)
2731 {
2732         struct amdgpu_device *adev = handle;
2733         struct drm_device *ddev = adev_to_drm(adev);
2734         struct amdgpu_display_manager *dm = &adev->dm;
2735         struct amdgpu_dm_connector *aconnector;
2736         struct drm_connector *connector;
2737         struct drm_connector_list_iter iter;
2738         struct drm_crtc *crtc;
2739         struct drm_crtc_state *new_crtc_state;
2740         struct dm_crtc_state *dm_new_crtc_state;
2741         struct drm_plane *plane;
2742         struct drm_plane_state *new_plane_state;
2743         struct dm_plane_state *dm_new_plane_state;
2744         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2745         enum dc_connection_type new_connection_type = dc_connection_none;
2746         struct dc_state *dc_state;
2747         int i, r, j;
2748
2749         if (amdgpu_in_reset(adev)) {
2750                 dc_state = dm->cached_dc_state;
2751
2752                 /*
2753                  * The dc->current_state is backed up into dm->cached_dc_state
2754                  * before we commit 0 streams.
2755                  *
2756                  * DC will clear link encoder assignments on the real state
2757                  * but the changes won't propagate over to the copy we made
2758                  * before the 0 streams commit.
2759                  *
2760                  * DC expects that link encoder assignments are *not* valid
2761                  * when committing a state, so as a workaround we can copy
2762                  * off of the current state.
2763                  *
2764                  * We lose the previous assignments, but we had already
2765                  * commit 0 streams anyway.
2766                  */
2767                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2768
2769                 r = dm_dmub_hw_init(adev);
2770                 if (r)
2771                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2772
2773                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2774                 dc_resume(dm->dc);
2775
2776                 amdgpu_dm_irq_resume_early(adev);
2777
2778                 for (i = 0; i < dc_state->stream_count; i++) {
2779                         dc_state->streams[i]->mode_changed = true;
2780                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2781                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2782                                         = 0xffffffff;
2783                         }
2784                 }
2785
2786                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2787                         amdgpu_dm_outbox_init(adev);
2788                         dc_enable_dmub_outbox(adev->dm.dc);
2789                 }
2790
2791                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2792
2793                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2794
2795                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2796
2797                 dc_release_state(dm->cached_dc_state);
2798                 dm->cached_dc_state = NULL;
2799
2800                 amdgpu_dm_irq_resume_late(adev);
2801
2802                 mutex_unlock(&dm->dc_lock);
2803
2804                 return 0;
2805         }
2806         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2807         dc_release_state(dm_state->context);
2808         dm_state->context = dc_create_state(dm->dc);
2809         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2810         dc_resource_state_construct(dm->dc, dm_state->context);
2811
2812         /* Before powering on DC we need to re-initialize DMUB. */
2813         dm_dmub_hw_resume(adev);
2814
2815         /* Re-enable outbox interrupts for DPIA. */
2816         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2817                 amdgpu_dm_outbox_init(adev);
2818                 dc_enable_dmub_outbox(adev->dm.dc);
2819         }
2820
2821         /* power on hardware */
2822         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2823
2824         /* program HPD filter */
2825         dc_resume(dm->dc);
2826
2827         /*
2828          * early enable HPD Rx IRQ, should be done before set mode as short
2829          * pulse interrupts are used for MST
2830          */
2831         amdgpu_dm_irq_resume_early(adev);
2832
2833         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2834         s3_handle_mst(ddev, false);
2835
2836         /* Do detection*/
2837         drm_connector_list_iter_begin(ddev, &iter);
2838         drm_for_each_connector_iter(connector, &iter) {
2839                 aconnector = to_amdgpu_dm_connector(connector);
2840
2841                 if (!aconnector->dc_link)
2842                         continue;
2843
2844                 /*
2845                  * this is the case when traversing through already created
2846                  * MST connectors, should be skipped
2847                  */
2848                 if (aconnector->dc_link->type == dc_connection_mst_branch)
2849                         continue;
2850
2851                 mutex_lock(&aconnector->hpd_lock);
2852                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2853                         DRM_ERROR("KMS: Failed to detect connector\n");
2854
2855                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2856                         emulated_link_detect(aconnector->dc_link);
2857                 } else {
2858                         mutex_lock(&dm->dc_lock);
2859                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2860                         mutex_unlock(&dm->dc_lock);
2861                 }
2862
2863                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2864                         aconnector->fake_enable = false;
2865
2866                 if (aconnector->dc_sink)
2867                         dc_sink_release(aconnector->dc_sink);
2868                 aconnector->dc_sink = NULL;
2869                 amdgpu_dm_update_connector_after_detect(aconnector);
2870                 mutex_unlock(&aconnector->hpd_lock);
2871         }
2872         drm_connector_list_iter_end(&iter);
2873
2874         /* Force mode set in atomic commit */
2875         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2876                 new_crtc_state->active_changed = true;
2877
2878         /*
2879          * atomic_check is expected to create the dc states. We need to release
2880          * them here, since they were duplicated as part of the suspend
2881          * procedure.
2882          */
2883         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2884                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2885                 if (dm_new_crtc_state->stream) {
2886                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2887                         dc_stream_release(dm_new_crtc_state->stream);
2888                         dm_new_crtc_state->stream = NULL;
2889                 }
2890         }
2891
2892         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2893                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2894                 if (dm_new_plane_state->dc_state) {
2895                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2896                         dc_plane_state_release(dm_new_plane_state->dc_state);
2897                         dm_new_plane_state->dc_state = NULL;
2898                 }
2899         }
2900
2901         drm_atomic_helper_resume(ddev, dm->cached_state);
2902
2903         dm->cached_state = NULL;
2904
2905         amdgpu_dm_irq_resume_late(adev);
2906
2907         amdgpu_dm_smu_write_watermarks_table(adev);
2908
2909         return 0;
2910 }
2911
2912 /**
2913  * DOC: DM Lifecycle
2914  *
2915  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2916  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2917  * the base driver's device list to be initialized and torn down accordingly.
2918  *
2919  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2920  */
2921
2922 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2923         .name = "dm",
2924         .early_init = dm_early_init,
2925         .late_init = dm_late_init,
2926         .sw_init = dm_sw_init,
2927         .sw_fini = dm_sw_fini,
2928         .early_fini = amdgpu_dm_early_fini,
2929         .hw_init = dm_hw_init,
2930         .hw_fini = dm_hw_fini,
2931         .suspend = dm_suspend,
2932         .resume = dm_resume,
2933         .is_idle = dm_is_idle,
2934         .wait_for_idle = dm_wait_for_idle,
2935         .check_soft_reset = dm_check_soft_reset,
2936         .soft_reset = dm_soft_reset,
2937         .set_clockgating_state = dm_set_clockgating_state,
2938         .set_powergating_state = dm_set_powergating_state,
2939 };
2940
2941 const struct amdgpu_ip_block_version dm_ip_block =
2942 {
2943         .type = AMD_IP_BLOCK_TYPE_DCE,
2944         .major = 1,
2945         .minor = 0,
2946         .rev = 0,
2947         .funcs = &amdgpu_dm_funcs,
2948 };
2949
2950
2951 /**
2952  * DOC: atomic
2953  *
2954  * *WIP*
2955  */
2956
2957 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2958         .fb_create = amdgpu_display_user_framebuffer_create,
2959         .get_format_info = amdgpu_dm_plane_get_format_info,
2960         .atomic_check = amdgpu_dm_atomic_check,
2961         .atomic_commit = drm_atomic_helper_commit,
2962 };
2963
2964 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2965         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2966         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2967 };
2968
2969 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2970 {
2971         struct amdgpu_dm_backlight_caps *caps;
2972         struct amdgpu_display_manager *dm;
2973         struct drm_connector *conn_base;
2974         struct amdgpu_device *adev;
2975         struct dc_link *link = NULL;
2976         struct drm_luminance_range_info *luminance_range;
2977         int i;
2978
2979         if (!aconnector || !aconnector->dc_link)
2980                 return;
2981
2982         link = aconnector->dc_link;
2983         if (link->connector_signal != SIGNAL_TYPE_EDP)
2984                 return;
2985
2986         conn_base = &aconnector->base;
2987         adev = drm_to_adev(conn_base->dev);
2988         dm = &adev->dm;
2989         for (i = 0; i < dm->num_of_edps; i++) {
2990                 if (link == dm->backlight_link[i])
2991                         break;
2992         }
2993         if (i >= dm->num_of_edps)
2994                 return;
2995         caps = &dm->backlight_caps[i];
2996         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2997         caps->aux_support = false;
2998
2999         if (caps->ext_caps->bits.oled == 1 /*||
3000             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3001             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3002                 caps->aux_support = true;
3003
3004         if (amdgpu_backlight == 0)
3005                 caps->aux_support = false;
3006         else if (amdgpu_backlight == 1)
3007                 caps->aux_support = true;
3008
3009         luminance_range = &conn_base->display_info.luminance_range;
3010
3011         if (luminance_range->max_luminance) {
3012                 caps->aux_min_input_signal = luminance_range->min_luminance;
3013                 caps->aux_max_input_signal = luminance_range->max_luminance;
3014         } else {
3015                 caps->aux_min_input_signal = 0;
3016                 caps->aux_max_input_signal = 512;
3017         }
3018 }
3019
3020 void amdgpu_dm_update_connector_after_detect(
3021                 struct amdgpu_dm_connector *aconnector)
3022 {
3023         struct drm_connector *connector = &aconnector->base;
3024         struct drm_device *dev = connector->dev;
3025         struct dc_sink *sink;
3026
3027         /* MST handled by drm_mst framework */
3028         if (aconnector->mst_mgr.mst_state == true)
3029                 return;
3030
3031         sink = aconnector->dc_link->local_sink;
3032         if (sink)
3033                 dc_sink_retain(sink);
3034
3035         /*
3036          * Edid mgmt connector gets first update only in mode_valid hook and then
3037          * the connector sink is set to either fake or physical sink depends on link status.
3038          * Skip if already done during boot.
3039          */
3040         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3041                         && aconnector->dc_em_sink) {
3042
3043                 /*
3044                  * For S3 resume with headless use eml_sink to fake stream
3045                  * because on resume connector->sink is set to NULL
3046                  */
3047                 mutex_lock(&dev->mode_config.mutex);
3048
3049                 if (sink) {
3050                         if (aconnector->dc_sink) {
3051                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3052                                 /*
3053                                  * retain and release below are used to
3054                                  * bump up refcount for sink because the link doesn't point
3055                                  * to it anymore after disconnect, so on next crtc to connector
3056                                  * reshuffle by UMD we will get into unwanted dc_sink release
3057                                  */
3058                                 dc_sink_release(aconnector->dc_sink);
3059                         }
3060                         aconnector->dc_sink = sink;
3061                         dc_sink_retain(aconnector->dc_sink);
3062                         amdgpu_dm_update_freesync_caps(connector,
3063                                         aconnector->edid);
3064                 } else {
3065                         amdgpu_dm_update_freesync_caps(connector, NULL);
3066                         if (!aconnector->dc_sink) {
3067                                 aconnector->dc_sink = aconnector->dc_em_sink;
3068                                 dc_sink_retain(aconnector->dc_sink);
3069                         }
3070                 }
3071
3072                 mutex_unlock(&dev->mode_config.mutex);
3073
3074                 if (sink)
3075                         dc_sink_release(sink);
3076                 return;
3077         }
3078
3079         /*
3080          * TODO: temporary guard to look for proper fix
3081          * if this sink is MST sink, we should not do anything
3082          */
3083         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3084                 dc_sink_release(sink);
3085                 return;
3086         }
3087
3088         if (aconnector->dc_sink == sink) {
3089                 /*
3090                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3091                  * Do nothing!!
3092                  */
3093                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3094                                 aconnector->connector_id);
3095                 if (sink)
3096                         dc_sink_release(sink);
3097                 return;
3098         }
3099
3100         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3101                 aconnector->connector_id, aconnector->dc_sink, sink);
3102
3103         mutex_lock(&dev->mode_config.mutex);
3104
3105         /*
3106          * 1. Update status of the drm connector
3107          * 2. Send an event and let userspace tell us what to do
3108          */
3109         if (sink) {
3110                 /*
3111                  * TODO: check if we still need the S3 mode update workaround.
3112                  * If yes, put it here.
3113                  */
3114                 if (aconnector->dc_sink) {
3115                         amdgpu_dm_update_freesync_caps(connector, NULL);
3116                         dc_sink_release(aconnector->dc_sink);
3117                 }
3118
3119                 aconnector->dc_sink = sink;
3120                 dc_sink_retain(aconnector->dc_sink);
3121                 if (sink->dc_edid.length == 0) {
3122                         aconnector->edid = NULL;
3123                         if (aconnector->dc_link->aux_mode) {
3124                                 drm_dp_cec_unset_edid(
3125                                         &aconnector->dm_dp_aux.aux);
3126                         }
3127                 } else {
3128                         aconnector->edid =
3129                                 (struct edid *)sink->dc_edid.raw_edid;
3130
3131                         if (aconnector->dc_link->aux_mode)
3132                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3133                                                     aconnector->edid);
3134                 }
3135
3136                 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3137                 if (!aconnector->timing_requested)
3138                         dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3139
3140                 drm_connector_update_edid_property(connector, aconnector->edid);
3141                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3142                 update_connector_ext_caps(aconnector);
3143         } else {
3144                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3145                 amdgpu_dm_update_freesync_caps(connector, NULL);
3146                 drm_connector_update_edid_property(connector, NULL);
3147                 aconnector->num_modes = 0;
3148                 dc_sink_release(aconnector->dc_sink);
3149                 aconnector->dc_sink = NULL;
3150                 aconnector->edid = NULL;
3151                 kfree(aconnector->timing_requested);
3152                 aconnector->timing_requested = NULL;
3153                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3154                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3155                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3156         }
3157
3158         mutex_unlock(&dev->mode_config.mutex);
3159
3160         update_subconnector_property(aconnector);
3161
3162         if (sink)
3163                 dc_sink_release(sink);
3164 }
3165
3166 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3167 {
3168         struct drm_connector *connector = &aconnector->base;
3169         struct drm_device *dev = connector->dev;
3170         enum dc_connection_type new_connection_type = dc_connection_none;
3171         struct amdgpu_device *adev = drm_to_adev(dev);
3172         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3173         bool ret = false;
3174
3175         if (adev->dm.disable_hpd_irq)
3176                 return;
3177
3178         /*
3179          * In case of failure or MST no need to update connector status or notify the OS
3180          * since (for MST case) MST does this in its own context.
3181          */
3182         mutex_lock(&aconnector->hpd_lock);
3183
3184         if (adev->dm.hdcp_workqueue) {
3185                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3186                 dm_con_state->update_hdcp = true;
3187         }
3188         if (aconnector->fake_enable)
3189                 aconnector->fake_enable = false;
3190
3191         aconnector->timing_changed = false;
3192
3193         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3194                 DRM_ERROR("KMS: Failed to detect connector\n");
3195
3196         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3197                 emulated_link_detect(aconnector->dc_link);
3198
3199                 drm_modeset_lock_all(dev);
3200                 dm_restore_drm_connector_state(dev, connector);
3201                 drm_modeset_unlock_all(dev);
3202
3203                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3204                         drm_kms_helper_connector_hotplug_event(connector);
3205         } else {
3206                 mutex_lock(&adev->dm.dc_lock);
3207                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3208                 mutex_unlock(&adev->dm.dc_lock);
3209                 if (ret) {
3210                         amdgpu_dm_update_connector_after_detect(aconnector);
3211
3212                         drm_modeset_lock_all(dev);
3213                         dm_restore_drm_connector_state(dev, connector);
3214                         drm_modeset_unlock_all(dev);
3215
3216                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3217                                 drm_kms_helper_connector_hotplug_event(connector);
3218                 }
3219         }
3220         mutex_unlock(&aconnector->hpd_lock);
3221
3222 }
3223
3224 static void handle_hpd_irq(void *param)
3225 {
3226         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3227
3228         handle_hpd_irq_helper(aconnector);
3229
3230 }
3231
3232 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3233 {
3234         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3235         u8 dret;
3236         bool new_irq_handled = false;
3237         int dpcd_addr;
3238         int dpcd_bytes_to_read;
3239
3240         const int max_process_count = 30;
3241         int process_count = 0;
3242
3243         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3244
3245         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3246                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3247                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3248                 dpcd_addr = DP_SINK_COUNT;
3249         } else {
3250                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3251                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3252                 dpcd_addr = DP_SINK_COUNT_ESI;
3253         }
3254
3255         dret = drm_dp_dpcd_read(
3256                 &aconnector->dm_dp_aux.aux,
3257                 dpcd_addr,
3258                 esi,
3259                 dpcd_bytes_to_read);
3260
3261         while (dret == dpcd_bytes_to_read &&
3262                 process_count < max_process_count) {
3263                 u8 retry;
3264                 dret = 0;
3265
3266                 process_count++;
3267
3268                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3269                 /* handle HPD short pulse irq */
3270                 if (aconnector->mst_mgr.mst_state)
3271                         drm_dp_mst_hpd_irq(
3272                                 &aconnector->mst_mgr,
3273                                 esi,
3274                                 &new_irq_handled);
3275
3276                 if (new_irq_handled) {
3277                         /* ACK at DPCD to notify down stream */
3278                         const int ack_dpcd_bytes_to_write =
3279                                 dpcd_bytes_to_read - 1;
3280
3281                         for (retry = 0; retry < 3; retry++) {
3282                                 u8 wret;
3283
3284                                 wret = drm_dp_dpcd_write(
3285                                         &aconnector->dm_dp_aux.aux,
3286                                         dpcd_addr + 1,
3287                                         &esi[1],
3288                                         ack_dpcd_bytes_to_write);
3289                                 if (wret == ack_dpcd_bytes_to_write)
3290                                         break;
3291                         }
3292
3293                         /* check if there is new irq to be handled */
3294                         dret = drm_dp_dpcd_read(
3295                                 &aconnector->dm_dp_aux.aux,
3296                                 dpcd_addr,
3297                                 esi,
3298                                 dpcd_bytes_to_read);
3299
3300                         new_irq_handled = false;
3301                 } else {
3302                         break;
3303                 }
3304         }
3305
3306         if (process_count == max_process_count)
3307                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3308 }
3309
3310 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3311                                                         union hpd_irq_data hpd_irq_data)
3312 {
3313         struct hpd_rx_irq_offload_work *offload_work =
3314                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3315
3316         if (!offload_work) {
3317                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3318                 return;
3319         }
3320
3321         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3322         offload_work->data = hpd_irq_data;
3323         offload_work->offload_wq = offload_wq;
3324
3325         queue_work(offload_wq->wq, &offload_work->work);
3326         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3327 }
3328
3329 static void handle_hpd_rx_irq(void *param)
3330 {
3331         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3332         struct drm_connector *connector = &aconnector->base;
3333         struct drm_device *dev = connector->dev;
3334         struct dc_link *dc_link = aconnector->dc_link;
3335         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3336         bool result = false;
3337         enum dc_connection_type new_connection_type = dc_connection_none;
3338         struct amdgpu_device *adev = drm_to_adev(dev);
3339         union hpd_irq_data hpd_irq_data;
3340         bool link_loss = false;
3341         bool has_left_work = false;
3342         int idx = dc_link->link_index;
3343         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3344
3345         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3346
3347         if (adev->dm.disable_hpd_irq)
3348                 return;
3349
3350         /*
3351          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3352          * conflict, after implement i2c helper, this mutex should be
3353          * retired.
3354          */
3355         mutex_lock(&aconnector->hpd_lock);
3356
3357         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3358                                                 &link_loss, true, &has_left_work);
3359
3360         if (!has_left_work)
3361                 goto out;
3362
3363         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3364                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3365                 goto out;
3366         }
3367
3368         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3369                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3370                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3371                         dm_handle_mst_sideband_msg(aconnector);
3372                         goto out;
3373                 }
3374
3375                 if (link_loss) {
3376                         bool skip = false;
3377
3378                         spin_lock(&offload_wq->offload_lock);
3379                         skip = offload_wq->is_handling_link_loss;
3380
3381                         if (!skip)
3382                                 offload_wq->is_handling_link_loss = true;
3383
3384                         spin_unlock(&offload_wq->offload_lock);
3385
3386                         if (!skip)
3387                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3388
3389                         goto out;
3390                 }
3391         }
3392
3393 out:
3394         if (result && !is_mst_root_connector) {
3395                 /* Downstream Port status changed. */
3396                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3397                         DRM_ERROR("KMS: Failed to detect connector\n");
3398
3399                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3400                         emulated_link_detect(dc_link);
3401
3402                         if (aconnector->fake_enable)
3403                                 aconnector->fake_enable = false;
3404
3405                         amdgpu_dm_update_connector_after_detect(aconnector);
3406
3407
3408                         drm_modeset_lock_all(dev);
3409                         dm_restore_drm_connector_state(dev, connector);
3410                         drm_modeset_unlock_all(dev);
3411
3412                         drm_kms_helper_connector_hotplug_event(connector);
3413                 } else {
3414                         bool ret = false;
3415
3416                         mutex_lock(&adev->dm.dc_lock);
3417                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3418                         mutex_unlock(&adev->dm.dc_lock);
3419
3420                         if (ret) {
3421                                 if (aconnector->fake_enable)
3422                                         aconnector->fake_enable = false;
3423
3424                                 amdgpu_dm_update_connector_after_detect(aconnector);
3425
3426                                 drm_modeset_lock_all(dev);
3427                                 dm_restore_drm_connector_state(dev, connector);
3428                                 drm_modeset_unlock_all(dev);
3429
3430                                 drm_kms_helper_connector_hotplug_event(connector);
3431                         }
3432                 }
3433         }
3434         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3435                 if (adev->dm.hdcp_workqueue)
3436                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3437         }
3438
3439         if (dc_link->type != dc_connection_mst_branch)
3440                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3441
3442         mutex_unlock(&aconnector->hpd_lock);
3443 }
3444
3445 static void register_hpd_handlers(struct amdgpu_device *adev)
3446 {
3447         struct drm_device *dev = adev_to_drm(adev);
3448         struct drm_connector *connector;
3449         struct amdgpu_dm_connector *aconnector;
3450         const struct dc_link *dc_link;
3451         struct dc_interrupt_params int_params = {0};
3452
3453         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3454         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3455
3456         list_for_each_entry(connector,
3457                         &dev->mode_config.connector_list, head) {
3458
3459                 aconnector = to_amdgpu_dm_connector(connector);
3460                 dc_link = aconnector->dc_link;
3461
3462                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3463                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3464                         int_params.irq_source = dc_link->irq_source_hpd;
3465
3466                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3467                                         handle_hpd_irq,
3468                                         (void *) aconnector);
3469                 }
3470
3471                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3472
3473                         /* Also register for DP short pulse (hpd_rx). */
3474                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3475                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3476
3477                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3478                                         handle_hpd_rx_irq,
3479                                         (void *) aconnector);
3480
3481                         if (adev->dm.hpd_rx_offload_wq)
3482                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3483                                         aconnector;
3484                 }
3485         }
3486 }
3487
3488 #if defined(CONFIG_DRM_AMD_DC_SI)
3489 /* Register IRQ sources and initialize IRQ callbacks */
3490 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3491 {
3492         struct dc *dc = adev->dm.dc;
3493         struct common_irq_params *c_irq_params;
3494         struct dc_interrupt_params int_params = {0};
3495         int r;
3496         int i;
3497         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3498
3499         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3500         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3501
3502         /*
3503          * Actions of amdgpu_irq_add_id():
3504          * 1. Register a set() function with base driver.
3505          *    Base driver will call set() function to enable/disable an
3506          *    interrupt in DC hardware.
3507          * 2. Register amdgpu_dm_irq_handler().
3508          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3509          *    coming from DC hardware.
3510          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3511          *    for acknowledging and handling. */
3512
3513         /* Use VBLANK interrupt */
3514         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3515                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3516                 if (r) {
3517                         DRM_ERROR("Failed to add crtc irq id!\n");
3518                         return r;
3519                 }
3520
3521                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3522                 int_params.irq_source =
3523                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3524
3525                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3526
3527                 c_irq_params->adev = adev;
3528                 c_irq_params->irq_src = int_params.irq_source;
3529
3530                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3531                                 dm_crtc_high_irq, c_irq_params);
3532         }
3533
3534         /* Use GRPH_PFLIP interrupt */
3535         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3536                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3537                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3538                 if (r) {
3539                         DRM_ERROR("Failed to add page flip irq id!\n");
3540                         return r;
3541                 }
3542
3543                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3544                 int_params.irq_source =
3545                         dc_interrupt_to_irq_source(dc, i, 0);
3546
3547                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3548
3549                 c_irq_params->adev = adev;
3550                 c_irq_params->irq_src = int_params.irq_source;
3551
3552                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3553                                 dm_pflip_high_irq, c_irq_params);
3554
3555         }
3556
3557         /* HPD */
3558         r = amdgpu_irq_add_id(adev, client_id,
3559                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3560         if (r) {
3561                 DRM_ERROR("Failed to add hpd irq id!\n");
3562                 return r;
3563         }
3564
3565         register_hpd_handlers(adev);
3566
3567         return 0;
3568 }
3569 #endif
3570
3571 /* Register IRQ sources and initialize IRQ callbacks */
3572 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3573 {
3574         struct dc *dc = adev->dm.dc;
3575         struct common_irq_params *c_irq_params;
3576         struct dc_interrupt_params int_params = {0};
3577         int r;
3578         int i;
3579         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3580
3581         if (adev->family >= AMDGPU_FAMILY_AI)
3582                 client_id = SOC15_IH_CLIENTID_DCE;
3583
3584         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3585         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3586
3587         /*
3588          * Actions of amdgpu_irq_add_id():
3589          * 1. Register a set() function with base driver.
3590          *    Base driver will call set() function to enable/disable an
3591          *    interrupt in DC hardware.
3592          * 2. Register amdgpu_dm_irq_handler().
3593          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3594          *    coming from DC hardware.
3595          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3596          *    for acknowledging and handling. */
3597
3598         /* Use VBLANK interrupt */
3599         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3600                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3601                 if (r) {
3602                         DRM_ERROR("Failed to add crtc irq id!\n");
3603                         return r;
3604                 }
3605
3606                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3607                 int_params.irq_source =
3608                         dc_interrupt_to_irq_source(dc, i, 0);
3609
3610                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3611
3612                 c_irq_params->adev = adev;
3613                 c_irq_params->irq_src = int_params.irq_source;
3614
3615                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3616                                 dm_crtc_high_irq, c_irq_params);
3617         }
3618
3619         /* Use VUPDATE interrupt */
3620         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3621                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3622                 if (r) {
3623                         DRM_ERROR("Failed to add vupdate irq id!\n");
3624                         return r;
3625                 }
3626
3627                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3628                 int_params.irq_source =
3629                         dc_interrupt_to_irq_source(dc, i, 0);
3630
3631                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3632
3633                 c_irq_params->adev = adev;
3634                 c_irq_params->irq_src = int_params.irq_source;
3635
3636                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3637                                 dm_vupdate_high_irq, c_irq_params);
3638         }
3639
3640         /* Use GRPH_PFLIP interrupt */
3641         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3642                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3643                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3644                 if (r) {
3645                         DRM_ERROR("Failed to add page flip irq id!\n");
3646                         return r;
3647                 }
3648
3649                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3650                 int_params.irq_source =
3651                         dc_interrupt_to_irq_source(dc, i, 0);
3652
3653                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3654
3655                 c_irq_params->adev = adev;
3656                 c_irq_params->irq_src = int_params.irq_source;
3657
3658                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3659                                 dm_pflip_high_irq, c_irq_params);
3660
3661         }
3662
3663         /* HPD */
3664         r = amdgpu_irq_add_id(adev, client_id,
3665                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3666         if (r) {
3667                 DRM_ERROR("Failed to add hpd irq id!\n");
3668                 return r;
3669         }
3670
3671         register_hpd_handlers(adev);
3672
3673         return 0;
3674 }
3675
3676 /* Register IRQ sources and initialize IRQ callbacks */
3677 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3678 {
3679         struct dc *dc = adev->dm.dc;
3680         struct common_irq_params *c_irq_params;
3681         struct dc_interrupt_params int_params = {0};
3682         int r;
3683         int i;
3684 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3685         static const unsigned int vrtl_int_srcid[] = {
3686                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3687                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3688                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3689                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3690                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3691                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3692         };
3693 #endif
3694
3695         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3696         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3697
3698         /*
3699          * Actions of amdgpu_irq_add_id():
3700          * 1. Register a set() function with base driver.
3701          *    Base driver will call set() function to enable/disable an
3702          *    interrupt in DC hardware.
3703          * 2. Register amdgpu_dm_irq_handler().
3704          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3705          *    coming from DC hardware.
3706          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3707          *    for acknowledging and handling.
3708          */
3709
3710         /* Use VSTARTUP interrupt */
3711         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3712                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3713                         i++) {
3714                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3715
3716                 if (r) {
3717                         DRM_ERROR("Failed to add crtc irq id!\n");
3718                         return r;
3719                 }
3720
3721                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3722                 int_params.irq_source =
3723                         dc_interrupt_to_irq_source(dc, i, 0);
3724
3725                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3726
3727                 c_irq_params->adev = adev;
3728                 c_irq_params->irq_src = int_params.irq_source;
3729
3730                 amdgpu_dm_irq_register_interrupt(
3731                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3732         }
3733
3734         /* Use otg vertical line interrupt */
3735 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3736         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3737                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3738                                 vrtl_int_srcid[i], &adev->vline0_irq);
3739
3740                 if (r) {
3741                         DRM_ERROR("Failed to add vline0 irq id!\n");
3742                         return r;
3743                 }
3744
3745                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3746                 int_params.irq_source =
3747                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3748
3749                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3750                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3751                         break;
3752                 }
3753
3754                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3755                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3756
3757                 c_irq_params->adev = adev;
3758                 c_irq_params->irq_src = int_params.irq_source;
3759
3760                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3761                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3762         }
3763 #endif
3764
3765         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3766          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3767          * to trigger at end of each vblank, regardless of state of the lock,
3768          * matching DCE behaviour.
3769          */
3770         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3771              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3772              i++) {
3773                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3774
3775                 if (r) {
3776                         DRM_ERROR("Failed to add vupdate irq id!\n");
3777                         return r;
3778                 }
3779
3780                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3781                 int_params.irq_source =
3782                         dc_interrupt_to_irq_source(dc, i, 0);
3783
3784                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3785
3786                 c_irq_params->adev = adev;
3787                 c_irq_params->irq_src = int_params.irq_source;
3788
3789                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3790                                 dm_vupdate_high_irq, c_irq_params);
3791         }
3792
3793         /* Use GRPH_PFLIP interrupt */
3794         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3795                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3796                         i++) {
3797                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3798                 if (r) {
3799                         DRM_ERROR("Failed to add page flip irq id!\n");
3800                         return r;
3801                 }
3802
3803                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3804                 int_params.irq_source =
3805                         dc_interrupt_to_irq_source(dc, i, 0);
3806
3807                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3808
3809                 c_irq_params->adev = adev;
3810                 c_irq_params->irq_src = int_params.irq_source;
3811
3812                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3813                                 dm_pflip_high_irq, c_irq_params);
3814
3815         }
3816
3817         /* HPD */
3818         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3819                         &adev->hpd_irq);
3820         if (r) {
3821                 DRM_ERROR("Failed to add hpd irq id!\n");
3822                 return r;
3823         }
3824
3825         register_hpd_handlers(adev);
3826
3827         return 0;
3828 }
3829 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3830 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3831 {
3832         struct dc *dc = adev->dm.dc;
3833         struct common_irq_params *c_irq_params;
3834         struct dc_interrupt_params int_params = {0};
3835         int r, i;
3836
3837         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3838         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3839
3840         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3841                         &adev->dmub_outbox_irq);
3842         if (r) {
3843                 DRM_ERROR("Failed to add outbox irq id!\n");
3844                 return r;
3845         }
3846
3847         if (dc->ctx->dmub_srv) {
3848                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3849                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3850                 int_params.irq_source =
3851                 dc_interrupt_to_irq_source(dc, i, 0);
3852
3853                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3854
3855                 c_irq_params->adev = adev;
3856                 c_irq_params->irq_src = int_params.irq_source;
3857
3858                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3859                                 dm_dmub_outbox1_low_irq, c_irq_params);
3860         }
3861
3862         return 0;
3863 }
3864
3865 /*
3866  * Acquires the lock for the atomic state object and returns
3867  * the new atomic state.
3868  *
3869  * This should only be called during atomic check.
3870  */
3871 int dm_atomic_get_state(struct drm_atomic_state *state,
3872                         struct dm_atomic_state **dm_state)
3873 {
3874         struct drm_device *dev = state->dev;
3875         struct amdgpu_device *adev = drm_to_adev(dev);
3876         struct amdgpu_display_manager *dm = &adev->dm;
3877         struct drm_private_state *priv_state;
3878
3879         if (*dm_state)
3880                 return 0;
3881
3882         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3883         if (IS_ERR(priv_state))
3884                 return PTR_ERR(priv_state);
3885
3886         *dm_state = to_dm_atomic_state(priv_state);
3887
3888         return 0;
3889 }
3890
3891 static struct dm_atomic_state *
3892 dm_atomic_get_new_state(struct drm_atomic_state *state)
3893 {
3894         struct drm_device *dev = state->dev;
3895         struct amdgpu_device *adev = drm_to_adev(dev);
3896         struct amdgpu_display_manager *dm = &adev->dm;
3897         struct drm_private_obj *obj;
3898         struct drm_private_state *new_obj_state;
3899         int i;
3900
3901         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3902                 if (obj->funcs == dm->atomic_obj.funcs)
3903                         return to_dm_atomic_state(new_obj_state);
3904         }
3905
3906         return NULL;
3907 }
3908
3909 static struct drm_private_state *
3910 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3911 {
3912         struct dm_atomic_state *old_state, *new_state;
3913
3914         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3915         if (!new_state)
3916                 return NULL;
3917
3918         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3919
3920         old_state = to_dm_atomic_state(obj->state);
3921
3922         if (old_state && old_state->context)
3923                 new_state->context = dc_copy_state(old_state->context);
3924
3925         if (!new_state->context) {
3926                 kfree(new_state);
3927                 return NULL;
3928         }
3929
3930         return &new_state->base;
3931 }
3932
3933 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3934                                     struct drm_private_state *state)
3935 {
3936         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3937
3938         if (dm_state && dm_state->context)
3939                 dc_release_state(dm_state->context);
3940
3941         kfree(dm_state);
3942 }
3943
3944 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3945         .atomic_duplicate_state = dm_atomic_duplicate_state,
3946         .atomic_destroy_state = dm_atomic_destroy_state,
3947 };
3948
3949 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3950 {
3951         struct dm_atomic_state *state;
3952         int r;
3953
3954         adev->mode_info.mode_config_initialized = true;
3955
3956         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3957         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3958
3959         adev_to_drm(adev)->mode_config.max_width = 16384;
3960         adev_to_drm(adev)->mode_config.max_height = 16384;
3961
3962         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3963         if (adev->asic_type == CHIP_HAWAII)
3964                 /* disable prefer shadow for now due to hibernation issues */
3965                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3966         else
3967                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3968         /* indicates support for immediate flip */
3969         adev_to_drm(adev)->mode_config.async_page_flip = true;
3970
3971         state = kzalloc(sizeof(*state), GFP_KERNEL);
3972         if (!state)
3973                 return -ENOMEM;
3974
3975         state->context = dc_create_state(adev->dm.dc);
3976         if (!state->context) {
3977                 kfree(state);
3978                 return -ENOMEM;
3979         }
3980
3981         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3982
3983         drm_atomic_private_obj_init(adev_to_drm(adev),
3984                                     &adev->dm.atomic_obj,
3985                                     &state->base,
3986                                     &dm_atomic_state_funcs);
3987
3988         r = amdgpu_display_modeset_create_props(adev);
3989         if (r) {
3990                 dc_release_state(state->context);
3991                 kfree(state);
3992                 return r;
3993         }
3994
3995         r = amdgpu_dm_audio_init(adev);
3996         if (r) {
3997                 dc_release_state(state->context);
3998                 kfree(state);
3999                 return r;
4000         }
4001
4002         return 0;
4003 }
4004
4005 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4006 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4007 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4008
4009 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4010                                             int bl_idx)
4011 {
4012 #if defined(CONFIG_ACPI)
4013         struct amdgpu_dm_backlight_caps caps;
4014
4015         memset(&caps, 0, sizeof(caps));
4016
4017         if (dm->backlight_caps[bl_idx].caps_valid)
4018                 return;
4019
4020         amdgpu_acpi_get_backlight_caps(&caps);
4021         if (caps.caps_valid) {
4022                 dm->backlight_caps[bl_idx].caps_valid = true;
4023                 if (caps.aux_support)
4024                         return;
4025                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4026                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4027         } else {
4028                 dm->backlight_caps[bl_idx].min_input_signal =
4029                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4030                 dm->backlight_caps[bl_idx].max_input_signal =
4031                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4032         }
4033 #else
4034         if (dm->backlight_caps[bl_idx].aux_support)
4035                 return;
4036
4037         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4038         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4039 #endif
4040 }
4041
4042 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4043                                 unsigned *min, unsigned *max)
4044 {
4045         if (!caps)
4046                 return 0;
4047
4048         if (caps->aux_support) {
4049                 // Firmware limits are in nits, DC API wants millinits.
4050                 *max = 1000 * caps->aux_max_input_signal;
4051                 *min = 1000 * caps->aux_min_input_signal;
4052         } else {
4053                 // Firmware limits are 8-bit, PWM control is 16-bit.
4054                 *max = 0x101 * caps->max_input_signal;
4055                 *min = 0x101 * caps->min_input_signal;
4056         }
4057         return 1;
4058 }
4059
4060 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4061                                         uint32_t brightness)
4062 {
4063         unsigned min, max;
4064
4065         if (!get_brightness_range(caps, &min, &max))
4066                 return brightness;
4067
4068         // Rescale 0..255 to min..max
4069         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4070                                        AMDGPU_MAX_BL_LEVEL);
4071 }
4072
4073 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4074                                       uint32_t brightness)
4075 {
4076         unsigned min, max;
4077
4078         if (!get_brightness_range(caps, &min, &max))
4079                 return brightness;
4080
4081         if (brightness < min)
4082                 return 0;
4083         // Rescale min..max to 0..255
4084         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4085                                  max - min);
4086 }
4087
4088 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4089                                          int bl_idx,
4090                                          u32 user_brightness)
4091 {
4092         struct amdgpu_dm_backlight_caps caps;
4093         struct dc_link *link;
4094         u32 brightness;
4095         bool rc;
4096
4097         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4098         caps = dm->backlight_caps[bl_idx];
4099
4100         dm->brightness[bl_idx] = user_brightness;
4101         /* update scratch register */
4102         if (bl_idx == 0)
4103                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4104         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4105         link = (struct dc_link *)dm->backlight_link[bl_idx];
4106
4107         /* Change brightness based on AUX property */
4108         if (caps.aux_support) {
4109                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4110                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4111                 if (!rc)
4112                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4113         } else {
4114                 rc = dc_link_set_backlight_level(link, brightness, 0);
4115                 if (!rc)
4116                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4117         }
4118
4119         if (rc)
4120                 dm->actual_brightness[bl_idx] = user_brightness;
4121 }
4122
4123 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4124 {
4125         struct amdgpu_display_manager *dm = bl_get_data(bd);
4126         int i;
4127
4128         for (i = 0; i < dm->num_of_edps; i++) {
4129                 if (bd == dm->backlight_dev[i])
4130                         break;
4131         }
4132         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4133                 i = 0;
4134         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4135
4136         return 0;
4137 }
4138
4139 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4140                                          int bl_idx)
4141 {
4142         struct amdgpu_dm_backlight_caps caps;
4143         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4144
4145         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4146         caps = dm->backlight_caps[bl_idx];
4147
4148         if (caps.aux_support) {
4149                 u32 avg, peak;
4150                 bool rc;
4151
4152                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4153                 if (!rc)
4154                         return dm->brightness[bl_idx];
4155                 return convert_brightness_to_user(&caps, avg);
4156         } else {
4157                 int ret = dc_link_get_backlight_level(link);
4158
4159                 if (ret == DC_ERROR_UNEXPECTED)
4160                         return dm->brightness[bl_idx];
4161                 return convert_brightness_to_user(&caps, ret);
4162         }
4163 }
4164
4165 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4166 {
4167         struct amdgpu_display_manager *dm = bl_get_data(bd);
4168         int i;
4169
4170         for (i = 0; i < dm->num_of_edps; i++) {
4171                 if (bd == dm->backlight_dev[i])
4172                         break;
4173         }
4174         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4175                 i = 0;
4176         return amdgpu_dm_backlight_get_level(dm, i);
4177 }
4178
4179 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4180         .options = BL_CORE_SUSPENDRESUME,
4181         .get_brightness = amdgpu_dm_backlight_get_brightness,
4182         .update_status  = amdgpu_dm_backlight_update_status,
4183 };
4184
4185 static void
4186 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4187 {
4188         char bl_name[16];
4189         struct backlight_properties props = { 0 };
4190
4191         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4192         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4193
4194         if (!acpi_video_backlight_use_native()) {
4195                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4196                 /* Try registering an ACPI video backlight device instead. */
4197                 acpi_video_register_backlight();
4198                 return;
4199         }
4200
4201         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4202         props.brightness = AMDGPU_MAX_BL_LEVEL;
4203         props.type = BACKLIGHT_RAW;
4204
4205         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4206                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4207
4208         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4209                                                                        adev_to_drm(dm->adev)->dev,
4210                                                                        dm,
4211                                                                        &amdgpu_dm_backlight_ops,
4212                                                                        &props);
4213
4214         if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4215                 DRM_ERROR("DM: Backlight registration failed!\n");
4216         else
4217                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4218 }
4219
4220 static int initialize_plane(struct amdgpu_display_manager *dm,
4221                             struct amdgpu_mode_info *mode_info, int plane_id,
4222                             enum drm_plane_type plane_type,
4223                             const struct dc_plane_cap *plane_cap)
4224 {
4225         struct drm_plane *plane;
4226         unsigned long possible_crtcs;
4227         int ret = 0;
4228
4229         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4230         if (!plane) {
4231                 DRM_ERROR("KMS: Failed to allocate plane\n");
4232                 return -ENOMEM;
4233         }
4234         plane->type = plane_type;
4235
4236         /*
4237          * HACK: IGT tests expect that the primary plane for a CRTC
4238          * can only have one possible CRTC. Only expose support for
4239          * any CRTC if they're not going to be used as a primary plane
4240          * for a CRTC - like overlay or underlay planes.
4241          */
4242         possible_crtcs = 1 << plane_id;
4243         if (plane_id >= dm->dc->caps.max_streams)
4244                 possible_crtcs = 0xff;
4245
4246         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4247
4248         if (ret) {
4249                 DRM_ERROR("KMS: Failed to initialize plane\n");
4250                 kfree(plane);
4251                 return ret;
4252         }
4253
4254         if (mode_info)
4255                 mode_info->planes[plane_id] = plane;
4256
4257         return ret;
4258 }
4259
4260
4261 static void register_backlight_device(struct amdgpu_display_manager *dm,
4262                                       struct dc_link *link)
4263 {
4264         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4265             link->type != dc_connection_none) {
4266                 /*
4267                  * Event if registration failed, we should continue with
4268                  * DM initialization because not having a backlight control
4269                  * is better then a black screen.
4270                  */
4271                 if (!dm->backlight_dev[dm->num_of_edps])
4272                         amdgpu_dm_register_backlight_device(dm);
4273
4274                 if (dm->backlight_dev[dm->num_of_edps]) {
4275                         dm->backlight_link[dm->num_of_edps] = link;
4276                         dm->num_of_edps++;
4277                 }
4278         }
4279 }
4280
4281 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4282
4283 /*
4284  * In this architecture, the association
4285  * connector -> encoder -> crtc
4286  * id not really requried. The crtc and connector will hold the
4287  * display_index as an abstraction to use with DAL component
4288  *
4289  * Returns 0 on success
4290  */
4291 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4292 {
4293         struct amdgpu_display_manager *dm = &adev->dm;
4294         s32 i;
4295         struct amdgpu_dm_connector *aconnector = NULL;
4296         struct amdgpu_encoder *aencoder = NULL;
4297         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4298         u32 link_cnt;
4299         s32 primary_planes;
4300         enum dc_connection_type new_connection_type = dc_connection_none;
4301         const struct dc_plane_cap *plane;
4302         bool psr_feature_enabled = false;
4303         int max_overlay = dm->dc->caps.max_slave_planes;
4304
4305         dm->display_indexes_num = dm->dc->caps.max_streams;
4306         /* Update the actual used number of crtc */
4307         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4308
4309         amdgpu_dm_set_irq_funcs(adev);
4310
4311         link_cnt = dm->dc->caps.max_links;
4312         if (amdgpu_dm_mode_config_init(dm->adev)) {
4313                 DRM_ERROR("DM: Failed to initialize mode config\n");
4314                 return -EINVAL;
4315         }
4316
4317         /* There is one primary plane per CRTC */
4318         primary_planes = dm->dc->caps.max_streams;
4319         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4320
4321         /*
4322          * Initialize primary planes, implicit planes for legacy IOCTLS.
4323          * Order is reversed to match iteration order in atomic check.
4324          */
4325         for (i = (primary_planes - 1); i >= 0; i--) {
4326                 plane = &dm->dc->caps.planes[i];
4327
4328                 if (initialize_plane(dm, mode_info, i,
4329                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4330                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4331                         goto fail;
4332                 }
4333         }
4334
4335         /*
4336          * Initialize overlay planes, index starting after primary planes.
4337          * These planes have a higher DRM index than the primary planes since
4338          * they should be considered as having a higher z-order.
4339          * Order is reversed to match iteration order in atomic check.
4340          *
4341          * Only support DCN for now, and only expose one so we don't encourage
4342          * userspace to use up all the pipes.
4343          */
4344         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4345                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4346
4347                 /* Do not create overlay if MPO disabled */
4348                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4349                         break;
4350
4351                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4352                         continue;
4353
4354                 if (!plane->pixel_format_support.argb8888)
4355                         continue;
4356
4357                 if (max_overlay-- == 0)
4358                         break;
4359
4360                 if (initialize_plane(dm, NULL, primary_planes + i,
4361                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4362                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4363                         goto fail;
4364                 }
4365         }
4366
4367         for (i = 0; i < dm->dc->caps.max_streams; i++)
4368                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4369                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4370                         goto fail;
4371                 }
4372
4373         /* Use Outbox interrupt */
4374         switch (adev->ip_versions[DCE_HWIP][0]) {
4375         case IP_VERSION(3, 0, 0):
4376         case IP_VERSION(3, 1, 2):
4377         case IP_VERSION(3, 1, 3):
4378         case IP_VERSION(3, 1, 4):
4379         case IP_VERSION(3, 1, 5):
4380         case IP_VERSION(3, 1, 6):
4381         case IP_VERSION(3, 2, 0):
4382         case IP_VERSION(3, 2, 1):
4383         case IP_VERSION(2, 1, 0):
4384                 if (register_outbox_irq_handlers(dm->adev)) {
4385                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4386                         goto fail;
4387                 }
4388                 break;
4389         default:
4390                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4391                               adev->ip_versions[DCE_HWIP][0]);
4392         }
4393
4394         /* Determine whether to enable PSR support by default. */
4395         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4396                 switch (adev->ip_versions[DCE_HWIP][0]) {
4397                 case IP_VERSION(3, 1, 2):
4398                 case IP_VERSION(3, 1, 3):
4399                 case IP_VERSION(3, 1, 4):
4400                 case IP_VERSION(3, 1, 5):
4401                 case IP_VERSION(3, 1, 6):
4402                 case IP_VERSION(3, 2, 0):
4403                 case IP_VERSION(3, 2, 1):
4404                         psr_feature_enabled = true;
4405                         break;
4406                 default:
4407                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4408                         break;
4409                 }
4410         }
4411
4412         /* loops over all connectors on the board */
4413         for (i = 0; i < link_cnt; i++) {
4414                 struct dc_link *link = NULL;
4415
4416                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4417                         DRM_ERROR(
4418                                 "KMS: Cannot support more than %d display indexes\n",
4419                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4420                         continue;
4421                 }
4422
4423                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4424                 if (!aconnector)
4425                         goto fail;
4426
4427                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4428                 if (!aencoder)
4429                         goto fail;
4430
4431                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4432                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4433                         goto fail;
4434                 }
4435
4436                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4437                         DRM_ERROR("KMS: Failed to initialize connector\n");
4438                         goto fail;
4439                 }
4440
4441                 link = dc_get_link_at_index(dm->dc, i);
4442
4443                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4444                         DRM_ERROR("KMS: Failed to detect connector\n");
4445
4446                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4447                         emulated_link_detect(link);
4448                         amdgpu_dm_update_connector_after_detect(aconnector);
4449                 } else {
4450                         bool ret = false;
4451
4452                         mutex_lock(&dm->dc_lock);
4453                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4454                         mutex_unlock(&dm->dc_lock);
4455
4456                         if (ret) {
4457                                 amdgpu_dm_update_connector_after_detect(aconnector);
4458                                 register_backlight_device(dm, link);
4459
4460                                 if (dm->num_of_edps)
4461                                         update_connector_ext_caps(aconnector);
4462
4463                                 if (psr_feature_enabled)
4464                                         amdgpu_dm_set_psr_caps(link);
4465
4466                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4467                                  * PSR is also supported.
4468                                  */
4469                                 if (link->psr_settings.psr_feature_enabled)
4470                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4471                         }
4472                 }
4473                 amdgpu_set_panel_orientation(&aconnector->base);
4474         }
4475
4476         /* If we didn't find a panel, notify the acpi video detection */
4477         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4478                 acpi_video_report_nolcd();
4479
4480         /* Software is initialized. Now we can register interrupt handlers. */
4481         switch (adev->asic_type) {
4482 #if defined(CONFIG_DRM_AMD_DC_SI)
4483         case CHIP_TAHITI:
4484         case CHIP_PITCAIRN:
4485         case CHIP_VERDE:
4486         case CHIP_OLAND:
4487                 if (dce60_register_irq_handlers(dm->adev)) {
4488                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4489                         goto fail;
4490                 }
4491                 break;
4492 #endif
4493         case CHIP_BONAIRE:
4494         case CHIP_HAWAII:
4495         case CHIP_KAVERI:
4496         case CHIP_KABINI:
4497         case CHIP_MULLINS:
4498         case CHIP_TONGA:
4499         case CHIP_FIJI:
4500         case CHIP_CARRIZO:
4501         case CHIP_STONEY:
4502         case CHIP_POLARIS11:
4503         case CHIP_POLARIS10:
4504         case CHIP_POLARIS12:
4505         case CHIP_VEGAM:
4506         case CHIP_VEGA10:
4507         case CHIP_VEGA12:
4508         case CHIP_VEGA20:
4509                 if (dce110_register_irq_handlers(dm->adev)) {
4510                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4511                         goto fail;
4512                 }
4513                 break;
4514         default:
4515                 switch (adev->ip_versions[DCE_HWIP][0]) {
4516                 case IP_VERSION(1, 0, 0):
4517                 case IP_VERSION(1, 0, 1):
4518                 case IP_VERSION(2, 0, 2):
4519                 case IP_VERSION(2, 0, 3):
4520                 case IP_VERSION(2, 0, 0):
4521                 case IP_VERSION(2, 1, 0):
4522                 case IP_VERSION(3, 0, 0):
4523                 case IP_VERSION(3, 0, 2):
4524                 case IP_VERSION(3, 0, 3):
4525                 case IP_VERSION(3, 0, 1):
4526                 case IP_VERSION(3, 1, 2):
4527                 case IP_VERSION(3, 1, 3):
4528                 case IP_VERSION(3, 1, 4):
4529                 case IP_VERSION(3, 1, 5):
4530                 case IP_VERSION(3, 1, 6):
4531                 case IP_VERSION(3, 2, 0):
4532                 case IP_VERSION(3, 2, 1):
4533                         if (dcn10_register_irq_handlers(dm->adev)) {
4534                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4535                                 goto fail;
4536                         }
4537                         break;
4538                 default:
4539                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4540                                         adev->ip_versions[DCE_HWIP][0]);
4541                         goto fail;
4542                 }
4543                 break;
4544         }
4545
4546         return 0;
4547 fail:
4548         kfree(aencoder);
4549         kfree(aconnector);
4550
4551         return -EINVAL;
4552 }
4553
4554 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4555 {
4556         drm_atomic_private_obj_fini(&dm->atomic_obj);
4557         return;
4558 }
4559
4560 /******************************************************************************
4561  * amdgpu_display_funcs functions
4562  *****************************************************************************/
4563
4564 /*
4565  * dm_bandwidth_update - program display watermarks
4566  *
4567  * @adev: amdgpu_device pointer
4568  *
4569  * Calculate and program the display watermarks and line buffer allocation.
4570  */
4571 static void dm_bandwidth_update(struct amdgpu_device *adev)
4572 {
4573         /* TODO: implement later */
4574 }
4575
4576 static const struct amdgpu_display_funcs dm_display_funcs = {
4577         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4578         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4579         .backlight_set_level = NULL, /* never called for DC */
4580         .backlight_get_level = NULL, /* never called for DC */
4581         .hpd_sense = NULL,/* called unconditionally */
4582         .hpd_set_polarity = NULL, /* called unconditionally */
4583         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4584         .page_flip_get_scanoutpos =
4585                 dm_crtc_get_scanoutpos,/* called unconditionally */
4586         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4587         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4588 };
4589
4590 #if defined(CONFIG_DEBUG_KERNEL_DC)
4591
4592 static ssize_t s3_debug_store(struct device *device,
4593                               struct device_attribute *attr,
4594                               const char *buf,
4595                               size_t count)
4596 {
4597         int ret;
4598         int s3_state;
4599         struct drm_device *drm_dev = dev_get_drvdata(device);
4600         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4601
4602         ret = kstrtoint(buf, 0, &s3_state);
4603
4604         if (ret == 0) {
4605                 if (s3_state) {
4606                         dm_resume(adev);
4607                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4608                 } else
4609                         dm_suspend(adev);
4610         }
4611
4612         return ret == 0 ? count : 0;
4613 }
4614
4615 DEVICE_ATTR_WO(s3_debug);
4616
4617 #endif
4618
4619 static int dm_init_microcode(struct amdgpu_device *adev)
4620 {
4621         char *fw_name_dmub;
4622         int r;
4623
4624         switch (adev->ip_versions[DCE_HWIP][0]) {
4625         case IP_VERSION(2, 1, 0):
4626                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4627                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4628                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4629                 break;
4630         case IP_VERSION(3, 0, 0):
4631                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4632                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4633                 else
4634                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4635                 break;
4636         case IP_VERSION(3, 0, 1):
4637                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4638                 break;
4639         case IP_VERSION(3, 0, 2):
4640                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4641                 break;
4642         case IP_VERSION(3, 0, 3):
4643                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4644                 break;
4645         case IP_VERSION(3, 1, 2):
4646         case IP_VERSION(3, 1, 3):
4647                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4648                 break;
4649         case IP_VERSION(3, 1, 4):
4650                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4651                 break;
4652         case IP_VERSION(3, 1, 5):
4653                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4654                 break;
4655         case IP_VERSION(3, 1, 6):
4656                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4657                 break;
4658         case IP_VERSION(3, 2, 0):
4659                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4660                 break;
4661         case IP_VERSION(3, 2, 1):
4662                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4663                 break;
4664         default:
4665                 /* ASIC doesn't support DMUB. */
4666                 return 0;
4667         }
4668         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4669         if (r)
4670                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4671         return r;
4672 }
4673
4674 static int dm_early_init(void *handle)
4675 {
4676         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4677         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4678         struct atom_context *ctx = mode_info->atom_context;
4679         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4680         u16 data_offset;
4681
4682         /* if there is no object header, skip DM */
4683         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4684                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4685                 dev_info(adev->dev, "No object header, skipping DM\n");
4686                 return -ENOENT;
4687         }
4688
4689         switch (adev->asic_type) {
4690 #if defined(CONFIG_DRM_AMD_DC_SI)
4691         case CHIP_TAHITI:
4692         case CHIP_PITCAIRN:
4693         case CHIP_VERDE:
4694                 adev->mode_info.num_crtc = 6;
4695                 adev->mode_info.num_hpd = 6;
4696                 adev->mode_info.num_dig = 6;
4697                 break;
4698         case CHIP_OLAND:
4699                 adev->mode_info.num_crtc = 2;
4700                 adev->mode_info.num_hpd = 2;
4701                 adev->mode_info.num_dig = 2;
4702                 break;
4703 #endif
4704         case CHIP_BONAIRE:
4705         case CHIP_HAWAII:
4706                 adev->mode_info.num_crtc = 6;
4707                 adev->mode_info.num_hpd = 6;
4708                 adev->mode_info.num_dig = 6;
4709                 break;
4710         case CHIP_KAVERI:
4711                 adev->mode_info.num_crtc = 4;
4712                 adev->mode_info.num_hpd = 6;
4713                 adev->mode_info.num_dig = 7;
4714                 break;
4715         case CHIP_KABINI:
4716         case CHIP_MULLINS:
4717                 adev->mode_info.num_crtc = 2;
4718                 adev->mode_info.num_hpd = 6;
4719                 adev->mode_info.num_dig = 6;
4720                 break;
4721         case CHIP_FIJI:
4722         case CHIP_TONGA:
4723                 adev->mode_info.num_crtc = 6;
4724                 adev->mode_info.num_hpd = 6;
4725                 adev->mode_info.num_dig = 7;
4726                 break;
4727         case CHIP_CARRIZO:
4728                 adev->mode_info.num_crtc = 3;
4729                 adev->mode_info.num_hpd = 6;
4730                 adev->mode_info.num_dig = 9;
4731                 break;
4732         case CHIP_STONEY:
4733                 adev->mode_info.num_crtc = 2;
4734                 adev->mode_info.num_hpd = 6;
4735                 adev->mode_info.num_dig = 9;
4736                 break;
4737         case CHIP_POLARIS11:
4738         case CHIP_POLARIS12:
4739                 adev->mode_info.num_crtc = 5;
4740                 adev->mode_info.num_hpd = 5;
4741                 adev->mode_info.num_dig = 5;
4742                 break;
4743         case CHIP_POLARIS10:
4744         case CHIP_VEGAM:
4745                 adev->mode_info.num_crtc = 6;
4746                 adev->mode_info.num_hpd = 6;
4747                 adev->mode_info.num_dig = 6;
4748                 break;
4749         case CHIP_VEGA10:
4750         case CHIP_VEGA12:
4751         case CHIP_VEGA20:
4752                 adev->mode_info.num_crtc = 6;
4753                 adev->mode_info.num_hpd = 6;
4754                 adev->mode_info.num_dig = 6;
4755                 break;
4756         default:
4757
4758                 switch (adev->ip_versions[DCE_HWIP][0]) {
4759                 case IP_VERSION(2, 0, 2):
4760                 case IP_VERSION(3, 0, 0):
4761                         adev->mode_info.num_crtc = 6;
4762                         adev->mode_info.num_hpd = 6;
4763                         adev->mode_info.num_dig = 6;
4764                         break;
4765                 case IP_VERSION(2, 0, 0):
4766                 case IP_VERSION(3, 0, 2):
4767                         adev->mode_info.num_crtc = 5;
4768                         adev->mode_info.num_hpd = 5;
4769                         adev->mode_info.num_dig = 5;
4770                         break;
4771                 case IP_VERSION(2, 0, 3):
4772                 case IP_VERSION(3, 0, 3):
4773                         adev->mode_info.num_crtc = 2;
4774                         adev->mode_info.num_hpd = 2;
4775                         adev->mode_info.num_dig = 2;
4776                         break;
4777                 case IP_VERSION(1, 0, 0):
4778                 case IP_VERSION(1, 0, 1):
4779                 case IP_VERSION(3, 0, 1):
4780                 case IP_VERSION(2, 1, 0):
4781                 case IP_VERSION(3, 1, 2):
4782                 case IP_VERSION(3, 1, 3):
4783                 case IP_VERSION(3, 1, 4):
4784                 case IP_VERSION(3, 1, 5):
4785                 case IP_VERSION(3, 1, 6):
4786                 case IP_VERSION(3, 2, 0):
4787                 case IP_VERSION(3, 2, 1):
4788                         adev->mode_info.num_crtc = 4;
4789                         adev->mode_info.num_hpd = 4;
4790                         adev->mode_info.num_dig = 4;
4791                         break;
4792                 default:
4793                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4794                                         adev->ip_versions[DCE_HWIP][0]);
4795                         return -EINVAL;
4796                 }
4797                 break;
4798         }
4799
4800         if (adev->mode_info.funcs == NULL)
4801                 adev->mode_info.funcs = &dm_display_funcs;
4802
4803         /*
4804          * Note: Do NOT change adev->audio_endpt_rreg and
4805          * adev->audio_endpt_wreg because they are initialised in
4806          * amdgpu_device_init()
4807          */
4808 #if defined(CONFIG_DEBUG_KERNEL_DC)
4809         device_create_file(
4810                 adev_to_drm(adev)->dev,
4811                 &dev_attr_s3_debug);
4812 #endif
4813         adev->dc_enabled = true;
4814
4815         return dm_init_microcode(adev);
4816 }
4817
4818 static bool modereset_required(struct drm_crtc_state *crtc_state)
4819 {
4820         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4821 }
4822
4823 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4824 {
4825         drm_encoder_cleanup(encoder);
4826         kfree(encoder);
4827 }
4828
4829 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4830         .destroy = amdgpu_dm_encoder_destroy,
4831 };
4832
4833 static int
4834 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4835                             const enum surface_pixel_format format,
4836                             enum dc_color_space *color_space)
4837 {
4838         bool full_range;
4839
4840         *color_space = COLOR_SPACE_SRGB;
4841
4842         /* DRM color properties only affect non-RGB formats. */
4843         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4844                 return 0;
4845
4846         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4847
4848         switch (plane_state->color_encoding) {
4849         case DRM_COLOR_YCBCR_BT601:
4850                 if (full_range)
4851                         *color_space = COLOR_SPACE_YCBCR601;
4852                 else
4853                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4854                 break;
4855
4856         case DRM_COLOR_YCBCR_BT709:
4857                 if (full_range)
4858                         *color_space = COLOR_SPACE_YCBCR709;
4859                 else
4860                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4861                 break;
4862
4863         case DRM_COLOR_YCBCR_BT2020:
4864                 if (full_range)
4865                         *color_space = COLOR_SPACE_2020_YCBCR;
4866                 else
4867                         return -EINVAL;
4868                 break;
4869
4870         default:
4871                 return -EINVAL;
4872         }
4873
4874         return 0;
4875 }
4876
4877 static int
4878 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4879                             const struct drm_plane_state *plane_state,
4880                             const u64 tiling_flags,
4881                             struct dc_plane_info *plane_info,
4882                             struct dc_plane_address *address,
4883                             bool tmz_surface,
4884                             bool force_disable_dcc)
4885 {
4886         const struct drm_framebuffer *fb = plane_state->fb;
4887         const struct amdgpu_framebuffer *afb =
4888                 to_amdgpu_framebuffer(plane_state->fb);
4889         int ret;
4890
4891         memset(plane_info, 0, sizeof(*plane_info));
4892
4893         switch (fb->format->format) {
4894         case DRM_FORMAT_C8:
4895                 plane_info->format =
4896                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4897                 break;
4898         case DRM_FORMAT_RGB565:
4899                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4900                 break;
4901         case DRM_FORMAT_XRGB8888:
4902         case DRM_FORMAT_ARGB8888:
4903                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4904                 break;
4905         case DRM_FORMAT_XRGB2101010:
4906         case DRM_FORMAT_ARGB2101010:
4907                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4908                 break;
4909         case DRM_FORMAT_XBGR2101010:
4910         case DRM_FORMAT_ABGR2101010:
4911                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4912                 break;
4913         case DRM_FORMAT_XBGR8888:
4914         case DRM_FORMAT_ABGR8888:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4916                 break;
4917         case DRM_FORMAT_NV21:
4918                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4919                 break;
4920         case DRM_FORMAT_NV12:
4921                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4922                 break;
4923         case DRM_FORMAT_P010:
4924                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4925                 break;
4926         case DRM_FORMAT_XRGB16161616F:
4927         case DRM_FORMAT_ARGB16161616F:
4928                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4929                 break;
4930         case DRM_FORMAT_XBGR16161616F:
4931         case DRM_FORMAT_ABGR16161616F:
4932                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4933                 break;
4934         case DRM_FORMAT_XRGB16161616:
4935         case DRM_FORMAT_ARGB16161616:
4936                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4937                 break;
4938         case DRM_FORMAT_XBGR16161616:
4939         case DRM_FORMAT_ABGR16161616:
4940                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4941                 break;
4942         default:
4943                 DRM_ERROR(
4944                         "Unsupported screen format %p4cc\n",
4945                         &fb->format->format);
4946                 return -EINVAL;
4947         }
4948
4949         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4950         case DRM_MODE_ROTATE_0:
4951                 plane_info->rotation = ROTATION_ANGLE_0;
4952                 break;
4953         case DRM_MODE_ROTATE_90:
4954                 plane_info->rotation = ROTATION_ANGLE_90;
4955                 break;
4956         case DRM_MODE_ROTATE_180:
4957                 plane_info->rotation = ROTATION_ANGLE_180;
4958                 break;
4959         case DRM_MODE_ROTATE_270:
4960                 plane_info->rotation = ROTATION_ANGLE_270;
4961                 break;
4962         default:
4963                 plane_info->rotation = ROTATION_ANGLE_0;
4964                 break;
4965         }
4966
4967
4968         plane_info->visible = true;
4969         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4970
4971         plane_info->layer_index = plane_state->normalized_zpos;
4972
4973         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4974                                           &plane_info->color_space);
4975         if (ret)
4976                 return ret;
4977
4978         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4979                                            plane_info->rotation, tiling_flags,
4980                                            &plane_info->tiling_info,
4981                                            &plane_info->plane_size,
4982                                            &plane_info->dcc, address,
4983                                            tmz_surface, force_disable_dcc);
4984         if (ret)
4985                 return ret;
4986
4987         amdgpu_dm_plane_fill_blending_from_plane_state(
4988                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4989                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4990
4991         return 0;
4992 }
4993
4994 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4995                                     struct dc_plane_state *dc_plane_state,
4996                                     struct drm_plane_state *plane_state,
4997                                     struct drm_crtc_state *crtc_state)
4998 {
4999         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5000         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5001         struct dc_scaling_info scaling_info;
5002         struct dc_plane_info plane_info;
5003         int ret;
5004         bool force_disable_dcc = false;
5005
5006         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5007         if (ret)
5008                 return ret;
5009
5010         dc_plane_state->src_rect = scaling_info.src_rect;
5011         dc_plane_state->dst_rect = scaling_info.dst_rect;
5012         dc_plane_state->clip_rect = scaling_info.clip_rect;
5013         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5014
5015         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5016         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5017                                           afb->tiling_flags,
5018                                           &plane_info,
5019                                           &dc_plane_state->address,
5020                                           afb->tmz_surface,
5021                                           force_disable_dcc);
5022         if (ret)
5023                 return ret;
5024
5025         dc_plane_state->format = plane_info.format;
5026         dc_plane_state->color_space = plane_info.color_space;
5027         dc_plane_state->format = plane_info.format;
5028         dc_plane_state->plane_size = plane_info.plane_size;
5029         dc_plane_state->rotation = plane_info.rotation;
5030         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5031         dc_plane_state->stereo_format = plane_info.stereo_format;
5032         dc_plane_state->tiling_info = plane_info.tiling_info;
5033         dc_plane_state->visible = plane_info.visible;
5034         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5035         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5036         dc_plane_state->global_alpha = plane_info.global_alpha;
5037         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5038         dc_plane_state->dcc = plane_info.dcc;
5039         dc_plane_state->layer_index = plane_info.layer_index;
5040         dc_plane_state->flip_int_enabled = true;
5041
5042         /*
5043          * Always set input transfer function, since plane state is refreshed
5044          * every time.
5045          */
5046         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5047         if (ret)
5048                 return ret;
5049
5050         return 0;
5051 }
5052
5053 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5054                                       struct rect *dirty_rect, int32_t x,
5055                                       s32 y, s32 width, s32 height,
5056                                       int *i, bool ffu)
5057 {
5058         if (*i > DC_MAX_DIRTY_RECTS)
5059                 return;
5060
5061         if (*i == DC_MAX_DIRTY_RECTS)
5062                 goto out;
5063
5064         dirty_rect->x = x;
5065         dirty_rect->y = y;
5066         dirty_rect->width = width;
5067         dirty_rect->height = height;
5068
5069         if (ffu)
5070                 drm_dbg(plane->dev,
5071                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5072                         plane->base.id, width, height);
5073         else
5074                 drm_dbg(plane->dev,
5075                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5076                         plane->base.id, x, y, width, height);
5077
5078 out:
5079         (*i)++;
5080 }
5081
5082 /**
5083  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5084  *
5085  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5086  *         remote fb
5087  * @old_plane_state: Old state of @plane
5088  * @new_plane_state: New state of @plane
5089  * @crtc_state: New state of CRTC connected to the @plane
5090  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5091  * @dirty_regions_changed: dirty regions changed
5092  *
5093  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5094  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5095  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5096  * amdgpu_dm's.
5097  *
5098  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5099  * plane with regions that require flushing to the eDP remote buffer. In
5100  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5101  * implicitly provide damage clips without any client support via the plane
5102  * bounds.
5103  */
5104 static void fill_dc_dirty_rects(struct drm_plane *plane,
5105                                 struct drm_plane_state *old_plane_state,
5106                                 struct drm_plane_state *new_plane_state,
5107                                 struct drm_crtc_state *crtc_state,
5108                                 struct dc_flip_addrs *flip_addrs,
5109                                 bool *dirty_regions_changed)
5110 {
5111         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5112         struct rect *dirty_rects = flip_addrs->dirty_rects;
5113         u32 num_clips;
5114         struct drm_mode_rect *clips;
5115         bool bb_changed;
5116         bool fb_changed;
5117         u32 i = 0;
5118         *dirty_regions_changed = false;
5119
5120         /*
5121          * Cursor plane has it's own dirty rect update interface. See
5122          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5123          */
5124         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5125                 return;
5126
5127         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5128         clips = drm_plane_get_damage_clips(new_plane_state);
5129
5130         if (!dm_crtc_state->mpo_requested) {
5131                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5132                         goto ffu;
5133
5134                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5135                         fill_dc_dirty_rect(new_plane_state->plane,
5136                                            &dirty_rects[flip_addrs->dirty_rect_count],
5137                                            clips->x1, clips->y1,
5138                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5139                                            &flip_addrs->dirty_rect_count,
5140                                            false);
5141                 return;
5142         }
5143
5144         /*
5145          * MPO is requested. Add entire plane bounding box to dirty rects if
5146          * flipped to or damaged.
5147          *
5148          * If plane is moved or resized, also add old bounding box to dirty
5149          * rects.
5150          */
5151         fb_changed = old_plane_state->fb->base.id !=
5152                      new_plane_state->fb->base.id;
5153         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5154                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5155                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5156                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5157
5158         drm_dbg(plane->dev,
5159                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5160                 new_plane_state->plane->base.id,
5161                 bb_changed, fb_changed, num_clips);
5162
5163         *dirty_regions_changed = bb_changed;
5164
5165         if (bb_changed) {
5166                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5167                                    new_plane_state->crtc_x,
5168                                    new_plane_state->crtc_y,
5169                                    new_plane_state->crtc_w,
5170                                    new_plane_state->crtc_h, &i, false);
5171
5172                 /* Add old plane bounding-box if plane is moved or resized */
5173                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5174                                    old_plane_state->crtc_x,
5175                                    old_plane_state->crtc_y,
5176                                    old_plane_state->crtc_w,
5177                                    old_plane_state->crtc_h, &i, false);
5178         }
5179
5180         if (num_clips) {
5181                 for (; i < num_clips; clips++)
5182                         fill_dc_dirty_rect(new_plane_state->plane,
5183                                            &dirty_rects[i], clips->x1,
5184                                            clips->y1, clips->x2 - clips->x1,
5185                                            clips->y2 - clips->y1, &i, false);
5186         } else if (fb_changed && !bb_changed) {
5187                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5188                                    new_plane_state->crtc_x,
5189                                    new_plane_state->crtc_y,
5190                                    new_plane_state->crtc_w,
5191                                    new_plane_state->crtc_h, &i, false);
5192         }
5193
5194         if (i > DC_MAX_DIRTY_RECTS)
5195                 goto ffu;
5196
5197         flip_addrs->dirty_rect_count = i;
5198         return;
5199
5200 ffu:
5201         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5202                            dm_crtc_state->base.mode.crtc_hdisplay,
5203                            dm_crtc_state->base.mode.crtc_vdisplay,
5204                            &flip_addrs->dirty_rect_count, true);
5205 }
5206
5207 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5208                                            const struct dm_connector_state *dm_state,
5209                                            struct dc_stream_state *stream)
5210 {
5211         enum amdgpu_rmx_type rmx_type;
5212
5213         struct rect src = { 0 }; /* viewport in composition space*/
5214         struct rect dst = { 0 }; /* stream addressable area */
5215
5216         /* no mode. nothing to be done */
5217         if (!mode)
5218                 return;
5219
5220         /* Full screen scaling by default */
5221         src.width = mode->hdisplay;
5222         src.height = mode->vdisplay;
5223         dst.width = stream->timing.h_addressable;
5224         dst.height = stream->timing.v_addressable;
5225
5226         if (dm_state) {
5227                 rmx_type = dm_state->scaling;
5228                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5229                         if (src.width * dst.height <
5230                                         src.height * dst.width) {
5231                                 /* height needs less upscaling/more downscaling */
5232                                 dst.width = src.width *
5233                                                 dst.height / src.height;
5234                         } else {
5235                                 /* width needs less upscaling/more downscaling */
5236                                 dst.height = src.height *
5237                                                 dst.width / src.width;
5238                         }
5239                 } else if (rmx_type == RMX_CENTER) {
5240                         dst = src;
5241                 }
5242
5243                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5244                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5245
5246                 if (dm_state->underscan_enable) {
5247                         dst.x += dm_state->underscan_hborder / 2;
5248                         dst.y += dm_state->underscan_vborder / 2;
5249                         dst.width -= dm_state->underscan_hborder;
5250                         dst.height -= dm_state->underscan_vborder;
5251                 }
5252         }
5253
5254         stream->src = src;
5255         stream->dst = dst;
5256
5257         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5258                       dst.x, dst.y, dst.width, dst.height);
5259
5260 }
5261
5262 static enum dc_color_depth
5263 convert_color_depth_from_display_info(const struct drm_connector *connector,
5264                                       bool is_y420, int requested_bpc)
5265 {
5266         u8 bpc;
5267
5268         if (is_y420) {
5269                 bpc = 8;
5270
5271                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5272                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5273                         bpc = 16;
5274                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5275                         bpc = 12;
5276                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5277                         bpc = 10;
5278         } else {
5279                 bpc = (uint8_t)connector->display_info.bpc;
5280                 /* Assume 8 bpc by default if no bpc is specified. */
5281                 bpc = bpc ? bpc : 8;
5282         }
5283
5284         if (requested_bpc > 0) {
5285                 /*
5286                  * Cap display bpc based on the user requested value.
5287                  *
5288                  * The value for state->max_bpc may not correctly updated
5289                  * depending on when the connector gets added to the state
5290                  * or if this was called outside of atomic check, so it
5291                  * can't be used directly.
5292                  */
5293                 bpc = min_t(u8, bpc, requested_bpc);
5294
5295                 /* Round down to the nearest even number. */
5296                 bpc = bpc - (bpc & 1);
5297         }
5298
5299         switch (bpc) {
5300         case 0:
5301                 /*
5302                  * Temporary Work around, DRM doesn't parse color depth for
5303                  * EDID revision before 1.4
5304                  * TODO: Fix edid parsing
5305                  */
5306                 return COLOR_DEPTH_888;
5307         case 6:
5308                 return COLOR_DEPTH_666;
5309         case 8:
5310                 return COLOR_DEPTH_888;
5311         case 10:
5312                 return COLOR_DEPTH_101010;
5313         case 12:
5314                 return COLOR_DEPTH_121212;
5315         case 14:
5316                 return COLOR_DEPTH_141414;
5317         case 16:
5318                 return COLOR_DEPTH_161616;
5319         default:
5320                 return COLOR_DEPTH_UNDEFINED;
5321         }
5322 }
5323
5324 static enum dc_aspect_ratio
5325 get_aspect_ratio(const struct drm_display_mode *mode_in)
5326 {
5327         /* 1-1 mapping, since both enums follow the HDMI spec. */
5328         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5329 }
5330
5331 static enum dc_color_space
5332 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5333 {
5334         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5335
5336         switch (dc_crtc_timing->pixel_encoding) {
5337         case PIXEL_ENCODING_YCBCR422:
5338         case PIXEL_ENCODING_YCBCR444:
5339         case PIXEL_ENCODING_YCBCR420:
5340         {
5341                 /*
5342                  * 27030khz is the separation point between HDTV and SDTV
5343                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5344                  * respectively
5345                  */
5346                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5347                         if (dc_crtc_timing->flags.Y_ONLY)
5348                                 color_space =
5349                                         COLOR_SPACE_YCBCR709_LIMITED;
5350                         else
5351                                 color_space = COLOR_SPACE_YCBCR709;
5352                 } else {
5353                         if (dc_crtc_timing->flags.Y_ONLY)
5354                                 color_space =
5355                                         COLOR_SPACE_YCBCR601_LIMITED;
5356                         else
5357                                 color_space = COLOR_SPACE_YCBCR601;
5358                 }
5359
5360         }
5361         break;
5362         case PIXEL_ENCODING_RGB:
5363                 color_space = COLOR_SPACE_SRGB;
5364                 break;
5365
5366         default:
5367                 WARN_ON(1);
5368                 break;
5369         }
5370
5371         return color_space;
5372 }
5373
5374 static bool adjust_colour_depth_from_display_info(
5375         struct dc_crtc_timing *timing_out,
5376         const struct drm_display_info *info)
5377 {
5378         enum dc_color_depth depth = timing_out->display_color_depth;
5379         int normalized_clk;
5380         do {
5381                 normalized_clk = timing_out->pix_clk_100hz / 10;
5382                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5383                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5384                         normalized_clk /= 2;
5385                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5386                 switch (depth) {
5387                 case COLOR_DEPTH_888:
5388                         break;
5389                 case COLOR_DEPTH_101010:
5390                         normalized_clk = (normalized_clk * 30) / 24;
5391                         break;
5392                 case COLOR_DEPTH_121212:
5393                         normalized_clk = (normalized_clk * 36) / 24;
5394                         break;
5395                 case COLOR_DEPTH_161616:
5396                         normalized_clk = (normalized_clk * 48) / 24;
5397                         break;
5398                 default:
5399                         /* The above depths are the only ones valid for HDMI. */
5400                         return false;
5401                 }
5402                 if (normalized_clk <= info->max_tmds_clock) {
5403                         timing_out->display_color_depth = depth;
5404                         return true;
5405                 }
5406         } while (--depth > COLOR_DEPTH_666);
5407         return false;
5408 }
5409
5410 static void fill_stream_properties_from_drm_display_mode(
5411         struct dc_stream_state *stream,
5412         const struct drm_display_mode *mode_in,
5413         const struct drm_connector *connector,
5414         const struct drm_connector_state *connector_state,
5415         const struct dc_stream_state *old_stream,
5416         int requested_bpc)
5417 {
5418         struct dc_crtc_timing *timing_out = &stream->timing;
5419         const struct drm_display_info *info = &connector->display_info;
5420         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5421         struct hdmi_vendor_infoframe hv_frame;
5422         struct hdmi_avi_infoframe avi_frame;
5423
5424         memset(&hv_frame, 0, sizeof(hv_frame));
5425         memset(&avi_frame, 0, sizeof(avi_frame));
5426
5427         timing_out->h_border_left = 0;
5428         timing_out->h_border_right = 0;
5429         timing_out->v_border_top = 0;
5430         timing_out->v_border_bottom = 0;
5431         /* TODO: un-hardcode */
5432         if (drm_mode_is_420_only(info, mode_in)
5433                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5434                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5435         else if (drm_mode_is_420_also(info, mode_in)
5436                         && aconnector->force_yuv420_output)
5437                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5438         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5439                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5440                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5441         else
5442                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5443
5444         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5445         timing_out->display_color_depth = convert_color_depth_from_display_info(
5446                 connector,
5447                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5448                 requested_bpc);
5449         timing_out->scan_type = SCANNING_TYPE_NODATA;
5450         timing_out->hdmi_vic = 0;
5451
5452         if (old_stream) {
5453                 timing_out->vic = old_stream->timing.vic;
5454                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5455                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5456         } else {
5457                 timing_out->vic = drm_match_cea_mode(mode_in);
5458                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5459                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5460                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5461                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5462         }
5463
5464         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5465                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5466                 timing_out->vic = avi_frame.video_code;
5467                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5468                 timing_out->hdmi_vic = hv_frame.vic;
5469         }
5470
5471         if (is_freesync_video_mode(mode_in, aconnector)) {
5472                 timing_out->h_addressable = mode_in->hdisplay;
5473                 timing_out->h_total = mode_in->htotal;
5474                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5475                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5476                 timing_out->v_total = mode_in->vtotal;
5477                 timing_out->v_addressable = mode_in->vdisplay;
5478                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5479                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5480                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5481         } else {
5482                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5483                 timing_out->h_total = mode_in->crtc_htotal;
5484                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5485                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5486                 timing_out->v_total = mode_in->crtc_vtotal;
5487                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5488                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5489                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5490                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5491         }
5492
5493         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5494
5495         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5496         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5497         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5498                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5499                     drm_mode_is_420_also(info, mode_in) &&
5500                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5501                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5502                         adjust_colour_depth_from_display_info(timing_out, info);
5503                 }
5504         }
5505
5506         stream->output_color_space = get_output_color_space(timing_out);
5507 }
5508
5509 static void fill_audio_info(struct audio_info *audio_info,
5510                             const struct drm_connector *drm_connector,
5511                             const struct dc_sink *dc_sink)
5512 {
5513         int i = 0;
5514         int cea_revision = 0;
5515         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5516
5517         audio_info->manufacture_id = edid_caps->manufacturer_id;
5518         audio_info->product_id = edid_caps->product_id;
5519
5520         cea_revision = drm_connector->display_info.cea_rev;
5521
5522         strscpy(audio_info->display_name,
5523                 edid_caps->display_name,
5524                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5525
5526         if (cea_revision >= 3) {
5527                 audio_info->mode_count = edid_caps->audio_mode_count;
5528
5529                 for (i = 0; i < audio_info->mode_count; ++i) {
5530                         audio_info->modes[i].format_code =
5531                                         (enum audio_format_code)
5532                                         (edid_caps->audio_modes[i].format_code);
5533                         audio_info->modes[i].channel_count =
5534                                         edid_caps->audio_modes[i].channel_count;
5535                         audio_info->modes[i].sample_rates.all =
5536                                         edid_caps->audio_modes[i].sample_rate;
5537                         audio_info->modes[i].sample_size =
5538                                         edid_caps->audio_modes[i].sample_size;
5539                 }
5540         }
5541
5542         audio_info->flags.all = edid_caps->speaker_flags;
5543
5544         /* TODO: We only check for the progressive mode, check for interlace mode too */
5545         if (drm_connector->latency_present[0]) {
5546                 audio_info->video_latency = drm_connector->video_latency[0];
5547                 audio_info->audio_latency = drm_connector->audio_latency[0];
5548         }
5549
5550         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5551
5552 }
5553
5554 static void
5555 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5556                                       struct drm_display_mode *dst_mode)
5557 {
5558         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5559         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5560         dst_mode->crtc_clock = src_mode->crtc_clock;
5561         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5562         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5563         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5564         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5565         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5566         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5567         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5568         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5569         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5570         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5571         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5572 }
5573
5574 static void
5575 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5576                                         const struct drm_display_mode *native_mode,
5577                                         bool scale_enabled)
5578 {
5579         if (scale_enabled) {
5580                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5581         } else if (native_mode->clock == drm_mode->clock &&
5582                         native_mode->htotal == drm_mode->htotal &&
5583                         native_mode->vtotal == drm_mode->vtotal) {
5584                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5585         } else {
5586                 /* no scaling nor amdgpu inserted, no need to patch */
5587         }
5588 }
5589
5590 static struct dc_sink *
5591 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5592 {
5593         struct dc_sink_init_data sink_init_data = { 0 };
5594         struct dc_sink *sink = NULL;
5595         sink_init_data.link = aconnector->dc_link;
5596         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5597
5598         sink = dc_sink_create(&sink_init_data);
5599         if (!sink) {
5600                 DRM_ERROR("Failed to create sink!\n");
5601                 return NULL;
5602         }
5603         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5604
5605         return sink;
5606 }
5607
5608 static void set_multisync_trigger_params(
5609                 struct dc_stream_state *stream)
5610 {
5611         struct dc_stream_state *master = NULL;
5612
5613         if (stream->triggered_crtc_reset.enabled) {
5614                 master = stream->triggered_crtc_reset.event_source;
5615                 stream->triggered_crtc_reset.event =
5616                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5617                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5618                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5619         }
5620 }
5621
5622 static void set_master_stream(struct dc_stream_state *stream_set[],
5623                               int stream_count)
5624 {
5625         int j, highest_rfr = 0, master_stream = 0;
5626
5627         for (j = 0;  j < stream_count; j++) {
5628                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5629                         int refresh_rate = 0;
5630
5631                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5632                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5633                         if (refresh_rate > highest_rfr) {
5634                                 highest_rfr = refresh_rate;
5635                                 master_stream = j;
5636                         }
5637                 }
5638         }
5639         for (j = 0;  j < stream_count; j++) {
5640                 if (stream_set[j])
5641                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5642         }
5643 }
5644
5645 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5646 {
5647         int i = 0;
5648         struct dc_stream_state *stream;
5649
5650         if (context->stream_count < 2)
5651                 return;
5652         for (i = 0; i < context->stream_count ; i++) {
5653                 if (!context->streams[i])
5654                         continue;
5655                 /*
5656                  * TODO: add a function to read AMD VSDB bits and set
5657                  * crtc_sync_master.multi_sync_enabled flag
5658                  * For now it's set to false
5659                  */
5660         }
5661
5662         set_master_stream(context->streams, context->stream_count);
5663
5664         for (i = 0; i < context->stream_count ; i++) {
5665                 stream = context->streams[i];
5666
5667                 if (!stream)
5668                         continue;
5669
5670                 set_multisync_trigger_params(stream);
5671         }
5672 }
5673
5674 /**
5675  * DOC: FreeSync Video
5676  *
5677  * When a userspace application wants to play a video, the content follows a
5678  * standard format definition that usually specifies the FPS for that format.
5679  * The below list illustrates some video format and the expected FPS,
5680  * respectively:
5681  *
5682  * - TV/NTSC (23.976 FPS)
5683  * - Cinema (24 FPS)
5684  * - TV/PAL (25 FPS)
5685  * - TV/NTSC (29.97 FPS)
5686  * - TV/NTSC (30 FPS)
5687  * - Cinema HFR (48 FPS)
5688  * - TV/PAL (50 FPS)
5689  * - Commonly used (60 FPS)
5690  * - Multiples of 24 (48,72,96 FPS)
5691  *
5692  * The list of standards video format is not huge and can be added to the
5693  * connector modeset list beforehand. With that, userspace can leverage
5694  * FreeSync to extends the front porch in order to attain the target refresh
5695  * rate. Such a switch will happen seamlessly, without screen blanking or
5696  * reprogramming of the output in any other way. If the userspace requests a
5697  * modesetting change compatible with FreeSync modes that only differ in the
5698  * refresh rate, DC will skip the full update and avoid blink during the
5699  * transition. For example, the video player can change the modesetting from
5700  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5701  * causing any display blink. This same concept can be applied to a mode
5702  * setting change.
5703  */
5704 static struct drm_display_mode *
5705 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5706                 bool use_probed_modes)
5707 {
5708         struct drm_display_mode *m, *m_pref = NULL;
5709         u16 current_refresh, highest_refresh;
5710         struct list_head *list_head = use_probed_modes ?
5711                 &aconnector->base.probed_modes :
5712                 &aconnector->base.modes;
5713
5714         if (aconnector->freesync_vid_base.clock != 0)
5715                 return &aconnector->freesync_vid_base;
5716
5717         /* Find the preferred mode */
5718         list_for_each_entry (m, list_head, head) {
5719                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5720                         m_pref = m;
5721                         break;
5722                 }
5723         }
5724
5725         if (!m_pref) {
5726                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5727                 m_pref = list_first_entry_or_null(
5728                                 &aconnector->base.modes, struct drm_display_mode, head);
5729                 if (!m_pref) {
5730                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5731                         return NULL;
5732                 }
5733         }
5734
5735         highest_refresh = drm_mode_vrefresh(m_pref);
5736
5737         /*
5738          * Find the mode with highest refresh rate with same resolution.
5739          * For some monitors, preferred mode is not the mode with highest
5740          * supported refresh rate.
5741          */
5742         list_for_each_entry (m, list_head, head) {
5743                 current_refresh  = drm_mode_vrefresh(m);
5744
5745                 if (m->hdisplay == m_pref->hdisplay &&
5746                     m->vdisplay == m_pref->vdisplay &&
5747                     highest_refresh < current_refresh) {
5748                         highest_refresh = current_refresh;
5749                         m_pref = m;
5750                 }
5751         }
5752
5753         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5754         return m_pref;
5755 }
5756
5757 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5758                 struct amdgpu_dm_connector *aconnector)
5759 {
5760         struct drm_display_mode *high_mode;
5761         int timing_diff;
5762
5763         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5764         if (!high_mode || !mode)
5765                 return false;
5766
5767         timing_diff = high_mode->vtotal - mode->vtotal;
5768
5769         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5770             high_mode->hdisplay != mode->hdisplay ||
5771             high_mode->vdisplay != mode->vdisplay ||
5772             high_mode->hsync_start != mode->hsync_start ||
5773             high_mode->hsync_end != mode->hsync_end ||
5774             high_mode->htotal != mode->htotal ||
5775             high_mode->hskew != mode->hskew ||
5776             high_mode->vscan != mode->vscan ||
5777             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5778             high_mode->vsync_end - mode->vsync_end != timing_diff)
5779                 return false;
5780         else
5781                 return true;
5782 }
5783
5784 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5785                             struct dc_sink *sink, struct dc_stream_state *stream,
5786                             struct dsc_dec_dpcd_caps *dsc_caps)
5787 {
5788         stream->timing.flags.DSC = 0;
5789         dsc_caps->is_dsc_supported = false;
5790
5791         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5792             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5793                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5794                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5795                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5796                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5797                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5798                                 dsc_caps);
5799         }
5800 }
5801
5802
5803 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5804                                     struct dc_sink *sink, struct dc_stream_state *stream,
5805                                     struct dsc_dec_dpcd_caps *dsc_caps,
5806                                     uint32_t max_dsc_target_bpp_limit_override)
5807 {
5808         const struct dc_link_settings *verified_link_cap = NULL;
5809         u32 link_bw_in_kbps;
5810         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5811         struct dc *dc = sink->ctx->dc;
5812         struct dc_dsc_bw_range bw_range = {0};
5813         struct dc_dsc_config dsc_cfg = {0};
5814         struct dc_dsc_config_options dsc_options = {0};
5815
5816         dc_dsc_get_default_config_option(dc, &dsc_options);
5817         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5818
5819         verified_link_cap = dc_link_get_link_cap(stream->link);
5820         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5821         edp_min_bpp_x16 = 8 * 16;
5822         edp_max_bpp_x16 = 8 * 16;
5823
5824         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5825                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5826
5827         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5828                 edp_min_bpp_x16 = edp_max_bpp_x16;
5829
5830         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5831                                 dc->debug.dsc_min_slice_height_override,
5832                                 edp_min_bpp_x16, edp_max_bpp_x16,
5833                                 dsc_caps,
5834                                 &stream->timing,
5835                                 &bw_range)) {
5836
5837                 if (bw_range.max_kbps < link_bw_in_kbps) {
5838                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5839                                         dsc_caps,
5840                                         &dsc_options,
5841                                         0,
5842                                         &stream->timing,
5843                                         &dsc_cfg)) {
5844                                 stream->timing.dsc_cfg = dsc_cfg;
5845                                 stream->timing.flags.DSC = 1;
5846                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5847                         }
5848                         return;
5849                 }
5850         }
5851
5852         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5853                                 dsc_caps,
5854                                 &dsc_options,
5855                                 link_bw_in_kbps,
5856                                 &stream->timing,
5857                                 &dsc_cfg)) {
5858                 stream->timing.dsc_cfg = dsc_cfg;
5859                 stream->timing.flags.DSC = 1;
5860         }
5861 }
5862
5863
5864 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5865                                         struct dc_sink *sink, struct dc_stream_state *stream,
5866                                         struct dsc_dec_dpcd_caps *dsc_caps)
5867 {
5868         struct drm_connector *drm_connector = &aconnector->base;
5869         u32 link_bandwidth_kbps;
5870         struct dc *dc = sink->ctx->dc;
5871         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5872         u32 dsc_max_supported_bw_in_kbps;
5873         u32 max_dsc_target_bpp_limit_override =
5874                 drm_connector->display_info.max_dsc_bpp;
5875         struct dc_dsc_config_options dsc_options = {0};
5876
5877         dc_dsc_get_default_config_option(dc, &dsc_options);
5878         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5879
5880         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5881                                                         dc_link_get_link_cap(aconnector->dc_link));
5882
5883         /* Set DSC policy according to dsc_clock_en */
5884         dc_dsc_policy_set_enable_dsc_when_not_needed(
5885                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5886
5887         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5888             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5889             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5890
5891                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5892
5893         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5894                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5895                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5896                                                 dsc_caps,
5897                                                 &dsc_options,
5898                                                 link_bandwidth_kbps,
5899                                                 &stream->timing,
5900                                                 &stream->timing.dsc_cfg)) {
5901                                 stream->timing.flags.DSC = 1;
5902                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5903                         }
5904                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5905                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5906                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5907                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5908
5909                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5910                                         max_supported_bw_in_kbps > 0 &&
5911                                         dsc_max_supported_bw_in_kbps > 0)
5912                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5913                                                 dsc_caps,
5914                                                 &dsc_options,
5915                                                 dsc_max_supported_bw_in_kbps,
5916                                                 &stream->timing,
5917                                                 &stream->timing.dsc_cfg)) {
5918                                         stream->timing.flags.DSC = 1;
5919                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5920                                                                          __func__, drm_connector->name);
5921                                 }
5922                 }
5923         }
5924
5925         /* Overwrite the stream flag if DSC is enabled through debugfs */
5926         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5927                 stream->timing.flags.DSC = 1;
5928
5929         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5930                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5931
5932         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5933                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5934
5935         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5936                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5937 }
5938
5939 static struct dc_stream_state *
5940 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5941                        const struct drm_display_mode *drm_mode,
5942                        const struct dm_connector_state *dm_state,
5943                        const struct dc_stream_state *old_stream,
5944                        int requested_bpc)
5945 {
5946         struct drm_display_mode *preferred_mode = NULL;
5947         struct drm_connector *drm_connector;
5948         const struct drm_connector_state *con_state =
5949                 dm_state ? &dm_state->base : NULL;
5950         struct dc_stream_state *stream = NULL;
5951         struct drm_display_mode mode;
5952         struct drm_display_mode saved_mode;
5953         struct drm_display_mode *freesync_mode = NULL;
5954         bool native_mode_found = false;
5955         bool recalculate_timing = false;
5956         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5957         int mode_refresh;
5958         int preferred_refresh = 0;
5959         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5960         struct dsc_dec_dpcd_caps dsc_caps;
5961
5962         struct dc_sink *sink = NULL;
5963
5964         drm_mode_init(&mode, drm_mode);
5965         memset(&saved_mode, 0, sizeof(saved_mode));
5966
5967         if (aconnector == NULL) {
5968                 DRM_ERROR("aconnector is NULL!\n");
5969                 return stream;
5970         }
5971
5972         drm_connector = &aconnector->base;
5973
5974         if (!aconnector->dc_sink) {
5975                 sink = create_fake_sink(aconnector);
5976                 if (!sink)
5977                         return stream;
5978         } else {
5979                 sink = aconnector->dc_sink;
5980                 dc_sink_retain(sink);
5981         }
5982
5983         stream = dc_create_stream_for_sink(sink);
5984
5985         if (stream == NULL) {
5986                 DRM_ERROR("Failed to create stream for sink!\n");
5987                 goto finish;
5988         }
5989
5990         stream->dm_stream_context = aconnector;
5991
5992         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5993                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5994
5995         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5996                 /* Search for preferred mode */
5997                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5998                         native_mode_found = true;
5999                         break;
6000                 }
6001         }
6002         if (!native_mode_found)
6003                 preferred_mode = list_first_entry_or_null(
6004                                 &aconnector->base.modes,
6005                                 struct drm_display_mode,
6006                                 head);
6007
6008         mode_refresh = drm_mode_vrefresh(&mode);
6009
6010         if (preferred_mode == NULL) {
6011                 /*
6012                  * This may not be an error, the use case is when we have no
6013                  * usermode calls to reset and set mode upon hotplug. In this
6014                  * case, we call set mode ourselves to restore the previous mode
6015                  * and the modelist may not be filled in in time.
6016                  */
6017                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6018         } else {
6019                 recalculate_timing = amdgpu_freesync_vid_mode &&
6020                                  is_freesync_video_mode(&mode, aconnector);
6021                 if (recalculate_timing) {
6022                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6023                         drm_mode_copy(&saved_mode, &mode);
6024                         drm_mode_copy(&mode, freesync_mode);
6025                 } else {
6026                         decide_crtc_timing_for_drm_display_mode(
6027                                         &mode, preferred_mode, scale);
6028
6029                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6030                 }
6031         }
6032
6033         if (recalculate_timing)
6034                 drm_mode_set_crtcinfo(&saved_mode, 0);
6035         else if (!dm_state)
6036                 drm_mode_set_crtcinfo(&mode, 0);
6037
6038         /*
6039         * If scaling is enabled and refresh rate didn't change
6040         * we copy the vic and polarities of the old timings
6041         */
6042         if (!scale || mode_refresh != preferred_refresh)
6043                 fill_stream_properties_from_drm_display_mode(
6044                         stream, &mode, &aconnector->base, con_state, NULL,
6045                         requested_bpc);
6046         else
6047                 fill_stream_properties_from_drm_display_mode(
6048                         stream, &mode, &aconnector->base, con_state, old_stream,
6049                         requested_bpc);
6050
6051         if (aconnector->timing_changed) {
6052                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6053                                 __func__,
6054                                 stream->timing.display_color_depth,
6055                                 aconnector->timing_requested->display_color_depth);
6056                 stream->timing = *aconnector->timing_requested;
6057         }
6058
6059         /* SST DSC determination policy */
6060         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6061         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6062                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6063
6064         update_stream_scaling_settings(&mode, dm_state, stream);
6065
6066         fill_audio_info(
6067                 &stream->audio_info,
6068                 drm_connector,
6069                 sink);
6070
6071         update_stream_signal(stream, sink);
6072
6073         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6074                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6075
6076         if (stream->link->psr_settings.psr_feature_enabled) {
6077                 //
6078                 // should decide stream support vsc sdp colorimetry capability
6079                 // before building vsc info packet
6080                 //
6081                 stream->use_vsc_sdp_for_colorimetry = false;
6082                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6083                         stream->use_vsc_sdp_for_colorimetry =
6084                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6085                 } else {
6086                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6087                                 stream->use_vsc_sdp_for_colorimetry = true;
6088                 }
6089                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6090                         tf = TRANSFER_FUNC_GAMMA_22;
6091                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6092                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6093
6094         }
6095 finish:
6096         dc_sink_release(sink);
6097
6098         return stream;
6099 }
6100
6101 static enum drm_connector_status
6102 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6103 {
6104         bool connected;
6105         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6106
6107         /*
6108          * Notes:
6109          * 1. This interface is NOT called in context of HPD irq.
6110          * 2. This interface *is called* in context of user-mode ioctl. Which
6111          * makes it a bad place for *any* MST-related activity.
6112          */
6113
6114         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6115             !aconnector->fake_enable)
6116                 connected = (aconnector->dc_sink != NULL);
6117         else
6118                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6119                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6120
6121         update_subconnector_property(aconnector);
6122
6123         return (connected ? connector_status_connected :
6124                         connector_status_disconnected);
6125 }
6126
6127 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6128                                             struct drm_connector_state *connector_state,
6129                                             struct drm_property *property,
6130                                             uint64_t val)
6131 {
6132         struct drm_device *dev = connector->dev;
6133         struct amdgpu_device *adev = drm_to_adev(dev);
6134         struct dm_connector_state *dm_old_state =
6135                 to_dm_connector_state(connector->state);
6136         struct dm_connector_state *dm_new_state =
6137                 to_dm_connector_state(connector_state);
6138
6139         int ret = -EINVAL;
6140
6141         if (property == dev->mode_config.scaling_mode_property) {
6142                 enum amdgpu_rmx_type rmx_type;
6143
6144                 switch (val) {
6145                 case DRM_MODE_SCALE_CENTER:
6146                         rmx_type = RMX_CENTER;
6147                         break;
6148                 case DRM_MODE_SCALE_ASPECT:
6149                         rmx_type = RMX_ASPECT;
6150                         break;
6151                 case DRM_MODE_SCALE_FULLSCREEN:
6152                         rmx_type = RMX_FULL;
6153                         break;
6154                 case DRM_MODE_SCALE_NONE:
6155                 default:
6156                         rmx_type = RMX_OFF;
6157                         break;
6158                 }
6159
6160                 if (dm_old_state->scaling == rmx_type)
6161                         return 0;
6162
6163                 dm_new_state->scaling = rmx_type;
6164                 ret = 0;
6165         } else if (property == adev->mode_info.underscan_hborder_property) {
6166                 dm_new_state->underscan_hborder = val;
6167                 ret = 0;
6168         } else if (property == adev->mode_info.underscan_vborder_property) {
6169                 dm_new_state->underscan_vborder = val;
6170                 ret = 0;
6171         } else if (property == adev->mode_info.underscan_property) {
6172                 dm_new_state->underscan_enable = val;
6173                 ret = 0;
6174         } else if (property == adev->mode_info.abm_level_property) {
6175                 dm_new_state->abm_level = val;
6176                 ret = 0;
6177         }
6178
6179         return ret;
6180 }
6181
6182 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6183                                             const struct drm_connector_state *state,
6184                                             struct drm_property *property,
6185                                             uint64_t *val)
6186 {
6187         struct drm_device *dev = connector->dev;
6188         struct amdgpu_device *adev = drm_to_adev(dev);
6189         struct dm_connector_state *dm_state =
6190                 to_dm_connector_state(state);
6191         int ret = -EINVAL;
6192
6193         if (property == dev->mode_config.scaling_mode_property) {
6194                 switch (dm_state->scaling) {
6195                 case RMX_CENTER:
6196                         *val = DRM_MODE_SCALE_CENTER;
6197                         break;
6198                 case RMX_ASPECT:
6199                         *val = DRM_MODE_SCALE_ASPECT;
6200                         break;
6201                 case RMX_FULL:
6202                         *val = DRM_MODE_SCALE_FULLSCREEN;
6203                         break;
6204                 case RMX_OFF:
6205                 default:
6206                         *val = DRM_MODE_SCALE_NONE;
6207                         break;
6208                 }
6209                 ret = 0;
6210         } else if (property == adev->mode_info.underscan_hborder_property) {
6211                 *val = dm_state->underscan_hborder;
6212                 ret = 0;
6213         } else if (property == adev->mode_info.underscan_vborder_property) {
6214                 *val = dm_state->underscan_vborder;
6215                 ret = 0;
6216         } else if (property == adev->mode_info.underscan_property) {
6217                 *val = dm_state->underscan_enable;
6218                 ret = 0;
6219         } else if (property == adev->mode_info.abm_level_property) {
6220                 *val = dm_state->abm_level;
6221                 ret = 0;
6222         }
6223
6224         return ret;
6225 }
6226
6227 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6228 {
6229         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6230
6231         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6232 }
6233
6234 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6235 {
6236         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6237         const struct dc_link *link = aconnector->dc_link;
6238         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6239         struct amdgpu_display_manager *dm = &adev->dm;
6240         int i;
6241
6242         /*
6243          * Call only if mst_mgr was initialized before since it's not done
6244          * for all connector types.
6245          */
6246         if (aconnector->mst_mgr.dev)
6247                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6248
6249         for (i = 0; i < dm->num_of_edps; i++) {
6250                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6251                         backlight_device_unregister(dm->backlight_dev[i]);
6252                         dm->backlight_dev[i] = NULL;
6253                 }
6254         }
6255
6256         if (aconnector->dc_em_sink)
6257                 dc_sink_release(aconnector->dc_em_sink);
6258         aconnector->dc_em_sink = NULL;
6259         if (aconnector->dc_sink)
6260                 dc_sink_release(aconnector->dc_sink);
6261         aconnector->dc_sink = NULL;
6262
6263         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6264         drm_connector_unregister(connector);
6265         drm_connector_cleanup(connector);
6266         if (aconnector->i2c) {
6267                 i2c_del_adapter(&aconnector->i2c->base);
6268                 kfree(aconnector->i2c);
6269         }
6270         kfree(aconnector->dm_dp_aux.aux.name);
6271
6272         kfree(connector);
6273 }
6274
6275 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6276 {
6277         struct dm_connector_state *state =
6278                 to_dm_connector_state(connector->state);
6279
6280         if (connector->state)
6281                 __drm_atomic_helper_connector_destroy_state(connector->state);
6282
6283         kfree(state);
6284
6285         state = kzalloc(sizeof(*state), GFP_KERNEL);
6286
6287         if (state) {
6288                 state->scaling = RMX_OFF;
6289                 state->underscan_enable = false;
6290                 state->underscan_hborder = 0;
6291                 state->underscan_vborder = 0;
6292                 state->base.max_requested_bpc = 8;
6293                 state->vcpi_slots = 0;
6294                 state->pbn = 0;
6295
6296                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6297                         state->abm_level = amdgpu_dm_abm_level;
6298
6299                 __drm_atomic_helper_connector_reset(connector, &state->base);
6300         }
6301 }
6302
6303 struct drm_connector_state *
6304 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6305 {
6306         struct dm_connector_state *state =
6307                 to_dm_connector_state(connector->state);
6308
6309         struct dm_connector_state *new_state =
6310                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6311
6312         if (!new_state)
6313                 return NULL;
6314
6315         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6316
6317         new_state->freesync_capable = state->freesync_capable;
6318         new_state->abm_level = state->abm_level;
6319         new_state->scaling = state->scaling;
6320         new_state->underscan_enable = state->underscan_enable;
6321         new_state->underscan_hborder = state->underscan_hborder;
6322         new_state->underscan_vborder = state->underscan_vborder;
6323         new_state->vcpi_slots = state->vcpi_slots;
6324         new_state->pbn = state->pbn;
6325         return &new_state->base;
6326 }
6327
6328 static int
6329 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6330 {
6331         struct amdgpu_dm_connector *amdgpu_dm_connector =
6332                 to_amdgpu_dm_connector(connector);
6333         int r;
6334
6335         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6336             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6337                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6338                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6339                 if (r)
6340                         return r;
6341         }
6342
6343 #if defined(CONFIG_DEBUG_FS)
6344         connector_debugfs_init(amdgpu_dm_connector);
6345 #endif
6346
6347         return 0;
6348 }
6349
6350 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6351         .reset = amdgpu_dm_connector_funcs_reset,
6352         .detect = amdgpu_dm_connector_detect,
6353         .fill_modes = drm_helper_probe_single_connector_modes,
6354         .destroy = amdgpu_dm_connector_destroy,
6355         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6356         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6357         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6358         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6359         .late_register = amdgpu_dm_connector_late_register,
6360         .early_unregister = amdgpu_dm_connector_unregister
6361 };
6362
6363 static int get_modes(struct drm_connector *connector)
6364 {
6365         return amdgpu_dm_connector_get_modes(connector);
6366 }
6367
6368 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6369 {
6370         struct dc_sink_init_data init_params = {
6371                         .link = aconnector->dc_link,
6372                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6373         };
6374         struct edid *edid;
6375
6376         if (!aconnector->base.edid_blob_ptr) {
6377                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6378                                 aconnector->base.name);
6379
6380                 aconnector->base.force = DRM_FORCE_OFF;
6381                 return;
6382         }
6383
6384         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6385
6386         aconnector->edid = edid;
6387
6388         aconnector->dc_em_sink = dc_link_add_remote_sink(
6389                 aconnector->dc_link,
6390                 (uint8_t *)edid,
6391                 (edid->extensions + 1) * EDID_LENGTH,
6392                 &init_params);
6393
6394         if (aconnector->base.force == DRM_FORCE_ON) {
6395                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6396                 aconnector->dc_link->local_sink :
6397                 aconnector->dc_em_sink;
6398                 dc_sink_retain(aconnector->dc_sink);
6399         }
6400 }
6401
6402 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6403 {
6404         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6405
6406         /*
6407          * In case of headless boot with force on for DP managed connector
6408          * Those settings have to be != 0 to get initial modeset
6409          */
6410         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6411                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6412                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6413         }
6414
6415         create_eml_sink(aconnector);
6416 }
6417
6418 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6419                                                 struct dc_stream_state *stream)
6420 {
6421         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6422         struct dc_plane_state *dc_plane_state = NULL;
6423         struct dc_state *dc_state = NULL;
6424
6425         if (!stream)
6426                 goto cleanup;
6427
6428         dc_plane_state = dc_create_plane_state(dc);
6429         if (!dc_plane_state)
6430                 goto cleanup;
6431
6432         dc_state = dc_create_state(dc);
6433         if (!dc_state)
6434                 goto cleanup;
6435
6436         /* populate stream to plane */
6437         dc_plane_state->src_rect.height  = stream->src.height;
6438         dc_plane_state->src_rect.width   = stream->src.width;
6439         dc_plane_state->dst_rect.height  = stream->src.height;
6440         dc_plane_state->dst_rect.width   = stream->src.width;
6441         dc_plane_state->clip_rect.height = stream->src.height;
6442         dc_plane_state->clip_rect.width  = stream->src.width;
6443         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6444         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6445         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6446         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6447         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6448         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6449         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6450         dc_plane_state->rotation = ROTATION_ANGLE_0;
6451         dc_plane_state->is_tiling_rotated = false;
6452         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6453
6454         dc_result = dc_validate_stream(dc, stream);
6455         if (dc_result == DC_OK)
6456                 dc_result = dc_validate_plane(dc, dc_plane_state);
6457
6458         if (dc_result == DC_OK)
6459                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6460
6461         if (dc_result == DC_OK && !dc_add_plane_to_context(
6462                                                 dc,
6463                                                 stream,
6464                                                 dc_plane_state,
6465                                                 dc_state))
6466                 dc_result = DC_FAIL_ATTACH_SURFACES;
6467
6468         if (dc_result == DC_OK)
6469                 dc_result = dc_validate_global_state(dc, dc_state, true);
6470
6471 cleanup:
6472         if (dc_state)
6473                 dc_release_state(dc_state);
6474
6475         if (dc_plane_state)
6476                 dc_plane_state_release(dc_plane_state);
6477
6478         return dc_result;
6479 }
6480
6481 struct dc_stream_state *
6482 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6483                                 const struct drm_display_mode *drm_mode,
6484                                 const struct dm_connector_state *dm_state,
6485                                 const struct dc_stream_state *old_stream)
6486 {
6487         struct drm_connector *connector = &aconnector->base;
6488         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6489         struct dc_stream_state *stream;
6490         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6491         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6492         enum dc_status dc_result = DC_OK;
6493
6494         do {
6495                 stream = create_stream_for_sink(aconnector, drm_mode,
6496                                                 dm_state, old_stream,
6497                                                 requested_bpc);
6498                 if (stream == NULL) {
6499                         DRM_ERROR("Failed to create stream for sink!\n");
6500                         break;
6501                 }
6502
6503                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6504                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6505                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6506
6507                 if (dc_result == DC_OK)
6508                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6509
6510                 if (dc_result != DC_OK) {
6511                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6512                                       drm_mode->hdisplay,
6513                                       drm_mode->vdisplay,
6514                                       drm_mode->clock,
6515                                       dc_result,
6516                                       dc_status_to_str(dc_result));
6517
6518                         dc_stream_release(stream);
6519                         stream = NULL;
6520                         requested_bpc -= 2; /* lower bpc to retry validation */
6521                 }
6522
6523         } while (stream == NULL && requested_bpc >= 6);
6524
6525         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6526                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6527
6528                 aconnector->force_yuv420_output = true;
6529                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6530                                                 dm_state, old_stream);
6531                 aconnector->force_yuv420_output = false;
6532         }
6533
6534         return stream;
6535 }
6536
6537 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6538                                    struct drm_display_mode *mode)
6539 {
6540         int result = MODE_ERROR;
6541         struct dc_sink *dc_sink;
6542         /* TODO: Unhardcode stream count */
6543         struct dc_stream_state *stream;
6544         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6545
6546         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6547                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6548                 return result;
6549
6550         /*
6551          * Only run this the first time mode_valid is called to initilialize
6552          * EDID mgmt
6553          */
6554         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6555                 !aconnector->dc_em_sink)
6556                 handle_edid_mgmt(aconnector);
6557
6558         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6559
6560         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6561                                 aconnector->base.force != DRM_FORCE_ON) {
6562                 DRM_ERROR("dc_sink is NULL!\n");
6563                 goto fail;
6564         }
6565
6566         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6567         if (stream) {
6568                 dc_stream_release(stream);
6569                 result = MODE_OK;
6570         }
6571
6572 fail:
6573         /* TODO: error handling*/
6574         return result;
6575 }
6576
6577 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6578                                 struct dc_info_packet *out)
6579 {
6580         struct hdmi_drm_infoframe frame;
6581         unsigned char buf[30]; /* 26 + 4 */
6582         ssize_t len;
6583         int ret, i;
6584
6585         memset(out, 0, sizeof(*out));
6586
6587         if (!state->hdr_output_metadata)
6588                 return 0;
6589
6590         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6591         if (ret)
6592                 return ret;
6593
6594         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6595         if (len < 0)
6596                 return (int)len;
6597
6598         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6599         if (len != 30)
6600                 return -EINVAL;
6601
6602         /* Prepare the infopacket for DC. */
6603         switch (state->connector->connector_type) {
6604         case DRM_MODE_CONNECTOR_HDMIA:
6605                 out->hb0 = 0x87; /* type */
6606                 out->hb1 = 0x01; /* version */
6607                 out->hb2 = 0x1A; /* length */
6608                 out->sb[0] = buf[3]; /* checksum */
6609                 i = 1;
6610                 break;
6611
6612         case DRM_MODE_CONNECTOR_DisplayPort:
6613         case DRM_MODE_CONNECTOR_eDP:
6614                 out->hb0 = 0x00; /* sdp id, zero */
6615                 out->hb1 = 0x87; /* type */
6616                 out->hb2 = 0x1D; /* payload len - 1 */
6617                 out->hb3 = (0x13 << 2); /* sdp version */
6618                 out->sb[0] = 0x01; /* version */
6619                 out->sb[1] = 0x1A; /* length */
6620                 i = 2;
6621                 break;
6622
6623         default:
6624                 return -EINVAL;
6625         }
6626
6627         memcpy(&out->sb[i], &buf[4], 26);
6628         out->valid = true;
6629
6630         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6631                        sizeof(out->sb), false);
6632
6633         return 0;
6634 }
6635
6636 static int
6637 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6638                                  struct drm_atomic_state *state)
6639 {
6640         struct drm_connector_state *new_con_state =
6641                 drm_atomic_get_new_connector_state(state, conn);
6642         struct drm_connector_state *old_con_state =
6643                 drm_atomic_get_old_connector_state(state, conn);
6644         struct drm_crtc *crtc = new_con_state->crtc;
6645         struct drm_crtc_state *new_crtc_state;
6646         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6647         int ret;
6648
6649         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6650
6651         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6652                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6653                 if (ret < 0)
6654                         return ret;
6655         }
6656
6657         if (!crtc)
6658                 return 0;
6659
6660         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6661                 struct dc_info_packet hdr_infopacket;
6662
6663                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6664                 if (ret)
6665                         return ret;
6666
6667                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6668                 if (IS_ERR(new_crtc_state))
6669                         return PTR_ERR(new_crtc_state);
6670
6671                 /*
6672                  * DC considers the stream backends changed if the
6673                  * static metadata changes. Forcing the modeset also
6674                  * gives a simple way for userspace to switch from
6675                  * 8bpc to 10bpc when setting the metadata to enter
6676                  * or exit HDR.
6677                  *
6678                  * Changing the static metadata after it's been
6679                  * set is permissible, however. So only force a
6680                  * modeset if we're entering or exiting HDR.
6681                  */
6682                 new_crtc_state->mode_changed =
6683                         !old_con_state->hdr_output_metadata ||
6684                         !new_con_state->hdr_output_metadata;
6685         }
6686
6687         return 0;
6688 }
6689
6690 static const struct drm_connector_helper_funcs
6691 amdgpu_dm_connector_helper_funcs = {
6692         /*
6693          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6694          * modes will be filtered by drm_mode_validate_size(), and those modes
6695          * are missing after user start lightdm. So we need to renew modes list.
6696          * in get_modes call back, not just return the modes count
6697          */
6698         .get_modes = get_modes,
6699         .mode_valid = amdgpu_dm_connector_mode_valid,
6700         .atomic_check = amdgpu_dm_connector_atomic_check,
6701 };
6702
6703 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6704 {
6705
6706 }
6707
6708 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6709 {
6710         switch (display_color_depth) {
6711         case COLOR_DEPTH_666:
6712                 return 6;
6713         case COLOR_DEPTH_888:
6714                 return 8;
6715         case COLOR_DEPTH_101010:
6716                 return 10;
6717         case COLOR_DEPTH_121212:
6718                 return 12;
6719         case COLOR_DEPTH_141414:
6720                 return 14;
6721         case COLOR_DEPTH_161616:
6722                 return 16;
6723         default:
6724                 break;
6725         }
6726         return 0;
6727 }
6728
6729 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6730                                           struct drm_crtc_state *crtc_state,
6731                                           struct drm_connector_state *conn_state)
6732 {
6733         struct drm_atomic_state *state = crtc_state->state;
6734         struct drm_connector *connector = conn_state->connector;
6735         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6736         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6737         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6738         struct drm_dp_mst_topology_mgr *mst_mgr;
6739         struct drm_dp_mst_port *mst_port;
6740         struct drm_dp_mst_topology_state *mst_state;
6741         enum dc_color_depth color_depth;
6742         int clock, bpp = 0;
6743         bool is_y420 = false;
6744
6745         if (!aconnector->mst_output_port || !aconnector->dc_sink)
6746                 return 0;
6747
6748         mst_port = aconnector->mst_output_port;
6749         mst_mgr = &aconnector->mst_root->mst_mgr;
6750
6751         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6752                 return 0;
6753
6754         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6755         if (IS_ERR(mst_state))
6756                 return PTR_ERR(mst_state);
6757
6758         if (!mst_state->pbn_div)
6759                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6760
6761         if (!state->duplicated) {
6762                 int max_bpc = conn_state->max_requested_bpc;
6763                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6764                           aconnector->force_yuv420_output;
6765                 color_depth = convert_color_depth_from_display_info(connector,
6766                                                                     is_y420,
6767                                                                     max_bpc);
6768                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6769                 clock = adjusted_mode->clock;
6770                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6771         }
6772
6773         dm_new_connector_state->vcpi_slots =
6774                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6775                                               dm_new_connector_state->pbn);
6776         if (dm_new_connector_state->vcpi_slots < 0) {
6777                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6778                 return dm_new_connector_state->vcpi_slots;
6779         }
6780         return 0;
6781 }
6782
6783 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6784         .disable = dm_encoder_helper_disable,
6785         .atomic_check = dm_encoder_helper_atomic_check
6786 };
6787
6788 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6789                                             struct dc_state *dc_state,
6790                                             struct dsc_mst_fairness_vars *vars)
6791 {
6792         struct dc_stream_state *stream = NULL;
6793         struct drm_connector *connector;
6794         struct drm_connector_state *new_con_state;
6795         struct amdgpu_dm_connector *aconnector;
6796         struct dm_connector_state *dm_conn_state;
6797         int i, j, ret;
6798         int vcpi, pbn_div, pbn, slot_num = 0;
6799
6800         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6801
6802                 aconnector = to_amdgpu_dm_connector(connector);
6803
6804                 if (!aconnector->mst_output_port)
6805                         continue;
6806
6807                 if (!new_con_state || !new_con_state->crtc)
6808                         continue;
6809
6810                 dm_conn_state = to_dm_connector_state(new_con_state);
6811
6812                 for (j = 0; j < dc_state->stream_count; j++) {
6813                         stream = dc_state->streams[j];
6814                         if (!stream)
6815                                 continue;
6816
6817                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6818                                 break;
6819
6820                         stream = NULL;
6821                 }
6822
6823                 if (!stream)
6824                         continue;
6825
6826                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6827                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6828                 for (j = 0; j < dc_state->stream_count; j++) {
6829                         if (vars[j].aconnector == aconnector) {
6830                                 pbn = vars[j].pbn;
6831                                 break;
6832                         }
6833                 }
6834
6835                 if (j == dc_state->stream_count)
6836                         continue;
6837
6838                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6839
6840                 if (stream->timing.flags.DSC != 1) {
6841                         dm_conn_state->pbn = pbn;
6842                         dm_conn_state->vcpi_slots = slot_num;
6843
6844                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6845                                                            dm_conn_state->pbn, false);
6846                         if (ret < 0)
6847                                 return ret;
6848
6849                         continue;
6850                 }
6851
6852                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6853                 if (vcpi < 0)
6854                         return vcpi;
6855
6856                 dm_conn_state->pbn = pbn;
6857                 dm_conn_state->vcpi_slots = vcpi;
6858         }
6859         return 0;
6860 }
6861
6862 static int to_drm_connector_type(enum signal_type st)
6863 {
6864         switch (st) {
6865         case SIGNAL_TYPE_HDMI_TYPE_A:
6866                 return DRM_MODE_CONNECTOR_HDMIA;
6867         case SIGNAL_TYPE_EDP:
6868                 return DRM_MODE_CONNECTOR_eDP;
6869         case SIGNAL_TYPE_LVDS:
6870                 return DRM_MODE_CONNECTOR_LVDS;
6871         case SIGNAL_TYPE_RGB:
6872                 return DRM_MODE_CONNECTOR_VGA;
6873         case SIGNAL_TYPE_DISPLAY_PORT:
6874         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6875                 return DRM_MODE_CONNECTOR_DisplayPort;
6876         case SIGNAL_TYPE_DVI_DUAL_LINK:
6877         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6878                 return DRM_MODE_CONNECTOR_DVID;
6879         case SIGNAL_TYPE_VIRTUAL:
6880                 return DRM_MODE_CONNECTOR_VIRTUAL;
6881
6882         default:
6883                 return DRM_MODE_CONNECTOR_Unknown;
6884         }
6885 }
6886
6887 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6888 {
6889         struct drm_encoder *encoder;
6890
6891         /* There is only one encoder per connector */
6892         drm_connector_for_each_possible_encoder(connector, encoder)
6893                 return encoder;
6894
6895         return NULL;
6896 }
6897
6898 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6899 {
6900         struct drm_encoder *encoder;
6901         struct amdgpu_encoder *amdgpu_encoder;
6902
6903         encoder = amdgpu_dm_connector_to_encoder(connector);
6904
6905         if (encoder == NULL)
6906                 return;
6907
6908         amdgpu_encoder = to_amdgpu_encoder(encoder);
6909
6910         amdgpu_encoder->native_mode.clock = 0;
6911
6912         if (!list_empty(&connector->probed_modes)) {
6913                 struct drm_display_mode *preferred_mode = NULL;
6914
6915                 list_for_each_entry(preferred_mode,
6916                                     &connector->probed_modes,
6917                                     head) {
6918                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6919                                 amdgpu_encoder->native_mode = *preferred_mode;
6920
6921                         break;
6922                 }
6923
6924         }
6925 }
6926
6927 static struct drm_display_mode *
6928 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6929                              char *name,
6930                              int hdisplay, int vdisplay)
6931 {
6932         struct drm_device *dev = encoder->dev;
6933         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6934         struct drm_display_mode *mode = NULL;
6935         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6936
6937         mode = drm_mode_duplicate(dev, native_mode);
6938
6939         if (mode == NULL)
6940                 return NULL;
6941
6942         mode->hdisplay = hdisplay;
6943         mode->vdisplay = vdisplay;
6944         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6945         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6946
6947         return mode;
6948
6949 }
6950
6951 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6952                                                  struct drm_connector *connector)
6953 {
6954         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6955         struct drm_display_mode *mode = NULL;
6956         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6957         struct amdgpu_dm_connector *amdgpu_dm_connector =
6958                                 to_amdgpu_dm_connector(connector);
6959         int i;
6960         int n;
6961         struct mode_size {
6962                 char name[DRM_DISPLAY_MODE_LEN];
6963                 int w;
6964                 int h;
6965         } common_modes[] = {
6966                 {  "640x480",  640,  480},
6967                 {  "800x600",  800,  600},
6968                 { "1024x768", 1024,  768},
6969                 { "1280x720", 1280,  720},
6970                 { "1280x800", 1280,  800},
6971                 {"1280x1024", 1280, 1024},
6972                 { "1440x900", 1440,  900},
6973                 {"1680x1050", 1680, 1050},
6974                 {"1600x1200", 1600, 1200},
6975                 {"1920x1080", 1920, 1080},
6976                 {"1920x1200", 1920, 1200}
6977         };
6978
6979         n = ARRAY_SIZE(common_modes);
6980
6981         for (i = 0; i < n; i++) {
6982                 struct drm_display_mode *curmode = NULL;
6983                 bool mode_existed = false;
6984
6985                 if (common_modes[i].w > native_mode->hdisplay ||
6986                     common_modes[i].h > native_mode->vdisplay ||
6987                    (common_modes[i].w == native_mode->hdisplay &&
6988                     common_modes[i].h == native_mode->vdisplay))
6989                         continue;
6990
6991                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6992                         if (common_modes[i].w == curmode->hdisplay &&
6993                             common_modes[i].h == curmode->vdisplay) {
6994                                 mode_existed = true;
6995                                 break;
6996                         }
6997                 }
6998
6999                 if (mode_existed)
7000                         continue;
7001
7002                 mode = amdgpu_dm_create_common_mode(encoder,
7003                                 common_modes[i].name, common_modes[i].w,
7004                                 common_modes[i].h);
7005                 if (!mode)
7006                         continue;
7007
7008                 drm_mode_probed_add(connector, mode);
7009                 amdgpu_dm_connector->num_modes++;
7010         }
7011 }
7012
7013 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7014 {
7015         struct drm_encoder *encoder;
7016         struct amdgpu_encoder *amdgpu_encoder;
7017         const struct drm_display_mode *native_mode;
7018
7019         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7020             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7021                 return;
7022
7023         mutex_lock(&connector->dev->mode_config.mutex);
7024         amdgpu_dm_connector_get_modes(connector);
7025         mutex_unlock(&connector->dev->mode_config.mutex);
7026
7027         encoder = amdgpu_dm_connector_to_encoder(connector);
7028         if (!encoder)
7029                 return;
7030
7031         amdgpu_encoder = to_amdgpu_encoder(encoder);
7032
7033         native_mode = &amdgpu_encoder->native_mode;
7034         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7035                 return;
7036
7037         drm_connector_set_panel_orientation_with_quirk(connector,
7038                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7039                                                        native_mode->hdisplay,
7040                                                        native_mode->vdisplay);
7041 }
7042
7043 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7044                                               struct edid *edid)
7045 {
7046         struct amdgpu_dm_connector *amdgpu_dm_connector =
7047                         to_amdgpu_dm_connector(connector);
7048
7049         if (edid) {
7050                 /* empty probed_modes */
7051                 INIT_LIST_HEAD(&connector->probed_modes);
7052                 amdgpu_dm_connector->num_modes =
7053                                 drm_add_edid_modes(connector, edid);
7054
7055                 /* sorting the probed modes before calling function
7056                  * amdgpu_dm_get_native_mode() since EDID can have
7057                  * more than one preferred mode. The modes that are
7058                  * later in the probed mode list could be of higher
7059                  * and preferred resolution. For example, 3840x2160
7060                  * resolution in base EDID preferred timing and 4096x2160
7061                  * preferred resolution in DID extension block later.
7062                  */
7063                 drm_mode_sort(&connector->probed_modes);
7064                 amdgpu_dm_get_native_mode(connector);
7065
7066                 /* Freesync capabilities are reset by calling
7067                  * drm_add_edid_modes() and need to be
7068                  * restored here.
7069                  */
7070                 amdgpu_dm_update_freesync_caps(connector, edid);
7071         } else {
7072                 amdgpu_dm_connector->num_modes = 0;
7073         }
7074 }
7075
7076 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7077                               struct drm_display_mode *mode)
7078 {
7079         struct drm_display_mode *m;
7080
7081         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7082                 if (drm_mode_equal(m, mode))
7083                         return true;
7084         }
7085
7086         return false;
7087 }
7088
7089 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7090 {
7091         const struct drm_display_mode *m;
7092         struct drm_display_mode *new_mode;
7093         uint i;
7094         u32 new_modes_count = 0;
7095
7096         /* Standard FPS values
7097          *
7098          * 23.976       - TV/NTSC
7099          * 24           - Cinema
7100          * 25           - TV/PAL
7101          * 29.97        - TV/NTSC
7102          * 30           - TV/NTSC
7103          * 48           - Cinema HFR
7104          * 50           - TV/PAL
7105          * 60           - Commonly used
7106          * 48,72,96,120 - Multiples of 24
7107          */
7108         static const u32 common_rates[] = {
7109                 23976, 24000, 25000, 29970, 30000,
7110                 48000, 50000, 60000, 72000, 96000, 120000
7111         };
7112
7113         /*
7114          * Find mode with highest refresh rate with the same resolution
7115          * as the preferred mode. Some monitors report a preferred mode
7116          * with lower resolution than the highest refresh rate supported.
7117          */
7118
7119         m = get_highest_refresh_rate_mode(aconnector, true);
7120         if (!m)
7121                 return 0;
7122
7123         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7124                 u64 target_vtotal, target_vtotal_diff;
7125                 u64 num, den;
7126
7127                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7128                         continue;
7129
7130                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7131                     common_rates[i] > aconnector->max_vfreq * 1000)
7132                         continue;
7133
7134                 num = (unsigned long long)m->clock * 1000 * 1000;
7135                 den = common_rates[i] * (unsigned long long)m->htotal;
7136                 target_vtotal = div_u64(num, den);
7137                 target_vtotal_diff = target_vtotal - m->vtotal;
7138
7139                 /* Check for illegal modes */
7140                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7141                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7142                     m->vtotal + target_vtotal_diff < m->vsync_end)
7143                         continue;
7144
7145                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7146                 if (!new_mode)
7147                         goto out;
7148
7149                 new_mode->vtotal += (u16)target_vtotal_diff;
7150                 new_mode->vsync_start += (u16)target_vtotal_diff;
7151                 new_mode->vsync_end += (u16)target_vtotal_diff;
7152                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7153                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7154
7155                 if (!is_duplicate_mode(aconnector, new_mode)) {
7156                         drm_mode_probed_add(&aconnector->base, new_mode);
7157                         new_modes_count += 1;
7158                 } else
7159                         drm_mode_destroy(aconnector->base.dev, new_mode);
7160         }
7161  out:
7162         return new_modes_count;
7163 }
7164
7165 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7166                                                    struct edid *edid)
7167 {
7168         struct amdgpu_dm_connector *amdgpu_dm_connector =
7169                 to_amdgpu_dm_connector(connector);
7170
7171         if (!(amdgpu_freesync_vid_mode && edid))
7172                 return;
7173
7174         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7175                 amdgpu_dm_connector->num_modes +=
7176                         add_fs_modes(amdgpu_dm_connector);
7177 }
7178
7179 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7180 {
7181         struct amdgpu_dm_connector *amdgpu_dm_connector =
7182                         to_amdgpu_dm_connector(connector);
7183         struct drm_encoder *encoder;
7184         struct edid *edid = amdgpu_dm_connector->edid;
7185         struct dc_link_settings *verified_link_cap =
7186                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7187         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7188
7189         encoder = amdgpu_dm_connector_to_encoder(connector);
7190
7191         if (!drm_edid_is_valid(edid)) {
7192                 amdgpu_dm_connector->num_modes =
7193                                 drm_add_modes_noedid(connector, 640, 480);
7194                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7195                         amdgpu_dm_connector->num_modes +=
7196                                 drm_add_modes_noedid(connector, 1920, 1080);
7197         } else {
7198                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7199                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7200                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7201         }
7202         amdgpu_dm_fbc_init(connector);
7203
7204         return amdgpu_dm_connector->num_modes;
7205 }
7206
7207 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7208                                      struct amdgpu_dm_connector *aconnector,
7209                                      int connector_type,
7210                                      struct dc_link *link,
7211                                      int link_index)
7212 {
7213         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7214
7215         /*
7216          * Some of the properties below require access to state, like bpc.
7217          * Allocate some default initial connector state with our reset helper.
7218          */
7219         if (aconnector->base.funcs->reset)
7220                 aconnector->base.funcs->reset(&aconnector->base);
7221
7222         aconnector->connector_id = link_index;
7223         aconnector->dc_link = link;
7224         aconnector->base.interlace_allowed = false;
7225         aconnector->base.doublescan_allowed = false;
7226         aconnector->base.stereo_allowed = false;
7227         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7228         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7229         aconnector->audio_inst = -1;
7230         aconnector->pack_sdp_v1_3 = false;
7231         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7232         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7233         mutex_init(&aconnector->hpd_lock);
7234
7235         /*
7236          * configure support HPD hot plug connector_>polled default value is 0
7237          * which means HPD hot plug not supported
7238          */
7239         switch (connector_type) {
7240         case DRM_MODE_CONNECTOR_HDMIA:
7241                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7242                 aconnector->base.ycbcr_420_allowed =
7243                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7244                 break;
7245         case DRM_MODE_CONNECTOR_DisplayPort:
7246                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7247                 link->link_enc = link_enc_cfg_get_link_enc(link);
7248                 ASSERT(link->link_enc);
7249                 if (link->link_enc)
7250                         aconnector->base.ycbcr_420_allowed =
7251                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7252                 break;
7253         case DRM_MODE_CONNECTOR_DVID:
7254                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7255                 break;
7256         default:
7257                 break;
7258         }
7259
7260         drm_object_attach_property(&aconnector->base.base,
7261                                 dm->ddev->mode_config.scaling_mode_property,
7262                                 DRM_MODE_SCALE_NONE);
7263
7264         drm_object_attach_property(&aconnector->base.base,
7265                                 adev->mode_info.underscan_property,
7266                                 UNDERSCAN_OFF);
7267         drm_object_attach_property(&aconnector->base.base,
7268                                 adev->mode_info.underscan_hborder_property,
7269                                 0);
7270         drm_object_attach_property(&aconnector->base.base,
7271                                 adev->mode_info.underscan_vborder_property,
7272                                 0);
7273
7274         if (!aconnector->mst_root)
7275                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7276
7277         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7278         aconnector->base.state->max_bpc = 16;
7279         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7280
7281         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7282             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7283                 drm_object_attach_property(&aconnector->base.base,
7284                                 adev->mode_info.abm_level_property, 0);
7285         }
7286
7287         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7288             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7289             connector_type == DRM_MODE_CONNECTOR_eDP) {
7290                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7291
7292                 if (!aconnector->mst_root)
7293                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7294
7295                 if (adev->dm.hdcp_workqueue)
7296                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7297         }
7298 }
7299
7300 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7301                               struct i2c_msg *msgs, int num)
7302 {
7303         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7304         struct ddc_service *ddc_service = i2c->ddc_service;
7305         struct i2c_command cmd;
7306         int i;
7307         int result = -EIO;
7308
7309         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7310
7311         if (!cmd.payloads)
7312                 return result;
7313
7314         cmd.number_of_payloads = num;
7315         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7316         cmd.speed = 100;
7317
7318         for (i = 0; i < num; i++) {
7319                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7320                 cmd.payloads[i].address = msgs[i].addr;
7321                 cmd.payloads[i].length = msgs[i].len;
7322                 cmd.payloads[i].data = msgs[i].buf;
7323         }
7324
7325         if (dc_submit_i2c(
7326                         ddc_service->ctx->dc,
7327                         ddc_service->link->link_index,
7328                         &cmd))
7329                 result = num;
7330
7331         kfree(cmd.payloads);
7332         return result;
7333 }
7334
7335 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7336 {
7337         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7338 }
7339
7340 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7341         .master_xfer = amdgpu_dm_i2c_xfer,
7342         .functionality = amdgpu_dm_i2c_func,
7343 };
7344
7345 static struct amdgpu_i2c_adapter *
7346 create_i2c(struct ddc_service *ddc_service,
7347            int link_index,
7348            int *res)
7349 {
7350         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7351         struct amdgpu_i2c_adapter *i2c;
7352
7353         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7354         if (!i2c)
7355                 return NULL;
7356         i2c->base.owner = THIS_MODULE;
7357         i2c->base.class = I2C_CLASS_DDC;
7358         i2c->base.dev.parent = &adev->pdev->dev;
7359         i2c->base.algo = &amdgpu_dm_i2c_algo;
7360         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7361         i2c_set_adapdata(&i2c->base, i2c);
7362         i2c->ddc_service = ddc_service;
7363
7364         return i2c;
7365 }
7366
7367
7368 /*
7369  * Note: this function assumes that dc_link_detect() was called for the
7370  * dc_link which will be represented by this aconnector.
7371  */
7372 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7373                                     struct amdgpu_dm_connector *aconnector,
7374                                     u32 link_index,
7375                                     struct amdgpu_encoder *aencoder)
7376 {
7377         int res = 0;
7378         int connector_type;
7379         struct dc *dc = dm->dc;
7380         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7381         struct amdgpu_i2c_adapter *i2c;
7382
7383         link->priv = aconnector;
7384
7385         DRM_DEBUG_DRIVER("%s()\n", __func__);
7386
7387         i2c = create_i2c(link->ddc, link->link_index, &res);
7388         if (!i2c) {
7389                 DRM_ERROR("Failed to create i2c adapter data\n");
7390                 return -ENOMEM;
7391         }
7392
7393         aconnector->i2c = i2c;
7394         res = i2c_add_adapter(&i2c->base);
7395
7396         if (res) {
7397                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7398                 goto out_free;
7399         }
7400
7401         connector_type = to_drm_connector_type(link->connector_signal);
7402
7403         res = drm_connector_init_with_ddc(
7404                         dm->ddev,
7405                         &aconnector->base,
7406                         &amdgpu_dm_connector_funcs,
7407                         connector_type,
7408                         &i2c->base);
7409
7410         if (res) {
7411                 DRM_ERROR("connector_init failed\n");
7412                 aconnector->connector_id = -1;
7413                 goto out_free;
7414         }
7415
7416         drm_connector_helper_add(
7417                         &aconnector->base,
7418                         &amdgpu_dm_connector_helper_funcs);
7419
7420         amdgpu_dm_connector_init_helper(
7421                 dm,
7422                 aconnector,
7423                 connector_type,
7424                 link,
7425                 link_index);
7426
7427         drm_connector_attach_encoder(
7428                 &aconnector->base, &aencoder->base);
7429
7430         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7431                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7432                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7433
7434 out_free:
7435         if (res) {
7436                 kfree(i2c);
7437                 aconnector->i2c = NULL;
7438         }
7439         return res;
7440 }
7441
7442 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7443 {
7444         switch (adev->mode_info.num_crtc) {
7445         case 1:
7446                 return 0x1;
7447         case 2:
7448                 return 0x3;
7449         case 3:
7450                 return 0x7;
7451         case 4:
7452                 return 0xf;
7453         case 5:
7454                 return 0x1f;
7455         case 6:
7456         default:
7457                 return 0x3f;
7458         }
7459 }
7460
7461 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7462                                   struct amdgpu_encoder *aencoder,
7463                                   uint32_t link_index)
7464 {
7465         struct amdgpu_device *adev = drm_to_adev(dev);
7466
7467         int res = drm_encoder_init(dev,
7468                                    &aencoder->base,
7469                                    &amdgpu_dm_encoder_funcs,
7470                                    DRM_MODE_ENCODER_TMDS,
7471                                    NULL);
7472
7473         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7474
7475         if (!res)
7476                 aencoder->encoder_id = link_index;
7477         else
7478                 aencoder->encoder_id = -1;
7479
7480         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7481
7482         return res;
7483 }
7484
7485 static void manage_dm_interrupts(struct amdgpu_device *adev,
7486                                  struct amdgpu_crtc *acrtc,
7487                                  bool enable)
7488 {
7489         /*
7490          * We have no guarantee that the frontend index maps to the same
7491          * backend index - some even map to more than one.
7492          *
7493          * TODO: Use a different interrupt or check DC itself for the mapping.
7494          */
7495         int irq_type =
7496                 amdgpu_display_crtc_idx_to_irq_type(
7497                         adev,
7498                         acrtc->crtc_id);
7499
7500         if (enable) {
7501                 drm_crtc_vblank_on(&acrtc->base);
7502                 amdgpu_irq_get(
7503                         adev,
7504                         &adev->pageflip_irq,
7505                         irq_type);
7506 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7507                 amdgpu_irq_get(
7508                         adev,
7509                         &adev->vline0_irq,
7510                         irq_type);
7511 #endif
7512         } else {
7513 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7514                 amdgpu_irq_put(
7515                         adev,
7516                         &adev->vline0_irq,
7517                         irq_type);
7518 #endif
7519                 amdgpu_irq_put(
7520                         adev,
7521                         &adev->pageflip_irq,
7522                         irq_type);
7523                 drm_crtc_vblank_off(&acrtc->base);
7524         }
7525 }
7526
7527 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7528                                       struct amdgpu_crtc *acrtc)
7529 {
7530         int irq_type =
7531                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7532
7533         /**
7534          * This reads the current state for the IRQ and force reapplies
7535          * the setting to hardware.
7536          */
7537         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7538 }
7539
7540 static bool
7541 is_scaling_state_different(const struct dm_connector_state *dm_state,
7542                            const struct dm_connector_state *old_dm_state)
7543 {
7544         if (dm_state->scaling != old_dm_state->scaling)
7545                 return true;
7546         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7547                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7548                         return true;
7549         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7550                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7551                         return true;
7552         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7553                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7554                 return true;
7555         return false;
7556 }
7557
7558 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7559                                             struct drm_crtc_state *old_crtc_state,
7560                                             struct drm_connector_state *new_conn_state,
7561                                             struct drm_connector_state *old_conn_state,
7562                                             const struct drm_connector *connector,
7563                                             struct hdcp_workqueue *hdcp_w)
7564 {
7565         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7566         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7567
7568         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7569                 connector->index, connector->status, connector->dpms);
7570         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7571                 old_conn_state->content_protection, new_conn_state->content_protection);
7572
7573         if (old_crtc_state)
7574                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7575                 old_crtc_state->enable,
7576                 old_crtc_state->active,
7577                 old_crtc_state->mode_changed,
7578                 old_crtc_state->active_changed,
7579                 old_crtc_state->connectors_changed);
7580
7581         if (new_crtc_state)
7582                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7583                 new_crtc_state->enable,
7584                 new_crtc_state->active,
7585                 new_crtc_state->mode_changed,
7586                 new_crtc_state->active_changed,
7587                 new_crtc_state->connectors_changed);
7588
7589         /* hdcp content type change */
7590         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7591             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7592                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7593                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7594                 return true;
7595         }
7596
7597         /* CP is being re enabled, ignore this */
7598         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7599             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7600                 if (new_crtc_state && new_crtc_state->mode_changed) {
7601                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7602                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7603                         return true;
7604                 }
7605                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7606                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7607                 return false;
7608         }
7609
7610         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7611          *
7612          * Handles:     UNDESIRED -> ENABLED
7613          */
7614         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7615             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7616                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7617
7618         /* Stream removed and re-enabled
7619          *
7620          * Can sometimes overlap with the HPD case,
7621          * thus set update_hdcp to false to avoid
7622          * setting HDCP multiple times.
7623          *
7624          * Handles:     DESIRED -> DESIRED (Special case)
7625          */
7626         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7627                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7628                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7629                 dm_con_state->update_hdcp = false;
7630                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7631                         __func__);
7632                 return true;
7633         }
7634
7635         /* Hot-plug, headless s3, dpms
7636          *
7637          * Only start HDCP if the display is connected/enabled.
7638          * update_hdcp flag will be set to false until the next
7639          * HPD comes in.
7640          *
7641          * Handles:     DESIRED -> DESIRED (Special case)
7642          */
7643         if (dm_con_state->update_hdcp &&
7644         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7645         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7646                 dm_con_state->update_hdcp = false;
7647                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7648                         __func__);
7649                 return true;
7650         }
7651
7652         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7653                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7654                         if (new_crtc_state && new_crtc_state->mode_changed) {
7655                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7656                                         __func__);
7657                                 return true;
7658                         }
7659                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7660                                 __func__);
7661                         return false;
7662                 }
7663
7664                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7665                 return false;
7666         }
7667
7668         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7669                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7670                         __func__);
7671                 return true;
7672         }
7673
7674         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7675         return false;
7676 }
7677
7678 static void remove_stream(struct amdgpu_device *adev,
7679                           struct amdgpu_crtc *acrtc,
7680                           struct dc_stream_state *stream)
7681 {
7682         /* this is the update mode case */
7683
7684         acrtc->otg_inst = -1;
7685         acrtc->enabled = false;
7686 }
7687
7688 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7689 {
7690
7691         assert_spin_locked(&acrtc->base.dev->event_lock);
7692         WARN_ON(acrtc->event);
7693
7694         acrtc->event = acrtc->base.state->event;
7695
7696         /* Set the flip status */
7697         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7698
7699         /* Mark this event as consumed */
7700         acrtc->base.state->event = NULL;
7701
7702         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7703                      acrtc->crtc_id);
7704 }
7705
7706 static void update_freesync_state_on_stream(
7707         struct amdgpu_display_manager *dm,
7708         struct dm_crtc_state *new_crtc_state,
7709         struct dc_stream_state *new_stream,
7710         struct dc_plane_state *surface,
7711         u32 flip_timestamp_in_us)
7712 {
7713         struct mod_vrr_params vrr_params;
7714         struct dc_info_packet vrr_infopacket = {0};
7715         struct amdgpu_device *adev = dm->adev;
7716         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7717         unsigned long flags;
7718         bool pack_sdp_v1_3 = false;
7719         struct amdgpu_dm_connector *aconn;
7720         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7721
7722         if (!new_stream)
7723                 return;
7724
7725         /*
7726          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7727          * For now it's sufficient to just guard against these conditions.
7728          */
7729
7730         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7731                 return;
7732
7733         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7734         vrr_params = acrtc->dm_irq_params.vrr_params;
7735
7736         if (surface) {
7737                 mod_freesync_handle_preflip(
7738                         dm->freesync_module,
7739                         surface,
7740                         new_stream,
7741                         flip_timestamp_in_us,
7742                         &vrr_params);
7743
7744                 if (adev->family < AMDGPU_FAMILY_AI &&
7745                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7746                         mod_freesync_handle_v_update(dm->freesync_module,
7747                                                      new_stream, &vrr_params);
7748
7749                         /* Need to call this before the frame ends. */
7750                         dc_stream_adjust_vmin_vmax(dm->dc,
7751                                                    new_crtc_state->stream,
7752                                                    &vrr_params.adjust);
7753                 }
7754         }
7755
7756         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7757
7758         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7759                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7760
7761                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7762                         packet_type = PACKET_TYPE_FS_V1;
7763                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7764                         packet_type = PACKET_TYPE_FS_V2;
7765                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7766                         packet_type = PACKET_TYPE_FS_V3;
7767
7768                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7769                                         &new_stream->adaptive_sync_infopacket);
7770         }
7771
7772         mod_freesync_build_vrr_infopacket(
7773                 dm->freesync_module,
7774                 new_stream,
7775                 &vrr_params,
7776                 packet_type,
7777                 TRANSFER_FUNC_UNKNOWN,
7778                 &vrr_infopacket,
7779                 pack_sdp_v1_3);
7780
7781         new_crtc_state->freesync_vrr_info_changed |=
7782                 (memcmp(&new_crtc_state->vrr_infopacket,
7783                         &vrr_infopacket,
7784                         sizeof(vrr_infopacket)) != 0);
7785
7786         acrtc->dm_irq_params.vrr_params = vrr_params;
7787         new_crtc_state->vrr_infopacket = vrr_infopacket;
7788
7789         new_stream->vrr_infopacket = vrr_infopacket;
7790         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7791
7792         if (new_crtc_state->freesync_vrr_info_changed)
7793                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7794                               new_crtc_state->base.crtc->base.id,
7795                               (int)new_crtc_state->base.vrr_enabled,
7796                               (int)vrr_params.state);
7797
7798         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7799 }
7800
7801 static void update_stream_irq_parameters(
7802         struct amdgpu_display_manager *dm,
7803         struct dm_crtc_state *new_crtc_state)
7804 {
7805         struct dc_stream_state *new_stream = new_crtc_state->stream;
7806         struct mod_vrr_params vrr_params;
7807         struct mod_freesync_config config = new_crtc_state->freesync_config;
7808         struct amdgpu_device *adev = dm->adev;
7809         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7810         unsigned long flags;
7811
7812         if (!new_stream)
7813                 return;
7814
7815         /*
7816          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7817          * For now it's sufficient to just guard against these conditions.
7818          */
7819         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7820                 return;
7821
7822         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7823         vrr_params = acrtc->dm_irq_params.vrr_params;
7824
7825         if (new_crtc_state->vrr_supported &&
7826             config.min_refresh_in_uhz &&
7827             config.max_refresh_in_uhz) {
7828                 /*
7829                  * if freesync compatible mode was set, config.state will be set
7830                  * in atomic check
7831                  */
7832                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7833                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7834                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7835                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7836                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7837                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7838                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7839                 } else {
7840                         config.state = new_crtc_state->base.vrr_enabled ?
7841                                                      VRR_STATE_ACTIVE_VARIABLE :
7842                                                      VRR_STATE_INACTIVE;
7843                 }
7844         } else {
7845                 config.state = VRR_STATE_UNSUPPORTED;
7846         }
7847
7848         mod_freesync_build_vrr_params(dm->freesync_module,
7849                                       new_stream,
7850                                       &config, &vrr_params);
7851
7852         new_crtc_state->freesync_config = config;
7853         /* Copy state for access from DM IRQ handler */
7854         acrtc->dm_irq_params.freesync_config = config;
7855         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7856         acrtc->dm_irq_params.vrr_params = vrr_params;
7857         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7858 }
7859
7860 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7861                                             struct dm_crtc_state *new_state)
7862 {
7863         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7864         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7865
7866         if (!old_vrr_active && new_vrr_active) {
7867                 /* Transition VRR inactive -> active:
7868                  * While VRR is active, we must not disable vblank irq, as a
7869                  * reenable after disable would compute bogus vblank/pflip
7870                  * timestamps if it likely happened inside display front-porch.
7871                  *
7872                  * We also need vupdate irq for the actual core vblank handling
7873                  * at end of vblank.
7874                  */
7875                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7876                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7877                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7878                                  __func__, new_state->base.crtc->base.id);
7879         } else if (old_vrr_active && !new_vrr_active) {
7880                 /* Transition VRR active -> inactive:
7881                  * Allow vblank irq disable again for fixed refresh rate.
7882                  */
7883                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7884                 drm_crtc_vblank_put(new_state->base.crtc);
7885                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7886                                  __func__, new_state->base.crtc->base.id);
7887         }
7888 }
7889
7890 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7891 {
7892         struct drm_plane *plane;
7893         struct drm_plane_state *old_plane_state;
7894         int i;
7895
7896         /*
7897          * TODO: Make this per-stream so we don't issue redundant updates for
7898          * commits with multiple streams.
7899          */
7900         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7901                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7902                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7903 }
7904
7905 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7906                                     struct dc_state *dc_state,
7907                                     struct drm_device *dev,
7908                                     struct amdgpu_display_manager *dm,
7909                                     struct drm_crtc *pcrtc,
7910                                     bool wait_for_vblank)
7911 {
7912         u32 i;
7913         u64 timestamp_ns = ktime_get_ns();
7914         struct drm_plane *plane;
7915         struct drm_plane_state *old_plane_state, *new_plane_state;
7916         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7917         struct drm_crtc_state *new_pcrtc_state =
7918                         drm_atomic_get_new_crtc_state(state, pcrtc);
7919         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7920         struct dm_crtc_state *dm_old_crtc_state =
7921                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7922         int planes_count = 0, vpos, hpos;
7923         unsigned long flags;
7924         u32 target_vblank, last_flip_vblank;
7925         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7926         bool cursor_update = false;
7927         bool pflip_present = false;
7928         bool dirty_rects_changed = false;
7929         struct {
7930                 struct dc_surface_update surface_updates[MAX_SURFACES];
7931                 struct dc_plane_info plane_infos[MAX_SURFACES];
7932                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7933                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7934                 struct dc_stream_update stream_update;
7935         } *bundle;
7936
7937         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7938
7939         if (!bundle) {
7940                 dm_error("Failed to allocate update bundle\n");
7941                 goto cleanup;
7942         }
7943
7944         /*
7945          * Disable the cursor first if we're disabling all the planes.
7946          * It'll remain on the screen after the planes are re-enabled
7947          * if we don't.
7948          */
7949         if (acrtc_state->active_planes == 0)
7950                 amdgpu_dm_commit_cursors(state);
7951
7952         /* update planes when needed */
7953         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7954                 struct drm_crtc *crtc = new_plane_state->crtc;
7955                 struct drm_crtc_state *new_crtc_state;
7956                 struct drm_framebuffer *fb = new_plane_state->fb;
7957                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7958                 bool plane_needs_flip;
7959                 struct dc_plane_state *dc_plane;
7960                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7961
7962                 /* Cursor plane is handled after stream updates */
7963                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7964                         if ((fb && crtc == pcrtc) ||
7965                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7966                                 cursor_update = true;
7967
7968                         continue;
7969                 }
7970
7971                 if (!fb || !crtc || pcrtc != crtc)
7972                         continue;
7973
7974                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7975                 if (!new_crtc_state->active)
7976                         continue;
7977
7978                 dc_plane = dm_new_plane_state->dc_state;
7979
7980                 bundle->surface_updates[planes_count].surface = dc_plane;
7981                 if (new_pcrtc_state->color_mgmt_changed) {
7982                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7983                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7984                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7985                 }
7986
7987                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7988                                      &bundle->scaling_infos[planes_count]);
7989
7990                 bundle->surface_updates[planes_count].scaling_info =
7991                         &bundle->scaling_infos[planes_count];
7992
7993                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7994
7995                 pflip_present = pflip_present || plane_needs_flip;
7996
7997                 if (!plane_needs_flip) {
7998                         planes_count += 1;
7999                         continue;
8000                 }
8001
8002                 fill_dc_plane_info_and_addr(
8003                         dm->adev, new_plane_state,
8004                         afb->tiling_flags,
8005                         &bundle->plane_infos[planes_count],
8006                         &bundle->flip_addrs[planes_count].address,
8007                         afb->tmz_surface, false);
8008
8009                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8010                                  new_plane_state->plane->index,
8011                                  bundle->plane_infos[planes_count].dcc.enable);
8012
8013                 bundle->surface_updates[planes_count].plane_info =
8014                         &bundle->plane_infos[planes_count];
8015
8016                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8017                         fill_dc_dirty_rects(plane, old_plane_state,
8018                                             new_plane_state, new_crtc_state,
8019                                             &bundle->flip_addrs[planes_count],
8020                                             &dirty_rects_changed);
8021
8022                         /*
8023                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8024                          * and enabled it again after dirty regions are stable to avoid video glitch.
8025                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8026                          * during the PSR-SU was disabled.
8027                          */
8028                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8029                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8030 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8031                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8032 #endif
8033                             dirty_rects_changed) {
8034                                 mutex_lock(&dm->dc_lock);
8035                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8036                                 timestamp_ns;
8037                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8038                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8039                                 mutex_unlock(&dm->dc_lock);
8040                         }
8041                 }
8042
8043                 /*
8044                  * Only allow immediate flips for fast updates that don't
8045                  * change FB pitch, DCC state, rotation or mirroing.
8046                  */
8047                 bundle->flip_addrs[planes_count].flip_immediate =
8048                         crtc->state->async_flip &&
8049                         acrtc_state->update_type == UPDATE_TYPE_FAST;
8050
8051                 timestamp_ns = ktime_get_ns();
8052                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8053                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8054                 bundle->surface_updates[planes_count].surface = dc_plane;
8055
8056                 if (!bundle->surface_updates[planes_count].surface) {
8057                         DRM_ERROR("No surface for CRTC: id=%d\n",
8058                                         acrtc_attach->crtc_id);
8059                         continue;
8060                 }
8061
8062                 if (plane == pcrtc->primary)
8063                         update_freesync_state_on_stream(
8064                                 dm,
8065                                 acrtc_state,
8066                                 acrtc_state->stream,
8067                                 dc_plane,
8068                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8069
8070                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8071                                  __func__,
8072                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8073                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8074
8075                 planes_count += 1;
8076
8077         }
8078
8079         if (pflip_present) {
8080                 if (!vrr_active) {
8081                         /* Use old throttling in non-vrr fixed refresh rate mode
8082                          * to keep flip scheduling based on target vblank counts
8083                          * working in a backwards compatible way, e.g., for
8084                          * clients using the GLX_OML_sync_control extension or
8085                          * DRI3/Present extension with defined target_msc.
8086                          */
8087                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8088                 }
8089                 else {
8090                         /* For variable refresh rate mode only:
8091                          * Get vblank of last completed flip to avoid > 1 vrr
8092                          * flips per video frame by use of throttling, but allow
8093                          * flip programming anywhere in the possibly large
8094                          * variable vrr vblank interval for fine-grained flip
8095                          * timing control and more opportunity to avoid stutter
8096                          * on late submission of flips.
8097                          */
8098                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8099                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8100                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8101                 }
8102
8103                 target_vblank = last_flip_vblank + wait_for_vblank;
8104
8105                 /*
8106                  * Wait until we're out of the vertical blank period before the one
8107                  * targeted by the flip
8108                  */
8109                 while ((acrtc_attach->enabled &&
8110                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8111                                                             0, &vpos, &hpos, NULL,
8112                                                             NULL, &pcrtc->hwmode)
8113                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8114                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8115                         (int)(target_vblank -
8116                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8117                         usleep_range(1000, 1100);
8118                 }
8119
8120                 /**
8121                  * Prepare the flip event for the pageflip interrupt to handle.
8122                  *
8123                  * This only works in the case where we've already turned on the
8124                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8125                  * from 0 -> n planes we have to skip a hardware generated event
8126                  * and rely on sending it from software.
8127                  */
8128                 if (acrtc_attach->base.state->event &&
8129                     acrtc_state->active_planes > 0) {
8130                         drm_crtc_vblank_get(pcrtc);
8131
8132                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8133
8134                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8135                         prepare_flip_isr(acrtc_attach);
8136
8137                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8138                 }
8139
8140                 if (acrtc_state->stream) {
8141                         if (acrtc_state->freesync_vrr_info_changed)
8142                                 bundle->stream_update.vrr_infopacket =
8143                                         &acrtc_state->stream->vrr_infopacket;
8144                 }
8145         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8146                    acrtc_attach->base.state->event) {
8147                 drm_crtc_vblank_get(pcrtc);
8148
8149                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8150
8151                 acrtc_attach->event = acrtc_attach->base.state->event;
8152                 acrtc_attach->base.state->event = NULL;
8153
8154                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8155         }
8156
8157         /* Update the planes if changed or disable if we don't have any. */
8158         if ((planes_count || acrtc_state->active_planes == 0) &&
8159                 acrtc_state->stream) {
8160                 /*
8161                  * If PSR or idle optimizations are enabled then flush out
8162                  * any pending work before hardware programming.
8163                  */
8164                 if (dm->vblank_control_workqueue)
8165                         flush_workqueue(dm->vblank_control_workqueue);
8166
8167                 bundle->stream_update.stream = acrtc_state->stream;
8168                 if (new_pcrtc_state->mode_changed) {
8169                         bundle->stream_update.src = acrtc_state->stream->src;
8170                         bundle->stream_update.dst = acrtc_state->stream->dst;
8171                 }
8172
8173                 if (new_pcrtc_state->color_mgmt_changed) {
8174                         /*
8175                          * TODO: This isn't fully correct since we've actually
8176                          * already modified the stream in place.
8177                          */
8178                         bundle->stream_update.gamut_remap =
8179                                 &acrtc_state->stream->gamut_remap_matrix;
8180                         bundle->stream_update.output_csc_transform =
8181                                 &acrtc_state->stream->csc_color_matrix;
8182                         bundle->stream_update.out_transfer_func =
8183                                 acrtc_state->stream->out_transfer_func;
8184                 }
8185
8186                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8187                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8188                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8189
8190                 /*
8191                  * If FreeSync state on the stream has changed then we need to
8192                  * re-adjust the min/max bounds now that DC doesn't handle this
8193                  * as part of commit.
8194                  */
8195                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8196                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8197                         dc_stream_adjust_vmin_vmax(
8198                                 dm->dc, acrtc_state->stream,
8199                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8200                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8201                 }
8202                 mutex_lock(&dm->dc_lock);
8203                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8204                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8205                         amdgpu_dm_psr_disable(acrtc_state->stream);
8206
8207                 update_planes_and_stream_adapter(dm->dc,
8208                                          acrtc_state->update_type,
8209                                          planes_count,
8210                                          acrtc_state->stream,
8211                                          &bundle->stream_update,
8212                                          bundle->surface_updates);
8213
8214                 /**
8215                  * Enable or disable the interrupts on the backend.
8216                  *
8217                  * Most pipes are put into power gating when unused.
8218                  *
8219                  * When power gating is enabled on a pipe we lose the
8220                  * interrupt enablement state when power gating is disabled.
8221                  *
8222                  * So we need to update the IRQ control state in hardware
8223                  * whenever the pipe turns on (since it could be previously
8224                  * power gated) or off (since some pipes can't be power gated
8225                  * on some ASICs).
8226                  */
8227                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8228                         dm_update_pflip_irq_state(drm_to_adev(dev),
8229                                                   acrtc_attach);
8230
8231                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8232                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8233                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8234                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8235
8236                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8237                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8238                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8239                         struct amdgpu_dm_connector *aconn =
8240                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8241
8242                         if (aconn->psr_skip_count > 0)
8243                                 aconn->psr_skip_count--;
8244
8245                         /* Allow PSR when skip count is 0. */
8246                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8247
8248                         /*
8249                          * If sink supports PSR SU, there is no need to rely on
8250                          * a vblank event disable request to enable PSR. PSR SU
8251                          * can be enabled immediately once OS demonstrates an
8252                          * adequate number of fast atomic commits to notify KMD
8253                          * of update events. See `vblank_control_worker()`.
8254                          */
8255                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8256                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8257 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8258                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8259 #endif
8260                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8261                             (timestamp_ns -
8262                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8263                             500000000)
8264                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8265                 } else {
8266                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8267                 }
8268
8269                 mutex_unlock(&dm->dc_lock);
8270         }
8271
8272         /*
8273          * Update cursor state *after* programming all the planes.
8274          * This avoids redundant programming in the case where we're going
8275          * to be disabling a single plane - those pipes are being disabled.
8276          */
8277         if (acrtc_state->active_planes)
8278                 amdgpu_dm_commit_cursors(state);
8279
8280 cleanup:
8281         kfree(bundle);
8282 }
8283
8284 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8285                                    struct drm_atomic_state *state)
8286 {
8287         struct amdgpu_device *adev = drm_to_adev(dev);
8288         struct amdgpu_dm_connector *aconnector;
8289         struct drm_connector *connector;
8290         struct drm_connector_state *old_con_state, *new_con_state;
8291         struct drm_crtc_state *new_crtc_state;
8292         struct dm_crtc_state *new_dm_crtc_state;
8293         const struct dc_stream_status *status;
8294         int i, inst;
8295
8296         /* Notify device removals. */
8297         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8298                 if (old_con_state->crtc != new_con_state->crtc) {
8299                         /* CRTC changes require notification. */
8300                         goto notify;
8301                 }
8302
8303                 if (!new_con_state->crtc)
8304                         continue;
8305
8306                 new_crtc_state = drm_atomic_get_new_crtc_state(
8307                         state, new_con_state->crtc);
8308
8309                 if (!new_crtc_state)
8310                         continue;
8311
8312                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8313                         continue;
8314
8315         notify:
8316                 aconnector = to_amdgpu_dm_connector(connector);
8317
8318                 mutex_lock(&adev->dm.audio_lock);
8319                 inst = aconnector->audio_inst;
8320                 aconnector->audio_inst = -1;
8321                 mutex_unlock(&adev->dm.audio_lock);
8322
8323                 amdgpu_dm_audio_eld_notify(adev, inst);
8324         }
8325
8326         /* Notify audio device additions. */
8327         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8328                 if (!new_con_state->crtc)
8329                         continue;
8330
8331                 new_crtc_state = drm_atomic_get_new_crtc_state(
8332                         state, new_con_state->crtc);
8333
8334                 if (!new_crtc_state)
8335                         continue;
8336
8337                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8338                         continue;
8339
8340                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8341                 if (!new_dm_crtc_state->stream)
8342                         continue;
8343
8344                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8345                 if (!status)
8346                         continue;
8347
8348                 aconnector = to_amdgpu_dm_connector(connector);
8349
8350                 mutex_lock(&adev->dm.audio_lock);
8351                 inst = status->audio_inst;
8352                 aconnector->audio_inst = inst;
8353                 mutex_unlock(&adev->dm.audio_lock);
8354
8355                 amdgpu_dm_audio_eld_notify(adev, inst);
8356         }
8357 }
8358
8359 /*
8360  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8361  * @crtc_state: the DRM CRTC state
8362  * @stream_state: the DC stream state.
8363  *
8364  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8365  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8366  */
8367 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8368                                                 struct dc_stream_state *stream_state)
8369 {
8370         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8371 }
8372
8373 /**
8374  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8375  * @state: The atomic state to commit
8376  *
8377  * This will tell DC to commit the constructed DC state from atomic_check,
8378  * programming the hardware. Any failures here implies a hardware failure, since
8379  * atomic check should have filtered anything non-kosher.
8380  */
8381 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8382 {
8383         struct drm_device *dev = state->dev;
8384         struct amdgpu_device *adev = drm_to_adev(dev);
8385         struct amdgpu_display_manager *dm = &adev->dm;
8386         struct dm_atomic_state *dm_state;
8387         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8388         u32 i, j;
8389         struct drm_crtc *crtc;
8390         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8391         unsigned long flags;
8392         bool wait_for_vblank = true;
8393         struct drm_connector *connector;
8394         struct drm_connector_state *old_con_state, *new_con_state;
8395         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8396         int crtc_disable_count = 0;
8397         bool mode_set_reset_required = false;
8398         int r;
8399
8400         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8401
8402         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8403         if (unlikely(r))
8404                 DRM_ERROR("Waiting for fences timed out!");
8405
8406         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8407         drm_dp_mst_atomic_wait_for_dependencies(state);
8408
8409         dm_state = dm_atomic_get_new_state(state);
8410         if (dm_state && dm_state->context) {
8411                 dc_state = dm_state->context;
8412         } else {
8413                 /* No state changes, retain current state. */
8414                 dc_state_temp = dc_create_state(dm->dc);
8415                 ASSERT(dc_state_temp);
8416                 dc_state = dc_state_temp;
8417                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8418         }
8419
8420         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8421                                        new_crtc_state, i) {
8422                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8423
8424                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8425
8426                 if (old_crtc_state->active &&
8427                     (!new_crtc_state->active ||
8428                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8429                         manage_dm_interrupts(adev, acrtc, false);
8430                         dc_stream_release(dm_old_crtc_state->stream);
8431                 }
8432         }
8433
8434         drm_atomic_helper_calc_timestamping_constants(state);
8435
8436         /* update changed items */
8437         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8438                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8439
8440                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8441                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8442
8443                 drm_dbg_state(state->dev,
8444                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8445                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8446                         "connectors_changed:%d\n",
8447                         acrtc->crtc_id,
8448                         new_crtc_state->enable,
8449                         new_crtc_state->active,
8450                         new_crtc_state->planes_changed,
8451                         new_crtc_state->mode_changed,
8452                         new_crtc_state->active_changed,
8453                         new_crtc_state->connectors_changed);
8454
8455                 /* Disable cursor if disabling crtc */
8456                 if (old_crtc_state->active && !new_crtc_state->active) {
8457                         struct dc_cursor_position position;
8458
8459                         memset(&position, 0, sizeof(position));
8460                         mutex_lock(&dm->dc_lock);
8461                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8462                         mutex_unlock(&dm->dc_lock);
8463                 }
8464
8465                 /* Copy all transient state flags into dc state */
8466                 if (dm_new_crtc_state->stream) {
8467                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8468                                                             dm_new_crtc_state->stream);
8469                 }
8470
8471                 /* handles headless hotplug case, updating new_state and
8472                  * aconnector as needed
8473                  */
8474
8475                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8476
8477                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8478
8479                         if (!dm_new_crtc_state->stream) {
8480                                 /*
8481                                  * this could happen because of issues with
8482                                  * userspace notifications delivery.
8483                                  * In this case userspace tries to set mode on
8484                                  * display which is disconnected in fact.
8485                                  * dc_sink is NULL in this case on aconnector.
8486                                  * We expect reset mode will come soon.
8487                                  *
8488                                  * This can also happen when unplug is done
8489                                  * during resume sequence ended
8490                                  *
8491                                  * In this case, we want to pretend we still
8492                                  * have a sink to keep the pipe running so that
8493                                  * hw state is consistent with the sw state
8494                                  */
8495                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8496                                                 __func__, acrtc->base.base.id);
8497                                 continue;
8498                         }
8499
8500                         if (dm_old_crtc_state->stream)
8501                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8502
8503                         pm_runtime_get_noresume(dev->dev);
8504
8505                         acrtc->enabled = true;
8506                         acrtc->hw_mode = new_crtc_state->mode;
8507                         crtc->hwmode = new_crtc_state->mode;
8508                         mode_set_reset_required = true;
8509                 } else if (modereset_required(new_crtc_state)) {
8510                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8511                         /* i.e. reset mode */
8512                         if (dm_old_crtc_state->stream)
8513                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8514
8515                         mode_set_reset_required = true;
8516                 }
8517         } /* for_each_crtc_in_state() */
8518
8519         if (dc_state) {
8520                 /* if there mode set or reset, disable eDP PSR */
8521                 if (mode_set_reset_required) {
8522                         if (dm->vblank_control_workqueue)
8523                                 flush_workqueue(dm->vblank_control_workqueue);
8524
8525                         amdgpu_dm_psr_disable_all(dm);
8526                 }
8527
8528                 dm_enable_per_frame_crtc_master_sync(dc_state);
8529                 mutex_lock(&dm->dc_lock);
8530                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8531
8532                 /* Allow idle optimization when vblank count is 0 for display off */
8533                 if (dm->active_vblank_irq_count == 0)
8534                         dc_allow_idle_optimizations(dm->dc, true);
8535                 mutex_unlock(&dm->dc_lock);
8536         }
8537
8538         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8539                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8540
8541                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8542
8543                 if (dm_new_crtc_state->stream != NULL) {
8544                         const struct dc_stream_status *status =
8545                                         dc_stream_get_status(dm_new_crtc_state->stream);
8546
8547                         if (!status)
8548                                 status = dc_stream_get_status_from_state(dc_state,
8549                                                                          dm_new_crtc_state->stream);
8550                         if (!status)
8551                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8552                         else
8553                                 acrtc->otg_inst = status->primary_otg_inst;
8554                 }
8555         }
8556         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8557                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8558                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8559                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8560
8561                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8562
8563                 if (!connector)
8564                         continue;
8565
8566                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8567                         connector->index, connector->status, connector->dpms);
8568                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8569                         old_con_state->content_protection, new_con_state->content_protection);
8570
8571                 if (aconnector->dc_sink) {
8572                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8573                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8574                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8575                                 aconnector->dc_sink->edid_caps.display_name);
8576                         }
8577                 }
8578
8579                 new_crtc_state = NULL;
8580                 old_crtc_state = NULL;
8581
8582                 if (acrtc) {
8583                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8584                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8585                 }
8586
8587                 if (old_crtc_state)
8588                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8589                         old_crtc_state->enable,
8590                         old_crtc_state->active,
8591                         old_crtc_state->mode_changed,
8592                         old_crtc_state->active_changed,
8593                         old_crtc_state->connectors_changed);
8594
8595                 if (new_crtc_state)
8596                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8597                         new_crtc_state->enable,
8598                         new_crtc_state->active,
8599                         new_crtc_state->mode_changed,
8600                         new_crtc_state->active_changed,
8601                         new_crtc_state->connectors_changed);
8602         }
8603
8604         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8605                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8606                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8607                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8608
8609                 new_crtc_state = NULL;
8610                 old_crtc_state = NULL;
8611
8612                 if (acrtc) {
8613                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8614                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8615                 }
8616
8617                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8618
8619                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8620                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8621                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8622                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8623                         dm_new_con_state->update_hdcp = true;
8624                         continue;
8625                 }
8626
8627                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8628                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8629                         /* when display is unplugged from mst hub, connctor will
8630                          * be destroyed within dm_dp_mst_connector_destroy. connector
8631                          * hdcp perperties, like type, undesired, desired, enabled,
8632                          * will be lost. So, save hdcp properties into hdcp_work within
8633                          * amdgpu_dm_atomic_commit_tail. if the same display is
8634                          * plugged back with same display index, its hdcp properties
8635                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8636                          */
8637
8638                         bool enable_encryption = false;
8639
8640                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8641                                 enable_encryption = true;
8642
8643                         if (aconnector->dc_link && aconnector->dc_sink &&
8644                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8645                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8646                                 struct hdcp_workqueue *hdcp_w =
8647                                         &hdcp_work[aconnector->dc_link->link_index];
8648
8649                                 hdcp_w->hdcp_content_type[connector->index] =
8650                                         new_con_state->hdcp_content_type;
8651                                 hdcp_w->content_protection[connector->index] =
8652                                         new_con_state->content_protection;
8653                         }
8654
8655                         if (new_crtc_state && new_crtc_state->mode_changed &&
8656                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8657                                 enable_encryption = true;
8658
8659                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8660
8661                         hdcp_update_display(
8662                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8663                                 new_con_state->hdcp_content_type, enable_encryption);
8664                 }
8665         }
8666
8667         /* Handle connector state changes */
8668         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8669                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8670                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8671                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8672                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8673                 struct dc_stream_update stream_update;
8674                 struct dc_info_packet hdr_packet;
8675                 struct dc_stream_status *status = NULL;
8676                 bool abm_changed, hdr_changed, scaling_changed;
8677
8678                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8679                 memset(&stream_update, 0, sizeof(stream_update));
8680
8681                 if (acrtc) {
8682                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8683                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8684                 }
8685
8686                 /* Skip any modesets/resets */
8687                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8688                         continue;
8689
8690                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8691                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8692
8693                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8694                                                              dm_old_con_state);
8695
8696                 abm_changed = dm_new_crtc_state->abm_level !=
8697                               dm_old_crtc_state->abm_level;
8698
8699                 hdr_changed =
8700                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8701
8702                 if (!scaling_changed && !abm_changed && !hdr_changed)
8703                         continue;
8704
8705                 stream_update.stream = dm_new_crtc_state->stream;
8706                 if (scaling_changed) {
8707                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8708                                         dm_new_con_state, dm_new_crtc_state->stream);
8709
8710                         stream_update.src = dm_new_crtc_state->stream->src;
8711                         stream_update.dst = dm_new_crtc_state->stream->dst;
8712                 }
8713
8714                 if (abm_changed) {
8715                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8716
8717                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8718                 }
8719
8720                 if (hdr_changed) {
8721                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8722                         stream_update.hdr_static_metadata = &hdr_packet;
8723                 }
8724
8725                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8726
8727                 if (WARN_ON(!status))
8728                         continue;
8729
8730                 WARN_ON(!status->plane_count);
8731
8732                 /*
8733                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8734                  * Here we create an empty update on each plane.
8735                  * To fix this, DC should permit updating only stream properties.
8736                  */
8737                 for (j = 0; j < status->plane_count; j++)
8738                         dummy_updates[j].surface = status->plane_states[0];
8739
8740
8741                 mutex_lock(&dm->dc_lock);
8742                 dc_update_planes_and_stream(dm->dc,
8743                                             dummy_updates,
8744                                             status->plane_count,
8745                                             dm_new_crtc_state->stream,
8746                                             &stream_update);
8747                 mutex_unlock(&dm->dc_lock);
8748         }
8749
8750         /**
8751          * Enable interrupts for CRTCs that are newly enabled or went through
8752          * a modeset. It was intentionally deferred until after the front end
8753          * state was modified to wait until the OTG was on and so the IRQ
8754          * handlers didn't access stale or invalid state.
8755          */
8756         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8757                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8758 #ifdef CONFIG_DEBUG_FS
8759                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8760 #endif
8761                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8762                 if (old_crtc_state->active && !new_crtc_state->active)
8763                         crtc_disable_count++;
8764
8765                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8766                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8767
8768                 /* For freesync config update on crtc state and params for irq */
8769                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8770
8771 #ifdef CONFIG_DEBUG_FS
8772                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8773                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8774                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8775 #endif
8776
8777                 if (new_crtc_state->active &&
8778                     (!old_crtc_state->active ||
8779                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8780                         dc_stream_retain(dm_new_crtc_state->stream);
8781                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8782                         manage_dm_interrupts(adev, acrtc, true);
8783                 }
8784                 /* Handle vrr on->off / off->on transitions */
8785                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8786
8787 #ifdef CONFIG_DEBUG_FS
8788                 if (new_crtc_state->active &&
8789                     (!old_crtc_state->active ||
8790                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8791                         /**
8792                          * Frontend may have changed so reapply the CRC capture
8793                          * settings for the stream.
8794                          */
8795                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8796 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8797                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8798                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8799                                         acrtc->dm_irq_params.window_param.update_win = true;
8800
8801                                         /**
8802                                          * It takes 2 frames for HW to stably generate CRC when
8803                                          * resuming from suspend, so we set skip_frame_cnt 2.
8804                                          */
8805                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8806                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8807                                 }
8808 #endif
8809                                 if (amdgpu_dm_crtc_configure_crc_source(
8810                                         crtc, dm_new_crtc_state, cur_crc_src))
8811                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8812                         }
8813                 }
8814 #endif
8815         }
8816
8817         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8818                 if (new_crtc_state->async_flip)
8819                         wait_for_vblank = false;
8820
8821         /* update planes when needed per crtc*/
8822         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8823                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8824
8825                 if (dm_new_crtc_state->stream)
8826                         amdgpu_dm_commit_planes(state, dc_state, dev,
8827                                                 dm, crtc, wait_for_vblank);
8828         }
8829
8830         /* Update audio instances for each connector. */
8831         amdgpu_dm_commit_audio(dev, state);
8832
8833         /* restore the backlight level */
8834         for (i = 0; i < dm->num_of_edps; i++) {
8835                 if (dm->backlight_dev[i] &&
8836                     (dm->actual_brightness[i] != dm->brightness[i]))
8837                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8838         }
8839
8840         /*
8841          * send vblank event on all events not handled in flip and
8842          * mark consumed event for drm_atomic_helper_commit_hw_done
8843          */
8844         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8845         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8846
8847                 if (new_crtc_state->event)
8848                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8849
8850                 new_crtc_state->event = NULL;
8851         }
8852         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8853
8854         /* Signal HW programming completion */
8855         drm_atomic_helper_commit_hw_done(state);
8856
8857         if (wait_for_vblank)
8858                 drm_atomic_helper_wait_for_flip_done(dev, state);
8859
8860         drm_atomic_helper_cleanup_planes(dev, state);
8861
8862         /* return the stolen vga memory back to VRAM */
8863         if (!adev->mman.keep_stolen_vga_memory)
8864                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8865         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8866
8867         /*
8868          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8869          * so we can put the GPU into runtime suspend if we're not driving any
8870          * displays anymore
8871          */
8872         for (i = 0; i < crtc_disable_count; i++)
8873                 pm_runtime_put_autosuspend(dev->dev);
8874         pm_runtime_mark_last_busy(dev->dev);
8875
8876         if (dc_state_temp)
8877                 dc_release_state(dc_state_temp);
8878 }
8879
8880 static int dm_force_atomic_commit(struct drm_connector *connector)
8881 {
8882         int ret = 0;
8883         struct drm_device *ddev = connector->dev;
8884         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8885         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8886         struct drm_plane *plane = disconnected_acrtc->base.primary;
8887         struct drm_connector_state *conn_state;
8888         struct drm_crtc_state *crtc_state;
8889         struct drm_plane_state *plane_state;
8890
8891         if (!state)
8892                 return -ENOMEM;
8893
8894         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8895
8896         /* Construct an atomic state to restore previous display setting */
8897
8898         /*
8899          * Attach connectors to drm_atomic_state
8900          */
8901         conn_state = drm_atomic_get_connector_state(state, connector);
8902
8903         ret = PTR_ERR_OR_ZERO(conn_state);
8904         if (ret)
8905                 goto out;
8906
8907         /* Attach crtc to drm_atomic_state*/
8908         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8909
8910         ret = PTR_ERR_OR_ZERO(crtc_state);
8911         if (ret)
8912                 goto out;
8913
8914         /* force a restore */
8915         crtc_state->mode_changed = true;
8916
8917         /* Attach plane to drm_atomic_state */
8918         plane_state = drm_atomic_get_plane_state(state, plane);
8919
8920         ret = PTR_ERR_OR_ZERO(plane_state);
8921         if (ret)
8922                 goto out;
8923
8924         /* Call commit internally with the state we just constructed */
8925         ret = drm_atomic_commit(state);
8926
8927 out:
8928         drm_atomic_state_put(state);
8929         if (ret)
8930                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8931
8932         return ret;
8933 }
8934
8935 /*
8936  * This function handles all cases when set mode does not come upon hotplug.
8937  * This includes when a display is unplugged then plugged back into the
8938  * same port and when running without usermode desktop manager supprot
8939  */
8940 void dm_restore_drm_connector_state(struct drm_device *dev,
8941                                     struct drm_connector *connector)
8942 {
8943         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8944         struct amdgpu_crtc *disconnected_acrtc;
8945         struct dm_crtc_state *acrtc_state;
8946
8947         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8948                 return;
8949
8950         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8951         if (!disconnected_acrtc)
8952                 return;
8953
8954         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8955         if (!acrtc_state->stream)
8956                 return;
8957
8958         /*
8959          * If the previous sink is not released and different from the current,
8960          * we deduce we are in a state where we can not rely on usermode call
8961          * to turn on the display, so we do it here
8962          */
8963         if (acrtc_state->stream->sink != aconnector->dc_sink)
8964                 dm_force_atomic_commit(&aconnector->base);
8965 }
8966
8967 /*
8968  * Grabs all modesetting locks to serialize against any blocking commits,
8969  * Waits for completion of all non blocking commits.
8970  */
8971 static int do_aquire_global_lock(struct drm_device *dev,
8972                                  struct drm_atomic_state *state)
8973 {
8974         struct drm_crtc *crtc;
8975         struct drm_crtc_commit *commit;
8976         long ret;
8977
8978         /*
8979          * Adding all modeset locks to aquire_ctx will
8980          * ensure that when the framework release it the
8981          * extra locks we are locking here will get released to
8982          */
8983         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8984         if (ret)
8985                 return ret;
8986
8987         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8988                 spin_lock(&crtc->commit_lock);
8989                 commit = list_first_entry_or_null(&crtc->commit_list,
8990                                 struct drm_crtc_commit, commit_entry);
8991                 if (commit)
8992                         drm_crtc_commit_get(commit);
8993                 spin_unlock(&crtc->commit_lock);
8994
8995                 if (!commit)
8996                         continue;
8997
8998                 /*
8999                  * Make sure all pending HW programming completed and
9000                  * page flips done
9001                  */
9002                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9003
9004                 if (ret > 0)
9005                         ret = wait_for_completion_interruptible_timeout(
9006                                         &commit->flip_done, 10*HZ);
9007
9008                 if (ret == 0)
9009                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9010                                   "timed out\n", crtc->base.id, crtc->name);
9011
9012                 drm_crtc_commit_put(commit);
9013         }
9014
9015         return ret < 0 ? ret : 0;
9016 }
9017
9018 static void get_freesync_config_for_crtc(
9019         struct dm_crtc_state *new_crtc_state,
9020         struct dm_connector_state *new_con_state)
9021 {
9022         struct mod_freesync_config config = {0};
9023         struct amdgpu_dm_connector *aconnector =
9024                         to_amdgpu_dm_connector(new_con_state->base.connector);
9025         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9026         int vrefresh = drm_mode_vrefresh(mode);
9027         bool fs_vid_mode = false;
9028
9029         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9030                                         vrefresh >= aconnector->min_vfreq &&
9031                                         vrefresh <= aconnector->max_vfreq;
9032
9033         if (new_crtc_state->vrr_supported) {
9034                 new_crtc_state->stream->ignore_msa_timing_param = true;
9035                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9036
9037                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9038                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9039                 config.vsif_supported = true;
9040                 config.btr = true;
9041
9042                 if (fs_vid_mode) {
9043                         config.state = VRR_STATE_ACTIVE_FIXED;
9044                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9045                         goto out;
9046                 } else if (new_crtc_state->base.vrr_enabled) {
9047                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9048                 } else {
9049                         config.state = VRR_STATE_INACTIVE;
9050                 }
9051         }
9052 out:
9053         new_crtc_state->freesync_config = config;
9054 }
9055
9056 static void reset_freesync_config_for_crtc(
9057         struct dm_crtc_state *new_crtc_state)
9058 {
9059         new_crtc_state->vrr_supported = false;
9060
9061         memset(&new_crtc_state->vrr_infopacket, 0,
9062                sizeof(new_crtc_state->vrr_infopacket));
9063 }
9064
9065 static bool
9066 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9067                                  struct drm_crtc_state *new_crtc_state)
9068 {
9069         const struct drm_display_mode *old_mode, *new_mode;
9070
9071         if (!old_crtc_state || !new_crtc_state)
9072                 return false;
9073
9074         old_mode = &old_crtc_state->mode;
9075         new_mode = &new_crtc_state->mode;
9076
9077         if (old_mode->clock       == new_mode->clock &&
9078             old_mode->hdisplay    == new_mode->hdisplay &&
9079             old_mode->vdisplay    == new_mode->vdisplay &&
9080             old_mode->htotal      == new_mode->htotal &&
9081             old_mode->vtotal      != new_mode->vtotal &&
9082             old_mode->hsync_start == new_mode->hsync_start &&
9083             old_mode->vsync_start != new_mode->vsync_start &&
9084             old_mode->hsync_end   == new_mode->hsync_end &&
9085             old_mode->vsync_end   != new_mode->vsync_end &&
9086             old_mode->hskew       == new_mode->hskew &&
9087             old_mode->vscan       == new_mode->vscan &&
9088             (old_mode->vsync_end - old_mode->vsync_start) ==
9089             (new_mode->vsync_end - new_mode->vsync_start))
9090                 return true;
9091
9092         return false;
9093 }
9094
9095 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9096         u64 num, den, res;
9097         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9098
9099         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9100
9101         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9102         den = (unsigned long long)new_crtc_state->mode.htotal *
9103               (unsigned long long)new_crtc_state->mode.vtotal;
9104
9105         res = div_u64(num, den);
9106         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9107 }
9108
9109 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9110                          struct drm_atomic_state *state,
9111                          struct drm_crtc *crtc,
9112                          struct drm_crtc_state *old_crtc_state,
9113                          struct drm_crtc_state *new_crtc_state,
9114                          bool enable,
9115                          bool *lock_and_validation_needed)
9116 {
9117         struct dm_atomic_state *dm_state = NULL;
9118         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9119         struct dc_stream_state *new_stream;
9120         int ret = 0;
9121
9122         /*
9123          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9124          * update changed items
9125          */
9126         struct amdgpu_crtc *acrtc = NULL;
9127         struct amdgpu_dm_connector *aconnector = NULL;
9128         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9129         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9130
9131         new_stream = NULL;
9132
9133         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9134         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9135         acrtc = to_amdgpu_crtc(crtc);
9136         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9137
9138         /* TODO This hack should go away */
9139         if (aconnector && enable) {
9140                 /* Make sure fake sink is created in plug-in scenario */
9141                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9142                                                             &aconnector->base);
9143                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9144                                                             &aconnector->base);
9145
9146                 if (IS_ERR(drm_new_conn_state)) {
9147                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9148                         goto fail;
9149                 }
9150
9151                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9152                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9153
9154                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9155                         goto skip_modeset;
9156
9157                 new_stream = create_validate_stream_for_sink(aconnector,
9158                                                              &new_crtc_state->mode,
9159                                                              dm_new_conn_state,
9160                                                              dm_old_crtc_state->stream);
9161
9162                 /*
9163                  * we can have no stream on ACTION_SET if a display
9164                  * was disconnected during S3, in this case it is not an
9165                  * error, the OS will be updated after detection, and
9166                  * will do the right thing on next atomic commit
9167                  */
9168
9169                 if (!new_stream) {
9170                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9171                                         __func__, acrtc->base.base.id);
9172                         ret = -ENOMEM;
9173                         goto fail;
9174                 }
9175
9176                 /*
9177                  * TODO: Check VSDB bits to decide whether this should
9178                  * be enabled or not.
9179                  */
9180                 new_stream->triggered_crtc_reset.enabled =
9181                         dm->force_timing_sync;
9182
9183                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9184
9185                 ret = fill_hdr_info_packet(drm_new_conn_state,
9186                                            &new_stream->hdr_static_metadata);
9187                 if (ret)
9188                         goto fail;
9189
9190                 /*
9191                  * If we already removed the old stream from the context
9192                  * (and set the new stream to NULL) then we can't reuse
9193                  * the old stream even if the stream and scaling are unchanged.
9194                  * We'll hit the BUG_ON and black screen.
9195                  *
9196                  * TODO: Refactor this function to allow this check to work
9197                  * in all conditions.
9198                  */
9199                 if (amdgpu_freesync_vid_mode &&
9200                     dm_new_crtc_state->stream &&
9201                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9202                         goto skip_modeset;
9203
9204                 if (dm_new_crtc_state->stream &&
9205                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9206                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9207                         new_crtc_state->mode_changed = false;
9208                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9209                                          new_crtc_state->mode_changed);
9210                 }
9211         }
9212
9213         /* mode_changed flag may get updated above, need to check again */
9214         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9215                 goto skip_modeset;
9216
9217         drm_dbg_state(state->dev,
9218                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9219                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9220                 "connectors_changed:%d\n",
9221                 acrtc->crtc_id,
9222                 new_crtc_state->enable,
9223                 new_crtc_state->active,
9224                 new_crtc_state->planes_changed,
9225                 new_crtc_state->mode_changed,
9226                 new_crtc_state->active_changed,
9227                 new_crtc_state->connectors_changed);
9228
9229         /* Remove stream for any changed/disabled CRTC */
9230         if (!enable) {
9231
9232                 if (!dm_old_crtc_state->stream)
9233                         goto skip_modeset;
9234
9235                 /* Unset freesync video if it was active before */
9236                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9237                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9238                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9239                 }
9240
9241                 /* Now check if we should set freesync video mode */
9242                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9243                     is_timing_unchanged_for_freesync(new_crtc_state,
9244                                                      old_crtc_state)) {
9245                         new_crtc_state->mode_changed = false;
9246                         DRM_DEBUG_DRIVER(
9247                                 "Mode change not required for front porch change, "
9248                                 "setting mode_changed to %d",
9249                                 new_crtc_state->mode_changed);
9250
9251                         set_freesync_fixed_config(dm_new_crtc_state);
9252
9253                         goto skip_modeset;
9254                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9255                            is_freesync_video_mode(&new_crtc_state->mode,
9256                                                   aconnector)) {
9257                         struct drm_display_mode *high_mode;
9258
9259                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9260                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9261                                 set_freesync_fixed_config(dm_new_crtc_state);
9262                         }
9263                 }
9264
9265                 ret = dm_atomic_get_state(state, &dm_state);
9266                 if (ret)
9267                         goto fail;
9268
9269                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9270                                 crtc->base.id);
9271
9272                 /* i.e. reset mode */
9273                 if (dc_remove_stream_from_ctx(
9274                                 dm->dc,
9275                                 dm_state->context,
9276                                 dm_old_crtc_state->stream) != DC_OK) {
9277                         ret = -EINVAL;
9278                         goto fail;
9279                 }
9280
9281                 dc_stream_release(dm_old_crtc_state->stream);
9282                 dm_new_crtc_state->stream = NULL;
9283
9284                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9285
9286                 *lock_and_validation_needed = true;
9287
9288         } else {/* Add stream for any updated/enabled CRTC */
9289                 /*
9290                  * Quick fix to prevent NULL pointer on new_stream when
9291                  * added MST connectors not found in existing crtc_state in the chained mode
9292                  * TODO: need to dig out the root cause of that
9293                  */
9294                 if (!aconnector)
9295                         goto skip_modeset;
9296
9297                 if (modereset_required(new_crtc_state))
9298                         goto skip_modeset;
9299
9300                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9301                                      dm_old_crtc_state->stream)) {
9302
9303                         WARN_ON(dm_new_crtc_state->stream);
9304
9305                         ret = dm_atomic_get_state(state, &dm_state);
9306                         if (ret)
9307                                 goto fail;
9308
9309                         dm_new_crtc_state->stream = new_stream;
9310
9311                         dc_stream_retain(new_stream);
9312
9313                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9314                                          crtc->base.id);
9315
9316                         if (dc_add_stream_to_ctx(
9317                                         dm->dc,
9318                                         dm_state->context,
9319                                         dm_new_crtc_state->stream) != DC_OK) {
9320                                 ret = -EINVAL;
9321                                 goto fail;
9322                         }
9323
9324                         *lock_and_validation_needed = true;
9325                 }
9326         }
9327
9328 skip_modeset:
9329         /* Release extra reference */
9330         if (new_stream)
9331                  dc_stream_release(new_stream);
9332
9333         /*
9334          * We want to do dc stream updates that do not require a
9335          * full modeset below.
9336          */
9337         if (!(enable && aconnector && new_crtc_state->active))
9338                 return 0;
9339         /*
9340          * Given above conditions, the dc state cannot be NULL because:
9341          * 1. We're in the process of enabling CRTCs (just been added
9342          *    to the dc context, or already is on the context)
9343          * 2. Has a valid connector attached, and
9344          * 3. Is currently active and enabled.
9345          * => The dc stream state currently exists.
9346          */
9347         BUG_ON(dm_new_crtc_state->stream == NULL);
9348
9349         /* Scaling or underscan settings */
9350         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9351                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9352                 update_stream_scaling_settings(
9353                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9354
9355         /* ABM settings */
9356         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9357
9358         /*
9359          * Color management settings. We also update color properties
9360          * when a modeset is needed, to ensure it gets reprogrammed.
9361          */
9362         if (dm_new_crtc_state->base.color_mgmt_changed ||
9363             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9364                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9365                 if (ret)
9366                         goto fail;
9367         }
9368
9369         /* Update Freesync settings. */
9370         get_freesync_config_for_crtc(dm_new_crtc_state,
9371                                      dm_new_conn_state);
9372
9373         return ret;
9374
9375 fail:
9376         if (new_stream)
9377                 dc_stream_release(new_stream);
9378         return ret;
9379 }
9380
9381 static bool should_reset_plane(struct drm_atomic_state *state,
9382                                struct drm_plane *plane,
9383                                struct drm_plane_state *old_plane_state,
9384                                struct drm_plane_state *new_plane_state)
9385 {
9386         struct drm_plane *other;
9387         struct drm_plane_state *old_other_state, *new_other_state;
9388         struct drm_crtc_state *new_crtc_state;
9389         int i;
9390
9391         /*
9392          * TODO: Remove this hack once the checks below are sufficient
9393          * enough to determine when we need to reset all the planes on
9394          * the stream.
9395          */
9396         if (state->allow_modeset)
9397                 return true;
9398
9399         /* Exit early if we know that we're adding or removing the plane. */
9400         if (old_plane_state->crtc != new_plane_state->crtc)
9401                 return true;
9402
9403         /* old crtc == new_crtc == NULL, plane not in context. */
9404         if (!new_plane_state->crtc)
9405                 return false;
9406
9407         new_crtc_state =
9408                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9409
9410         if (!new_crtc_state)
9411                 return true;
9412
9413         /* CRTC Degamma changes currently require us to recreate planes. */
9414         if (new_crtc_state->color_mgmt_changed)
9415                 return true;
9416
9417         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9418                 return true;
9419
9420         /*
9421          * If there are any new primary or overlay planes being added or
9422          * removed then the z-order can potentially change. To ensure
9423          * correct z-order and pipe acquisition the current DC architecture
9424          * requires us to remove and recreate all existing planes.
9425          *
9426          * TODO: Come up with a more elegant solution for this.
9427          */
9428         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9429                 struct amdgpu_framebuffer *old_afb, *new_afb;
9430                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9431                         continue;
9432
9433                 if (old_other_state->crtc != new_plane_state->crtc &&
9434                     new_other_state->crtc != new_plane_state->crtc)
9435                         continue;
9436
9437                 if (old_other_state->crtc != new_other_state->crtc)
9438                         return true;
9439
9440                 /* Src/dst size and scaling updates. */
9441                 if (old_other_state->src_w != new_other_state->src_w ||
9442                     old_other_state->src_h != new_other_state->src_h ||
9443                     old_other_state->crtc_w != new_other_state->crtc_w ||
9444                     old_other_state->crtc_h != new_other_state->crtc_h)
9445                         return true;
9446
9447                 /* Rotation / mirroring updates. */
9448                 if (old_other_state->rotation != new_other_state->rotation)
9449                         return true;
9450
9451                 /* Blending updates. */
9452                 if (old_other_state->pixel_blend_mode !=
9453                     new_other_state->pixel_blend_mode)
9454                         return true;
9455
9456                 /* Alpha updates. */
9457                 if (old_other_state->alpha != new_other_state->alpha)
9458                         return true;
9459
9460                 /* Colorspace changes. */
9461                 if (old_other_state->color_range != new_other_state->color_range ||
9462                     old_other_state->color_encoding != new_other_state->color_encoding)
9463                         return true;
9464
9465                 /* Framebuffer checks fall at the end. */
9466                 if (!old_other_state->fb || !new_other_state->fb)
9467                         continue;
9468
9469                 /* Pixel format changes can require bandwidth updates. */
9470                 if (old_other_state->fb->format != new_other_state->fb->format)
9471                         return true;
9472
9473                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9474                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9475
9476                 /* Tiling and DCC changes also require bandwidth updates. */
9477                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9478                     old_afb->base.modifier != new_afb->base.modifier)
9479                         return true;
9480         }
9481
9482         return false;
9483 }
9484
9485 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9486                               struct drm_plane_state *new_plane_state,
9487                               struct drm_framebuffer *fb)
9488 {
9489         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9490         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9491         unsigned int pitch;
9492         bool linear;
9493
9494         if (fb->width > new_acrtc->max_cursor_width ||
9495             fb->height > new_acrtc->max_cursor_height) {
9496                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9497                                  new_plane_state->fb->width,
9498                                  new_plane_state->fb->height);
9499                 return -EINVAL;
9500         }
9501         if (new_plane_state->src_w != fb->width << 16 ||
9502             new_plane_state->src_h != fb->height << 16) {
9503                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9504                 return -EINVAL;
9505         }
9506
9507         /* Pitch in pixels */
9508         pitch = fb->pitches[0] / fb->format->cpp[0];
9509
9510         if (fb->width != pitch) {
9511                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9512                                  fb->width, pitch);
9513                 return -EINVAL;
9514         }
9515
9516         switch (pitch) {
9517         case 64:
9518         case 128:
9519         case 256:
9520                 /* FB pitch is supported by cursor plane */
9521                 break;
9522         default:
9523                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9524                 return -EINVAL;
9525         }
9526
9527         /* Core DRM takes care of checking FB modifiers, so we only need to
9528          * check tiling flags when the FB doesn't have a modifier. */
9529         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9530                 if (adev->family < AMDGPU_FAMILY_AI) {
9531                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9532                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9533                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9534                 } else {
9535                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9536                 }
9537                 if (!linear) {
9538                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9539                         return -EINVAL;
9540                 }
9541         }
9542
9543         return 0;
9544 }
9545
9546 static int dm_update_plane_state(struct dc *dc,
9547                                  struct drm_atomic_state *state,
9548                                  struct drm_plane *plane,
9549                                  struct drm_plane_state *old_plane_state,
9550                                  struct drm_plane_state *new_plane_state,
9551                                  bool enable,
9552                                  bool *lock_and_validation_needed,
9553                                  bool *is_top_most_overlay)
9554 {
9555
9556         struct dm_atomic_state *dm_state = NULL;
9557         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9558         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9559         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9560         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9561         struct amdgpu_crtc *new_acrtc;
9562         bool needs_reset;
9563         int ret = 0;
9564
9565
9566         new_plane_crtc = new_plane_state->crtc;
9567         old_plane_crtc = old_plane_state->crtc;
9568         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9569         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9570
9571         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9572                 if (!enable || !new_plane_crtc ||
9573                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9574                         return 0;
9575
9576                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9577
9578                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9579                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9580                         return -EINVAL;
9581                 }
9582
9583                 if (new_plane_state->fb) {
9584                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9585                                                  new_plane_state->fb);
9586                         if (ret)
9587                                 return ret;
9588                 }
9589
9590                 return 0;
9591         }
9592
9593         needs_reset = should_reset_plane(state, plane, old_plane_state,
9594                                          new_plane_state);
9595
9596         /* Remove any changed/removed planes */
9597         if (!enable) {
9598                 if (!needs_reset)
9599                         return 0;
9600
9601                 if (!old_plane_crtc)
9602                         return 0;
9603
9604                 old_crtc_state = drm_atomic_get_old_crtc_state(
9605                                 state, old_plane_crtc);
9606                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9607
9608                 if (!dm_old_crtc_state->stream)
9609                         return 0;
9610
9611                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9612                                 plane->base.id, old_plane_crtc->base.id);
9613
9614                 ret = dm_atomic_get_state(state, &dm_state);
9615                 if (ret)
9616                         return ret;
9617
9618                 if (!dc_remove_plane_from_context(
9619                                 dc,
9620                                 dm_old_crtc_state->stream,
9621                                 dm_old_plane_state->dc_state,
9622                                 dm_state->context)) {
9623
9624                         return -EINVAL;
9625                 }
9626
9627
9628                 dc_plane_state_release(dm_old_plane_state->dc_state);
9629                 dm_new_plane_state->dc_state = NULL;
9630
9631                 *lock_and_validation_needed = true;
9632
9633         } else { /* Add new planes */
9634                 struct dc_plane_state *dc_new_plane_state;
9635
9636                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9637                         return 0;
9638
9639                 if (!new_plane_crtc)
9640                         return 0;
9641
9642                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9643                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9644
9645                 if (!dm_new_crtc_state->stream)
9646                         return 0;
9647
9648                 if (!needs_reset)
9649                         return 0;
9650
9651                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9652                 if (ret)
9653                         return ret;
9654
9655                 WARN_ON(dm_new_plane_state->dc_state);
9656
9657                 dc_new_plane_state = dc_create_plane_state(dc);
9658                 if (!dc_new_plane_state)
9659                         return -ENOMEM;
9660
9661                 /* Block top most plane from being a video plane */
9662                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9663                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9664                                 return -EINVAL;
9665                         else
9666                                 *is_top_most_overlay = false;
9667                 }
9668
9669                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9670                                  plane->base.id, new_plane_crtc->base.id);
9671
9672                 ret = fill_dc_plane_attributes(
9673                         drm_to_adev(new_plane_crtc->dev),
9674                         dc_new_plane_state,
9675                         new_plane_state,
9676                         new_crtc_state);
9677                 if (ret) {
9678                         dc_plane_state_release(dc_new_plane_state);
9679                         return ret;
9680                 }
9681
9682                 ret = dm_atomic_get_state(state, &dm_state);
9683                 if (ret) {
9684                         dc_plane_state_release(dc_new_plane_state);
9685                         return ret;
9686                 }
9687
9688                 /*
9689                  * Any atomic check errors that occur after this will
9690                  * not need a release. The plane state will be attached
9691                  * to the stream, and therefore part of the atomic
9692                  * state. It'll be released when the atomic state is
9693                  * cleaned.
9694                  */
9695                 if (!dc_add_plane_to_context(
9696                                 dc,
9697                                 dm_new_crtc_state->stream,
9698                                 dc_new_plane_state,
9699                                 dm_state->context)) {
9700
9701                         dc_plane_state_release(dc_new_plane_state);
9702                         return -EINVAL;
9703                 }
9704
9705                 dm_new_plane_state->dc_state = dc_new_plane_state;
9706
9707                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9708
9709                 /* Tell DC to do a full surface update every time there
9710                  * is a plane change. Inefficient, but works for now.
9711                  */
9712                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9713
9714                 *lock_and_validation_needed = true;
9715         }
9716
9717
9718         return ret;
9719 }
9720
9721 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9722                                        int *src_w, int *src_h)
9723 {
9724         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9725         case DRM_MODE_ROTATE_90:
9726         case DRM_MODE_ROTATE_270:
9727                 *src_w = plane_state->src_h >> 16;
9728                 *src_h = plane_state->src_w >> 16;
9729                 break;
9730         case DRM_MODE_ROTATE_0:
9731         case DRM_MODE_ROTATE_180:
9732         default:
9733                 *src_w = plane_state->src_w >> 16;
9734                 *src_h = plane_state->src_h >> 16;
9735                 break;
9736         }
9737 }
9738
9739 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9740                                 struct drm_crtc *crtc,
9741                                 struct drm_crtc_state *new_crtc_state)
9742 {
9743         struct drm_plane *cursor = crtc->cursor, *underlying;
9744         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9745         int i;
9746         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9747         int cursor_src_w, cursor_src_h;
9748         int underlying_src_w, underlying_src_h;
9749
9750         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9751          * cursor per pipe but it's going to inherit the scaling and
9752          * positioning from the underlying pipe. Check the cursor plane's
9753          * blending properties match the underlying planes'. */
9754
9755         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9756         if (!new_cursor_state || !new_cursor_state->fb) {
9757                 return 0;
9758         }
9759
9760         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9761         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9762         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9763
9764         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9765                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9766                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9767                         continue;
9768
9769                 /* Ignore disabled planes */
9770                 if (!new_underlying_state->fb)
9771                         continue;
9772
9773                 dm_get_oriented_plane_size(new_underlying_state,
9774                                            &underlying_src_w, &underlying_src_h);
9775                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9776                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9777
9778                 if (cursor_scale_w != underlying_scale_w ||
9779                     cursor_scale_h != underlying_scale_h) {
9780                         drm_dbg_atomic(crtc->dev,
9781                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9782                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9783                         return -EINVAL;
9784                 }
9785
9786                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9787                 if (new_underlying_state->crtc_x <= 0 &&
9788                     new_underlying_state->crtc_y <= 0 &&
9789                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9790                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9791                         break;
9792         }
9793
9794         return 0;
9795 }
9796
9797 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9798 {
9799         struct drm_connector *connector;
9800         struct drm_connector_state *conn_state, *old_conn_state;
9801         struct amdgpu_dm_connector *aconnector = NULL;
9802         int i;
9803         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9804                 if (!conn_state->crtc)
9805                         conn_state = old_conn_state;
9806
9807                 if (conn_state->crtc != crtc)
9808                         continue;
9809
9810                 aconnector = to_amdgpu_dm_connector(connector);
9811                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9812                         aconnector = NULL;
9813                 else
9814                         break;
9815         }
9816
9817         if (!aconnector)
9818                 return 0;
9819
9820         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9821 }
9822
9823 /**
9824  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9825  *
9826  * @dev: The DRM device
9827  * @state: The atomic state to commit
9828  *
9829  * Validate that the given atomic state is programmable by DC into hardware.
9830  * This involves constructing a &struct dc_state reflecting the new hardware
9831  * state we wish to commit, then querying DC to see if it is programmable. It's
9832  * important not to modify the existing DC state. Otherwise, atomic_check
9833  * may unexpectedly commit hardware changes.
9834  *
9835  * When validating the DC state, it's important that the right locks are
9836  * acquired. For full updates case which removes/adds/updates streams on one
9837  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9838  * that any such full update commit will wait for completion of any outstanding
9839  * flip using DRMs synchronization events.
9840  *
9841  * Note that DM adds the affected connectors for all CRTCs in state, when that
9842  * might not seem necessary. This is because DC stream creation requires the
9843  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9844  * be possible but non-trivial - a possible TODO item.
9845  *
9846  * Return: -Error code if validation failed.
9847  */
9848 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9849                                   struct drm_atomic_state *state)
9850 {
9851         struct amdgpu_device *adev = drm_to_adev(dev);
9852         struct dm_atomic_state *dm_state = NULL;
9853         struct dc *dc = adev->dm.dc;
9854         struct drm_connector *connector;
9855         struct drm_connector_state *old_con_state, *new_con_state;
9856         struct drm_crtc *crtc;
9857         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9858         struct drm_plane *plane;
9859         struct drm_plane_state *old_plane_state, *new_plane_state;
9860         enum dc_status status;
9861         int ret, i;
9862         bool lock_and_validation_needed = false;
9863         bool is_top_most_overlay = true;
9864         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9865         struct drm_dp_mst_topology_mgr *mgr;
9866         struct drm_dp_mst_topology_state *mst_state;
9867         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9868
9869         trace_amdgpu_dm_atomic_check_begin(state);
9870
9871         ret = drm_atomic_helper_check_modeset(dev, state);
9872         if (ret) {
9873                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9874                 goto fail;
9875         }
9876
9877         /* Check connector changes */
9878         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9879                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9880                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9881
9882                 /* Skip connectors that are disabled or part of modeset already. */
9883                 if (!new_con_state->crtc)
9884                         continue;
9885
9886                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9887                 if (IS_ERR(new_crtc_state)) {
9888                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9889                         ret = PTR_ERR(new_crtc_state);
9890                         goto fail;
9891                 }
9892
9893                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9894                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9895                         new_crtc_state->connectors_changed = true;
9896         }
9897
9898         if (dc_resource_is_dsc_encoding_supported(dc)) {
9899                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9900                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9901                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9902                                 if (ret) {
9903                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9904                                         goto fail;
9905                                 }
9906                         }
9907                 }
9908         }
9909         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9910                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9911
9912                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9913                     !new_crtc_state->color_mgmt_changed &&
9914                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9915                         dm_old_crtc_state->dsc_force_changed == false)
9916                         continue;
9917
9918                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9919                 if (ret) {
9920                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9921                         goto fail;
9922                 }
9923
9924                 if (!new_crtc_state->enable)
9925                         continue;
9926
9927                 ret = drm_atomic_add_affected_connectors(state, crtc);
9928                 if (ret) {
9929                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9930                         goto fail;
9931                 }
9932
9933                 ret = drm_atomic_add_affected_planes(state, crtc);
9934                 if (ret) {
9935                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9936                         goto fail;
9937                 }
9938
9939                 if (dm_old_crtc_state->dsc_force_changed)
9940                         new_crtc_state->mode_changed = true;
9941         }
9942
9943         /*
9944          * Add all primary and overlay planes on the CRTC to the state
9945          * whenever a plane is enabled to maintain correct z-ordering
9946          * and to enable fast surface updates.
9947          */
9948         drm_for_each_crtc(crtc, dev) {
9949                 bool modified = false;
9950
9951                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9952                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9953                                 continue;
9954
9955                         if (new_plane_state->crtc == crtc ||
9956                             old_plane_state->crtc == crtc) {
9957                                 modified = true;
9958                                 break;
9959                         }
9960                 }
9961
9962                 if (!modified)
9963                         continue;
9964
9965                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9966                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9967                                 continue;
9968
9969                         new_plane_state =
9970                                 drm_atomic_get_plane_state(state, plane);
9971
9972                         if (IS_ERR(new_plane_state)) {
9973                                 ret = PTR_ERR(new_plane_state);
9974                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9975                                 goto fail;
9976                         }
9977                 }
9978         }
9979
9980         /*
9981          * DC consults the zpos (layer_index in DC terminology) to determine the
9982          * hw plane on which to enable the hw cursor (see
9983          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9984          * atomic state, so call drm helper to normalize zpos.
9985          */
9986         ret = drm_atomic_normalize_zpos(dev, state);
9987         if (ret) {
9988                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9989                 goto fail;
9990         }
9991
9992         /* Remove exiting planes if they are modified */
9993         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9994                 ret = dm_update_plane_state(dc, state, plane,
9995                                             old_plane_state,
9996                                             new_plane_state,
9997                                             false,
9998                                             &lock_and_validation_needed,
9999                                             &is_top_most_overlay);
10000                 if (ret) {
10001                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10002                         goto fail;
10003                 }
10004         }
10005
10006         /* Disable all crtcs which require disable */
10007         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10008                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10009                                            old_crtc_state,
10010                                            new_crtc_state,
10011                                            false,
10012                                            &lock_and_validation_needed);
10013                 if (ret) {
10014                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10015                         goto fail;
10016                 }
10017         }
10018
10019         /* Enable all crtcs which require enable */
10020         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10021                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10022                                            old_crtc_state,
10023                                            new_crtc_state,
10024                                            true,
10025                                            &lock_and_validation_needed);
10026                 if (ret) {
10027                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10028                         goto fail;
10029                 }
10030         }
10031
10032         /* Add new/modified planes */
10033         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10034                 ret = dm_update_plane_state(dc, state, plane,
10035                                             old_plane_state,
10036                                             new_plane_state,
10037                                             true,
10038                                             &lock_and_validation_needed,
10039                                             &is_top_most_overlay);
10040                 if (ret) {
10041                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10042                         goto fail;
10043                 }
10044         }
10045
10046         if (dc_resource_is_dsc_encoding_supported(dc)) {
10047                 ret = pre_validate_dsc(state, &dm_state, vars);
10048                 if (ret != 0)
10049                         goto fail;
10050         }
10051
10052         /* Run this here since we want to validate the streams we created */
10053         ret = drm_atomic_helper_check_planes(dev, state);
10054         if (ret) {
10055                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10056                 goto fail;
10057         }
10058
10059         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10060                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10061                 if (dm_new_crtc_state->mpo_requested)
10062                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10063         }
10064
10065         /* Check cursor planes scaling */
10066         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10067                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10068                 if (ret) {
10069                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10070                         goto fail;
10071                 }
10072         }
10073
10074         if (state->legacy_cursor_update) {
10075                 /*
10076                  * This is a fast cursor update coming from the plane update
10077                  * helper, check if it can be done asynchronously for better
10078                  * performance.
10079                  */
10080                 state->async_update =
10081                         !drm_atomic_helper_async_check(dev, state);
10082
10083                 /*
10084                  * Skip the remaining global validation if this is an async
10085                  * update. Cursor updates can be done without affecting
10086                  * state or bandwidth calcs and this avoids the performance
10087                  * penalty of locking the private state object and
10088                  * allocating a new dc_state.
10089                  */
10090                 if (state->async_update)
10091                         return 0;
10092         }
10093
10094         /* Check scaling and underscan changes*/
10095         /* TODO Removed scaling changes validation due to inability to commit
10096          * new stream into context w\o causing full reset. Need to
10097          * decide how to handle.
10098          */
10099         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10100                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10101                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10102                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10103
10104                 /* Skip any modesets/resets */
10105                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10106                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10107                         continue;
10108
10109                 /* Skip any thing not scale or underscan changes */
10110                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10111                         continue;
10112
10113                 lock_and_validation_needed = true;
10114         }
10115
10116         /* set the slot info for each mst_state based on the link encoding format */
10117         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10118                 struct amdgpu_dm_connector *aconnector;
10119                 struct drm_connector *connector;
10120                 struct drm_connector_list_iter iter;
10121                 u8 link_coding_cap;
10122
10123                 drm_connector_list_iter_begin(dev, &iter);
10124                 drm_for_each_connector_iter(connector, &iter) {
10125                         if (connector->index == mst_state->mgr->conn_base_id) {
10126                                 aconnector = to_amdgpu_dm_connector(connector);
10127                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10128                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10129
10130                                 break;
10131                         }
10132                 }
10133                 drm_connector_list_iter_end(&iter);
10134         }
10135
10136         /**
10137          * Streams and planes are reset when there are changes that affect
10138          * bandwidth. Anything that affects bandwidth needs to go through
10139          * DC global validation to ensure that the configuration can be applied
10140          * to hardware.
10141          *
10142          * We have to currently stall out here in atomic_check for outstanding
10143          * commits to finish in this case because our IRQ handlers reference
10144          * DRM state directly - we can end up disabling interrupts too early
10145          * if we don't.
10146          *
10147          * TODO: Remove this stall and drop DM state private objects.
10148          */
10149         if (lock_and_validation_needed) {
10150                 ret = dm_atomic_get_state(state, &dm_state);
10151                 if (ret) {
10152                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10153                         goto fail;
10154                 }
10155
10156                 ret = do_aquire_global_lock(dev, state);
10157                 if (ret) {
10158                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10159                         goto fail;
10160                 }
10161
10162                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10163                 if (ret) {
10164                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10165                         goto fail;
10166                 }
10167
10168                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10169                 if (ret) {
10170                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10171                         goto fail;
10172                 }
10173
10174                 /*
10175                  * Perform validation of MST topology in the state:
10176                  * We need to perform MST atomic check before calling
10177                  * dc_validate_global_state(), or there is a chance
10178                  * to get stuck in an infinite loop and hang eventually.
10179                  */
10180                 ret = drm_dp_mst_atomic_check(state);
10181                 if (ret) {
10182                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10183                         goto fail;
10184                 }
10185                 status = dc_validate_global_state(dc, dm_state->context, true);
10186                 if (status != DC_OK) {
10187                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10188                                        dc_status_to_str(status), status);
10189                         ret = -EINVAL;
10190                         goto fail;
10191                 }
10192         } else {
10193                 /*
10194                  * The commit is a fast update. Fast updates shouldn't change
10195                  * the DC context, affect global validation, and can have their
10196                  * commit work done in parallel with other commits not touching
10197                  * the same resource. If we have a new DC context as part of
10198                  * the DM atomic state from validation we need to free it and
10199                  * retain the existing one instead.
10200                  *
10201                  * Furthermore, since the DM atomic state only contains the DC
10202                  * context and can safely be annulled, we can free the state
10203                  * and clear the associated private object now to free
10204                  * some memory and avoid a possible use-after-free later.
10205                  */
10206
10207                 for (i = 0; i < state->num_private_objs; i++) {
10208                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10209
10210                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10211                                 int j = state->num_private_objs-1;
10212
10213                                 dm_atomic_destroy_state(obj,
10214                                                 state->private_objs[i].state);
10215
10216                                 /* If i is not at the end of the array then the
10217                                  * last element needs to be moved to where i was
10218                                  * before the array can safely be truncated.
10219                                  */
10220                                 if (i != j)
10221                                         state->private_objs[i] =
10222                                                 state->private_objs[j];
10223
10224                                 state->private_objs[j].ptr = NULL;
10225                                 state->private_objs[j].state = NULL;
10226                                 state->private_objs[j].old_state = NULL;
10227                                 state->private_objs[j].new_state = NULL;
10228
10229                                 state->num_private_objs = j;
10230                                 break;
10231                         }
10232                 }
10233         }
10234
10235         /* Store the overall update type for use later in atomic check. */
10236         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10237                 struct dm_crtc_state *dm_new_crtc_state =
10238                         to_dm_crtc_state(new_crtc_state);
10239
10240                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10241                                                          UPDATE_TYPE_FULL :
10242                                                          UPDATE_TYPE_FAST;
10243         }
10244
10245         /* Must be success */
10246         WARN_ON(ret);
10247
10248         trace_amdgpu_dm_atomic_check_finish(state, ret);
10249
10250         return ret;
10251
10252 fail:
10253         if (ret == -EDEADLK)
10254                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10255         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10256                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10257         else
10258                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10259
10260         trace_amdgpu_dm_atomic_check_finish(state, ret);
10261
10262         return ret;
10263 }
10264
10265 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10266                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10267 {
10268         u8 dpcd_data;
10269         bool capable = false;
10270
10271         if (amdgpu_dm_connector->dc_link &&
10272                 dm_helpers_dp_read_dpcd(
10273                                 NULL,
10274                                 amdgpu_dm_connector->dc_link,
10275                                 DP_DOWN_STREAM_PORT_COUNT,
10276                                 &dpcd_data,
10277                                 sizeof(dpcd_data))) {
10278                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10279         }
10280
10281         return capable;
10282 }
10283
10284 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10285                 unsigned int offset,
10286                 unsigned int total_length,
10287                 u8 *data,
10288                 unsigned int length,
10289                 struct amdgpu_hdmi_vsdb_info *vsdb)
10290 {
10291         bool res;
10292         union dmub_rb_cmd cmd;
10293         struct dmub_cmd_send_edid_cea *input;
10294         struct dmub_cmd_edid_cea_output *output;
10295
10296         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10297                 return false;
10298
10299         memset(&cmd, 0, sizeof(cmd));
10300
10301         input = &cmd.edid_cea.data.input;
10302
10303         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10304         cmd.edid_cea.header.sub_type = 0;
10305         cmd.edid_cea.header.payload_bytes =
10306                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10307         input->offset = offset;
10308         input->length = length;
10309         input->cea_total_length = total_length;
10310         memcpy(input->payload, data, length);
10311
10312         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10313         if (!res) {
10314                 DRM_ERROR("EDID CEA parser failed\n");
10315                 return false;
10316         }
10317
10318         output = &cmd.edid_cea.data.output;
10319
10320         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10321                 if (!output->ack.success) {
10322                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10323                                         output->ack.offset);
10324                 }
10325         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10326                 if (!output->amd_vsdb.vsdb_found)
10327                         return false;
10328
10329                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10330                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10331                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10332                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10333         } else {
10334                 DRM_WARN("Unknown EDID CEA parser results\n");
10335                 return false;
10336         }
10337
10338         return true;
10339 }
10340
10341 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10342                 u8 *edid_ext, int len,
10343                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10344 {
10345         int i;
10346
10347         /* send extension block to DMCU for parsing */
10348         for (i = 0; i < len; i += 8) {
10349                 bool res;
10350                 int offset;
10351
10352                 /* send 8 bytes a time */
10353                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10354                         return false;
10355
10356                 if (i+8 == len) {
10357                         /* EDID block sent completed, expect result */
10358                         int version, min_rate, max_rate;
10359
10360                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10361                         if (res) {
10362                                 /* amd vsdb found */
10363                                 vsdb_info->freesync_supported = 1;
10364                                 vsdb_info->amd_vsdb_version = version;
10365                                 vsdb_info->min_refresh_rate_hz = min_rate;
10366                                 vsdb_info->max_refresh_rate_hz = max_rate;
10367                                 return true;
10368                         }
10369                         /* not amd vsdb */
10370                         return false;
10371                 }
10372
10373                 /* check for ack*/
10374                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10375                 if (!res)
10376                         return false;
10377         }
10378
10379         return false;
10380 }
10381
10382 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10383                 u8 *edid_ext, int len,
10384                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10385 {
10386         int i;
10387
10388         /* send extension block to DMCU for parsing */
10389         for (i = 0; i < len; i += 8) {
10390                 /* send 8 bytes a time */
10391                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10392                         return false;
10393         }
10394
10395         return vsdb_info->freesync_supported;
10396 }
10397
10398 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10399                 u8 *edid_ext, int len,
10400                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10401 {
10402         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10403         bool ret;
10404
10405         mutex_lock(&adev->dm.dc_lock);
10406         if (adev->dm.dmub_srv)
10407                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10408         else
10409                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10410         mutex_unlock(&adev->dm.dc_lock);
10411         return ret;
10412 }
10413
10414 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10415                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10416 {
10417         u8 *edid_ext = NULL;
10418         int i;
10419         bool valid_vsdb_found = false;
10420
10421         /*----- drm_find_cea_extension() -----*/
10422         /* No EDID or EDID extensions */
10423         if (edid == NULL || edid->extensions == 0)
10424                 return -ENODEV;
10425
10426         /* Find CEA extension */
10427         for (i = 0; i < edid->extensions; i++) {
10428                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10429                 if (edid_ext[0] == CEA_EXT)
10430                         break;
10431         }
10432
10433         if (i == edid->extensions)
10434                 return -ENODEV;
10435
10436         /*----- cea_db_offsets() -----*/
10437         if (edid_ext[0] != CEA_EXT)
10438                 return -ENODEV;
10439
10440         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10441
10442         return valid_vsdb_found ? i : -ENODEV;
10443 }
10444
10445 /**
10446  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10447  *
10448  * @connector: Connector to query.
10449  * @edid: EDID from monitor
10450  *
10451  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10452  * track of some of the display information in the internal data struct used by
10453  * amdgpu_dm. This function checks which type of connector we need to set the
10454  * FreeSync parameters.
10455  */
10456 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10457                                     struct edid *edid)
10458 {
10459         int i = 0;
10460         struct detailed_timing *timing;
10461         struct detailed_non_pixel *data;
10462         struct detailed_data_monitor_range *range;
10463         struct amdgpu_dm_connector *amdgpu_dm_connector =
10464                         to_amdgpu_dm_connector(connector);
10465         struct dm_connector_state *dm_con_state = NULL;
10466         struct dc_sink *sink;
10467
10468         struct drm_device *dev = connector->dev;
10469         struct amdgpu_device *adev = drm_to_adev(dev);
10470         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10471         bool freesync_capable = false;
10472         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10473
10474         if (!connector->state) {
10475                 DRM_ERROR("%s - Connector has no state", __func__);
10476                 goto update;
10477         }
10478
10479         sink = amdgpu_dm_connector->dc_sink ?
10480                 amdgpu_dm_connector->dc_sink :
10481                 amdgpu_dm_connector->dc_em_sink;
10482
10483         if (!edid || !sink) {
10484                 dm_con_state = to_dm_connector_state(connector->state);
10485
10486                 amdgpu_dm_connector->min_vfreq = 0;
10487                 amdgpu_dm_connector->max_vfreq = 0;
10488                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10489                 connector->display_info.monitor_range.min_vfreq = 0;
10490                 connector->display_info.monitor_range.max_vfreq = 0;
10491                 freesync_capable = false;
10492
10493                 goto update;
10494         }
10495
10496         dm_con_state = to_dm_connector_state(connector->state);
10497
10498         if (!adev->dm.freesync_module)
10499                 goto update;
10500
10501         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10502                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10503                 bool edid_check_required = false;
10504
10505                 if (edid) {
10506                         edid_check_required = is_dp_capable_without_timing_msa(
10507                                                 adev->dm.dc,
10508                                                 amdgpu_dm_connector);
10509                 }
10510
10511                 if (edid_check_required == true && (edid->version > 1 ||
10512                    (edid->version == 1 && edid->revision > 1))) {
10513                         for (i = 0; i < 4; i++) {
10514
10515                                 timing  = &edid->detailed_timings[i];
10516                                 data    = &timing->data.other_data;
10517                                 range   = &data->data.range;
10518                                 /*
10519                                  * Check if monitor has continuous frequency mode
10520                                  */
10521                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10522                                         continue;
10523                                 /*
10524                                  * Check for flag range limits only. If flag == 1 then
10525                                  * no additional timing information provided.
10526                                  * Default GTF, GTF Secondary curve and CVT are not
10527                                  * supported
10528                                  */
10529                                 if (range->flags != 1)
10530                                         continue;
10531
10532                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10533                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10534                                 amdgpu_dm_connector->pixel_clock_mhz =
10535                                         range->pixel_clock_mhz * 10;
10536
10537                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10538                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10539
10540                                 break;
10541                         }
10542
10543                         if (amdgpu_dm_connector->max_vfreq -
10544                             amdgpu_dm_connector->min_vfreq > 10) {
10545
10546                                 freesync_capable = true;
10547                         }
10548                 }
10549         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10550                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10551                 if (i >= 0 && vsdb_info.freesync_supported) {
10552                         timing  = &edid->detailed_timings[i];
10553                         data    = &timing->data.other_data;
10554
10555                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10556                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10557                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10558                                 freesync_capable = true;
10559
10560                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10561                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10562                 }
10563         }
10564
10565         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10566
10567         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10568                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10569                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10570
10571                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10572                         amdgpu_dm_connector->as_type = as_type;
10573                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10574
10575                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10576                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10577                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10578                                 freesync_capable = true;
10579
10580                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10581                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10582                 }
10583         }
10584
10585 update:
10586         if (dm_con_state)
10587                 dm_con_state->freesync_capable = freesync_capable;
10588
10589         if (connector->vrr_capable_property)
10590                 drm_connector_set_vrr_capable_property(connector,
10591                                                        freesync_capable);
10592 }
10593
10594 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10595 {
10596         struct amdgpu_device *adev = drm_to_adev(dev);
10597         struct dc *dc = adev->dm.dc;
10598         int i;
10599
10600         mutex_lock(&adev->dm.dc_lock);
10601         if (dc->current_state) {
10602                 for (i = 0; i < dc->current_state->stream_count; ++i)
10603                         dc->current_state->streams[i]
10604                                 ->triggered_crtc_reset.enabled =
10605                                 adev->dm.force_timing_sync;
10606
10607                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10608                 dc_trigger_sync(dc, dc->current_state);
10609         }
10610         mutex_unlock(&adev->dm.dc_lock);
10611 }
10612
10613 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10614                        u32 value, const char *func_name)
10615 {
10616 #ifdef DM_CHECK_ADDR_0
10617         if (address == 0) {
10618                 DC_ERR("invalid register write. address = 0");
10619                 return;
10620         }
10621 #endif
10622         cgs_write_register(ctx->cgs_device, address, value);
10623         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10624 }
10625
10626 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10627                           const char *func_name)
10628 {
10629         u32 value;
10630 #ifdef DM_CHECK_ADDR_0
10631         if (address == 0) {
10632                 DC_ERR("invalid register read; address = 0\n");
10633                 return 0;
10634         }
10635 #endif
10636
10637         if (ctx->dmub_srv &&
10638             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10639             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10640                 ASSERT(false);
10641                 return 0;
10642         }
10643
10644         value = cgs_read_register(ctx->cgs_device, address);
10645
10646         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10647
10648         return value;
10649 }
10650
10651 int amdgpu_dm_process_dmub_aux_transfer_sync(
10652                 struct dc_context *ctx,
10653                 unsigned int link_index,
10654                 struct aux_payload *payload,
10655                 enum aux_return_code_type *operation_result)
10656 {
10657         struct amdgpu_device *adev = ctx->driver_context;
10658         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10659         int ret = -1;
10660
10661         mutex_lock(&adev->dm.dpia_aux_lock);
10662         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10663                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10664                 goto out;
10665         }
10666
10667         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10668                 DRM_ERROR("wait_for_completion_timeout timeout!");
10669                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10670                 goto out;
10671         }
10672
10673         if (p_notify->result != AUX_RET_SUCCESS) {
10674                 /*
10675                  * Transient states before tunneling is enabled could
10676                  * lead to this error. We can ignore this for now.
10677                  */
10678                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10679                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10680                                         payload->address, payload->length,
10681                                         p_notify->result);
10682                 }
10683                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10684                 goto out;
10685         }
10686
10687
10688         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10689         if (!payload->write && p_notify->aux_reply.length &&
10690                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10691
10692                 if (payload->length != p_notify->aux_reply.length) {
10693                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10694                                 p_notify->aux_reply.length,
10695                                         payload->address, payload->length);
10696                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10697                         goto out;
10698                 }
10699
10700                 memcpy(payload->data, p_notify->aux_reply.data,
10701                                 p_notify->aux_reply.length);
10702         }
10703
10704         /* success */
10705         ret = p_notify->aux_reply.length;
10706         *operation_result = p_notify->result;
10707 out:
10708         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10709         mutex_unlock(&adev->dm.dpia_aux_lock);
10710         return ret;
10711 }
10712
10713 int amdgpu_dm_process_dmub_set_config_sync(
10714                 struct dc_context *ctx,
10715                 unsigned int link_index,
10716                 struct set_config_cmd_payload *payload,
10717                 enum set_config_status *operation_result)
10718 {
10719         struct amdgpu_device *adev = ctx->driver_context;
10720         bool is_cmd_complete;
10721         int ret;
10722
10723         mutex_lock(&adev->dm.dpia_aux_lock);
10724         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10725                         link_index, payload, adev->dm.dmub_notify);
10726
10727         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10728                 ret = 0;
10729                 *operation_result = adev->dm.dmub_notify->sc_status;
10730         } else {
10731                 DRM_ERROR("wait_for_completion_timeout timeout!");
10732                 ret = -1;
10733                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10734         }
10735
10736         if (!is_cmd_complete)
10737                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10738         mutex_unlock(&adev->dm.dpia_aux_lock);
10739         return ret;
10740 }
10741
10742 /*
10743  * Check whether seamless boot is supported.
10744  *
10745  * So far we only support seamless boot on CHIP_VANGOGH.
10746  * If everything goes well, we may consider expanding
10747  * seamless boot to other ASICs.
10748  */
10749 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10750 {
10751         switch (adev->ip_versions[DCE_HWIP][0]) {
10752         case IP_VERSION(3, 0, 1):
10753                 if (!adev->mman.keep_stolen_vga_memory)
10754                         return true;
10755                 break;
10756         default:
10757                 break;
10758         }
10759
10760         return false;
10761 }