2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_ucode.h"
38 #include "amdgpu_dm.h"
39 #include "amdgpu_pm.h"
41 #include "amd_shared.h"
42 #include "amdgpu_dm_irq.h"
43 #include "dm_helpers.h"
44 #include "amdgpu_dm_mst_types.h"
45 #if defined(CONFIG_DEBUG_FS)
46 #include "amdgpu_dm_debugfs.h"
49 #include "ivsrcid/ivsrcid_vislands30.h"
51 #include <linux/module.h>
52 #include <linux/moduleparam.h>
53 #include <linux/version.h>
54 #include <linux/types.h>
55 #include <linux/pm_runtime.h>
56 #include <linux/firmware.h>
59 #include <drm/drm_atomic.h>
60 #include <drm/drm_atomic_uapi.h>
61 #include <drm/drm_atomic_helper.h>
62 #include <drm/drm_dp_mst_helper.h>
63 #include <drm/drm_fb_helper.h>
64 #include <drm/drm_edid.h>
66 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67 #include "ivsrcid/irqsrcs_dcn_1_0.h"
69 #include "dcn/dcn_1_0_offset.h"
70 #include "dcn/dcn_1_0_sh_mask.h"
71 #include "soc15_hw_ip.h"
72 #include "vega10_ip_offset.h"
74 #include "soc15_common.h"
77 #include "modules/inc/mod_freesync.h"
78 #include "modules/power/power_helpers.h"
79 #include "modules/inc/mod_info_packet.h"
81 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
91 * The root control structure is &struct amdgpu_display_manager.
94 /* basic init/fini API */
95 static int amdgpu_dm_init(struct amdgpu_device *adev);
96 static void amdgpu_dm_fini(struct amdgpu_device *adev);
99 * initializes drm_device display related structures, based on the information
100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
103 * Returns 0 on success
105 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106 /* removes and deallocates the drm structures, created by the above function */
107 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
110 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
112 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
113 struct drm_plane *plane,
114 unsigned long possible_crtcs);
115 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane,
117 uint32_t link_index);
118 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
119 struct amdgpu_dm_connector *amdgpu_dm_connector,
121 struct amdgpu_encoder *amdgpu_encoder);
122 static int amdgpu_dm_encoder_init(struct drm_device *dev,
123 struct amdgpu_encoder *aencoder,
124 uint32_t link_index);
126 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
128 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state,
132 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
134 static int amdgpu_dm_atomic_check(struct drm_device *dev,
135 struct drm_atomic_state *state);
137 static void handle_cursor_update(struct drm_plane *plane,
138 struct drm_plane_state *old_plane_state);
142 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
143 DRM_PLANE_TYPE_PRIMARY,
144 DRM_PLANE_TYPE_PRIMARY,
145 DRM_PLANE_TYPE_PRIMARY,
146 DRM_PLANE_TYPE_PRIMARY,
147 DRM_PLANE_TYPE_PRIMARY,
148 DRM_PLANE_TYPE_PRIMARY,
151 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
152 DRM_PLANE_TYPE_PRIMARY,
153 DRM_PLANE_TYPE_PRIMARY,
154 DRM_PLANE_TYPE_PRIMARY,
155 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
158 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
159 DRM_PLANE_TYPE_PRIMARY,
160 DRM_PLANE_TYPE_PRIMARY,
161 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
165 * dm_vblank_get_counter
168 * Get counter for number of vertical blanks
171 * struct amdgpu_device *adev - [in] desired amdgpu device
172 * int disp_idx - [in] which CRTC to get the counter from
175 * Counter for vertical blanks
177 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
179 if (crtc >= adev->mode_info.num_crtc)
182 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
183 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
187 if (acrtc_state->stream == NULL) {
188 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
193 return dc_stream_get_vblank_counter(acrtc_state->stream);
197 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
198 u32 *vbl, u32 *position)
200 uint32_t v_blank_start, v_blank_end, h_position, v_position;
202 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
205 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
206 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
209 if (acrtc_state->stream == NULL) {
210 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
216 * TODO rework base driver to use values directly.
217 * for now parse it back into reg-format
219 dc_stream_get_scanoutpos(acrtc_state->stream,
225 *position = v_position | (h_position << 16);
226 *vbl = v_blank_start | (v_blank_end << 16);
232 static bool dm_is_idle(void *handle)
238 static int dm_wait_for_idle(void *handle)
244 static bool dm_check_soft_reset(void *handle)
249 static int dm_soft_reset(void *handle)
255 static struct amdgpu_crtc *
256 get_crtc_by_otg_inst(struct amdgpu_device *adev,
259 struct drm_device *dev = adev->ddev;
260 struct drm_crtc *crtc;
261 struct amdgpu_crtc *amdgpu_crtc;
263 if (otg_inst == -1) {
265 return adev->mode_info.crtcs[0];
268 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
269 amdgpu_crtc = to_amdgpu_crtc(crtc);
271 if (amdgpu_crtc->otg_inst == otg_inst)
278 static void dm_pflip_high_irq(void *interrupt_params)
280 struct amdgpu_crtc *amdgpu_crtc;
281 struct common_irq_params *irq_params = interrupt_params;
282 struct amdgpu_device *adev = irq_params->adev;
285 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
287 /* IRQ could occur when in initial stage */
288 /* TODO work and BO cleanup */
289 if (amdgpu_crtc == NULL) {
290 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
294 spin_lock_irqsave(&adev->ddev->event_lock, flags);
296 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
297 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
298 amdgpu_crtc->pflip_status,
299 AMDGPU_FLIP_SUBMITTED,
300 amdgpu_crtc->crtc_id,
302 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
307 /* wake up userspace */
308 if (amdgpu_crtc->event) {
309 /* Update to correct count(s) if racing with vblank irq */
310 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
312 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
314 /* page flip completed. clean up */
315 amdgpu_crtc->event = NULL;
320 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
321 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
323 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
324 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
326 drm_crtc_vblank_put(&amdgpu_crtc->base);
329 static void dm_crtc_high_irq(void *interrupt_params)
331 struct common_irq_params *irq_params = interrupt_params;
332 struct amdgpu_device *adev = irq_params->adev;
333 struct amdgpu_crtc *acrtc;
334 struct dm_crtc_state *acrtc_state;
336 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
339 drm_crtc_handle_vblank(&acrtc->base);
340 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
342 acrtc_state = to_dm_crtc_state(acrtc->base.state);
344 if (acrtc_state->stream &&
345 acrtc_state->vrr_params.supported &&
346 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
347 mod_freesync_handle_v_update(
348 adev->dm.freesync_module,
350 &acrtc_state->vrr_params);
352 dc_stream_adjust_vmin_vmax(
355 &acrtc_state->vrr_params.adjust);
360 static int dm_set_clockgating_state(void *handle,
361 enum amd_clockgating_state state)
366 static int dm_set_powergating_state(void *handle,
367 enum amd_powergating_state state)
372 /* Prototypes of private functions */
373 static int dm_early_init(void* handle);
375 /* Allocate memory for FBC compressed data */
376 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
378 struct drm_device *dev = connector->dev;
379 struct amdgpu_device *adev = dev->dev_private;
380 struct dm_comressor_info *compressor = &adev->dm.compressor;
381 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
382 struct drm_display_mode *mode;
383 unsigned long max_size = 0;
385 if (adev->dm.dc->fbc_compressor == NULL)
388 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
391 if (compressor->bo_ptr)
395 list_for_each_entry(mode, &connector->modes, head) {
396 if (max_size < mode->htotal * mode->vtotal)
397 max_size = mode->htotal * mode->vtotal;
401 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
402 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
403 &compressor->gpu_addr, &compressor->cpu_addr);
406 DRM_ERROR("DM: Failed to initialize FBC\n");
408 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
409 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
416 static int amdgpu_dm_init(struct amdgpu_device *adev)
418 struct dc_init_data init_data;
419 adev->dm.ddev = adev->ddev;
420 adev->dm.adev = adev;
422 /* Zero all the fields */
423 memset(&init_data, 0, sizeof(init_data));
425 mutex_init(&adev->dm.dc_lock);
427 if(amdgpu_dm_irq_init(adev)) {
428 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
432 init_data.asic_id.chip_family = adev->family;
434 init_data.asic_id.pci_revision_id = adev->rev_id;
435 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
437 init_data.asic_id.vram_width = adev->gmc.vram_width;
438 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
439 init_data.asic_id.atombios_base_address =
440 adev->mode_info.atom_context->bios;
442 init_data.driver = adev;
444 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
446 if (!adev->dm.cgs_device) {
447 DRM_ERROR("amdgpu: failed to create cgs device.\n");
451 init_data.cgs_device = adev->dm.cgs_device;
453 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
456 * TODO debug why this doesn't work on Raven
458 if (adev->flags & AMD_IS_APU &&
459 adev->asic_type >= CHIP_CARRIZO &&
460 adev->asic_type < CHIP_RAVEN)
461 init_data.flags.gpu_vm_support = true;
463 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
464 init_data.flags.fbc_support = true;
466 /* Display Core create. */
467 adev->dm.dc = dc_create(&init_data);
470 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
472 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
476 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
477 if (!adev->dm.freesync_module) {
479 "amdgpu: failed to initialize freesync_module.\n");
481 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
482 adev->dm.freesync_module);
484 amdgpu_dm_init_color_mod();
486 if (amdgpu_dm_initialize_drm_device(adev)) {
488 "amdgpu: failed to initialize sw for display support.\n");
492 /* Update the actual used number of crtc */
493 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
495 /* TODO: Add_display_info? */
497 /* TODO use dynamic cursor width */
498 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
499 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
501 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
503 "amdgpu: failed to initialize sw for display support.\n");
507 #if defined(CONFIG_DEBUG_FS)
508 if (dtn_debugfs_init(adev))
509 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
512 DRM_DEBUG_DRIVER("KMS initialized.\n");
516 amdgpu_dm_fini(adev);
521 static void amdgpu_dm_fini(struct amdgpu_device *adev)
523 amdgpu_dm_destroy_drm_device(&adev->dm);
525 * TODO: pageflip, vlank interrupt
527 * amdgpu_dm_irq_fini(adev);
530 if (adev->dm.cgs_device) {
531 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
532 adev->dm.cgs_device = NULL;
534 if (adev->dm.freesync_module) {
535 mod_freesync_destroy(adev->dm.freesync_module);
536 adev->dm.freesync_module = NULL;
538 /* DC Destroy TODO: Replace destroy DAL */
540 dc_destroy(&adev->dm.dc);
542 mutex_destroy(&adev->dm.dc_lock);
547 static int load_dmcu_fw(struct amdgpu_device *adev)
549 const char *fw_name_dmcu;
551 const struct dmcu_firmware_header_v1_0 *hdr;
553 switch(adev->asic_type) {
572 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
575 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
579 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
580 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
584 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
586 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
587 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
588 adev->dm.fw_dmcu = NULL;
592 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
597 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
599 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
601 release_firmware(adev->dm.fw_dmcu);
602 adev->dm.fw_dmcu = NULL;
606 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
607 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
608 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
609 adev->firmware.fw_size +=
610 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
612 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
613 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
614 adev->firmware.fw_size +=
615 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
617 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
619 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
624 static int dm_sw_init(void *handle)
626 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
628 return load_dmcu_fw(adev);
631 static int dm_sw_fini(void *handle)
633 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
635 if(adev->dm.fw_dmcu) {
636 release_firmware(adev->dm.fw_dmcu);
637 adev->dm.fw_dmcu = NULL;
643 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
645 struct amdgpu_dm_connector *aconnector;
646 struct drm_connector *connector;
649 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
652 aconnector = to_amdgpu_dm_connector(connector);
653 if (aconnector->dc_link->type == dc_connection_mst_branch &&
654 aconnector->mst_mgr.aux) {
655 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
656 aconnector, aconnector->base.base.id);
658 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
660 DRM_ERROR("DM_MST: Failed to start MST\n");
661 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
667 drm_modeset_unlock(&dev->mode_config.connection_mutex);
671 static int dm_late_init(void *handle)
673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
675 struct dmcu_iram_parameters params;
676 unsigned int linear_lut[16];
678 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
681 for (i = 0; i < 16; i++)
682 linear_lut[i] = 0xFFFF * i / 15;
685 params.backlight_ramping_start = 0xCCCC;
686 params.backlight_ramping_reduction = 0xCCCCCCCC;
687 params.backlight_lut_array_size = 16;
688 params.backlight_lut_array = linear_lut;
690 ret = dmcu_load_iram(dmcu, params);
695 return detect_mst_link_for_all_connectors(adev->ddev);
698 static void s3_handle_mst(struct drm_device *dev, bool suspend)
700 struct amdgpu_dm_connector *aconnector;
701 struct drm_connector *connector;
703 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
705 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
706 aconnector = to_amdgpu_dm_connector(connector);
707 if (aconnector->dc_link->type == dc_connection_mst_branch &&
708 !aconnector->mst_port) {
711 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
713 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
717 drm_modeset_unlock(&dev->mode_config.connection_mutex);
721 * dm_hw_init() - Initialize DC device
722 * @handle: The base driver device containing the amdpgu_dm device.
724 * Initialize the &struct amdgpu_display_manager device. This involves calling
725 * the initializers of each DM component, then populating the struct with them.
727 * Although the function implies hardware initialization, both hardware and
728 * software are initialized here. Splitting them out to their relevant init
729 * hooks is a future TODO item.
731 * Some notable things that are initialized here:
733 * - Display Core, both software and hardware
734 * - DC modules that we need (freesync and color management)
735 * - DRM software states
736 * - Interrupt sources and handlers
738 * - Debug FS entries, if enabled
740 static int dm_hw_init(void *handle)
742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743 /* Create DAL display manager */
744 amdgpu_dm_init(adev);
745 amdgpu_dm_hpd_init(adev);
751 * dm_hw_fini() - Teardown DC device
752 * @handle: The base driver device containing the amdpgu_dm device.
754 * Teardown components within &struct amdgpu_display_manager that require
755 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
756 * were loaded. Also flush IRQ workqueues and disable them.
758 static int dm_hw_fini(void *handle)
760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
762 amdgpu_dm_hpd_fini(adev);
764 amdgpu_dm_irq_fini(adev);
765 amdgpu_dm_fini(adev);
769 static int dm_suspend(void *handle)
771 struct amdgpu_device *adev = handle;
772 struct amdgpu_display_manager *dm = &adev->dm;
775 s3_handle_mst(adev->ddev, true);
777 amdgpu_dm_irq_suspend(adev);
779 WARN_ON(adev->dm.cached_state);
780 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
782 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
787 static struct amdgpu_dm_connector *
788 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
789 struct drm_crtc *crtc)
792 struct drm_connector_state *new_con_state;
793 struct drm_connector *connector;
794 struct drm_crtc *crtc_from_state;
796 for_each_new_connector_in_state(state, connector, new_con_state, i) {
797 crtc_from_state = new_con_state->crtc;
799 if (crtc_from_state == crtc)
800 return to_amdgpu_dm_connector(connector);
806 static void emulated_link_detect(struct dc_link *link)
808 struct dc_sink_init_data sink_init_data = { 0 };
809 struct display_sink_capability sink_caps = { 0 };
810 enum dc_edid_status edid_status;
811 struct dc_context *dc_ctx = link->ctx;
812 struct dc_sink *sink = NULL;
813 struct dc_sink *prev_sink = NULL;
815 link->type = dc_connection_none;
816 prev_sink = link->local_sink;
818 if (prev_sink != NULL)
819 dc_sink_retain(prev_sink);
821 switch (link->connector_signal) {
822 case SIGNAL_TYPE_HDMI_TYPE_A: {
823 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
824 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
828 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
829 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
830 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
834 case SIGNAL_TYPE_DVI_DUAL_LINK: {
835 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
836 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
840 case SIGNAL_TYPE_LVDS: {
841 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
842 sink_caps.signal = SIGNAL_TYPE_LVDS;
846 case SIGNAL_TYPE_EDP: {
847 sink_caps.transaction_type =
848 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
849 sink_caps.signal = SIGNAL_TYPE_EDP;
853 case SIGNAL_TYPE_DISPLAY_PORT: {
854 sink_caps.transaction_type =
855 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
856 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
861 DC_ERROR("Invalid connector type! signal:%d\n",
862 link->connector_signal);
866 sink_init_data.link = link;
867 sink_init_data.sink_signal = sink_caps.signal;
869 sink = dc_sink_create(&sink_init_data);
871 DC_ERROR("Failed to create sink!\n");
875 link->local_sink = sink;
877 edid_status = dm_helpers_read_local_edid(
882 if (edid_status != EDID_OK)
883 DC_ERROR("Failed to read EDID");
887 static int dm_resume(void *handle)
889 struct amdgpu_device *adev = handle;
890 struct drm_device *ddev = adev->ddev;
891 struct amdgpu_display_manager *dm = &adev->dm;
892 struct amdgpu_dm_connector *aconnector;
893 struct drm_connector *connector;
894 struct drm_crtc *crtc;
895 struct drm_crtc_state *new_crtc_state;
896 struct dm_crtc_state *dm_new_crtc_state;
897 struct drm_plane *plane;
898 struct drm_plane_state *new_plane_state;
899 struct dm_plane_state *dm_new_plane_state;
900 enum dc_connection_type new_connection_type = dc_connection_none;
904 /* power on hardware */
905 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
907 /* program HPD filter */
910 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
911 s3_handle_mst(ddev, false);
914 * early enable HPD Rx IRQ, should be done before set mode as short
915 * pulse interrupts are used for MST
917 amdgpu_dm_irq_resume_early(adev);
920 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
921 aconnector = to_amdgpu_dm_connector(connector);
924 * this is the case when traversing through already created
925 * MST connectors, should be skipped
927 if (aconnector->mst_port)
930 mutex_lock(&aconnector->hpd_lock);
931 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
932 DRM_ERROR("KMS: Failed to detect connector\n");
934 if (aconnector->base.force && new_connection_type == dc_connection_none)
935 emulated_link_detect(aconnector->dc_link);
937 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
939 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
940 aconnector->fake_enable = false;
942 aconnector->dc_sink = NULL;
943 amdgpu_dm_update_connector_after_detect(aconnector);
944 mutex_unlock(&aconnector->hpd_lock);
947 /* Force mode set in atomic commit */
948 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
949 new_crtc_state->active_changed = true;
952 * atomic_check is expected to create the dc states. We need to release
953 * them here, since they were duplicated as part of the suspend
956 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
957 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
958 if (dm_new_crtc_state->stream) {
959 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
960 dc_stream_release(dm_new_crtc_state->stream);
961 dm_new_crtc_state->stream = NULL;
965 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
966 dm_new_plane_state = to_dm_plane_state(new_plane_state);
967 if (dm_new_plane_state->dc_state) {
968 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
969 dc_plane_state_release(dm_new_plane_state->dc_state);
970 dm_new_plane_state->dc_state = NULL;
974 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
976 dm->cached_state = NULL;
978 amdgpu_dm_irq_resume_late(adev);
986 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
987 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
988 * the base driver's device list to be initialized and torn down accordingly.
990 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
993 static const struct amd_ip_funcs amdgpu_dm_funcs = {
995 .early_init = dm_early_init,
996 .late_init = dm_late_init,
997 .sw_init = dm_sw_init,
998 .sw_fini = dm_sw_fini,
999 .hw_init = dm_hw_init,
1000 .hw_fini = dm_hw_fini,
1001 .suspend = dm_suspend,
1002 .resume = dm_resume,
1003 .is_idle = dm_is_idle,
1004 .wait_for_idle = dm_wait_for_idle,
1005 .check_soft_reset = dm_check_soft_reset,
1006 .soft_reset = dm_soft_reset,
1007 .set_clockgating_state = dm_set_clockgating_state,
1008 .set_powergating_state = dm_set_powergating_state,
1011 const struct amdgpu_ip_block_version dm_ip_block =
1013 .type = AMD_IP_BLOCK_TYPE_DCE,
1017 .funcs = &amdgpu_dm_funcs,
1027 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1028 .fb_create = amdgpu_display_user_framebuffer_create,
1029 .output_poll_changed = drm_fb_helper_output_poll_changed,
1030 .atomic_check = amdgpu_dm_atomic_check,
1031 .atomic_commit = amdgpu_dm_atomic_commit,
1034 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1035 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1039 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1041 struct drm_connector *connector = &aconnector->base;
1042 struct drm_device *dev = connector->dev;
1043 struct dc_sink *sink;
1045 /* MST handled by drm_mst framework */
1046 if (aconnector->mst_mgr.mst_state == true)
1050 sink = aconnector->dc_link->local_sink;
1053 * Edid mgmt connector gets first update only in mode_valid hook and then
1054 * the connector sink is set to either fake or physical sink depends on link status.
1055 * Skip if already done during boot.
1057 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1058 && aconnector->dc_em_sink) {
1061 * For S3 resume with headless use eml_sink to fake stream
1062 * because on resume connector->sink is set to NULL
1064 mutex_lock(&dev->mode_config.mutex);
1067 if (aconnector->dc_sink) {
1068 amdgpu_dm_update_freesync_caps(connector, NULL);
1070 * retain and release below are used to
1071 * bump up refcount for sink because the link doesn't point
1072 * to it anymore after disconnect, so on next crtc to connector
1073 * reshuffle by UMD we will get into unwanted dc_sink release
1075 if (aconnector->dc_sink != aconnector->dc_em_sink)
1076 dc_sink_release(aconnector->dc_sink);
1078 aconnector->dc_sink = sink;
1079 amdgpu_dm_update_freesync_caps(connector,
1082 amdgpu_dm_update_freesync_caps(connector, NULL);
1083 if (!aconnector->dc_sink)
1084 aconnector->dc_sink = aconnector->dc_em_sink;
1085 else if (aconnector->dc_sink != aconnector->dc_em_sink)
1086 dc_sink_retain(aconnector->dc_sink);
1089 mutex_unlock(&dev->mode_config.mutex);
1094 * TODO: temporary guard to look for proper fix
1095 * if this sink is MST sink, we should not do anything
1097 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
1100 if (aconnector->dc_sink == sink) {
1102 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1105 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1106 aconnector->connector_id);
1110 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1111 aconnector->connector_id, aconnector->dc_sink, sink);
1113 mutex_lock(&dev->mode_config.mutex);
1116 * 1. Update status of the drm connector
1117 * 2. Send an event and let userspace tell us what to do
1121 * TODO: check if we still need the S3 mode update workaround.
1122 * If yes, put it here.
1124 if (aconnector->dc_sink)
1125 amdgpu_dm_update_freesync_caps(connector, NULL);
1127 aconnector->dc_sink = sink;
1128 if (sink->dc_edid.length == 0) {
1129 aconnector->edid = NULL;
1130 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1133 (struct edid *) sink->dc_edid.raw_edid;
1136 drm_connector_update_edid_property(connector,
1138 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1141 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1144 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1145 amdgpu_dm_update_freesync_caps(connector, NULL);
1146 drm_connector_update_edid_property(connector, NULL);
1147 aconnector->num_modes = 0;
1148 aconnector->dc_sink = NULL;
1149 aconnector->edid = NULL;
1152 mutex_unlock(&dev->mode_config.mutex);
1155 static void handle_hpd_irq(void *param)
1157 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1158 struct drm_connector *connector = &aconnector->base;
1159 struct drm_device *dev = connector->dev;
1160 enum dc_connection_type new_connection_type = dc_connection_none;
1163 * In case of failure or MST no need to update connector status or notify the OS
1164 * since (for MST case) MST does this in its own context.
1166 mutex_lock(&aconnector->hpd_lock);
1168 if (aconnector->fake_enable)
1169 aconnector->fake_enable = false;
1171 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1172 DRM_ERROR("KMS: Failed to detect connector\n");
1174 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1175 emulated_link_detect(aconnector->dc_link);
1178 drm_modeset_lock_all(dev);
1179 dm_restore_drm_connector_state(dev, connector);
1180 drm_modeset_unlock_all(dev);
1182 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1183 drm_kms_helper_hotplug_event(dev);
1185 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1186 amdgpu_dm_update_connector_after_detect(aconnector);
1189 drm_modeset_lock_all(dev);
1190 dm_restore_drm_connector_state(dev, connector);
1191 drm_modeset_unlock_all(dev);
1193 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1194 drm_kms_helper_hotplug_event(dev);
1196 mutex_unlock(&aconnector->hpd_lock);
1200 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1202 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1204 bool new_irq_handled = false;
1206 int dpcd_bytes_to_read;
1208 const int max_process_count = 30;
1209 int process_count = 0;
1211 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1213 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1214 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1215 /* DPCD 0x200 - 0x201 for downstream IRQ */
1216 dpcd_addr = DP_SINK_COUNT;
1218 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1219 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1220 dpcd_addr = DP_SINK_COUNT_ESI;
1223 dret = drm_dp_dpcd_read(
1224 &aconnector->dm_dp_aux.aux,
1227 dpcd_bytes_to_read);
1229 while (dret == dpcd_bytes_to_read &&
1230 process_count < max_process_count) {
1236 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1237 /* handle HPD short pulse irq */
1238 if (aconnector->mst_mgr.mst_state)
1240 &aconnector->mst_mgr,
1244 if (new_irq_handled) {
1245 /* ACK at DPCD to notify down stream */
1246 const int ack_dpcd_bytes_to_write =
1247 dpcd_bytes_to_read - 1;
1249 for (retry = 0; retry < 3; retry++) {
1252 wret = drm_dp_dpcd_write(
1253 &aconnector->dm_dp_aux.aux,
1256 ack_dpcd_bytes_to_write);
1257 if (wret == ack_dpcd_bytes_to_write)
1261 /* check if there is new irq to be handled */
1262 dret = drm_dp_dpcd_read(
1263 &aconnector->dm_dp_aux.aux,
1266 dpcd_bytes_to_read);
1268 new_irq_handled = false;
1274 if (process_count == max_process_count)
1275 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1278 static void handle_hpd_rx_irq(void *param)
1280 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1281 struct drm_connector *connector = &aconnector->base;
1282 struct drm_device *dev = connector->dev;
1283 struct dc_link *dc_link = aconnector->dc_link;
1284 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1285 enum dc_connection_type new_connection_type = dc_connection_none;
1288 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1289 * conflict, after implement i2c helper, this mutex should be
1292 if (dc_link->type != dc_connection_mst_branch)
1293 mutex_lock(&aconnector->hpd_lock);
1295 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1296 !is_mst_root_connector) {
1297 /* Downstream Port status changed. */
1298 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1299 DRM_ERROR("KMS: Failed to detect connector\n");
1301 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1302 emulated_link_detect(dc_link);
1304 if (aconnector->fake_enable)
1305 aconnector->fake_enable = false;
1307 amdgpu_dm_update_connector_after_detect(aconnector);
1310 drm_modeset_lock_all(dev);
1311 dm_restore_drm_connector_state(dev, connector);
1312 drm_modeset_unlock_all(dev);
1314 drm_kms_helper_hotplug_event(dev);
1315 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1317 if (aconnector->fake_enable)
1318 aconnector->fake_enable = false;
1320 amdgpu_dm_update_connector_after_detect(aconnector);
1323 drm_modeset_lock_all(dev);
1324 dm_restore_drm_connector_state(dev, connector);
1325 drm_modeset_unlock_all(dev);
1327 drm_kms_helper_hotplug_event(dev);
1330 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1331 (dc_link->type == dc_connection_mst_branch))
1332 dm_handle_hpd_rx_irq(aconnector);
1334 if (dc_link->type != dc_connection_mst_branch) {
1335 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1336 mutex_unlock(&aconnector->hpd_lock);
1340 static void register_hpd_handlers(struct amdgpu_device *adev)
1342 struct drm_device *dev = adev->ddev;
1343 struct drm_connector *connector;
1344 struct amdgpu_dm_connector *aconnector;
1345 const struct dc_link *dc_link;
1346 struct dc_interrupt_params int_params = {0};
1348 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1349 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1351 list_for_each_entry(connector,
1352 &dev->mode_config.connector_list, head) {
1354 aconnector = to_amdgpu_dm_connector(connector);
1355 dc_link = aconnector->dc_link;
1357 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1358 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1359 int_params.irq_source = dc_link->irq_source_hpd;
1361 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1363 (void *) aconnector);
1366 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1368 /* Also register for DP short pulse (hpd_rx). */
1369 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1370 int_params.irq_source = dc_link->irq_source_hpd_rx;
1372 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1374 (void *) aconnector);
1379 /* Register IRQ sources and initialize IRQ callbacks */
1380 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1382 struct dc *dc = adev->dm.dc;
1383 struct common_irq_params *c_irq_params;
1384 struct dc_interrupt_params int_params = {0};
1387 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1389 if (adev->asic_type == CHIP_VEGA10 ||
1390 adev->asic_type == CHIP_VEGA12 ||
1391 adev->asic_type == CHIP_VEGA20 ||
1392 adev->asic_type == CHIP_RAVEN)
1393 client_id = SOC15_IH_CLIENTID_DCE;
1395 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1396 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1399 * Actions of amdgpu_irq_add_id():
1400 * 1. Register a set() function with base driver.
1401 * Base driver will call set() function to enable/disable an
1402 * interrupt in DC hardware.
1403 * 2. Register amdgpu_dm_irq_handler().
1404 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1405 * coming from DC hardware.
1406 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1407 * for acknowledging and handling. */
1409 /* Use VBLANK interrupt */
1410 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1411 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1413 DRM_ERROR("Failed to add crtc irq id!\n");
1417 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1418 int_params.irq_source =
1419 dc_interrupt_to_irq_source(dc, i, 0);
1421 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1423 c_irq_params->adev = adev;
1424 c_irq_params->irq_src = int_params.irq_source;
1426 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1427 dm_crtc_high_irq, c_irq_params);
1430 /* Use GRPH_PFLIP interrupt */
1431 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1432 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1433 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1435 DRM_ERROR("Failed to add page flip irq id!\n");
1439 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1440 int_params.irq_source =
1441 dc_interrupt_to_irq_source(dc, i, 0);
1443 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1445 c_irq_params->adev = adev;
1446 c_irq_params->irq_src = int_params.irq_source;
1448 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1449 dm_pflip_high_irq, c_irq_params);
1454 r = amdgpu_irq_add_id(adev, client_id,
1455 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1457 DRM_ERROR("Failed to add hpd irq id!\n");
1461 register_hpd_handlers(adev);
1466 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1467 /* Register IRQ sources and initialize IRQ callbacks */
1468 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1470 struct dc *dc = adev->dm.dc;
1471 struct common_irq_params *c_irq_params;
1472 struct dc_interrupt_params int_params = {0};
1476 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1477 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1480 * Actions of amdgpu_irq_add_id():
1481 * 1. Register a set() function with base driver.
1482 * Base driver will call set() function to enable/disable an
1483 * interrupt in DC hardware.
1484 * 2. Register amdgpu_dm_irq_handler().
1485 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1486 * coming from DC hardware.
1487 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1488 * for acknowledging and handling.
1491 /* Use VSTARTUP interrupt */
1492 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1493 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1495 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1498 DRM_ERROR("Failed to add crtc irq id!\n");
1502 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1503 int_params.irq_source =
1504 dc_interrupt_to_irq_source(dc, i, 0);
1506 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1508 c_irq_params->adev = adev;
1509 c_irq_params->irq_src = int_params.irq_source;
1511 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1512 dm_crtc_high_irq, c_irq_params);
1515 /* Use GRPH_PFLIP interrupt */
1516 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1517 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1519 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1521 DRM_ERROR("Failed to add page flip irq id!\n");
1525 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1526 int_params.irq_source =
1527 dc_interrupt_to_irq_source(dc, i, 0);
1529 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1531 c_irq_params->adev = adev;
1532 c_irq_params->irq_src = int_params.irq_source;
1534 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1535 dm_pflip_high_irq, c_irq_params);
1540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1543 DRM_ERROR("Failed to add hpd irq id!\n");
1547 register_hpd_handlers(adev);
1554 * Acquires the lock for the atomic state object and returns
1555 * the new atomic state.
1557 * This should only be called during atomic check.
1559 static int dm_atomic_get_state(struct drm_atomic_state *state,
1560 struct dm_atomic_state **dm_state)
1562 struct drm_device *dev = state->dev;
1563 struct amdgpu_device *adev = dev->dev_private;
1564 struct amdgpu_display_manager *dm = &adev->dm;
1565 struct drm_private_state *priv_state;
1571 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1575 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1576 if (IS_ERR(priv_state))
1577 return PTR_ERR(priv_state);
1579 *dm_state = to_dm_atomic_state(priv_state);
1584 struct dm_atomic_state *
1585 dm_atomic_get_new_state(struct drm_atomic_state *state)
1587 struct drm_device *dev = state->dev;
1588 struct amdgpu_device *adev = dev->dev_private;
1589 struct amdgpu_display_manager *dm = &adev->dm;
1590 struct drm_private_obj *obj;
1591 struct drm_private_state *new_obj_state;
1594 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1595 if (obj->funcs == dm->atomic_obj.funcs)
1596 return to_dm_atomic_state(new_obj_state);
1602 struct dm_atomic_state *
1603 dm_atomic_get_old_state(struct drm_atomic_state *state)
1605 struct drm_device *dev = state->dev;
1606 struct amdgpu_device *adev = dev->dev_private;
1607 struct amdgpu_display_manager *dm = &adev->dm;
1608 struct drm_private_obj *obj;
1609 struct drm_private_state *old_obj_state;
1612 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1613 if (obj->funcs == dm->atomic_obj.funcs)
1614 return to_dm_atomic_state(old_obj_state);
1620 static struct drm_private_state *
1621 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1623 struct dm_atomic_state *old_state, *new_state;
1625 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1629 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1631 new_state->context = dc_create_state();
1632 if (!new_state->context) {
1637 old_state = to_dm_atomic_state(obj->state);
1638 if (old_state && old_state->context)
1639 dc_resource_state_copy_construct(old_state->context,
1640 new_state->context);
1642 return &new_state->base;
1645 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1646 struct drm_private_state *state)
1648 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1650 if (dm_state && dm_state->context)
1651 dc_release_state(dm_state->context);
1656 static struct drm_private_state_funcs dm_atomic_state_funcs = {
1657 .atomic_duplicate_state = dm_atomic_duplicate_state,
1658 .atomic_destroy_state = dm_atomic_destroy_state,
1661 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1663 struct dm_atomic_state *state;
1666 adev->mode_info.mode_config_initialized = true;
1668 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1669 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1671 adev->ddev->mode_config.max_width = 16384;
1672 adev->ddev->mode_config.max_height = 16384;
1674 adev->ddev->mode_config.preferred_depth = 24;
1675 adev->ddev->mode_config.prefer_shadow = 1;
1676 /* indicates support for immediate flip */
1677 adev->ddev->mode_config.async_page_flip = true;
1679 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1681 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1683 state = kzalloc(sizeof(*state), GFP_KERNEL);
1687 state->context = dc_create_state();
1688 if (!state->context) {
1693 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1695 drm_atomic_private_obj_init(&adev->dm.atomic_obj,
1697 &dm_atomic_state_funcs);
1699 r = amdgpu_display_modeset_create_props(adev);
1706 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1707 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1709 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1710 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1712 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1714 #if defined(CONFIG_ACPI)
1715 struct amdgpu_dm_backlight_caps caps;
1717 if (dm->backlight_caps.caps_valid)
1720 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1721 if (caps.caps_valid) {
1722 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1723 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1724 dm->backlight_caps.caps_valid = true;
1726 dm->backlight_caps.min_input_signal =
1727 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1728 dm->backlight_caps.max_input_signal =
1729 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1732 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1733 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1737 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1739 struct amdgpu_display_manager *dm = bl_get_data(bd);
1740 struct amdgpu_dm_backlight_caps caps;
1741 uint32_t brightness = bd->props.brightness;
1743 amdgpu_dm_update_backlight_caps(dm);
1744 caps = dm->backlight_caps;
1746 * The brightness input is in the range 0-255
1747 * It needs to be rescaled to be between the
1748 * requested min and max input signal
1750 * It also needs to be scaled up by 0x101 to
1751 * match the DC interface which has a range of
1757 * (caps.max_input_signal - caps.min_input_signal)
1758 / AMDGPU_MAX_BL_LEVEL
1759 + caps.min_input_signal * 0x101;
1761 if (dc_link_set_backlight_level(dm->backlight_link,
1768 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1770 struct amdgpu_display_manager *dm = bl_get_data(bd);
1771 int ret = dc_link_get_backlight_level(dm->backlight_link);
1773 if (ret == DC_ERROR_UNEXPECTED)
1774 return bd->props.brightness;
1778 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1779 .get_brightness = amdgpu_dm_backlight_get_brightness,
1780 .update_status = amdgpu_dm_backlight_update_status,
1784 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1787 struct backlight_properties props = { 0 };
1789 amdgpu_dm_update_backlight_caps(dm);
1791 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1792 props.brightness = AMDGPU_MAX_BL_LEVEL;
1793 props.type = BACKLIGHT_RAW;
1795 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1796 dm->adev->ddev->primary->index);
1798 dm->backlight_dev = backlight_device_register(bl_name,
1799 dm->adev->ddev->dev,
1801 &amdgpu_dm_backlight_ops,
1804 if (IS_ERR(dm->backlight_dev))
1805 DRM_ERROR("DM: Backlight registration failed!\n");
1807 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1812 static int initialize_plane(struct amdgpu_display_manager *dm,
1813 struct amdgpu_mode_info *mode_info,
1816 struct drm_plane *plane;
1817 unsigned long possible_crtcs;
1820 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
1821 mode_info->planes[plane_id] = plane;
1824 DRM_ERROR("KMS: Failed to allocate plane\n");
1827 plane->type = mode_info->plane_type[plane_id];
1830 * HACK: IGT tests expect that each plane can only have
1831 * one possible CRTC. For now, set one CRTC for each
1832 * plane that is not an underlay, but still allow multiple
1833 * CRTCs for underlay planes.
1835 possible_crtcs = 1 << plane_id;
1836 if (plane_id >= dm->dc->caps.max_streams)
1837 possible_crtcs = 0xff;
1839 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1842 DRM_ERROR("KMS: Failed to initialize plane\n");
1850 static void register_backlight_device(struct amdgpu_display_manager *dm,
1851 struct dc_link *link)
1853 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1854 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1856 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1857 link->type != dc_connection_none) {
1859 * Event if registration failed, we should continue with
1860 * DM initialization because not having a backlight control
1861 * is better then a black screen.
1863 amdgpu_dm_register_backlight_device(dm);
1865 if (dm->backlight_dev)
1866 dm->backlight_link = link;
1873 * In this architecture, the association
1874 * connector -> encoder -> crtc
1875 * id not really requried. The crtc and connector will hold the
1876 * display_index as an abstraction to use with DAL component
1878 * Returns 0 on success
1880 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1882 struct amdgpu_display_manager *dm = &adev->dm;
1884 struct amdgpu_dm_connector *aconnector = NULL;
1885 struct amdgpu_encoder *aencoder = NULL;
1886 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1888 int32_t total_overlay_planes, total_primary_planes;
1889 enum dc_connection_type new_connection_type = dc_connection_none;
1891 link_cnt = dm->dc->caps.max_links;
1892 if (amdgpu_dm_mode_config_init(dm->adev)) {
1893 DRM_ERROR("DM: Failed to initialize mode config\n");
1897 /* Identify the number of planes to be initialized */
1898 total_overlay_planes = dm->dc->caps.max_slave_planes;
1899 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1901 /* First initialize overlay planes, index starting after primary planes */
1902 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1903 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1904 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1909 /* Initialize primary planes */
1910 for (i = (total_primary_planes - 1); i >= 0; i--) {
1911 if (initialize_plane(dm, mode_info, i)) {
1912 DRM_ERROR("KMS: Failed to initialize primary plane\n");
1917 for (i = 0; i < dm->dc->caps.max_streams; i++)
1918 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
1919 DRM_ERROR("KMS: Failed to initialize crtc\n");
1923 dm->display_indexes_num = dm->dc->caps.max_streams;
1925 /* loops over all connectors on the board */
1926 for (i = 0; i < link_cnt; i++) {
1927 struct dc_link *link = NULL;
1929 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1931 "KMS: Cannot support more than %d display indexes\n",
1932 AMDGPU_DM_MAX_DISPLAY_INDEX);
1936 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1940 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1944 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1945 DRM_ERROR("KMS: Failed to initialize encoder\n");
1949 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1950 DRM_ERROR("KMS: Failed to initialize connector\n");
1954 link = dc_get_link_at_index(dm->dc, i);
1956 if (!dc_link_detect_sink(link, &new_connection_type))
1957 DRM_ERROR("KMS: Failed to detect connector\n");
1959 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1960 emulated_link_detect(link);
1961 amdgpu_dm_update_connector_after_detect(aconnector);
1963 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1964 amdgpu_dm_update_connector_after_detect(aconnector);
1965 register_backlight_device(dm, link);
1971 /* Software is initialized. Now we can register interrupt handlers. */
1972 switch (adev->asic_type) {
1982 case CHIP_POLARIS11:
1983 case CHIP_POLARIS10:
1984 case CHIP_POLARIS12:
1989 if (dce110_register_irq_handlers(dm->adev)) {
1990 DRM_ERROR("DM: Failed to initialize IRQ\n");
1994 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1996 if (dcn10_register_irq_handlers(dm->adev)) {
1997 DRM_ERROR("DM: Failed to initialize IRQ\n");
2003 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2007 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2008 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2014 for (i = 0; i < dm->dc->caps.max_planes; i++)
2015 kfree(mode_info->planes[i]);
2019 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2021 drm_mode_config_cleanup(dm->ddev);
2022 drm_atomic_private_obj_fini(&dm->atomic_obj);
2026 /******************************************************************************
2027 * amdgpu_display_funcs functions
2028 *****************************************************************************/
2031 * dm_bandwidth_update - program display watermarks
2033 * @adev: amdgpu_device pointer
2035 * Calculate and program the display watermarks and line buffer allocation.
2037 static void dm_bandwidth_update(struct amdgpu_device *adev)
2039 /* TODO: implement later */
2042 static const struct amdgpu_display_funcs dm_display_funcs = {
2043 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2044 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2045 .backlight_set_level = NULL, /* never called for DC */
2046 .backlight_get_level = NULL, /* never called for DC */
2047 .hpd_sense = NULL,/* called unconditionally */
2048 .hpd_set_polarity = NULL, /* called unconditionally */
2049 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2050 .page_flip_get_scanoutpos =
2051 dm_crtc_get_scanoutpos,/* called unconditionally */
2052 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2053 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2056 #if defined(CONFIG_DEBUG_KERNEL_DC)
2058 static ssize_t s3_debug_store(struct device *device,
2059 struct device_attribute *attr,
2065 struct pci_dev *pdev = to_pci_dev(device);
2066 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2067 struct amdgpu_device *adev = drm_dev->dev_private;
2069 ret = kstrtoint(buf, 0, &s3_state);
2074 drm_kms_helper_hotplug_event(adev->ddev);
2079 return ret == 0 ? count : 0;
2082 DEVICE_ATTR_WO(s3_debug);
2086 static int dm_early_init(void *handle)
2088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2090 switch (adev->asic_type) {
2093 adev->mode_info.num_crtc = 6;
2094 adev->mode_info.num_hpd = 6;
2095 adev->mode_info.num_dig = 6;
2096 adev->mode_info.plane_type = dm_plane_type_default;
2099 adev->mode_info.num_crtc = 4;
2100 adev->mode_info.num_hpd = 6;
2101 adev->mode_info.num_dig = 7;
2102 adev->mode_info.plane_type = dm_plane_type_default;
2106 adev->mode_info.num_crtc = 2;
2107 adev->mode_info.num_hpd = 6;
2108 adev->mode_info.num_dig = 6;
2109 adev->mode_info.plane_type = dm_plane_type_default;
2113 adev->mode_info.num_crtc = 6;
2114 adev->mode_info.num_hpd = 6;
2115 adev->mode_info.num_dig = 7;
2116 adev->mode_info.plane_type = dm_plane_type_default;
2119 adev->mode_info.num_crtc = 3;
2120 adev->mode_info.num_hpd = 6;
2121 adev->mode_info.num_dig = 9;
2122 adev->mode_info.plane_type = dm_plane_type_carizzo;
2125 adev->mode_info.num_crtc = 2;
2126 adev->mode_info.num_hpd = 6;
2127 adev->mode_info.num_dig = 9;
2128 adev->mode_info.plane_type = dm_plane_type_stoney;
2130 case CHIP_POLARIS11:
2131 case CHIP_POLARIS12:
2132 adev->mode_info.num_crtc = 5;
2133 adev->mode_info.num_hpd = 5;
2134 adev->mode_info.num_dig = 5;
2135 adev->mode_info.plane_type = dm_plane_type_default;
2137 case CHIP_POLARIS10:
2139 adev->mode_info.num_crtc = 6;
2140 adev->mode_info.num_hpd = 6;
2141 adev->mode_info.num_dig = 6;
2142 adev->mode_info.plane_type = dm_plane_type_default;
2147 adev->mode_info.num_crtc = 6;
2148 adev->mode_info.num_hpd = 6;
2149 adev->mode_info.num_dig = 6;
2150 adev->mode_info.plane_type = dm_plane_type_default;
2152 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2154 adev->mode_info.num_crtc = 4;
2155 adev->mode_info.num_hpd = 4;
2156 adev->mode_info.num_dig = 4;
2157 adev->mode_info.plane_type = dm_plane_type_default;
2161 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2165 amdgpu_dm_set_irq_funcs(adev);
2167 if (adev->mode_info.funcs == NULL)
2168 adev->mode_info.funcs = &dm_display_funcs;
2171 * Note: Do NOT change adev->audio_endpt_rreg and
2172 * adev->audio_endpt_wreg because they are initialised in
2173 * amdgpu_device_init()
2175 #if defined(CONFIG_DEBUG_KERNEL_DC)
2178 &dev_attr_s3_debug);
2184 static bool modeset_required(struct drm_crtc_state *crtc_state,
2185 struct dc_stream_state *new_stream,
2186 struct dc_stream_state *old_stream)
2188 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2191 if (!crtc_state->enable)
2194 return crtc_state->active;
2197 static bool modereset_required(struct drm_crtc_state *crtc_state)
2199 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2202 return !crtc_state->enable || !crtc_state->active;
2205 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2207 drm_encoder_cleanup(encoder);
2211 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2212 .destroy = amdgpu_dm_encoder_destroy,
2215 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2216 struct dc_plane_state *plane_state)
2218 plane_state->src_rect.x = state->src_x >> 16;
2219 plane_state->src_rect.y = state->src_y >> 16;
2220 /* we ignore the mantissa for now and do not deal with floating pixels :( */
2221 plane_state->src_rect.width = state->src_w >> 16;
2223 if (plane_state->src_rect.width == 0)
2226 plane_state->src_rect.height = state->src_h >> 16;
2227 if (plane_state->src_rect.height == 0)
2230 plane_state->dst_rect.x = state->crtc_x;
2231 plane_state->dst_rect.y = state->crtc_y;
2233 if (state->crtc_w == 0)
2236 plane_state->dst_rect.width = state->crtc_w;
2238 if (state->crtc_h == 0)
2241 plane_state->dst_rect.height = state->crtc_h;
2243 plane_state->clip_rect = plane_state->dst_rect;
2245 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2246 case DRM_MODE_ROTATE_0:
2247 plane_state->rotation = ROTATION_ANGLE_0;
2249 case DRM_MODE_ROTATE_90:
2250 plane_state->rotation = ROTATION_ANGLE_90;
2252 case DRM_MODE_ROTATE_180:
2253 plane_state->rotation = ROTATION_ANGLE_180;
2255 case DRM_MODE_ROTATE_270:
2256 plane_state->rotation = ROTATION_ANGLE_270;
2259 plane_state->rotation = ROTATION_ANGLE_0;
2265 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2266 uint64_t *tiling_flags)
2268 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2269 int r = amdgpu_bo_reserve(rbo, false);
2272 /* Don't show error message when returning -ERESTARTSYS */
2273 if (r != -ERESTARTSYS)
2274 DRM_ERROR("Unable to reserve buffer: %d\n", r);
2279 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2281 amdgpu_bo_unreserve(rbo);
2286 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2287 struct dc_plane_state *plane_state,
2288 const struct amdgpu_framebuffer *amdgpu_fb)
2290 uint64_t tiling_flags;
2291 unsigned int awidth;
2292 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2294 struct drm_format_name_buf format_name;
2303 switch (fb->format->format) {
2305 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2307 case DRM_FORMAT_RGB565:
2308 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2310 case DRM_FORMAT_XRGB8888:
2311 case DRM_FORMAT_ARGB8888:
2312 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2314 case DRM_FORMAT_XRGB2101010:
2315 case DRM_FORMAT_ARGB2101010:
2316 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2318 case DRM_FORMAT_XBGR2101010:
2319 case DRM_FORMAT_ABGR2101010:
2320 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2322 case DRM_FORMAT_XBGR8888:
2323 case DRM_FORMAT_ABGR8888:
2324 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2326 case DRM_FORMAT_NV21:
2327 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2329 case DRM_FORMAT_NV12:
2330 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2333 DRM_ERROR("Unsupported screen format %s\n",
2334 drm_get_format_name(fb->format->format, &format_name));
2338 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2339 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
2340 plane_state->plane_size.grph.surface_size.x = 0;
2341 plane_state->plane_size.grph.surface_size.y = 0;
2342 plane_state->plane_size.grph.surface_size.width = fb->width;
2343 plane_state->plane_size.grph.surface_size.height = fb->height;
2344 plane_state->plane_size.grph.surface_pitch =
2345 fb->pitches[0] / fb->format->cpp[0];
2346 /* TODO: unhardcode */
2347 plane_state->color_space = COLOR_SPACE_SRGB;
2350 awidth = ALIGN(fb->width, 64);
2351 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2352 plane_state->plane_size.video.luma_size.x = 0;
2353 plane_state->plane_size.video.luma_size.y = 0;
2354 plane_state->plane_size.video.luma_size.width = awidth;
2355 plane_state->plane_size.video.luma_size.height = fb->height;
2356 /* TODO: unhardcode */
2357 plane_state->plane_size.video.luma_pitch = awidth;
2359 plane_state->plane_size.video.chroma_size.x = 0;
2360 plane_state->plane_size.video.chroma_size.y = 0;
2361 plane_state->plane_size.video.chroma_size.width = awidth;
2362 plane_state->plane_size.video.chroma_size.height = fb->height;
2363 plane_state->plane_size.video.chroma_pitch = awidth / 2;
2365 /* TODO: unhardcode */
2366 plane_state->color_space = COLOR_SPACE_YCBCR709;
2369 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2371 /* Fill GFX8 params */
2372 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2373 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2375 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2376 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2377 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2378 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2379 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2381 /* XXX fix me for VI */
2382 plane_state->tiling_info.gfx8.num_banks = num_banks;
2383 plane_state->tiling_info.gfx8.array_mode =
2384 DC_ARRAY_2D_TILED_THIN1;
2385 plane_state->tiling_info.gfx8.tile_split = tile_split;
2386 plane_state->tiling_info.gfx8.bank_width = bankw;
2387 plane_state->tiling_info.gfx8.bank_height = bankh;
2388 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2389 plane_state->tiling_info.gfx8.tile_mode =
2390 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2391 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2392 == DC_ARRAY_1D_TILED_THIN1) {
2393 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2396 plane_state->tiling_info.gfx8.pipe_config =
2397 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2399 if (adev->asic_type == CHIP_VEGA10 ||
2400 adev->asic_type == CHIP_VEGA12 ||
2401 adev->asic_type == CHIP_VEGA20 ||
2402 adev->asic_type == CHIP_RAVEN) {
2403 /* Fill GFX9 params */
2404 plane_state->tiling_info.gfx9.num_pipes =
2405 adev->gfx.config.gb_addr_config_fields.num_pipes;
2406 plane_state->tiling_info.gfx9.num_banks =
2407 adev->gfx.config.gb_addr_config_fields.num_banks;
2408 plane_state->tiling_info.gfx9.pipe_interleave =
2409 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2410 plane_state->tiling_info.gfx9.num_shader_engines =
2411 adev->gfx.config.gb_addr_config_fields.num_se;
2412 plane_state->tiling_info.gfx9.max_compressed_frags =
2413 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2414 plane_state->tiling_info.gfx9.num_rb_per_se =
2415 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2416 plane_state->tiling_info.gfx9.swizzle =
2417 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2418 plane_state->tiling_info.gfx9.shaderEnable = 1;
2421 plane_state->visible = true;
2422 plane_state->scaling_quality.h_taps_c = 0;
2423 plane_state->scaling_quality.v_taps_c = 0;
2425 /* is this needed? is plane_state zeroed at allocation? */
2426 plane_state->scaling_quality.h_taps = 0;
2427 plane_state->scaling_quality.v_taps = 0;
2428 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
2434 static int fill_plane_attributes(struct amdgpu_device *adev,
2435 struct dc_plane_state *dc_plane_state,
2436 struct drm_plane_state *plane_state,
2437 struct drm_crtc_state *crtc_state)
2439 const struct amdgpu_framebuffer *amdgpu_fb =
2440 to_amdgpu_framebuffer(plane_state->fb);
2441 const struct drm_crtc *crtc = plane_state->crtc;
2444 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2447 ret = fill_plane_attributes_from_fb(
2448 crtc->dev->dev_private,
2456 * Always set input transfer function, since plane state is refreshed
2459 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2461 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2462 dc_plane_state->in_transfer_func = NULL;
2468 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2469 const struct dm_connector_state *dm_state,
2470 struct dc_stream_state *stream)
2472 enum amdgpu_rmx_type rmx_type;
2474 struct rect src = { 0 }; /* viewport in composition space*/
2475 struct rect dst = { 0 }; /* stream addressable area */
2477 /* no mode. nothing to be done */
2481 /* Full screen scaling by default */
2482 src.width = mode->hdisplay;
2483 src.height = mode->vdisplay;
2484 dst.width = stream->timing.h_addressable;
2485 dst.height = stream->timing.v_addressable;
2488 rmx_type = dm_state->scaling;
2489 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2490 if (src.width * dst.height <
2491 src.height * dst.width) {
2492 /* height needs less upscaling/more downscaling */
2493 dst.width = src.width *
2494 dst.height / src.height;
2496 /* width needs less upscaling/more downscaling */
2497 dst.height = src.height *
2498 dst.width / src.width;
2500 } else if (rmx_type == RMX_CENTER) {
2504 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2505 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2507 if (dm_state->underscan_enable) {
2508 dst.x += dm_state->underscan_hborder / 2;
2509 dst.y += dm_state->underscan_vborder / 2;
2510 dst.width -= dm_state->underscan_hborder;
2511 dst.height -= dm_state->underscan_vborder;
2518 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2519 dst.x, dst.y, dst.width, dst.height);
2523 static enum dc_color_depth
2524 convert_color_depth_from_display_info(const struct drm_connector *connector)
2526 struct dm_connector_state *dm_conn_state =
2527 to_dm_connector_state(connector->state);
2528 uint32_t bpc = connector->display_info.bpc;
2530 /* TODO: Remove this when there's support for max_bpc in drm */
2531 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2532 /* Round down to nearest even number. */
2533 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2538 * Temporary Work around, DRM doesn't parse color depth for
2539 * EDID revision before 1.4
2540 * TODO: Fix edid parsing
2542 return COLOR_DEPTH_888;
2544 return COLOR_DEPTH_666;
2546 return COLOR_DEPTH_888;
2548 return COLOR_DEPTH_101010;
2550 return COLOR_DEPTH_121212;
2552 return COLOR_DEPTH_141414;
2554 return COLOR_DEPTH_161616;
2556 return COLOR_DEPTH_UNDEFINED;
2560 static enum dc_aspect_ratio
2561 get_aspect_ratio(const struct drm_display_mode *mode_in)
2563 /* 1-1 mapping, since both enums follow the HDMI spec. */
2564 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
2567 static enum dc_color_space
2568 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2570 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2572 switch (dc_crtc_timing->pixel_encoding) {
2573 case PIXEL_ENCODING_YCBCR422:
2574 case PIXEL_ENCODING_YCBCR444:
2575 case PIXEL_ENCODING_YCBCR420:
2578 * 27030khz is the separation point between HDTV and SDTV
2579 * according to HDMI spec, we use YCbCr709 and YCbCr601
2582 if (dc_crtc_timing->pix_clk_khz > 27030) {
2583 if (dc_crtc_timing->flags.Y_ONLY)
2585 COLOR_SPACE_YCBCR709_LIMITED;
2587 color_space = COLOR_SPACE_YCBCR709;
2589 if (dc_crtc_timing->flags.Y_ONLY)
2591 COLOR_SPACE_YCBCR601_LIMITED;
2593 color_space = COLOR_SPACE_YCBCR601;
2598 case PIXEL_ENCODING_RGB:
2599 color_space = COLOR_SPACE_SRGB;
2610 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2612 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2615 timing_out->display_color_depth--;
2618 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2619 const struct drm_display_info *info)
2622 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2625 normalized_clk = timing_out->pix_clk_khz;
2626 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2627 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2628 normalized_clk /= 2;
2629 /* Adjusting pix clock following on HDMI spec based on colour depth */
2630 switch (timing_out->display_color_depth) {
2631 case COLOR_DEPTH_101010:
2632 normalized_clk = (normalized_clk * 30) / 24;
2634 case COLOR_DEPTH_121212:
2635 normalized_clk = (normalized_clk * 36) / 24;
2637 case COLOR_DEPTH_161616:
2638 normalized_clk = (normalized_clk * 48) / 24;
2643 if (normalized_clk <= info->max_tmds_clock)
2645 reduce_mode_colour_depth(timing_out);
2647 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2652 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2653 const struct drm_display_mode *mode_in,
2654 const struct drm_connector *connector,
2655 const struct dc_stream_state *old_stream)
2657 struct dc_crtc_timing *timing_out = &stream->timing;
2658 const struct drm_display_info *info = &connector->display_info;
2660 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2662 timing_out->h_border_left = 0;
2663 timing_out->h_border_right = 0;
2664 timing_out->v_border_top = 0;
2665 timing_out->v_border_bottom = 0;
2666 /* TODO: un-hardcode */
2667 if (drm_mode_is_420_only(info, mode_in)
2668 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2669 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2670 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2671 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2672 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2674 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2676 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2677 timing_out->display_color_depth = convert_color_depth_from_display_info(
2679 timing_out->scan_type = SCANNING_TYPE_NODATA;
2680 timing_out->hdmi_vic = 0;
2683 timing_out->vic = old_stream->timing.vic;
2684 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2685 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2687 timing_out->vic = drm_match_cea_mode(mode_in);
2688 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2689 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2690 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2691 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2694 timing_out->h_addressable = mode_in->crtc_hdisplay;
2695 timing_out->h_total = mode_in->crtc_htotal;
2696 timing_out->h_sync_width =
2697 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2698 timing_out->h_front_porch =
2699 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2700 timing_out->v_total = mode_in->crtc_vtotal;
2701 timing_out->v_addressable = mode_in->crtc_vdisplay;
2702 timing_out->v_front_porch =
2703 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2704 timing_out->v_sync_width =
2705 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2706 timing_out->pix_clk_khz = mode_in->crtc_clock;
2707 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2709 stream->output_color_space = get_output_color_space(timing_out);
2711 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2712 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
2713 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2714 adjust_colour_depth_from_display_info(timing_out, info);
2717 static void fill_audio_info(struct audio_info *audio_info,
2718 const struct drm_connector *drm_connector,
2719 const struct dc_sink *dc_sink)
2722 int cea_revision = 0;
2723 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2725 audio_info->manufacture_id = edid_caps->manufacturer_id;
2726 audio_info->product_id = edid_caps->product_id;
2728 cea_revision = drm_connector->display_info.cea_rev;
2730 strscpy(audio_info->display_name,
2731 edid_caps->display_name,
2732 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
2734 if (cea_revision >= 3) {
2735 audio_info->mode_count = edid_caps->audio_mode_count;
2737 for (i = 0; i < audio_info->mode_count; ++i) {
2738 audio_info->modes[i].format_code =
2739 (enum audio_format_code)
2740 (edid_caps->audio_modes[i].format_code);
2741 audio_info->modes[i].channel_count =
2742 edid_caps->audio_modes[i].channel_count;
2743 audio_info->modes[i].sample_rates.all =
2744 edid_caps->audio_modes[i].sample_rate;
2745 audio_info->modes[i].sample_size =
2746 edid_caps->audio_modes[i].sample_size;
2750 audio_info->flags.all = edid_caps->speaker_flags;
2752 /* TODO: We only check for the progressive mode, check for interlace mode too */
2753 if (drm_connector->latency_present[0]) {
2754 audio_info->video_latency = drm_connector->video_latency[0];
2755 audio_info->audio_latency = drm_connector->audio_latency[0];
2758 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2763 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2764 struct drm_display_mode *dst_mode)
2766 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2767 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2768 dst_mode->crtc_clock = src_mode->crtc_clock;
2769 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2770 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2771 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
2772 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2773 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2774 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2775 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2776 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2777 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2778 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2779 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2783 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2784 const struct drm_display_mode *native_mode,
2787 if (scale_enabled) {
2788 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2789 } else if (native_mode->clock == drm_mode->clock &&
2790 native_mode->htotal == drm_mode->htotal &&
2791 native_mode->vtotal == drm_mode->vtotal) {
2792 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2794 /* no scaling nor amdgpu inserted, no need to patch */
2798 static struct dc_sink *
2799 create_fake_sink(struct amdgpu_dm_connector *aconnector)
2801 struct dc_sink_init_data sink_init_data = { 0 };
2802 struct dc_sink *sink = NULL;
2803 sink_init_data.link = aconnector->dc_link;
2804 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2806 sink = dc_sink_create(&sink_init_data);
2808 DRM_ERROR("Failed to create sink!\n");
2811 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2816 static void set_multisync_trigger_params(
2817 struct dc_stream_state *stream)
2819 if (stream->triggered_crtc_reset.enabled) {
2820 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2821 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2825 static void set_master_stream(struct dc_stream_state *stream_set[],
2828 int j, highest_rfr = 0, master_stream = 0;
2830 for (j = 0; j < stream_count; j++) {
2831 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2832 int refresh_rate = 0;
2834 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2835 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2836 if (refresh_rate > highest_rfr) {
2837 highest_rfr = refresh_rate;
2842 for (j = 0; j < stream_count; j++) {
2844 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2848 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2852 if (context->stream_count < 2)
2854 for (i = 0; i < context->stream_count ; i++) {
2855 if (!context->streams[i])
2858 * TODO: add a function to read AMD VSDB bits and set
2859 * crtc_sync_master.multi_sync_enabled flag
2860 * For now it's set to false
2862 set_multisync_trigger_params(context->streams[i]);
2864 set_master_stream(context->streams, context->stream_count);
2867 static struct dc_stream_state *
2868 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2869 const struct drm_display_mode *drm_mode,
2870 const struct dm_connector_state *dm_state,
2871 const struct dc_stream_state *old_stream)
2873 struct drm_display_mode *preferred_mode = NULL;
2874 struct drm_connector *drm_connector;
2875 struct dc_stream_state *stream = NULL;
2876 struct drm_display_mode mode = *drm_mode;
2877 bool native_mode_found = false;
2878 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2880 int preferred_refresh = 0;
2882 struct dc_sink *sink = NULL;
2883 if (aconnector == NULL) {
2884 DRM_ERROR("aconnector is NULL!\n");
2888 drm_connector = &aconnector->base;
2890 if (!aconnector->dc_sink) {
2891 if (!aconnector->mst_port) {
2892 sink = create_fake_sink(aconnector);
2897 sink = aconnector->dc_sink;
2900 stream = dc_create_stream_for_sink(sink);
2902 if (stream == NULL) {
2903 DRM_ERROR("Failed to create stream for sink!\n");
2907 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2908 /* Search for preferred mode */
2909 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2910 native_mode_found = true;
2914 if (!native_mode_found)
2915 preferred_mode = list_first_entry_or_null(
2916 &aconnector->base.modes,
2917 struct drm_display_mode,
2920 mode_refresh = drm_mode_vrefresh(&mode);
2922 if (preferred_mode == NULL) {
2924 * This may not be an error, the use case is when we have no
2925 * usermode calls to reset and set mode upon hotplug. In this
2926 * case, we call set mode ourselves to restore the previous mode
2927 * and the modelist may not be filled in in time.
2929 DRM_DEBUG_DRIVER("No preferred mode found\n");
2931 decide_crtc_timing_for_drm_display_mode(
2932 &mode, preferred_mode,
2933 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2934 preferred_refresh = drm_mode_vrefresh(preferred_mode);
2938 drm_mode_set_crtcinfo(&mode, 0);
2941 * If scaling is enabled and refresh rate didn't change
2942 * we copy the vic and polarities of the old timings
2944 if (!scale || mode_refresh != preferred_refresh)
2945 fill_stream_properties_from_drm_display_mode(stream,
2946 &mode, &aconnector->base, NULL);
2948 fill_stream_properties_from_drm_display_mode(stream,
2949 &mode, &aconnector->base, old_stream);
2951 update_stream_scaling_settings(&mode, dm_state, stream);
2954 &stream->audio_info,
2958 update_stream_signal(stream);
2960 if (dm_state && dm_state->freesync_capable)
2961 stream->ignore_msa_timing_param = true;
2964 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON)
2965 dc_sink_release(sink);
2970 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2972 drm_crtc_cleanup(crtc);
2976 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2977 struct drm_crtc_state *state)
2979 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2981 /* TODO Destroy dc_stream objects are stream object is flattened */
2983 dc_stream_release(cur->stream);
2986 __drm_atomic_helper_crtc_destroy_state(state);
2992 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2994 struct dm_crtc_state *state;
2997 dm_crtc_destroy_state(crtc, crtc->state);
2999 state = kzalloc(sizeof(*state), GFP_KERNEL);
3000 if (WARN_ON(!state))
3003 crtc->state = &state->base;
3004 crtc->state->crtc = crtc;
3008 static struct drm_crtc_state *
3009 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3011 struct dm_crtc_state *state, *cur;
3013 cur = to_dm_crtc_state(crtc->state);
3015 if (WARN_ON(!crtc->state))
3018 state = kzalloc(sizeof(*state), GFP_KERNEL);
3022 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3025 state->stream = cur->stream;
3026 dc_stream_retain(state->stream);
3029 state->vrr_params = cur->vrr_params;
3030 state->vrr_infopacket = cur->vrr_infopacket;
3031 state->abm_level = cur->abm_level;
3032 state->vrr_supported = cur->vrr_supported;
3033 state->freesync_config = cur->freesync_config;
3034 state->crc_enabled = cur->crc_enabled;
3036 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3038 return &state->base;
3042 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3044 enum dc_irq_source irq_source;
3045 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3046 struct amdgpu_device *adev = crtc->dev->dev_private;
3048 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3049 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3052 static int dm_enable_vblank(struct drm_crtc *crtc)
3054 return dm_set_vblank(crtc, true);
3057 static void dm_disable_vblank(struct drm_crtc *crtc)
3059 dm_set_vblank(crtc, false);
3062 /* Implemented only the options currently availible for the driver */
3063 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3064 .reset = dm_crtc_reset_state,
3065 .destroy = amdgpu_dm_crtc_destroy,
3066 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3067 .set_config = drm_atomic_helper_set_config,
3068 .page_flip = drm_atomic_helper_page_flip,
3069 .atomic_duplicate_state = dm_crtc_duplicate_state,
3070 .atomic_destroy_state = dm_crtc_destroy_state,
3071 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3072 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3073 .enable_vblank = dm_enable_vblank,
3074 .disable_vblank = dm_disable_vblank,
3077 static enum drm_connector_status
3078 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3081 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3085 * 1. This interface is NOT called in context of HPD irq.
3086 * 2. This interface *is called* in context of user-mode ioctl. Which
3087 * makes it a bad place for *any* MST-related activity.
3090 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3091 !aconnector->fake_enable)
3092 connected = (aconnector->dc_sink != NULL);
3094 connected = (aconnector->base.force == DRM_FORCE_ON);
3096 return (connected ? connector_status_connected :
3097 connector_status_disconnected);
3100 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3101 struct drm_connector_state *connector_state,
3102 struct drm_property *property,
3105 struct drm_device *dev = connector->dev;
3106 struct amdgpu_device *adev = dev->dev_private;
3107 struct dm_connector_state *dm_old_state =
3108 to_dm_connector_state(connector->state);
3109 struct dm_connector_state *dm_new_state =
3110 to_dm_connector_state(connector_state);
3114 if (property == dev->mode_config.scaling_mode_property) {
3115 enum amdgpu_rmx_type rmx_type;
3118 case DRM_MODE_SCALE_CENTER:
3119 rmx_type = RMX_CENTER;
3121 case DRM_MODE_SCALE_ASPECT:
3122 rmx_type = RMX_ASPECT;
3124 case DRM_MODE_SCALE_FULLSCREEN:
3125 rmx_type = RMX_FULL;
3127 case DRM_MODE_SCALE_NONE:
3133 if (dm_old_state->scaling == rmx_type)
3136 dm_new_state->scaling = rmx_type;
3138 } else if (property == adev->mode_info.underscan_hborder_property) {
3139 dm_new_state->underscan_hborder = val;
3141 } else if (property == adev->mode_info.underscan_vborder_property) {
3142 dm_new_state->underscan_vborder = val;
3144 } else if (property == adev->mode_info.underscan_property) {
3145 dm_new_state->underscan_enable = val;
3147 } else if (property == adev->mode_info.max_bpc_property) {
3148 dm_new_state->max_bpc = val;
3150 } else if (property == adev->mode_info.abm_level_property) {
3151 dm_new_state->abm_level = val;
3158 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3159 const struct drm_connector_state *state,
3160 struct drm_property *property,
3163 struct drm_device *dev = connector->dev;
3164 struct amdgpu_device *adev = dev->dev_private;
3165 struct dm_connector_state *dm_state =
3166 to_dm_connector_state(state);
3169 if (property == dev->mode_config.scaling_mode_property) {
3170 switch (dm_state->scaling) {
3172 *val = DRM_MODE_SCALE_CENTER;
3175 *val = DRM_MODE_SCALE_ASPECT;
3178 *val = DRM_MODE_SCALE_FULLSCREEN;
3182 *val = DRM_MODE_SCALE_NONE;
3186 } else if (property == adev->mode_info.underscan_hborder_property) {
3187 *val = dm_state->underscan_hborder;
3189 } else if (property == adev->mode_info.underscan_vborder_property) {
3190 *val = dm_state->underscan_vborder;
3192 } else if (property == adev->mode_info.underscan_property) {
3193 *val = dm_state->underscan_enable;
3195 } else if (property == adev->mode_info.max_bpc_property) {
3196 *val = dm_state->max_bpc;
3198 } else if (property == adev->mode_info.abm_level_property) {
3199 *val = dm_state->abm_level;
3206 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3208 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3209 const struct dc_link *link = aconnector->dc_link;
3210 struct amdgpu_device *adev = connector->dev->dev_private;
3211 struct amdgpu_display_manager *dm = &adev->dm;
3213 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3214 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3216 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3217 link->type != dc_connection_none &&
3218 dm->backlight_dev) {
3219 backlight_device_unregister(dm->backlight_dev);
3220 dm->backlight_dev = NULL;
3223 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3224 drm_connector_unregister(connector);
3225 drm_connector_cleanup(connector);
3229 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3231 struct dm_connector_state *state =
3232 to_dm_connector_state(connector->state);
3234 if (connector->state)
3235 __drm_atomic_helper_connector_destroy_state(connector->state);
3239 state = kzalloc(sizeof(*state), GFP_KERNEL);
3242 state->scaling = RMX_OFF;
3243 state->underscan_enable = false;
3244 state->underscan_hborder = 0;
3245 state->underscan_vborder = 0;
3248 __drm_atomic_helper_connector_reset(connector, &state->base);
3252 struct drm_connector_state *
3253 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3255 struct dm_connector_state *state =
3256 to_dm_connector_state(connector->state);
3258 struct dm_connector_state *new_state =
3259 kmemdup(state, sizeof(*state), GFP_KERNEL);
3264 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3266 new_state->freesync_capable = state->freesync_capable;
3267 new_state->abm_level = state->abm_level;
3268 new_state->scaling = state->scaling;
3269 new_state->underscan_enable = state->underscan_enable;
3270 new_state->underscan_hborder = state->underscan_hborder;
3271 new_state->underscan_vborder = state->underscan_vborder;
3272 new_state->max_bpc = state->max_bpc;
3274 return &new_state->base;
3277 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3278 .reset = amdgpu_dm_connector_funcs_reset,
3279 .detect = amdgpu_dm_connector_detect,
3280 .fill_modes = drm_helper_probe_single_connector_modes,
3281 .destroy = amdgpu_dm_connector_destroy,
3282 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3283 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3284 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3285 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3288 static int get_modes(struct drm_connector *connector)
3290 return amdgpu_dm_connector_get_modes(connector);
3293 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3295 struct dc_sink_init_data init_params = {
3296 .link = aconnector->dc_link,
3297 .sink_signal = SIGNAL_TYPE_VIRTUAL
3301 if (!aconnector->base.edid_blob_ptr) {
3302 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3303 aconnector->base.name);
3305 aconnector->base.force = DRM_FORCE_OFF;
3306 aconnector->base.override_edid = false;
3310 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3312 aconnector->edid = edid;
3314 aconnector->dc_em_sink = dc_link_add_remote_sink(
3315 aconnector->dc_link,
3317 (edid->extensions + 1) * EDID_LENGTH,
3320 if (aconnector->base.force == DRM_FORCE_ON)
3321 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3322 aconnector->dc_link->local_sink :
3323 aconnector->dc_em_sink;
3326 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
3328 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3331 * In case of headless boot with force on for DP managed connector
3332 * Those settings have to be != 0 to get initial modeset
3334 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3335 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3336 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3340 aconnector->base.override_edid = true;
3341 create_eml_sink(aconnector);
3344 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3345 struct drm_display_mode *mode)
3347 int result = MODE_ERROR;
3348 struct dc_sink *dc_sink;
3349 struct amdgpu_device *adev = connector->dev->dev_private;
3350 /* TODO: Unhardcode stream count */
3351 struct dc_stream_state *stream;
3352 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3353 enum dc_status dc_result = DC_OK;
3355 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3356 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3360 * Only run this the first time mode_valid is called to initilialize
3363 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3364 !aconnector->dc_em_sink)
3365 handle_edid_mgmt(aconnector);
3367 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
3369 if (dc_sink == NULL) {
3370 DRM_ERROR("dc_sink is NULL!\n");
3374 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
3375 if (stream == NULL) {
3376 DRM_ERROR("Failed to create stream for sink!\n");
3380 dc_result = dc_validate_stream(adev->dm.dc, stream);
3382 if (dc_result == DC_OK)
3385 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
3391 dc_stream_release(stream);
3394 /* TODO: error handling*/
3398 static const struct drm_connector_helper_funcs
3399 amdgpu_dm_connector_helper_funcs = {
3401 * If hotplugging a second bigger display in FB Con mode, bigger resolution
3402 * modes will be filtered by drm_mode_validate_size(), and those modes
3403 * are missing after user start lightdm. So we need to renew modes list.
3404 * in get_modes call back, not just return the modes count
3406 .get_modes = get_modes,
3407 .mode_valid = amdgpu_dm_connector_mode_valid,
3410 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3414 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3415 struct drm_crtc_state *state)
3417 struct amdgpu_device *adev = crtc->dev->dev_private;
3418 struct dc *dc = adev->dm.dc;
3419 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3422 if (unlikely(!dm_crtc_state->stream &&
3423 modeset_required(state, NULL, dm_crtc_state->stream))) {
3428 /* In some use cases, like reset, no stream is attached */
3429 if (!dm_crtc_state->stream)
3432 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
3438 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3439 const struct drm_display_mode *mode,
3440 struct drm_display_mode *adjusted_mode)
3445 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3446 .disable = dm_crtc_helper_disable,
3447 .atomic_check = dm_crtc_helper_atomic_check,
3448 .mode_fixup = dm_crtc_helper_mode_fixup
3451 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3456 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3457 struct drm_crtc_state *crtc_state,
3458 struct drm_connector_state *conn_state)
3463 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3464 .disable = dm_encoder_helper_disable,
3465 .atomic_check = dm_encoder_helper_atomic_check
3468 static void dm_drm_plane_reset(struct drm_plane *plane)
3470 struct dm_plane_state *amdgpu_state = NULL;
3473 plane->funcs->atomic_destroy_state(plane, plane->state);
3475 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
3476 WARN_ON(amdgpu_state == NULL);
3479 plane->state = &amdgpu_state->base;
3480 plane->state->plane = plane;
3481 plane->state->rotation = DRM_MODE_ROTATE_0;
3485 static struct drm_plane_state *
3486 dm_drm_plane_duplicate_state(struct drm_plane *plane)
3488 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3490 old_dm_plane_state = to_dm_plane_state(plane->state);
3491 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3492 if (!dm_plane_state)
3495 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3497 if (old_dm_plane_state->dc_state) {
3498 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3499 dc_plane_state_retain(dm_plane_state->dc_state);
3502 return &dm_plane_state->base;
3505 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3506 struct drm_plane_state *state)
3508 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3510 if (dm_plane_state->dc_state)
3511 dc_plane_state_release(dm_plane_state->dc_state);
3513 drm_atomic_helper_plane_destroy_state(plane, state);
3516 static const struct drm_plane_funcs dm_plane_funcs = {
3517 .update_plane = drm_atomic_helper_update_plane,
3518 .disable_plane = drm_atomic_helper_disable_plane,
3519 .destroy = drm_primary_helper_destroy,
3520 .reset = dm_drm_plane_reset,
3521 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3522 .atomic_destroy_state = dm_drm_plane_destroy_state,
3525 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3526 struct drm_plane_state *new_state)
3528 struct amdgpu_framebuffer *afb;
3529 struct drm_gem_object *obj;
3530 struct amdgpu_device *adev;
3531 struct amdgpu_bo *rbo;
3532 uint64_t chroma_addr = 0;
3533 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3534 unsigned int awidth;
3538 dm_plane_state_old = to_dm_plane_state(plane->state);
3539 dm_plane_state_new = to_dm_plane_state(new_state);
3541 if (!new_state->fb) {
3542 DRM_DEBUG_DRIVER("No FB bound\n");
3546 afb = to_amdgpu_framebuffer(new_state->fb);
3547 obj = new_state->fb->obj[0];
3548 rbo = gem_to_amdgpu_bo(obj);
3549 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3550 r = amdgpu_bo_reserve(rbo, false);
3551 if (unlikely(r != 0))
3554 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3555 domain = amdgpu_display_supported_domains(adev);
3557 domain = AMDGPU_GEM_DOMAIN_VRAM;
3559 r = amdgpu_bo_pin(rbo, domain);
3560 if (unlikely(r != 0)) {
3561 if (r != -ERESTARTSYS)
3562 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3563 amdgpu_bo_unreserve(rbo);
3567 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3568 if (unlikely(r != 0)) {
3569 amdgpu_bo_unpin(rbo);
3570 amdgpu_bo_unreserve(rbo);
3571 DRM_ERROR("%p bind failed\n", rbo);
3574 amdgpu_bo_unreserve(rbo);
3576 afb->address = amdgpu_bo_gpu_offset(rbo);
3580 if (dm_plane_state_new->dc_state &&
3581 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3582 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3584 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3585 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3586 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3588 awidth = ALIGN(new_state->fb->width, 64);
3589 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3590 plane_state->address.video_progressive.luma_addr.low_part
3591 = lower_32_bits(afb->address);
3592 plane_state->address.video_progressive.luma_addr.high_part
3593 = upper_32_bits(afb->address);
3594 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3595 plane_state->address.video_progressive.chroma_addr.low_part
3596 = lower_32_bits(chroma_addr);
3597 plane_state->address.video_progressive.chroma_addr.high_part
3598 = upper_32_bits(chroma_addr);
3605 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3606 struct drm_plane_state *old_state)
3608 struct amdgpu_bo *rbo;
3614 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
3615 r = amdgpu_bo_reserve(rbo, false);
3617 DRM_ERROR("failed to reserve rbo before unpin\n");
3621 amdgpu_bo_unpin(rbo);
3622 amdgpu_bo_unreserve(rbo);
3623 amdgpu_bo_unref(&rbo);
3626 static int dm_plane_atomic_check(struct drm_plane *plane,
3627 struct drm_plane_state *state)
3629 struct amdgpu_device *adev = plane->dev->dev_private;
3630 struct dc *dc = adev->dm.dc;
3631 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3633 if (!dm_plane_state->dc_state)
3636 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3639 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3645 static int dm_plane_atomic_async_check(struct drm_plane *plane,
3646 struct drm_plane_state *new_plane_state)
3648 struct drm_plane_state *old_plane_state =
3649 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3651 /* Only support async updates on cursor planes. */
3652 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3656 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3657 * async commits so don't allow fb changes.
3659 if (old_plane_state->fb != new_plane_state->fb)
3665 static void dm_plane_atomic_async_update(struct drm_plane *plane,
3666 struct drm_plane_state *new_state)
3668 struct drm_plane_state *old_state =
3669 drm_atomic_get_old_plane_state(new_state->state, plane);
3671 if (plane->state->fb != new_state->fb)
3672 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3674 plane->state->src_x = new_state->src_x;
3675 plane->state->src_y = new_state->src_y;
3676 plane->state->src_w = new_state->src_w;
3677 plane->state->src_h = new_state->src_h;
3678 plane->state->crtc_x = new_state->crtc_x;
3679 plane->state->crtc_y = new_state->crtc_y;
3680 plane->state->crtc_w = new_state->crtc_w;
3681 plane->state->crtc_h = new_state->crtc_h;
3683 handle_cursor_update(plane, old_state);
3686 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3687 .prepare_fb = dm_plane_helper_prepare_fb,
3688 .cleanup_fb = dm_plane_helper_cleanup_fb,
3689 .atomic_check = dm_plane_atomic_check,
3690 .atomic_async_check = dm_plane_atomic_async_check,
3691 .atomic_async_update = dm_plane_atomic_async_update
3695 * TODO: these are currently initialized to rgb formats only.
3696 * For future use cases we should either initialize them dynamically based on
3697 * plane capabilities, or initialize this array to all formats, so internal drm
3698 * check will succeed, and let DC implement proper check
3700 static const uint32_t rgb_formats[] = {
3702 DRM_FORMAT_XRGB8888,
3703 DRM_FORMAT_ARGB8888,
3704 DRM_FORMAT_RGBA8888,
3705 DRM_FORMAT_XRGB2101010,
3706 DRM_FORMAT_XBGR2101010,
3707 DRM_FORMAT_ARGB2101010,
3708 DRM_FORMAT_ABGR2101010,
3709 DRM_FORMAT_XBGR8888,
3710 DRM_FORMAT_ABGR8888,
3713 static const uint32_t yuv_formats[] = {
3718 static const u32 cursor_formats[] = {
3722 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3723 struct drm_plane *plane,
3724 unsigned long possible_crtcs)
3728 switch (plane->type) {
3729 case DRM_PLANE_TYPE_PRIMARY:
3730 res = drm_universal_plane_init(
3736 ARRAY_SIZE(rgb_formats),
3737 NULL, plane->type, NULL);
3739 case DRM_PLANE_TYPE_OVERLAY:
3740 res = drm_universal_plane_init(
3746 ARRAY_SIZE(yuv_formats),
3747 NULL, plane->type, NULL);
3749 case DRM_PLANE_TYPE_CURSOR:
3750 res = drm_universal_plane_init(
3756 ARRAY_SIZE(cursor_formats),
3757 NULL, plane->type, NULL);
3761 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
3763 /* Create (reset) the plane state */
3764 if (plane->funcs->reset)
3765 plane->funcs->reset(plane);
3771 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3772 struct drm_plane *plane,
3773 uint32_t crtc_index)
3775 struct amdgpu_crtc *acrtc = NULL;
3776 struct drm_plane *cursor_plane;
3780 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3784 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
3785 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3787 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3791 res = drm_crtc_init_with_planes(
3796 &amdgpu_dm_crtc_funcs, NULL);
3801 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3803 /* Create (reset) the plane state */
3804 if (acrtc->base.funcs->reset)
3805 acrtc->base.funcs->reset(&acrtc->base);
3807 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3808 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3810 acrtc->crtc_id = crtc_index;
3811 acrtc->base.enabled = false;
3812 acrtc->otg_inst = -1;
3814 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3815 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3816 true, MAX_COLOR_LUT_ENTRIES);
3817 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3823 kfree(cursor_plane);
3828 static int to_drm_connector_type(enum signal_type st)
3831 case SIGNAL_TYPE_HDMI_TYPE_A:
3832 return DRM_MODE_CONNECTOR_HDMIA;
3833 case SIGNAL_TYPE_EDP:
3834 return DRM_MODE_CONNECTOR_eDP;
3835 case SIGNAL_TYPE_LVDS:
3836 return DRM_MODE_CONNECTOR_LVDS;
3837 case SIGNAL_TYPE_RGB:
3838 return DRM_MODE_CONNECTOR_VGA;
3839 case SIGNAL_TYPE_DISPLAY_PORT:
3840 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3841 return DRM_MODE_CONNECTOR_DisplayPort;
3842 case SIGNAL_TYPE_DVI_DUAL_LINK:
3843 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3844 return DRM_MODE_CONNECTOR_DVID;
3845 case SIGNAL_TYPE_VIRTUAL:
3846 return DRM_MODE_CONNECTOR_VIRTUAL;
3849 return DRM_MODE_CONNECTOR_Unknown;
3853 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3855 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3858 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3860 struct drm_encoder *encoder;
3861 struct amdgpu_encoder *amdgpu_encoder;
3863 encoder = amdgpu_dm_connector_to_encoder(connector);
3865 if (encoder == NULL)
3868 amdgpu_encoder = to_amdgpu_encoder(encoder);
3870 amdgpu_encoder->native_mode.clock = 0;
3872 if (!list_empty(&connector->probed_modes)) {
3873 struct drm_display_mode *preferred_mode = NULL;
3875 list_for_each_entry(preferred_mode,
3876 &connector->probed_modes,
3878 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3879 amdgpu_encoder->native_mode = *preferred_mode;
3887 static struct drm_display_mode *
3888 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3890 int hdisplay, int vdisplay)
3892 struct drm_device *dev = encoder->dev;
3893 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3894 struct drm_display_mode *mode = NULL;
3895 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3897 mode = drm_mode_duplicate(dev, native_mode);
3902 mode->hdisplay = hdisplay;
3903 mode->vdisplay = vdisplay;
3904 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3905 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3911 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3912 struct drm_connector *connector)
3914 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3915 struct drm_display_mode *mode = NULL;
3916 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3917 struct amdgpu_dm_connector *amdgpu_dm_connector =
3918 to_amdgpu_dm_connector(connector);
3922 char name[DRM_DISPLAY_MODE_LEN];
3925 } common_modes[] = {
3926 { "640x480", 640, 480},
3927 { "800x600", 800, 600},
3928 { "1024x768", 1024, 768},
3929 { "1280x720", 1280, 720},
3930 { "1280x800", 1280, 800},
3931 {"1280x1024", 1280, 1024},
3932 { "1440x900", 1440, 900},
3933 {"1680x1050", 1680, 1050},
3934 {"1600x1200", 1600, 1200},
3935 {"1920x1080", 1920, 1080},
3936 {"1920x1200", 1920, 1200}
3939 n = ARRAY_SIZE(common_modes);
3941 for (i = 0; i < n; i++) {
3942 struct drm_display_mode *curmode = NULL;
3943 bool mode_existed = false;
3945 if (common_modes[i].w > native_mode->hdisplay ||
3946 common_modes[i].h > native_mode->vdisplay ||
3947 (common_modes[i].w == native_mode->hdisplay &&
3948 common_modes[i].h == native_mode->vdisplay))
3951 list_for_each_entry(curmode, &connector->probed_modes, head) {
3952 if (common_modes[i].w == curmode->hdisplay &&
3953 common_modes[i].h == curmode->vdisplay) {
3954 mode_existed = true;
3962 mode = amdgpu_dm_create_common_mode(encoder,
3963 common_modes[i].name, common_modes[i].w,
3965 drm_mode_probed_add(connector, mode);
3966 amdgpu_dm_connector->num_modes++;
3970 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3973 struct amdgpu_dm_connector *amdgpu_dm_connector =
3974 to_amdgpu_dm_connector(connector);
3977 /* empty probed_modes */
3978 INIT_LIST_HEAD(&connector->probed_modes);
3979 amdgpu_dm_connector->num_modes =
3980 drm_add_edid_modes(connector, edid);
3982 amdgpu_dm_get_native_mode(connector);
3984 amdgpu_dm_connector->num_modes = 0;
3988 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3990 struct amdgpu_dm_connector *amdgpu_dm_connector =
3991 to_amdgpu_dm_connector(connector);
3992 struct drm_encoder *encoder;
3993 struct edid *edid = amdgpu_dm_connector->edid;
3995 encoder = amdgpu_dm_connector_to_encoder(connector);
3997 if (!edid || !drm_edid_is_valid(edid)) {
3998 amdgpu_dm_connector->num_modes =
3999 drm_add_modes_noedid(connector, 640, 480);
4001 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4002 amdgpu_dm_connector_add_common_modes(encoder, connector);
4004 amdgpu_dm_fbc_init(connector);
4006 return amdgpu_dm_connector->num_modes;
4009 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4010 struct amdgpu_dm_connector *aconnector,
4012 struct dc_link *link,
4015 struct amdgpu_device *adev = dm->ddev->dev_private;
4017 aconnector->connector_id = link_index;
4018 aconnector->dc_link = link;
4019 aconnector->base.interlace_allowed = false;
4020 aconnector->base.doublescan_allowed = false;
4021 aconnector->base.stereo_allowed = false;
4022 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4023 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
4024 mutex_init(&aconnector->hpd_lock);
4027 * configure support HPD hot plug connector_>polled default value is 0
4028 * which means HPD hot plug not supported
4030 switch (connector_type) {
4031 case DRM_MODE_CONNECTOR_HDMIA:
4032 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4033 aconnector->base.ycbcr_420_allowed =
4034 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
4036 case DRM_MODE_CONNECTOR_DisplayPort:
4037 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4038 aconnector->base.ycbcr_420_allowed =
4039 link->link_enc->features.dp_ycbcr420_supported ? true : false;
4041 case DRM_MODE_CONNECTOR_DVID:
4042 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4048 drm_object_attach_property(&aconnector->base.base,
4049 dm->ddev->mode_config.scaling_mode_property,
4050 DRM_MODE_SCALE_NONE);
4052 drm_object_attach_property(&aconnector->base.base,
4053 adev->mode_info.underscan_property,
4055 drm_object_attach_property(&aconnector->base.base,
4056 adev->mode_info.underscan_hborder_property,
4058 drm_object_attach_property(&aconnector->base.base,
4059 adev->mode_info.underscan_vborder_property,
4061 drm_object_attach_property(&aconnector->base.base,
4062 adev->mode_info.max_bpc_property,
4065 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4066 dc_is_dmcu_initialized(adev->dm.dc)) {
4067 drm_object_attach_property(&aconnector->base.base,
4068 adev->mode_info.abm_level_property, 0);
4071 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4072 connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
4073 drm_connector_attach_vrr_capable_property(
4078 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4079 struct i2c_msg *msgs, int num)
4081 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4082 struct ddc_service *ddc_service = i2c->ddc_service;
4083 struct i2c_command cmd;
4087 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
4092 cmd.number_of_payloads = num;
4093 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4096 for (i = 0; i < num; i++) {
4097 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4098 cmd.payloads[i].address = msgs[i].addr;
4099 cmd.payloads[i].length = msgs[i].len;
4100 cmd.payloads[i].data = msgs[i].buf;
4104 ddc_service->ctx->dc,
4105 ddc_service->ddc_pin->hw_info.ddc_channel,
4109 kfree(cmd.payloads);
4113 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
4115 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4118 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4119 .master_xfer = amdgpu_dm_i2c_xfer,
4120 .functionality = amdgpu_dm_i2c_func,
4123 static struct amdgpu_i2c_adapter *
4124 create_i2c(struct ddc_service *ddc_service,
4128 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4129 struct amdgpu_i2c_adapter *i2c;
4131 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
4134 i2c->base.owner = THIS_MODULE;
4135 i2c->base.class = I2C_CLASS_DDC;
4136 i2c->base.dev.parent = &adev->pdev->dev;
4137 i2c->base.algo = &amdgpu_dm_i2c_algo;
4138 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4139 i2c_set_adapdata(&i2c->base, i2c);
4140 i2c->ddc_service = ddc_service;
4141 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
4148 * Note: this function assumes that dc_link_detect() was called for the
4149 * dc_link which will be represented by this aconnector.
4151 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4152 struct amdgpu_dm_connector *aconnector,
4153 uint32_t link_index,
4154 struct amdgpu_encoder *aencoder)
4158 struct dc *dc = dm->dc;
4159 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4160 struct amdgpu_i2c_adapter *i2c;
4162 link->priv = aconnector;
4164 DRM_DEBUG_DRIVER("%s()\n", __func__);
4166 i2c = create_i2c(link->ddc, link->link_index, &res);
4168 DRM_ERROR("Failed to create i2c adapter data\n");
4172 aconnector->i2c = i2c;
4173 res = i2c_add_adapter(&i2c->base);
4176 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4180 connector_type = to_drm_connector_type(link->connector_signal);
4182 res = drm_connector_init(
4185 &amdgpu_dm_connector_funcs,
4189 DRM_ERROR("connector_init failed\n");
4190 aconnector->connector_id = -1;
4194 drm_connector_helper_add(
4196 &amdgpu_dm_connector_helper_funcs);
4198 if (aconnector->base.funcs->reset)
4199 aconnector->base.funcs->reset(&aconnector->base);
4201 amdgpu_dm_connector_init_helper(
4208 drm_connector_attach_encoder(
4209 &aconnector->base, &aencoder->base);
4211 drm_connector_register(&aconnector->base);
4212 #if defined(CONFIG_DEBUG_FS)
4213 res = connector_debugfs_init(aconnector);
4215 DRM_ERROR("Failed to create debugfs for connector");
4220 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4221 || connector_type == DRM_MODE_CONNECTOR_eDP)
4222 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4227 aconnector->i2c = NULL;
4232 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4234 switch (adev->mode_info.num_crtc) {
4251 static int amdgpu_dm_encoder_init(struct drm_device *dev,
4252 struct amdgpu_encoder *aencoder,
4253 uint32_t link_index)
4255 struct amdgpu_device *adev = dev->dev_private;
4257 int res = drm_encoder_init(dev,
4259 &amdgpu_dm_encoder_funcs,
4260 DRM_MODE_ENCODER_TMDS,
4263 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4266 aencoder->encoder_id = link_index;
4268 aencoder->encoder_id = -1;
4270 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4275 static void manage_dm_interrupts(struct amdgpu_device *adev,
4276 struct amdgpu_crtc *acrtc,
4280 * this is not correct translation but will work as soon as VBLANK
4281 * constant is the same as PFLIP
4284 amdgpu_display_crtc_idx_to_irq_type(
4289 drm_crtc_vblank_on(&acrtc->base);
4292 &adev->pageflip_irq,
4298 &adev->pageflip_irq,
4300 drm_crtc_vblank_off(&acrtc->base);
4305 is_scaling_state_different(const struct dm_connector_state *dm_state,
4306 const struct dm_connector_state *old_dm_state)
4308 if (dm_state->scaling != old_dm_state->scaling)
4310 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4311 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4313 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4314 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4316 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4317 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4322 static void remove_stream(struct amdgpu_device *adev,
4323 struct amdgpu_crtc *acrtc,
4324 struct dc_stream_state *stream)
4326 /* this is the update mode case */
4328 acrtc->otg_inst = -1;
4329 acrtc->enabled = false;
4332 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4333 struct dc_cursor_position *position)
4335 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4337 int xorigin = 0, yorigin = 0;
4339 if (!crtc || !plane->state->fb) {
4340 position->enable = false;
4346 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4347 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4348 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4350 plane->state->crtc_w,
4351 plane->state->crtc_h);
4355 x = plane->state->crtc_x;
4356 y = plane->state->crtc_y;
4357 /* avivo cursor are offset into the total surface */
4358 x += crtc->primary->state->src_x >> 16;
4359 y += crtc->primary->state->src_y >> 16;
4361 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4365 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4368 position->enable = true;
4371 position->x_hotspot = xorigin;
4372 position->y_hotspot = yorigin;
4377 static void handle_cursor_update(struct drm_plane *plane,
4378 struct drm_plane_state *old_plane_state)
4380 struct amdgpu_device *adev = plane->dev->dev_private;
4381 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4382 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4383 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4384 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4385 uint64_t address = afb ? afb->address : 0;
4386 struct dc_cursor_position position;
4387 struct dc_cursor_attributes attributes;
4390 if (!plane->state->fb && !old_plane_state->fb)
4393 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
4395 amdgpu_crtc->crtc_id,
4396 plane->state->crtc_w,
4397 plane->state->crtc_h);
4399 ret = get_cursor_position(plane, crtc, &position);
4403 if (!position.enable) {
4404 /* turn off cursor */
4405 if (crtc_state && crtc_state->stream) {
4406 mutex_lock(&adev->dm.dc_lock);
4407 dc_stream_set_cursor_position(crtc_state->stream,
4409 mutex_unlock(&adev->dm.dc_lock);
4414 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4415 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4417 attributes.address.high_part = upper_32_bits(address);
4418 attributes.address.low_part = lower_32_bits(address);
4419 attributes.width = plane->state->crtc_w;
4420 attributes.height = plane->state->crtc_h;
4421 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4422 attributes.rotation_angle = 0;
4423 attributes.attribute_flags.value = 0;
4425 attributes.pitch = attributes.width;
4427 if (crtc_state->stream) {
4428 mutex_lock(&adev->dm.dc_lock);
4429 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4431 DRM_ERROR("DC failed to set cursor attributes\n");
4433 if (!dc_stream_set_cursor_position(crtc_state->stream,
4435 DRM_ERROR("DC failed to set cursor position\n");
4436 mutex_unlock(&adev->dm.dc_lock);
4440 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4443 assert_spin_locked(&acrtc->base.dev->event_lock);
4444 WARN_ON(acrtc->event);
4446 acrtc->event = acrtc->base.state->event;
4448 /* Set the flip status */
4449 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4451 /* Mark this event as consumed */
4452 acrtc->base.state->event = NULL;
4454 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4458 struct dc_stream_status *dc_state_get_stream_status(
4459 struct dc_state *state,
4460 struct dc_stream_state *stream)
4464 for (i = 0; i < state->stream_count; i++) {
4465 if (stream == state->streams[i])
4466 return &state->stream_status[i];
4472 static void update_freesync_state_on_stream(
4473 struct amdgpu_display_manager *dm,
4474 struct dm_crtc_state *new_crtc_state,
4475 struct dc_stream_state *new_stream,
4476 struct dc_plane_state *surface,
4477 u32 flip_timestamp_in_us)
4479 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
4480 struct dc_info_packet vrr_infopacket = {0};
4481 struct mod_freesync_config config = new_crtc_state->freesync_config;
4487 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4488 * For now it's sufficient to just guard against these conditions.
4491 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4494 if (new_crtc_state->vrr_supported &&
4495 config.min_refresh_in_uhz &&
4496 config.max_refresh_in_uhz) {
4497 config.state = new_crtc_state->base.vrr_enabled ?
4498 VRR_STATE_ACTIVE_VARIABLE :
4501 config.state = VRR_STATE_UNSUPPORTED;
4504 mod_freesync_build_vrr_params(dm->freesync_module,
4506 &config, &vrr_params);
4509 mod_freesync_handle_preflip(
4510 dm->freesync_module,
4513 flip_timestamp_in_us,
4517 mod_freesync_build_vrr_infopacket(
4518 dm->freesync_module,
4522 TRANSFER_FUNC_UNKNOWN,
4525 new_crtc_state->freesync_timing_changed =
4526 (memcmp(&new_crtc_state->vrr_params.adjust,
4528 sizeof(vrr_params.adjust)) != 0);
4530 new_crtc_state->freesync_vrr_info_changed =
4531 (memcmp(&new_crtc_state->vrr_infopacket,
4533 sizeof(vrr_infopacket)) != 0);
4535 new_crtc_state->vrr_params = vrr_params;
4536 new_crtc_state->vrr_infopacket = vrr_infopacket;
4538 new_stream->adjust = new_crtc_state->vrr_params.adjust;
4539 new_stream->vrr_infopacket = vrr_infopacket;
4541 if (new_crtc_state->freesync_vrr_info_changed)
4542 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4543 new_crtc_state->base.crtc->base.id,
4544 (int)new_crtc_state->base.vrr_enabled,
4545 (int)vrr_params.state);
4547 if (new_crtc_state->freesync_timing_changed)
4548 DRM_DEBUG_KMS("VRR timing update: crtc=%u min=%u max=%u\n",
4549 new_crtc_state->base.crtc->base.id,
4550 vrr_params.adjust.v_total_min,
4551 vrr_params.adjust.v_total_max);
4557 * Waits on all BO's fences and for proper vblank count
4559 static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
4560 struct drm_framebuffer *fb,
4562 struct dc_state *state)
4564 unsigned long flags;
4565 uint64_t timestamp_ns;
4566 uint32_t target_vblank;
4568 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4569 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
4570 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
4571 struct amdgpu_device *adev = crtc->dev->dev_private;
4572 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
4573 struct dc_flip_addrs addr = { {0} };
4574 /* TODO eliminate or rename surface_update */
4575 struct dc_surface_update surface_updates[1] = { {0} };
4576 struct dc_stream_update stream_update = {0};
4577 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4578 struct dc_stream_status *stream_status;
4579 struct dc_plane_state *surface;
4582 /* Prepare wait for target vblank early - before the fence-waits */
4583 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
4584 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
4587 * TODO This might fail and hence better not used, wait
4588 * explicitly on fences instead
4589 * and in general should be called for
4590 * blocking commit to as per framework helpers
4592 r = amdgpu_bo_reserve(abo, true);
4593 if (unlikely(r != 0)) {
4594 DRM_ERROR("failed to reserve buffer before flip\n");
4598 /* Wait for all fences on this FB */
4599 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4600 MAX_SCHEDULE_TIMEOUT) < 0);
4602 amdgpu_bo_unreserve(abo);
4605 * Wait until we're out of the vertical blank period before the one
4606 * targeted by the flip
4608 while ((acrtc->enabled &&
4609 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4610 0, &vpos, &hpos, NULL,
4611 NULL, &crtc->hwmode)
4612 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4613 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4614 (int)(target_vblank -
4615 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4616 usleep_range(1000, 1100);
4620 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4622 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4623 WARN_ON(!acrtc_state->stream);
4625 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4626 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4627 addr.flip_immediate = async_flip;
4629 timestamp_ns = ktime_get_ns();
4630 addr.flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
4633 if (acrtc->base.state->event)
4634 prepare_flip_isr(acrtc);
4636 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4638 stream_status = dc_stream_get_status(acrtc_state->stream);
4639 if (!stream_status) {
4640 DRM_ERROR("No stream status for CRTC: id=%d\n",
4645 surface = stream_status->plane_states[0];
4646 surface_updates->surface = surface;
4649 DRM_ERROR("No surface for CRTC: id=%d\n",
4653 surface_updates->flip_addr = &addr;
4655 if (acrtc_state->stream) {
4656 update_freesync_state_on_stream(
4659 acrtc_state->stream,
4661 addr.flip_timestamp_in_us);
4663 if (acrtc_state->freesync_timing_changed)
4664 stream_update.adjust =
4665 &acrtc_state->stream->adjust;
4667 if (acrtc_state->freesync_vrr_info_changed)
4668 stream_update.vrr_infopacket =
4669 &acrtc_state->stream->vrr_infopacket;
4672 /* Update surface timing information. */
4673 surface->time.time_elapsed_in_us[surface->time.index] =
4674 addr.flip_timestamp_in_us - surface->time.prev_update_time_in_us;
4675 surface->time.prev_update_time_in_us = addr.flip_timestamp_in_us;
4676 surface->time.index++;
4677 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
4678 surface->time.index = 0;
4680 mutex_lock(&adev->dm.dc_lock);
4682 dc_commit_updates_for_stream(adev->dm.dc,
4685 acrtc_state->stream,
4687 &surface_updates->surface,
4689 mutex_unlock(&adev->dm.dc_lock);
4691 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4693 addr.address.grph.addr.high_part,
4694 addr.address.grph.addr.low_part);
4698 * TODO this whole function needs to go
4700 * dc_surface_update is needlessly complex. See if we can just replace this
4701 * with a dc_plane_state and follow the atomic model a bit more closely here.
4703 static bool commit_planes_to_stream(
4704 struct amdgpu_display_manager *dm,
4706 struct dc_plane_state **plane_states,
4707 uint8_t new_plane_count,
4708 struct dm_crtc_state *dm_new_crtc_state,
4709 struct dm_crtc_state *dm_old_crtc_state,
4710 struct dc_state *state)
4712 /* no need to dynamically allocate this. it's pretty small */
4713 struct dc_surface_update updates[MAX_SURFACES];
4714 struct dc_flip_addrs *flip_addr;
4715 struct dc_plane_info *plane_info;
4716 struct dc_scaling_info *scaling_info;
4718 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4719 struct dc_stream_update *stream_update =
4720 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
4721 unsigned int abm_level;
4723 if (!stream_update) {
4724 BREAK_TO_DEBUGGER();
4728 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4730 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4732 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4735 if (!flip_addr || !plane_info || !scaling_info) {
4738 kfree(scaling_info);
4739 kfree(stream_update);
4743 memset(updates, 0, sizeof(updates));
4745 stream_update->src = dc_stream->src;
4746 stream_update->dst = dc_stream->dst;
4747 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4749 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
4750 abm_level = dm_new_crtc_state->abm_level;
4751 stream_update->abm_level = &abm_level;
4754 for (i = 0; i < new_plane_count; i++) {
4755 updates[i].surface = plane_states[i];
4757 (struct dc_gamma *)plane_states[i]->gamma_correction;
4758 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4759 flip_addr[i].address = plane_states[i]->address;
4760 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4761 plane_info[i].color_space = plane_states[i]->color_space;
4762 plane_info[i].format = plane_states[i]->format;
4763 plane_info[i].plane_size = plane_states[i]->plane_size;
4764 plane_info[i].rotation = plane_states[i]->rotation;
4765 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4766 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4767 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4768 plane_info[i].visible = plane_states[i]->visible;
4769 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4770 plane_info[i].dcc = plane_states[i]->dcc;
4771 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4772 scaling_info[i].src_rect = plane_states[i]->src_rect;
4773 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4774 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4776 updates[i].flip_addr = &flip_addr[i];
4777 updates[i].plane_info = &plane_info[i];
4778 updates[i].scaling_info = &scaling_info[i];
4781 mutex_lock(&dm->dc_lock);
4782 dc_commit_updates_for_stream(
4786 dc_stream, stream_update, plane_states, state);
4787 mutex_unlock(&dm->dc_lock);
4791 kfree(scaling_info);
4792 kfree(stream_update);
4796 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
4797 struct dc_state *dc_state,
4798 struct drm_device *dev,
4799 struct amdgpu_display_manager *dm,
4800 struct drm_crtc *pcrtc,
4801 bool *wait_for_vblank)
4804 struct drm_plane *plane;
4805 struct drm_plane_state *old_plane_state, *new_plane_state;
4806 struct dc_stream_state *dc_stream_attach;
4807 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
4808 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4809 struct drm_crtc_state *new_pcrtc_state =
4810 drm_atomic_get_new_crtc_state(state, pcrtc);
4811 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4812 struct dm_crtc_state *dm_old_crtc_state =
4813 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
4814 int planes_count = 0;
4815 unsigned long flags;
4817 /* update planes when needed */
4818 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4819 struct drm_crtc *crtc = new_plane_state->crtc;
4820 struct drm_crtc_state *new_crtc_state;
4821 struct drm_framebuffer *fb = new_plane_state->fb;
4823 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4825 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4826 handle_cursor_update(plane, old_plane_state);
4830 if (!fb || !crtc || pcrtc != crtc)
4833 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4834 if (!new_crtc_state->active)
4837 pflip_needed = !state->allow_modeset;
4839 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4840 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
4841 DRM_ERROR("%s: acrtc %d, already busy\n",
4843 acrtc_attach->crtc_id);
4844 /* In commit tail framework this cannot happen */
4847 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4849 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
4850 WARN_ON(!dm_new_plane_state->dc_state);
4852 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
4854 dc_stream_attach = acrtc_state->stream;
4857 } else if (new_crtc_state->planes_changed) {
4858 /* Assume even ONE crtc with immediate flip means
4859 * entire can't wait for VBLANK
4860 * TODO Check if it's correct
4863 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
4866 /* TODO: Needs rework for multiplane flip */
4867 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4868 drm_crtc_vblank_get(crtc);
4873 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4880 unsigned long flags;
4882 if (new_pcrtc_state->event) {
4884 drm_crtc_vblank_get(pcrtc);
4886 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4887 prepare_flip_isr(acrtc_attach);
4888 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4891 dc_stream_attach->abm_level = acrtc_state->abm_level;
4893 if (false == commit_planes_to_stream(dm,
4895 plane_states_constructed,
4900 dm_error("%s: Failed to attach plane!\n", __func__);
4902 /*TODO BUG Here should go disable planes on CRTC. */
4907 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4908 * @crtc_state: the DRM CRTC state
4909 * @stream_state: the DC stream state.
4911 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4912 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4914 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4915 struct dc_stream_state *stream_state)
4917 stream_state->mode_changed = crtc_state->mode_changed;
4920 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4921 struct drm_atomic_state *state,
4924 struct drm_crtc *crtc;
4925 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4926 struct amdgpu_device *adev = dev->dev_private;
4930 * We evade vblanks and pflips on crtc that
4931 * should be changed. We do it here to flush & disable
4932 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4933 * it will update crtc->dm_crtc_state->stream pointer which is used in
4936 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4937 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4938 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4940 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4941 manage_dm_interrupts(adev, acrtc, false);
4944 * Add check here for SoC's that support hardware cursor plane, to
4945 * unset legacy_cursor_update
4948 return drm_atomic_helper_commit(dev, state, nonblock);
4950 /*TODO Handle EINTR, reenable IRQ*/
4954 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4955 * @state: The atomic state to commit
4957 * This will tell DC to commit the constructed DC state from atomic_check,
4958 * programming the hardware. Any failures here implies a hardware failure, since
4959 * atomic check should have filtered anything non-kosher.
4961 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4963 struct drm_device *dev = state->dev;
4964 struct amdgpu_device *adev = dev->dev_private;
4965 struct amdgpu_display_manager *dm = &adev->dm;
4966 struct dm_atomic_state *dm_state;
4967 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
4969 struct drm_crtc *crtc;
4970 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4971 unsigned long flags;
4972 bool wait_for_vblank = true;
4973 struct drm_connector *connector;
4974 struct drm_connector_state *old_con_state, *new_con_state;
4975 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4976 int crtc_disable_count = 0;
4978 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4980 dm_state = dm_atomic_get_new_state(state);
4981 if (dm_state && dm_state->context) {
4982 dc_state = dm_state->context;
4984 /* No state changes, retain current state. */
4985 dc_state_temp = dc_create_state();
4986 ASSERT(dc_state_temp);
4987 dc_state = dc_state_temp;
4988 dc_resource_state_copy_construct_current(dm->dc, dc_state);
4991 /* update changed items */
4992 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4993 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4995 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4996 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4999 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5000 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5001 "connectors_changed:%d\n",
5003 new_crtc_state->enable,
5004 new_crtc_state->active,
5005 new_crtc_state->planes_changed,
5006 new_crtc_state->mode_changed,
5007 new_crtc_state->active_changed,
5008 new_crtc_state->connectors_changed);
5010 /* Copy all transient state flags into dc state */
5011 if (dm_new_crtc_state->stream) {
5012 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5013 dm_new_crtc_state->stream);
5016 /* handles headless hotplug case, updating new_state and
5017 * aconnector as needed
5020 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
5022 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
5024 if (!dm_new_crtc_state->stream) {
5026 * this could happen because of issues with
5027 * userspace notifications delivery.
5028 * In this case userspace tries to set mode on
5029 * display which is disconnected in fact.
5030 * dc_sink is NULL in this case on aconnector.
5031 * We expect reset mode will come soon.
5033 * This can also happen when unplug is done
5034 * during resume sequence ended
5036 * In this case, we want to pretend we still
5037 * have a sink to keep the pipe running so that
5038 * hw state is consistent with the sw state
5040 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5041 __func__, acrtc->base.base.id);
5045 if (dm_old_crtc_state->stream)
5046 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5048 pm_runtime_get_noresume(dev->dev);
5050 acrtc->enabled = true;
5051 acrtc->hw_mode = new_crtc_state->mode;
5052 crtc->hwmode = new_crtc_state->mode;
5053 } else if (modereset_required(new_crtc_state)) {
5054 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
5056 /* i.e. reset mode */
5057 if (dm_old_crtc_state->stream)
5058 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5060 } /* for_each_crtc_in_state() */
5063 dm_enable_per_frame_crtc_master_sync(dc_state);
5064 mutex_lock(&dm->dc_lock);
5065 WARN_ON(!dc_commit_state(dm->dc, dc_state));
5066 mutex_unlock(&dm->dc_lock);
5069 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5070 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5072 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5074 if (dm_new_crtc_state->stream != NULL) {
5075 const struct dc_stream_status *status =
5076 dc_stream_get_status(dm_new_crtc_state->stream);
5079 status = dc_state_get_stream_status(dc_state,
5080 dm_new_crtc_state->stream);
5083 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
5085 acrtc->otg_inst = status->primary_otg_inst;
5089 /* Handle scaling, underscan, and abm changes*/
5090 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5091 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5092 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5093 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5094 struct dc_stream_status *status = NULL;
5097 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
5098 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5101 /* Skip any modesets/resets */
5102 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
5106 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5107 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5109 /* Skip anything that is not scaling or underscan changes */
5110 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5111 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5114 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5115 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
5117 if (!dm_new_crtc_state->stream)
5120 status = dc_stream_get_status(dm_new_crtc_state->stream);
5122 WARN_ON(!status->plane_count);
5124 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5126 /*TODO How it works with MPO ?*/
5127 if (!commit_planes_to_stream(
5130 status->plane_states,
5131 status->plane_count,
5133 to_dm_crtc_state(old_crtc_state),
5135 dm_error("%s: Failed to update stream scaling!\n", __func__);
5138 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5139 new_crtc_state, i) {
5141 * loop to enable interrupts on newly arrived crtc
5143 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5144 bool modeset_needed;
5146 if (old_crtc_state->active && !new_crtc_state->active)
5147 crtc_disable_count++;
5149 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5150 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5151 modeset_needed = modeset_required(
5153 dm_new_crtc_state->stream,
5154 dm_old_crtc_state->stream);
5156 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5159 manage_dm_interrupts(adev, acrtc, true);
5162 /* update planes when needed per crtc*/
5163 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
5164 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5166 if (dm_new_crtc_state->stream)
5167 amdgpu_dm_commit_planes(state, dc_state, dev,
5168 dm, crtc, &wait_for_vblank);
5173 * send vblank event on all events not handled in flip and
5174 * mark consumed event for drm_atomic_helper_commit_hw_done
5176 spin_lock_irqsave(&adev->ddev->event_lock, flags);
5177 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5179 if (new_crtc_state->event)
5180 drm_send_event_locked(dev, &new_crtc_state->event->base);
5182 new_crtc_state->event = NULL;
5184 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5187 if (wait_for_vblank)
5188 drm_atomic_helper_wait_for_flip_done(dev, state);
5192 * Delay hw_done() until flip_done() is signaled. This is to block
5193 * another commit from freeing the CRTC state while we're still
5194 * waiting on flip_done.
5196 drm_atomic_helper_commit_hw_done(state);
5198 drm_atomic_helper_cleanup_planes(dev, state);
5201 * Finally, drop a runtime PM reference for each newly disabled CRTC,
5202 * so we can put the GPU into runtime suspend if we're not driving any
5205 for (i = 0; i < crtc_disable_count; i++)
5206 pm_runtime_put_autosuspend(dev->dev);
5207 pm_runtime_mark_last_busy(dev->dev);
5210 dc_release_state(dc_state_temp);
5214 static int dm_force_atomic_commit(struct drm_connector *connector)
5217 struct drm_device *ddev = connector->dev;
5218 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5219 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5220 struct drm_plane *plane = disconnected_acrtc->base.primary;
5221 struct drm_connector_state *conn_state;
5222 struct drm_crtc_state *crtc_state;
5223 struct drm_plane_state *plane_state;
5228 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5230 /* Construct an atomic state to restore previous display setting */
5233 * Attach connectors to drm_atomic_state
5235 conn_state = drm_atomic_get_connector_state(state, connector);
5237 ret = PTR_ERR_OR_ZERO(conn_state);
5241 /* Attach crtc to drm_atomic_state*/
5242 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5244 ret = PTR_ERR_OR_ZERO(crtc_state);
5248 /* force a restore */
5249 crtc_state->mode_changed = true;
5251 /* Attach plane to drm_atomic_state */
5252 plane_state = drm_atomic_get_plane_state(state, plane);
5254 ret = PTR_ERR_OR_ZERO(plane_state);
5259 /* Call commit internally with the state we just constructed */
5260 ret = drm_atomic_commit(state);
5265 DRM_ERROR("Restoring old state failed with %i\n", ret);
5266 drm_atomic_state_put(state);
5272 * This function handles all cases when set mode does not come upon hotplug.
5273 * This includes when a display is unplugged then plugged back into the
5274 * same port and when running without usermode desktop manager supprot
5276 void dm_restore_drm_connector_state(struct drm_device *dev,
5277 struct drm_connector *connector)
5279 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5280 struct amdgpu_crtc *disconnected_acrtc;
5281 struct dm_crtc_state *acrtc_state;
5283 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5286 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5287 if (!disconnected_acrtc)
5290 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5291 if (!acrtc_state->stream)
5295 * If the previous sink is not released and different from the current,
5296 * we deduce we are in a state where we can not rely on usermode call
5297 * to turn on the display, so we do it here
5299 if (acrtc_state->stream->sink != aconnector->dc_sink)
5300 dm_force_atomic_commit(&aconnector->base);
5304 * Grabs all modesetting locks to serialize against any blocking commits,
5305 * Waits for completion of all non blocking commits.
5307 static int do_aquire_global_lock(struct drm_device *dev,
5308 struct drm_atomic_state *state)
5310 struct drm_crtc *crtc;
5311 struct drm_crtc_commit *commit;
5315 * Adding all modeset locks to aquire_ctx will
5316 * ensure that when the framework release it the
5317 * extra locks we are locking here will get released to
5319 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5323 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5324 spin_lock(&crtc->commit_lock);
5325 commit = list_first_entry_or_null(&crtc->commit_list,
5326 struct drm_crtc_commit, commit_entry);
5328 drm_crtc_commit_get(commit);
5329 spin_unlock(&crtc->commit_lock);
5335 * Make sure all pending HW programming completed and
5338 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5341 ret = wait_for_completion_interruptible_timeout(
5342 &commit->flip_done, 10*HZ);
5345 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
5346 "timed out\n", crtc->base.id, crtc->name);
5348 drm_crtc_commit_put(commit);
5351 return ret < 0 ? ret : 0;
5354 static void get_freesync_config_for_crtc(
5355 struct dm_crtc_state *new_crtc_state,
5356 struct dm_connector_state *new_con_state)
5358 struct mod_freesync_config config = {0};
5359 struct amdgpu_dm_connector *aconnector =
5360 to_amdgpu_dm_connector(new_con_state->base.connector);
5362 new_crtc_state->vrr_supported = new_con_state->freesync_capable;
5364 if (new_con_state->freesync_capable) {
5365 config.state = new_crtc_state->base.vrr_enabled ?
5366 VRR_STATE_ACTIVE_VARIABLE :
5368 config.min_refresh_in_uhz =
5369 aconnector->min_vfreq * 1000000;
5370 config.max_refresh_in_uhz =
5371 aconnector->max_vfreq * 1000000;
5372 config.vsif_supported = true;
5376 new_crtc_state->freesync_config = config;
5379 static void reset_freesync_config_for_crtc(
5380 struct dm_crtc_state *new_crtc_state)
5382 new_crtc_state->vrr_supported = false;
5384 memset(&new_crtc_state->vrr_params, 0,
5385 sizeof(new_crtc_state->vrr_params));
5386 memset(&new_crtc_state->vrr_infopacket, 0,
5387 sizeof(new_crtc_state->vrr_infopacket));
5390 static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
5391 struct drm_atomic_state *state,
5393 bool *lock_and_validation_needed)
5395 struct dm_atomic_state *dm_state = NULL;
5396 struct drm_crtc *crtc;
5397 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5399 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
5400 struct dc_stream_state *new_stream;
5404 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5405 * update changed items
5407 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5408 struct amdgpu_crtc *acrtc = NULL;
5409 struct amdgpu_dm_connector *aconnector = NULL;
5410 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5411 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5412 struct drm_plane_state *new_plane_state = NULL;
5416 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5417 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5418 acrtc = to_amdgpu_crtc(crtc);
5420 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
5422 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5427 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
5429 /* TODO This hack should go away */
5430 if (aconnector && enable) {
5431 /* Make sure fake sink is created in plug-in scenario */
5432 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5434 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5437 if (IS_ERR(drm_new_conn_state)) {
5438 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5442 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5443 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
5445 new_stream = create_stream_for_sink(aconnector,
5446 &new_crtc_state->mode,
5448 dm_old_crtc_state->stream);
5451 * we can have no stream on ACTION_SET if a display
5452 * was disconnected during S3, in this case it is not an
5453 * error, the OS will be updated after detection, and
5454 * will do the right thing on next atomic commit
5458 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5459 __func__, acrtc->base.base.id);
5463 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
5465 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5466 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5467 new_crtc_state->mode_changed = false;
5468 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5469 new_crtc_state->mode_changed);
5473 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5477 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5478 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5479 "connectors_changed:%d\n",
5481 new_crtc_state->enable,
5482 new_crtc_state->active,
5483 new_crtc_state->planes_changed,
5484 new_crtc_state->mode_changed,
5485 new_crtc_state->active_changed,
5486 new_crtc_state->connectors_changed);
5488 /* Remove stream for any changed/disabled CRTC */
5491 if (!dm_old_crtc_state->stream)
5494 ret = dm_atomic_get_state(state, &dm_state);
5498 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5501 /* i.e. reset mode */
5502 if (dc_remove_stream_from_ctx(
5505 dm_old_crtc_state->stream) != DC_OK) {
5510 dc_stream_release(dm_old_crtc_state->stream);
5511 dm_new_crtc_state->stream = NULL;
5513 reset_freesync_config_for_crtc(dm_new_crtc_state);
5515 *lock_and_validation_needed = true;
5517 } else {/* Add stream for any updated/enabled CRTC */
5519 * Quick fix to prevent NULL pointer on new_stream when
5520 * added MST connectors not found in existing crtc_state in the chained mode
5521 * TODO: need to dig out the root cause of that
5523 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5526 if (modereset_required(new_crtc_state))
5529 if (modeset_required(new_crtc_state, new_stream,
5530 dm_old_crtc_state->stream)) {
5532 WARN_ON(dm_new_crtc_state->stream);
5534 ret = dm_atomic_get_state(state, &dm_state);
5538 dm_new_crtc_state->stream = new_stream;
5540 dc_stream_retain(new_stream);
5542 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5545 if (dc_add_stream_to_ctx(
5548 dm_new_crtc_state->stream) != DC_OK) {
5553 *lock_and_validation_needed = true;
5558 /* Release extra reference */
5560 dc_stream_release(new_stream);
5563 * We want to do dc stream updates that do not require a
5564 * full modeset below.
5566 if (!(enable && aconnector && new_crtc_state->enable &&
5567 new_crtc_state->active))
5570 * Given above conditions, the dc state cannot be NULL because:
5571 * 1. We're in the process of enabling CRTCs (just been added
5572 * to the dc context, or already is on the context)
5573 * 2. Has a valid connector attached, and
5574 * 3. Is currently active and enabled.
5575 * => The dc stream state currently exists.
5577 BUG_ON(dm_new_crtc_state->stream == NULL);
5579 /* Scaling or underscan settings */
5580 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5581 update_stream_scaling_settings(
5582 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
5585 * Color management settings. We also update color properties
5586 * when a modeset is needed, to ensure it gets reprogrammed.
5588 if (dm_new_crtc_state->base.color_mgmt_changed ||
5589 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5590 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5593 amdgpu_dm_set_ctm(dm_new_crtc_state);
5596 /* Update Freesync settings. */
5597 get_freesync_config_for_crtc(dm_new_crtc_state,
5605 dc_stream_release(new_stream);
5609 static int dm_update_planes_state(struct dc *dc,
5610 struct drm_atomic_state *state,
5612 bool *lock_and_validation_needed)
5615 struct dm_atomic_state *dm_state = NULL;
5616 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5617 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5618 struct drm_plane *plane;
5619 struct drm_plane_state *old_plane_state, *new_plane_state;
5620 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
5621 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
5623 /* TODO return page_flip_needed() function */
5624 bool pflip_needed = !state->allow_modeset;
5628 /* Add new planes, in reverse order as DC expectation */
5629 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
5630 new_plane_crtc = new_plane_state->crtc;
5631 old_plane_crtc = old_plane_state->crtc;
5632 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5633 dm_old_plane_state = to_dm_plane_state(old_plane_state);
5635 /*TODO Implement atomic check for cursor plane */
5636 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5639 /* Remove any changed/removed planes */
5642 plane->type != DRM_PLANE_TYPE_OVERLAY)
5645 if (!old_plane_crtc)
5648 old_crtc_state = drm_atomic_get_old_crtc_state(
5649 state, old_plane_crtc);
5650 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5652 if (!dm_old_crtc_state->stream)
5655 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5656 plane->base.id, old_plane_crtc->base.id);
5658 ret = dm_atomic_get_state(state, &dm_state);
5662 if (!dc_remove_plane_from_context(
5664 dm_old_crtc_state->stream,
5665 dm_old_plane_state->dc_state,
5666 dm_state->context)) {
5673 dc_plane_state_release(dm_old_plane_state->dc_state);
5674 dm_new_plane_state->dc_state = NULL;
5676 *lock_and_validation_needed = true;
5678 } else { /* Add new planes */
5679 struct dc_plane_state *dc_new_plane_state;
5681 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5684 if (!new_plane_crtc)
5687 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5688 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5690 if (!dm_new_crtc_state->stream)
5694 plane->type != DRM_PLANE_TYPE_OVERLAY)
5697 WARN_ON(dm_new_plane_state->dc_state);
5699 dc_new_plane_state = dc_create_plane_state(dc);
5700 if (!dc_new_plane_state)
5703 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5704 plane->base.id, new_plane_crtc->base.id);
5706 ret = fill_plane_attributes(
5707 new_plane_crtc->dev->dev_private,
5712 dc_plane_state_release(dc_new_plane_state);
5716 ret = dm_atomic_get_state(state, &dm_state);
5718 dc_plane_state_release(dc_new_plane_state);
5723 * Any atomic check errors that occur after this will
5724 * not need a release. The plane state will be attached
5725 * to the stream, and therefore part of the atomic
5726 * state. It'll be released when the atomic state is
5729 if (!dc_add_plane_to_context(
5731 dm_new_crtc_state->stream,
5733 dm_state->context)) {
5735 dc_plane_state_release(dc_new_plane_state);
5739 dm_new_plane_state->dc_state = dc_new_plane_state;
5741 /* Tell DC to do a full surface update every time there
5742 * is a plane change. Inefficient, but works for now.
5744 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5746 *lock_and_validation_needed = true;
5755 dm_determine_update_type_for_commit(struct dc *dc,
5756 struct drm_atomic_state *state,
5757 enum surface_update_type *out_type)
5759 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5760 int i, j, num_plane, ret = 0;
5761 struct drm_plane_state *old_plane_state, *new_plane_state;
5762 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5763 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5764 struct drm_plane *plane;
5766 struct drm_crtc *crtc;
5767 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5768 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5769 struct dc_stream_status *status = NULL;
5771 struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL);
5772 struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);
5773 struct dc_stream_update stream_update;
5774 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5776 if (!updates || !surface) {
5777 DRM_ERROR("Plane or surface update failed to allocate");
5778 /* Set type to FULL to avoid crashing in DC*/
5779 update_type = UPDATE_TYPE_FULL;
5783 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5784 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5785 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5788 if (new_dm_crtc_state->stream) {
5790 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5791 new_plane_crtc = new_plane_state->crtc;
5792 old_plane_crtc = old_plane_state->crtc;
5793 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5794 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5796 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5799 if (!state->allow_modeset)
5802 if (crtc == new_plane_crtc) {
5803 updates[num_plane].surface = &surface[num_plane];
5805 if (new_crtc_state->mode_changed) {
5806 updates[num_plane].surface->src_rect =
5807 new_dm_plane_state->dc_state->src_rect;
5808 updates[num_plane].surface->dst_rect =
5809 new_dm_plane_state->dc_state->dst_rect;
5810 updates[num_plane].surface->rotation =
5811 new_dm_plane_state->dc_state->rotation;
5812 updates[num_plane].surface->in_transfer_func =
5813 new_dm_plane_state->dc_state->in_transfer_func;
5814 stream_update.dst = new_dm_crtc_state->stream->dst;
5815 stream_update.src = new_dm_crtc_state->stream->src;
5818 if (new_crtc_state->color_mgmt_changed) {
5819 updates[num_plane].gamma =
5820 new_dm_plane_state->dc_state->gamma_correction;
5821 updates[num_plane].in_transfer_func =
5822 new_dm_plane_state->dc_state->in_transfer_func;
5823 stream_update.gamut_remap =
5824 &new_dm_crtc_state->stream->gamut_remap_matrix;
5825 stream_update.out_transfer_func =
5826 new_dm_crtc_state->stream->out_transfer_func;
5833 if (num_plane > 0) {
5834 ret = dm_atomic_get_state(state, &dm_state);
5838 old_dm_state = dm_atomic_get_old_state(state);
5839 if (!old_dm_state) {
5844 status = dc_state_get_stream_status(old_dm_state->context,
5845 new_dm_crtc_state->stream);
5847 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5848 &stream_update, status);
5850 if (update_type > UPDATE_TYPE_MED) {
5851 update_type = UPDATE_TYPE_FULL;
5856 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5857 update_type = UPDATE_TYPE_FULL;
5866 *out_type = update_type;
5871 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5872 * @dev: The DRM device
5873 * @state: The atomic state to commit
5875 * Validate that the given atomic state is programmable by DC into hardware.
5876 * This involves constructing a &struct dc_state reflecting the new hardware
5877 * state we wish to commit, then querying DC to see if it is programmable. It's
5878 * important not to modify the existing DC state. Otherwise, atomic_check
5879 * may unexpectedly commit hardware changes.
5881 * When validating the DC state, it's important that the right locks are
5882 * acquired. For full updates case which removes/adds/updates streams on one
5883 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5884 * that any such full update commit will wait for completion of any outstanding
5885 * flip using DRMs synchronization events. See
5886 * dm_determine_update_type_for_commit()
5888 * Note that DM adds the affected connectors for all CRTCs in state, when that
5889 * might not seem necessary. This is because DC stream creation requires the
5890 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5891 * be possible but non-trivial - a possible TODO item.
5893 * Return: -Error code if validation failed.
5895 static int amdgpu_dm_atomic_check(struct drm_device *dev,
5896 struct drm_atomic_state *state)
5898 struct amdgpu_device *adev = dev->dev_private;
5899 struct dm_atomic_state *dm_state = NULL;
5900 struct dc *dc = adev->dm.dc;
5901 struct drm_connector *connector;
5902 struct drm_connector_state *old_con_state, *new_con_state;
5903 struct drm_crtc *crtc;
5904 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5905 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5906 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5911 * This bool will be set for true for any modeset/reset
5912 * or plane update which implies non fast surface update.
5914 bool lock_and_validation_needed = false;
5916 ret = drm_atomic_helper_check_modeset(dev, state);
5920 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5921 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
5922 !new_crtc_state->color_mgmt_changed &&
5923 !new_crtc_state->vrr_enabled)
5926 if (!new_crtc_state->enable)
5929 ret = drm_atomic_add_affected_connectors(state, crtc);
5933 ret = drm_atomic_add_affected_planes(state, crtc);
5938 /* Remove exiting planes if they are modified */
5939 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5944 /* Disable all crtcs which require disable */
5945 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
5950 /* Enable all crtcs which require enable */
5951 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
5956 /* Add new/modified planes */
5957 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5962 /* Run this here since we want to validate the streams we created */
5963 ret = drm_atomic_helper_check_planes(dev, state);
5967 /* Check scaling and underscan changes*/
5968 /* TODO Removed scaling changes validation due to inability to commit
5969 * new stream into context w\o causing full reset. Need to
5970 * decide how to handle.
5972 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5973 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5974 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5975 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5977 /* Skip any modesets/resets */
5978 if (!acrtc || drm_atomic_crtc_needs_modeset(
5979 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
5982 /* Skip any thing not scale or underscan changes */
5983 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
5986 overall_update_type = UPDATE_TYPE_FULL;
5987 lock_and_validation_needed = true;
5990 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
5994 if (overall_update_type < update_type)
5995 overall_update_type = update_type;
5998 * lock_and_validation_needed was an old way to determine if we need to set
5999 * the global lock. Leaving it in to check if we broke any corner cases
6000 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6001 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6003 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6004 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6005 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6006 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
6009 if (overall_update_type > UPDATE_TYPE_FAST) {
6010 ret = dm_atomic_get_state(state, &dm_state);
6014 ret = do_aquire_global_lock(dev, state);
6018 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
6022 } else if (state->legacy_cursor_update) {
6024 * This is a fast cursor update coming from the plane update
6025 * helper, check if it can be done asynchronously for better
6028 state->async_update = !drm_atomic_helper_async_check(dev, state);
6031 /* Must be success */
6036 if (ret == -EDEADLK)
6037 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
6038 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
6039 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
6041 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
6046 static bool is_dp_capable_without_timing_msa(struct dc *dc,
6047 struct amdgpu_dm_connector *amdgpu_dm_connector)
6050 bool capable = false;
6052 if (amdgpu_dm_connector->dc_link &&
6053 dm_helpers_dp_read_dpcd(
6055 amdgpu_dm_connector->dc_link,
6056 DP_DOWN_STREAM_PORT_COUNT,
6058 sizeof(dpcd_data))) {
6059 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6064 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6068 bool edid_check_required;
6069 struct detailed_timing *timing;
6070 struct detailed_non_pixel *data;
6071 struct detailed_data_monitor_range *range;
6072 struct amdgpu_dm_connector *amdgpu_dm_connector =
6073 to_amdgpu_dm_connector(connector);
6074 struct dm_connector_state *dm_con_state = NULL;
6076 struct drm_device *dev = connector->dev;
6077 struct amdgpu_device *adev = dev->dev_private;
6078 bool freesync_capable = false;
6080 if (!connector->state) {
6081 DRM_ERROR("%s - Connector has no state", __func__);
6086 dm_con_state = to_dm_connector_state(connector->state);
6088 amdgpu_dm_connector->min_vfreq = 0;
6089 amdgpu_dm_connector->max_vfreq = 0;
6090 amdgpu_dm_connector->pixel_clock_mhz = 0;
6095 dm_con_state = to_dm_connector_state(connector->state);
6097 edid_check_required = false;
6098 if (!amdgpu_dm_connector->dc_sink) {
6099 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
6102 if (!adev->dm.freesync_module)
6105 * if edid non zero restrict freesync only for dp and edp
6108 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6109 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
6110 edid_check_required = is_dp_capable_without_timing_msa(
6112 amdgpu_dm_connector);
6115 if (edid_check_required == true && (edid->version > 1 ||
6116 (edid->version == 1 && edid->revision > 1))) {
6117 for (i = 0; i < 4; i++) {
6119 timing = &edid->detailed_timings[i];
6120 data = &timing->data.other_data;
6121 range = &data->data.range;
6123 * Check if monitor has continuous frequency mode
6125 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6128 * Check for flag range limits only. If flag == 1 then
6129 * no additional timing information provided.
6130 * Default GTF, GTF Secondary curve and CVT are not
6133 if (range->flags != 1)
6136 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6137 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6138 amdgpu_dm_connector->pixel_clock_mhz =
6139 range->pixel_clock_mhz * 10;
6143 if (amdgpu_dm_connector->max_vfreq -
6144 amdgpu_dm_connector->min_vfreq > 10) {
6146 freesync_capable = true;
6152 dm_con_state->freesync_capable = freesync_capable;
6154 if (connector->vrr_capable_property)
6155 drm_connector_set_vrr_capable_property(connector,