2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
32 #include "dal_asic_id.h"
33 #include "dmub/dmub_srv.h"
34 #include "dc/inc/hw/dmcu.h"
35 #include "dc/inc/hw/abm.h"
36 #include "dc/dc_dmub_srv.h"
37 #include "dc/dc_edid_parser.h"
38 #include "amdgpu_dm_trace.h"
42 #include "amdgpu_display.h"
43 #include "amdgpu_ucode.h"
45 #include "amdgpu_dm.h"
46 #ifdef CONFIG_DRM_AMD_DC_HDCP
47 #include "amdgpu_dm_hdcp.h"
48 #include <drm/drm_hdcp.h>
50 #include "amdgpu_pm.h"
52 #include "amd_shared.h"
53 #include "amdgpu_dm_irq.h"
54 #include "dm_helpers.h"
55 #include "amdgpu_dm_mst_types.h"
56 #if defined(CONFIG_DEBUG_FS)
57 #include "amdgpu_dm_debugfs.h"
60 #include "ivsrcid/ivsrcid_vislands30.h"
62 #include <linux/module.h>
63 #include <linux/moduleparam.h>
64 #include <linux/types.h>
65 #include <linux/pm_runtime.h>
66 #include <linux/pci.h>
67 #include <linux/firmware.h>
68 #include <linux/component.h>
70 #include <drm/drm_atomic.h>
71 #include <drm/drm_atomic_uapi.h>
72 #include <drm/drm_atomic_helper.h>
73 #include <drm/drm_dp_mst_helper.h>
74 #include <drm/drm_fb_helper.h>
75 #include <drm/drm_fourcc.h>
76 #include <drm/drm_edid.h>
77 #include <drm/drm_vblank.h>
78 #include <drm/drm_audio_component.h>
80 #if defined(CONFIG_DRM_AMD_DC_DCN)
81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
83 #include "dcn/dcn_1_0_offset.h"
84 #include "dcn/dcn_1_0_sh_mask.h"
85 #include "soc15_hw_ip.h"
86 #include "vega10_ip_offset.h"
88 #include "soc15_common.h"
91 #include "modules/inc/mod_freesync.h"
92 #include "modules/power/power_helpers.h"
93 #include "modules/inc/mod_info_packet.h"
95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
97 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
98 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
99 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
100 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
101 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
102 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
103 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
104 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
105 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
106 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
108 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
109 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
111 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
112 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
114 /* Number of bytes in PSP header for firmware. */
115 #define PSP_HEADER_BYTES 0x100
117 /* Number of bytes in PSP footer for firmware. */
118 #define PSP_FOOTER_BYTES 0x100
123 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
124 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
125 * requests into DC requests, and DC responses into DRM responses.
127 * The root control structure is &struct amdgpu_display_manager.
130 /* basic init/fini API */
131 static int amdgpu_dm_init(struct amdgpu_device *adev);
132 static void amdgpu_dm_fini(struct amdgpu_device *adev);
133 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
135 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
137 switch (link->dpcd_caps.dongle_type) {
138 case DISPLAY_DONGLE_NONE:
139 return DRM_MODE_SUBCONNECTOR_Native;
140 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
141 return DRM_MODE_SUBCONNECTOR_VGA;
142 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
143 case DISPLAY_DONGLE_DP_DVI_DONGLE:
144 return DRM_MODE_SUBCONNECTOR_DVID;
145 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
146 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
147 return DRM_MODE_SUBCONNECTOR_HDMIA;
148 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
150 return DRM_MODE_SUBCONNECTOR_Unknown;
154 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
156 struct dc_link *link = aconnector->dc_link;
157 struct drm_connector *connector = &aconnector->base;
158 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
160 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
163 if (aconnector->dc_sink)
164 subconnector = get_subconnector_type(link);
166 drm_object_property_set_value(&connector->base,
167 connector->dev->mode_config.dp_subconnector_property,
172 * initializes drm_device display related structures, based on the information
173 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
174 * drm_encoder, drm_mode_config
176 * Returns 0 on success
178 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
179 /* removes and deallocates the drm structures, created by the above function */
180 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
182 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
183 struct drm_plane *plane,
184 unsigned long possible_crtcs,
185 const struct dc_plane_cap *plane_cap);
186 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
187 struct drm_plane *plane,
188 uint32_t link_index);
189 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
190 struct amdgpu_dm_connector *amdgpu_dm_connector,
192 struct amdgpu_encoder *amdgpu_encoder);
193 static int amdgpu_dm_encoder_init(struct drm_device *dev,
194 struct amdgpu_encoder *aencoder,
195 uint32_t link_index);
197 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
199 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
201 static int amdgpu_dm_atomic_check(struct drm_device *dev,
202 struct drm_atomic_state *state);
204 static void handle_cursor_update(struct drm_plane *plane,
205 struct drm_plane_state *old_plane_state);
207 static void amdgpu_dm_set_psr_caps(struct dc_link *link);
208 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
209 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
210 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
211 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
213 static const struct drm_format_info *
214 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
217 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
218 struct drm_crtc_state *new_crtc_state);
220 * dm_vblank_get_counter
223 * Get counter for number of vertical blanks
226 * struct amdgpu_device *adev - [in] desired amdgpu device
227 * int disp_idx - [in] which CRTC to get the counter from
230 * Counter for vertical blanks
232 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
234 if (crtc >= adev->mode_info.num_crtc)
237 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
239 if (acrtc->dm_irq_params.stream == NULL) {
240 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
245 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
249 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
250 u32 *vbl, u32 *position)
252 uint32_t v_blank_start, v_blank_end, h_position, v_position;
254 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
257 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
259 if (acrtc->dm_irq_params.stream == NULL) {
260 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
266 * TODO rework base driver to use values directly.
267 * for now parse it back into reg-format
269 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
275 *position = v_position | (h_position << 16);
276 *vbl = v_blank_start | (v_blank_end << 16);
282 static bool dm_is_idle(void *handle)
288 static int dm_wait_for_idle(void *handle)
294 static bool dm_check_soft_reset(void *handle)
299 static int dm_soft_reset(void *handle)
305 static struct amdgpu_crtc *
306 get_crtc_by_otg_inst(struct amdgpu_device *adev,
309 struct drm_device *dev = adev_to_drm(adev);
310 struct drm_crtc *crtc;
311 struct amdgpu_crtc *amdgpu_crtc;
313 if (otg_inst == -1) {
315 return adev->mode_info.crtcs[0];
318 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
319 amdgpu_crtc = to_amdgpu_crtc(crtc);
321 if (amdgpu_crtc->otg_inst == otg_inst)
328 static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
330 return acrtc->dm_irq_params.freesync_config.state ==
331 VRR_STATE_ACTIVE_VARIABLE ||
332 acrtc->dm_irq_params.freesync_config.state ==
333 VRR_STATE_ACTIVE_FIXED;
336 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
338 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
339 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
342 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
343 struct dm_crtc_state *new_state)
345 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
347 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
354 * dm_pflip_high_irq() - Handle pageflip interrupt
355 * @interrupt_params: ignored
357 * Handles the pageflip interrupt by notifying all interested parties
358 * that the pageflip has been completed.
360 static void dm_pflip_high_irq(void *interrupt_params)
362 struct amdgpu_crtc *amdgpu_crtc;
363 struct common_irq_params *irq_params = interrupt_params;
364 struct amdgpu_device *adev = irq_params->adev;
366 struct drm_pending_vblank_event *e;
367 uint32_t vpos, hpos, v_blank_start, v_blank_end;
370 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
372 /* IRQ could occur when in initial stage */
373 /* TODO work and BO cleanup */
374 if (amdgpu_crtc == NULL) {
375 DC_LOG_PFLIP("CRTC is null, returning.\n");
379 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
381 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
382 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
383 amdgpu_crtc->pflip_status,
384 AMDGPU_FLIP_SUBMITTED,
385 amdgpu_crtc->crtc_id,
387 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
391 /* page flip completed. */
392 e = amdgpu_crtc->event;
393 amdgpu_crtc->event = NULL;
398 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
400 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
402 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
403 &v_blank_end, &hpos, &vpos) ||
404 (vpos < v_blank_start)) {
405 /* Update to correct count and vblank timestamp if racing with
406 * vblank irq. This also updates to the correct vblank timestamp
407 * even in VRR mode, as scanout is past the front-porch atm.
409 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
411 /* Wake up userspace by sending the pageflip event with proper
412 * count and timestamp of vblank of flip completion.
415 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
417 /* Event sent, so done with vblank for this flip */
418 drm_crtc_vblank_put(&amdgpu_crtc->base);
421 /* VRR active and inside front-porch: vblank count and
422 * timestamp for pageflip event will only be up to date after
423 * drm_crtc_handle_vblank() has been executed from late vblank
424 * irq handler after start of back-porch (vline 0). We queue the
425 * pageflip event for send-out by drm_crtc_handle_vblank() with
426 * updated timestamp and count, once it runs after us.
428 * We need to open-code this instead of using the helper
429 * drm_crtc_arm_vblank_event(), as that helper would
430 * call drm_crtc_accurate_vblank_count(), which we must
431 * not call in VRR mode while we are in front-porch!
434 /* sequence will be replaced by real count during send-out. */
435 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
436 e->pipe = amdgpu_crtc->crtc_id;
438 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
442 /* Keep track of vblank of this flip for flip throttling. We use the
443 * cooked hw counter, as that one incremented at start of this vblank
444 * of pageflip completion, so last_flip_vblank is the forbidden count
445 * for queueing new pageflips if vsync + VRR is enabled.
447 amdgpu_crtc->dm_irq_params.last_flip_vblank =
448 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
450 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
451 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
453 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
454 amdgpu_crtc->crtc_id, amdgpu_crtc,
455 vrr_active, (int) !e);
458 static void dm_vupdate_high_irq(void *interrupt_params)
460 struct common_irq_params *irq_params = interrupt_params;
461 struct amdgpu_device *adev = irq_params->adev;
462 struct amdgpu_crtc *acrtc;
463 struct drm_device *drm_dev;
464 struct drm_vblank_crtc *vblank;
465 ktime_t frame_duration_ns, previous_timestamp;
469 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
472 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
473 drm_dev = acrtc->base.dev;
474 vblank = &drm_dev->vblank[acrtc->base.index];
475 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
476 frame_duration_ns = vblank->time - previous_timestamp;
478 if (frame_duration_ns > 0) {
479 trace_amdgpu_refresh_rate_track(acrtc->base.index,
481 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
482 atomic64_set(&irq_params->previous_timestamp, vblank->time);
485 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
489 /* Core vblank handling is done here after end of front-porch in
490 * vrr mode, as vblank timestamping will give valid results
491 * while now done after front-porch. This will also deliver
492 * page-flip completion events that have been queued to us
493 * if a pageflip happened inside front-porch.
496 drm_crtc_handle_vblank(&acrtc->base);
498 /* BTR processing for pre-DCE12 ASICs */
499 if (acrtc->dm_irq_params.stream &&
500 adev->family < AMDGPU_FAMILY_AI) {
501 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
502 mod_freesync_handle_v_update(
503 adev->dm.freesync_module,
504 acrtc->dm_irq_params.stream,
505 &acrtc->dm_irq_params.vrr_params);
507 dc_stream_adjust_vmin_vmax(
509 acrtc->dm_irq_params.stream,
510 &acrtc->dm_irq_params.vrr_params.adjust);
511 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
518 * dm_crtc_high_irq() - Handles CRTC interrupt
519 * @interrupt_params: used for determining the CRTC instance
521 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
524 static void dm_crtc_high_irq(void *interrupt_params)
526 struct common_irq_params *irq_params = interrupt_params;
527 struct amdgpu_device *adev = irq_params->adev;
528 struct amdgpu_crtc *acrtc;
532 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
536 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
538 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
539 vrr_active, acrtc->dm_irq_params.active_planes);
542 * Core vblank handling at start of front-porch is only possible
543 * in non-vrr mode, as only there vblank timestamping will give
544 * valid results while done in front-porch. Otherwise defer it
545 * to dm_vupdate_high_irq after end of front-porch.
548 drm_crtc_handle_vblank(&acrtc->base);
551 * Following stuff must happen at start of vblank, for crc
552 * computation and below-the-range btr support in vrr mode.
554 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
556 /* BTR updates need to happen before VUPDATE on Vega and above. */
557 if (adev->family < AMDGPU_FAMILY_AI)
560 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
562 if (acrtc->dm_irq_params.stream &&
563 acrtc->dm_irq_params.vrr_params.supported &&
564 acrtc->dm_irq_params.freesync_config.state ==
565 VRR_STATE_ACTIVE_VARIABLE) {
566 mod_freesync_handle_v_update(adev->dm.freesync_module,
567 acrtc->dm_irq_params.stream,
568 &acrtc->dm_irq_params.vrr_params);
570 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
571 &acrtc->dm_irq_params.vrr_params.adjust);
575 * If there aren't any active_planes then DCH HUBP may be clock-gated.
576 * In that case, pageflip completion interrupts won't fire and pageflip
577 * completion events won't get delivered. Prevent this by sending
578 * pending pageflip events from here if a flip is still pending.
580 * If any planes are enabled, use dm_pflip_high_irq() instead, to
581 * avoid race conditions between flip programming and completion,
582 * which could cause too early flip completion events.
584 if (adev->family >= AMDGPU_FAMILY_RV &&
585 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
586 acrtc->dm_irq_params.active_planes == 0) {
588 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
590 drm_crtc_vblank_put(&acrtc->base);
592 acrtc->pflip_status = AMDGPU_FLIP_NONE;
595 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
598 #if defined(CONFIG_DRM_AMD_DC_DCN)
600 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
601 * DCN generation ASICs
602 * @interrupt params - interrupt parameters
604 * Used to set crc window/read out crc value at vertical line 0 position
606 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
607 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
609 struct common_irq_params *irq_params = interrupt_params;
610 struct amdgpu_device *adev = irq_params->adev;
611 struct amdgpu_crtc *acrtc;
613 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
618 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
623 static int dm_set_clockgating_state(void *handle,
624 enum amd_clockgating_state state)
629 static int dm_set_powergating_state(void *handle,
630 enum amd_powergating_state state)
635 /* Prototypes of private functions */
636 static int dm_early_init(void* handle);
638 /* Allocate memory for FBC compressed data */
639 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
641 struct drm_device *dev = connector->dev;
642 struct amdgpu_device *adev = drm_to_adev(dev);
643 struct dm_compressor_info *compressor = &adev->dm.compressor;
644 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
645 struct drm_display_mode *mode;
646 unsigned long max_size = 0;
648 if (adev->dm.dc->fbc_compressor == NULL)
651 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
654 if (compressor->bo_ptr)
658 list_for_each_entry(mode, &connector->modes, head) {
659 if (max_size < mode->htotal * mode->vtotal)
660 max_size = mode->htotal * mode->vtotal;
664 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
665 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
666 &compressor->gpu_addr, &compressor->cpu_addr);
669 DRM_ERROR("DM: Failed to initialize FBC\n");
671 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
672 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
679 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
680 int pipe, bool *enabled,
681 unsigned char *buf, int max_bytes)
683 struct drm_device *dev = dev_get_drvdata(kdev);
684 struct amdgpu_device *adev = drm_to_adev(dev);
685 struct drm_connector *connector;
686 struct drm_connector_list_iter conn_iter;
687 struct amdgpu_dm_connector *aconnector;
692 mutex_lock(&adev->dm.audio_lock);
694 drm_connector_list_iter_begin(dev, &conn_iter);
695 drm_for_each_connector_iter(connector, &conn_iter) {
696 aconnector = to_amdgpu_dm_connector(connector);
697 if (aconnector->audio_inst != port)
701 ret = drm_eld_size(connector->eld);
702 memcpy(buf, connector->eld, min(max_bytes, ret));
706 drm_connector_list_iter_end(&conn_iter);
708 mutex_unlock(&adev->dm.audio_lock);
710 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
715 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
716 .get_eld = amdgpu_dm_audio_component_get_eld,
719 static int amdgpu_dm_audio_component_bind(struct device *kdev,
720 struct device *hda_kdev, void *data)
722 struct drm_device *dev = dev_get_drvdata(kdev);
723 struct amdgpu_device *adev = drm_to_adev(dev);
724 struct drm_audio_component *acomp = data;
726 acomp->ops = &amdgpu_dm_audio_component_ops;
728 adev->dm.audio_component = acomp;
733 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
734 struct device *hda_kdev, void *data)
736 struct drm_device *dev = dev_get_drvdata(kdev);
737 struct amdgpu_device *adev = drm_to_adev(dev);
738 struct drm_audio_component *acomp = data;
742 adev->dm.audio_component = NULL;
745 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
746 .bind = amdgpu_dm_audio_component_bind,
747 .unbind = amdgpu_dm_audio_component_unbind,
750 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
757 adev->mode_info.audio.enabled = true;
759 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
761 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
762 adev->mode_info.audio.pin[i].channels = -1;
763 adev->mode_info.audio.pin[i].rate = -1;
764 adev->mode_info.audio.pin[i].bits_per_sample = -1;
765 adev->mode_info.audio.pin[i].status_bits = 0;
766 adev->mode_info.audio.pin[i].category_code = 0;
767 adev->mode_info.audio.pin[i].connected = false;
768 adev->mode_info.audio.pin[i].id =
769 adev->dm.dc->res_pool->audios[i]->inst;
770 adev->mode_info.audio.pin[i].offset = 0;
773 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
777 adev->dm.audio_registered = true;
782 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
787 if (!adev->mode_info.audio.enabled)
790 if (adev->dm.audio_registered) {
791 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
792 adev->dm.audio_registered = false;
795 /* TODO: Disable audio? */
797 adev->mode_info.audio.enabled = false;
800 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
802 struct drm_audio_component *acomp = adev->dm.audio_component;
804 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
805 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
807 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
812 static int dm_dmub_hw_init(struct amdgpu_device *adev)
814 const struct dmcub_firmware_header_v1_0 *hdr;
815 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
816 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
817 const struct firmware *dmub_fw = adev->dm.dmub_fw;
818 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
819 struct abm *abm = adev->dm.dc->res_pool->abm;
820 struct dmub_srv_hw_params hw_params;
821 enum dmub_status status;
822 const unsigned char *fw_inst_const, *fw_bss_data;
823 uint32_t i, fw_inst_const_size, fw_bss_data_size;
827 /* DMUB isn't supported on the ASIC. */
831 DRM_ERROR("No framebuffer info for DMUB service.\n");
836 /* Firmware required for DMUB support. */
837 DRM_ERROR("No firmware provided for DMUB.\n");
841 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
842 if (status != DMUB_STATUS_OK) {
843 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
847 if (!has_hw_support) {
848 DRM_INFO("DMUB unsupported on ASIC\n");
852 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
854 fw_inst_const = dmub_fw->data +
855 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
858 fw_bss_data = dmub_fw->data +
859 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
860 le32_to_cpu(hdr->inst_const_bytes);
862 /* Copy firmware and bios info into FB memory. */
863 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
864 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
866 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
868 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
869 * amdgpu_ucode_init_single_fw will load dmub firmware
870 * fw_inst_const part to cw0; otherwise, the firmware back door load
871 * will be done by dm_dmub_hw_init
873 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
874 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
878 if (fw_bss_data_size)
879 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
880 fw_bss_data, fw_bss_data_size);
882 /* Copy firmware bios info into FB memory. */
883 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
886 /* Reset regions that need to be reset. */
887 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
888 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
890 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
891 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
893 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
894 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
896 /* Initialize hardware. */
897 memset(&hw_params, 0, sizeof(hw_params));
898 hw_params.fb_base = adev->gmc.fb_start;
899 hw_params.fb_offset = adev->gmc.aper_base;
901 /* backdoor load firmware and trigger dmub running */
902 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
903 hw_params.load_inst_const = true;
906 hw_params.psp_version = dmcu->psp_version;
908 for (i = 0; i < fb_info->num_fb; ++i)
909 hw_params.fb[i] = &fb_info->fb[i];
911 status = dmub_srv_hw_init(dmub_srv, &hw_params);
912 if (status != DMUB_STATUS_OK) {
913 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
917 /* Wait for firmware load to finish. */
918 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
919 if (status != DMUB_STATUS_OK)
920 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
922 /* Init DMCU and ABM if available. */
924 dmcu->funcs->dmcu_init(dmcu);
925 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
928 if (!adev->dm.dc->ctx->dmub_srv)
929 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
930 if (!adev->dm.dc->ctx->dmub_srv) {
931 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
935 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
936 adev->dm.dmcub_fw_version);
941 #if defined(CONFIG_DRM_AMD_DC_DCN)
942 #define DMUB_TRACE_MAX_READ 64
943 static void dm_dmub_trace_high_irq(void *interrupt_params)
945 struct common_irq_params *irq_params = interrupt_params;
946 struct amdgpu_device *adev = irq_params->adev;
947 struct amdgpu_display_manager *dm = &adev->dm;
948 struct dmcub_trace_buf_entry entry = { 0 };
952 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
953 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
954 entry.param0, entry.param1);
956 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
957 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
963 } while (count <= DMUB_TRACE_MAX_READ);
965 ASSERT(count <= DMUB_TRACE_MAX_READ);
968 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
971 uint32_t logical_addr_low;
972 uint32_t logical_addr_high;
973 uint32_t agp_base, agp_bot, agp_top;
974 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
976 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
977 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
979 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
981 * Raven2 has a HW issue that it is unable to use the vram which
982 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
983 * workaround that increase system aperture high address (add 1)
984 * to get rid of the VM fault and hardware hang.
986 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
988 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
991 agp_bot = adev->gmc.agp_start >> 24;
992 agp_top = adev->gmc.agp_end >> 24;
995 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
996 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
997 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
998 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
999 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1000 page_table_base.low_part = lower_32_bits(pt_base);
1002 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1003 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1005 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1006 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1007 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1009 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1010 pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
1011 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1013 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1014 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1015 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1017 pa_config->is_hvm_enabled = 0;
1021 #if defined(CONFIG_DRM_AMD_DC_DCN)
1022 static void event_mall_stutter(struct work_struct *work)
1025 struct vblank_workqueue *vblank_work = container_of(work, struct vblank_workqueue, mall_work);
1026 struct amdgpu_display_manager *dm = vblank_work->dm;
1028 mutex_lock(&dm->dc_lock);
1030 if (vblank_work->enable)
1031 dm->active_vblank_irq_count++;
1032 else if(dm->active_vblank_irq_count)
1033 dm->active_vblank_irq_count--;
1035 dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
1037 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
1039 mutex_unlock(&dm->dc_lock);
1042 static struct vblank_workqueue *vblank_create_workqueue(struct amdgpu_device *adev, struct dc *dc)
1045 int max_caps = dc->caps.max_links;
1046 struct vblank_workqueue *vblank_work;
1049 vblank_work = kcalloc(max_caps, sizeof(*vblank_work), GFP_KERNEL);
1050 if (ZERO_OR_NULL_PTR(vblank_work)) {
1055 for (i = 0; i < max_caps; i++)
1056 INIT_WORK(&vblank_work[i].mall_work, event_mall_stutter);
1061 static int amdgpu_dm_init(struct amdgpu_device *adev)
1063 struct dc_init_data init_data;
1064 #ifdef CONFIG_DRM_AMD_DC_HDCP
1065 struct dc_callback_init init_params;
1069 adev->dm.ddev = adev_to_drm(adev);
1070 adev->dm.adev = adev;
1072 /* Zero all the fields */
1073 memset(&init_data, 0, sizeof(init_data));
1074 #ifdef CONFIG_DRM_AMD_DC_HDCP
1075 memset(&init_params, 0, sizeof(init_params));
1078 mutex_init(&adev->dm.dc_lock);
1079 mutex_init(&adev->dm.audio_lock);
1080 #if defined(CONFIG_DRM_AMD_DC_DCN)
1081 spin_lock_init(&adev->dm.vblank_lock);
1084 if(amdgpu_dm_irq_init(adev)) {
1085 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1089 init_data.asic_id.chip_family = adev->family;
1091 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1092 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1094 init_data.asic_id.vram_width = adev->gmc.vram_width;
1095 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1096 init_data.asic_id.atombios_base_address =
1097 adev->mode_info.atom_context->bios;
1099 init_data.driver = adev;
1101 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1103 if (!adev->dm.cgs_device) {
1104 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1108 init_data.cgs_device = adev->dm.cgs_device;
1110 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1112 switch (adev->asic_type) {
1117 init_data.flags.gpu_vm_support = true;
1118 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1119 init_data.flags.disable_dmcu = true;
1121 #if defined(CONFIG_DRM_AMD_DC_DCN)
1123 init_data.flags.gpu_vm_support = true;
1130 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1131 init_data.flags.fbc_support = true;
1133 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1134 init_data.flags.multi_mon_pp_mclk_switch = true;
1136 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1137 init_data.flags.disable_fractional_pwm = true;
1139 init_data.flags.power_down_display_on_boot = true;
1141 INIT_LIST_HEAD(&adev->dm.da_list);
1142 /* Display Core create. */
1143 adev->dm.dc = dc_create(&init_data);
1146 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1148 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1152 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1153 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1154 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1157 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1158 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1160 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1161 adev->dm.dc->debug.disable_stutter = true;
1163 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1164 adev->dm.dc->debug.disable_dsc = true;
1166 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1167 adev->dm.dc->debug.disable_clock_gate = true;
1169 r = dm_dmub_hw_init(adev);
1171 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1175 dc_hardware_init(adev->dm.dc);
1177 #if defined(CONFIG_DRM_AMD_DC_DCN)
1178 if (adev->apu_flags) {
1179 struct dc_phy_addr_space_config pa_config;
1181 mmhub_read_system_context(adev, &pa_config);
1183 // Call the DC init_memory func
1184 dc_setup_system_context(adev->dm.dc, &pa_config);
1188 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1189 if (!adev->dm.freesync_module) {
1191 "amdgpu: failed to initialize freesync_module.\n");
1193 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1194 adev->dm.freesync_module);
1196 amdgpu_dm_init_color_mod();
1198 #if defined(CONFIG_DRM_AMD_DC_DCN)
1199 if (adev->dm.dc->caps.max_links > 0) {
1200 adev->dm.vblank_workqueue = vblank_create_workqueue(adev, adev->dm.dc);
1202 if (!adev->dm.vblank_workqueue)
1203 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1205 DRM_DEBUG_DRIVER("amdgpu: vblank_workqueue init done %p.\n", adev->dm.vblank_workqueue);
1209 #ifdef CONFIG_DRM_AMD_DC_HDCP
1210 if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
1211 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1213 if (!adev->dm.hdcp_workqueue)
1214 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1216 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1218 dc_init_callbacks(adev->dm.dc, &init_params);
1221 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1222 adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1224 if (amdgpu_dm_initialize_drm_device(adev)) {
1226 "amdgpu: failed to initialize sw for display support.\n");
1230 /* create fake encoders for MST */
1231 dm_dp_create_fake_mst_encoders(adev);
1233 /* TODO: Add_display_info? */
1235 /* TODO use dynamic cursor width */
1236 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1237 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1239 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1241 "amdgpu: failed to initialize sw for display support.\n");
1246 DRM_DEBUG_DRIVER("KMS initialized.\n");
1250 amdgpu_dm_fini(adev);
1255 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1259 for (i = 0; i < adev->dm.display_indexes_num; i++) {
1260 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1263 amdgpu_dm_audio_fini(adev);
1265 amdgpu_dm_destroy_drm_device(&adev->dm);
1267 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1268 if (adev->dm.crc_rd_wrk) {
1269 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1270 kfree(adev->dm.crc_rd_wrk);
1271 adev->dm.crc_rd_wrk = NULL;
1274 #ifdef CONFIG_DRM_AMD_DC_HDCP
1275 if (adev->dm.hdcp_workqueue) {
1276 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1277 adev->dm.hdcp_workqueue = NULL;
1281 dc_deinit_callbacks(adev->dm.dc);
1284 #if defined(CONFIG_DRM_AMD_DC_DCN)
1285 if (adev->dm.vblank_workqueue) {
1286 adev->dm.vblank_workqueue->dm = NULL;
1287 kfree(adev->dm.vblank_workqueue);
1288 adev->dm.vblank_workqueue = NULL;
1292 if (adev->dm.dc->ctx->dmub_srv) {
1293 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1294 adev->dm.dc->ctx->dmub_srv = NULL;
1297 if (adev->dm.dmub_bo)
1298 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1299 &adev->dm.dmub_bo_gpu_addr,
1300 &adev->dm.dmub_bo_cpu_addr);
1302 /* DC Destroy TODO: Replace destroy DAL */
1304 dc_destroy(&adev->dm.dc);
1306 * TODO: pageflip, vlank interrupt
1308 * amdgpu_dm_irq_fini(adev);
1311 if (adev->dm.cgs_device) {
1312 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1313 adev->dm.cgs_device = NULL;
1315 if (adev->dm.freesync_module) {
1316 mod_freesync_destroy(adev->dm.freesync_module);
1317 adev->dm.freesync_module = NULL;
1320 mutex_destroy(&adev->dm.audio_lock);
1321 mutex_destroy(&adev->dm.dc_lock);
1326 static int load_dmcu_fw(struct amdgpu_device *adev)
1328 const char *fw_name_dmcu = NULL;
1330 const struct dmcu_firmware_header_v1_0 *hdr;
1332 switch(adev->asic_type) {
1333 #if defined(CONFIG_DRM_AMD_DC_SI)
1348 case CHIP_POLARIS11:
1349 case CHIP_POLARIS10:
1350 case CHIP_POLARIS12:
1358 case CHIP_SIENNA_CICHLID:
1359 case CHIP_NAVY_FLOUNDER:
1360 case CHIP_DIMGREY_CAVEFISH:
1364 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1367 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1368 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1369 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1370 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1375 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1379 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1380 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1384 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1386 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1387 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1388 adev->dm.fw_dmcu = NULL;
1392 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1397 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1399 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1401 release_firmware(adev->dm.fw_dmcu);
1402 adev->dm.fw_dmcu = NULL;
1406 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1407 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1408 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1409 adev->firmware.fw_size +=
1410 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1412 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1413 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1414 adev->firmware.fw_size +=
1415 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1417 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1419 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1424 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1426 struct amdgpu_device *adev = ctx;
1428 return dm_read_reg(adev->dm.dc->ctx, address);
1431 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1434 struct amdgpu_device *adev = ctx;
1436 return dm_write_reg(adev->dm.dc->ctx, address, value);
1439 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1441 struct dmub_srv_create_params create_params;
1442 struct dmub_srv_region_params region_params;
1443 struct dmub_srv_region_info region_info;
1444 struct dmub_srv_fb_params fb_params;
1445 struct dmub_srv_fb_info *fb_info;
1446 struct dmub_srv *dmub_srv;
1447 const struct dmcub_firmware_header_v1_0 *hdr;
1448 const char *fw_name_dmub;
1449 enum dmub_asic dmub_asic;
1450 enum dmub_status status;
1453 switch (adev->asic_type) {
1455 dmub_asic = DMUB_ASIC_DCN21;
1456 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1457 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1458 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1460 case CHIP_SIENNA_CICHLID:
1461 dmub_asic = DMUB_ASIC_DCN30;
1462 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1464 case CHIP_NAVY_FLOUNDER:
1465 dmub_asic = DMUB_ASIC_DCN30;
1466 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1469 dmub_asic = DMUB_ASIC_DCN301;
1470 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1472 case CHIP_DIMGREY_CAVEFISH:
1473 dmub_asic = DMUB_ASIC_DCN302;
1474 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1478 /* ASIC doesn't support DMUB. */
1482 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1484 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1488 r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1490 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1494 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1496 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1497 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1498 AMDGPU_UCODE_ID_DMCUB;
1499 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1501 adev->firmware.fw_size +=
1502 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1504 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1505 adev->dm.dmcub_fw_version);
1508 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1510 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1511 dmub_srv = adev->dm.dmub_srv;
1514 DRM_ERROR("Failed to allocate DMUB service!\n");
1518 memset(&create_params, 0, sizeof(create_params));
1519 create_params.user_ctx = adev;
1520 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1521 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1522 create_params.asic = dmub_asic;
1524 /* Create the DMUB service. */
1525 status = dmub_srv_create(dmub_srv, &create_params);
1526 if (status != DMUB_STATUS_OK) {
1527 DRM_ERROR("Error creating DMUB service: %d\n", status);
1531 /* Calculate the size of all the regions for the DMUB service. */
1532 memset(®ion_params, 0, sizeof(region_params));
1534 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1535 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1536 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1537 region_params.vbios_size = adev->bios_size;
1538 region_params.fw_bss_data = region_params.bss_data_size ?
1539 adev->dm.dmub_fw->data +
1540 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1541 le32_to_cpu(hdr->inst_const_bytes) : NULL;
1542 region_params.fw_inst_const =
1543 adev->dm.dmub_fw->data +
1544 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1547 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
1550 if (status != DMUB_STATUS_OK) {
1551 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1556 * Allocate a framebuffer based on the total size of all the regions.
1557 * TODO: Move this into GART.
1559 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1560 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1561 &adev->dm.dmub_bo_gpu_addr,
1562 &adev->dm.dmub_bo_cpu_addr);
1566 /* Rebase the regions on the framebuffer address. */
1567 memset(&fb_params, 0, sizeof(fb_params));
1568 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1569 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1570 fb_params.region_info = ®ion_info;
1572 adev->dm.dmub_fb_info =
1573 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1574 fb_info = adev->dm.dmub_fb_info;
1578 "Failed to allocate framebuffer info for DMUB service!\n");
1582 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1583 if (status != DMUB_STATUS_OK) {
1584 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1591 static int dm_sw_init(void *handle)
1593 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1596 r = dm_dmub_sw_init(adev);
1600 return load_dmcu_fw(adev);
1603 static int dm_sw_fini(void *handle)
1605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1607 kfree(adev->dm.dmub_fb_info);
1608 adev->dm.dmub_fb_info = NULL;
1610 if (adev->dm.dmub_srv) {
1611 dmub_srv_destroy(adev->dm.dmub_srv);
1612 adev->dm.dmub_srv = NULL;
1615 release_firmware(adev->dm.dmub_fw);
1616 adev->dm.dmub_fw = NULL;
1618 release_firmware(adev->dm.fw_dmcu);
1619 adev->dm.fw_dmcu = NULL;
1624 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1626 struct amdgpu_dm_connector *aconnector;
1627 struct drm_connector *connector;
1628 struct drm_connector_list_iter iter;
1631 drm_connector_list_iter_begin(dev, &iter);
1632 drm_for_each_connector_iter(connector, &iter) {
1633 aconnector = to_amdgpu_dm_connector(connector);
1634 if (aconnector->dc_link->type == dc_connection_mst_branch &&
1635 aconnector->mst_mgr.aux) {
1636 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1638 aconnector->base.base.id);
1640 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1642 DRM_ERROR("DM_MST: Failed to start MST\n");
1643 aconnector->dc_link->type =
1644 dc_connection_single;
1649 drm_connector_list_iter_end(&iter);
1654 static int dm_late_init(void *handle)
1656 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1658 struct dmcu_iram_parameters params;
1659 unsigned int linear_lut[16];
1661 struct dmcu *dmcu = NULL;
1664 dmcu = adev->dm.dc->res_pool->dmcu;
1666 for (i = 0; i < 16; i++)
1667 linear_lut[i] = 0xFFFF * i / 15;
1670 params.backlight_ramping_start = 0xCCCC;
1671 params.backlight_ramping_reduction = 0xCCCCCCCC;
1672 params.backlight_lut_array_size = 16;
1673 params.backlight_lut_array = linear_lut;
1675 /* Min backlight level after ABM reduction, Don't allow below 1%
1676 * 0xFFFF x 0.01 = 0x28F
1678 params.min_abm_backlight = 0x28F;
1680 /* In the case where abm is implemented on dmcub,
1681 * dmcu object will be null.
1682 * ABM 2.4 and up are implemented on dmcub.
1685 ret = dmcu_load_iram(dmcu, params);
1686 else if (adev->dm.dc->ctx->dmub_srv)
1687 ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
1692 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
1695 static void s3_handle_mst(struct drm_device *dev, bool suspend)
1697 struct amdgpu_dm_connector *aconnector;
1698 struct drm_connector *connector;
1699 struct drm_connector_list_iter iter;
1700 struct drm_dp_mst_topology_mgr *mgr;
1702 bool need_hotplug = false;
1704 drm_connector_list_iter_begin(dev, &iter);
1705 drm_for_each_connector_iter(connector, &iter) {
1706 aconnector = to_amdgpu_dm_connector(connector);
1707 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1708 aconnector->mst_port)
1711 mgr = &aconnector->mst_mgr;
1714 drm_dp_mst_topology_mgr_suspend(mgr);
1716 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
1718 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1719 need_hotplug = true;
1723 drm_connector_list_iter_end(&iter);
1726 drm_kms_helper_hotplug_event(dev);
1729 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
1731 struct smu_context *smu = &adev->smu;
1734 if (!is_support_sw_smu(adev))
1737 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
1738 * on window driver dc implementation.
1739 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
1740 * should be passed to smu during boot up and resume from s3.
1741 * boot up: dc calculate dcn watermark clock settings within dc_create,
1742 * dcn20_resource_construct
1743 * then call pplib functions below to pass the settings to smu:
1744 * smu_set_watermarks_for_clock_ranges
1745 * smu_set_watermarks_table
1746 * navi10_set_watermarks_table
1747 * smu_write_watermarks_table
1749 * For Renoir, clock settings of dcn watermark are also fixed values.
1750 * dc has implemented different flow for window driver:
1751 * dc_hardware_init / dc_set_power_state
1756 * smu_set_watermarks_for_clock_ranges
1757 * renoir_set_watermarks_table
1758 * smu_write_watermarks_table
1761 * dc_hardware_init -> amdgpu_dm_init
1762 * dc_set_power_state --> dm_resume
1764 * therefore, this function apply to navi10/12/14 but not Renoir
1767 switch(adev->asic_type) {
1776 ret = smu_write_watermarks_table(smu);
1778 DRM_ERROR("Failed to update WMTABLE!\n");
1786 * dm_hw_init() - Initialize DC device
1787 * @handle: The base driver device containing the amdgpu_dm device.
1789 * Initialize the &struct amdgpu_display_manager device. This involves calling
1790 * the initializers of each DM component, then populating the struct with them.
1792 * Although the function implies hardware initialization, both hardware and
1793 * software are initialized here. Splitting them out to their relevant init
1794 * hooks is a future TODO item.
1796 * Some notable things that are initialized here:
1798 * - Display Core, both software and hardware
1799 * - DC modules that we need (freesync and color management)
1800 * - DRM software states
1801 * - Interrupt sources and handlers
1803 * - Debug FS entries, if enabled
1805 static int dm_hw_init(void *handle)
1807 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1808 /* Create DAL display manager */
1809 amdgpu_dm_init(adev);
1810 amdgpu_dm_hpd_init(adev);
1816 * dm_hw_fini() - Teardown DC device
1817 * @handle: The base driver device containing the amdgpu_dm device.
1819 * Teardown components within &struct amdgpu_display_manager that require
1820 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1821 * were loaded. Also flush IRQ workqueues and disable them.
1823 static int dm_hw_fini(void *handle)
1825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1827 amdgpu_dm_hpd_fini(adev);
1829 amdgpu_dm_irq_fini(adev);
1830 amdgpu_dm_fini(adev);
1835 static int dm_enable_vblank(struct drm_crtc *crtc);
1836 static void dm_disable_vblank(struct drm_crtc *crtc);
1838 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
1839 struct dc_state *state, bool enable)
1841 enum dc_irq_source irq_source;
1842 struct amdgpu_crtc *acrtc;
1846 for (i = 0; i < state->stream_count; i++) {
1847 acrtc = get_crtc_by_otg_inst(
1848 adev, state->stream_status[i].primary_otg_inst);
1850 if (acrtc && state->stream_status[i].plane_count != 0) {
1851 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
1852 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
1853 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
1854 acrtc->crtc_id, enable ? "en" : "dis", rc);
1856 DRM_WARN("Failed to %s pflip interrupts\n",
1857 enable ? "enable" : "disable");
1860 rc = dm_enable_vblank(&acrtc->base);
1862 DRM_WARN("Failed to enable vblank interrupts\n");
1864 dm_disable_vblank(&acrtc->base);
1872 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
1874 struct dc_state *context = NULL;
1875 enum dc_status res = DC_ERROR_UNEXPECTED;
1877 struct dc_stream_state *del_streams[MAX_PIPES];
1878 int del_streams_count = 0;
1880 memset(del_streams, 0, sizeof(del_streams));
1882 context = dc_create_state(dc);
1883 if (context == NULL)
1884 goto context_alloc_fail;
1886 dc_resource_state_copy_construct_current(dc, context);
1888 /* First remove from context all streams */
1889 for (i = 0; i < context->stream_count; i++) {
1890 struct dc_stream_state *stream = context->streams[i];
1892 del_streams[del_streams_count++] = stream;
1895 /* Remove all planes for removed streams and then remove the streams */
1896 for (i = 0; i < del_streams_count; i++) {
1897 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
1898 res = DC_FAIL_DETACH_SURFACES;
1902 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
1908 res = dc_validate_global_state(dc, context, false);
1911 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res);
1915 res = dc_commit_state(dc, context);
1918 dc_release_state(context);
1924 static int dm_suspend(void *handle)
1926 struct amdgpu_device *adev = handle;
1927 struct amdgpu_display_manager *dm = &adev->dm;
1930 if (amdgpu_in_reset(adev)) {
1931 mutex_lock(&dm->dc_lock);
1933 #if defined(CONFIG_DRM_AMD_DC_DCN)
1934 dc_allow_idle_optimizations(adev->dm.dc, false);
1937 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
1939 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
1941 amdgpu_dm_commit_zero_streams(dm->dc);
1943 amdgpu_dm_irq_suspend(adev);
1948 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
1949 amdgpu_dm_crtc_secure_display_suspend(adev);
1951 WARN_ON(adev->dm.cached_state);
1952 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
1954 s3_handle_mst(adev_to_drm(adev), true);
1956 amdgpu_dm_irq_suspend(adev);
1958 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1963 static struct amdgpu_dm_connector *
1964 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1965 struct drm_crtc *crtc)
1968 struct drm_connector_state *new_con_state;
1969 struct drm_connector *connector;
1970 struct drm_crtc *crtc_from_state;
1972 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1973 crtc_from_state = new_con_state->crtc;
1975 if (crtc_from_state == crtc)
1976 return to_amdgpu_dm_connector(connector);
1982 static void emulated_link_detect(struct dc_link *link)
1984 struct dc_sink_init_data sink_init_data = { 0 };
1985 struct display_sink_capability sink_caps = { 0 };
1986 enum dc_edid_status edid_status;
1987 struct dc_context *dc_ctx = link->ctx;
1988 struct dc_sink *sink = NULL;
1989 struct dc_sink *prev_sink = NULL;
1991 link->type = dc_connection_none;
1992 prev_sink = link->local_sink;
1995 dc_sink_release(prev_sink);
1997 switch (link->connector_signal) {
1998 case SIGNAL_TYPE_HDMI_TYPE_A: {
1999 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2000 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2004 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2005 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2006 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2010 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2011 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2012 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2016 case SIGNAL_TYPE_LVDS: {
2017 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2018 sink_caps.signal = SIGNAL_TYPE_LVDS;
2022 case SIGNAL_TYPE_EDP: {
2023 sink_caps.transaction_type =
2024 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2025 sink_caps.signal = SIGNAL_TYPE_EDP;
2029 case SIGNAL_TYPE_DISPLAY_PORT: {
2030 sink_caps.transaction_type =
2031 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2032 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2037 DC_ERROR("Invalid connector type! signal:%d\n",
2038 link->connector_signal);
2042 sink_init_data.link = link;
2043 sink_init_data.sink_signal = sink_caps.signal;
2045 sink = dc_sink_create(&sink_init_data);
2047 DC_ERROR("Failed to create sink!\n");
2051 /* dc_sink_create returns a new reference */
2052 link->local_sink = sink;
2054 edid_status = dm_helpers_read_local_edid(
2059 if (edid_status != EDID_OK)
2060 DC_ERROR("Failed to read EDID");
2064 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2065 struct amdgpu_display_manager *dm)
2068 struct dc_surface_update surface_updates[MAX_SURFACES];
2069 struct dc_plane_info plane_infos[MAX_SURFACES];
2070 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2071 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2072 struct dc_stream_update stream_update;
2076 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2079 dm_error("Failed to allocate update bundle\n");
2083 for (k = 0; k < dc_state->stream_count; k++) {
2084 bundle->stream_update.stream = dc_state->streams[k];
2086 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2087 bundle->surface_updates[m].surface =
2088 dc_state->stream_status->plane_states[m];
2089 bundle->surface_updates[m].surface->force_full_update =
2092 dc_commit_updates_for_stream(
2093 dm->dc, bundle->surface_updates,
2094 dc_state->stream_status->plane_count,
2095 dc_state->streams[k], &bundle->stream_update, dc_state);
2104 static void dm_set_dpms_off(struct dc_link *link)
2106 struct dc_stream_state *stream_state;
2107 struct amdgpu_dm_connector *aconnector = link->priv;
2108 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
2109 struct dc_stream_update stream_update;
2110 bool dpms_off = true;
2112 memset(&stream_update, 0, sizeof(stream_update));
2113 stream_update.dpms_off = &dpms_off;
2115 mutex_lock(&adev->dm.dc_lock);
2116 stream_state = dc_stream_find_from_link(link);
2118 if (stream_state == NULL) {
2119 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n");
2120 mutex_unlock(&adev->dm.dc_lock);
2124 stream_update.stream = stream_state;
2125 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
2126 stream_state, &stream_update,
2127 stream_state->ctx->dc->current_state);
2128 mutex_unlock(&adev->dm.dc_lock);
2131 static int dm_resume(void *handle)
2133 struct amdgpu_device *adev = handle;
2134 struct drm_device *ddev = adev_to_drm(adev);
2135 struct amdgpu_display_manager *dm = &adev->dm;
2136 struct amdgpu_dm_connector *aconnector;
2137 struct drm_connector *connector;
2138 struct drm_connector_list_iter iter;
2139 struct drm_crtc *crtc;
2140 struct drm_crtc_state *new_crtc_state;
2141 struct dm_crtc_state *dm_new_crtc_state;
2142 struct drm_plane *plane;
2143 struct drm_plane_state *new_plane_state;
2144 struct dm_plane_state *dm_new_plane_state;
2145 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2146 enum dc_connection_type new_connection_type = dc_connection_none;
2147 struct dc_state *dc_state;
2150 if (amdgpu_in_reset(adev)) {
2151 dc_state = dm->cached_dc_state;
2153 r = dm_dmub_hw_init(adev);
2155 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2157 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2160 amdgpu_dm_irq_resume_early(adev);
2162 for (i = 0; i < dc_state->stream_count; i++) {
2163 dc_state->streams[i]->mode_changed = true;
2164 for (j = 0; j < dc_state->stream_status->plane_count; j++) {
2165 dc_state->stream_status->plane_states[j]->update_flags.raw
2170 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2172 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2174 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2176 dc_release_state(dm->cached_dc_state);
2177 dm->cached_dc_state = NULL;
2179 amdgpu_dm_irq_resume_late(adev);
2181 mutex_unlock(&dm->dc_lock);
2185 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2186 dc_release_state(dm_state->context);
2187 dm_state->context = dc_create_state(dm->dc);
2188 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2189 dc_resource_state_construct(dm->dc, dm_state->context);
2191 /* Before powering on DC we need to re-initialize DMUB. */
2192 r = dm_dmub_hw_init(adev);
2194 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2196 /* power on hardware */
2197 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2199 /* program HPD filter */
2203 * early enable HPD Rx IRQ, should be done before set mode as short
2204 * pulse interrupts are used for MST
2206 amdgpu_dm_irq_resume_early(adev);
2208 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2209 s3_handle_mst(ddev, false);
2212 drm_connector_list_iter_begin(ddev, &iter);
2213 drm_for_each_connector_iter(connector, &iter) {
2214 aconnector = to_amdgpu_dm_connector(connector);
2217 * this is the case when traversing through already created
2218 * MST connectors, should be skipped
2220 if (aconnector->mst_port)
2223 mutex_lock(&aconnector->hpd_lock);
2224 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2225 DRM_ERROR("KMS: Failed to detect connector\n");
2227 if (aconnector->base.force && new_connection_type == dc_connection_none)
2228 emulated_link_detect(aconnector->dc_link);
2230 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2232 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2233 aconnector->fake_enable = false;
2235 if (aconnector->dc_sink)
2236 dc_sink_release(aconnector->dc_sink);
2237 aconnector->dc_sink = NULL;
2238 amdgpu_dm_update_connector_after_detect(aconnector);
2239 mutex_unlock(&aconnector->hpd_lock);
2241 drm_connector_list_iter_end(&iter);
2243 /* Force mode set in atomic commit */
2244 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2245 new_crtc_state->active_changed = true;
2248 * atomic_check is expected to create the dc states. We need to release
2249 * them here, since they were duplicated as part of the suspend
2252 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2253 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2254 if (dm_new_crtc_state->stream) {
2255 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2256 dc_stream_release(dm_new_crtc_state->stream);
2257 dm_new_crtc_state->stream = NULL;
2261 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2262 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2263 if (dm_new_plane_state->dc_state) {
2264 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2265 dc_plane_state_release(dm_new_plane_state->dc_state);
2266 dm_new_plane_state->dc_state = NULL;
2270 drm_atomic_helper_resume(ddev, dm->cached_state);
2272 dm->cached_state = NULL;
2274 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2275 amdgpu_dm_crtc_secure_display_resume(adev);
2278 amdgpu_dm_irq_resume_late(adev);
2280 amdgpu_dm_smu_write_watermarks_table(adev);
2288 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2289 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2290 * the base driver's device list to be initialized and torn down accordingly.
2292 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2295 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2297 .early_init = dm_early_init,
2298 .late_init = dm_late_init,
2299 .sw_init = dm_sw_init,
2300 .sw_fini = dm_sw_fini,
2301 .hw_init = dm_hw_init,
2302 .hw_fini = dm_hw_fini,
2303 .suspend = dm_suspend,
2304 .resume = dm_resume,
2305 .is_idle = dm_is_idle,
2306 .wait_for_idle = dm_wait_for_idle,
2307 .check_soft_reset = dm_check_soft_reset,
2308 .soft_reset = dm_soft_reset,
2309 .set_clockgating_state = dm_set_clockgating_state,
2310 .set_powergating_state = dm_set_powergating_state,
2313 const struct amdgpu_ip_block_version dm_ip_block =
2315 .type = AMD_IP_BLOCK_TYPE_DCE,
2319 .funcs = &amdgpu_dm_funcs,
2329 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2330 .fb_create = amdgpu_display_user_framebuffer_create,
2331 .get_format_info = amd_get_format_info,
2332 .output_poll_changed = drm_fb_helper_output_poll_changed,
2333 .atomic_check = amdgpu_dm_atomic_check,
2334 .atomic_commit = drm_atomic_helper_commit,
2337 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2338 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
2341 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2343 u32 max_cll, min_cll, max, min, q, r;
2344 struct amdgpu_dm_backlight_caps *caps;
2345 struct amdgpu_display_manager *dm;
2346 struct drm_connector *conn_base;
2347 struct amdgpu_device *adev;
2348 struct dc_link *link = NULL;
2349 static const u8 pre_computed_values[] = {
2350 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
2351 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
2353 if (!aconnector || !aconnector->dc_link)
2356 link = aconnector->dc_link;
2357 if (link->connector_signal != SIGNAL_TYPE_EDP)
2360 conn_base = &aconnector->base;
2361 adev = drm_to_adev(conn_base->dev);
2363 caps = &dm->backlight_caps;
2364 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2365 caps->aux_support = false;
2366 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
2367 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
2369 if (caps->ext_caps->bits.oled == 1 ||
2370 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2371 caps->ext_caps->bits.hdr_aux_backlight_control == 1)
2372 caps->aux_support = true;
2374 if (amdgpu_backlight == 0)
2375 caps->aux_support = false;
2376 else if (amdgpu_backlight == 1)
2377 caps->aux_support = true;
2379 /* From the specification (CTA-861-G), for calculating the maximum
2380 * luminance we need to use:
2381 * Luminance = 50*2**(CV/32)
2382 * Where CV is a one-byte value.
2383 * For calculating this expression we may need float point precision;
2384 * to avoid this complexity level, we take advantage that CV is divided
2385 * by a constant. From the Euclids division algorithm, we know that CV
2386 * can be written as: CV = 32*q + r. Next, we replace CV in the
2387 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
2388 * need to pre-compute the value of r/32. For pre-computing the values
2389 * We just used the following Ruby line:
2390 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
2391 * The results of the above expressions can be verified at
2392 * pre_computed_values.
2396 max = (1 << q) * pre_computed_values[r];
2398 // min luminance: maxLum * (CV/255)^2 / 100
2399 q = DIV_ROUND_CLOSEST(min_cll, 255);
2400 min = max * DIV_ROUND_CLOSEST((q * q), 100);
2402 caps->aux_max_input_signal = max;
2403 caps->aux_min_input_signal = min;
2406 void amdgpu_dm_update_connector_after_detect(
2407 struct amdgpu_dm_connector *aconnector)
2409 struct drm_connector *connector = &aconnector->base;
2410 struct drm_device *dev = connector->dev;
2411 struct dc_sink *sink;
2413 /* MST handled by drm_mst framework */
2414 if (aconnector->mst_mgr.mst_state == true)
2417 sink = aconnector->dc_link->local_sink;
2419 dc_sink_retain(sink);
2422 * Edid mgmt connector gets first update only in mode_valid hook and then
2423 * the connector sink is set to either fake or physical sink depends on link status.
2424 * Skip if already done during boot.
2426 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2427 && aconnector->dc_em_sink) {
2430 * For S3 resume with headless use eml_sink to fake stream
2431 * because on resume connector->sink is set to NULL
2433 mutex_lock(&dev->mode_config.mutex);
2436 if (aconnector->dc_sink) {
2437 amdgpu_dm_update_freesync_caps(connector, NULL);
2439 * retain and release below are used to
2440 * bump up refcount for sink because the link doesn't point
2441 * to it anymore after disconnect, so on next crtc to connector
2442 * reshuffle by UMD we will get into unwanted dc_sink release
2444 dc_sink_release(aconnector->dc_sink);
2446 aconnector->dc_sink = sink;
2447 dc_sink_retain(aconnector->dc_sink);
2448 amdgpu_dm_update_freesync_caps(connector,
2451 amdgpu_dm_update_freesync_caps(connector, NULL);
2452 if (!aconnector->dc_sink) {
2453 aconnector->dc_sink = aconnector->dc_em_sink;
2454 dc_sink_retain(aconnector->dc_sink);
2458 mutex_unlock(&dev->mode_config.mutex);
2461 dc_sink_release(sink);
2466 * TODO: temporary guard to look for proper fix
2467 * if this sink is MST sink, we should not do anything
2469 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2470 dc_sink_release(sink);
2474 if (aconnector->dc_sink == sink) {
2476 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2479 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2480 aconnector->connector_id);
2482 dc_sink_release(sink);
2486 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2487 aconnector->connector_id, aconnector->dc_sink, sink);
2489 mutex_lock(&dev->mode_config.mutex);
2492 * 1. Update status of the drm connector
2493 * 2. Send an event and let userspace tell us what to do
2497 * TODO: check if we still need the S3 mode update workaround.
2498 * If yes, put it here.
2500 if (aconnector->dc_sink) {
2501 amdgpu_dm_update_freesync_caps(connector, NULL);
2502 dc_sink_release(aconnector->dc_sink);
2505 aconnector->dc_sink = sink;
2506 dc_sink_retain(aconnector->dc_sink);
2507 if (sink->dc_edid.length == 0) {
2508 aconnector->edid = NULL;
2509 if (aconnector->dc_link->aux_mode) {
2510 drm_dp_cec_unset_edid(
2511 &aconnector->dm_dp_aux.aux);
2515 (struct edid *)sink->dc_edid.raw_edid;
2517 drm_connector_update_edid_property(connector,
2519 if (aconnector->dc_link->aux_mode)
2520 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2524 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2525 update_connector_ext_caps(aconnector);
2527 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2528 amdgpu_dm_update_freesync_caps(connector, NULL);
2529 drm_connector_update_edid_property(connector, NULL);
2530 aconnector->num_modes = 0;
2531 dc_sink_release(aconnector->dc_sink);
2532 aconnector->dc_sink = NULL;
2533 aconnector->edid = NULL;
2534 #ifdef CONFIG_DRM_AMD_DC_HDCP
2535 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2536 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2537 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2541 mutex_unlock(&dev->mode_config.mutex);
2543 update_subconnector_property(aconnector);
2546 dc_sink_release(sink);
2549 static void handle_hpd_irq(void *param)
2551 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2552 struct drm_connector *connector = &aconnector->base;
2553 struct drm_device *dev = connector->dev;
2554 enum dc_connection_type new_connection_type = dc_connection_none;
2555 struct amdgpu_device *adev = drm_to_adev(dev);
2556 #ifdef CONFIG_DRM_AMD_DC_HDCP
2557 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
2560 if (adev->dm.disable_hpd_irq)
2564 * In case of failure or MST no need to update connector status or notify the OS
2565 * since (for MST case) MST does this in its own context.
2567 mutex_lock(&aconnector->hpd_lock);
2569 #ifdef CONFIG_DRM_AMD_DC_HDCP
2570 if (adev->dm.hdcp_workqueue) {
2571 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
2572 dm_con_state->update_hdcp = true;
2575 if (aconnector->fake_enable)
2576 aconnector->fake_enable = false;
2578 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2579 DRM_ERROR("KMS: Failed to detect connector\n");
2581 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2582 emulated_link_detect(aconnector->dc_link);
2585 drm_modeset_lock_all(dev);
2586 dm_restore_drm_connector_state(dev, connector);
2587 drm_modeset_unlock_all(dev);
2589 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2590 drm_kms_helper_hotplug_event(dev);
2592 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
2593 if (new_connection_type == dc_connection_none &&
2594 aconnector->dc_link->type == dc_connection_none)
2595 dm_set_dpms_off(aconnector->dc_link);
2597 amdgpu_dm_update_connector_after_detect(aconnector);
2599 drm_modeset_lock_all(dev);
2600 dm_restore_drm_connector_state(dev, connector);
2601 drm_modeset_unlock_all(dev);
2603 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2604 drm_kms_helper_hotplug_event(dev);
2606 mutex_unlock(&aconnector->hpd_lock);
2610 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
2612 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
2614 bool new_irq_handled = false;
2616 int dpcd_bytes_to_read;
2618 const int max_process_count = 30;
2619 int process_count = 0;
2621 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
2623 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
2624 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
2625 /* DPCD 0x200 - 0x201 for downstream IRQ */
2626 dpcd_addr = DP_SINK_COUNT;
2628 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
2629 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
2630 dpcd_addr = DP_SINK_COUNT_ESI;
2633 dret = drm_dp_dpcd_read(
2634 &aconnector->dm_dp_aux.aux,
2637 dpcd_bytes_to_read);
2639 while (dret == dpcd_bytes_to_read &&
2640 process_count < max_process_count) {
2646 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
2647 /* handle HPD short pulse irq */
2648 if (aconnector->mst_mgr.mst_state)
2650 &aconnector->mst_mgr,
2654 if (new_irq_handled) {
2655 /* ACK at DPCD to notify down stream */
2656 const int ack_dpcd_bytes_to_write =
2657 dpcd_bytes_to_read - 1;
2659 for (retry = 0; retry < 3; retry++) {
2662 wret = drm_dp_dpcd_write(
2663 &aconnector->dm_dp_aux.aux,
2666 ack_dpcd_bytes_to_write);
2667 if (wret == ack_dpcd_bytes_to_write)
2671 /* check if there is new irq to be handled */
2672 dret = drm_dp_dpcd_read(
2673 &aconnector->dm_dp_aux.aux,
2676 dpcd_bytes_to_read);
2678 new_irq_handled = false;
2684 if (process_count == max_process_count)
2685 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2688 static void handle_hpd_rx_irq(void *param)
2690 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2691 struct drm_connector *connector = &aconnector->base;
2692 struct drm_device *dev = connector->dev;
2693 struct dc_link *dc_link = aconnector->dc_link;
2694 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
2695 bool result = false;
2696 enum dc_connection_type new_connection_type = dc_connection_none;
2697 struct amdgpu_device *adev = drm_to_adev(dev);
2698 union hpd_irq_data hpd_irq_data;
2700 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
2702 if (adev->dm.disable_hpd_irq)
2707 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2708 * conflict, after implement i2c helper, this mutex should be
2711 if (dc_link->type != dc_connection_mst_branch)
2712 mutex_lock(&aconnector->hpd_lock);
2714 read_hpd_rx_irq_data(dc_link, &hpd_irq_data);
2716 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2717 (dc_link->type == dc_connection_mst_branch)) {
2718 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) {
2720 dm_handle_hpd_rx_irq(aconnector);
2722 } else if (hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
2724 dm_handle_hpd_rx_irq(aconnector);
2729 mutex_lock(&adev->dm.dc_lock);
2730 #ifdef CONFIG_DRM_AMD_DC_HDCP
2731 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL);
2733 result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL);
2735 mutex_unlock(&adev->dm.dc_lock);
2738 if (result && !is_mst_root_connector) {
2739 /* Downstream Port status changed. */
2740 if (!dc_link_detect_sink(dc_link, &new_connection_type))
2741 DRM_ERROR("KMS: Failed to detect connector\n");
2743 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2744 emulated_link_detect(dc_link);
2746 if (aconnector->fake_enable)
2747 aconnector->fake_enable = false;
2749 amdgpu_dm_update_connector_after_detect(aconnector);
2752 drm_modeset_lock_all(dev);
2753 dm_restore_drm_connector_state(dev, connector);
2754 drm_modeset_unlock_all(dev);
2756 drm_kms_helper_hotplug_event(dev);
2757 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
2759 if (aconnector->fake_enable)
2760 aconnector->fake_enable = false;
2762 amdgpu_dm_update_connector_after_detect(aconnector);
2765 drm_modeset_lock_all(dev);
2766 dm_restore_drm_connector_state(dev, connector);
2767 drm_modeset_unlock_all(dev);
2769 drm_kms_helper_hotplug_event(dev);
2772 #ifdef CONFIG_DRM_AMD_DC_HDCP
2773 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
2774 if (adev->dm.hdcp_workqueue)
2775 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2779 if (dc_link->type != dc_connection_mst_branch) {
2780 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
2781 mutex_unlock(&aconnector->hpd_lock);
2785 static void register_hpd_handlers(struct amdgpu_device *adev)
2787 struct drm_device *dev = adev_to_drm(adev);
2788 struct drm_connector *connector;
2789 struct amdgpu_dm_connector *aconnector;
2790 const struct dc_link *dc_link;
2791 struct dc_interrupt_params int_params = {0};
2793 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2794 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2796 list_for_each_entry(connector,
2797 &dev->mode_config.connector_list, head) {
2799 aconnector = to_amdgpu_dm_connector(connector);
2800 dc_link = aconnector->dc_link;
2802 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2803 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2804 int_params.irq_source = dc_link->irq_source_hpd;
2806 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2808 (void *) aconnector);
2811 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2813 /* Also register for DP short pulse (hpd_rx). */
2814 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2815 int_params.irq_source = dc_link->irq_source_hpd_rx;
2817 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2819 (void *) aconnector);
2824 #if defined(CONFIG_DRM_AMD_DC_SI)
2825 /* Register IRQ sources and initialize IRQ callbacks */
2826 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
2828 struct dc *dc = adev->dm.dc;
2829 struct common_irq_params *c_irq_params;
2830 struct dc_interrupt_params int_params = {0};
2833 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2835 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2836 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2839 * Actions of amdgpu_irq_add_id():
2840 * 1. Register a set() function with base driver.
2841 * Base driver will call set() function to enable/disable an
2842 * interrupt in DC hardware.
2843 * 2. Register amdgpu_dm_irq_handler().
2844 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2845 * coming from DC hardware.
2846 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2847 * for acknowledging and handling. */
2849 /* Use VBLANK interrupt */
2850 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2851 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
2853 DRM_ERROR("Failed to add crtc irq id!\n");
2857 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2858 int_params.irq_source =
2859 dc_interrupt_to_irq_source(dc, i+1 , 0);
2861 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2863 c_irq_params->adev = adev;
2864 c_irq_params->irq_src = int_params.irq_source;
2866 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2867 dm_crtc_high_irq, c_irq_params);
2870 /* Use GRPH_PFLIP interrupt */
2871 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2872 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2873 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2875 DRM_ERROR("Failed to add page flip irq id!\n");
2879 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2880 int_params.irq_source =
2881 dc_interrupt_to_irq_source(dc, i, 0);
2883 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2885 c_irq_params->adev = adev;
2886 c_irq_params->irq_src = int_params.irq_source;
2888 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2889 dm_pflip_high_irq, c_irq_params);
2894 r = amdgpu_irq_add_id(adev, client_id,
2895 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2897 DRM_ERROR("Failed to add hpd irq id!\n");
2901 register_hpd_handlers(adev);
2907 /* Register IRQ sources and initialize IRQ callbacks */
2908 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2910 struct dc *dc = adev->dm.dc;
2911 struct common_irq_params *c_irq_params;
2912 struct dc_interrupt_params int_params = {0};
2915 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2917 if (adev->asic_type >= CHIP_VEGA10)
2918 client_id = SOC15_IH_CLIENTID_DCE;
2920 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2921 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2924 * Actions of amdgpu_irq_add_id():
2925 * 1. Register a set() function with base driver.
2926 * Base driver will call set() function to enable/disable an
2927 * interrupt in DC hardware.
2928 * 2. Register amdgpu_dm_irq_handler().
2929 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2930 * coming from DC hardware.
2931 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2932 * for acknowledging and handling. */
2934 /* Use VBLANK interrupt */
2935 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2936 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
2938 DRM_ERROR("Failed to add crtc irq id!\n");
2942 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2943 int_params.irq_source =
2944 dc_interrupt_to_irq_source(dc, i, 0);
2946 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2948 c_irq_params->adev = adev;
2949 c_irq_params->irq_src = int_params.irq_source;
2951 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2952 dm_crtc_high_irq, c_irq_params);
2955 /* Use VUPDATE interrupt */
2956 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2957 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2959 DRM_ERROR("Failed to add vupdate irq id!\n");
2963 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2964 int_params.irq_source =
2965 dc_interrupt_to_irq_source(dc, i, 0);
2967 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2969 c_irq_params->adev = adev;
2970 c_irq_params->irq_src = int_params.irq_source;
2972 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2973 dm_vupdate_high_irq, c_irq_params);
2976 /* Use GRPH_PFLIP interrupt */
2977 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2978 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2979 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2981 DRM_ERROR("Failed to add page flip irq id!\n");
2985 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2986 int_params.irq_source =
2987 dc_interrupt_to_irq_source(dc, i, 0);
2989 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2991 c_irq_params->adev = adev;
2992 c_irq_params->irq_src = int_params.irq_source;
2994 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2995 dm_pflip_high_irq, c_irq_params);
3000 r = amdgpu_irq_add_id(adev, client_id,
3001 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3003 DRM_ERROR("Failed to add hpd irq id!\n");
3007 register_hpd_handlers(adev);
3012 #if defined(CONFIG_DRM_AMD_DC_DCN)
3013 /* Register IRQ sources and initialize IRQ callbacks */
3014 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3016 struct dc *dc = adev->dm.dc;
3017 struct common_irq_params *c_irq_params;
3018 struct dc_interrupt_params int_params = {0};
3021 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3022 static const unsigned int vrtl_int_srcid[] = {
3023 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3024 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3025 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3026 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3027 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3028 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3032 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3033 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3036 * Actions of amdgpu_irq_add_id():
3037 * 1. Register a set() function with base driver.
3038 * Base driver will call set() function to enable/disable an
3039 * interrupt in DC hardware.
3040 * 2. Register amdgpu_dm_irq_handler().
3041 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3042 * coming from DC hardware.
3043 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3044 * for acknowledging and handling.
3047 /* Use VSTARTUP interrupt */
3048 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3049 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3051 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3054 DRM_ERROR("Failed to add crtc irq id!\n");
3058 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3059 int_params.irq_source =
3060 dc_interrupt_to_irq_source(dc, i, 0);
3062 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3064 c_irq_params->adev = adev;
3065 c_irq_params->irq_src = int_params.irq_source;
3067 amdgpu_dm_irq_register_interrupt(
3068 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3071 /* Use otg vertical line interrupt */
3072 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3073 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3074 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3075 vrtl_int_srcid[i], &adev->vline0_irq);
3078 DRM_ERROR("Failed to add vline0 irq id!\n");
3082 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3083 int_params.irq_source =
3084 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3086 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3087 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3091 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3092 - DC_IRQ_SOURCE_DC1_VLINE0];
3094 c_irq_params->adev = adev;
3095 c_irq_params->irq_src = int_params.irq_source;
3097 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3098 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3102 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3103 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3104 * to trigger at end of each vblank, regardless of state of the lock,
3105 * matching DCE behaviour.
3107 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3108 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3110 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3113 DRM_ERROR("Failed to add vupdate irq id!\n");
3117 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3118 int_params.irq_source =
3119 dc_interrupt_to_irq_source(dc, i, 0);
3121 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3123 c_irq_params->adev = adev;
3124 c_irq_params->irq_src = int_params.irq_source;
3126 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3127 dm_vupdate_high_irq, c_irq_params);
3130 /* Use GRPH_PFLIP interrupt */
3131 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3132 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
3134 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3136 DRM_ERROR("Failed to add page flip irq id!\n");
3140 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3141 int_params.irq_source =
3142 dc_interrupt_to_irq_source(dc, i, 0);
3144 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3146 c_irq_params->adev = adev;
3147 c_irq_params->irq_src = int_params.irq_source;
3149 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3150 dm_pflip_high_irq, c_irq_params);
3154 if (dc->ctx->dmub_srv) {
3155 i = DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT;
3156 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->dmub_trace_irq);
3159 DRM_ERROR("Failed to add dmub trace irq id!\n");
3163 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3164 int_params.irq_source =
3165 dc_interrupt_to_irq_source(dc, i, 0);
3167 c_irq_params = &adev->dm.dmub_trace_params[0];
3169 c_irq_params->adev = adev;
3170 c_irq_params->irq_src = int_params.irq_source;
3172 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3173 dm_dmub_trace_high_irq, c_irq_params);
3177 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3180 DRM_ERROR("Failed to add hpd irq id!\n");
3184 register_hpd_handlers(adev);
3191 * Acquires the lock for the atomic state object and returns
3192 * the new atomic state.
3194 * This should only be called during atomic check.
3196 static int dm_atomic_get_state(struct drm_atomic_state *state,
3197 struct dm_atomic_state **dm_state)
3199 struct drm_device *dev = state->dev;
3200 struct amdgpu_device *adev = drm_to_adev(dev);
3201 struct amdgpu_display_manager *dm = &adev->dm;
3202 struct drm_private_state *priv_state;
3207 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3208 if (IS_ERR(priv_state))
3209 return PTR_ERR(priv_state);
3211 *dm_state = to_dm_atomic_state(priv_state);
3216 static struct dm_atomic_state *
3217 dm_atomic_get_new_state(struct drm_atomic_state *state)
3219 struct drm_device *dev = state->dev;
3220 struct amdgpu_device *adev = drm_to_adev(dev);
3221 struct amdgpu_display_manager *dm = &adev->dm;
3222 struct drm_private_obj *obj;
3223 struct drm_private_state *new_obj_state;
3226 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3227 if (obj->funcs == dm->atomic_obj.funcs)
3228 return to_dm_atomic_state(new_obj_state);
3234 static struct drm_private_state *
3235 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3237 struct dm_atomic_state *old_state, *new_state;
3239 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3243 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3245 old_state = to_dm_atomic_state(obj->state);
3247 if (old_state && old_state->context)
3248 new_state->context = dc_copy_state(old_state->context);
3250 if (!new_state->context) {
3255 return &new_state->base;
3258 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3259 struct drm_private_state *state)
3261 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3263 if (dm_state && dm_state->context)
3264 dc_release_state(dm_state->context);
3269 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3270 .atomic_duplicate_state = dm_atomic_duplicate_state,
3271 .atomic_destroy_state = dm_atomic_destroy_state,
3274 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3276 struct dm_atomic_state *state;
3279 adev->mode_info.mode_config_initialized = true;
3281 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3282 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3284 adev_to_drm(adev)->mode_config.max_width = 16384;
3285 adev_to_drm(adev)->mode_config.max_height = 16384;
3287 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3288 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3289 /* indicates support for immediate flip */
3290 adev_to_drm(adev)->mode_config.async_page_flip = true;
3292 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
3294 state = kzalloc(sizeof(*state), GFP_KERNEL);
3298 state->context = dc_create_state(adev->dm.dc);
3299 if (!state->context) {
3304 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3306 drm_atomic_private_obj_init(adev_to_drm(adev),
3307 &adev->dm.atomic_obj,
3309 &dm_atomic_state_funcs);
3311 r = amdgpu_display_modeset_create_props(adev);
3313 dc_release_state(state->context);
3318 r = amdgpu_dm_audio_init(adev);
3320 dc_release_state(state->context);
3328 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3329 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3330 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3332 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3333 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3335 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
3337 #if defined(CONFIG_ACPI)
3338 struct amdgpu_dm_backlight_caps caps;
3340 memset(&caps, 0, sizeof(caps));
3342 if (dm->backlight_caps.caps_valid)
3345 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
3346 if (caps.caps_valid) {
3347 dm->backlight_caps.caps_valid = true;
3348 if (caps.aux_support)
3350 dm->backlight_caps.min_input_signal = caps.min_input_signal;
3351 dm->backlight_caps.max_input_signal = caps.max_input_signal;
3353 dm->backlight_caps.min_input_signal =
3354 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3355 dm->backlight_caps.max_input_signal =
3356 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3359 if (dm->backlight_caps.aux_support)
3362 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3363 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3367 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3368 unsigned *min, unsigned *max)
3373 if (caps->aux_support) {
3374 // Firmware limits are in nits, DC API wants millinits.
3375 *max = 1000 * caps->aux_max_input_signal;
3376 *min = 1000 * caps->aux_min_input_signal;
3378 // Firmware limits are 8-bit, PWM control is 16-bit.
3379 *max = 0x101 * caps->max_input_signal;
3380 *min = 0x101 * caps->min_input_signal;
3385 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3386 uint32_t brightness)
3390 if (!get_brightness_range(caps, &min, &max))
3393 // Rescale 0..255 to min..max
3394 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3395 AMDGPU_MAX_BL_LEVEL);
3398 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3399 uint32_t brightness)
3403 if (!get_brightness_range(caps, &min, &max))
3406 if (brightness < min)
3408 // Rescale min..max to 0..255
3409 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3413 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3415 struct amdgpu_display_manager *dm = bl_get_data(bd);
3416 struct amdgpu_dm_backlight_caps caps;
3417 struct dc_link *link = NULL;
3421 amdgpu_dm_update_backlight_caps(dm);
3422 caps = dm->backlight_caps;
3424 link = (struct dc_link *)dm->backlight_link;
3426 brightness = convert_brightness_from_user(&caps, bd->props.brightness);
3427 // Change brightness based on AUX property
3428 if (caps.aux_support)
3429 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3430 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3432 rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);
3437 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
3439 struct amdgpu_display_manager *dm = bl_get_data(bd);
3440 struct amdgpu_dm_backlight_caps caps;
3442 amdgpu_dm_update_backlight_caps(dm);
3443 caps = dm->backlight_caps;
3445 if (caps.aux_support) {
3446 struct dc_link *link = (struct dc_link *)dm->backlight_link;
3450 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
3452 return bd->props.brightness;
3453 return convert_brightness_to_user(&caps, avg);
3455 int ret = dc_link_get_backlight_level(dm->backlight_link);
3457 if (ret == DC_ERROR_UNEXPECTED)
3458 return bd->props.brightness;
3459 return convert_brightness_to_user(&caps, ret);
3463 static const struct backlight_ops amdgpu_dm_backlight_ops = {
3464 .options = BL_CORE_SUSPENDRESUME,
3465 .get_brightness = amdgpu_dm_backlight_get_brightness,
3466 .update_status = amdgpu_dm_backlight_update_status,
3470 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
3473 struct backlight_properties props = { 0 };
3475 amdgpu_dm_update_backlight_caps(dm);
3477 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
3478 props.brightness = AMDGPU_MAX_BL_LEVEL;
3479 props.type = BACKLIGHT_RAW;
3481 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
3482 adev_to_drm(dm->adev)->primary->index);
3484 dm->backlight_dev = backlight_device_register(bl_name,
3485 adev_to_drm(dm->adev)->dev,
3487 &amdgpu_dm_backlight_ops,
3490 if (IS_ERR(dm->backlight_dev))
3491 DRM_ERROR("DM: Backlight registration failed!\n");
3493 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
3498 static int initialize_plane(struct amdgpu_display_manager *dm,
3499 struct amdgpu_mode_info *mode_info, int plane_id,
3500 enum drm_plane_type plane_type,
3501 const struct dc_plane_cap *plane_cap)
3503 struct drm_plane *plane;
3504 unsigned long possible_crtcs;
3507 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
3509 DRM_ERROR("KMS: Failed to allocate plane\n");
3512 plane->type = plane_type;
3515 * HACK: IGT tests expect that the primary plane for a CRTC
3516 * can only have one possible CRTC. Only expose support for
3517 * any CRTC if they're not going to be used as a primary plane
3518 * for a CRTC - like overlay or underlay planes.
3520 possible_crtcs = 1 << plane_id;
3521 if (plane_id >= dm->dc->caps.max_streams)
3522 possible_crtcs = 0xff;
3524 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
3527 DRM_ERROR("KMS: Failed to initialize plane\n");
3533 mode_info->planes[plane_id] = plane;
3539 static void register_backlight_device(struct amdgpu_display_manager *dm,
3540 struct dc_link *link)
3542 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3543 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3545 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3546 link->type != dc_connection_none) {
3548 * Event if registration failed, we should continue with
3549 * DM initialization because not having a backlight control
3550 * is better then a black screen.
3552 amdgpu_dm_register_backlight_device(dm);
3554 if (dm->backlight_dev)
3555 dm->backlight_link = link;
3562 * In this architecture, the association
3563 * connector -> encoder -> crtc
3564 * id not really requried. The crtc and connector will hold the
3565 * display_index as an abstraction to use with DAL component
3567 * Returns 0 on success
3569 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
3571 struct amdgpu_display_manager *dm = &adev->dm;
3573 struct amdgpu_dm_connector *aconnector = NULL;
3574 struct amdgpu_encoder *aencoder = NULL;
3575 struct amdgpu_mode_info *mode_info = &adev->mode_info;
3577 int32_t primary_planes;
3578 enum dc_connection_type new_connection_type = dc_connection_none;
3579 const struct dc_plane_cap *plane;
3581 dm->display_indexes_num = dm->dc->caps.max_streams;
3582 /* Update the actual used number of crtc */
3583 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
3585 link_cnt = dm->dc->caps.max_links;
3586 if (amdgpu_dm_mode_config_init(dm->adev)) {
3587 DRM_ERROR("DM: Failed to initialize mode config\n");
3591 /* There is one primary plane per CRTC */
3592 primary_planes = dm->dc->caps.max_streams;
3593 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
3596 * Initialize primary planes, implicit planes for legacy IOCTLS.
3597 * Order is reversed to match iteration order in atomic check.
3599 for (i = (primary_planes - 1); i >= 0; i--) {
3600 plane = &dm->dc->caps.planes[i];
3602 if (initialize_plane(dm, mode_info, i,
3603 DRM_PLANE_TYPE_PRIMARY, plane)) {
3604 DRM_ERROR("KMS: Failed to initialize primary plane\n");
3610 * Initialize overlay planes, index starting after primary planes.
3611 * These planes have a higher DRM index than the primary planes since
3612 * they should be considered as having a higher z-order.
3613 * Order is reversed to match iteration order in atomic check.
3615 * Only support DCN for now, and only expose one so we don't encourage
3616 * userspace to use up all the pipes.
3618 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
3619 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
3621 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
3624 if (!plane->blends_with_above || !plane->blends_with_below)
3627 if (!plane->pixel_format_support.argb8888)
3630 if (initialize_plane(dm, NULL, primary_planes + i,
3631 DRM_PLANE_TYPE_OVERLAY, plane)) {
3632 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
3636 /* Only create one overlay plane. */
3640 for (i = 0; i < dm->dc->caps.max_streams; i++)
3641 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
3642 DRM_ERROR("KMS: Failed to initialize crtc\n");
3646 /* loops over all connectors on the board */
3647 for (i = 0; i < link_cnt; i++) {
3648 struct dc_link *link = NULL;
3650 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
3652 "KMS: Cannot support more than %d display indexes\n",
3653 AMDGPU_DM_MAX_DISPLAY_INDEX);
3657 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
3661 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
3665 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
3666 DRM_ERROR("KMS: Failed to initialize encoder\n");
3670 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
3671 DRM_ERROR("KMS: Failed to initialize connector\n");
3675 link = dc_get_link_at_index(dm->dc, i);
3677 if (!dc_link_detect_sink(link, &new_connection_type))
3678 DRM_ERROR("KMS: Failed to detect connector\n");
3680 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3681 emulated_link_detect(link);
3682 amdgpu_dm_update_connector_after_detect(aconnector);
3684 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
3685 amdgpu_dm_update_connector_after_detect(aconnector);
3686 register_backlight_device(dm, link);
3687 if (amdgpu_dc_feature_mask & DC_PSR_MASK)
3688 amdgpu_dm_set_psr_caps(link);
3694 /* Software is initialized. Now we can register interrupt handlers. */
3695 switch (adev->asic_type) {
3696 #if defined(CONFIG_DRM_AMD_DC_SI)
3701 if (dce60_register_irq_handlers(dm->adev)) {
3702 DRM_ERROR("DM: Failed to initialize IRQ\n");
3716 case CHIP_POLARIS11:
3717 case CHIP_POLARIS10:
3718 case CHIP_POLARIS12:
3723 if (dce110_register_irq_handlers(dm->adev)) {
3724 DRM_ERROR("DM: Failed to initialize IRQ\n");
3728 #if defined(CONFIG_DRM_AMD_DC_DCN)
3734 case CHIP_SIENNA_CICHLID:
3735 case CHIP_NAVY_FLOUNDER:
3736 case CHIP_DIMGREY_CAVEFISH:
3738 if (dcn10_register_irq_handlers(dm->adev)) {
3739 DRM_ERROR("DM: Failed to initialize IRQ\n");
3745 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3757 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
3759 drm_mode_config_cleanup(dm->ddev);
3760 drm_atomic_private_obj_fini(&dm->atomic_obj);
3764 /******************************************************************************
3765 * amdgpu_display_funcs functions
3766 *****************************************************************************/
3769 * dm_bandwidth_update - program display watermarks
3771 * @adev: amdgpu_device pointer
3773 * Calculate and program the display watermarks and line buffer allocation.
3775 static void dm_bandwidth_update(struct amdgpu_device *adev)
3777 /* TODO: implement later */
3780 static const struct amdgpu_display_funcs dm_display_funcs = {
3781 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
3782 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
3783 .backlight_set_level = NULL, /* never called for DC */
3784 .backlight_get_level = NULL, /* never called for DC */
3785 .hpd_sense = NULL,/* called unconditionally */
3786 .hpd_set_polarity = NULL, /* called unconditionally */
3787 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
3788 .page_flip_get_scanoutpos =
3789 dm_crtc_get_scanoutpos,/* called unconditionally */
3790 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
3791 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
3794 #if defined(CONFIG_DEBUG_KERNEL_DC)
3796 static ssize_t s3_debug_store(struct device *device,
3797 struct device_attribute *attr,
3803 struct drm_device *drm_dev = dev_get_drvdata(device);
3804 struct amdgpu_device *adev = drm_to_adev(drm_dev);
3806 ret = kstrtoint(buf, 0, &s3_state);
3811 drm_kms_helper_hotplug_event(adev_to_drm(adev));
3816 return ret == 0 ? count : 0;
3819 DEVICE_ATTR_WO(s3_debug);
3823 static int dm_early_init(void *handle)
3825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3827 switch (adev->asic_type) {
3828 #if defined(CONFIG_DRM_AMD_DC_SI)
3832 adev->mode_info.num_crtc = 6;
3833 adev->mode_info.num_hpd = 6;
3834 adev->mode_info.num_dig = 6;
3837 adev->mode_info.num_crtc = 2;
3838 adev->mode_info.num_hpd = 2;
3839 adev->mode_info.num_dig = 2;
3844 adev->mode_info.num_crtc = 6;
3845 adev->mode_info.num_hpd = 6;
3846 adev->mode_info.num_dig = 6;
3849 adev->mode_info.num_crtc = 4;
3850 adev->mode_info.num_hpd = 6;
3851 adev->mode_info.num_dig = 7;
3855 adev->mode_info.num_crtc = 2;
3856 adev->mode_info.num_hpd = 6;
3857 adev->mode_info.num_dig = 6;
3861 adev->mode_info.num_crtc = 6;
3862 adev->mode_info.num_hpd = 6;
3863 adev->mode_info.num_dig = 7;
3866 adev->mode_info.num_crtc = 3;
3867 adev->mode_info.num_hpd = 6;
3868 adev->mode_info.num_dig = 9;
3871 adev->mode_info.num_crtc = 2;
3872 adev->mode_info.num_hpd = 6;
3873 adev->mode_info.num_dig = 9;
3875 case CHIP_POLARIS11:
3876 case CHIP_POLARIS12:
3877 adev->mode_info.num_crtc = 5;
3878 adev->mode_info.num_hpd = 5;
3879 adev->mode_info.num_dig = 5;
3881 case CHIP_POLARIS10:
3883 adev->mode_info.num_crtc = 6;
3884 adev->mode_info.num_hpd = 6;
3885 adev->mode_info.num_dig = 6;
3890 adev->mode_info.num_crtc = 6;
3891 adev->mode_info.num_hpd = 6;
3892 adev->mode_info.num_dig = 6;
3894 #if defined(CONFIG_DRM_AMD_DC_DCN)
3898 adev->mode_info.num_crtc = 4;
3899 adev->mode_info.num_hpd = 4;
3900 adev->mode_info.num_dig = 4;
3904 case CHIP_SIENNA_CICHLID:
3905 case CHIP_NAVY_FLOUNDER:
3906 adev->mode_info.num_crtc = 6;
3907 adev->mode_info.num_hpd = 6;
3908 adev->mode_info.num_dig = 6;
3911 case CHIP_DIMGREY_CAVEFISH:
3912 adev->mode_info.num_crtc = 5;
3913 adev->mode_info.num_hpd = 5;
3914 adev->mode_info.num_dig = 5;
3918 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3922 amdgpu_dm_set_irq_funcs(adev);
3924 if (adev->mode_info.funcs == NULL)
3925 adev->mode_info.funcs = &dm_display_funcs;
3928 * Note: Do NOT change adev->audio_endpt_rreg and
3929 * adev->audio_endpt_wreg because they are initialised in
3930 * amdgpu_device_init()
3932 #if defined(CONFIG_DEBUG_KERNEL_DC)
3934 adev_to_drm(adev)->dev,
3935 &dev_attr_s3_debug);
3941 static bool modeset_required(struct drm_crtc_state *crtc_state,
3942 struct dc_stream_state *new_stream,
3943 struct dc_stream_state *old_stream)
3945 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3948 static bool modereset_required(struct drm_crtc_state *crtc_state)
3950 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3953 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3955 drm_encoder_cleanup(encoder);
3959 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3960 .destroy = amdgpu_dm_encoder_destroy,
3964 static void get_min_max_dc_plane_scaling(struct drm_device *dev,
3965 struct drm_framebuffer *fb,
3966 int *min_downscale, int *max_upscale)
3968 struct amdgpu_device *adev = drm_to_adev(dev);
3969 struct dc *dc = adev->dm.dc;
3970 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
3971 struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
3973 switch (fb->format->format) {
3974 case DRM_FORMAT_P010:
3975 case DRM_FORMAT_NV12:
3976 case DRM_FORMAT_NV21:
3977 *max_upscale = plane_cap->max_upscale_factor.nv12;
3978 *min_downscale = plane_cap->max_downscale_factor.nv12;
3981 case DRM_FORMAT_XRGB16161616F:
3982 case DRM_FORMAT_ARGB16161616F:
3983 case DRM_FORMAT_XBGR16161616F:
3984 case DRM_FORMAT_ABGR16161616F:
3985 *max_upscale = plane_cap->max_upscale_factor.fp16;
3986 *min_downscale = plane_cap->max_downscale_factor.fp16;
3990 *max_upscale = plane_cap->max_upscale_factor.argb8888;
3991 *min_downscale = plane_cap->max_downscale_factor.argb8888;
3996 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a
3997 * scaling factor of 1.0 == 1000 units.
3999 if (*max_upscale == 1)
4000 *max_upscale = 1000;
4002 if (*min_downscale == 1)
4003 *min_downscale = 1000;
4007 static int fill_dc_scaling_info(const struct drm_plane_state *state,
4008 struct dc_scaling_info *scaling_info)
4010 int scale_w, scale_h, min_downscale, max_upscale;
4012 memset(scaling_info, 0, sizeof(*scaling_info));
4014 /* Source is fixed 16.16 but we ignore mantissa for now... */
4015 scaling_info->src_rect.x = state->src_x >> 16;
4016 scaling_info->src_rect.y = state->src_y >> 16;
4019 * For reasons we don't (yet) fully understand a non-zero
4020 * src_y coordinate into an NV12 buffer can cause a
4021 * system hang. To avoid hangs (and maybe be overly cautious)
4022 * let's reject both non-zero src_x and src_y.
4024 * We currently know of only one use-case to reproduce a
4025 * scenario with non-zero src_x and src_y for NV12, which
4026 * is to gesture the YouTube Android app into full screen
4030 state->fb->format->format == DRM_FORMAT_NV12 &&
4031 (scaling_info->src_rect.x != 0 ||
4032 scaling_info->src_rect.y != 0))
4035 scaling_info->src_rect.width = state->src_w >> 16;
4036 if (scaling_info->src_rect.width == 0)
4039 scaling_info->src_rect.height = state->src_h >> 16;
4040 if (scaling_info->src_rect.height == 0)
4043 scaling_info->dst_rect.x = state->crtc_x;
4044 scaling_info->dst_rect.y = state->crtc_y;
4046 if (state->crtc_w == 0)
4049 scaling_info->dst_rect.width = state->crtc_w;
4051 if (state->crtc_h == 0)
4054 scaling_info->dst_rect.height = state->crtc_h;
4056 /* DRM doesn't specify clipping on destination output. */
4057 scaling_info->clip_rect = scaling_info->dst_rect;
4059 /* Validate scaling per-format with DC plane caps */
4060 if (state->plane && state->plane->dev && state->fb) {
4061 get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
4062 &min_downscale, &max_upscale);
4064 min_downscale = 250;
4065 max_upscale = 16000;
4068 scale_w = scaling_info->dst_rect.width * 1000 /
4069 scaling_info->src_rect.width;
4071 if (scale_w < min_downscale || scale_w > max_upscale)
4074 scale_h = scaling_info->dst_rect.height * 1000 /
4075 scaling_info->src_rect.height;
4077 if (scale_h < min_downscale || scale_h > max_upscale)
4081 * The "scaling_quality" can be ignored for now, quality = 0 has DC
4082 * assume reasonable defaults based on the format.
4089 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
4090 uint64_t tiling_flags)
4092 /* Fill GFX8 params */
4093 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
4094 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
4096 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
4097 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
4098 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
4099 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
4100 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
4102 /* XXX fix me for VI */
4103 tiling_info->gfx8.num_banks = num_banks;
4104 tiling_info->gfx8.array_mode =
4105 DC_ARRAY_2D_TILED_THIN1;
4106 tiling_info->gfx8.tile_split = tile_split;
4107 tiling_info->gfx8.bank_width = bankw;
4108 tiling_info->gfx8.bank_height = bankh;
4109 tiling_info->gfx8.tile_aspect = mtaspect;
4110 tiling_info->gfx8.tile_mode =
4111 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
4112 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
4113 == DC_ARRAY_1D_TILED_THIN1) {
4114 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
4117 tiling_info->gfx8.pipe_config =
4118 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
4122 fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
4123 union dc_tiling_info *tiling_info)
4125 tiling_info->gfx9.num_pipes =
4126 adev->gfx.config.gb_addr_config_fields.num_pipes;
4127 tiling_info->gfx9.num_banks =
4128 adev->gfx.config.gb_addr_config_fields.num_banks;
4129 tiling_info->gfx9.pipe_interleave =
4130 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
4131 tiling_info->gfx9.num_shader_engines =
4132 adev->gfx.config.gb_addr_config_fields.num_se;
4133 tiling_info->gfx9.max_compressed_frags =
4134 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
4135 tiling_info->gfx9.num_rb_per_se =
4136 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
4137 tiling_info->gfx9.shaderEnable = 1;
4138 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4139 adev->asic_type == CHIP_NAVY_FLOUNDER ||
4140 adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
4141 adev->asic_type == CHIP_VANGOGH)
4142 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
4146 validate_dcc(struct amdgpu_device *adev,
4147 const enum surface_pixel_format format,
4148 const enum dc_rotation_angle rotation,
4149 const union dc_tiling_info *tiling_info,
4150 const struct dc_plane_dcc_param *dcc,
4151 const struct dc_plane_address *address,
4152 const struct plane_size *plane_size)
4154 struct dc *dc = adev->dm.dc;
4155 struct dc_dcc_surface_param input;
4156 struct dc_surface_dcc_cap output;
4158 memset(&input, 0, sizeof(input));
4159 memset(&output, 0, sizeof(output));
4164 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
4165 !dc->cap_funcs.get_dcc_compression_cap)
4168 input.format = format;
4169 input.surface_size.width = plane_size->surface_size.width;
4170 input.surface_size.height = plane_size->surface_size.height;
4171 input.swizzle_mode = tiling_info->gfx9.swizzle;
4173 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
4174 input.scan = SCAN_DIRECTION_HORIZONTAL;
4175 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
4176 input.scan = SCAN_DIRECTION_VERTICAL;
4178 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
4181 if (!output.capable)
4184 if (dcc->independent_64b_blks == 0 &&
4185 output.grph.rgb.independent_64b_blks != 0)
4192 modifier_has_dcc(uint64_t modifier)
4194 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
4198 modifier_gfx9_swizzle_mode(uint64_t modifier)
4200 if (modifier == DRM_FORMAT_MOD_LINEAR)
4203 return AMD_FMT_MOD_GET(TILE, modifier);
4206 static const struct drm_format_info *
4207 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
4209 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
4213 fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
4214 union dc_tiling_info *tiling_info,
4217 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
4218 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
4219 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
4220 unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
4222 fill_gfx9_tiling_info_from_device(adev, tiling_info);
4224 if (!IS_AMD_FMT_MOD(modifier))
4227 tiling_info->gfx9.num_pipes = 1u << pipes_log2;
4228 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
4230 if (adev->family >= AMDGPU_FAMILY_NV) {
4231 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
4233 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
4235 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
4239 enum dm_micro_swizzle {
4240 MICRO_SWIZZLE_Z = 0,
4241 MICRO_SWIZZLE_S = 1,
4242 MICRO_SWIZZLE_D = 2,
4246 static bool dm_plane_format_mod_supported(struct drm_plane *plane,
4250 struct amdgpu_device *adev = drm_to_adev(plane->dev);
4251 const struct drm_format_info *info = drm_format_info(format);
4254 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
4260 * We always have to allow these modifiers:
4261 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers.
4262 * 2. Not passing any modifiers is the same as explicitly passing INVALID.
4264 if (modifier == DRM_FORMAT_MOD_LINEAR ||
4265 modifier == DRM_FORMAT_MOD_INVALID) {
4269 /* Check that the modifier is on the list of the plane's supported modifiers. */
4270 for (i = 0; i < plane->modifier_count; i++) {
4271 if (modifier == plane->modifiers[i])
4274 if (i == plane->modifier_count)
4278 * For D swizzle the canonical modifier depends on the bpp, so check
4281 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
4282 adev->family >= AMDGPU_FAMILY_NV) {
4283 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
4287 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
4291 if (modifier_has_dcc(modifier)) {
4292 /* Per radeonsi comments 16/64 bpp are more complicated. */
4293 if (info->cpp[0] != 4)
4295 /* We support multi-planar formats, but not when combined with
4296 * additional DCC metadata planes. */
4297 if (info->num_planes > 1)
4305 add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
4310 if (*cap - *size < 1) {
4311 uint64_t new_cap = *cap * 2;
4312 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
4320 memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
4326 (*mods)[*size] = mod;
4331 add_gfx9_modifiers(const struct amdgpu_device *adev,
4332 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4334 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4335 int pipe_xor_bits = min(8, pipes +
4336 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
4337 int bank_xor_bits = min(8 - pipe_xor_bits,
4338 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
4339 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
4340 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
4343 if (adev->family == AMDGPU_FAMILY_RV) {
4344 /* Raven2 and later */
4345 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
4348 * No _D DCC swizzles yet because we only allow 32bpp, which
4349 * doesn't support _D on DCN
4352 if (has_constant_encode) {
4353 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4354 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4355 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4356 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4357 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4358 AMD_FMT_MOD_SET(DCC, 1) |
4359 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4360 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4361 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
4364 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4365 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4366 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4367 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4368 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4369 AMD_FMT_MOD_SET(DCC, 1) |
4370 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4371 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4372 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
4374 if (has_constant_encode) {
4375 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4376 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4377 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4378 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4379 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4380 AMD_FMT_MOD_SET(DCC, 1) |
4381 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4382 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4383 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4385 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4386 AMD_FMT_MOD_SET(RB, rb) |
4387 AMD_FMT_MOD_SET(PIPE, pipes));
4390 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4391 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4392 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4393 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4394 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4395 AMD_FMT_MOD_SET(DCC, 1) |
4396 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4397 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4398 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4399 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
4400 AMD_FMT_MOD_SET(RB, rb) |
4401 AMD_FMT_MOD_SET(PIPE, pipes));
4405 * Only supported for 64bpp on Raven, will be filtered on format in
4406 * dm_plane_format_mod_supported.
4408 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4409 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
4410 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4411 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4412 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4414 if (adev->family == AMDGPU_FAMILY_RV) {
4415 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4416 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4417 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4418 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4419 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4423 * Only supported for 64bpp on Raven, will be filtered on format in
4424 * dm_plane_format_mod_supported.
4426 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4427 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4428 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4430 if (adev->family == AMDGPU_FAMILY_RV) {
4431 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4432 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4433 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4438 add_gfx10_1_modifiers(const struct amdgpu_device *adev,
4439 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4441 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4443 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4444 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4445 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4446 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4447 AMD_FMT_MOD_SET(DCC, 1) |
4448 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4449 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4450 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4452 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4453 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4454 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4455 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4456 AMD_FMT_MOD_SET(DCC, 1) |
4457 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4458 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4459 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4460 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4462 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4463 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4464 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4465 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4467 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4468 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4469 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4470 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4473 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4474 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4475 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4476 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4478 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4479 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4480 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4484 add_gfx10_3_modifiers(const struct amdgpu_device *adev,
4485 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4487 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4488 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
4490 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4491 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4492 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4493 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4494 AMD_FMT_MOD_SET(PACKERS, pkrs) |
4495 AMD_FMT_MOD_SET(DCC, 1) |
4496 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4497 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4498 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4499 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4501 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4502 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4503 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4504 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4505 AMD_FMT_MOD_SET(PACKERS, pkrs) |
4506 AMD_FMT_MOD_SET(DCC, 1) |
4507 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4508 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4509 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4510 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4511 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4513 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4514 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4515 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4516 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4517 AMD_FMT_MOD_SET(PACKERS, pkrs));
4519 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4520 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4521 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4522 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4523 AMD_FMT_MOD_SET(PACKERS, pkrs));
4525 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4526 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4527 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4528 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4530 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4531 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4532 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4536 get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
4538 uint64_t size = 0, capacity = 128;
4541 /* We have not hooked up any pre-GFX9 modifiers. */
4542 if (adev->family < AMDGPU_FAMILY_AI)
4545 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
4547 if (plane_type == DRM_PLANE_TYPE_CURSOR) {
4548 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4549 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4550 return *mods ? 0 : -ENOMEM;
4553 switch (adev->family) {
4554 case AMDGPU_FAMILY_AI:
4555 case AMDGPU_FAMILY_RV:
4556 add_gfx9_modifiers(adev, mods, &size, &capacity);
4558 case AMDGPU_FAMILY_NV:
4559 case AMDGPU_FAMILY_VGH:
4560 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4561 add_gfx10_3_modifiers(adev, mods, &size, &capacity);
4563 add_gfx10_1_modifiers(adev, mods, &size, &capacity);
4567 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4569 /* INVALID marks the end of the list. */
4570 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4579 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
4580 const struct amdgpu_framebuffer *afb,
4581 const enum surface_pixel_format format,
4582 const enum dc_rotation_angle rotation,
4583 const struct plane_size *plane_size,
4584 union dc_tiling_info *tiling_info,
4585 struct dc_plane_dcc_param *dcc,
4586 struct dc_plane_address *address,
4587 const bool force_disable_dcc)
4589 const uint64_t modifier = afb->base.modifier;
4592 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
4593 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
4595 if (modifier_has_dcc(modifier) && !force_disable_dcc) {
4596 uint64_t dcc_address = afb->address + afb->base.offsets[1];
4599 dcc->meta_pitch = afb->base.pitches[1];
4600 dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
4602 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
4603 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
4606 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
4614 fill_plane_buffer_attributes(struct amdgpu_device *adev,
4615 const struct amdgpu_framebuffer *afb,
4616 const enum surface_pixel_format format,
4617 const enum dc_rotation_angle rotation,
4618 const uint64_t tiling_flags,
4619 union dc_tiling_info *tiling_info,
4620 struct plane_size *plane_size,
4621 struct dc_plane_dcc_param *dcc,
4622 struct dc_plane_address *address,
4624 bool force_disable_dcc)
4626 const struct drm_framebuffer *fb = &afb->base;
4629 memset(tiling_info, 0, sizeof(*tiling_info));
4630 memset(plane_size, 0, sizeof(*plane_size));
4631 memset(dcc, 0, sizeof(*dcc));
4632 memset(address, 0, sizeof(*address));
4634 address->tmz_surface = tmz_surface;
4636 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
4637 uint64_t addr = afb->address + fb->offsets[0];
4639 plane_size->surface_size.x = 0;
4640 plane_size->surface_size.y = 0;
4641 plane_size->surface_size.width = fb->width;
4642 plane_size->surface_size.height = fb->height;
4643 plane_size->surface_pitch =
4644 fb->pitches[0] / fb->format->cpp[0];
4646 address->type = PLN_ADDR_TYPE_GRAPHICS;
4647 address->grph.addr.low_part = lower_32_bits(addr);
4648 address->grph.addr.high_part = upper_32_bits(addr);
4649 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
4650 uint64_t luma_addr = afb->address + fb->offsets[0];
4651 uint64_t chroma_addr = afb->address + fb->offsets[1];
4653 plane_size->surface_size.x = 0;
4654 plane_size->surface_size.y = 0;
4655 plane_size->surface_size.width = fb->width;
4656 plane_size->surface_size.height = fb->height;
4657 plane_size->surface_pitch =
4658 fb->pitches[0] / fb->format->cpp[0];
4660 plane_size->chroma_size.x = 0;
4661 plane_size->chroma_size.y = 0;
4662 /* TODO: set these based on surface format */
4663 plane_size->chroma_size.width = fb->width / 2;
4664 plane_size->chroma_size.height = fb->height / 2;
4666 plane_size->chroma_pitch =
4667 fb->pitches[1] / fb->format->cpp[1];
4669 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
4670 address->video_progressive.luma_addr.low_part =
4671 lower_32_bits(luma_addr);
4672 address->video_progressive.luma_addr.high_part =
4673 upper_32_bits(luma_addr);
4674 address->video_progressive.chroma_addr.low_part =
4675 lower_32_bits(chroma_addr);
4676 address->video_progressive.chroma_addr.high_part =
4677 upper_32_bits(chroma_addr);
4680 if (adev->family >= AMDGPU_FAMILY_AI) {
4681 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
4682 rotation, plane_size,
4689 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
4696 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
4697 bool *per_pixel_alpha, bool *global_alpha,
4698 int *global_alpha_value)
4700 *per_pixel_alpha = false;
4701 *global_alpha = false;
4702 *global_alpha_value = 0xff;
4704 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
4707 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
4708 static const uint32_t alpha_formats[] = {
4709 DRM_FORMAT_ARGB8888,
4710 DRM_FORMAT_RGBA8888,
4711 DRM_FORMAT_ABGR8888,
4713 uint32_t format = plane_state->fb->format->format;
4716 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
4717 if (format == alpha_formats[i]) {
4718 *per_pixel_alpha = true;
4724 if (plane_state->alpha < 0xffff) {
4725 *global_alpha = true;
4726 *global_alpha_value = plane_state->alpha >> 8;
4731 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4732 const enum surface_pixel_format format,
4733 enum dc_color_space *color_space)
4737 *color_space = COLOR_SPACE_SRGB;
4739 /* DRM color properties only affect non-RGB formats. */
4740 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4743 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4745 switch (plane_state->color_encoding) {
4746 case DRM_COLOR_YCBCR_BT601:
4748 *color_space = COLOR_SPACE_YCBCR601;
4750 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4753 case DRM_COLOR_YCBCR_BT709:
4755 *color_space = COLOR_SPACE_YCBCR709;
4757 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4760 case DRM_COLOR_YCBCR_BT2020:
4762 *color_space = COLOR_SPACE_2020_YCBCR;
4775 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4776 const struct drm_plane_state *plane_state,
4777 const uint64_t tiling_flags,
4778 struct dc_plane_info *plane_info,
4779 struct dc_plane_address *address,
4781 bool force_disable_dcc)
4783 const struct drm_framebuffer *fb = plane_state->fb;
4784 const struct amdgpu_framebuffer *afb =
4785 to_amdgpu_framebuffer(plane_state->fb);
4788 memset(plane_info, 0, sizeof(*plane_info));
4790 switch (fb->format->format) {
4792 plane_info->format =
4793 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4795 case DRM_FORMAT_RGB565:
4796 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4798 case DRM_FORMAT_XRGB8888:
4799 case DRM_FORMAT_ARGB8888:
4800 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4802 case DRM_FORMAT_XRGB2101010:
4803 case DRM_FORMAT_ARGB2101010:
4804 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4806 case DRM_FORMAT_XBGR2101010:
4807 case DRM_FORMAT_ABGR2101010:
4808 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4810 case DRM_FORMAT_XBGR8888:
4811 case DRM_FORMAT_ABGR8888:
4812 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4814 case DRM_FORMAT_NV21:
4815 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4817 case DRM_FORMAT_NV12:
4818 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4820 case DRM_FORMAT_P010:
4821 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4823 case DRM_FORMAT_XRGB16161616F:
4824 case DRM_FORMAT_ARGB16161616F:
4825 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4827 case DRM_FORMAT_XBGR16161616F:
4828 case DRM_FORMAT_ABGR16161616F:
4829 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4833 "Unsupported screen format %p4cc\n",
4834 &fb->format->format);
4838 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4839 case DRM_MODE_ROTATE_0:
4840 plane_info->rotation = ROTATION_ANGLE_0;
4842 case DRM_MODE_ROTATE_90:
4843 plane_info->rotation = ROTATION_ANGLE_90;
4845 case DRM_MODE_ROTATE_180:
4846 plane_info->rotation = ROTATION_ANGLE_180;
4848 case DRM_MODE_ROTATE_270:
4849 plane_info->rotation = ROTATION_ANGLE_270;
4852 plane_info->rotation = ROTATION_ANGLE_0;
4856 plane_info->visible = true;
4857 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4859 plane_info->layer_index = 0;
4861 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4862 &plane_info->color_space);
4866 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4867 plane_info->rotation, tiling_flags,
4868 &plane_info->tiling_info,
4869 &plane_info->plane_size,
4870 &plane_info->dcc, address, tmz_surface,
4875 fill_blending_from_plane_state(
4876 plane_state, &plane_info->per_pixel_alpha,
4877 &plane_info->global_alpha, &plane_info->global_alpha_value);
4882 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4883 struct dc_plane_state *dc_plane_state,
4884 struct drm_plane_state *plane_state,
4885 struct drm_crtc_state *crtc_state)
4887 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4888 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4889 struct dc_scaling_info scaling_info;
4890 struct dc_plane_info plane_info;
4892 bool force_disable_dcc = false;
4894 ret = fill_dc_scaling_info(plane_state, &scaling_info);
4898 dc_plane_state->src_rect = scaling_info.src_rect;
4899 dc_plane_state->dst_rect = scaling_info.dst_rect;
4900 dc_plane_state->clip_rect = scaling_info.clip_rect;
4901 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4903 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4904 ret = fill_dc_plane_info_and_addr(adev, plane_state,
4907 &dc_plane_state->address,
4913 dc_plane_state->format = plane_info.format;
4914 dc_plane_state->color_space = plane_info.color_space;
4915 dc_plane_state->format = plane_info.format;
4916 dc_plane_state->plane_size = plane_info.plane_size;
4917 dc_plane_state->rotation = plane_info.rotation;
4918 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4919 dc_plane_state->stereo_format = plane_info.stereo_format;
4920 dc_plane_state->tiling_info = plane_info.tiling_info;
4921 dc_plane_state->visible = plane_info.visible;
4922 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4923 dc_plane_state->global_alpha = plane_info.global_alpha;
4924 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4925 dc_plane_state->dcc = plane_info.dcc;
4926 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
4927 dc_plane_state->flip_int_enabled = true;
4930 * Always set input transfer function, since plane state is refreshed
4933 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4940 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4941 const struct dm_connector_state *dm_state,
4942 struct dc_stream_state *stream)
4944 enum amdgpu_rmx_type rmx_type;
4946 struct rect src = { 0 }; /* viewport in composition space*/
4947 struct rect dst = { 0 }; /* stream addressable area */
4949 /* no mode. nothing to be done */
4953 /* Full screen scaling by default */
4954 src.width = mode->hdisplay;
4955 src.height = mode->vdisplay;
4956 dst.width = stream->timing.h_addressable;
4957 dst.height = stream->timing.v_addressable;
4960 rmx_type = dm_state->scaling;
4961 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4962 if (src.width * dst.height <
4963 src.height * dst.width) {
4964 /* height needs less upscaling/more downscaling */
4965 dst.width = src.width *
4966 dst.height / src.height;
4968 /* width needs less upscaling/more downscaling */
4969 dst.height = src.height *
4970 dst.width / src.width;
4972 } else if (rmx_type == RMX_CENTER) {
4976 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4977 dst.y = (stream->timing.v_addressable - dst.height) / 2;
4979 if (dm_state->underscan_enable) {
4980 dst.x += dm_state->underscan_hborder / 2;
4981 dst.y += dm_state->underscan_vborder / 2;
4982 dst.width -= dm_state->underscan_hborder;
4983 dst.height -= dm_state->underscan_vborder;
4990 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
4991 dst.x, dst.y, dst.width, dst.height);
4995 static enum dc_color_depth
4996 convert_color_depth_from_display_info(const struct drm_connector *connector,
4997 bool is_y420, int requested_bpc)
5004 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5005 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5007 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5009 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5012 bpc = (uint8_t)connector->display_info.bpc;
5013 /* Assume 8 bpc by default if no bpc is specified. */
5014 bpc = bpc ? bpc : 8;
5017 if (requested_bpc > 0) {
5019 * Cap display bpc based on the user requested value.
5021 * The value for state->max_bpc may not correctly updated
5022 * depending on when the connector gets added to the state
5023 * or if this was called outside of atomic check, so it
5024 * can't be used directly.
5026 bpc = min_t(u8, bpc, requested_bpc);
5028 /* Round down to the nearest even number. */
5029 bpc = bpc - (bpc & 1);
5035 * Temporary Work around, DRM doesn't parse color depth for
5036 * EDID revision before 1.4
5037 * TODO: Fix edid parsing
5039 return COLOR_DEPTH_888;
5041 return COLOR_DEPTH_666;
5043 return COLOR_DEPTH_888;
5045 return COLOR_DEPTH_101010;
5047 return COLOR_DEPTH_121212;
5049 return COLOR_DEPTH_141414;
5051 return COLOR_DEPTH_161616;
5053 return COLOR_DEPTH_UNDEFINED;
5057 static enum dc_aspect_ratio
5058 get_aspect_ratio(const struct drm_display_mode *mode_in)
5060 /* 1-1 mapping, since both enums follow the HDMI spec. */
5061 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5064 static enum dc_color_space
5065 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5067 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5069 switch (dc_crtc_timing->pixel_encoding) {
5070 case PIXEL_ENCODING_YCBCR422:
5071 case PIXEL_ENCODING_YCBCR444:
5072 case PIXEL_ENCODING_YCBCR420:
5075 * 27030khz is the separation point between HDTV and SDTV
5076 * according to HDMI spec, we use YCbCr709 and YCbCr601
5079 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5080 if (dc_crtc_timing->flags.Y_ONLY)
5082 COLOR_SPACE_YCBCR709_LIMITED;
5084 color_space = COLOR_SPACE_YCBCR709;
5086 if (dc_crtc_timing->flags.Y_ONLY)
5088 COLOR_SPACE_YCBCR601_LIMITED;
5090 color_space = COLOR_SPACE_YCBCR601;
5095 case PIXEL_ENCODING_RGB:
5096 color_space = COLOR_SPACE_SRGB;
5107 static bool adjust_colour_depth_from_display_info(
5108 struct dc_crtc_timing *timing_out,
5109 const struct drm_display_info *info)
5111 enum dc_color_depth depth = timing_out->display_color_depth;
5114 normalized_clk = timing_out->pix_clk_100hz / 10;
5115 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5116 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5117 normalized_clk /= 2;
5118 /* Adjusting pix clock following on HDMI spec based on colour depth */
5120 case COLOR_DEPTH_888:
5122 case COLOR_DEPTH_101010:
5123 normalized_clk = (normalized_clk * 30) / 24;
5125 case COLOR_DEPTH_121212:
5126 normalized_clk = (normalized_clk * 36) / 24;
5128 case COLOR_DEPTH_161616:
5129 normalized_clk = (normalized_clk * 48) / 24;
5132 /* The above depths are the only ones valid for HDMI. */
5135 if (normalized_clk <= info->max_tmds_clock) {
5136 timing_out->display_color_depth = depth;
5139 } while (--depth > COLOR_DEPTH_666);
5143 static void fill_stream_properties_from_drm_display_mode(
5144 struct dc_stream_state *stream,
5145 const struct drm_display_mode *mode_in,
5146 const struct drm_connector *connector,
5147 const struct drm_connector_state *connector_state,
5148 const struct dc_stream_state *old_stream,
5151 struct dc_crtc_timing *timing_out = &stream->timing;
5152 const struct drm_display_info *info = &connector->display_info;
5153 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5154 struct hdmi_vendor_infoframe hv_frame;
5155 struct hdmi_avi_infoframe avi_frame;
5157 memset(&hv_frame, 0, sizeof(hv_frame));
5158 memset(&avi_frame, 0, sizeof(avi_frame));
5160 timing_out->h_border_left = 0;
5161 timing_out->h_border_right = 0;
5162 timing_out->v_border_top = 0;
5163 timing_out->v_border_bottom = 0;
5164 /* TODO: un-hardcode */
5165 if (drm_mode_is_420_only(info, mode_in)
5166 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5167 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5168 else if (drm_mode_is_420_also(info, mode_in)
5169 && aconnector->force_yuv420_output)
5170 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5171 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
5172 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5173 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5175 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5177 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5178 timing_out->display_color_depth = convert_color_depth_from_display_info(
5180 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5182 timing_out->scan_type = SCANNING_TYPE_NODATA;
5183 timing_out->hdmi_vic = 0;
5186 timing_out->vic = old_stream->timing.vic;
5187 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5188 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5190 timing_out->vic = drm_match_cea_mode(mode_in);
5191 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5192 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5193 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5194 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5197 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5198 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5199 timing_out->vic = avi_frame.video_code;
5200 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5201 timing_out->hdmi_vic = hv_frame.vic;
5204 if (is_freesync_video_mode(mode_in, aconnector)) {
5205 timing_out->h_addressable = mode_in->hdisplay;
5206 timing_out->h_total = mode_in->htotal;
5207 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5208 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5209 timing_out->v_total = mode_in->vtotal;
5210 timing_out->v_addressable = mode_in->vdisplay;
5211 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5212 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5213 timing_out->pix_clk_100hz = mode_in->clock * 10;
5215 timing_out->h_addressable = mode_in->crtc_hdisplay;
5216 timing_out->h_total = mode_in->crtc_htotal;
5217 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5218 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5219 timing_out->v_total = mode_in->crtc_vtotal;
5220 timing_out->v_addressable = mode_in->crtc_vdisplay;
5221 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5222 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5223 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5226 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5228 stream->output_color_space = get_output_color_space(timing_out);
5230 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5231 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5232 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5233 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5234 drm_mode_is_420_also(info, mode_in) &&
5235 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5236 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5237 adjust_colour_depth_from_display_info(timing_out, info);
5242 static void fill_audio_info(struct audio_info *audio_info,
5243 const struct drm_connector *drm_connector,
5244 const struct dc_sink *dc_sink)
5247 int cea_revision = 0;
5248 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5250 audio_info->manufacture_id = edid_caps->manufacturer_id;
5251 audio_info->product_id = edid_caps->product_id;
5253 cea_revision = drm_connector->display_info.cea_rev;
5255 strscpy(audio_info->display_name,
5256 edid_caps->display_name,
5257 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5259 if (cea_revision >= 3) {
5260 audio_info->mode_count = edid_caps->audio_mode_count;
5262 for (i = 0; i < audio_info->mode_count; ++i) {
5263 audio_info->modes[i].format_code =
5264 (enum audio_format_code)
5265 (edid_caps->audio_modes[i].format_code);
5266 audio_info->modes[i].channel_count =
5267 edid_caps->audio_modes[i].channel_count;
5268 audio_info->modes[i].sample_rates.all =
5269 edid_caps->audio_modes[i].sample_rate;
5270 audio_info->modes[i].sample_size =
5271 edid_caps->audio_modes[i].sample_size;
5275 audio_info->flags.all = edid_caps->speaker_flags;
5277 /* TODO: We only check for the progressive mode, check for interlace mode too */
5278 if (drm_connector->latency_present[0]) {
5279 audio_info->video_latency = drm_connector->video_latency[0];
5280 audio_info->audio_latency = drm_connector->audio_latency[0];
5283 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5288 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5289 struct drm_display_mode *dst_mode)
5291 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5292 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5293 dst_mode->crtc_clock = src_mode->crtc_clock;
5294 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5295 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5296 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5297 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5298 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5299 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5300 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5301 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5302 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5303 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5304 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5308 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5309 const struct drm_display_mode *native_mode,
5312 if (scale_enabled) {
5313 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5314 } else if (native_mode->clock == drm_mode->clock &&
5315 native_mode->htotal == drm_mode->htotal &&
5316 native_mode->vtotal == drm_mode->vtotal) {
5317 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5319 /* no scaling nor amdgpu inserted, no need to patch */
5323 static struct dc_sink *
5324 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5326 struct dc_sink_init_data sink_init_data = { 0 };
5327 struct dc_sink *sink = NULL;
5328 sink_init_data.link = aconnector->dc_link;
5329 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5331 sink = dc_sink_create(&sink_init_data);
5333 DRM_ERROR("Failed to create sink!\n");
5336 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5341 static void set_multisync_trigger_params(
5342 struct dc_stream_state *stream)
5344 struct dc_stream_state *master = NULL;
5346 if (stream->triggered_crtc_reset.enabled) {
5347 master = stream->triggered_crtc_reset.event_source;
5348 stream->triggered_crtc_reset.event =
5349 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5350 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5351 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5355 static void set_master_stream(struct dc_stream_state *stream_set[],
5358 int j, highest_rfr = 0, master_stream = 0;
5360 for (j = 0; j < stream_count; j++) {
5361 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5362 int refresh_rate = 0;
5364 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5365 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5366 if (refresh_rate > highest_rfr) {
5367 highest_rfr = refresh_rate;
5372 for (j = 0; j < stream_count; j++) {
5374 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5378 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5381 struct dc_stream_state *stream;
5383 if (context->stream_count < 2)
5385 for (i = 0; i < context->stream_count ; i++) {
5386 if (!context->streams[i])
5389 * TODO: add a function to read AMD VSDB bits and set
5390 * crtc_sync_master.multi_sync_enabled flag
5391 * For now it's set to false
5395 set_master_stream(context->streams, context->stream_count);
5397 for (i = 0; i < context->stream_count ; i++) {
5398 stream = context->streams[i];
5403 set_multisync_trigger_params(stream);
5407 static struct drm_display_mode *
5408 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5409 bool use_probed_modes)
5411 struct drm_display_mode *m, *m_pref = NULL;
5412 u16 current_refresh, highest_refresh;
5413 struct list_head *list_head = use_probed_modes ?
5414 &aconnector->base.probed_modes :
5415 &aconnector->base.modes;
5417 if (aconnector->freesync_vid_base.clock != 0)
5418 return &aconnector->freesync_vid_base;
5420 /* Find the preferred mode */
5421 list_for_each_entry (m, list_head, head) {
5422 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5429 /* Probably an EDID with no preferred mode. Fallback to first entry */
5430 m_pref = list_first_entry_or_null(
5431 &aconnector->base.modes, struct drm_display_mode, head);
5433 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5438 highest_refresh = drm_mode_vrefresh(m_pref);
5441 * Find the mode with highest refresh rate with same resolution.
5442 * For some monitors, preferred mode is not the mode with highest
5443 * supported refresh rate.
5445 list_for_each_entry (m, list_head, head) {
5446 current_refresh = drm_mode_vrefresh(m);
5448 if (m->hdisplay == m_pref->hdisplay &&
5449 m->vdisplay == m_pref->vdisplay &&
5450 highest_refresh < current_refresh) {
5451 highest_refresh = current_refresh;
5456 aconnector->freesync_vid_base = *m_pref;
5460 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5461 struct amdgpu_dm_connector *aconnector)
5463 struct drm_display_mode *high_mode;
5466 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5467 if (!high_mode || !mode)
5470 timing_diff = high_mode->vtotal - mode->vtotal;
5472 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5473 high_mode->hdisplay != mode->hdisplay ||
5474 high_mode->vdisplay != mode->vdisplay ||
5475 high_mode->hsync_start != mode->hsync_start ||
5476 high_mode->hsync_end != mode->hsync_end ||
5477 high_mode->htotal != mode->htotal ||
5478 high_mode->hskew != mode->hskew ||
5479 high_mode->vscan != mode->vscan ||
5480 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5481 high_mode->vsync_end - mode->vsync_end != timing_diff)
5487 static struct dc_stream_state *
5488 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5489 const struct drm_display_mode *drm_mode,
5490 const struct dm_connector_state *dm_state,
5491 const struct dc_stream_state *old_stream,
5494 struct drm_display_mode *preferred_mode = NULL;
5495 struct drm_connector *drm_connector;
5496 const struct drm_connector_state *con_state =
5497 dm_state ? &dm_state->base : NULL;
5498 struct dc_stream_state *stream = NULL;
5499 struct drm_display_mode mode = *drm_mode;
5500 struct drm_display_mode saved_mode;
5501 struct drm_display_mode *freesync_mode = NULL;
5502 bool native_mode_found = false;
5503 bool recalculate_timing = false;
5504 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5506 int preferred_refresh = 0;
5507 #if defined(CONFIG_DRM_AMD_DC_DCN)
5508 struct dsc_dec_dpcd_caps dsc_caps;
5509 uint32_t link_bandwidth_kbps;
5511 struct dc_sink *sink = NULL;
5513 memset(&saved_mode, 0, sizeof(saved_mode));
5515 if (aconnector == NULL) {
5516 DRM_ERROR("aconnector is NULL!\n");
5520 drm_connector = &aconnector->base;
5522 if (!aconnector->dc_sink) {
5523 sink = create_fake_sink(aconnector);
5527 sink = aconnector->dc_sink;
5528 dc_sink_retain(sink);
5531 stream = dc_create_stream_for_sink(sink);
5533 if (stream == NULL) {
5534 DRM_ERROR("Failed to create stream for sink!\n");
5538 stream->dm_stream_context = aconnector;
5540 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5541 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5543 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5544 /* Search for preferred mode */
5545 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5546 native_mode_found = true;
5550 if (!native_mode_found)
5551 preferred_mode = list_first_entry_or_null(
5552 &aconnector->base.modes,
5553 struct drm_display_mode,
5556 mode_refresh = drm_mode_vrefresh(&mode);
5558 if (preferred_mode == NULL) {
5560 * This may not be an error, the use case is when we have no
5561 * usermode calls to reset and set mode upon hotplug. In this
5562 * case, we call set mode ourselves to restore the previous mode
5563 * and the modelist may not be filled in in time.
5565 DRM_DEBUG_DRIVER("No preferred mode found\n");
5567 recalculate_timing = amdgpu_freesync_vid_mode &&
5568 is_freesync_video_mode(&mode, aconnector);
5569 if (recalculate_timing) {
5570 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5572 mode = *freesync_mode;
5574 decide_crtc_timing_for_drm_display_mode(
5575 &mode, preferred_mode, scale);
5577 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5581 if (recalculate_timing)
5582 drm_mode_set_crtcinfo(&saved_mode, 0);
5584 drm_mode_set_crtcinfo(&mode, 0);
5587 * If scaling is enabled and refresh rate didn't change
5588 * we copy the vic and polarities of the old timings
5590 if (!scale || mode_refresh != preferred_refresh)
5591 fill_stream_properties_from_drm_display_mode(
5592 stream, &mode, &aconnector->base, con_state, NULL,
5595 fill_stream_properties_from_drm_display_mode(
5596 stream, &mode, &aconnector->base, con_state, old_stream,
5599 stream->timing.flags.DSC = 0;
5601 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5602 #if defined(CONFIG_DRM_AMD_DC_DCN)
5603 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5604 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5605 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5607 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5608 dc_link_get_link_cap(aconnector->dc_link));
5610 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) {
5611 /* Set DSC policy according to dsc_clock_en */
5612 dc_dsc_policy_set_enable_dsc_when_not_needed(
5613 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5615 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5617 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5619 link_bandwidth_kbps,
5621 &stream->timing.dsc_cfg))
5622 stream->timing.flags.DSC = 1;
5623 /* Overwrite the stream flag if DSC is enabled through debugfs */
5624 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5625 stream->timing.flags.DSC = 1;
5627 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5628 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5630 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5631 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5633 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5634 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5639 update_stream_scaling_settings(&mode, dm_state, stream);
5642 &stream->audio_info,
5646 update_stream_signal(stream, sink);
5648 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5649 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5651 if (stream->link->psr_settings.psr_feature_enabled) {
5653 // should decide stream support vsc sdp colorimetry capability
5654 // before building vsc info packet
5656 stream->use_vsc_sdp_for_colorimetry = false;
5657 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5658 stream->use_vsc_sdp_for_colorimetry =
5659 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5661 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5662 stream->use_vsc_sdp_for_colorimetry = true;
5664 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
5667 dc_sink_release(sink);
5672 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
5674 drm_crtc_cleanup(crtc);
5678 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
5679 struct drm_crtc_state *state)
5681 struct dm_crtc_state *cur = to_dm_crtc_state(state);
5683 /* TODO Destroy dc_stream objects are stream object is flattened */
5685 dc_stream_release(cur->stream);
5688 __drm_atomic_helper_crtc_destroy_state(state);
5694 static void dm_crtc_reset_state(struct drm_crtc *crtc)
5696 struct dm_crtc_state *state;
5699 dm_crtc_destroy_state(crtc, crtc->state);
5701 state = kzalloc(sizeof(*state), GFP_KERNEL);
5702 if (WARN_ON(!state))
5705 __drm_atomic_helper_crtc_reset(crtc, &state->base);
5708 static struct drm_crtc_state *
5709 dm_crtc_duplicate_state(struct drm_crtc *crtc)
5711 struct dm_crtc_state *state, *cur;
5713 cur = to_dm_crtc_state(crtc->state);
5715 if (WARN_ON(!crtc->state))
5718 state = kzalloc(sizeof(*state), GFP_KERNEL);
5722 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
5725 state->stream = cur->stream;
5726 dc_stream_retain(state->stream);
5729 state->active_planes = cur->active_planes;
5730 state->vrr_infopacket = cur->vrr_infopacket;
5731 state->abm_level = cur->abm_level;
5732 state->vrr_supported = cur->vrr_supported;
5733 state->freesync_config = cur->freesync_config;
5734 state->cm_has_degamma = cur->cm_has_degamma;
5735 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
5736 /* TODO Duplicate dc_stream after objects are stream object is flattened */
5738 return &state->base;
5741 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
5742 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
5744 crtc_debugfs_init(crtc);
5750 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
5752 enum dc_irq_source irq_source;
5753 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5754 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
5757 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
5759 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
5761 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
5762 acrtc->crtc_id, enable ? "en" : "dis", rc);
5766 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
5768 enum dc_irq_source irq_source;
5769 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5770 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
5771 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
5772 #if defined(CONFIG_DRM_AMD_DC_DCN)
5773 struct amdgpu_display_manager *dm = &adev->dm;
5774 unsigned long flags;
5779 /* vblank irq on -> Only need vupdate irq in vrr mode */
5780 if (amdgpu_dm_vrr_active(acrtc_state))
5781 rc = dm_set_vupdate_irq(crtc, true);
5783 /* vblank irq off -> vupdate irq off */
5784 rc = dm_set_vupdate_irq(crtc, false);
5790 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
5792 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
5795 if (amdgpu_in_reset(adev))
5798 #if defined(CONFIG_DRM_AMD_DC_DCN)
5799 spin_lock_irqsave(&dm->vblank_lock, flags);
5800 dm->vblank_workqueue->dm = dm;
5801 dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
5802 dm->vblank_workqueue->enable = enable;
5803 spin_unlock_irqrestore(&dm->vblank_lock, flags);
5804 schedule_work(&dm->vblank_workqueue->mall_work);
5810 static int dm_enable_vblank(struct drm_crtc *crtc)
5812 return dm_set_vblank(crtc, true);
5815 static void dm_disable_vblank(struct drm_crtc *crtc)
5817 dm_set_vblank(crtc, false);
5820 /* Implemented only the options currently availible for the driver */
5821 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
5822 .reset = dm_crtc_reset_state,
5823 .destroy = amdgpu_dm_crtc_destroy,
5824 .set_config = drm_atomic_helper_set_config,
5825 .page_flip = drm_atomic_helper_page_flip,
5826 .atomic_duplicate_state = dm_crtc_duplicate_state,
5827 .atomic_destroy_state = dm_crtc_destroy_state,
5828 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
5829 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
5830 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
5831 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
5832 .enable_vblank = dm_enable_vblank,
5833 .disable_vblank = dm_disable_vblank,
5834 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
5835 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
5836 .late_register = amdgpu_dm_crtc_late_register,
5840 static enum drm_connector_status
5841 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5844 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5848 * 1. This interface is NOT called in context of HPD irq.
5849 * 2. This interface *is called* in context of user-mode ioctl. Which
5850 * makes it a bad place for *any* MST-related activity.
5853 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5854 !aconnector->fake_enable)
5855 connected = (aconnector->dc_sink != NULL);
5857 connected = (aconnector->base.force == DRM_FORCE_ON);
5859 update_subconnector_property(aconnector);
5861 return (connected ? connector_status_connected :
5862 connector_status_disconnected);
5865 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5866 struct drm_connector_state *connector_state,
5867 struct drm_property *property,
5870 struct drm_device *dev = connector->dev;
5871 struct amdgpu_device *adev = drm_to_adev(dev);
5872 struct dm_connector_state *dm_old_state =
5873 to_dm_connector_state(connector->state);
5874 struct dm_connector_state *dm_new_state =
5875 to_dm_connector_state(connector_state);
5879 if (property == dev->mode_config.scaling_mode_property) {
5880 enum amdgpu_rmx_type rmx_type;
5883 case DRM_MODE_SCALE_CENTER:
5884 rmx_type = RMX_CENTER;
5886 case DRM_MODE_SCALE_ASPECT:
5887 rmx_type = RMX_ASPECT;
5889 case DRM_MODE_SCALE_FULLSCREEN:
5890 rmx_type = RMX_FULL;
5892 case DRM_MODE_SCALE_NONE:
5898 if (dm_old_state->scaling == rmx_type)
5901 dm_new_state->scaling = rmx_type;
5903 } else if (property == adev->mode_info.underscan_hborder_property) {
5904 dm_new_state->underscan_hborder = val;
5906 } else if (property == adev->mode_info.underscan_vborder_property) {
5907 dm_new_state->underscan_vborder = val;
5909 } else if (property == adev->mode_info.underscan_property) {
5910 dm_new_state->underscan_enable = val;
5912 } else if (property == adev->mode_info.abm_level_property) {
5913 dm_new_state->abm_level = val;
5920 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5921 const struct drm_connector_state *state,
5922 struct drm_property *property,
5925 struct drm_device *dev = connector->dev;
5926 struct amdgpu_device *adev = drm_to_adev(dev);
5927 struct dm_connector_state *dm_state =
5928 to_dm_connector_state(state);
5931 if (property == dev->mode_config.scaling_mode_property) {
5932 switch (dm_state->scaling) {
5934 *val = DRM_MODE_SCALE_CENTER;
5937 *val = DRM_MODE_SCALE_ASPECT;
5940 *val = DRM_MODE_SCALE_FULLSCREEN;
5944 *val = DRM_MODE_SCALE_NONE;
5948 } else if (property == adev->mode_info.underscan_hborder_property) {
5949 *val = dm_state->underscan_hborder;
5951 } else if (property == adev->mode_info.underscan_vborder_property) {
5952 *val = dm_state->underscan_vborder;
5954 } else if (property == adev->mode_info.underscan_property) {
5955 *val = dm_state->underscan_enable;
5957 } else if (property == adev->mode_info.abm_level_property) {
5958 *val = dm_state->abm_level;
5965 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5967 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5969 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5972 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5974 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5975 const struct dc_link *link = aconnector->dc_link;
5976 struct amdgpu_device *adev = drm_to_adev(connector->dev);
5977 struct amdgpu_display_manager *dm = &adev->dm;
5980 * Call only if mst_mgr was iniitalized before since it's not done
5981 * for all connector types.
5983 if (aconnector->mst_mgr.dev)
5984 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5986 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5987 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5989 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5990 link->type != dc_connection_none &&
5991 dm->backlight_dev) {
5992 backlight_device_unregister(dm->backlight_dev);
5993 dm->backlight_dev = NULL;
5997 if (aconnector->dc_em_sink)
5998 dc_sink_release(aconnector->dc_em_sink);
5999 aconnector->dc_em_sink = NULL;
6000 if (aconnector->dc_sink)
6001 dc_sink_release(aconnector->dc_sink);
6002 aconnector->dc_sink = NULL;
6004 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6005 drm_connector_unregister(connector);
6006 drm_connector_cleanup(connector);
6007 if (aconnector->i2c) {
6008 i2c_del_adapter(&aconnector->i2c->base);
6009 kfree(aconnector->i2c);
6011 kfree(aconnector->dm_dp_aux.aux.name);
6016 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6018 struct dm_connector_state *state =
6019 to_dm_connector_state(connector->state);
6021 if (connector->state)
6022 __drm_atomic_helper_connector_destroy_state(connector->state);
6026 state = kzalloc(sizeof(*state), GFP_KERNEL);
6029 state->scaling = RMX_OFF;
6030 state->underscan_enable = false;
6031 state->underscan_hborder = 0;
6032 state->underscan_vborder = 0;
6033 state->base.max_requested_bpc = 8;
6034 state->vcpi_slots = 0;
6036 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6037 state->abm_level = amdgpu_dm_abm_level;
6039 __drm_atomic_helper_connector_reset(connector, &state->base);
6043 struct drm_connector_state *
6044 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6046 struct dm_connector_state *state =
6047 to_dm_connector_state(connector->state);
6049 struct dm_connector_state *new_state =
6050 kmemdup(state, sizeof(*state), GFP_KERNEL);
6055 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6057 new_state->freesync_capable = state->freesync_capable;
6058 new_state->abm_level = state->abm_level;
6059 new_state->scaling = state->scaling;
6060 new_state->underscan_enable = state->underscan_enable;
6061 new_state->underscan_hborder = state->underscan_hborder;
6062 new_state->underscan_vborder = state->underscan_vborder;
6063 new_state->vcpi_slots = state->vcpi_slots;
6064 new_state->pbn = state->pbn;
6065 return &new_state->base;
6069 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6071 struct amdgpu_dm_connector *amdgpu_dm_connector =
6072 to_amdgpu_dm_connector(connector);
6075 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6076 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6077 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6078 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6083 #if defined(CONFIG_DEBUG_FS)
6084 connector_debugfs_init(amdgpu_dm_connector);
6090 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6091 .reset = amdgpu_dm_connector_funcs_reset,
6092 .detect = amdgpu_dm_connector_detect,
6093 .fill_modes = drm_helper_probe_single_connector_modes,
6094 .destroy = amdgpu_dm_connector_destroy,
6095 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6096 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6097 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6098 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6099 .late_register = amdgpu_dm_connector_late_register,
6100 .early_unregister = amdgpu_dm_connector_unregister
6103 static int get_modes(struct drm_connector *connector)
6105 return amdgpu_dm_connector_get_modes(connector);
6108 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6110 struct dc_sink_init_data init_params = {
6111 .link = aconnector->dc_link,
6112 .sink_signal = SIGNAL_TYPE_VIRTUAL
6116 if (!aconnector->base.edid_blob_ptr) {
6117 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6118 aconnector->base.name);
6120 aconnector->base.force = DRM_FORCE_OFF;
6121 aconnector->base.override_edid = false;
6125 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6127 aconnector->edid = edid;
6129 aconnector->dc_em_sink = dc_link_add_remote_sink(
6130 aconnector->dc_link,
6132 (edid->extensions + 1) * EDID_LENGTH,
6135 if (aconnector->base.force == DRM_FORCE_ON) {
6136 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6137 aconnector->dc_link->local_sink :
6138 aconnector->dc_em_sink;
6139 dc_sink_retain(aconnector->dc_sink);
6143 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6145 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6148 * In case of headless boot with force on for DP managed connector
6149 * Those settings have to be != 0 to get initial modeset
6151 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6152 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6153 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6157 aconnector->base.override_edid = true;
6158 create_eml_sink(aconnector);
6161 static struct dc_stream_state *
6162 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6163 const struct drm_display_mode *drm_mode,
6164 const struct dm_connector_state *dm_state,
6165 const struct dc_stream_state *old_stream)
6167 struct drm_connector *connector = &aconnector->base;
6168 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6169 struct dc_stream_state *stream;
6170 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6171 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6172 enum dc_status dc_result = DC_OK;
6175 stream = create_stream_for_sink(aconnector, drm_mode,
6176 dm_state, old_stream,
6178 if (stream == NULL) {
6179 DRM_ERROR("Failed to create stream for sink!\n");
6183 dc_result = dc_validate_stream(adev->dm.dc, stream);
6185 if (dc_result != DC_OK) {
6186 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6191 dc_status_to_str(dc_result));
6193 dc_stream_release(stream);
6195 requested_bpc -= 2; /* lower bpc to retry validation */
6198 } while (stream == NULL && requested_bpc >= 6);
6200 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6201 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6203 aconnector->force_yuv420_output = true;
6204 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6205 dm_state, old_stream);
6206 aconnector->force_yuv420_output = false;
6212 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6213 struct drm_display_mode *mode)
6215 int result = MODE_ERROR;
6216 struct dc_sink *dc_sink;
6217 /* TODO: Unhardcode stream count */
6218 struct dc_stream_state *stream;
6219 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6221 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6222 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6226 * Only run this the first time mode_valid is called to initilialize
6229 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6230 !aconnector->dc_em_sink)
6231 handle_edid_mgmt(aconnector);
6233 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6235 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6236 aconnector->base.force != DRM_FORCE_ON) {
6237 DRM_ERROR("dc_sink is NULL!\n");
6241 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6243 dc_stream_release(stream);
6248 /* TODO: error handling*/
6252 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6253 struct dc_info_packet *out)
6255 struct hdmi_drm_infoframe frame;
6256 unsigned char buf[30]; /* 26 + 4 */
6260 memset(out, 0, sizeof(*out));
6262 if (!state->hdr_output_metadata)
6265 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6269 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6273 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6277 /* Prepare the infopacket for DC. */
6278 switch (state->connector->connector_type) {
6279 case DRM_MODE_CONNECTOR_HDMIA:
6280 out->hb0 = 0x87; /* type */
6281 out->hb1 = 0x01; /* version */
6282 out->hb2 = 0x1A; /* length */
6283 out->sb[0] = buf[3]; /* checksum */
6287 case DRM_MODE_CONNECTOR_DisplayPort:
6288 case DRM_MODE_CONNECTOR_eDP:
6289 out->hb0 = 0x00; /* sdp id, zero */
6290 out->hb1 = 0x87; /* type */
6291 out->hb2 = 0x1D; /* payload len - 1 */
6292 out->hb3 = (0x13 << 2); /* sdp version */
6293 out->sb[0] = 0x01; /* version */
6294 out->sb[1] = 0x1A; /* length */
6302 memcpy(&out->sb[i], &buf[4], 26);
6305 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6306 sizeof(out->sb), false);
6312 is_hdr_metadata_different(const struct drm_connector_state *old_state,
6313 const struct drm_connector_state *new_state)
6315 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
6316 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
6318 if (old_blob != new_blob) {
6319 if (old_blob && new_blob &&
6320 old_blob->length == new_blob->length)
6321 return memcmp(old_blob->data, new_blob->data,
6331 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6332 struct drm_atomic_state *state)
6334 struct drm_connector_state *new_con_state =
6335 drm_atomic_get_new_connector_state(state, conn);
6336 struct drm_connector_state *old_con_state =
6337 drm_atomic_get_old_connector_state(state, conn);
6338 struct drm_crtc *crtc = new_con_state->crtc;
6339 struct drm_crtc_state *new_crtc_state;
6342 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6347 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
6348 struct dc_info_packet hdr_infopacket;
6350 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6354 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6355 if (IS_ERR(new_crtc_state))
6356 return PTR_ERR(new_crtc_state);
6359 * DC considers the stream backends changed if the
6360 * static metadata changes. Forcing the modeset also
6361 * gives a simple way for userspace to switch from
6362 * 8bpc to 10bpc when setting the metadata to enter
6365 * Changing the static metadata after it's been
6366 * set is permissible, however. So only force a
6367 * modeset if we're entering or exiting HDR.
6369 new_crtc_state->mode_changed =
6370 !old_con_state->hdr_output_metadata ||
6371 !new_con_state->hdr_output_metadata;
6377 static const struct drm_connector_helper_funcs
6378 amdgpu_dm_connector_helper_funcs = {
6380 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6381 * modes will be filtered by drm_mode_validate_size(), and those modes
6382 * are missing after user start lightdm. So we need to renew modes list.
6383 * in get_modes call back, not just return the modes count
6385 .get_modes = get_modes,
6386 .mode_valid = amdgpu_dm_connector_mode_valid,
6387 .atomic_check = amdgpu_dm_connector_atomic_check,
6390 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
6394 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
6396 struct drm_atomic_state *state = new_crtc_state->state;
6397 struct drm_plane *plane;
6400 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
6401 struct drm_plane_state *new_plane_state;
6403 /* Cursor planes are "fake". */
6404 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6407 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
6409 if (!new_plane_state) {
6411 * The plane is enable on the CRTC and hasn't changed
6412 * state. This means that it previously passed
6413 * validation and is therefore enabled.
6419 /* We need a framebuffer to be considered enabled. */
6420 num_active += (new_plane_state->fb != NULL);
6426 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
6427 struct drm_crtc_state *new_crtc_state)
6429 struct dm_crtc_state *dm_new_crtc_state =
6430 to_dm_crtc_state(new_crtc_state);
6432 dm_new_crtc_state->active_planes = 0;
6434 if (!dm_new_crtc_state->stream)
6437 dm_new_crtc_state->active_planes =
6438 count_crtc_active_planes(new_crtc_state);
6441 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
6442 struct drm_atomic_state *state)
6444 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
6446 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
6447 struct dc *dc = adev->dm.dc;
6448 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
6451 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
6453 dm_update_crtc_active_planes(crtc, crtc_state);
6455 if (unlikely(!dm_crtc_state->stream &&
6456 modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {
6462 * We require the primary plane to be enabled whenever the CRTC is, otherwise
6463 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
6464 * planes are disabled, which is not supported by the hardware. And there is legacy
6465 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
6467 if (crtc_state->enable &&
6468 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
6469 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
6473 /* In some use cases, like reset, no stream is attached */
6474 if (!dm_crtc_state->stream)
6477 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
6480 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
6484 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
6485 const struct drm_display_mode *mode,
6486 struct drm_display_mode *adjusted_mode)
6491 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
6492 .disable = dm_crtc_helper_disable,
6493 .atomic_check = dm_crtc_helper_atomic_check,
6494 .mode_fixup = dm_crtc_helper_mode_fixup,
6495 .get_scanout_position = amdgpu_crtc_get_scanout_position,
6498 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6503 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
6505 switch (display_color_depth) {
6506 case COLOR_DEPTH_666:
6508 case COLOR_DEPTH_888:
6510 case COLOR_DEPTH_101010:
6512 case COLOR_DEPTH_121212:
6514 case COLOR_DEPTH_141414:
6516 case COLOR_DEPTH_161616:
6524 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6525 struct drm_crtc_state *crtc_state,
6526 struct drm_connector_state *conn_state)
6528 struct drm_atomic_state *state = crtc_state->state;
6529 struct drm_connector *connector = conn_state->connector;
6530 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6531 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6532 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6533 struct drm_dp_mst_topology_mgr *mst_mgr;
6534 struct drm_dp_mst_port *mst_port;
6535 enum dc_color_depth color_depth;
6537 bool is_y420 = false;
6539 if (!aconnector->port || !aconnector->dc_sink)
6542 mst_port = aconnector->port;
6543 mst_mgr = &aconnector->mst_port->mst_mgr;
6545 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6548 if (!state->duplicated) {
6549 int max_bpc = conn_state->max_requested_bpc;
6550 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6551 aconnector->force_yuv420_output;
6552 color_depth = convert_color_depth_from_display_info(connector,
6555 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6556 clock = adjusted_mode->clock;
6557 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6559 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
6562 dm_new_connector_state->pbn,
6563 dm_mst_get_pbn_divider(aconnector->dc_link));
6564 if (dm_new_connector_state->vcpi_slots < 0) {
6565 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6566 return dm_new_connector_state->vcpi_slots;
6571 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6572 .disable = dm_encoder_helper_disable,
6573 .atomic_check = dm_encoder_helper_atomic_check
6576 #if defined(CONFIG_DRM_AMD_DC_DCN)
6577 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6578 struct dc_state *dc_state)
6580 struct dc_stream_state *stream = NULL;
6581 struct drm_connector *connector;
6582 struct drm_connector_state *new_con_state, *old_con_state;
6583 struct amdgpu_dm_connector *aconnector;
6584 struct dm_connector_state *dm_conn_state;
6585 int i, j, clock, bpp;
6586 int vcpi, pbn_div, pbn = 0;
6588 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6590 aconnector = to_amdgpu_dm_connector(connector);
6592 if (!aconnector->port)
6595 if (!new_con_state || !new_con_state->crtc)
6598 dm_conn_state = to_dm_connector_state(new_con_state);
6600 for (j = 0; j < dc_state->stream_count; j++) {
6601 stream = dc_state->streams[j];
6605 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
6614 if (stream->timing.flags.DSC != 1) {
6615 drm_dp_mst_atomic_enable_dsc(state,
6623 pbn_div = dm_mst_get_pbn_divider(stream->link);
6624 bpp = stream->timing.dsc_cfg.bits_per_pixel;
6625 clock = stream->timing.pix_clk_100hz / 10;
6626 pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
6627 vcpi = drm_dp_mst_atomic_enable_dsc(state,
6634 dm_conn_state->pbn = pbn;
6635 dm_conn_state->vcpi_slots = vcpi;
6641 static void dm_drm_plane_reset(struct drm_plane *plane)
6643 struct dm_plane_state *amdgpu_state = NULL;
6646 plane->funcs->atomic_destroy_state(plane, plane->state);
6648 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
6649 WARN_ON(amdgpu_state == NULL);
6652 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
6655 static struct drm_plane_state *
6656 dm_drm_plane_duplicate_state(struct drm_plane *plane)
6658 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
6660 old_dm_plane_state = to_dm_plane_state(plane->state);
6661 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
6662 if (!dm_plane_state)
6665 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
6667 if (old_dm_plane_state->dc_state) {
6668 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
6669 dc_plane_state_retain(dm_plane_state->dc_state);
6672 return &dm_plane_state->base;
6675 static void dm_drm_plane_destroy_state(struct drm_plane *plane,
6676 struct drm_plane_state *state)
6678 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
6680 if (dm_plane_state->dc_state)
6681 dc_plane_state_release(dm_plane_state->dc_state);
6683 drm_atomic_helper_plane_destroy_state(plane, state);
6686 static const struct drm_plane_funcs dm_plane_funcs = {
6687 .update_plane = drm_atomic_helper_update_plane,
6688 .disable_plane = drm_atomic_helper_disable_plane,
6689 .destroy = drm_primary_helper_destroy,
6690 .reset = dm_drm_plane_reset,
6691 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
6692 .atomic_destroy_state = dm_drm_plane_destroy_state,
6693 .format_mod_supported = dm_plane_format_mod_supported,
6696 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
6697 struct drm_plane_state *new_state)
6699 struct amdgpu_framebuffer *afb;
6700 struct drm_gem_object *obj;
6701 struct amdgpu_device *adev;
6702 struct amdgpu_bo *rbo;
6703 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
6704 struct list_head list;
6705 struct ttm_validate_buffer tv;
6706 struct ww_acquire_ctx ticket;
6710 if (!new_state->fb) {
6711 DRM_DEBUG_KMS("No FB bound\n");
6715 afb = to_amdgpu_framebuffer(new_state->fb);
6716 obj = new_state->fb->obj[0];
6717 rbo = gem_to_amdgpu_bo(obj);
6718 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
6719 INIT_LIST_HEAD(&list);
6723 list_add(&tv.head, &list);
6725 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
6727 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
6731 if (plane->type != DRM_PLANE_TYPE_CURSOR)
6732 domain = amdgpu_display_supported_domains(adev, rbo->flags);
6734 domain = AMDGPU_GEM_DOMAIN_VRAM;
6736 r = amdgpu_bo_pin(rbo, domain);
6737 if (unlikely(r != 0)) {
6738 if (r != -ERESTARTSYS)
6739 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
6740 ttm_eu_backoff_reservation(&ticket, &list);
6744 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
6745 if (unlikely(r != 0)) {
6746 amdgpu_bo_unpin(rbo);
6747 ttm_eu_backoff_reservation(&ticket, &list);
6748 DRM_ERROR("%p bind failed\n", rbo);
6752 ttm_eu_backoff_reservation(&ticket, &list);
6754 afb->address = amdgpu_bo_gpu_offset(rbo);
6759 * We don't do surface updates on planes that have been newly created,
6760 * but we also don't have the afb->address during atomic check.
6762 * Fill in buffer attributes depending on the address here, but only on
6763 * newly created planes since they're not being used by DC yet and this
6764 * won't modify global state.
6766 dm_plane_state_old = to_dm_plane_state(plane->state);
6767 dm_plane_state_new = to_dm_plane_state(new_state);
6769 if (dm_plane_state_new->dc_state &&
6770 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
6771 struct dc_plane_state *plane_state =
6772 dm_plane_state_new->dc_state;
6773 bool force_disable_dcc = !plane_state->dcc.enable;
6775 fill_plane_buffer_attributes(
6776 adev, afb, plane_state->format, plane_state->rotation,
6778 &plane_state->tiling_info, &plane_state->plane_size,
6779 &plane_state->dcc, &plane_state->address,
6780 afb->tmz_surface, force_disable_dcc);
6786 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
6787 struct drm_plane_state *old_state)
6789 struct amdgpu_bo *rbo;
6795 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
6796 r = amdgpu_bo_reserve(rbo, false);
6798 DRM_ERROR("failed to reserve rbo before unpin\n");
6802 amdgpu_bo_unpin(rbo);
6803 amdgpu_bo_unreserve(rbo);
6804 amdgpu_bo_unref(&rbo);
6807 static int dm_plane_helper_check_state(struct drm_plane_state *state,
6808 struct drm_crtc_state *new_crtc_state)
6810 struct drm_framebuffer *fb = state->fb;
6811 int min_downscale, max_upscale;
6813 int max_scale = INT_MAX;
6815 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */
6816 if (fb && state->crtc) {
6817 /* Validate viewport to cover the case when only the position changes */
6818 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {
6819 int viewport_width = state->crtc_w;
6820 int viewport_height = state->crtc_h;
6822 if (state->crtc_x < 0)
6823 viewport_width += state->crtc_x;
6824 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay)
6825 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x;
6827 if (state->crtc_y < 0)
6828 viewport_height += state->crtc_y;
6829 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay)
6830 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
6832 if (viewport_width < 0 || viewport_height < 0) {
6833 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n");
6835 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */
6836 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2);
6838 } else if (viewport_height < MIN_VIEWPORT_SIZE) {
6839 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE);
6845 /* Get min/max allowed scaling factors from plane caps. */
6846 get_min_max_dc_plane_scaling(state->crtc->dev, fb,
6847 &min_downscale, &max_upscale);
6849 * Convert to drm convention: 16.16 fixed point, instead of dc's
6850 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's
6851 * dst/src, so min_scale = 1.0 / max_upscale, etc.
6853 min_scale = (1000 << 16) / max_upscale;
6854 max_scale = (1000 << 16) / min_downscale;
6857 return drm_atomic_helper_check_plane_state(
6858 state, new_crtc_state, min_scale, max_scale, true, true);
6861 static int dm_plane_atomic_check(struct drm_plane *plane,
6862 struct drm_atomic_state *state)
6864 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
6866 struct amdgpu_device *adev = drm_to_adev(plane->dev);
6867 struct dc *dc = adev->dm.dc;
6868 struct dm_plane_state *dm_plane_state;
6869 struct dc_scaling_info scaling_info;
6870 struct drm_crtc_state *new_crtc_state;
6873 trace_amdgpu_dm_plane_atomic_check(new_plane_state);
6875 dm_plane_state = to_dm_plane_state(new_plane_state);
6877 if (!dm_plane_state->dc_state)
6881 drm_atomic_get_new_crtc_state(state,
6882 new_plane_state->crtc);
6883 if (!new_crtc_state)
6886 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
6890 ret = fill_dc_scaling_info(new_plane_state, &scaling_info);
6894 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
6900 static int dm_plane_atomic_async_check(struct drm_plane *plane,
6901 struct drm_atomic_state *state)
6903 /* Only support async updates on cursor planes. */
6904 if (plane->type != DRM_PLANE_TYPE_CURSOR)
6910 static void dm_plane_atomic_async_update(struct drm_plane *plane,
6911 struct drm_atomic_state *state)
6913 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
6915 struct drm_plane_state *old_state =
6916 drm_atomic_get_old_plane_state(state, plane);
6918 trace_amdgpu_dm_atomic_update_cursor(new_state);
6920 swap(plane->state->fb, new_state->fb);
6922 plane->state->src_x = new_state->src_x;
6923 plane->state->src_y = new_state->src_y;
6924 plane->state->src_w = new_state->src_w;
6925 plane->state->src_h = new_state->src_h;
6926 plane->state->crtc_x = new_state->crtc_x;
6927 plane->state->crtc_y = new_state->crtc_y;
6928 plane->state->crtc_w = new_state->crtc_w;
6929 plane->state->crtc_h = new_state->crtc_h;
6931 handle_cursor_update(plane, old_state);
6934 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
6935 .prepare_fb = dm_plane_helper_prepare_fb,
6936 .cleanup_fb = dm_plane_helper_cleanup_fb,
6937 .atomic_check = dm_plane_atomic_check,
6938 .atomic_async_check = dm_plane_atomic_async_check,
6939 .atomic_async_update = dm_plane_atomic_async_update
6943 * TODO: these are currently initialized to rgb formats only.
6944 * For future use cases we should either initialize them dynamically based on
6945 * plane capabilities, or initialize this array to all formats, so internal drm
6946 * check will succeed, and let DC implement proper check
6948 static const uint32_t rgb_formats[] = {
6949 DRM_FORMAT_XRGB8888,
6950 DRM_FORMAT_ARGB8888,
6951 DRM_FORMAT_RGBA8888,
6952 DRM_FORMAT_XRGB2101010,
6953 DRM_FORMAT_XBGR2101010,
6954 DRM_FORMAT_ARGB2101010,
6955 DRM_FORMAT_ABGR2101010,
6956 DRM_FORMAT_XBGR8888,
6957 DRM_FORMAT_ABGR8888,
6961 static const uint32_t overlay_formats[] = {
6962 DRM_FORMAT_XRGB8888,
6963 DRM_FORMAT_ARGB8888,
6964 DRM_FORMAT_RGBA8888,
6965 DRM_FORMAT_XBGR8888,
6966 DRM_FORMAT_ABGR8888,
6970 static const u32 cursor_formats[] = {
6974 static int get_plane_formats(const struct drm_plane *plane,
6975 const struct dc_plane_cap *plane_cap,
6976 uint32_t *formats, int max_formats)
6978 int i, num_formats = 0;
6981 * TODO: Query support for each group of formats directly from
6982 * DC plane caps. This will require adding more formats to the
6986 switch (plane->type) {
6987 case DRM_PLANE_TYPE_PRIMARY:
6988 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
6989 if (num_formats >= max_formats)
6992 formats[num_formats++] = rgb_formats[i];
6995 if (plane_cap && plane_cap->pixel_format_support.nv12)
6996 formats[num_formats++] = DRM_FORMAT_NV12;
6997 if (plane_cap && plane_cap->pixel_format_support.p010)
6998 formats[num_formats++] = DRM_FORMAT_P010;
6999 if (plane_cap && plane_cap->pixel_format_support.fp16) {
7000 formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
7001 formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
7002 formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
7003 formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
7007 case DRM_PLANE_TYPE_OVERLAY:
7008 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
7009 if (num_formats >= max_formats)
7012 formats[num_formats++] = overlay_formats[i];
7016 case DRM_PLANE_TYPE_CURSOR:
7017 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
7018 if (num_formats >= max_formats)
7021 formats[num_formats++] = cursor_formats[i];
7029 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
7030 struct drm_plane *plane,
7031 unsigned long possible_crtcs,
7032 const struct dc_plane_cap *plane_cap)
7034 uint32_t formats[32];
7037 unsigned int supported_rotations;
7038 uint64_t *modifiers = NULL;
7040 num_formats = get_plane_formats(plane, plane_cap, formats,
7041 ARRAY_SIZE(formats));
7043 res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
7047 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
7048 &dm_plane_funcs, formats, num_formats,
7049 modifiers, plane->type, NULL);
7054 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
7055 plane_cap && plane_cap->per_pixel_alpha) {
7056 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
7057 BIT(DRM_MODE_BLEND_PREMULTI);
7059 drm_plane_create_alpha_property(plane);
7060 drm_plane_create_blend_mode_property(plane, blend_caps);
7063 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
7065 (plane_cap->pixel_format_support.nv12 ||
7066 plane_cap->pixel_format_support.p010)) {
7067 /* This only affects YUV formats. */
7068 drm_plane_create_color_properties(
7070 BIT(DRM_COLOR_YCBCR_BT601) |
7071 BIT(DRM_COLOR_YCBCR_BT709) |
7072 BIT(DRM_COLOR_YCBCR_BT2020),
7073 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
7074 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
7075 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
7078 supported_rotations =
7079 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
7080 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
7082 if (dm->adev->asic_type >= CHIP_BONAIRE &&
7083 plane->type != DRM_PLANE_TYPE_CURSOR)
7084 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
7085 supported_rotations);
7087 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
7089 /* Create (reset) the plane state */
7090 if (plane->funcs->reset)
7091 plane->funcs->reset(plane);
7096 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
7097 struct drm_plane *plane,
7098 uint32_t crtc_index)
7100 struct amdgpu_crtc *acrtc = NULL;
7101 struct drm_plane *cursor_plane;
7105 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
7109 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
7110 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
7112 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
7116 res = drm_crtc_init_with_planes(
7121 &amdgpu_dm_crtc_funcs, NULL);
7126 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
7128 /* Create (reset) the plane state */
7129 if (acrtc->base.funcs->reset)
7130 acrtc->base.funcs->reset(&acrtc->base);
7132 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
7133 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
7135 acrtc->crtc_id = crtc_index;
7136 acrtc->base.enabled = false;
7137 acrtc->otg_inst = -1;
7139 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
7140 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
7141 true, MAX_COLOR_LUT_ENTRIES);
7142 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
7148 kfree(cursor_plane);
7153 static int to_drm_connector_type(enum signal_type st)
7156 case SIGNAL_TYPE_HDMI_TYPE_A:
7157 return DRM_MODE_CONNECTOR_HDMIA;
7158 case SIGNAL_TYPE_EDP:
7159 return DRM_MODE_CONNECTOR_eDP;
7160 case SIGNAL_TYPE_LVDS:
7161 return DRM_MODE_CONNECTOR_LVDS;
7162 case SIGNAL_TYPE_RGB:
7163 return DRM_MODE_CONNECTOR_VGA;
7164 case SIGNAL_TYPE_DISPLAY_PORT:
7165 case SIGNAL_TYPE_DISPLAY_PORT_MST:
7166 return DRM_MODE_CONNECTOR_DisplayPort;
7167 case SIGNAL_TYPE_DVI_DUAL_LINK:
7168 case SIGNAL_TYPE_DVI_SINGLE_LINK:
7169 return DRM_MODE_CONNECTOR_DVID;
7170 case SIGNAL_TYPE_VIRTUAL:
7171 return DRM_MODE_CONNECTOR_VIRTUAL;
7174 return DRM_MODE_CONNECTOR_Unknown;
7178 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7180 struct drm_encoder *encoder;
7182 /* There is only one encoder per connector */
7183 drm_connector_for_each_possible_encoder(connector, encoder)
7189 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7191 struct drm_encoder *encoder;
7192 struct amdgpu_encoder *amdgpu_encoder;
7194 encoder = amdgpu_dm_connector_to_encoder(connector);
7196 if (encoder == NULL)
7199 amdgpu_encoder = to_amdgpu_encoder(encoder);
7201 amdgpu_encoder->native_mode.clock = 0;
7203 if (!list_empty(&connector->probed_modes)) {
7204 struct drm_display_mode *preferred_mode = NULL;
7206 list_for_each_entry(preferred_mode,
7207 &connector->probed_modes,
7209 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7210 amdgpu_encoder->native_mode = *preferred_mode;
7218 static struct drm_display_mode *
7219 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7221 int hdisplay, int vdisplay)
7223 struct drm_device *dev = encoder->dev;
7224 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7225 struct drm_display_mode *mode = NULL;
7226 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7228 mode = drm_mode_duplicate(dev, native_mode);
7233 mode->hdisplay = hdisplay;
7234 mode->vdisplay = vdisplay;
7235 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7236 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7242 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7243 struct drm_connector *connector)
7245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7246 struct drm_display_mode *mode = NULL;
7247 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7248 struct amdgpu_dm_connector *amdgpu_dm_connector =
7249 to_amdgpu_dm_connector(connector);
7253 char name[DRM_DISPLAY_MODE_LEN];
7256 } common_modes[] = {
7257 { "640x480", 640, 480},
7258 { "800x600", 800, 600},
7259 { "1024x768", 1024, 768},
7260 { "1280x720", 1280, 720},
7261 { "1280x800", 1280, 800},
7262 {"1280x1024", 1280, 1024},
7263 { "1440x900", 1440, 900},
7264 {"1680x1050", 1680, 1050},
7265 {"1600x1200", 1600, 1200},
7266 {"1920x1080", 1920, 1080},
7267 {"1920x1200", 1920, 1200}
7270 n = ARRAY_SIZE(common_modes);
7272 for (i = 0; i < n; i++) {
7273 struct drm_display_mode *curmode = NULL;
7274 bool mode_existed = false;
7276 if (common_modes[i].w > native_mode->hdisplay ||
7277 common_modes[i].h > native_mode->vdisplay ||
7278 (common_modes[i].w == native_mode->hdisplay &&
7279 common_modes[i].h == native_mode->vdisplay))
7282 list_for_each_entry(curmode, &connector->probed_modes, head) {
7283 if (common_modes[i].w == curmode->hdisplay &&
7284 common_modes[i].h == curmode->vdisplay) {
7285 mode_existed = true;
7293 mode = amdgpu_dm_create_common_mode(encoder,
7294 common_modes[i].name, common_modes[i].w,
7296 drm_mode_probed_add(connector, mode);
7297 amdgpu_dm_connector->num_modes++;
7301 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7304 struct amdgpu_dm_connector *amdgpu_dm_connector =
7305 to_amdgpu_dm_connector(connector);
7308 /* empty probed_modes */
7309 INIT_LIST_HEAD(&connector->probed_modes);
7310 amdgpu_dm_connector->num_modes =
7311 drm_add_edid_modes(connector, edid);
7313 /* sorting the probed modes before calling function
7314 * amdgpu_dm_get_native_mode() since EDID can have
7315 * more than one preferred mode. The modes that are
7316 * later in the probed mode list could be of higher
7317 * and preferred resolution. For example, 3840x2160
7318 * resolution in base EDID preferred timing and 4096x2160
7319 * preferred resolution in DID extension block later.
7321 drm_mode_sort(&connector->probed_modes);
7322 amdgpu_dm_get_native_mode(connector);
7324 /* Freesync capabilities are reset by calling
7325 * drm_add_edid_modes() and need to be
7328 amdgpu_dm_update_freesync_caps(connector, edid);
7330 amdgpu_dm_connector->num_modes = 0;
7334 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7335 struct drm_display_mode *mode)
7337 struct drm_display_mode *m;
7339 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7340 if (drm_mode_equal(m, mode))
7347 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7349 const struct drm_display_mode *m;
7350 struct drm_display_mode *new_mode;
7352 uint32_t new_modes_count = 0;
7354 /* Standard FPS values
7363 * 60 - Commonly used
7364 * 48,72,96 - Multiples of 24
7366 const uint32_t common_rates[] = { 23976, 24000, 25000, 29970, 30000,
7367 48000, 50000, 60000, 72000, 96000 };
7370 * Find mode with highest refresh rate with the same resolution
7371 * as the preferred mode. Some monitors report a preferred mode
7372 * with lower resolution than the highest refresh rate supported.
7375 m = get_highest_refresh_rate_mode(aconnector, true);
7379 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7380 uint64_t target_vtotal, target_vtotal_diff;
7383 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7386 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7387 common_rates[i] > aconnector->max_vfreq * 1000)
7390 num = (unsigned long long)m->clock * 1000 * 1000;
7391 den = common_rates[i] * (unsigned long long)m->htotal;
7392 target_vtotal = div_u64(num, den);
7393 target_vtotal_diff = target_vtotal - m->vtotal;
7395 /* Check for illegal modes */
7396 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7397 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7398 m->vtotal + target_vtotal_diff < m->vsync_end)
7401 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7405 new_mode->vtotal += (u16)target_vtotal_diff;
7406 new_mode->vsync_start += (u16)target_vtotal_diff;
7407 new_mode->vsync_end += (u16)target_vtotal_diff;
7408 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7409 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7411 if (!is_duplicate_mode(aconnector, new_mode)) {
7412 drm_mode_probed_add(&aconnector->base, new_mode);
7413 new_modes_count += 1;
7415 drm_mode_destroy(aconnector->base.dev, new_mode);
7418 return new_modes_count;
7421 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7424 struct amdgpu_dm_connector *amdgpu_dm_connector =
7425 to_amdgpu_dm_connector(connector);
7427 if (!(amdgpu_freesync_vid_mode && edid))
7430 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7431 amdgpu_dm_connector->num_modes +=
7432 add_fs_modes(amdgpu_dm_connector);
7435 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7437 struct amdgpu_dm_connector *amdgpu_dm_connector =
7438 to_amdgpu_dm_connector(connector);
7439 struct drm_encoder *encoder;
7440 struct edid *edid = amdgpu_dm_connector->edid;
7442 encoder = amdgpu_dm_connector_to_encoder(connector);
7444 if (!drm_edid_is_valid(edid)) {
7445 amdgpu_dm_connector->num_modes =
7446 drm_add_modes_noedid(connector, 640, 480);
7448 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7449 amdgpu_dm_connector_add_common_modes(encoder, connector);
7450 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7452 amdgpu_dm_fbc_init(connector);
7454 return amdgpu_dm_connector->num_modes;
7457 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7458 struct amdgpu_dm_connector *aconnector,
7460 struct dc_link *link,
7463 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7466 * Some of the properties below require access to state, like bpc.
7467 * Allocate some default initial connector state with our reset helper.
7469 if (aconnector->base.funcs->reset)
7470 aconnector->base.funcs->reset(&aconnector->base);
7472 aconnector->connector_id = link_index;
7473 aconnector->dc_link = link;
7474 aconnector->base.interlace_allowed = false;
7475 aconnector->base.doublescan_allowed = false;
7476 aconnector->base.stereo_allowed = false;
7477 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7478 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7479 aconnector->audio_inst = -1;
7480 mutex_init(&aconnector->hpd_lock);
7483 * configure support HPD hot plug connector_>polled default value is 0
7484 * which means HPD hot plug not supported
7486 switch (connector_type) {
7487 case DRM_MODE_CONNECTOR_HDMIA:
7488 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7489 aconnector->base.ycbcr_420_allowed =
7490 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7492 case DRM_MODE_CONNECTOR_DisplayPort:
7493 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7494 aconnector->base.ycbcr_420_allowed =
7495 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7497 case DRM_MODE_CONNECTOR_DVID:
7498 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7504 drm_object_attach_property(&aconnector->base.base,
7505 dm->ddev->mode_config.scaling_mode_property,
7506 DRM_MODE_SCALE_NONE);
7508 drm_object_attach_property(&aconnector->base.base,
7509 adev->mode_info.underscan_property,
7511 drm_object_attach_property(&aconnector->base.base,
7512 adev->mode_info.underscan_hborder_property,
7514 drm_object_attach_property(&aconnector->base.base,
7515 adev->mode_info.underscan_vborder_property,
7518 if (!aconnector->mst_port)
7519 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7521 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7522 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7523 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7525 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7526 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7527 drm_object_attach_property(&aconnector->base.base,
7528 adev->mode_info.abm_level_property, 0);
7531 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7532 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7533 connector_type == DRM_MODE_CONNECTOR_eDP) {
7534 drm_object_attach_property(
7535 &aconnector->base.base,
7536 dm->ddev->mode_config.hdr_output_metadata_property, 0);
7538 if (!aconnector->mst_port)
7539 drm_connector_attach_vrr_capable_property(&aconnector->base);
7541 #ifdef CONFIG_DRM_AMD_DC_HDCP
7542 if (adev->dm.hdcp_workqueue)
7543 drm_connector_attach_content_protection_property(&aconnector->base, true);
7548 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7549 struct i2c_msg *msgs, int num)
7551 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7552 struct ddc_service *ddc_service = i2c->ddc_service;
7553 struct i2c_command cmd;
7557 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7562 cmd.number_of_payloads = num;
7563 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7566 for (i = 0; i < num; i++) {
7567 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7568 cmd.payloads[i].address = msgs[i].addr;
7569 cmd.payloads[i].length = msgs[i].len;
7570 cmd.payloads[i].data = msgs[i].buf;
7574 ddc_service->ctx->dc,
7575 ddc_service->ddc_pin->hw_info.ddc_channel,
7579 kfree(cmd.payloads);
7583 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7585 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7588 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7589 .master_xfer = amdgpu_dm_i2c_xfer,
7590 .functionality = amdgpu_dm_i2c_func,
7593 static struct amdgpu_i2c_adapter *
7594 create_i2c(struct ddc_service *ddc_service,
7598 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7599 struct amdgpu_i2c_adapter *i2c;
7601 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7604 i2c->base.owner = THIS_MODULE;
7605 i2c->base.class = I2C_CLASS_DDC;
7606 i2c->base.dev.parent = &adev->pdev->dev;
7607 i2c->base.algo = &amdgpu_dm_i2c_algo;
7608 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7609 i2c_set_adapdata(&i2c->base, i2c);
7610 i2c->ddc_service = ddc_service;
7611 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
7618 * Note: this function assumes that dc_link_detect() was called for the
7619 * dc_link which will be represented by this aconnector.
7621 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7622 struct amdgpu_dm_connector *aconnector,
7623 uint32_t link_index,
7624 struct amdgpu_encoder *aencoder)
7628 struct dc *dc = dm->dc;
7629 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7630 struct amdgpu_i2c_adapter *i2c;
7632 link->priv = aconnector;
7634 DRM_DEBUG_DRIVER("%s()\n", __func__);
7636 i2c = create_i2c(link->ddc, link->link_index, &res);
7638 DRM_ERROR("Failed to create i2c adapter data\n");
7642 aconnector->i2c = i2c;
7643 res = i2c_add_adapter(&i2c->base);
7646 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7650 connector_type = to_drm_connector_type(link->connector_signal);
7652 res = drm_connector_init_with_ddc(
7655 &amdgpu_dm_connector_funcs,
7660 DRM_ERROR("connector_init failed\n");
7661 aconnector->connector_id = -1;
7665 drm_connector_helper_add(
7667 &amdgpu_dm_connector_helper_funcs);
7669 amdgpu_dm_connector_init_helper(
7676 drm_connector_attach_encoder(
7677 &aconnector->base, &aencoder->base);
7679 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7680 || connector_type == DRM_MODE_CONNECTOR_eDP)
7681 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7686 aconnector->i2c = NULL;
7691 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7693 switch (adev->mode_info.num_crtc) {
7710 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7711 struct amdgpu_encoder *aencoder,
7712 uint32_t link_index)
7714 struct amdgpu_device *adev = drm_to_adev(dev);
7716 int res = drm_encoder_init(dev,
7718 &amdgpu_dm_encoder_funcs,
7719 DRM_MODE_ENCODER_TMDS,
7722 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7725 aencoder->encoder_id = link_index;
7727 aencoder->encoder_id = -1;
7729 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7734 static void manage_dm_interrupts(struct amdgpu_device *adev,
7735 struct amdgpu_crtc *acrtc,
7739 * We have no guarantee that the frontend index maps to the same
7740 * backend index - some even map to more than one.
7742 * TODO: Use a different interrupt or check DC itself for the mapping.
7745 amdgpu_display_crtc_idx_to_irq_type(
7750 drm_crtc_vblank_on(&acrtc->base);
7753 &adev->pageflip_irq,
7755 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7762 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7770 &adev->pageflip_irq,
7772 drm_crtc_vblank_off(&acrtc->base);
7776 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7777 struct amdgpu_crtc *acrtc)
7780 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7783 * This reads the current state for the IRQ and force reapplies
7784 * the setting to hardware.
7786 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7790 is_scaling_state_different(const struct dm_connector_state *dm_state,
7791 const struct dm_connector_state *old_dm_state)
7793 if (dm_state->scaling != old_dm_state->scaling)
7795 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7796 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7798 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7799 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7801 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7802 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7807 #ifdef CONFIG_DRM_AMD_DC_HDCP
7808 static bool is_content_protection_different(struct drm_connector_state *state,
7809 const struct drm_connector_state *old_state,
7810 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7812 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7813 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7815 /* Handle: Type0/1 change */
7816 if (old_state->hdcp_content_type != state->hdcp_content_type &&
7817 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7818 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7822 /* CP is being re enabled, ignore this
7824 * Handles: ENABLED -> DESIRED
7826 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7827 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7828 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7832 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7834 * Handles: UNDESIRED -> ENABLED
7836 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7837 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7838 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7840 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
7841 * hot-plug, headless s3, dpms
7843 * Handles: DESIRED -> DESIRED (Special case)
7845 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7846 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7847 dm_con_state->update_hdcp = false;
7852 * Handles: UNDESIRED -> UNDESIRED
7853 * DESIRED -> DESIRED
7854 * ENABLED -> ENABLED
7856 if (old_state->content_protection == state->content_protection)
7860 * Handles: UNDESIRED -> DESIRED
7861 * DESIRED -> UNDESIRED
7862 * ENABLED -> UNDESIRED
7864 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7868 * Handles: DESIRED -> ENABLED
7874 static void remove_stream(struct amdgpu_device *adev,
7875 struct amdgpu_crtc *acrtc,
7876 struct dc_stream_state *stream)
7878 /* this is the update mode case */
7880 acrtc->otg_inst = -1;
7881 acrtc->enabled = false;
7884 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
7885 struct dc_cursor_position *position)
7887 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7889 int xorigin = 0, yorigin = 0;
7891 if (!crtc || !plane->state->fb)
7894 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
7895 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
7896 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
7898 plane->state->crtc_w,
7899 plane->state->crtc_h);
7903 x = plane->state->crtc_x;
7904 y = plane->state->crtc_y;
7906 if (x <= -amdgpu_crtc->max_cursor_width ||
7907 y <= -amdgpu_crtc->max_cursor_height)
7911 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
7915 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
7918 position->enable = true;
7919 position->translate_by_source = true;
7922 position->x_hotspot = xorigin;
7923 position->y_hotspot = yorigin;
7928 static void handle_cursor_update(struct drm_plane *plane,
7929 struct drm_plane_state *old_plane_state)
7931 struct amdgpu_device *adev = drm_to_adev(plane->dev);
7932 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
7933 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
7934 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
7935 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7936 uint64_t address = afb ? afb->address : 0;
7937 struct dc_cursor_position position = {0};
7938 struct dc_cursor_attributes attributes;
7941 if (!plane->state->fb && !old_plane_state->fb)
7944 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n",
7946 amdgpu_crtc->crtc_id,
7947 plane->state->crtc_w,
7948 plane->state->crtc_h);
7950 ret = get_cursor_position(plane, crtc, &position);
7954 if (!position.enable) {
7955 /* turn off cursor */
7956 if (crtc_state && crtc_state->stream) {
7957 mutex_lock(&adev->dm.dc_lock);
7958 dc_stream_set_cursor_position(crtc_state->stream,
7960 mutex_unlock(&adev->dm.dc_lock);
7965 amdgpu_crtc->cursor_width = plane->state->crtc_w;
7966 amdgpu_crtc->cursor_height = plane->state->crtc_h;
7968 memset(&attributes, 0, sizeof(attributes));
7969 attributes.address.high_part = upper_32_bits(address);
7970 attributes.address.low_part = lower_32_bits(address);
7971 attributes.width = plane->state->crtc_w;
7972 attributes.height = plane->state->crtc_h;
7973 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
7974 attributes.rotation_angle = 0;
7975 attributes.attribute_flags.value = 0;
7977 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
7979 if (crtc_state->stream) {
7980 mutex_lock(&adev->dm.dc_lock);
7981 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
7983 DRM_ERROR("DC failed to set cursor attributes\n");
7985 if (!dc_stream_set_cursor_position(crtc_state->stream,
7987 DRM_ERROR("DC failed to set cursor position\n");
7988 mutex_unlock(&adev->dm.dc_lock);
7992 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7995 assert_spin_locked(&acrtc->base.dev->event_lock);
7996 WARN_ON(acrtc->event);
7998 acrtc->event = acrtc->base.state->event;
8000 /* Set the flip status */
8001 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
8003 /* Mark this event as consumed */
8004 acrtc->base.state->event = NULL;
8006 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
8010 static void update_freesync_state_on_stream(
8011 struct amdgpu_display_manager *dm,
8012 struct dm_crtc_state *new_crtc_state,
8013 struct dc_stream_state *new_stream,
8014 struct dc_plane_state *surface,
8015 u32 flip_timestamp_in_us)
8017 struct mod_vrr_params vrr_params;
8018 struct dc_info_packet vrr_infopacket = {0};
8019 struct amdgpu_device *adev = dm->adev;
8020 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8021 unsigned long flags;
8022 bool pack_sdp_v1_3 = false;
8028 * TODO: Determine why min/max totals and vrefresh can be 0 here.
8029 * For now it's sufficient to just guard against these conditions.
8032 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8035 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8036 vrr_params = acrtc->dm_irq_params.vrr_params;
8039 mod_freesync_handle_preflip(
8040 dm->freesync_module,
8043 flip_timestamp_in_us,
8046 if (adev->family < AMDGPU_FAMILY_AI &&
8047 amdgpu_dm_vrr_active(new_crtc_state)) {
8048 mod_freesync_handle_v_update(dm->freesync_module,
8049 new_stream, &vrr_params);
8051 /* Need to call this before the frame ends. */
8052 dc_stream_adjust_vmin_vmax(dm->dc,
8053 new_crtc_state->stream,
8054 &vrr_params.adjust);
8058 mod_freesync_build_vrr_infopacket(
8059 dm->freesync_module,
8063 TRANSFER_FUNC_UNKNOWN,
8067 new_crtc_state->freesync_timing_changed |=
8068 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
8070 sizeof(vrr_params.adjust)) != 0);
8072 new_crtc_state->freesync_vrr_info_changed |=
8073 (memcmp(&new_crtc_state->vrr_infopacket,
8075 sizeof(vrr_infopacket)) != 0);
8077 acrtc->dm_irq_params.vrr_params = vrr_params;
8078 new_crtc_state->vrr_infopacket = vrr_infopacket;
8080 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
8081 new_stream->vrr_infopacket = vrr_infopacket;
8083 if (new_crtc_state->freesync_vrr_info_changed)
8084 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8085 new_crtc_state->base.crtc->base.id,
8086 (int)new_crtc_state->base.vrr_enabled,
8087 (int)vrr_params.state);
8089 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8092 static void update_stream_irq_parameters(
8093 struct amdgpu_display_manager *dm,
8094 struct dm_crtc_state *new_crtc_state)
8096 struct dc_stream_state *new_stream = new_crtc_state->stream;
8097 struct mod_vrr_params vrr_params;
8098 struct mod_freesync_config config = new_crtc_state->freesync_config;
8099 struct amdgpu_device *adev = dm->adev;
8100 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8101 unsigned long flags;
8107 * TODO: Determine why min/max totals and vrefresh can be 0 here.
8108 * For now it's sufficient to just guard against these conditions.
8110 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8113 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8114 vrr_params = acrtc->dm_irq_params.vrr_params;
8116 if (new_crtc_state->vrr_supported &&
8117 config.min_refresh_in_uhz &&
8118 config.max_refresh_in_uhz) {
8120 * if freesync compatible mode was set, config.state will be set
8123 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8124 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8125 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8126 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8127 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8128 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8129 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8131 config.state = new_crtc_state->base.vrr_enabled ?
8132 VRR_STATE_ACTIVE_VARIABLE :
8136 config.state = VRR_STATE_UNSUPPORTED;
8139 mod_freesync_build_vrr_params(dm->freesync_module,
8141 &config, &vrr_params);
8143 new_crtc_state->freesync_timing_changed |=
8144 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
8145 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0);
8147 new_crtc_state->freesync_config = config;
8148 /* Copy state for access from DM IRQ handler */
8149 acrtc->dm_irq_params.freesync_config = config;
8150 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8151 acrtc->dm_irq_params.vrr_params = vrr_params;
8152 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8155 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8156 struct dm_crtc_state *new_state)
8158 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
8159 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
8161 if (!old_vrr_active && new_vrr_active) {
8162 /* Transition VRR inactive -> active:
8163 * While VRR is active, we must not disable vblank irq, as a
8164 * reenable after disable would compute bogus vblank/pflip
8165 * timestamps if it likely happened inside display front-porch.
8167 * We also need vupdate irq for the actual core vblank handling
8170 dm_set_vupdate_irq(new_state->base.crtc, true);
8171 drm_crtc_vblank_get(new_state->base.crtc);
8172 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8173 __func__, new_state->base.crtc->base.id);
8174 } else if (old_vrr_active && !new_vrr_active) {
8175 /* Transition VRR active -> inactive:
8176 * Allow vblank irq disable again for fixed refresh rate.
8178 dm_set_vupdate_irq(new_state->base.crtc, false);
8179 drm_crtc_vblank_put(new_state->base.crtc);
8180 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8181 __func__, new_state->base.crtc->base.id);
8185 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8187 struct drm_plane *plane;
8188 struct drm_plane_state *old_plane_state, *new_plane_state;
8192 * TODO: Make this per-stream so we don't issue redundant updates for
8193 * commits with multiple streams.
8195 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
8197 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8198 handle_cursor_update(plane, old_plane_state);
8201 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8202 struct dc_state *dc_state,
8203 struct drm_device *dev,
8204 struct amdgpu_display_manager *dm,
8205 struct drm_crtc *pcrtc,
8206 bool wait_for_vblank)
8209 uint64_t timestamp_ns;
8210 struct drm_plane *plane;
8211 struct drm_plane_state *old_plane_state, *new_plane_state;
8212 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8213 struct drm_crtc_state *new_pcrtc_state =
8214 drm_atomic_get_new_crtc_state(state, pcrtc);
8215 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8216 struct dm_crtc_state *dm_old_crtc_state =
8217 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8218 int planes_count = 0, vpos, hpos;
8220 unsigned long flags;
8221 struct amdgpu_bo *abo;
8222 uint32_t target_vblank, last_flip_vblank;
8223 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
8224 bool pflip_present = false;
8226 struct dc_surface_update surface_updates[MAX_SURFACES];
8227 struct dc_plane_info plane_infos[MAX_SURFACES];
8228 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8229 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8230 struct dc_stream_update stream_update;
8233 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8236 dm_error("Failed to allocate update bundle\n");
8241 * Disable the cursor first if we're disabling all the planes.
8242 * It'll remain on the screen after the planes are re-enabled
8245 if (acrtc_state->active_planes == 0)
8246 amdgpu_dm_commit_cursors(state);
8248 /* update planes when needed */
8249 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8250 struct drm_crtc *crtc = new_plane_state->crtc;
8251 struct drm_crtc_state *new_crtc_state;
8252 struct drm_framebuffer *fb = new_plane_state->fb;
8253 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8254 bool plane_needs_flip;
8255 struct dc_plane_state *dc_plane;
8256 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8258 /* Cursor plane is handled after stream updates */
8259 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8262 if (!fb || !crtc || pcrtc != crtc)
8265 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8266 if (!new_crtc_state->active)
8269 dc_plane = dm_new_plane_state->dc_state;
8271 bundle->surface_updates[planes_count].surface = dc_plane;
8272 if (new_pcrtc_state->color_mgmt_changed) {
8273 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8274 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8275 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8278 fill_dc_scaling_info(new_plane_state,
8279 &bundle->scaling_infos[planes_count]);
8281 bundle->surface_updates[planes_count].scaling_info =
8282 &bundle->scaling_infos[planes_count];
8284 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8286 pflip_present = pflip_present || plane_needs_flip;
8288 if (!plane_needs_flip) {
8293 abo = gem_to_amdgpu_bo(fb->obj[0]);
8296 * Wait for all fences on this FB. Do limited wait to avoid
8297 * deadlock during GPU reset when this fence will not signal
8298 * but we hold reservation lock for the BO.
8300 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
8302 msecs_to_jiffies(5000));
8303 if (unlikely(r <= 0))
8304 DRM_ERROR("Waiting for fences timed out!");
8306 fill_dc_plane_info_and_addr(
8307 dm->adev, new_plane_state,
8309 &bundle->plane_infos[planes_count],
8310 &bundle->flip_addrs[planes_count].address,
8311 afb->tmz_surface, false);
8313 DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n",
8314 new_plane_state->plane->index,
8315 bundle->plane_infos[planes_count].dcc.enable);
8317 bundle->surface_updates[planes_count].plane_info =
8318 &bundle->plane_infos[planes_count];
8321 * Only allow immediate flips for fast updates that don't
8322 * change FB pitch, DCC state, rotation or mirroing.
8324 bundle->flip_addrs[planes_count].flip_immediate =
8325 crtc->state->async_flip &&
8326 acrtc_state->update_type == UPDATE_TYPE_FAST;
8328 timestamp_ns = ktime_get_ns();
8329 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8330 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8331 bundle->surface_updates[planes_count].surface = dc_plane;
8333 if (!bundle->surface_updates[planes_count].surface) {
8334 DRM_ERROR("No surface for CRTC: id=%d\n",
8335 acrtc_attach->crtc_id);
8339 if (plane == pcrtc->primary)
8340 update_freesync_state_on_stream(
8343 acrtc_state->stream,
8345 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8347 DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n",
8349 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8350 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8356 if (pflip_present) {
8358 /* Use old throttling in non-vrr fixed refresh rate mode
8359 * to keep flip scheduling based on target vblank counts
8360 * working in a backwards compatible way, e.g., for
8361 * clients using the GLX_OML_sync_control extension or
8362 * DRI3/Present extension with defined target_msc.
8364 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8367 /* For variable refresh rate mode only:
8368 * Get vblank of last completed flip to avoid > 1 vrr
8369 * flips per video frame by use of throttling, but allow
8370 * flip programming anywhere in the possibly large
8371 * variable vrr vblank interval for fine-grained flip
8372 * timing control and more opportunity to avoid stutter
8373 * on late submission of flips.
8375 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8376 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8377 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8380 target_vblank = last_flip_vblank + wait_for_vblank;
8383 * Wait until we're out of the vertical blank period before the one
8384 * targeted by the flip
8386 while ((acrtc_attach->enabled &&
8387 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8388 0, &vpos, &hpos, NULL,
8389 NULL, &pcrtc->hwmode)
8390 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8391 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8392 (int)(target_vblank -
8393 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8394 usleep_range(1000, 1100);
8398 * Prepare the flip event for the pageflip interrupt to handle.
8400 * This only works in the case where we've already turned on the
8401 * appropriate hardware blocks (eg. HUBP) so in the transition case
8402 * from 0 -> n planes we have to skip a hardware generated event
8403 * and rely on sending it from software.
8405 if (acrtc_attach->base.state->event &&
8406 acrtc_state->active_planes > 0) {
8407 drm_crtc_vblank_get(pcrtc);
8409 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8411 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8412 prepare_flip_isr(acrtc_attach);
8414 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8417 if (acrtc_state->stream) {
8418 if (acrtc_state->freesync_vrr_info_changed)
8419 bundle->stream_update.vrr_infopacket =
8420 &acrtc_state->stream->vrr_infopacket;
8424 /* Update the planes if changed or disable if we don't have any. */
8425 if ((planes_count || acrtc_state->active_planes == 0) &&
8426 acrtc_state->stream) {
8427 bundle->stream_update.stream = acrtc_state->stream;
8428 if (new_pcrtc_state->mode_changed) {
8429 bundle->stream_update.src = acrtc_state->stream->src;
8430 bundle->stream_update.dst = acrtc_state->stream->dst;
8433 if (new_pcrtc_state->color_mgmt_changed) {
8435 * TODO: This isn't fully correct since we've actually
8436 * already modified the stream in place.
8438 bundle->stream_update.gamut_remap =
8439 &acrtc_state->stream->gamut_remap_matrix;
8440 bundle->stream_update.output_csc_transform =
8441 &acrtc_state->stream->csc_color_matrix;
8442 bundle->stream_update.out_transfer_func =
8443 acrtc_state->stream->out_transfer_func;
8446 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8447 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8448 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8451 * If FreeSync state on the stream has changed then we need to
8452 * re-adjust the min/max bounds now that DC doesn't handle this
8453 * as part of commit.
8455 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8456 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8457 dc_stream_adjust_vmin_vmax(
8458 dm->dc, acrtc_state->stream,
8459 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8460 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8462 mutex_lock(&dm->dc_lock);
8463 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8464 acrtc_state->stream->link->psr_settings.psr_allow_active)
8465 amdgpu_dm_psr_disable(acrtc_state->stream);
8467 dc_commit_updates_for_stream(dm->dc,
8468 bundle->surface_updates,
8470 acrtc_state->stream,
8471 &bundle->stream_update,
8475 * Enable or disable the interrupts on the backend.
8477 * Most pipes are put into power gating when unused.
8479 * When power gating is enabled on a pipe we lose the
8480 * interrupt enablement state when power gating is disabled.
8482 * So we need to update the IRQ control state in hardware
8483 * whenever the pipe turns on (since it could be previously
8484 * power gated) or off (since some pipes can't be power gated
8487 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8488 dm_update_pflip_irq_state(drm_to_adev(dev),
8491 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8492 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8493 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8494 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8495 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
8496 acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
8497 !acrtc_state->stream->link->psr_settings.psr_allow_active) {
8498 amdgpu_dm_psr_enable(acrtc_state->stream);
8501 mutex_unlock(&dm->dc_lock);
8505 * Update cursor state *after* programming all the planes.
8506 * This avoids redundant programming in the case where we're going
8507 * to be disabling a single plane - those pipes are being disabled.
8509 if (acrtc_state->active_planes)
8510 amdgpu_dm_commit_cursors(state);
8516 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8517 struct drm_atomic_state *state)
8519 struct amdgpu_device *adev = drm_to_adev(dev);
8520 struct amdgpu_dm_connector *aconnector;
8521 struct drm_connector *connector;
8522 struct drm_connector_state *old_con_state, *new_con_state;
8523 struct drm_crtc_state *new_crtc_state;
8524 struct dm_crtc_state *new_dm_crtc_state;
8525 const struct dc_stream_status *status;
8528 /* Notify device removals. */
8529 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8530 if (old_con_state->crtc != new_con_state->crtc) {
8531 /* CRTC changes require notification. */
8535 if (!new_con_state->crtc)
8538 new_crtc_state = drm_atomic_get_new_crtc_state(
8539 state, new_con_state->crtc);
8541 if (!new_crtc_state)
8544 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8548 aconnector = to_amdgpu_dm_connector(connector);
8550 mutex_lock(&adev->dm.audio_lock);
8551 inst = aconnector->audio_inst;
8552 aconnector->audio_inst = -1;
8553 mutex_unlock(&adev->dm.audio_lock);
8555 amdgpu_dm_audio_eld_notify(adev, inst);
8558 /* Notify audio device additions. */
8559 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8560 if (!new_con_state->crtc)
8563 new_crtc_state = drm_atomic_get_new_crtc_state(
8564 state, new_con_state->crtc);
8566 if (!new_crtc_state)
8569 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8572 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8573 if (!new_dm_crtc_state->stream)
8576 status = dc_stream_get_status(new_dm_crtc_state->stream);
8580 aconnector = to_amdgpu_dm_connector(connector);
8582 mutex_lock(&adev->dm.audio_lock);
8583 inst = status->audio_inst;
8584 aconnector->audio_inst = inst;
8585 mutex_unlock(&adev->dm.audio_lock);
8587 amdgpu_dm_audio_eld_notify(adev, inst);
8592 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8593 * @crtc_state: the DRM CRTC state
8594 * @stream_state: the DC stream state.
8596 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8597 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8599 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8600 struct dc_stream_state *stream_state)
8602 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8606 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8607 * @state: The atomic state to commit
8609 * This will tell DC to commit the constructed DC state from atomic_check,
8610 * programming the hardware. Any failures here implies a hardware failure, since
8611 * atomic check should have filtered anything non-kosher.
8613 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8615 struct drm_device *dev = state->dev;
8616 struct amdgpu_device *adev = drm_to_adev(dev);
8617 struct amdgpu_display_manager *dm = &adev->dm;
8618 struct dm_atomic_state *dm_state;
8619 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8621 struct drm_crtc *crtc;
8622 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8623 unsigned long flags;
8624 bool wait_for_vblank = true;
8625 struct drm_connector *connector;
8626 struct drm_connector_state *old_con_state, *new_con_state;
8627 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8628 int crtc_disable_count = 0;
8629 bool mode_set_reset_required = false;
8631 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8633 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8635 dm_state = dm_atomic_get_new_state(state);
8636 if (dm_state && dm_state->context) {
8637 dc_state = dm_state->context;
8639 /* No state changes, retain current state. */
8640 dc_state_temp = dc_create_state(dm->dc);
8641 ASSERT(dc_state_temp);
8642 dc_state = dc_state_temp;
8643 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8646 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8647 new_crtc_state, i) {
8648 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8650 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8652 if (old_crtc_state->active &&
8653 (!new_crtc_state->active ||
8654 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8655 manage_dm_interrupts(adev, acrtc, false);
8656 dc_stream_release(dm_old_crtc_state->stream);
8660 drm_atomic_helper_calc_timestamping_constants(state);
8662 /* update changed items */
8663 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8664 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8666 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8667 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8670 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8671 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8672 "connectors_changed:%d\n",
8674 new_crtc_state->enable,
8675 new_crtc_state->active,
8676 new_crtc_state->planes_changed,
8677 new_crtc_state->mode_changed,
8678 new_crtc_state->active_changed,
8679 new_crtc_state->connectors_changed);
8681 /* Disable cursor if disabling crtc */
8682 if (old_crtc_state->active && !new_crtc_state->active) {
8683 struct dc_cursor_position position;
8685 memset(&position, 0, sizeof(position));
8686 mutex_lock(&dm->dc_lock);
8687 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8688 mutex_unlock(&dm->dc_lock);
8691 /* Copy all transient state flags into dc state */
8692 if (dm_new_crtc_state->stream) {
8693 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8694 dm_new_crtc_state->stream);
8697 /* handles headless hotplug case, updating new_state and
8698 * aconnector as needed
8701 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8703 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8705 if (!dm_new_crtc_state->stream) {
8707 * this could happen because of issues with
8708 * userspace notifications delivery.
8709 * In this case userspace tries to set mode on
8710 * display which is disconnected in fact.
8711 * dc_sink is NULL in this case on aconnector.
8712 * We expect reset mode will come soon.
8714 * This can also happen when unplug is done
8715 * during resume sequence ended
8717 * In this case, we want to pretend we still
8718 * have a sink to keep the pipe running so that
8719 * hw state is consistent with the sw state
8721 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8722 __func__, acrtc->base.base.id);
8726 if (dm_old_crtc_state->stream)
8727 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8729 pm_runtime_get_noresume(dev->dev);
8731 acrtc->enabled = true;
8732 acrtc->hw_mode = new_crtc_state->mode;
8733 crtc->hwmode = new_crtc_state->mode;
8734 mode_set_reset_required = true;
8735 } else if (modereset_required(new_crtc_state)) {
8736 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8737 /* i.e. reset mode */
8738 if (dm_old_crtc_state->stream)
8739 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8741 mode_set_reset_required = true;
8743 } /* for_each_crtc_in_state() */
8746 /* if there mode set or reset, disable eDP PSR */
8747 if (mode_set_reset_required)
8748 amdgpu_dm_psr_disable_all(dm);
8750 dm_enable_per_frame_crtc_master_sync(dc_state);
8751 mutex_lock(&dm->dc_lock);
8752 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8753 #if defined(CONFIG_DRM_AMD_DC_DCN)
8754 /* Allow idle optimization when vblank count is 0 for display off */
8755 if (dm->active_vblank_irq_count == 0)
8756 dc_allow_idle_optimizations(dm->dc,true);
8758 mutex_unlock(&dm->dc_lock);
8761 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8762 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8764 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8766 if (dm_new_crtc_state->stream != NULL) {
8767 const struct dc_stream_status *status =
8768 dc_stream_get_status(dm_new_crtc_state->stream);
8771 status = dc_stream_get_status_from_state(dc_state,
8772 dm_new_crtc_state->stream);
8774 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8776 acrtc->otg_inst = status->primary_otg_inst;
8779 #ifdef CONFIG_DRM_AMD_DC_HDCP
8780 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8781 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8782 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8783 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8785 new_crtc_state = NULL;
8788 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8790 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8792 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8793 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8794 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8795 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8796 dm_new_con_state->update_hdcp = true;
8800 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8801 hdcp_update_display(
8802 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8803 new_con_state->hdcp_content_type,
8804 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8808 /* Handle connector state changes */
8809 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8810 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8811 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8812 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8813 struct dc_surface_update dummy_updates[MAX_SURFACES];
8814 struct dc_stream_update stream_update;
8815 struct dc_info_packet hdr_packet;
8816 struct dc_stream_status *status = NULL;
8817 bool abm_changed, hdr_changed, scaling_changed;
8819 memset(&dummy_updates, 0, sizeof(dummy_updates));
8820 memset(&stream_update, 0, sizeof(stream_update));
8823 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8824 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8827 /* Skip any modesets/resets */
8828 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8831 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8832 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8834 scaling_changed = is_scaling_state_different(dm_new_con_state,
8837 abm_changed = dm_new_crtc_state->abm_level !=
8838 dm_old_crtc_state->abm_level;
8841 is_hdr_metadata_different(old_con_state, new_con_state);
8843 if (!scaling_changed && !abm_changed && !hdr_changed)
8846 stream_update.stream = dm_new_crtc_state->stream;
8847 if (scaling_changed) {
8848 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8849 dm_new_con_state, dm_new_crtc_state->stream);
8851 stream_update.src = dm_new_crtc_state->stream->src;
8852 stream_update.dst = dm_new_crtc_state->stream->dst;
8856 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8858 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8862 fill_hdr_info_packet(new_con_state, &hdr_packet);
8863 stream_update.hdr_static_metadata = &hdr_packet;
8866 status = dc_stream_get_status(dm_new_crtc_state->stream);
8868 WARN_ON(!status->plane_count);
8871 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8872 * Here we create an empty update on each plane.
8873 * To fix this, DC should permit updating only stream properties.
8875 for (j = 0; j < status->plane_count; j++)
8876 dummy_updates[j].surface = status->plane_states[0];
8879 mutex_lock(&dm->dc_lock);
8880 dc_commit_updates_for_stream(dm->dc,
8882 status->plane_count,
8883 dm_new_crtc_state->stream,
8886 mutex_unlock(&dm->dc_lock);
8889 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8890 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8891 new_crtc_state, i) {
8892 if (old_crtc_state->active && !new_crtc_state->active)
8893 crtc_disable_count++;
8895 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8896 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8898 /* For freesync config update on crtc state and params for irq */
8899 update_stream_irq_parameters(dm, dm_new_crtc_state);
8901 /* Handle vrr on->off / off->on transitions */
8902 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
8907 * Enable interrupts for CRTCs that are newly enabled or went through
8908 * a modeset. It was intentionally deferred until after the front end
8909 * state was modified to wait until the OTG was on and so the IRQ
8910 * handlers didn't access stale or invalid state.
8912 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8913 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8914 #ifdef CONFIG_DEBUG_FS
8915 bool configure_crc = false;
8916 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8918 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8920 if (new_crtc_state->active &&
8921 (!old_crtc_state->active ||
8922 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8923 dc_stream_retain(dm_new_crtc_state->stream);
8924 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8925 manage_dm_interrupts(adev, acrtc, true);
8927 #ifdef CONFIG_DEBUG_FS
8929 * Frontend may have changed so reapply the CRC capture
8930 * settings for the stream.
8932 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8933 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8934 cur_crc_src = acrtc->dm_irq_params.crc_src;
8935 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8937 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8938 configure_crc = true;
8939 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8940 if (amdgpu_dm_crc_window_is_activated(crtc))
8941 configure_crc = false;
8946 amdgpu_dm_crtc_configure_crc_source(
8947 crtc, dm_new_crtc_state, cur_crc_src);
8952 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8953 if (new_crtc_state->async_flip)
8954 wait_for_vblank = false;
8956 /* update planes when needed per crtc*/
8957 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8958 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8960 if (dm_new_crtc_state->stream)
8961 amdgpu_dm_commit_planes(state, dc_state, dev,
8962 dm, crtc, wait_for_vblank);
8965 /* Update audio instances for each connector. */
8966 amdgpu_dm_commit_audio(dev, state);
8969 * send vblank event on all events not handled in flip and
8970 * mark consumed event for drm_atomic_helper_commit_hw_done
8972 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8973 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8975 if (new_crtc_state->event)
8976 drm_send_event_locked(dev, &new_crtc_state->event->base);
8978 new_crtc_state->event = NULL;
8980 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8982 /* Signal HW programming completion */
8983 drm_atomic_helper_commit_hw_done(state);
8985 if (wait_for_vblank)
8986 drm_atomic_helper_wait_for_flip_done(dev, state);
8988 drm_atomic_helper_cleanup_planes(dev, state);
8990 /* return the stolen vga memory back to VRAM */
8991 if (!adev->mman.keep_stolen_vga_memory)
8992 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8993 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8996 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8997 * so we can put the GPU into runtime suspend if we're not driving any
9000 for (i = 0; i < crtc_disable_count; i++)
9001 pm_runtime_put_autosuspend(dev->dev);
9002 pm_runtime_mark_last_busy(dev->dev);
9005 dc_release_state(dc_state_temp);
9009 static int dm_force_atomic_commit(struct drm_connector *connector)
9012 struct drm_device *ddev = connector->dev;
9013 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9014 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9015 struct drm_plane *plane = disconnected_acrtc->base.primary;
9016 struct drm_connector_state *conn_state;
9017 struct drm_crtc_state *crtc_state;
9018 struct drm_plane_state *plane_state;
9023 state->acquire_ctx = ddev->mode_config.acquire_ctx;
9025 /* Construct an atomic state to restore previous display setting */
9028 * Attach connectors to drm_atomic_state
9030 conn_state = drm_atomic_get_connector_state(state, connector);
9032 ret = PTR_ERR_OR_ZERO(conn_state);
9036 /* Attach crtc to drm_atomic_state*/
9037 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9039 ret = PTR_ERR_OR_ZERO(crtc_state);
9043 /* force a restore */
9044 crtc_state->mode_changed = true;
9046 /* Attach plane to drm_atomic_state */
9047 plane_state = drm_atomic_get_plane_state(state, plane);
9049 ret = PTR_ERR_OR_ZERO(plane_state);
9053 /* Call commit internally with the state we just constructed */
9054 ret = drm_atomic_commit(state);
9057 drm_atomic_state_put(state);
9059 DRM_ERROR("Restoring old state failed with %i\n", ret);
9065 * This function handles all cases when set mode does not come upon hotplug.
9066 * This includes when a display is unplugged then plugged back into the
9067 * same port and when running without usermode desktop manager supprot
9069 void dm_restore_drm_connector_state(struct drm_device *dev,
9070 struct drm_connector *connector)
9072 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9073 struct amdgpu_crtc *disconnected_acrtc;
9074 struct dm_crtc_state *acrtc_state;
9076 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9079 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9080 if (!disconnected_acrtc)
9083 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9084 if (!acrtc_state->stream)
9088 * If the previous sink is not released and different from the current,
9089 * we deduce we are in a state where we can not rely on usermode call
9090 * to turn on the display, so we do it here
9092 if (acrtc_state->stream->sink != aconnector->dc_sink)
9093 dm_force_atomic_commit(&aconnector->base);
9097 * Grabs all modesetting locks to serialize against any blocking commits,
9098 * Waits for completion of all non blocking commits.
9100 static int do_aquire_global_lock(struct drm_device *dev,
9101 struct drm_atomic_state *state)
9103 struct drm_crtc *crtc;
9104 struct drm_crtc_commit *commit;
9108 * Adding all modeset locks to aquire_ctx will
9109 * ensure that when the framework release it the
9110 * extra locks we are locking here will get released to
9112 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9116 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9117 spin_lock(&crtc->commit_lock);
9118 commit = list_first_entry_or_null(&crtc->commit_list,
9119 struct drm_crtc_commit, commit_entry);
9121 drm_crtc_commit_get(commit);
9122 spin_unlock(&crtc->commit_lock);
9128 * Make sure all pending HW programming completed and
9131 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9134 ret = wait_for_completion_interruptible_timeout(
9135 &commit->flip_done, 10*HZ);
9138 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9139 "timed out\n", crtc->base.id, crtc->name);
9141 drm_crtc_commit_put(commit);
9144 return ret < 0 ? ret : 0;
9147 static void get_freesync_config_for_crtc(
9148 struct dm_crtc_state *new_crtc_state,
9149 struct dm_connector_state *new_con_state)
9151 struct mod_freesync_config config = {0};
9152 struct amdgpu_dm_connector *aconnector =
9153 to_amdgpu_dm_connector(new_con_state->base.connector);
9154 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9155 int vrefresh = drm_mode_vrefresh(mode);
9156 bool fs_vid_mode = false;
9158 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9159 vrefresh >= aconnector->min_vfreq &&
9160 vrefresh <= aconnector->max_vfreq;
9162 if (new_crtc_state->vrr_supported) {
9163 new_crtc_state->stream->ignore_msa_timing_param = true;
9164 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9166 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9167 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9168 config.vsif_supported = true;
9172 config.state = VRR_STATE_ACTIVE_FIXED;
9173 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9175 } else if (new_crtc_state->base.vrr_enabled) {
9176 config.state = VRR_STATE_ACTIVE_VARIABLE;
9178 config.state = VRR_STATE_INACTIVE;
9182 new_crtc_state->freesync_config = config;
9185 static void reset_freesync_config_for_crtc(
9186 struct dm_crtc_state *new_crtc_state)
9188 new_crtc_state->vrr_supported = false;
9190 memset(&new_crtc_state->vrr_infopacket, 0,
9191 sizeof(new_crtc_state->vrr_infopacket));
9195 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9196 struct drm_crtc_state *new_crtc_state)
9198 struct drm_display_mode old_mode, new_mode;
9200 if (!old_crtc_state || !new_crtc_state)
9203 old_mode = old_crtc_state->mode;
9204 new_mode = new_crtc_state->mode;
9206 if (old_mode.clock == new_mode.clock &&
9207 old_mode.hdisplay == new_mode.hdisplay &&
9208 old_mode.vdisplay == new_mode.vdisplay &&
9209 old_mode.htotal == new_mode.htotal &&
9210 old_mode.vtotal != new_mode.vtotal &&
9211 old_mode.hsync_start == new_mode.hsync_start &&
9212 old_mode.vsync_start != new_mode.vsync_start &&
9213 old_mode.hsync_end == new_mode.hsync_end &&
9214 old_mode.vsync_end != new_mode.vsync_end &&
9215 old_mode.hskew == new_mode.hskew &&
9216 old_mode.vscan == new_mode.vscan &&
9217 (old_mode.vsync_end - old_mode.vsync_start) ==
9218 (new_mode.vsync_end - new_mode.vsync_start))
9224 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9225 uint64_t num, den, res;
9226 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9228 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9230 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9231 den = (unsigned long long)new_crtc_state->mode.htotal *
9232 (unsigned long long)new_crtc_state->mode.vtotal;
9234 res = div_u64(num, den);
9235 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9238 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9239 struct drm_atomic_state *state,
9240 struct drm_crtc *crtc,
9241 struct drm_crtc_state *old_crtc_state,
9242 struct drm_crtc_state *new_crtc_state,
9244 bool *lock_and_validation_needed)
9246 struct dm_atomic_state *dm_state = NULL;
9247 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9248 struct dc_stream_state *new_stream;
9252 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9253 * update changed items
9255 struct amdgpu_crtc *acrtc = NULL;
9256 struct amdgpu_dm_connector *aconnector = NULL;
9257 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9258 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9262 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9263 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9264 acrtc = to_amdgpu_crtc(crtc);
9265 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9267 /* TODO This hack should go away */
9268 if (aconnector && enable) {
9269 /* Make sure fake sink is created in plug-in scenario */
9270 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9272 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9275 if (IS_ERR(drm_new_conn_state)) {
9276 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9280 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9281 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9283 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9286 new_stream = create_validate_stream_for_sink(aconnector,
9287 &new_crtc_state->mode,
9289 dm_old_crtc_state->stream);
9292 * we can have no stream on ACTION_SET if a display
9293 * was disconnected during S3, in this case it is not an
9294 * error, the OS will be updated after detection, and
9295 * will do the right thing on next atomic commit
9299 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9300 __func__, acrtc->base.base.id);
9306 * TODO: Check VSDB bits to decide whether this should
9307 * be enabled or not.
9309 new_stream->triggered_crtc_reset.enabled =
9310 dm->force_timing_sync;
9312 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9314 ret = fill_hdr_info_packet(drm_new_conn_state,
9315 &new_stream->hdr_static_metadata);
9320 * If we already removed the old stream from the context
9321 * (and set the new stream to NULL) then we can't reuse
9322 * the old stream even if the stream and scaling are unchanged.
9323 * We'll hit the BUG_ON and black screen.
9325 * TODO: Refactor this function to allow this check to work
9326 * in all conditions.
9328 if (amdgpu_freesync_vid_mode &&
9329 dm_new_crtc_state->stream &&
9330 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9333 if (dm_new_crtc_state->stream &&
9334 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9335 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9336 new_crtc_state->mode_changed = false;
9337 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9338 new_crtc_state->mode_changed);
9342 /* mode_changed flag may get updated above, need to check again */
9343 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9347 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9348 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9349 "connectors_changed:%d\n",
9351 new_crtc_state->enable,
9352 new_crtc_state->active,
9353 new_crtc_state->planes_changed,
9354 new_crtc_state->mode_changed,
9355 new_crtc_state->active_changed,
9356 new_crtc_state->connectors_changed);
9358 /* Remove stream for any changed/disabled CRTC */
9361 if (!dm_old_crtc_state->stream)
9364 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9365 is_timing_unchanged_for_freesync(new_crtc_state,
9367 new_crtc_state->mode_changed = false;
9369 "Mode change not required for front porch change, "
9370 "setting mode_changed to %d",
9371 new_crtc_state->mode_changed);
9373 set_freesync_fixed_config(dm_new_crtc_state);
9376 } else if (amdgpu_freesync_vid_mode && aconnector &&
9377 is_freesync_video_mode(&new_crtc_state->mode,
9379 set_freesync_fixed_config(dm_new_crtc_state);
9382 ret = dm_atomic_get_state(state, &dm_state);
9386 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9389 /* i.e. reset mode */
9390 if (dc_remove_stream_from_ctx(
9393 dm_old_crtc_state->stream) != DC_OK) {
9398 dc_stream_release(dm_old_crtc_state->stream);
9399 dm_new_crtc_state->stream = NULL;
9401 reset_freesync_config_for_crtc(dm_new_crtc_state);
9403 *lock_and_validation_needed = true;
9405 } else {/* Add stream for any updated/enabled CRTC */
9407 * Quick fix to prevent NULL pointer on new_stream when
9408 * added MST connectors not found in existing crtc_state in the chained mode
9409 * TODO: need to dig out the root cause of that
9411 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
9414 if (modereset_required(new_crtc_state))
9417 if (modeset_required(new_crtc_state, new_stream,
9418 dm_old_crtc_state->stream)) {
9420 WARN_ON(dm_new_crtc_state->stream);
9422 ret = dm_atomic_get_state(state, &dm_state);
9426 dm_new_crtc_state->stream = new_stream;
9428 dc_stream_retain(new_stream);
9430 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9433 if (dc_add_stream_to_ctx(
9436 dm_new_crtc_state->stream) != DC_OK) {
9441 *lock_and_validation_needed = true;
9446 /* Release extra reference */
9448 dc_stream_release(new_stream);
9451 * We want to do dc stream updates that do not require a
9452 * full modeset below.
9454 if (!(enable && aconnector && new_crtc_state->active))
9457 * Given above conditions, the dc state cannot be NULL because:
9458 * 1. We're in the process of enabling CRTCs (just been added
9459 * to the dc context, or already is on the context)
9460 * 2. Has a valid connector attached, and
9461 * 3. Is currently active and enabled.
9462 * => The dc stream state currently exists.
9464 BUG_ON(dm_new_crtc_state->stream == NULL);
9466 /* Scaling or underscan settings */
9467 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
9468 update_stream_scaling_settings(
9469 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9472 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9475 * Color management settings. We also update color properties
9476 * when a modeset is needed, to ensure it gets reprogrammed.
9478 if (dm_new_crtc_state->base.color_mgmt_changed ||
9479 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9480 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9485 /* Update Freesync settings. */
9486 get_freesync_config_for_crtc(dm_new_crtc_state,
9493 dc_stream_release(new_stream);
9497 static bool should_reset_plane(struct drm_atomic_state *state,
9498 struct drm_plane *plane,
9499 struct drm_plane_state *old_plane_state,
9500 struct drm_plane_state *new_plane_state)
9502 struct drm_plane *other;
9503 struct drm_plane_state *old_other_state, *new_other_state;
9504 struct drm_crtc_state *new_crtc_state;
9508 * TODO: Remove this hack once the checks below are sufficient
9509 * enough to determine when we need to reset all the planes on
9512 if (state->allow_modeset)
9515 /* Exit early if we know that we're adding or removing the plane. */
9516 if (old_plane_state->crtc != new_plane_state->crtc)
9519 /* old crtc == new_crtc == NULL, plane not in context. */
9520 if (!new_plane_state->crtc)
9524 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9526 if (!new_crtc_state)
9529 /* CRTC Degamma changes currently require us to recreate planes. */
9530 if (new_crtc_state->color_mgmt_changed)
9533 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9537 * If there are any new primary or overlay planes being added or
9538 * removed then the z-order can potentially change. To ensure
9539 * correct z-order and pipe acquisition the current DC architecture
9540 * requires us to remove and recreate all existing planes.
9542 * TODO: Come up with a more elegant solution for this.
9544 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9545 struct amdgpu_framebuffer *old_afb, *new_afb;
9546 if (other->type == DRM_PLANE_TYPE_CURSOR)
9549 if (old_other_state->crtc != new_plane_state->crtc &&
9550 new_other_state->crtc != new_plane_state->crtc)
9553 if (old_other_state->crtc != new_other_state->crtc)
9556 /* Src/dst size and scaling updates. */
9557 if (old_other_state->src_w != new_other_state->src_w ||
9558 old_other_state->src_h != new_other_state->src_h ||
9559 old_other_state->crtc_w != new_other_state->crtc_w ||
9560 old_other_state->crtc_h != new_other_state->crtc_h)
9563 /* Rotation / mirroring updates. */
9564 if (old_other_state->rotation != new_other_state->rotation)
9567 /* Blending updates. */
9568 if (old_other_state->pixel_blend_mode !=
9569 new_other_state->pixel_blend_mode)
9572 /* Alpha updates. */
9573 if (old_other_state->alpha != new_other_state->alpha)
9576 /* Colorspace changes. */
9577 if (old_other_state->color_range != new_other_state->color_range ||
9578 old_other_state->color_encoding != new_other_state->color_encoding)
9581 /* Framebuffer checks fall at the end. */
9582 if (!old_other_state->fb || !new_other_state->fb)
9585 /* Pixel format changes can require bandwidth updates. */
9586 if (old_other_state->fb->format != new_other_state->fb->format)
9589 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9590 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9592 /* Tiling and DCC changes also require bandwidth updates. */
9593 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9594 old_afb->base.modifier != new_afb->base.modifier)
9601 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9602 struct drm_plane_state *new_plane_state,
9603 struct drm_framebuffer *fb)
9605 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9606 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9610 if (fb->width > new_acrtc->max_cursor_width ||
9611 fb->height > new_acrtc->max_cursor_height) {
9612 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9613 new_plane_state->fb->width,
9614 new_plane_state->fb->height);
9617 if (new_plane_state->src_w != fb->width << 16 ||
9618 new_plane_state->src_h != fb->height << 16) {
9619 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9623 /* Pitch in pixels */
9624 pitch = fb->pitches[0] / fb->format->cpp[0];
9626 if (fb->width != pitch) {
9627 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9636 /* FB pitch is supported by cursor plane */
9639 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9643 /* Core DRM takes care of checking FB modifiers, so we only need to
9644 * check tiling flags when the FB doesn't have a modifier. */
9645 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9646 if (adev->family < AMDGPU_FAMILY_AI) {
9647 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9648 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9649 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9651 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9654 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9662 static int dm_update_plane_state(struct dc *dc,
9663 struct drm_atomic_state *state,
9664 struct drm_plane *plane,
9665 struct drm_plane_state *old_plane_state,
9666 struct drm_plane_state *new_plane_state,
9668 bool *lock_and_validation_needed)
9671 struct dm_atomic_state *dm_state = NULL;
9672 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9673 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9674 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9675 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9676 struct amdgpu_crtc *new_acrtc;
9681 new_plane_crtc = new_plane_state->crtc;
9682 old_plane_crtc = old_plane_state->crtc;
9683 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9684 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9686 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9687 if (!enable || !new_plane_crtc ||
9688 drm_atomic_plane_disabling(plane->state, new_plane_state))
9691 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9693 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9694 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9698 if (new_plane_state->fb) {
9699 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9700 new_plane_state->fb);
9708 needs_reset = should_reset_plane(state, plane, old_plane_state,
9711 /* Remove any changed/removed planes */
9716 if (!old_plane_crtc)
9719 old_crtc_state = drm_atomic_get_old_crtc_state(
9720 state, old_plane_crtc);
9721 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9723 if (!dm_old_crtc_state->stream)
9726 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9727 plane->base.id, old_plane_crtc->base.id);
9729 ret = dm_atomic_get_state(state, &dm_state);
9733 if (!dc_remove_plane_from_context(
9735 dm_old_crtc_state->stream,
9736 dm_old_plane_state->dc_state,
9737 dm_state->context)) {
9743 dc_plane_state_release(dm_old_plane_state->dc_state);
9744 dm_new_plane_state->dc_state = NULL;
9746 *lock_and_validation_needed = true;
9748 } else { /* Add new planes */
9749 struct dc_plane_state *dc_new_plane_state;
9751 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9754 if (!new_plane_crtc)
9757 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9758 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9760 if (!dm_new_crtc_state->stream)
9766 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9770 WARN_ON(dm_new_plane_state->dc_state);
9772 dc_new_plane_state = dc_create_plane_state(dc);
9773 if (!dc_new_plane_state)
9776 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9777 plane->base.id, new_plane_crtc->base.id);
9779 ret = fill_dc_plane_attributes(
9780 drm_to_adev(new_plane_crtc->dev),
9785 dc_plane_state_release(dc_new_plane_state);
9789 ret = dm_atomic_get_state(state, &dm_state);
9791 dc_plane_state_release(dc_new_plane_state);
9796 * Any atomic check errors that occur after this will
9797 * not need a release. The plane state will be attached
9798 * to the stream, and therefore part of the atomic
9799 * state. It'll be released when the atomic state is
9802 if (!dc_add_plane_to_context(
9804 dm_new_crtc_state->stream,
9806 dm_state->context)) {
9808 dc_plane_state_release(dc_new_plane_state);
9812 dm_new_plane_state->dc_state = dc_new_plane_state;
9814 /* Tell DC to do a full surface update every time there
9815 * is a plane change. Inefficient, but works for now.
9817 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9819 *lock_and_validation_needed = true;
9826 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9827 struct drm_crtc *crtc,
9828 struct drm_crtc_state *new_crtc_state)
9830 struct drm_plane_state *new_cursor_state, *new_primary_state;
9831 int cursor_scale_w, cursor_scale_h, primary_scale_w, primary_scale_h;
9833 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9834 * cursor per pipe but it's going to inherit the scaling and
9835 * positioning from the underlying pipe. Check the cursor plane's
9836 * blending properties match the primary plane's. */
9838 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
9839 new_primary_state = drm_atomic_get_new_plane_state(state, crtc->primary);
9840 if (!new_cursor_state || !new_primary_state ||
9841 !new_cursor_state->fb || !new_primary_state->fb) {
9845 cursor_scale_w = new_cursor_state->crtc_w * 1000 /
9846 (new_cursor_state->src_w >> 16);
9847 cursor_scale_h = new_cursor_state->crtc_h * 1000 /
9848 (new_cursor_state->src_h >> 16);
9850 primary_scale_w = new_primary_state->crtc_w * 1000 /
9851 (new_primary_state->src_w >> 16);
9852 primary_scale_h = new_primary_state->crtc_h * 1000 /
9853 (new_primary_state->src_h >> 16);
9855 if (cursor_scale_w != primary_scale_w ||
9856 cursor_scale_h != primary_scale_h) {
9857 drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't match primary plane\n");
9864 #if defined(CONFIG_DRM_AMD_DC_DCN)
9865 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9867 struct drm_connector *connector;
9868 struct drm_connector_state *conn_state;
9869 struct amdgpu_dm_connector *aconnector = NULL;
9871 for_each_new_connector_in_state(state, connector, conn_state, i) {
9872 if (conn_state->crtc != crtc)
9875 aconnector = to_amdgpu_dm_connector(connector);
9876 if (!aconnector->port || !aconnector->mst_port)
9885 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9889 static int validate_overlay(struct drm_atomic_state *state)
9892 struct drm_plane *plane;
9893 struct drm_plane_state *old_plane_state, *new_plane_state;
9894 struct drm_plane_state *primary_state, *cursor_state, *overlay_state = NULL;
9896 /* Check if primary plane is contained inside overlay */
9897 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9898 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9899 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9902 overlay_state = new_plane_state;
9907 /* check if we're making changes to the overlay plane */
9911 /* check if overlay plane is enabled */
9912 if (!overlay_state->crtc)
9915 /* find the primary plane for the CRTC that the overlay is enabled on */
9916 primary_state = drm_atomic_get_plane_state(state, overlay_state->crtc->primary);
9917 if (IS_ERR(primary_state))
9918 return PTR_ERR(primary_state);
9920 /* check if primary plane is enabled */
9921 if (!primary_state->crtc)
9924 /* check if cursor plane is enabled */
9925 cursor_state = drm_atomic_get_plane_state(state, overlay_state->crtc->cursor);
9926 if (IS_ERR(cursor_state))
9927 return PTR_ERR(cursor_state);
9929 if (drm_atomic_plane_disabling(plane->state, cursor_state))
9932 /* Perform the bounds check to ensure the overlay plane covers the primary */
9933 if (primary_state->crtc_x < overlay_state->crtc_x ||
9934 primary_state->crtc_y < overlay_state->crtc_y ||
9935 primary_state->crtc_x + primary_state->crtc_w > overlay_state->crtc_x + overlay_state->crtc_w ||
9936 primary_state->crtc_y + primary_state->crtc_h > overlay_state->crtc_y + overlay_state->crtc_h) {
9937 DRM_DEBUG_ATOMIC("Overlay plane is enabled with hardware cursor but does not fully cover primary plane\n");
9945 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9946 * @dev: The DRM device
9947 * @state: The atomic state to commit
9949 * Validate that the given atomic state is programmable by DC into hardware.
9950 * This involves constructing a &struct dc_state reflecting the new hardware
9951 * state we wish to commit, then querying DC to see if it is programmable. It's
9952 * important not to modify the existing DC state. Otherwise, atomic_check
9953 * may unexpectedly commit hardware changes.
9955 * When validating the DC state, it's important that the right locks are
9956 * acquired. For full updates case which removes/adds/updates streams on one
9957 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9958 * that any such full update commit will wait for completion of any outstanding
9959 * flip using DRMs synchronization events.
9961 * Note that DM adds the affected connectors for all CRTCs in state, when that
9962 * might not seem necessary. This is because DC stream creation requires the
9963 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9964 * be possible but non-trivial - a possible TODO item.
9966 * Return: -Error code if validation failed.
9968 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9969 struct drm_atomic_state *state)
9971 struct amdgpu_device *adev = drm_to_adev(dev);
9972 struct dm_atomic_state *dm_state = NULL;
9973 struct dc *dc = adev->dm.dc;
9974 struct drm_connector *connector;
9975 struct drm_connector_state *old_con_state, *new_con_state;
9976 struct drm_crtc *crtc;
9977 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9978 struct drm_plane *plane;
9979 struct drm_plane_state *old_plane_state, *new_plane_state;
9980 enum dc_status status;
9982 bool lock_and_validation_needed = false;
9983 struct dm_crtc_state *dm_old_crtc_state;
9985 trace_amdgpu_dm_atomic_check_begin(state);
9987 ret = drm_atomic_helper_check_modeset(dev, state);
9991 /* Check connector changes */
9992 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9993 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9994 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9996 /* Skip connectors that are disabled or part of modeset already. */
9997 if (!old_con_state->crtc && !new_con_state->crtc)
10000 if (!new_con_state->crtc)
10003 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10004 if (IS_ERR(new_crtc_state)) {
10005 ret = PTR_ERR(new_crtc_state);
10009 if (dm_old_con_state->abm_level !=
10010 dm_new_con_state->abm_level)
10011 new_crtc_state->connectors_changed = true;
10014 #if defined(CONFIG_DRM_AMD_DC_DCN)
10015 if (dc_resource_is_dsc_encoding_supported(dc)) {
10016 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10017 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10018 ret = add_affected_mst_dsc_crtcs(state, crtc);
10025 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10026 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10028 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10029 !new_crtc_state->color_mgmt_changed &&
10030 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10031 dm_old_crtc_state->dsc_force_changed == false)
10034 if (!new_crtc_state->enable)
10037 ret = drm_atomic_add_affected_connectors(state, crtc);
10041 ret = drm_atomic_add_affected_planes(state, crtc);
10045 if (dm_old_crtc_state->dsc_force_changed)
10046 new_crtc_state->mode_changed = true;
10050 * Add all primary and overlay planes on the CRTC to the state
10051 * whenever a plane is enabled to maintain correct z-ordering
10052 * and to enable fast surface updates.
10054 drm_for_each_crtc(crtc, dev) {
10055 bool modified = false;
10057 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10058 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10061 if (new_plane_state->crtc == crtc ||
10062 old_plane_state->crtc == crtc) {
10071 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10072 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10076 drm_atomic_get_plane_state(state, plane);
10078 if (IS_ERR(new_plane_state)) {
10079 ret = PTR_ERR(new_plane_state);
10085 /* Remove exiting planes if they are modified */
10086 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10087 ret = dm_update_plane_state(dc, state, plane,
10091 &lock_and_validation_needed);
10096 /* Disable all crtcs which require disable */
10097 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10098 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10102 &lock_and_validation_needed);
10107 /* Enable all crtcs which require enable */
10108 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10109 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10113 &lock_and_validation_needed);
10118 ret = validate_overlay(state);
10122 /* Add new/modified planes */
10123 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10124 ret = dm_update_plane_state(dc, state, plane,
10128 &lock_and_validation_needed);
10133 /* Run this here since we want to validate the streams we created */
10134 ret = drm_atomic_helper_check_planes(dev, state);
10138 /* Check cursor planes scaling */
10139 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10140 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10145 if (state->legacy_cursor_update) {
10147 * This is a fast cursor update coming from the plane update
10148 * helper, check if it can be done asynchronously for better
10151 state->async_update =
10152 !drm_atomic_helper_async_check(dev, state);
10155 * Skip the remaining global validation if this is an async
10156 * update. Cursor updates can be done without affecting
10157 * state or bandwidth calcs and this avoids the performance
10158 * penalty of locking the private state object and
10159 * allocating a new dc_state.
10161 if (state->async_update)
10165 /* Check scaling and underscan changes*/
10166 /* TODO Removed scaling changes validation due to inability to commit
10167 * new stream into context w\o causing full reset. Need to
10168 * decide how to handle.
10170 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10171 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10172 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10173 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10175 /* Skip any modesets/resets */
10176 if (!acrtc || drm_atomic_crtc_needs_modeset(
10177 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10180 /* Skip any thing not scale or underscan changes */
10181 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10184 lock_and_validation_needed = true;
10188 * Streams and planes are reset when there are changes that affect
10189 * bandwidth. Anything that affects bandwidth needs to go through
10190 * DC global validation to ensure that the configuration can be applied
10193 * We have to currently stall out here in atomic_check for outstanding
10194 * commits to finish in this case because our IRQ handlers reference
10195 * DRM state directly - we can end up disabling interrupts too early
10198 * TODO: Remove this stall and drop DM state private objects.
10200 if (lock_and_validation_needed) {
10201 ret = dm_atomic_get_state(state, &dm_state);
10205 ret = do_aquire_global_lock(dev, state);
10209 #if defined(CONFIG_DRM_AMD_DC_DCN)
10210 if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
10213 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
10219 * Perform validation of MST topology in the state:
10220 * We need to perform MST atomic check before calling
10221 * dc_validate_global_state(), or there is a chance
10222 * to get stuck in an infinite loop and hang eventually.
10224 ret = drm_dp_mst_atomic_check(state);
10227 status = dc_validate_global_state(dc, dm_state->context, false);
10228 if (status != DC_OK) {
10229 DC_LOG_WARNING("DC global validation failure: %s (%d)",
10230 dc_status_to_str(status), status);
10236 * The commit is a fast update. Fast updates shouldn't change
10237 * the DC context, affect global validation, and can have their
10238 * commit work done in parallel with other commits not touching
10239 * the same resource. If we have a new DC context as part of
10240 * the DM atomic state from validation we need to free it and
10241 * retain the existing one instead.
10243 * Furthermore, since the DM atomic state only contains the DC
10244 * context and can safely be annulled, we can free the state
10245 * and clear the associated private object now to free
10246 * some memory and avoid a possible use-after-free later.
10249 for (i = 0; i < state->num_private_objs; i++) {
10250 struct drm_private_obj *obj = state->private_objs[i].ptr;
10252 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10253 int j = state->num_private_objs-1;
10255 dm_atomic_destroy_state(obj,
10256 state->private_objs[i].state);
10258 /* If i is not at the end of the array then the
10259 * last element needs to be moved to where i was
10260 * before the array can safely be truncated.
10263 state->private_objs[i] =
10264 state->private_objs[j];
10266 state->private_objs[j].ptr = NULL;
10267 state->private_objs[j].state = NULL;
10268 state->private_objs[j].old_state = NULL;
10269 state->private_objs[j].new_state = NULL;
10271 state->num_private_objs = j;
10277 /* Store the overall update type for use later in atomic check. */
10278 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10279 struct dm_crtc_state *dm_new_crtc_state =
10280 to_dm_crtc_state(new_crtc_state);
10282 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10287 /* Must be success */
10290 trace_amdgpu_dm_atomic_check_finish(state, ret);
10295 if (ret == -EDEADLK)
10296 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10297 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10298 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10300 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10302 trace_amdgpu_dm_atomic_check_finish(state, ret);
10307 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10308 struct amdgpu_dm_connector *amdgpu_dm_connector)
10311 bool capable = false;
10313 if (amdgpu_dm_connector->dc_link &&
10314 dm_helpers_dp_read_dpcd(
10316 amdgpu_dm_connector->dc_link,
10317 DP_DOWN_STREAM_PORT_COUNT,
10319 sizeof(dpcd_data))) {
10320 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10326 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10327 uint8_t *edid_ext, int len,
10328 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10331 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10332 struct dc *dc = adev->dm.dc;
10334 /* send extension block to DMCU for parsing */
10335 for (i = 0; i < len; i += 8) {
10339 /* send 8 bytes a time */
10340 if (!dc_edid_parser_send_cea(dc, i, len, &edid_ext[i], 8))
10344 /* EDID block sent completed, expect result */
10345 int version, min_rate, max_rate;
10347 res = dc_edid_parser_recv_amd_vsdb(dc, &version, &min_rate, &max_rate);
10349 /* amd vsdb found */
10350 vsdb_info->freesync_supported = 1;
10351 vsdb_info->amd_vsdb_version = version;
10352 vsdb_info->min_refresh_rate_hz = min_rate;
10353 vsdb_info->max_refresh_rate_hz = max_rate;
10361 res = dc_edid_parser_recv_cea_ack(dc, &offset);
10369 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10370 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10372 uint8_t *edid_ext = NULL;
10374 bool valid_vsdb_found = false;
10376 /*----- drm_find_cea_extension() -----*/
10377 /* No EDID or EDID extensions */
10378 if (edid == NULL || edid->extensions == 0)
10381 /* Find CEA extension */
10382 for (i = 0; i < edid->extensions; i++) {
10383 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10384 if (edid_ext[0] == CEA_EXT)
10388 if (i == edid->extensions)
10391 /*----- cea_db_offsets() -----*/
10392 if (edid_ext[0] != CEA_EXT)
10395 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10397 return valid_vsdb_found ? i : -ENODEV;
10400 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10404 struct detailed_timing *timing;
10405 struct detailed_non_pixel *data;
10406 struct detailed_data_monitor_range *range;
10407 struct amdgpu_dm_connector *amdgpu_dm_connector =
10408 to_amdgpu_dm_connector(connector);
10409 struct dm_connector_state *dm_con_state = NULL;
10411 struct drm_device *dev = connector->dev;
10412 struct amdgpu_device *adev = drm_to_adev(dev);
10413 bool freesync_capable = false;
10414 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10416 if (!connector->state) {
10417 DRM_ERROR("%s - Connector has no state", __func__);
10422 dm_con_state = to_dm_connector_state(connector->state);
10424 amdgpu_dm_connector->min_vfreq = 0;
10425 amdgpu_dm_connector->max_vfreq = 0;
10426 amdgpu_dm_connector->pixel_clock_mhz = 0;
10431 dm_con_state = to_dm_connector_state(connector->state);
10433 if (!amdgpu_dm_connector->dc_sink) {
10434 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
10437 if (!adev->dm.freesync_module)
10441 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10442 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
10443 bool edid_check_required = false;
10446 edid_check_required = is_dp_capable_without_timing_msa(
10448 amdgpu_dm_connector);
10451 if (edid_check_required == true && (edid->version > 1 ||
10452 (edid->version == 1 && edid->revision > 1))) {
10453 for (i = 0; i < 4; i++) {
10455 timing = &edid->detailed_timings[i];
10456 data = &timing->data.other_data;
10457 range = &data->data.range;
10459 * Check if monitor has continuous frequency mode
10461 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10464 * Check for flag range limits only. If flag == 1 then
10465 * no additional timing information provided.
10466 * Default GTF, GTF Secondary curve and CVT are not
10469 if (range->flags != 1)
10472 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10473 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10474 amdgpu_dm_connector->pixel_clock_mhz =
10475 range->pixel_clock_mhz * 10;
10477 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10478 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10483 if (amdgpu_dm_connector->max_vfreq -
10484 amdgpu_dm_connector->min_vfreq > 10) {
10486 freesync_capable = true;
10489 } else if (edid && amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10490 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10491 if (i >= 0 && vsdb_info.freesync_supported) {
10492 timing = &edid->detailed_timings[i];
10493 data = &timing->data.other_data;
10495 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10496 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10497 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10498 freesync_capable = true;
10500 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10501 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10507 dm_con_state->freesync_capable = freesync_capable;
10509 if (connector->vrr_capable_property)
10510 drm_connector_set_vrr_capable_property(connector,
10514 static void amdgpu_dm_set_psr_caps(struct dc_link *link)
10516 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
10518 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
10520 if (link->type == dc_connection_none)
10522 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
10523 dpcd_data, sizeof(dpcd_data))) {
10524 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
10526 if (dpcd_data[0] == 0) {
10527 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
10528 link->psr_settings.psr_feature_enabled = false;
10530 link->psr_settings.psr_version = DC_PSR_VERSION_1;
10531 link->psr_settings.psr_feature_enabled = true;
10534 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
10539 * amdgpu_dm_link_setup_psr() - configure psr link
10540 * @stream: stream state
10542 * Return: true if success
10544 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
10546 struct dc_link *link = NULL;
10547 struct psr_config psr_config = {0};
10548 struct psr_context psr_context = {0};
10551 if (stream == NULL)
10554 link = stream->link;
10556 psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
10558 if (psr_config.psr_version > 0) {
10559 psr_config.psr_exit_link_training_required = 0x1;
10560 psr_config.psr_frame_capture_indication_req = 0;
10561 psr_config.psr_rfb_setup_time = 0x37;
10562 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
10563 psr_config.allow_smu_optimizations = 0x0;
10565 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
10568 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
10574 * amdgpu_dm_psr_enable() - enable psr f/w
10575 * @stream: stream state
10577 * Return: true if success
10579 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
10581 struct dc_link *link = stream->link;
10582 unsigned int vsync_rate_hz = 0;
10583 struct dc_static_screen_params params = {0};
10584 /* Calculate number of static frames before generating interrupt to
10587 // Init fail safe of 2 frames static
10588 unsigned int num_frames_static = 2;
10590 DRM_DEBUG_DRIVER("Enabling psr...\n");
10592 vsync_rate_hz = div64_u64(div64_u64((
10593 stream->timing.pix_clk_100hz * 100),
10594 stream->timing.v_total),
10595 stream->timing.h_total);
10598 * Calculate number of frames such that at least 30 ms of time has
10601 if (vsync_rate_hz != 0) {
10602 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
10603 num_frames_static = (30000 / frame_time_microsec) + 1;
10606 params.triggers.cursor_update = true;
10607 params.triggers.overlay_update = true;
10608 params.triggers.surface_update = true;
10609 params.num_frames = num_frames_static;
10611 dc_stream_set_static_screen_params(link->ctx->dc,
10615 return dc_link_set_psr_allow_active(link, true, false, false);
10619 * amdgpu_dm_psr_disable() - disable psr f/w
10620 * @stream: stream state
10622 * Return: true if success
10624 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
10627 DRM_DEBUG_DRIVER("Disabling psr...\n");
10629 return dc_link_set_psr_allow_active(stream->link, false, true, false);
10633 * amdgpu_dm_psr_disable() - disable psr f/w
10634 * if psr is enabled on any stream
10636 * Return: true if success
10638 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
10640 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
10641 return dc_set_psr_allow_active(dm->dc, false);
10644 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10646 struct amdgpu_device *adev = drm_to_adev(dev);
10647 struct dc *dc = adev->dm.dc;
10650 mutex_lock(&adev->dm.dc_lock);
10651 if (dc->current_state) {
10652 for (i = 0; i < dc->current_state->stream_count; ++i)
10653 dc->current_state->streams[i]
10654 ->triggered_crtc_reset.enabled =
10655 adev->dm.force_timing_sync;
10657 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10658 dc_trigger_sync(dc, dc->current_state);
10660 mutex_unlock(&adev->dm.dc_lock);
10663 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10664 uint32_t value, const char *func_name)
10666 #ifdef DM_CHECK_ADDR_0
10667 if (address == 0) {
10668 DC_ERR("invalid register write. address = 0");
10672 cgs_write_register(ctx->cgs_device, address, value);
10673 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10676 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10677 const char *func_name)
10680 #ifdef DM_CHECK_ADDR_0
10681 if (address == 0) {
10682 DC_ERR("invalid register read; address = 0\n");
10687 if (ctx->dmub_srv &&
10688 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10689 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10694 value = cgs_read_register(ctx->cgs_device, address);
10696 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);