2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
47 #include "amdgpu_display.h"
48 #include "amdgpu_ucode.h"
50 #include "amdgpu_dm.h"
51 #include "amdgpu_dm_plane.h"
52 #include "amdgpu_dm_crtc.h"
53 #ifdef CONFIG_DRM_AMD_DC_HDCP
54 #include "amdgpu_dm_hdcp.h"
55 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
67 #include "amdgpu_dm_psr.h"
69 #include "ivsrcid/ivsrcid_vislands30.h"
71 #include <linux/backlight.h>
72 #include <linux/module.h>
73 #include <linux/moduleparam.h>
74 #include <linux/types.h>
75 #include <linux/pm_runtime.h>
76 #include <linux/pci.h>
77 #include <linux/firmware.h>
78 #include <linux/component.h>
79 #include <linux/dmi.h>
81 #include <drm/display/drm_dp_mst_helper.h>
82 #include <drm/display/drm_hdmi_helper.h>
83 #include <drm/drm_atomic.h>
84 #include <drm/drm_atomic_uapi.h>
85 #include <drm/drm_atomic_helper.h>
86 #include <drm/drm_blend.h>
87 #include <drm/drm_fourcc.h>
88 #include <drm/drm_edid.h>
89 #include <drm/drm_vblank.h>
90 #include <drm/drm_audio_component.h>
91 #include <drm/drm_gem_atomic_helper.h>
92 #include <drm/drm_plane_helper.h>
94 #include <acpi/video.h>
96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
98 #include "dcn/dcn_1_0_offset.h"
99 #include "dcn/dcn_1_0_sh_mask.h"
100 #include "soc15_hw_ip.h"
101 #include "soc15_common.h"
102 #include "vega10_ip_offset.h"
104 #include "gc/gc_11_0_0_offset.h"
105 #include "gc/gc_11_0_0_sh_mask.h"
107 #include "modules/inc/mod_freesync.h"
108 #include "modules/power/power_helpers.h"
109 #include "modules/inc/mod_info_packet.h"
111 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
112 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
113 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
114 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
115 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
116 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
117 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
118 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
119 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
120 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
121 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
122 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
123 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
124 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
125 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
126 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
127 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
128 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
129 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
130 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
131 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
132 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
134 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
136 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
139 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
140 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
142 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
143 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
145 /* Number of bytes in PSP header for firmware. */
146 #define PSP_HEADER_BYTES 0x100
148 /* Number of bytes in PSP footer for firmware. */
149 #define PSP_FOOTER_BYTES 0x100
154 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
155 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
156 * requests into DC requests, and DC responses into DRM responses.
158 * The root control structure is &struct amdgpu_display_manager.
161 /* basic init/fini API */
162 static int amdgpu_dm_init(struct amdgpu_device *adev);
163 static void amdgpu_dm_fini(struct amdgpu_device *adev);
164 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
166 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
168 switch (link->dpcd_caps.dongle_type) {
169 case DISPLAY_DONGLE_NONE:
170 return DRM_MODE_SUBCONNECTOR_Native;
171 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
172 return DRM_MODE_SUBCONNECTOR_VGA;
173 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
174 case DISPLAY_DONGLE_DP_DVI_DONGLE:
175 return DRM_MODE_SUBCONNECTOR_DVID;
176 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
177 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
178 return DRM_MODE_SUBCONNECTOR_HDMIA;
179 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
181 return DRM_MODE_SUBCONNECTOR_Unknown;
185 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
187 struct dc_link *link = aconnector->dc_link;
188 struct drm_connector *connector = &aconnector->base;
189 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
191 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
194 if (aconnector->dc_sink)
195 subconnector = get_subconnector_type(link);
197 drm_object_property_set_value(&connector->base,
198 connector->dev->mode_config.dp_subconnector_property,
203 * initializes drm_device display related structures, based on the information
204 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
205 * drm_encoder, drm_mode_config
207 * Returns 0 on success
209 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
210 /* removes and deallocates the drm structures, created by the above function */
211 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
213 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
214 struct amdgpu_dm_connector *amdgpu_dm_connector,
216 struct amdgpu_encoder *amdgpu_encoder);
217 static int amdgpu_dm_encoder_init(struct drm_device *dev,
218 struct amdgpu_encoder *aencoder,
219 uint32_t link_index);
221 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
223 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
225 static int amdgpu_dm_atomic_check(struct drm_device *dev,
226 struct drm_atomic_state *state);
228 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
229 static void handle_hpd_rx_irq(void *param);
232 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
233 struct drm_crtc_state *new_crtc_state);
235 * dm_vblank_get_counter
238 * Get counter for number of vertical blanks
241 * struct amdgpu_device *adev - [in] desired amdgpu device
242 * int disp_idx - [in] which CRTC to get the counter from
245 * Counter for vertical blanks
247 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
249 if (crtc >= adev->mode_info.num_crtc)
252 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
254 if (acrtc->dm_irq_params.stream == NULL) {
255 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
260 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
264 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
265 u32 *vbl, u32 *position)
267 u32 v_blank_start, v_blank_end, h_position, v_position;
269 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
272 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
274 if (acrtc->dm_irq_params.stream == NULL) {
275 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
281 * TODO rework base driver to use values directly.
282 * for now parse it back into reg-format
284 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
290 *position = v_position | (h_position << 16);
291 *vbl = v_blank_start | (v_blank_end << 16);
297 static bool dm_is_idle(void *handle)
303 static int dm_wait_for_idle(void *handle)
309 static bool dm_check_soft_reset(void *handle)
314 static int dm_soft_reset(void *handle)
320 static struct amdgpu_crtc *
321 get_crtc_by_otg_inst(struct amdgpu_device *adev,
324 struct drm_device *dev = adev_to_drm(adev);
325 struct drm_crtc *crtc;
326 struct amdgpu_crtc *amdgpu_crtc;
328 if (WARN_ON(otg_inst == -1))
329 return adev->mode_info.crtcs[0];
331 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
332 amdgpu_crtc = to_amdgpu_crtc(crtc);
334 if (amdgpu_crtc->otg_inst == otg_inst)
341 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
342 struct dm_crtc_state *new_state)
344 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
346 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
353 * dm_pflip_high_irq() - Handle pageflip interrupt
354 * @interrupt_params: ignored
356 * Handles the pageflip interrupt by notifying all interested parties
357 * that the pageflip has been completed.
359 static void dm_pflip_high_irq(void *interrupt_params)
361 struct amdgpu_crtc *amdgpu_crtc;
362 struct common_irq_params *irq_params = interrupt_params;
363 struct amdgpu_device *adev = irq_params->adev;
365 struct drm_pending_vblank_event *e;
366 u32 vpos, hpos, v_blank_start, v_blank_end;
369 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
371 /* IRQ could occur when in initial stage */
372 /* TODO work and BO cleanup */
373 if (amdgpu_crtc == NULL) {
374 DC_LOG_PFLIP("CRTC is null, returning.\n");
378 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
380 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
381 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
382 amdgpu_crtc->pflip_status,
383 AMDGPU_FLIP_SUBMITTED,
384 amdgpu_crtc->crtc_id,
386 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
390 /* page flip completed. */
391 e = amdgpu_crtc->event;
392 amdgpu_crtc->event = NULL;
396 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
398 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
400 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
401 &v_blank_end, &hpos, &vpos) ||
402 (vpos < v_blank_start)) {
403 /* Update to correct count and vblank timestamp if racing with
404 * vblank irq. This also updates to the correct vblank timestamp
405 * even in VRR mode, as scanout is past the front-porch atm.
407 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
409 /* Wake up userspace by sending the pageflip event with proper
410 * count and timestamp of vblank of flip completion.
413 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
415 /* Event sent, so done with vblank for this flip */
416 drm_crtc_vblank_put(&amdgpu_crtc->base);
419 /* VRR active and inside front-porch: vblank count and
420 * timestamp for pageflip event will only be up to date after
421 * drm_crtc_handle_vblank() has been executed from late vblank
422 * irq handler after start of back-porch (vline 0). We queue the
423 * pageflip event for send-out by drm_crtc_handle_vblank() with
424 * updated timestamp and count, once it runs after us.
426 * We need to open-code this instead of using the helper
427 * drm_crtc_arm_vblank_event(), as that helper would
428 * call drm_crtc_accurate_vblank_count(), which we must
429 * not call in VRR mode while we are in front-porch!
432 /* sequence will be replaced by real count during send-out. */
433 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
434 e->pipe = amdgpu_crtc->crtc_id;
436 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
440 /* Keep track of vblank of this flip for flip throttling. We use the
441 * cooked hw counter, as that one incremented at start of this vblank
442 * of pageflip completion, so last_flip_vblank is the forbidden count
443 * for queueing new pageflips if vsync + VRR is enabled.
445 amdgpu_crtc->dm_irq_params.last_flip_vblank =
446 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
448 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
449 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
451 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
452 amdgpu_crtc->crtc_id, amdgpu_crtc,
453 vrr_active, (int) !e);
456 static void dm_vupdate_high_irq(void *interrupt_params)
458 struct common_irq_params *irq_params = interrupt_params;
459 struct amdgpu_device *adev = irq_params->adev;
460 struct amdgpu_crtc *acrtc;
461 struct drm_device *drm_dev;
462 struct drm_vblank_crtc *vblank;
463 ktime_t frame_duration_ns, previous_timestamp;
467 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
470 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
471 drm_dev = acrtc->base.dev;
472 vblank = &drm_dev->vblank[acrtc->base.index];
473 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
474 frame_duration_ns = vblank->time - previous_timestamp;
476 if (frame_duration_ns > 0) {
477 trace_amdgpu_refresh_rate_track(acrtc->base.index,
479 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
480 atomic64_set(&irq_params->previous_timestamp, vblank->time);
483 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
487 /* Core vblank handling is done here after end of front-porch in
488 * vrr mode, as vblank timestamping will give valid results
489 * while now done after front-porch. This will also deliver
490 * page-flip completion events that have been queued to us
491 * if a pageflip happened inside front-porch.
494 dm_crtc_handle_vblank(acrtc);
496 /* BTR processing for pre-DCE12 ASICs */
497 if (acrtc->dm_irq_params.stream &&
498 adev->family < AMDGPU_FAMILY_AI) {
499 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
500 mod_freesync_handle_v_update(
501 adev->dm.freesync_module,
502 acrtc->dm_irq_params.stream,
503 &acrtc->dm_irq_params.vrr_params);
505 dc_stream_adjust_vmin_vmax(
507 acrtc->dm_irq_params.stream,
508 &acrtc->dm_irq_params.vrr_params.adjust);
509 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
516 * dm_crtc_high_irq() - Handles CRTC interrupt
517 * @interrupt_params: used for determining the CRTC instance
519 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
522 static void dm_crtc_high_irq(void *interrupt_params)
524 struct common_irq_params *irq_params = interrupt_params;
525 struct amdgpu_device *adev = irq_params->adev;
526 struct amdgpu_crtc *acrtc;
530 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
534 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
536 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
537 vrr_active, acrtc->dm_irq_params.active_planes);
540 * Core vblank handling at start of front-porch is only possible
541 * in non-vrr mode, as only there vblank timestamping will give
542 * valid results while done in front-porch. Otherwise defer it
543 * to dm_vupdate_high_irq after end of front-porch.
546 dm_crtc_handle_vblank(acrtc);
549 * Following stuff must happen at start of vblank, for crc
550 * computation and below-the-range btr support in vrr mode.
552 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
554 /* BTR updates need to happen before VUPDATE on Vega and above. */
555 if (adev->family < AMDGPU_FAMILY_AI)
558 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
560 if (acrtc->dm_irq_params.stream &&
561 acrtc->dm_irq_params.vrr_params.supported &&
562 acrtc->dm_irq_params.freesync_config.state ==
563 VRR_STATE_ACTIVE_VARIABLE) {
564 mod_freesync_handle_v_update(adev->dm.freesync_module,
565 acrtc->dm_irq_params.stream,
566 &acrtc->dm_irq_params.vrr_params);
568 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
569 &acrtc->dm_irq_params.vrr_params.adjust);
573 * If there aren't any active_planes then DCH HUBP may be clock-gated.
574 * In that case, pageflip completion interrupts won't fire and pageflip
575 * completion events won't get delivered. Prevent this by sending
576 * pending pageflip events from here if a flip is still pending.
578 * If any planes are enabled, use dm_pflip_high_irq() instead, to
579 * avoid race conditions between flip programming and completion,
580 * which could cause too early flip completion events.
582 if (adev->family >= AMDGPU_FAMILY_RV &&
583 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
584 acrtc->dm_irq_params.active_planes == 0) {
586 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
588 drm_crtc_vblank_put(&acrtc->base);
590 acrtc->pflip_status = AMDGPU_FLIP_NONE;
593 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
596 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
598 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
599 * DCN generation ASICs
600 * @interrupt_params: interrupt parameters
602 * Used to set crc window/read out crc value at vertical line 0 position
604 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
606 struct common_irq_params *irq_params = interrupt_params;
607 struct amdgpu_device *adev = irq_params->adev;
608 struct amdgpu_crtc *acrtc;
610 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
615 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
617 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
620 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
621 * @adev: amdgpu_device pointer
622 * @notify: dmub notification structure
624 * Dmub AUX or SET_CONFIG command completion processing callback
625 * Copies dmub notification to DM which is to be read by AUX command.
626 * issuing thread and also signals the event to wake up the thread.
628 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
629 struct dmub_notification *notify)
631 if (adev->dm.dmub_notify)
632 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
633 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
634 complete(&adev->dm.dmub_aux_transfer_done);
638 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
639 * @adev: amdgpu_device pointer
640 * @notify: dmub notification structure
642 * Dmub Hpd interrupt processing callback. Gets displayindex through the
643 * ink index and calls helper to do the processing.
645 static void dmub_hpd_callback(struct amdgpu_device *adev,
646 struct dmub_notification *notify)
648 struct amdgpu_dm_connector *aconnector;
649 struct amdgpu_dm_connector *hpd_aconnector = NULL;
650 struct drm_connector *connector;
651 struct drm_connector_list_iter iter;
652 struct dc_link *link;
654 struct drm_device *dev;
659 if (notify == NULL) {
660 DRM_ERROR("DMUB HPD callback notification was NULL");
664 if (notify->link_index > adev->dm.dc->link_count) {
665 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
669 link_index = notify->link_index;
670 link = adev->dm.dc->links[link_index];
673 drm_connector_list_iter_begin(dev, &iter);
674 drm_for_each_connector_iter(connector, &iter) {
675 aconnector = to_amdgpu_dm_connector(connector);
676 if (link && aconnector->dc_link == link) {
677 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
678 hpd_aconnector = aconnector;
682 drm_connector_list_iter_end(&iter);
684 if (hpd_aconnector) {
685 if (notify->type == DMUB_NOTIFICATION_HPD)
686 handle_hpd_irq_helper(hpd_aconnector);
687 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
688 handle_hpd_rx_irq(hpd_aconnector);
693 * register_dmub_notify_callback - Sets callback for DMUB notify
694 * @adev: amdgpu_device pointer
695 * @type: Type of dmub notification
696 * @callback: Dmub interrupt callback function
697 * @dmub_int_thread_offload: offload indicator
699 * API to register a dmub callback handler for a dmub notification
700 * Also sets indicator whether callback processing to be offloaded.
701 * to dmub interrupt handling thread
702 * Return: true if successfully registered, false if there is existing registration
704 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
705 enum dmub_notification_type type,
706 dmub_notify_interrupt_callback_t callback,
707 bool dmub_int_thread_offload)
709 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
710 adev->dm.dmub_callback[type] = callback;
711 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
718 static void dm_handle_hpd_work(struct work_struct *work)
720 struct dmub_hpd_work *dmub_hpd_wrk;
722 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
724 if (!dmub_hpd_wrk->dmub_notify) {
725 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
729 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
730 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
731 dmub_hpd_wrk->dmub_notify);
734 kfree(dmub_hpd_wrk->dmub_notify);
739 #define DMUB_TRACE_MAX_READ 64
741 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
742 * @interrupt_params: used for determining the Outbox instance
744 * Handles the Outbox Interrupt
747 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
749 struct dmub_notification notify;
750 struct common_irq_params *irq_params = interrupt_params;
751 struct amdgpu_device *adev = irq_params->adev;
752 struct amdgpu_display_manager *dm = &adev->dm;
753 struct dmcub_trace_buf_entry entry = { 0 };
755 struct dmub_hpd_work *dmub_hpd_wrk;
756 struct dc_link *plink = NULL;
758 if (dc_enable_dmub_notifications(adev->dm.dc) &&
759 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
762 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
763 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
764 DRM_ERROR("DM: notify type %d invalid!", notify.type);
767 if (!dm->dmub_callback[notify.type]) {
768 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
771 if (dm->dmub_thread_offload[notify.type] == true) {
772 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
774 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
777 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
778 if (!dmub_hpd_wrk->dmub_notify) {
780 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
783 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
784 if (dmub_hpd_wrk->dmub_notify)
785 memcpy(dmub_hpd_wrk->dmub_notify, ¬ify, sizeof(struct dmub_notification));
786 dmub_hpd_wrk->adev = adev;
787 if (notify.type == DMUB_NOTIFICATION_HPD) {
788 plink = adev->dm.dc->links[notify.link_index];
791 notify.hpd_status == DP_HPD_PLUG;
794 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
796 dm->dmub_callback[notify.type](adev, ¬ify);
798 } while (notify.pending_notification);
803 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
804 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
805 entry.param0, entry.param1);
807 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
808 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
814 } while (count <= DMUB_TRACE_MAX_READ);
816 if (count > DMUB_TRACE_MAX_READ)
817 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
820 static int dm_set_clockgating_state(void *handle,
821 enum amd_clockgating_state state)
826 static int dm_set_powergating_state(void *handle,
827 enum amd_powergating_state state)
832 /* Prototypes of private functions */
833 static int dm_early_init(void* handle);
835 /* Allocate memory for FBC compressed data */
836 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
838 struct drm_device *dev = connector->dev;
839 struct amdgpu_device *adev = drm_to_adev(dev);
840 struct dm_compressor_info *compressor = &adev->dm.compressor;
841 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
842 struct drm_display_mode *mode;
843 unsigned long max_size = 0;
845 if (adev->dm.dc->fbc_compressor == NULL)
848 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
851 if (compressor->bo_ptr)
855 list_for_each_entry(mode, &connector->modes, head) {
856 if (max_size < mode->htotal * mode->vtotal)
857 max_size = mode->htotal * mode->vtotal;
861 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
862 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
863 &compressor->gpu_addr, &compressor->cpu_addr);
866 DRM_ERROR("DM: Failed to initialize FBC\n");
868 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
869 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
876 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
877 int pipe, bool *enabled,
878 unsigned char *buf, int max_bytes)
880 struct drm_device *dev = dev_get_drvdata(kdev);
881 struct amdgpu_device *adev = drm_to_adev(dev);
882 struct drm_connector *connector;
883 struct drm_connector_list_iter conn_iter;
884 struct amdgpu_dm_connector *aconnector;
889 mutex_lock(&adev->dm.audio_lock);
891 drm_connector_list_iter_begin(dev, &conn_iter);
892 drm_for_each_connector_iter(connector, &conn_iter) {
893 aconnector = to_amdgpu_dm_connector(connector);
894 if (aconnector->audio_inst != port)
898 ret = drm_eld_size(connector->eld);
899 memcpy(buf, connector->eld, min(max_bytes, ret));
903 drm_connector_list_iter_end(&conn_iter);
905 mutex_unlock(&adev->dm.audio_lock);
907 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
912 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
913 .get_eld = amdgpu_dm_audio_component_get_eld,
916 static int amdgpu_dm_audio_component_bind(struct device *kdev,
917 struct device *hda_kdev, void *data)
919 struct drm_device *dev = dev_get_drvdata(kdev);
920 struct amdgpu_device *adev = drm_to_adev(dev);
921 struct drm_audio_component *acomp = data;
923 acomp->ops = &amdgpu_dm_audio_component_ops;
925 adev->dm.audio_component = acomp;
930 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
931 struct device *hda_kdev, void *data)
933 struct drm_device *dev = dev_get_drvdata(kdev);
934 struct amdgpu_device *adev = drm_to_adev(dev);
935 struct drm_audio_component *acomp = data;
939 adev->dm.audio_component = NULL;
942 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
943 .bind = amdgpu_dm_audio_component_bind,
944 .unbind = amdgpu_dm_audio_component_unbind,
947 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
954 adev->mode_info.audio.enabled = true;
956 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
958 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
959 adev->mode_info.audio.pin[i].channels = -1;
960 adev->mode_info.audio.pin[i].rate = -1;
961 adev->mode_info.audio.pin[i].bits_per_sample = -1;
962 adev->mode_info.audio.pin[i].status_bits = 0;
963 adev->mode_info.audio.pin[i].category_code = 0;
964 adev->mode_info.audio.pin[i].connected = false;
965 adev->mode_info.audio.pin[i].id =
966 adev->dm.dc->res_pool->audios[i]->inst;
967 adev->mode_info.audio.pin[i].offset = 0;
970 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
974 adev->dm.audio_registered = true;
979 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
984 if (!adev->mode_info.audio.enabled)
987 if (adev->dm.audio_registered) {
988 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
989 adev->dm.audio_registered = false;
992 /* TODO: Disable audio? */
994 adev->mode_info.audio.enabled = false;
997 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
999 struct drm_audio_component *acomp = adev->dm.audio_component;
1001 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1002 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1004 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1009 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1011 const struct dmcub_firmware_header_v1_0 *hdr;
1012 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1013 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1014 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1015 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1016 struct abm *abm = adev->dm.dc->res_pool->abm;
1017 struct dmub_srv_hw_params hw_params;
1018 enum dmub_status status;
1019 const unsigned char *fw_inst_const, *fw_bss_data;
1020 u32 i, fw_inst_const_size, fw_bss_data_size;
1021 bool has_hw_support;
1024 /* DMUB isn't supported on the ASIC. */
1028 DRM_ERROR("No framebuffer info for DMUB service.\n");
1033 /* Firmware required for DMUB support. */
1034 DRM_ERROR("No firmware provided for DMUB.\n");
1038 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1039 if (status != DMUB_STATUS_OK) {
1040 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1044 if (!has_hw_support) {
1045 DRM_INFO("DMUB unsupported on ASIC\n");
1049 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1050 status = dmub_srv_hw_reset(dmub_srv);
1051 if (status != DMUB_STATUS_OK)
1052 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1054 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1056 fw_inst_const = dmub_fw->data +
1057 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1060 fw_bss_data = dmub_fw->data +
1061 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1062 le32_to_cpu(hdr->inst_const_bytes);
1064 /* Copy firmware and bios info into FB memory. */
1065 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1066 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1068 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1070 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1071 * amdgpu_ucode_init_single_fw will load dmub firmware
1072 * fw_inst_const part to cw0; otherwise, the firmware back door load
1073 * will be done by dm_dmub_hw_init
1075 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1076 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1077 fw_inst_const_size);
1080 if (fw_bss_data_size)
1081 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1082 fw_bss_data, fw_bss_data_size);
1084 /* Copy firmware bios info into FB memory. */
1085 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1088 /* Reset regions that need to be reset. */
1089 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1090 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1092 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1093 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1095 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1096 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1098 /* Initialize hardware. */
1099 memset(&hw_params, 0, sizeof(hw_params));
1100 hw_params.fb_base = adev->gmc.fb_start;
1101 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1103 /* backdoor load firmware and trigger dmub running */
1104 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1105 hw_params.load_inst_const = true;
1108 hw_params.psp_version = dmcu->psp_version;
1110 for (i = 0; i < fb_info->num_fb; ++i)
1111 hw_params.fb[i] = &fb_info->fb[i];
1113 switch (adev->ip_versions[DCE_HWIP][0]) {
1114 case IP_VERSION(3, 1, 3):
1115 case IP_VERSION(3, 1, 4):
1116 hw_params.dpia_supported = true;
1117 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1123 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1124 if (status != DMUB_STATUS_OK) {
1125 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1129 /* Wait for firmware load to finish. */
1130 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1131 if (status != DMUB_STATUS_OK)
1132 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1134 /* Init DMCU and ABM if available. */
1136 dmcu->funcs->dmcu_init(dmcu);
1137 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1140 if (!adev->dm.dc->ctx->dmub_srv)
1141 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1142 if (!adev->dm.dc->ctx->dmub_srv) {
1143 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1147 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1148 adev->dm.dmcub_fw_version);
1153 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1155 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1156 enum dmub_status status;
1160 /* DMUB isn't supported on the ASIC. */
1164 status = dmub_srv_is_hw_init(dmub_srv, &init);
1165 if (status != DMUB_STATUS_OK)
1166 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1168 if (status == DMUB_STATUS_OK && init) {
1169 /* Wait for firmware load to finish. */
1170 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1171 if (status != DMUB_STATUS_OK)
1172 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1174 /* Perform the full hardware initialization. */
1175 dm_dmub_hw_init(adev);
1179 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1182 u32 logical_addr_low;
1183 u32 logical_addr_high;
1184 u32 agp_base, agp_bot, agp_top;
1185 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1187 memset(pa_config, 0, sizeof(*pa_config));
1189 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1190 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1192 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1194 * Raven2 has a HW issue that it is unable to use the vram which
1195 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1196 * workaround that increase system aperture high address (add 1)
1197 * to get rid of the VM fault and hardware hang.
1199 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1201 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1204 agp_bot = adev->gmc.agp_start >> 24;
1205 agp_top = adev->gmc.agp_end >> 24;
1208 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1209 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1210 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1211 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1212 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1213 page_table_base.low_part = lower_32_bits(pt_base);
1215 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1216 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1218 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1219 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1220 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1222 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1223 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1224 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1226 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1227 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1228 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1230 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1234 static void force_connector_state(
1235 struct amdgpu_dm_connector *aconnector,
1236 enum drm_connector_force force_state)
1238 struct drm_connector *connector = &aconnector->base;
1240 mutex_lock(&connector->dev->mode_config.mutex);
1241 aconnector->base.force = force_state;
1242 mutex_unlock(&connector->dev->mode_config.mutex);
1244 mutex_lock(&aconnector->hpd_lock);
1245 drm_kms_helper_connector_hotplug_event(connector);
1246 mutex_unlock(&aconnector->hpd_lock);
1249 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1251 struct hpd_rx_irq_offload_work *offload_work;
1252 struct amdgpu_dm_connector *aconnector;
1253 struct dc_link *dc_link;
1254 struct amdgpu_device *adev;
1255 enum dc_connection_type new_connection_type = dc_connection_none;
1256 unsigned long flags;
1257 union test_response test_response;
1259 memset(&test_response, 0, sizeof(test_response));
1261 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1262 aconnector = offload_work->offload_wq->aconnector;
1265 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1269 adev = drm_to_adev(aconnector->base.dev);
1270 dc_link = aconnector->dc_link;
1272 mutex_lock(&aconnector->hpd_lock);
1273 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1274 DRM_ERROR("KMS: Failed to detect connector\n");
1275 mutex_unlock(&aconnector->hpd_lock);
1277 if (new_connection_type == dc_connection_none)
1280 if (amdgpu_in_reset(adev))
1283 mutex_lock(&adev->dm.dc_lock);
1284 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1285 dc_link_dp_handle_automated_test(dc_link);
1287 if (aconnector->timing_changed) {
1288 /* force connector disconnect and reconnect */
1289 force_connector_state(aconnector, DRM_FORCE_OFF);
1291 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1294 test_response.bits.ACK = 1;
1296 core_link_write_dpcd(
1300 sizeof(test_response));
1302 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1303 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1304 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1305 dc_link_dp_handle_link_loss(dc_link);
1306 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1307 offload_work->offload_wq->is_handling_link_loss = false;
1308 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1310 mutex_unlock(&adev->dm.dc_lock);
1313 kfree(offload_work);
1317 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1319 int max_caps = dc->caps.max_links;
1321 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1323 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1325 if (!hpd_rx_offload_wq)
1329 for (i = 0; i < max_caps; i++) {
1330 hpd_rx_offload_wq[i].wq =
1331 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1333 if (hpd_rx_offload_wq[i].wq == NULL) {
1334 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1338 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1341 return hpd_rx_offload_wq;
1344 for (i = 0; i < max_caps; i++) {
1345 if (hpd_rx_offload_wq[i].wq)
1346 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1348 kfree(hpd_rx_offload_wq);
1352 struct amdgpu_stutter_quirk {
1360 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1361 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1362 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1366 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1368 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1370 while (p && p->chip_device != 0) {
1371 if (pdev->vendor == p->chip_vendor &&
1372 pdev->device == p->chip_device &&
1373 pdev->subsystem_vendor == p->subsys_vendor &&
1374 pdev->subsystem_device == p->subsys_device &&
1375 pdev->revision == p->revision) {
1383 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1386 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1387 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1392 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1393 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1398 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1399 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1404 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1405 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1410 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1411 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1416 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1417 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1422 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1423 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1428 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1429 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1434 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1435 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1439 /* TODO: refactor this from a fixed table to a dynamic option */
1442 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1444 const struct dmi_system_id *dmi_id;
1446 dm->aux_hpd_discon_quirk = false;
1448 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1450 dm->aux_hpd_discon_quirk = true;
1451 DRM_INFO("aux_hpd_discon_quirk attached\n");
1455 static int amdgpu_dm_init(struct amdgpu_device *adev)
1457 struct dc_init_data init_data;
1458 #ifdef CONFIG_DRM_AMD_DC_HDCP
1459 struct dc_callback_init init_params;
1463 adev->dm.ddev = adev_to_drm(adev);
1464 adev->dm.adev = adev;
1466 /* Zero all the fields */
1467 memset(&init_data, 0, sizeof(init_data));
1468 #ifdef CONFIG_DRM_AMD_DC_HDCP
1469 memset(&init_params, 0, sizeof(init_params));
1472 mutex_init(&adev->dm.dpia_aux_lock);
1473 mutex_init(&adev->dm.dc_lock);
1474 mutex_init(&adev->dm.audio_lock);
1476 if(amdgpu_dm_irq_init(adev)) {
1477 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1481 init_data.asic_id.chip_family = adev->family;
1483 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1484 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1485 init_data.asic_id.chip_id = adev->pdev->device;
1487 init_data.asic_id.vram_width = adev->gmc.vram_width;
1488 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1489 init_data.asic_id.atombios_base_address =
1490 adev->mode_info.atom_context->bios;
1492 init_data.driver = adev;
1494 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1496 if (!adev->dm.cgs_device) {
1497 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1501 init_data.cgs_device = adev->dm.cgs_device;
1503 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1505 switch (adev->ip_versions[DCE_HWIP][0]) {
1506 case IP_VERSION(2, 1, 0):
1507 switch (adev->dm.dmcub_fw_version) {
1508 case 0: /* development */
1509 case 0x1: /* linux-firmware.git hash 6d9f399 */
1510 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1511 init_data.flags.disable_dmcu = false;
1514 init_data.flags.disable_dmcu = true;
1517 case IP_VERSION(2, 0, 3):
1518 init_data.flags.disable_dmcu = true;
1524 switch (adev->asic_type) {
1527 init_data.flags.gpu_vm_support = true;
1530 switch (adev->ip_versions[DCE_HWIP][0]) {
1531 case IP_VERSION(1, 0, 0):
1532 case IP_VERSION(1, 0, 1):
1533 /* enable S/G on PCO and RV2 */
1534 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1535 (adev->apu_flags & AMD_APU_IS_PICASSO))
1536 init_data.flags.gpu_vm_support = true;
1538 case IP_VERSION(2, 1, 0):
1539 case IP_VERSION(3, 0, 1):
1540 case IP_VERSION(3, 1, 2):
1541 case IP_VERSION(3, 1, 3):
1542 case IP_VERSION(3, 1, 6):
1543 init_data.flags.gpu_vm_support = true;
1551 if (init_data.flags.gpu_vm_support)
1552 adev->mode_info.gpu_vm_support = true;
1554 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1555 init_data.flags.fbc_support = true;
1557 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1558 init_data.flags.multi_mon_pp_mclk_switch = true;
1560 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1561 init_data.flags.disable_fractional_pwm = true;
1563 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1564 init_data.flags.edp_no_power_sequencing = true;
1566 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1567 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1568 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1569 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1571 init_data.flags.seamless_boot_edp_requested = false;
1573 if (check_seamless_boot_capability(adev)) {
1574 init_data.flags.seamless_boot_edp_requested = true;
1575 init_data.flags.allow_seamless_boot_optimization = true;
1576 DRM_INFO("Seamless boot condition check passed\n");
1579 init_data.flags.enable_mipi_converter_optimization = true;
1581 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1582 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1584 INIT_LIST_HEAD(&adev->dm.da_list);
1586 retrieve_dmi_info(&adev->dm);
1588 /* Display Core create. */
1589 adev->dm.dc = dc_create(&init_data);
1592 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1594 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1598 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1599 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1600 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1603 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1604 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1605 if (dm_should_disable_stutter(adev->pdev))
1606 adev->dm.dc->debug.disable_stutter = true;
1608 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1609 adev->dm.dc->debug.disable_stutter = true;
1611 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1612 adev->dm.dc->debug.disable_dsc = true;
1615 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1616 adev->dm.dc->debug.disable_clock_gate = true;
1618 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1619 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1621 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1623 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1624 adev->dm.dc->debug.ignore_cable_id = true;
1626 r = dm_dmub_hw_init(adev);
1628 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1632 dc_hardware_init(adev->dm.dc);
1634 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1635 if (!adev->dm.hpd_rx_offload_wq) {
1636 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1640 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1641 struct dc_phy_addr_space_config pa_config;
1643 mmhub_read_system_context(adev, &pa_config);
1645 // Call the DC init_memory func
1646 dc_setup_system_context(adev->dm.dc, &pa_config);
1649 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1650 if (!adev->dm.freesync_module) {
1652 "amdgpu: failed to initialize freesync_module.\n");
1654 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1655 adev->dm.freesync_module);
1657 amdgpu_dm_init_color_mod();
1659 if (adev->dm.dc->caps.max_links > 0) {
1660 adev->dm.vblank_control_workqueue =
1661 create_singlethread_workqueue("dm_vblank_control_workqueue");
1662 if (!adev->dm.vblank_control_workqueue)
1663 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1666 #ifdef CONFIG_DRM_AMD_DC_HDCP
1667 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1668 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1670 if (!adev->dm.hdcp_workqueue)
1671 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1673 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1675 dc_init_callbacks(adev->dm.dc, &init_params);
1678 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1679 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1680 if (!adev->dm.secure_display_ctxs) {
1681 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1684 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1685 init_completion(&adev->dm.dmub_aux_transfer_done);
1686 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1687 if (!adev->dm.dmub_notify) {
1688 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1692 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1693 if (!adev->dm.delayed_hpd_wq) {
1694 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1698 amdgpu_dm_outbox_init(adev);
1699 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1700 dmub_aux_setconfig_callback, false)) {
1701 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1704 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1705 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1708 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1709 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1714 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1715 * It is expected that DMUB will resend any pending notifications at this point, for
1716 * example HPD from DPIA.
1718 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1719 dc_enable_dmub_outbox(adev->dm.dc);
1721 if (amdgpu_dm_initialize_drm_device(adev)) {
1723 "amdgpu: failed to initialize sw for display support.\n");
1727 /* create fake encoders for MST */
1728 dm_dp_create_fake_mst_encoders(adev);
1730 /* TODO: Add_display_info? */
1732 /* TODO use dynamic cursor width */
1733 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1734 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1736 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1738 "amdgpu: failed to initialize sw for display support.\n");
1743 DRM_DEBUG_DRIVER("KMS initialized.\n");
1747 amdgpu_dm_fini(adev);
1752 static int amdgpu_dm_early_fini(void *handle)
1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1756 amdgpu_dm_audio_fini(adev);
1761 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1765 if (adev->dm.vblank_control_workqueue) {
1766 destroy_workqueue(adev->dm.vblank_control_workqueue);
1767 adev->dm.vblank_control_workqueue = NULL;
1770 amdgpu_dm_destroy_drm_device(&adev->dm);
1772 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1773 if (adev->dm.secure_display_ctxs) {
1774 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1775 if (adev->dm.secure_display_ctxs[i].crtc) {
1776 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1777 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1780 kfree(adev->dm.secure_display_ctxs);
1781 adev->dm.secure_display_ctxs = NULL;
1784 #ifdef CONFIG_DRM_AMD_DC_HDCP
1785 if (adev->dm.hdcp_workqueue) {
1786 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1787 adev->dm.hdcp_workqueue = NULL;
1791 dc_deinit_callbacks(adev->dm.dc);
1794 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1796 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1797 kfree(adev->dm.dmub_notify);
1798 adev->dm.dmub_notify = NULL;
1799 destroy_workqueue(adev->dm.delayed_hpd_wq);
1800 adev->dm.delayed_hpd_wq = NULL;
1803 if (adev->dm.dmub_bo)
1804 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1805 &adev->dm.dmub_bo_gpu_addr,
1806 &adev->dm.dmub_bo_cpu_addr);
1808 if (adev->dm.hpd_rx_offload_wq) {
1809 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1810 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1811 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1812 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1816 kfree(adev->dm.hpd_rx_offload_wq);
1817 adev->dm.hpd_rx_offload_wq = NULL;
1820 /* DC Destroy TODO: Replace destroy DAL */
1822 dc_destroy(&adev->dm.dc);
1824 * TODO: pageflip, vlank interrupt
1826 * amdgpu_dm_irq_fini(adev);
1829 if (adev->dm.cgs_device) {
1830 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1831 adev->dm.cgs_device = NULL;
1833 if (adev->dm.freesync_module) {
1834 mod_freesync_destroy(adev->dm.freesync_module);
1835 adev->dm.freesync_module = NULL;
1838 mutex_destroy(&adev->dm.audio_lock);
1839 mutex_destroy(&adev->dm.dc_lock);
1840 mutex_destroy(&adev->dm.dpia_aux_lock);
1845 static int load_dmcu_fw(struct amdgpu_device *adev)
1847 const char *fw_name_dmcu = NULL;
1849 const struct dmcu_firmware_header_v1_0 *hdr;
1851 switch(adev->asic_type) {
1852 #if defined(CONFIG_DRM_AMD_DC_SI)
1867 case CHIP_POLARIS11:
1868 case CHIP_POLARIS10:
1869 case CHIP_POLARIS12:
1876 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1879 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1880 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1881 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1882 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1887 switch (adev->ip_versions[DCE_HWIP][0]) {
1888 case IP_VERSION(2, 0, 2):
1889 case IP_VERSION(2, 0, 3):
1890 case IP_VERSION(2, 0, 0):
1891 case IP_VERSION(2, 1, 0):
1892 case IP_VERSION(3, 0, 0):
1893 case IP_VERSION(3, 0, 2):
1894 case IP_VERSION(3, 0, 3):
1895 case IP_VERSION(3, 0, 1):
1896 case IP_VERSION(3, 1, 2):
1897 case IP_VERSION(3, 1, 3):
1898 case IP_VERSION(3, 1, 4):
1899 case IP_VERSION(3, 1, 5):
1900 case IP_VERSION(3, 1, 6):
1901 case IP_VERSION(3, 2, 0):
1902 case IP_VERSION(3, 2, 1):
1907 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1911 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1912 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1916 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
1918 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1919 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1920 adev->dm.fw_dmcu = NULL;
1924 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1926 amdgpu_ucode_release(&adev->dm.fw_dmcu);
1930 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1931 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1932 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1933 adev->firmware.fw_size +=
1934 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1936 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1937 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1938 adev->firmware.fw_size +=
1939 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1941 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1943 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1948 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1950 struct amdgpu_device *adev = ctx;
1952 return dm_read_reg(adev->dm.dc->ctx, address);
1955 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1958 struct amdgpu_device *adev = ctx;
1960 return dm_write_reg(adev->dm.dc->ctx, address, value);
1963 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1965 struct dmub_srv_create_params create_params;
1966 struct dmub_srv_region_params region_params;
1967 struct dmub_srv_region_info region_info;
1968 struct dmub_srv_fb_params fb_params;
1969 struct dmub_srv_fb_info *fb_info;
1970 struct dmub_srv *dmub_srv;
1971 const struct dmcub_firmware_header_v1_0 *hdr;
1972 enum dmub_asic dmub_asic;
1973 enum dmub_status status;
1976 switch (adev->ip_versions[DCE_HWIP][0]) {
1977 case IP_VERSION(2, 1, 0):
1978 dmub_asic = DMUB_ASIC_DCN21;
1980 case IP_VERSION(3, 0, 0):
1981 dmub_asic = DMUB_ASIC_DCN30;
1983 case IP_VERSION(3, 0, 1):
1984 dmub_asic = DMUB_ASIC_DCN301;
1986 case IP_VERSION(3, 0, 2):
1987 dmub_asic = DMUB_ASIC_DCN302;
1989 case IP_VERSION(3, 0, 3):
1990 dmub_asic = DMUB_ASIC_DCN303;
1992 case IP_VERSION(3, 1, 2):
1993 case IP_VERSION(3, 1, 3):
1994 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1996 case IP_VERSION(3, 1, 4):
1997 dmub_asic = DMUB_ASIC_DCN314;
1999 case IP_VERSION(3, 1, 5):
2000 dmub_asic = DMUB_ASIC_DCN315;
2002 case IP_VERSION(3, 1, 6):
2003 dmub_asic = DMUB_ASIC_DCN316;
2005 case IP_VERSION(3, 2, 0):
2006 dmub_asic = DMUB_ASIC_DCN32;
2008 case IP_VERSION(3, 2, 1):
2009 dmub_asic = DMUB_ASIC_DCN321;
2012 /* ASIC doesn't support DMUB. */
2016 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2017 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2019 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2020 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2021 AMDGPU_UCODE_ID_DMCUB;
2022 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2024 adev->firmware.fw_size +=
2025 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2027 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2028 adev->dm.dmcub_fw_version);
2032 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2033 dmub_srv = adev->dm.dmub_srv;
2036 DRM_ERROR("Failed to allocate DMUB service!\n");
2040 memset(&create_params, 0, sizeof(create_params));
2041 create_params.user_ctx = adev;
2042 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2043 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2044 create_params.asic = dmub_asic;
2046 /* Create the DMUB service. */
2047 status = dmub_srv_create(dmub_srv, &create_params);
2048 if (status != DMUB_STATUS_OK) {
2049 DRM_ERROR("Error creating DMUB service: %d\n", status);
2053 /* Calculate the size of all the regions for the DMUB service. */
2054 memset(®ion_params, 0, sizeof(region_params));
2056 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2057 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2058 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2059 region_params.vbios_size = adev->bios_size;
2060 region_params.fw_bss_data = region_params.bss_data_size ?
2061 adev->dm.dmub_fw->data +
2062 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2063 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2064 region_params.fw_inst_const =
2065 adev->dm.dmub_fw->data +
2066 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2069 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2072 if (status != DMUB_STATUS_OK) {
2073 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2078 * Allocate a framebuffer based on the total size of all the regions.
2079 * TODO: Move this into GART.
2081 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2082 AMDGPU_GEM_DOMAIN_VRAM |
2083 AMDGPU_GEM_DOMAIN_GTT,
2085 &adev->dm.dmub_bo_gpu_addr,
2086 &adev->dm.dmub_bo_cpu_addr);
2090 /* Rebase the regions on the framebuffer address. */
2091 memset(&fb_params, 0, sizeof(fb_params));
2092 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2093 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2094 fb_params.region_info = ®ion_info;
2096 adev->dm.dmub_fb_info =
2097 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2098 fb_info = adev->dm.dmub_fb_info;
2102 "Failed to allocate framebuffer info for DMUB service!\n");
2106 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2107 if (status != DMUB_STATUS_OK) {
2108 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2115 static int dm_sw_init(void *handle)
2117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2120 r = dm_dmub_sw_init(adev);
2124 return load_dmcu_fw(adev);
2127 static int dm_sw_fini(void *handle)
2129 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2131 kfree(adev->dm.dmub_fb_info);
2132 adev->dm.dmub_fb_info = NULL;
2134 if (adev->dm.dmub_srv) {
2135 dmub_srv_destroy(adev->dm.dmub_srv);
2136 adev->dm.dmub_srv = NULL;
2139 amdgpu_ucode_release(&adev->dm.dmub_fw);
2140 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2145 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2147 struct amdgpu_dm_connector *aconnector;
2148 struct drm_connector *connector;
2149 struct drm_connector_list_iter iter;
2152 drm_connector_list_iter_begin(dev, &iter);
2153 drm_for_each_connector_iter(connector, &iter) {
2154 aconnector = to_amdgpu_dm_connector(connector);
2155 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2156 aconnector->mst_mgr.aux) {
2157 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2159 aconnector->base.base.id);
2161 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2163 DRM_ERROR("DM_MST: Failed to start MST\n");
2164 aconnector->dc_link->type =
2165 dc_connection_single;
2166 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2167 aconnector->dc_link);
2172 drm_connector_list_iter_end(&iter);
2177 static int dm_late_init(void *handle)
2179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2181 struct dmcu_iram_parameters params;
2182 unsigned int linear_lut[16];
2184 struct dmcu *dmcu = NULL;
2186 dmcu = adev->dm.dc->res_pool->dmcu;
2188 for (i = 0; i < 16; i++)
2189 linear_lut[i] = 0xFFFF * i / 15;
2192 params.backlight_ramping_override = false;
2193 params.backlight_ramping_start = 0xCCCC;
2194 params.backlight_ramping_reduction = 0xCCCCCCCC;
2195 params.backlight_lut_array_size = 16;
2196 params.backlight_lut_array = linear_lut;
2198 /* Min backlight level after ABM reduction, Don't allow below 1%
2199 * 0xFFFF x 0.01 = 0x28F
2201 params.min_abm_backlight = 0x28F;
2202 /* In the case where abm is implemented on dmcub,
2203 * dmcu object will be null.
2204 * ABM 2.4 and up are implemented on dmcub.
2207 if (!dmcu_load_iram(dmcu, params))
2209 } else if (adev->dm.dc->ctx->dmub_srv) {
2210 struct dc_link *edp_links[MAX_NUM_EDP];
2213 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2214 for (i = 0; i < edp_num; i++) {
2215 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2220 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2223 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2225 struct amdgpu_dm_connector *aconnector;
2226 struct drm_connector *connector;
2227 struct drm_connector_list_iter iter;
2228 struct drm_dp_mst_topology_mgr *mgr;
2230 bool need_hotplug = false;
2232 drm_connector_list_iter_begin(dev, &iter);
2233 drm_for_each_connector_iter(connector, &iter) {
2234 aconnector = to_amdgpu_dm_connector(connector);
2235 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2236 aconnector->mst_root)
2239 mgr = &aconnector->mst_mgr;
2242 drm_dp_mst_topology_mgr_suspend(mgr);
2244 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2246 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2247 aconnector->dc_link);
2248 need_hotplug = true;
2252 drm_connector_list_iter_end(&iter);
2255 drm_kms_helper_hotplug_event(dev);
2258 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2262 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2263 * on window driver dc implementation.
2264 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2265 * should be passed to smu during boot up and resume from s3.
2266 * boot up: dc calculate dcn watermark clock settings within dc_create,
2267 * dcn20_resource_construct
2268 * then call pplib functions below to pass the settings to smu:
2269 * smu_set_watermarks_for_clock_ranges
2270 * smu_set_watermarks_table
2271 * navi10_set_watermarks_table
2272 * smu_write_watermarks_table
2274 * For Renoir, clock settings of dcn watermark are also fixed values.
2275 * dc has implemented different flow for window driver:
2276 * dc_hardware_init / dc_set_power_state
2281 * smu_set_watermarks_for_clock_ranges
2282 * renoir_set_watermarks_table
2283 * smu_write_watermarks_table
2286 * dc_hardware_init -> amdgpu_dm_init
2287 * dc_set_power_state --> dm_resume
2289 * therefore, this function apply to navi10/12/14 but not Renoir
2292 switch (adev->ip_versions[DCE_HWIP][0]) {
2293 case IP_VERSION(2, 0, 2):
2294 case IP_VERSION(2, 0, 0):
2300 ret = amdgpu_dpm_write_watermarks_table(adev);
2302 DRM_ERROR("Failed to update WMTABLE!\n");
2310 * dm_hw_init() - Initialize DC device
2311 * @handle: The base driver device containing the amdgpu_dm device.
2313 * Initialize the &struct amdgpu_display_manager device. This involves calling
2314 * the initializers of each DM component, then populating the struct with them.
2316 * Although the function implies hardware initialization, both hardware and
2317 * software are initialized here. Splitting them out to their relevant init
2318 * hooks is a future TODO item.
2320 * Some notable things that are initialized here:
2322 * - Display Core, both software and hardware
2323 * - DC modules that we need (freesync and color management)
2324 * - DRM software states
2325 * - Interrupt sources and handlers
2327 * - Debug FS entries, if enabled
2329 static int dm_hw_init(void *handle)
2331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2332 /* Create DAL display manager */
2333 amdgpu_dm_init(adev);
2334 amdgpu_dm_hpd_init(adev);
2340 * dm_hw_fini() - Teardown DC device
2341 * @handle: The base driver device containing the amdgpu_dm device.
2343 * Teardown components within &struct amdgpu_display_manager that require
2344 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2345 * were loaded. Also flush IRQ workqueues and disable them.
2347 static int dm_hw_fini(void *handle)
2349 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2351 amdgpu_dm_hpd_fini(adev);
2353 amdgpu_dm_irq_fini(adev);
2354 amdgpu_dm_fini(adev);
2359 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2360 struct dc_state *state, bool enable)
2362 enum dc_irq_source irq_source;
2363 struct amdgpu_crtc *acrtc;
2367 for (i = 0; i < state->stream_count; i++) {
2368 acrtc = get_crtc_by_otg_inst(
2369 adev, state->stream_status[i].primary_otg_inst);
2371 if (acrtc && state->stream_status[i].plane_count != 0) {
2372 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2373 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2374 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2375 acrtc->crtc_id, enable ? "en" : "dis", rc);
2377 DRM_WARN("Failed to %s pflip interrupts\n",
2378 enable ? "enable" : "disable");
2381 rc = dm_enable_vblank(&acrtc->base);
2383 DRM_WARN("Failed to enable vblank interrupts\n");
2385 dm_disable_vblank(&acrtc->base);
2393 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2395 struct dc_state *context = NULL;
2396 enum dc_status res = DC_ERROR_UNEXPECTED;
2398 struct dc_stream_state *del_streams[MAX_PIPES];
2399 int del_streams_count = 0;
2401 memset(del_streams, 0, sizeof(del_streams));
2403 context = dc_create_state(dc);
2404 if (context == NULL)
2405 goto context_alloc_fail;
2407 dc_resource_state_copy_construct_current(dc, context);
2409 /* First remove from context all streams */
2410 for (i = 0; i < context->stream_count; i++) {
2411 struct dc_stream_state *stream = context->streams[i];
2413 del_streams[del_streams_count++] = stream;
2416 /* Remove all planes for removed streams and then remove the streams */
2417 for (i = 0; i < del_streams_count; i++) {
2418 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2419 res = DC_FAIL_DETACH_SURFACES;
2423 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2428 res = dc_commit_state(dc, context);
2431 dc_release_state(context);
2437 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2441 if (dm->hpd_rx_offload_wq) {
2442 for (i = 0; i < dm->dc->caps.max_links; i++)
2443 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2447 static int dm_suspend(void *handle)
2449 struct amdgpu_device *adev = handle;
2450 struct amdgpu_display_manager *dm = &adev->dm;
2453 if (amdgpu_in_reset(adev)) {
2454 mutex_lock(&dm->dc_lock);
2456 dc_allow_idle_optimizations(adev->dm.dc, false);
2458 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2460 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2462 amdgpu_dm_commit_zero_streams(dm->dc);
2464 amdgpu_dm_irq_suspend(adev);
2466 hpd_rx_irq_work_suspend(dm);
2471 WARN_ON(adev->dm.cached_state);
2472 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2474 s3_handle_mst(adev_to_drm(adev), true);
2476 amdgpu_dm_irq_suspend(adev);
2478 hpd_rx_irq_work_suspend(dm);
2480 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2485 struct amdgpu_dm_connector *
2486 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2487 struct drm_crtc *crtc)
2490 struct drm_connector_state *new_con_state;
2491 struct drm_connector *connector;
2492 struct drm_crtc *crtc_from_state;
2494 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2495 crtc_from_state = new_con_state->crtc;
2497 if (crtc_from_state == crtc)
2498 return to_amdgpu_dm_connector(connector);
2504 static void emulated_link_detect(struct dc_link *link)
2506 struct dc_sink_init_data sink_init_data = { 0 };
2507 struct display_sink_capability sink_caps = { 0 };
2508 enum dc_edid_status edid_status;
2509 struct dc_context *dc_ctx = link->ctx;
2510 struct dc_sink *sink = NULL;
2511 struct dc_sink *prev_sink = NULL;
2513 link->type = dc_connection_none;
2514 prev_sink = link->local_sink;
2517 dc_sink_release(prev_sink);
2519 switch (link->connector_signal) {
2520 case SIGNAL_TYPE_HDMI_TYPE_A: {
2521 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2522 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2526 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2527 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2528 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2532 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2533 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2534 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2538 case SIGNAL_TYPE_LVDS: {
2539 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2540 sink_caps.signal = SIGNAL_TYPE_LVDS;
2544 case SIGNAL_TYPE_EDP: {
2545 sink_caps.transaction_type =
2546 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2547 sink_caps.signal = SIGNAL_TYPE_EDP;
2551 case SIGNAL_TYPE_DISPLAY_PORT: {
2552 sink_caps.transaction_type =
2553 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2554 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2559 DC_ERROR("Invalid connector type! signal:%d\n",
2560 link->connector_signal);
2564 sink_init_data.link = link;
2565 sink_init_data.sink_signal = sink_caps.signal;
2567 sink = dc_sink_create(&sink_init_data);
2569 DC_ERROR("Failed to create sink!\n");
2573 /* dc_sink_create returns a new reference */
2574 link->local_sink = sink;
2576 edid_status = dm_helpers_read_local_edid(
2581 if (edid_status != EDID_OK)
2582 DC_ERROR("Failed to read EDID");
2586 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2587 struct amdgpu_display_manager *dm)
2590 struct dc_surface_update surface_updates[MAX_SURFACES];
2591 struct dc_plane_info plane_infos[MAX_SURFACES];
2592 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2593 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2594 struct dc_stream_update stream_update;
2598 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2601 dm_error("Failed to allocate update bundle\n");
2605 for (k = 0; k < dc_state->stream_count; k++) {
2606 bundle->stream_update.stream = dc_state->streams[k];
2608 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2609 bundle->surface_updates[m].surface =
2610 dc_state->stream_status->plane_states[m];
2611 bundle->surface_updates[m].surface->force_full_update =
2614 dc_commit_updates_for_stream(
2615 dm->dc, bundle->surface_updates,
2616 dc_state->stream_status->plane_count,
2617 dc_state->streams[k], &bundle->stream_update, dc_state);
2626 static int dm_resume(void *handle)
2628 struct amdgpu_device *adev = handle;
2629 struct drm_device *ddev = adev_to_drm(adev);
2630 struct amdgpu_display_manager *dm = &adev->dm;
2631 struct amdgpu_dm_connector *aconnector;
2632 struct drm_connector *connector;
2633 struct drm_connector_list_iter iter;
2634 struct drm_crtc *crtc;
2635 struct drm_crtc_state *new_crtc_state;
2636 struct dm_crtc_state *dm_new_crtc_state;
2637 struct drm_plane *plane;
2638 struct drm_plane_state *new_plane_state;
2639 struct dm_plane_state *dm_new_plane_state;
2640 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2641 enum dc_connection_type new_connection_type = dc_connection_none;
2642 struct dc_state *dc_state;
2645 if (amdgpu_in_reset(adev)) {
2646 dc_state = dm->cached_dc_state;
2649 * The dc->current_state is backed up into dm->cached_dc_state
2650 * before we commit 0 streams.
2652 * DC will clear link encoder assignments on the real state
2653 * but the changes won't propagate over to the copy we made
2654 * before the 0 streams commit.
2656 * DC expects that link encoder assignments are *not* valid
2657 * when committing a state, so as a workaround we can copy
2658 * off of the current state.
2660 * We lose the previous assignments, but we had already
2661 * commit 0 streams anyway.
2663 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2665 r = dm_dmub_hw_init(adev);
2667 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2669 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2672 amdgpu_dm_irq_resume_early(adev);
2674 for (i = 0; i < dc_state->stream_count; i++) {
2675 dc_state->streams[i]->mode_changed = true;
2676 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2677 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2682 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2683 amdgpu_dm_outbox_init(adev);
2684 dc_enable_dmub_outbox(adev->dm.dc);
2687 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2689 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2691 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2693 dc_release_state(dm->cached_dc_state);
2694 dm->cached_dc_state = NULL;
2696 amdgpu_dm_irq_resume_late(adev);
2698 mutex_unlock(&dm->dc_lock);
2702 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2703 dc_release_state(dm_state->context);
2704 dm_state->context = dc_create_state(dm->dc);
2705 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2706 dc_resource_state_construct(dm->dc, dm_state->context);
2708 /* Before powering on DC we need to re-initialize DMUB. */
2709 dm_dmub_hw_resume(adev);
2711 /* Re-enable outbox interrupts for DPIA. */
2712 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2713 amdgpu_dm_outbox_init(adev);
2714 dc_enable_dmub_outbox(adev->dm.dc);
2717 /* power on hardware */
2718 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2720 /* program HPD filter */
2724 * early enable HPD Rx IRQ, should be done before set mode as short
2725 * pulse interrupts are used for MST
2727 amdgpu_dm_irq_resume_early(adev);
2729 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2730 s3_handle_mst(ddev, false);
2733 drm_connector_list_iter_begin(ddev, &iter);
2734 drm_for_each_connector_iter(connector, &iter) {
2735 aconnector = to_amdgpu_dm_connector(connector);
2737 if (!aconnector->dc_link)
2741 * this is the case when traversing through already created
2742 * MST connectors, should be skipped
2744 if (aconnector->dc_link->type == dc_connection_mst_branch)
2747 mutex_lock(&aconnector->hpd_lock);
2748 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2749 DRM_ERROR("KMS: Failed to detect connector\n");
2751 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2752 emulated_link_detect(aconnector->dc_link);
2754 mutex_lock(&dm->dc_lock);
2755 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2756 mutex_unlock(&dm->dc_lock);
2759 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2760 aconnector->fake_enable = false;
2762 if (aconnector->dc_sink)
2763 dc_sink_release(aconnector->dc_sink);
2764 aconnector->dc_sink = NULL;
2765 amdgpu_dm_update_connector_after_detect(aconnector);
2766 mutex_unlock(&aconnector->hpd_lock);
2768 drm_connector_list_iter_end(&iter);
2770 /* Force mode set in atomic commit */
2771 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2772 new_crtc_state->active_changed = true;
2775 * atomic_check is expected to create the dc states. We need to release
2776 * them here, since they were duplicated as part of the suspend
2779 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2780 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2781 if (dm_new_crtc_state->stream) {
2782 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2783 dc_stream_release(dm_new_crtc_state->stream);
2784 dm_new_crtc_state->stream = NULL;
2788 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2789 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2790 if (dm_new_plane_state->dc_state) {
2791 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2792 dc_plane_state_release(dm_new_plane_state->dc_state);
2793 dm_new_plane_state->dc_state = NULL;
2797 drm_atomic_helper_resume(ddev, dm->cached_state);
2799 dm->cached_state = NULL;
2801 amdgpu_dm_irq_resume_late(adev);
2803 amdgpu_dm_smu_write_watermarks_table(adev);
2811 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2812 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2813 * the base driver's device list to be initialized and torn down accordingly.
2815 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2818 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2820 .early_init = dm_early_init,
2821 .late_init = dm_late_init,
2822 .sw_init = dm_sw_init,
2823 .sw_fini = dm_sw_fini,
2824 .early_fini = amdgpu_dm_early_fini,
2825 .hw_init = dm_hw_init,
2826 .hw_fini = dm_hw_fini,
2827 .suspend = dm_suspend,
2828 .resume = dm_resume,
2829 .is_idle = dm_is_idle,
2830 .wait_for_idle = dm_wait_for_idle,
2831 .check_soft_reset = dm_check_soft_reset,
2832 .soft_reset = dm_soft_reset,
2833 .set_clockgating_state = dm_set_clockgating_state,
2834 .set_powergating_state = dm_set_powergating_state,
2837 const struct amdgpu_ip_block_version dm_ip_block =
2839 .type = AMD_IP_BLOCK_TYPE_DCE,
2843 .funcs = &amdgpu_dm_funcs,
2853 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2854 .fb_create = amdgpu_display_user_framebuffer_create,
2855 .get_format_info = amd_get_format_info,
2856 .atomic_check = amdgpu_dm_atomic_check,
2857 .atomic_commit = drm_atomic_helper_commit,
2860 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2861 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2862 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2865 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2867 struct amdgpu_dm_backlight_caps *caps;
2868 struct amdgpu_display_manager *dm;
2869 struct drm_connector *conn_base;
2870 struct amdgpu_device *adev;
2871 struct dc_link *link = NULL;
2872 struct drm_luminance_range_info *luminance_range;
2875 if (!aconnector || !aconnector->dc_link)
2878 link = aconnector->dc_link;
2879 if (link->connector_signal != SIGNAL_TYPE_EDP)
2882 conn_base = &aconnector->base;
2883 adev = drm_to_adev(conn_base->dev);
2885 for (i = 0; i < dm->num_of_edps; i++) {
2886 if (link == dm->backlight_link[i])
2889 if (i >= dm->num_of_edps)
2891 caps = &dm->backlight_caps[i];
2892 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2893 caps->aux_support = false;
2895 if (caps->ext_caps->bits.oled == 1 /*||
2896 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2897 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2898 caps->aux_support = true;
2900 if (amdgpu_backlight == 0)
2901 caps->aux_support = false;
2902 else if (amdgpu_backlight == 1)
2903 caps->aux_support = true;
2905 luminance_range = &conn_base->display_info.luminance_range;
2906 caps->aux_min_input_signal = luminance_range->min_luminance;
2907 caps->aux_max_input_signal = luminance_range->max_luminance;
2910 void amdgpu_dm_update_connector_after_detect(
2911 struct amdgpu_dm_connector *aconnector)
2913 struct drm_connector *connector = &aconnector->base;
2914 struct drm_device *dev = connector->dev;
2915 struct dc_sink *sink;
2917 /* MST handled by drm_mst framework */
2918 if (aconnector->mst_mgr.mst_state == true)
2921 sink = aconnector->dc_link->local_sink;
2923 dc_sink_retain(sink);
2926 * Edid mgmt connector gets first update only in mode_valid hook and then
2927 * the connector sink is set to either fake or physical sink depends on link status.
2928 * Skip if already done during boot.
2930 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2931 && aconnector->dc_em_sink) {
2934 * For S3 resume with headless use eml_sink to fake stream
2935 * because on resume connector->sink is set to NULL
2937 mutex_lock(&dev->mode_config.mutex);
2940 if (aconnector->dc_sink) {
2941 amdgpu_dm_update_freesync_caps(connector, NULL);
2943 * retain and release below are used to
2944 * bump up refcount for sink because the link doesn't point
2945 * to it anymore after disconnect, so on next crtc to connector
2946 * reshuffle by UMD we will get into unwanted dc_sink release
2948 dc_sink_release(aconnector->dc_sink);
2950 aconnector->dc_sink = sink;
2951 dc_sink_retain(aconnector->dc_sink);
2952 amdgpu_dm_update_freesync_caps(connector,
2955 amdgpu_dm_update_freesync_caps(connector, NULL);
2956 if (!aconnector->dc_sink) {
2957 aconnector->dc_sink = aconnector->dc_em_sink;
2958 dc_sink_retain(aconnector->dc_sink);
2962 mutex_unlock(&dev->mode_config.mutex);
2965 dc_sink_release(sink);
2970 * TODO: temporary guard to look for proper fix
2971 * if this sink is MST sink, we should not do anything
2973 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2974 dc_sink_release(sink);
2978 if (aconnector->dc_sink == sink) {
2980 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2983 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2984 aconnector->connector_id);
2986 dc_sink_release(sink);
2990 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2991 aconnector->connector_id, aconnector->dc_sink, sink);
2993 mutex_lock(&dev->mode_config.mutex);
2996 * 1. Update status of the drm connector
2997 * 2. Send an event and let userspace tell us what to do
3001 * TODO: check if we still need the S3 mode update workaround.
3002 * If yes, put it here.
3004 if (aconnector->dc_sink) {
3005 amdgpu_dm_update_freesync_caps(connector, NULL);
3006 dc_sink_release(aconnector->dc_sink);
3009 aconnector->dc_sink = sink;
3010 dc_sink_retain(aconnector->dc_sink);
3011 if (sink->dc_edid.length == 0) {
3012 aconnector->edid = NULL;
3013 if (aconnector->dc_link->aux_mode) {
3014 drm_dp_cec_unset_edid(
3015 &aconnector->dm_dp_aux.aux);
3019 (struct edid *)sink->dc_edid.raw_edid;
3021 if (aconnector->dc_link->aux_mode)
3022 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3026 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3027 if (!aconnector->timing_requested)
3028 dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3030 drm_connector_update_edid_property(connector, aconnector->edid);
3031 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3032 update_connector_ext_caps(aconnector);
3034 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3035 amdgpu_dm_update_freesync_caps(connector, NULL);
3036 drm_connector_update_edid_property(connector, NULL);
3037 aconnector->num_modes = 0;
3038 dc_sink_release(aconnector->dc_sink);
3039 aconnector->dc_sink = NULL;
3040 aconnector->edid = NULL;
3041 kfree(aconnector->timing_requested);
3042 aconnector->timing_requested = NULL;
3043 #ifdef CONFIG_DRM_AMD_DC_HDCP
3044 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3045 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3046 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3050 mutex_unlock(&dev->mode_config.mutex);
3052 update_subconnector_property(aconnector);
3055 dc_sink_release(sink);
3058 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3060 struct drm_connector *connector = &aconnector->base;
3061 struct drm_device *dev = connector->dev;
3062 enum dc_connection_type new_connection_type = dc_connection_none;
3063 struct amdgpu_device *adev = drm_to_adev(dev);
3064 #ifdef CONFIG_DRM_AMD_DC_HDCP
3065 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3069 if (adev->dm.disable_hpd_irq)
3073 * In case of failure or MST no need to update connector status or notify the OS
3074 * since (for MST case) MST does this in its own context.
3076 mutex_lock(&aconnector->hpd_lock);
3078 #ifdef CONFIG_DRM_AMD_DC_HDCP
3079 if (adev->dm.hdcp_workqueue) {
3080 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3081 dm_con_state->update_hdcp = true;
3084 if (aconnector->fake_enable)
3085 aconnector->fake_enable = false;
3087 aconnector->timing_changed = false;
3089 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3090 DRM_ERROR("KMS: Failed to detect connector\n");
3092 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3093 emulated_link_detect(aconnector->dc_link);
3095 drm_modeset_lock_all(dev);
3096 dm_restore_drm_connector_state(dev, connector);
3097 drm_modeset_unlock_all(dev);
3099 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3100 drm_kms_helper_connector_hotplug_event(connector);
3102 mutex_lock(&adev->dm.dc_lock);
3103 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3104 mutex_unlock(&adev->dm.dc_lock);
3106 amdgpu_dm_update_connector_after_detect(aconnector);
3108 drm_modeset_lock_all(dev);
3109 dm_restore_drm_connector_state(dev, connector);
3110 drm_modeset_unlock_all(dev);
3112 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3113 drm_kms_helper_connector_hotplug_event(connector);
3116 mutex_unlock(&aconnector->hpd_lock);
3120 static void handle_hpd_irq(void *param)
3122 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3124 handle_hpd_irq_helper(aconnector);
3128 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3130 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3132 bool new_irq_handled = false;
3134 int dpcd_bytes_to_read;
3136 const int max_process_count = 30;
3137 int process_count = 0;
3139 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3141 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3142 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3143 /* DPCD 0x200 - 0x201 for downstream IRQ */
3144 dpcd_addr = DP_SINK_COUNT;
3146 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3147 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3148 dpcd_addr = DP_SINK_COUNT_ESI;
3151 dret = drm_dp_dpcd_read(
3152 &aconnector->dm_dp_aux.aux,
3155 dpcd_bytes_to_read);
3157 while (dret == dpcd_bytes_to_read &&
3158 process_count < max_process_count) {
3164 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3165 /* handle HPD short pulse irq */
3166 if (aconnector->mst_mgr.mst_state)
3168 &aconnector->mst_mgr,
3172 if (new_irq_handled) {
3173 /* ACK at DPCD to notify down stream */
3174 const int ack_dpcd_bytes_to_write =
3175 dpcd_bytes_to_read - 1;
3177 for (retry = 0; retry < 3; retry++) {
3180 wret = drm_dp_dpcd_write(
3181 &aconnector->dm_dp_aux.aux,
3184 ack_dpcd_bytes_to_write);
3185 if (wret == ack_dpcd_bytes_to_write)
3189 /* check if there is new irq to be handled */
3190 dret = drm_dp_dpcd_read(
3191 &aconnector->dm_dp_aux.aux,
3194 dpcd_bytes_to_read);
3196 new_irq_handled = false;
3202 if (process_count == max_process_count)
3203 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3206 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3207 union hpd_irq_data hpd_irq_data)
3209 struct hpd_rx_irq_offload_work *offload_work =
3210 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3212 if (!offload_work) {
3213 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3217 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3218 offload_work->data = hpd_irq_data;
3219 offload_work->offload_wq = offload_wq;
3221 queue_work(offload_wq->wq, &offload_work->work);
3222 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3225 static void handle_hpd_rx_irq(void *param)
3227 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3228 struct drm_connector *connector = &aconnector->base;
3229 struct drm_device *dev = connector->dev;
3230 struct dc_link *dc_link = aconnector->dc_link;
3231 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3232 bool result = false;
3233 enum dc_connection_type new_connection_type = dc_connection_none;
3234 struct amdgpu_device *adev = drm_to_adev(dev);
3235 union hpd_irq_data hpd_irq_data;
3236 bool link_loss = false;
3237 bool has_left_work = false;
3238 int idx = aconnector->base.index;
3239 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3241 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3243 if (adev->dm.disable_hpd_irq)
3247 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3248 * conflict, after implement i2c helper, this mutex should be
3251 mutex_lock(&aconnector->hpd_lock);
3253 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3254 &link_loss, true, &has_left_work);
3259 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3260 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3264 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3265 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3266 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3267 dm_handle_mst_sideband_msg(aconnector);
3274 spin_lock(&offload_wq->offload_lock);
3275 skip = offload_wq->is_handling_link_loss;
3278 offload_wq->is_handling_link_loss = true;
3280 spin_unlock(&offload_wq->offload_lock);
3283 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3290 if (result && !is_mst_root_connector) {
3291 /* Downstream Port status changed. */
3292 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3293 DRM_ERROR("KMS: Failed to detect connector\n");
3295 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3296 emulated_link_detect(dc_link);
3298 if (aconnector->fake_enable)
3299 aconnector->fake_enable = false;
3301 amdgpu_dm_update_connector_after_detect(aconnector);
3304 drm_modeset_lock_all(dev);
3305 dm_restore_drm_connector_state(dev, connector);
3306 drm_modeset_unlock_all(dev);
3308 drm_kms_helper_connector_hotplug_event(connector);
3312 mutex_lock(&adev->dm.dc_lock);
3313 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3314 mutex_unlock(&adev->dm.dc_lock);
3317 if (aconnector->fake_enable)
3318 aconnector->fake_enable = false;
3320 amdgpu_dm_update_connector_after_detect(aconnector);
3322 drm_modeset_lock_all(dev);
3323 dm_restore_drm_connector_state(dev, connector);
3324 drm_modeset_unlock_all(dev);
3326 drm_kms_helper_connector_hotplug_event(connector);
3330 #ifdef CONFIG_DRM_AMD_DC_HDCP
3331 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3332 if (adev->dm.hdcp_workqueue)
3333 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3337 if (dc_link->type != dc_connection_mst_branch)
3338 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3340 mutex_unlock(&aconnector->hpd_lock);
3343 static void register_hpd_handlers(struct amdgpu_device *adev)
3345 struct drm_device *dev = adev_to_drm(adev);
3346 struct drm_connector *connector;
3347 struct amdgpu_dm_connector *aconnector;
3348 const struct dc_link *dc_link;
3349 struct dc_interrupt_params int_params = {0};
3351 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3352 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3354 list_for_each_entry(connector,
3355 &dev->mode_config.connector_list, head) {
3357 aconnector = to_amdgpu_dm_connector(connector);
3358 dc_link = aconnector->dc_link;
3360 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3361 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3362 int_params.irq_source = dc_link->irq_source_hpd;
3364 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3366 (void *) aconnector);
3369 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3371 /* Also register for DP short pulse (hpd_rx). */
3372 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3373 int_params.irq_source = dc_link->irq_source_hpd_rx;
3375 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3377 (void *) aconnector);
3379 if (adev->dm.hpd_rx_offload_wq)
3380 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3386 #if defined(CONFIG_DRM_AMD_DC_SI)
3387 /* Register IRQ sources and initialize IRQ callbacks */
3388 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3390 struct dc *dc = adev->dm.dc;
3391 struct common_irq_params *c_irq_params;
3392 struct dc_interrupt_params int_params = {0};
3395 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3397 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3398 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3401 * Actions of amdgpu_irq_add_id():
3402 * 1. Register a set() function with base driver.
3403 * Base driver will call set() function to enable/disable an
3404 * interrupt in DC hardware.
3405 * 2. Register amdgpu_dm_irq_handler().
3406 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3407 * coming from DC hardware.
3408 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3409 * for acknowledging and handling. */
3411 /* Use VBLANK interrupt */
3412 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3413 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3415 DRM_ERROR("Failed to add crtc irq id!\n");
3419 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3420 int_params.irq_source =
3421 dc_interrupt_to_irq_source(dc, i+1 , 0);
3423 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3425 c_irq_params->adev = adev;
3426 c_irq_params->irq_src = int_params.irq_source;
3428 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3429 dm_crtc_high_irq, c_irq_params);
3432 /* Use GRPH_PFLIP interrupt */
3433 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3434 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3435 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3437 DRM_ERROR("Failed to add page flip irq id!\n");
3441 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3442 int_params.irq_source =
3443 dc_interrupt_to_irq_source(dc, i, 0);
3445 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3447 c_irq_params->adev = adev;
3448 c_irq_params->irq_src = int_params.irq_source;
3450 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3451 dm_pflip_high_irq, c_irq_params);
3456 r = amdgpu_irq_add_id(adev, client_id,
3457 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3459 DRM_ERROR("Failed to add hpd irq id!\n");
3463 register_hpd_handlers(adev);
3469 /* Register IRQ sources and initialize IRQ callbacks */
3470 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3472 struct dc *dc = adev->dm.dc;
3473 struct common_irq_params *c_irq_params;
3474 struct dc_interrupt_params int_params = {0};
3477 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3479 if (adev->family >= AMDGPU_FAMILY_AI)
3480 client_id = SOC15_IH_CLIENTID_DCE;
3482 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3483 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3486 * Actions of amdgpu_irq_add_id():
3487 * 1. Register a set() function with base driver.
3488 * Base driver will call set() function to enable/disable an
3489 * interrupt in DC hardware.
3490 * 2. Register amdgpu_dm_irq_handler().
3491 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3492 * coming from DC hardware.
3493 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3494 * for acknowledging and handling. */
3496 /* Use VBLANK interrupt */
3497 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3498 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3500 DRM_ERROR("Failed to add crtc irq id!\n");
3504 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3505 int_params.irq_source =
3506 dc_interrupt_to_irq_source(dc, i, 0);
3508 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3510 c_irq_params->adev = adev;
3511 c_irq_params->irq_src = int_params.irq_source;
3513 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3514 dm_crtc_high_irq, c_irq_params);
3517 /* Use VUPDATE interrupt */
3518 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3519 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3521 DRM_ERROR("Failed to add vupdate irq id!\n");
3525 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3526 int_params.irq_source =
3527 dc_interrupt_to_irq_source(dc, i, 0);
3529 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3531 c_irq_params->adev = adev;
3532 c_irq_params->irq_src = int_params.irq_source;
3534 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3535 dm_vupdate_high_irq, c_irq_params);
3538 /* Use GRPH_PFLIP interrupt */
3539 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3540 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3541 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3543 DRM_ERROR("Failed to add page flip irq id!\n");
3547 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3548 int_params.irq_source =
3549 dc_interrupt_to_irq_source(dc, i, 0);
3551 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3553 c_irq_params->adev = adev;
3554 c_irq_params->irq_src = int_params.irq_source;
3556 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3557 dm_pflip_high_irq, c_irq_params);
3562 r = amdgpu_irq_add_id(adev, client_id,
3563 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3565 DRM_ERROR("Failed to add hpd irq id!\n");
3569 register_hpd_handlers(adev);
3574 /* Register IRQ sources and initialize IRQ callbacks */
3575 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3577 struct dc *dc = adev->dm.dc;
3578 struct common_irq_params *c_irq_params;
3579 struct dc_interrupt_params int_params = {0};
3582 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3583 static const unsigned int vrtl_int_srcid[] = {
3584 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3585 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3586 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3587 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3588 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3589 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3593 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3594 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3597 * Actions of amdgpu_irq_add_id():
3598 * 1. Register a set() function with base driver.
3599 * Base driver will call set() function to enable/disable an
3600 * interrupt in DC hardware.
3601 * 2. Register amdgpu_dm_irq_handler().
3602 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3603 * coming from DC hardware.
3604 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3605 * for acknowledging and handling.
3608 /* Use VSTARTUP interrupt */
3609 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3610 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3612 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3615 DRM_ERROR("Failed to add crtc irq id!\n");
3619 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3620 int_params.irq_source =
3621 dc_interrupt_to_irq_source(dc, i, 0);
3623 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3625 c_irq_params->adev = adev;
3626 c_irq_params->irq_src = int_params.irq_source;
3628 amdgpu_dm_irq_register_interrupt(
3629 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3632 /* Use otg vertical line interrupt */
3633 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3634 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3635 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3636 vrtl_int_srcid[i], &adev->vline0_irq);
3639 DRM_ERROR("Failed to add vline0 irq id!\n");
3643 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3644 int_params.irq_source =
3645 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3647 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3648 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3652 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3653 - DC_IRQ_SOURCE_DC1_VLINE0];
3655 c_irq_params->adev = adev;
3656 c_irq_params->irq_src = int_params.irq_source;
3658 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3659 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3663 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3664 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3665 * to trigger at end of each vblank, regardless of state of the lock,
3666 * matching DCE behaviour.
3668 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3669 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3671 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3674 DRM_ERROR("Failed to add vupdate irq id!\n");
3678 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3679 int_params.irq_source =
3680 dc_interrupt_to_irq_source(dc, i, 0);
3682 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3684 c_irq_params->adev = adev;
3685 c_irq_params->irq_src = int_params.irq_source;
3687 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3688 dm_vupdate_high_irq, c_irq_params);
3691 /* Use GRPH_PFLIP interrupt */
3692 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3693 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3695 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3697 DRM_ERROR("Failed to add page flip irq id!\n");
3701 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3702 int_params.irq_source =
3703 dc_interrupt_to_irq_source(dc, i, 0);
3705 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3707 c_irq_params->adev = adev;
3708 c_irq_params->irq_src = int_params.irq_source;
3710 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3711 dm_pflip_high_irq, c_irq_params);
3716 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3719 DRM_ERROR("Failed to add hpd irq id!\n");
3723 register_hpd_handlers(adev);
3727 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3728 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3730 struct dc *dc = adev->dm.dc;
3731 struct common_irq_params *c_irq_params;
3732 struct dc_interrupt_params int_params = {0};
3735 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3736 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3738 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3739 &adev->dmub_outbox_irq);
3741 DRM_ERROR("Failed to add outbox irq id!\n");
3745 if (dc->ctx->dmub_srv) {
3746 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3747 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3748 int_params.irq_source =
3749 dc_interrupt_to_irq_source(dc, i, 0);
3751 c_irq_params = &adev->dm.dmub_outbox_params[0];
3753 c_irq_params->adev = adev;
3754 c_irq_params->irq_src = int_params.irq_source;
3756 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3757 dm_dmub_outbox1_low_irq, c_irq_params);
3764 * Acquires the lock for the atomic state object and returns
3765 * the new atomic state.
3767 * This should only be called during atomic check.
3769 int dm_atomic_get_state(struct drm_atomic_state *state,
3770 struct dm_atomic_state **dm_state)
3772 struct drm_device *dev = state->dev;
3773 struct amdgpu_device *adev = drm_to_adev(dev);
3774 struct amdgpu_display_manager *dm = &adev->dm;
3775 struct drm_private_state *priv_state;
3780 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3781 if (IS_ERR(priv_state))
3782 return PTR_ERR(priv_state);
3784 *dm_state = to_dm_atomic_state(priv_state);
3789 static struct dm_atomic_state *
3790 dm_atomic_get_new_state(struct drm_atomic_state *state)
3792 struct drm_device *dev = state->dev;
3793 struct amdgpu_device *adev = drm_to_adev(dev);
3794 struct amdgpu_display_manager *dm = &adev->dm;
3795 struct drm_private_obj *obj;
3796 struct drm_private_state *new_obj_state;
3799 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3800 if (obj->funcs == dm->atomic_obj.funcs)
3801 return to_dm_atomic_state(new_obj_state);
3807 static struct drm_private_state *
3808 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3810 struct dm_atomic_state *old_state, *new_state;
3812 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3816 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3818 old_state = to_dm_atomic_state(obj->state);
3820 if (old_state && old_state->context)
3821 new_state->context = dc_copy_state(old_state->context);
3823 if (!new_state->context) {
3828 return &new_state->base;
3831 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3832 struct drm_private_state *state)
3834 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3836 if (dm_state && dm_state->context)
3837 dc_release_state(dm_state->context);
3842 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3843 .atomic_duplicate_state = dm_atomic_duplicate_state,
3844 .atomic_destroy_state = dm_atomic_destroy_state,
3847 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3849 struct dm_atomic_state *state;
3852 adev->mode_info.mode_config_initialized = true;
3854 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3855 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3857 adev_to_drm(adev)->mode_config.max_width = 16384;
3858 adev_to_drm(adev)->mode_config.max_height = 16384;
3860 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3861 if (adev->asic_type == CHIP_HAWAII)
3862 /* disable prefer shadow for now due to hibernation issues */
3863 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3865 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3866 /* indicates support for immediate flip */
3867 adev_to_drm(adev)->mode_config.async_page_flip = true;
3869 state = kzalloc(sizeof(*state), GFP_KERNEL);
3873 state->context = dc_create_state(adev->dm.dc);
3874 if (!state->context) {
3879 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3881 drm_atomic_private_obj_init(adev_to_drm(adev),
3882 &adev->dm.atomic_obj,
3884 &dm_atomic_state_funcs);
3886 r = amdgpu_display_modeset_create_props(adev);
3888 dc_release_state(state->context);
3893 r = amdgpu_dm_audio_init(adev);
3895 dc_release_state(state->context);
3903 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3904 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3905 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3907 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3910 #if defined(CONFIG_ACPI)
3911 struct amdgpu_dm_backlight_caps caps;
3913 memset(&caps, 0, sizeof(caps));
3915 if (dm->backlight_caps[bl_idx].caps_valid)
3918 amdgpu_acpi_get_backlight_caps(&caps);
3919 if (caps.caps_valid) {
3920 dm->backlight_caps[bl_idx].caps_valid = true;
3921 if (caps.aux_support)
3923 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3924 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3926 dm->backlight_caps[bl_idx].min_input_signal =
3927 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3928 dm->backlight_caps[bl_idx].max_input_signal =
3929 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3932 if (dm->backlight_caps[bl_idx].aux_support)
3935 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3936 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3940 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3941 unsigned *min, unsigned *max)
3946 if (caps->aux_support) {
3947 // Firmware limits are in nits, DC API wants millinits.
3948 *max = 1000 * caps->aux_max_input_signal;
3949 *min = 1000 * caps->aux_min_input_signal;
3951 // Firmware limits are 8-bit, PWM control is 16-bit.
3952 *max = 0x101 * caps->max_input_signal;
3953 *min = 0x101 * caps->min_input_signal;
3958 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3959 uint32_t brightness)
3963 if (!get_brightness_range(caps, &min, &max))
3966 // Rescale 0..255 to min..max
3967 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3968 AMDGPU_MAX_BL_LEVEL);
3971 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3972 uint32_t brightness)
3976 if (!get_brightness_range(caps, &min, &max))
3979 if (brightness < min)
3981 // Rescale min..max to 0..255
3982 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3986 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
3988 u32 user_brightness)
3990 struct amdgpu_dm_backlight_caps caps;
3991 struct dc_link *link;
3995 amdgpu_dm_update_backlight_caps(dm, bl_idx);
3996 caps = dm->backlight_caps[bl_idx];
3998 dm->brightness[bl_idx] = user_brightness;
3999 /* update scratch register */
4001 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4002 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4003 link = (struct dc_link *)dm->backlight_link[bl_idx];
4005 /* Change brightness based on AUX property */
4006 if (caps.aux_support) {
4007 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4008 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4010 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4012 rc = dc_link_set_backlight_level(link, brightness, 0);
4014 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4018 dm->actual_brightness[bl_idx] = user_brightness;
4021 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4023 struct amdgpu_display_manager *dm = bl_get_data(bd);
4026 for (i = 0; i < dm->num_of_edps; i++) {
4027 if (bd == dm->backlight_dev[i])
4030 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4032 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4037 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4040 struct amdgpu_dm_backlight_caps caps;
4041 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4043 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4044 caps = dm->backlight_caps[bl_idx];
4046 if (caps.aux_support) {
4050 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4052 return dm->brightness[bl_idx];
4053 return convert_brightness_to_user(&caps, avg);
4055 int ret = dc_link_get_backlight_level(link);
4057 if (ret == DC_ERROR_UNEXPECTED)
4058 return dm->brightness[bl_idx];
4059 return convert_brightness_to_user(&caps, ret);
4063 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4065 struct amdgpu_display_manager *dm = bl_get_data(bd);
4068 for (i = 0; i < dm->num_of_edps; i++) {
4069 if (bd == dm->backlight_dev[i])
4072 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4074 return amdgpu_dm_backlight_get_level(dm, i);
4077 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4078 .options = BL_CORE_SUSPENDRESUME,
4079 .get_brightness = amdgpu_dm_backlight_get_brightness,
4080 .update_status = amdgpu_dm_backlight_update_status,
4084 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4087 struct backlight_properties props = { 0 };
4089 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4090 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4092 if (!acpi_video_backlight_use_native()) {
4093 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4094 /* Try registering an ACPI video backlight device instead. */
4095 acpi_video_register_backlight();
4099 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4100 props.brightness = AMDGPU_MAX_BL_LEVEL;
4101 props.type = BACKLIGHT_RAW;
4103 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4104 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4106 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4107 adev_to_drm(dm->adev)->dev,
4109 &amdgpu_dm_backlight_ops,
4112 if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4113 DRM_ERROR("DM: Backlight registration failed!\n");
4115 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4118 static int initialize_plane(struct amdgpu_display_manager *dm,
4119 struct amdgpu_mode_info *mode_info, int plane_id,
4120 enum drm_plane_type plane_type,
4121 const struct dc_plane_cap *plane_cap)
4123 struct drm_plane *plane;
4124 unsigned long possible_crtcs;
4127 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4129 DRM_ERROR("KMS: Failed to allocate plane\n");
4132 plane->type = plane_type;
4135 * HACK: IGT tests expect that the primary plane for a CRTC
4136 * can only have one possible CRTC. Only expose support for
4137 * any CRTC if they're not going to be used as a primary plane
4138 * for a CRTC - like overlay or underlay planes.
4140 possible_crtcs = 1 << plane_id;
4141 if (plane_id >= dm->dc->caps.max_streams)
4142 possible_crtcs = 0xff;
4144 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4147 DRM_ERROR("KMS: Failed to initialize plane\n");
4153 mode_info->planes[plane_id] = plane;
4159 static void register_backlight_device(struct amdgpu_display_manager *dm,
4160 struct dc_link *link)
4162 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4163 link->type != dc_connection_none) {
4165 * Event if registration failed, we should continue with
4166 * DM initialization because not having a backlight control
4167 * is better then a black screen.
4169 if (!dm->backlight_dev[dm->num_of_edps])
4170 amdgpu_dm_register_backlight_device(dm);
4172 if (dm->backlight_dev[dm->num_of_edps]) {
4173 dm->backlight_link[dm->num_of_edps] = link;
4179 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4182 * In this architecture, the association
4183 * connector -> encoder -> crtc
4184 * id not really requried. The crtc and connector will hold the
4185 * display_index as an abstraction to use with DAL component
4187 * Returns 0 on success
4189 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4191 struct amdgpu_display_manager *dm = &adev->dm;
4193 struct amdgpu_dm_connector *aconnector = NULL;
4194 struct amdgpu_encoder *aencoder = NULL;
4195 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4198 enum dc_connection_type new_connection_type = dc_connection_none;
4199 const struct dc_plane_cap *plane;
4200 bool psr_feature_enabled = false;
4202 dm->display_indexes_num = dm->dc->caps.max_streams;
4203 /* Update the actual used number of crtc */
4204 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4206 link_cnt = dm->dc->caps.max_links;
4207 if (amdgpu_dm_mode_config_init(dm->adev)) {
4208 DRM_ERROR("DM: Failed to initialize mode config\n");
4212 /* There is one primary plane per CRTC */
4213 primary_planes = dm->dc->caps.max_streams;
4214 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4217 * Initialize primary planes, implicit planes for legacy IOCTLS.
4218 * Order is reversed to match iteration order in atomic check.
4220 for (i = (primary_planes - 1); i >= 0; i--) {
4221 plane = &dm->dc->caps.planes[i];
4223 if (initialize_plane(dm, mode_info, i,
4224 DRM_PLANE_TYPE_PRIMARY, plane)) {
4225 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4231 * Initialize overlay planes, index starting after primary planes.
4232 * These planes have a higher DRM index than the primary planes since
4233 * they should be considered as having a higher z-order.
4234 * Order is reversed to match iteration order in atomic check.
4236 * Only support DCN for now, and only expose one so we don't encourage
4237 * userspace to use up all the pipes.
4239 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4240 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4242 /* Do not create overlay if MPO disabled */
4243 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4246 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4249 if (!plane->blends_with_above || !plane->blends_with_below)
4252 if (!plane->pixel_format_support.argb8888)
4255 if (initialize_plane(dm, NULL, primary_planes + i,
4256 DRM_PLANE_TYPE_OVERLAY, plane)) {
4257 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4261 /* Only create one overlay plane. */
4265 for (i = 0; i < dm->dc->caps.max_streams; i++)
4266 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4267 DRM_ERROR("KMS: Failed to initialize crtc\n");
4271 /* Use Outbox interrupt */
4272 switch (adev->ip_versions[DCE_HWIP][0]) {
4273 case IP_VERSION(3, 0, 0):
4274 case IP_VERSION(3, 1, 2):
4275 case IP_VERSION(3, 1, 3):
4276 case IP_VERSION(3, 1, 4):
4277 case IP_VERSION(3, 1, 5):
4278 case IP_VERSION(3, 1, 6):
4279 case IP_VERSION(3, 2, 0):
4280 case IP_VERSION(3, 2, 1):
4281 case IP_VERSION(2, 1, 0):
4282 if (register_outbox_irq_handlers(dm->adev)) {
4283 DRM_ERROR("DM: Failed to initialize IRQ\n");
4288 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4289 adev->ip_versions[DCE_HWIP][0]);
4292 /* Determine whether to enable PSR support by default. */
4293 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4294 switch (adev->ip_versions[DCE_HWIP][0]) {
4295 case IP_VERSION(3, 1, 2):
4296 case IP_VERSION(3, 1, 3):
4297 case IP_VERSION(3, 1, 4):
4298 case IP_VERSION(3, 1, 5):
4299 case IP_VERSION(3, 1, 6):
4300 case IP_VERSION(3, 2, 0):
4301 case IP_VERSION(3, 2, 1):
4302 psr_feature_enabled = true;
4305 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4310 /* loops over all connectors on the board */
4311 for (i = 0; i < link_cnt; i++) {
4312 struct dc_link *link = NULL;
4314 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4316 "KMS: Cannot support more than %d display indexes\n",
4317 AMDGPU_DM_MAX_DISPLAY_INDEX);
4321 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4325 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4329 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4330 DRM_ERROR("KMS: Failed to initialize encoder\n");
4334 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4335 DRM_ERROR("KMS: Failed to initialize connector\n");
4339 link = dc_get_link_at_index(dm->dc, i);
4341 if (!dc_link_detect_sink(link, &new_connection_type))
4342 DRM_ERROR("KMS: Failed to detect connector\n");
4344 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4345 emulated_link_detect(link);
4346 amdgpu_dm_update_connector_after_detect(aconnector);
4350 mutex_lock(&dm->dc_lock);
4351 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4352 mutex_unlock(&dm->dc_lock);
4355 amdgpu_dm_update_connector_after_detect(aconnector);
4356 register_backlight_device(dm, link);
4358 if (dm->num_of_edps)
4359 update_connector_ext_caps(aconnector);
4361 if (psr_feature_enabled)
4362 amdgpu_dm_set_psr_caps(link);
4364 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4365 * PSR is also supported.
4367 if (link->psr_settings.psr_feature_enabled)
4368 adev_to_drm(adev)->vblank_disable_immediate = false;
4371 amdgpu_set_panel_orientation(&aconnector->base);
4374 /* If we didn't find a panel, notify the acpi video detection */
4375 if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4376 acpi_video_report_nolcd();
4378 /* Software is initialized. Now we can register interrupt handlers. */
4379 switch (adev->asic_type) {
4380 #if defined(CONFIG_DRM_AMD_DC_SI)
4385 if (dce60_register_irq_handlers(dm->adev)) {
4386 DRM_ERROR("DM: Failed to initialize IRQ\n");
4400 case CHIP_POLARIS11:
4401 case CHIP_POLARIS10:
4402 case CHIP_POLARIS12:
4407 if (dce110_register_irq_handlers(dm->adev)) {
4408 DRM_ERROR("DM: Failed to initialize IRQ\n");
4413 switch (adev->ip_versions[DCE_HWIP][0]) {
4414 case IP_VERSION(1, 0, 0):
4415 case IP_VERSION(1, 0, 1):
4416 case IP_VERSION(2, 0, 2):
4417 case IP_VERSION(2, 0, 3):
4418 case IP_VERSION(2, 0, 0):
4419 case IP_VERSION(2, 1, 0):
4420 case IP_VERSION(3, 0, 0):
4421 case IP_VERSION(3, 0, 2):
4422 case IP_VERSION(3, 0, 3):
4423 case IP_VERSION(3, 0, 1):
4424 case IP_VERSION(3, 1, 2):
4425 case IP_VERSION(3, 1, 3):
4426 case IP_VERSION(3, 1, 4):
4427 case IP_VERSION(3, 1, 5):
4428 case IP_VERSION(3, 1, 6):
4429 case IP_VERSION(3, 2, 0):
4430 case IP_VERSION(3, 2, 1):
4431 if (dcn10_register_irq_handlers(dm->adev)) {
4432 DRM_ERROR("DM: Failed to initialize IRQ\n");
4437 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4438 adev->ip_versions[DCE_HWIP][0]);
4452 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4454 drm_atomic_private_obj_fini(&dm->atomic_obj);
4458 /******************************************************************************
4459 * amdgpu_display_funcs functions
4460 *****************************************************************************/
4463 * dm_bandwidth_update - program display watermarks
4465 * @adev: amdgpu_device pointer
4467 * Calculate and program the display watermarks and line buffer allocation.
4469 static void dm_bandwidth_update(struct amdgpu_device *adev)
4471 /* TODO: implement later */
4474 static const struct amdgpu_display_funcs dm_display_funcs = {
4475 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4476 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4477 .backlight_set_level = NULL, /* never called for DC */
4478 .backlight_get_level = NULL, /* never called for DC */
4479 .hpd_sense = NULL,/* called unconditionally */
4480 .hpd_set_polarity = NULL, /* called unconditionally */
4481 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4482 .page_flip_get_scanoutpos =
4483 dm_crtc_get_scanoutpos,/* called unconditionally */
4484 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4485 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4488 #if defined(CONFIG_DEBUG_KERNEL_DC)
4490 static ssize_t s3_debug_store(struct device *device,
4491 struct device_attribute *attr,
4497 struct drm_device *drm_dev = dev_get_drvdata(device);
4498 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4500 ret = kstrtoint(buf, 0, &s3_state);
4505 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4510 return ret == 0 ? count : 0;
4513 DEVICE_ATTR_WO(s3_debug);
4517 static int dm_init_microcode(struct amdgpu_device *adev)
4522 switch (adev->ip_versions[DCE_HWIP][0]) {
4523 case IP_VERSION(2, 1, 0):
4524 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4525 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4526 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4528 case IP_VERSION(3, 0, 0):
4529 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4530 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4532 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4534 case IP_VERSION(3, 0, 1):
4535 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4537 case IP_VERSION(3, 0, 2):
4538 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4540 case IP_VERSION(3, 0, 3):
4541 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4543 case IP_VERSION(3, 1, 2):
4544 case IP_VERSION(3, 1, 3):
4545 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4547 case IP_VERSION(3, 1, 4):
4548 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4550 case IP_VERSION(3, 1, 5):
4551 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4553 case IP_VERSION(3, 1, 6):
4554 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4556 case IP_VERSION(3, 2, 0):
4557 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4559 case IP_VERSION(3, 2, 1):
4560 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4563 /* ASIC doesn't support DMUB. */
4566 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4568 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4572 static int dm_early_init(void *handle)
4574 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4576 switch (adev->asic_type) {
4577 #if defined(CONFIG_DRM_AMD_DC_SI)
4581 adev->mode_info.num_crtc = 6;
4582 adev->mode_info.num_hpd = 6;
4583 adev->mode_info.num_dig = 6;
4586 adev->mode_info.num_crtc = 2;
4587 adev->mode_info.num_hpd = 2;
4588 adev->mode_info.num_dig = 2;
4593 adev->mode_info.num_crtc = 6;
4594 adev->mode_info.num_hpd = 6;
4595 adev->mode_info.num_dig = 6;
4598 adev->mode_info.num_crtc = 4;
4599 adev->mode_info.num_hpd = 6;
4600 adev->mode_info.num_dig = 7;
4604 adev->mode_info.num_crtc = 2;
4605 adev->mode_info.num_hpd = 6;
4606 adev->mode_info.num_dig = 6;
4610 adev->mode_info.num_crtc = 6;
4611 adev->mode_info.num_hpd = 6;
4612 adev->mode_info.num_dig = 7;
4615 adev->mode_info.num_crtc = 3;
4616 adev->mode_info.num_hpd = 6;
4617 adev->mode_info.num_dig = 9;
4620 adev->mode_info.num_crtc = 2;
4621 adev->mode_info.num_hpd = 6;
4622 adev->mode_info.num_dig = 9;
4624 case CHIP_POLARIS11:
4625 case CHIP_POLARIS12:
4626 adev->mode_info.num_crtc = 5;
4627 adev->mode_info.num_hpd = 5;
4628 adev->mode_info.num_dig = 5;
4630 case CHIP_POLARIS10:
4632 adev->mode_info.num_crtc = 6;
4633 adev->mode_info.num_hpd = 6;
4634 adev->mode_info.num_dig = 6;
4639 adev->mode_info.num_crtc = 6;
4640 adev->mode_info.num_hpd = 6;
4641 adev->mode_info.num_dig = 6;
4645 switch (adev->ip_versions[DCE_HWIP][0]) {
4646 case IP_VERSION(2, 0, 2):
4647 case IP_VERSION(3, 0, 0):
4648 adev->mode_info.num_crtc = 6;
4649 adev->mode_info.num_hpd = 6;
4650 adev->mode_info.num_dig = 6;
4652 case IP_VERSION(2, 0, 0):
4653 case IP_VERSION(3, 0, 2):
4654 adev->mode_info.num_crtc = 5;
4655 adev->mode_info.num_hpd = 5;
4656 adev->mode_info.num_dig = 5;
4658 case IP_VERSION(2, 0, 3):
4659 case IP_VERSION(3, 0, 3):
4660 adev->mode_info.num_crtc = 2;
4661 adev->mode_info.num_hpd = 2;
4662 adev->mode_info.num_dig = 2;
4664 case IP_VERSION(1, 0, 0):
4665 case IP_VERSION(1, 0, 1):
4666 case IP_VERSION(3, 0, 1):
4667 case IP_VERSION(2, 1, 0):
4668 case IP_VERSION(3, 1, 2):
4669 case IP_VERSION(3, 1, 3):
4670 case IP_VERSION(3, 1, 4):
4671 case IP_VERSION(3, 1, 5):
4672 case IP_VERSION(3, 1, 6):
4673 case IP_VERSION(3, 2, 0):
4674 case IP_VERSION(3, 2, 1):
4675 adev->mode_info.num_crtc = 4;
4676 adev->mode_info.num_hpd = 4;
4677 adev->mode_info.num_dig = 4;
4680 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4681 adev->ip_versions[DCE_HWIP][0]);
4687 amdgpu_dm_set_irq_funcs(adev);
4689 if (adev->mode_info.funcs == NULL)
4690 adev->mode_info.funcs = &dm_display_funcs;
4693 * Note: Do NOT change adev->audio_endpt_rreg and
4694 * adev->audio_endpt_wreg because they are initialised in
4695 * amdgpu_device_init()
4697 #if defined(CONFIG_DEBUG_KERNEL_DC)
4699 adev_to_drm(adev)->dev,
4700 &dev_attr_s3_debug);
4702 adev->dc_enabled = true;
4704 return dm_init_microcode(adev);
4707 static bool modereset_required(struct drm_crtc_state *crtc_state)
4709 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4712 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4714 drm_encoder_cleanup(encoder);
4718 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4719 .destroy = amdgpu_dm_encoder_destroy,
4723 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4724 const enum surface_pixel_format format,
4725 enum dc_color_space *color_space)
4729 *color_space = COLOR_SPACE_SRGB;
4731 /* DRM color properties only affect non-RGB formats. */
4732 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4735 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4737 switch (plane_state->color_encoding) {
4738 case DRM_COLOR_YCBCR_BT601:
4740 *color_space = COLOR_SPACE_YCBCR601;
4742 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4745 case DRM_COLOR_YCBCR_BT709:
4747 *color_space = COLOR_SPACE_YCBCR709;
4749 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4752 case DRM_COLOR_YCBCR_BT2020:
4754 *color_space = COLOR_SPACE_2020_YCBCR;
4767 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4768 const struct drm_plane_state *plane_state,
4769 const u64 tiling_flags,
4770 struct dc_plane_info *plane_info,
4771 struct dc_plane_address *address,
4773 bool force_disable_dcc)
4775 const struct drm_framebuffer *fb = plane_state->fb;
4776 const struct amdgpu_framebuffer *afb =
4777 to_amdgpu_framebuffer(plane_state->fb);
4780 memset(plane_info, 0, sizeof(*plane_info));
4782 switch (fb->format->format) {
4784 plane_info->format =
4785 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4787 case DRM_FORMAT_RGB565:
4788 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4790 case DRM_FORMAT_XRGB8888:
4791 case DRM_FORMAT_ARGB8888:
4792 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4794 case DRM_FORMAT_XRGB2101010:
4795 case DRM_FORMAT_ARGB2101010:
4796 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4798 case DRM_FORMAT_XBGR2101010:
4799 case DRM_FORMAT_ABGR2101010:
4800 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4802 case DRM_FORMAT_XBGR8888:
4803 case DRM_FORMAT_ABGR8888:
4804 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4806 case DRM_FORMAT_NV21:
4807 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4809 case DRM_FORMAT_NV12:
4810 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4812 case DRM_FORMAT_P010:
4813 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4815 case DRM_FORMAT_XRGB16161616F:
4816 case DRM_FORMAT_ARGB16161616F:
4817 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4819 case DRM_FORMAT_XBGR16161616F:
4820 case DRM_FORMAT_ABGR16161616F:
4821 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4823 case DRM_FORMAT_XRGB16161616:
4824 case DRM_FORMAT_ARGB16161616:
4825 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4827 case DRM_FORMAT_XBGR16161616:
4828 case DRM_FORMAT_ABGR16161616:
4829 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4833 "Unsupported screen format %p4cc\n",
4834 &fb->format->format);
4838 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4839 case DRM_MODE_ROTATE_0:
4840 plane_info->rotation = ROTATION_ANGLE_0;
4842 case DRM_MODE_ROTATE_90:
4843 plane_info->rotation = ROTATION_ANGLE_90;
4845 case DRM_MODE_ROTATE_180:
4846 plane_info->rotation = ROTATION_ANGLE_180;
4848 case DRM_MODE_ROTATE_270:
4849 plane_info->rotation = ROTATION_ANGLE_270;
4852 plane_info->rotation = ROTATION_ANGLE_0;
4857 plane_info->visible = true;
4858 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4860 plane_info->layer_index = plane_state->normalized_zpos;
4862 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4863 &plane_info->color_space);
4867 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4868 plane_info->rotation, tiling_flags,
4869 &plane_info->tiling_info,
4870 &plane_info->plane_size,
4871 &plane_info->dcc, address,
4872 tmz_surface, force_disable_dcc);
4876 fill_blending_from_plane_state(
4877 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4878 &plane_info->global_alpha, &plane_info->global_alpha_value);
4883 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4884 struct dc_plane_state *dc_plane_state,
4885 struct drm_plane_state *plane_state,
4886 struct drm_crtc_state *crtc_state)
4888 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4889 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4890 struct dc_scaling_info scaling_info;
4891 struct dc_plane_info plane_info;
4893 bool force_disable_dcc = false;
4895 ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4899 dc_plane_state->src_rect = scaling_info.src_rect;
4900 dc_plane_state->dst_rect = scaling_info.dst_rect;
4901 dc_plane_state->clip_rect = scaling_info.clip_rect;
4902 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4904 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4905 ret = fill_dc_plane_info_and_addr(adev, plane_state,
4908 &dc_plane_state->address,
4914 dc_plane_state->format = plane_info.format;
4915 dc_plane_state->color_space = plane_info.color_space;
4916 dc_plane_state->format = plane_info.format;
4917 dc_plane_state->plane_size = plane_info.plane_size;
4918 dc_plane_state->rotation = plane_info.rotation;
4919 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4920 dc_plane_state->stereo_format = plane_info.stereo_format;
4921 dc_plane_state->tiling_info = plane_info.tiling_info;
4922 dc_plane_state->visible = plane_info.visible;
4923 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4924 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4925 dc_plane_state->global_alpha = plane_info.global_alpha;
4926 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4927 dc_plane_state->dcc = plane_info.dcc;
4928 dc_plane_state->layer_index = plane_info.layer_index;
4929 dc_plane_state->flip_int_enabled = true;
4932 * Always set input transfer function, since plane state is refreshed
4935 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4942 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
4943 struct rect *dirty_rect, int32_t x,
4944 s32 y, s32 width, s32 height,
4947 if (*i > DC_MAX_DIRTY_RECTS)
4950 if (*i == DC_MAX_DIRTY_RECTS)
4955 dirty_rect->width = width;
4956 dirty_rect->height = height;
4960 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4961 plane->base.id, width, height);
4964 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
4965 plane->base.id, x, y, width, height);
4972 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4974 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4976 * @old_plane_state: Old state of @plane
4977 * @new_plane_state: New state of @plane
4978 * @crtc_state: New state of CRTC connected to the @plane
4979 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4981 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4982 * (referred to as "damage clips" in DRM nomenclature) that require updating on
4983 * the eDP remote buffer. The responsibility of specifying the dirty regions is
4986 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4987 * plane with regions that require flushing to the eDP remote buffer. In
4988 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4989 * implicitly provide damage clips without any client support via the plane
4992 static void fill_dc_dirty_rects(struct drm_plane *plane,
4993 struct drm_plane_state *old_plane_state,
4994 struct drm_plane_state *new_plane_state,
4995 struct drm_crtc_state *crtc_state,
4996 struct dc_flip_addrs *flip_addrs)
4998 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4999 struct rect *dirty_rects = flip_addrs->dirty_rects;
5001 struct drm_mode_rect *clips;
5007 * Cursor plane has it's own dirty rect update interface. See
5008 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5010 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5013 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5014 clips = drm_plane_get_damage_clips(new_plane_state);
5016 if (!dm_crtc_state->mpo_requested) {
5017 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5020 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5021 fill_dc_dirty_rect(new_plane_state->plane,
5022 &dirty_rects[i], clips->x1,
5023 clips->y1, clips->x2 - clips->x1,
5024 clips->y2 - clips->y1,
5025 &flip_addrs->dirty_rect_count,
5031 * MPO is requested. Add entire plane bounding box to dirty rects if
5032 * flipped to or damaged.
5034 * If plane is moved or resized, also add old bounding box to dirty
5037 fb_changed = old_plane_state->fb->base.id !=
5038 new_plane_state->fb->base.id;
5039 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5040 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5041 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5042 old_plane_state->crtc_h != new_plane_state->crtc_h);
5045 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5046 new_plane_state->plane->base.id,
5047 bb_changed, fb_changed, num_clips);
5050 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5051 new_plane_state->crtc_x,
5052 new_plane_state->crtc_y,
5053 new_plane_state->crtc_w,
5054 new_plane_state->crtc_h, &i, false);
5056 /* Add old plane bounding-box if plane is moved or resized */
5057 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5058 old_plane_state->crtc_x,
5059 old_plane_state->crtc_y,
5060 old_plane_state->crtc_w,
5061 old_plane_state->crtc_h, &i, false);
5065 for (; i < num_clips; clips++)
5066 fill_dc_dirty_rect(new_plane_state->plane,
5067 &dirty_rects[i], clips->x1,
5068 clips->y1, clips->x2 - clips->x1,
5069 clips->y2 - clips->y1, &i, false);
5070 } else if (fb_changed && !bb_changed) {
5071 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5072 new_plane_state->crtc_x,
5073 new_plane_state->crtc_y,
5074 new_plane_state->crtc_w,
5075 new_plane_state->crtc_h, &i, false);
5078 if (i > DC_MAX_DIRTY_RECTS)
5081 flip_addrs->dirty_rect_count = i;
5085 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5086 dm_crtc_state->base.mode.crtc_hdisplay,
5087 dm_crtc_state->base.mode.crtc_vdisplay,
5088 &flip_addrs->dirty_rect_count, true);
5091 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5092 const struct dm_connector_state *dm_state,
5093 struct dc_stream_state *stream)
5095 enum amdgpu_rmx_type rmx_type;
5097 struct rect src = { 0 }; /* viewport in composition space*/
5098 struct rect dst = { 0 }; /* stream addressable area */
5100 /* no mode. nothing to be done */
5104 /* Full screen scaling by default */
5105 src.width = mode->hdisplay;
5106 src.height = mode->vdisplay;
5107 dst.width = stream->timing.h_addressable;
5108 dst.height = stream->timing.v_addressable;
5111 rmx_type = dm_state->scaling;
5112 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5113 if (src.width * dst.height <
5114 src.height * dst.width) {
5115 /* height needs less upscaling/more downscaling */
5116 dst.width = src.width *
5117 dst.height / src.height;
5119 /* width needs less upscaling/more downscaling */
5120 dst.height = src.height *
5121 dst.width / src.width;
5123 } else if (rmx_type == RMX_CENTER) {
5127 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5128 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5130 if (dm_state->underscan_enable) {
5131 dst.x += dm_state->underscan_hborder / 2;
5132 dst.y += dm_state->underscan_vborder / 2;
5133 dst.width -= dm_state->underscan_hborder;
5134 dst.height -= dm_state->underscan_vborder;
5141 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5142 dst.x, dst.y, dst.width, dst.height);
5146 static enum dc_color_depth
5147 convert_color_depth_from_display_info(const struct drm_connector *connector,
5148 bool is_y420, int requested_bpc)
5155 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5156 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5158 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5160 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5163 bpc = (uint8_t)connector->display_info.bpc;
5164 /* Assume 8 bpc by default if no bpc is specified. */
5165 bpc = bpc ? bpc : 8;
5168 if (requested_bpc > 0) {
5170 * Cap display bpc based on the user requested value.
5172 * The value for state->max_bpc may not correctly updated
5173 * depending on when the connector gets added to the state
5174 * or if this was called outside of atomic check, so it
5175 * can't be used directly.
5177 bpc = min_t(u8, bpc, requested_bpc);
5179 /* Round down to the nearest even number. */
5180 bpc = bpc - (bpc & 1);
5186 * Temporary Work around, DRM doesn't parse color depth for
5187 * EDID revision before 1.4
5188 * TODO: Fix edid parsing
5190 return COLOR_DEPTH_888;
5192 return COLOR_DEPTH_666;
5194 return COLOR_DEPTH_888;
5196 return COLOR_DEPTH_101010;
5198 return COLOR_DEPTH_121212;
5200 return COLOR_DEPTH_141414;
5202 return COLOR_DEPTH_161616;
5204 return COLOR_DEPTH_UNDEFINED;
5208 static enum dc_aspect_ratio
5209 get_aspect_ratio(const struct drm_display_mode *mode_in)
5211 /* 1-1 mapping, since both enums follow the HDMI spec. */
5212 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5215 static enum dc_color_space
5216 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5218 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5220 switch (dc_crtc_timing->pixel_encoding) {
5221 case PIXEL_ENCODING_YCBCR422:
5222 case PIXEL_ENCODING_YCBCR444:
5223 case PIXEL_ENCODING_YCBCR420:
5226 * 27030khz is the separation point between HDTV and SDTV
5227 * according to HDMI spec, we use YCbCr709 and YCbCr601
5230 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5231 if (dc_crtc_timing->flags.Y_ONLY)
5233 COLOR_SPACE_YCBCR709_LIMITED;
5235 color_space = COLOR_SPACE_YCBCR709;
5237 if (dc_crtc_timing->flags.Y_ONLY)
5239 COLOR_SPACE_YCBCR601_LIMITED;
5241 color_space = COLOR_SPACE_YCBCR601;
5246 case PIXEL_ENCODING_RGB:
5247 color_space = COLOR_SPACE_SRGB;
5258 static bool adjust_colour_depth_from_display_info(
5259 struct dc_crtc_timing *timing_out,
5260 const struct drm_display_info *info)
5262 enum dc_color_depth depth = timing_out->display_color_depth;
5265 normalized_clk = timing_out->pix_clk_100hz / 10;
5266 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5267 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5268 normalized_clk /= 2;
5269 /* Adjusting pix clock following on HDMI spec based on colour depth */
5271 case COLOR_DEPTH_888:
5273 case COLOR_DEPTH_101010:
5274 normalized_clk = (normalized_clk * 30) / 24;
5276 case COLOR_DEPTH_121212:
5277 normalized_clk = (normalized_clk * 36) / 24;
5279 case COLOR_DEPTH_161616:
5280 normalized_clk = (normalized_clk * 48) / 24;
5283 /* The above depths are the only ones valid for HDMI. */
5286 if (normalized_clk <= info->max_tmds_clock) {
5287 timing_out->display_color_depth = depth;
5290 } while (--depth > COLOR_DEPTH_666);
5294 static void fill_stream_properties_from_drm_display_mode(
5295 struct dc_stream_state *stream,
5296 const struct drm_display_mode *mode_in,
5297 const struct drm_connector *connector,
5298 const struct drm_connector_state *connector_state,
5299 const struct dc_stream_state *old_stream,
5302 struct dc_crtc_timing *timing_out = &stream->timing;
5303 const struct drm_display_info *info = &connector->display_info;
5304 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5305 struct hdmi_vendor_infoframe hv_frame;
5306 struct hdmi_avi_infoframe avi_frame;
5308 memset(&hv_frame, 0, sizeof(hv_frame));
5309 memset(&avi_frame, 0, sizeof(avi_frame));
5311 timing_out->h_border_left = 0;
5312 timing_out->h_border_right = 0;
5313 timing_out->v_border_top = 0;
5314 timing_out->v_border_bottom = 0;
5315 /* TODO: un-hardcode */
5316 if (drm_mode_is_420_only(info, mode_in)
5317 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5318 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5319 else if (drm_mode_is_420_also(info, mode_in)
5320 && aconnector->force_yuv420_output)
5321 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5322 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5323 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5324 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5326 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5328 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5329 timing_out->display_color_depth = convert_color_depth_from_display_info(
5331 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5333 timing_out->scan_type = SCANNING_TYPE_NODATA;
5334 timing_out->hdmi_vic = 0;
5337 timing_out->vic = old_stream->timing.vic;
5338 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5339 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5341 timing_out->vic = drm_match_cea_mode(mode_in);
5342 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5343 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5344 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5345 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5348 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5349 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5350 timing_out->vic = avi_frame.video_code;
5351 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5352 timing_out->hdmi_vic = hv_frame.vic;
5355 if (is_freesync_video_mode(mode_in, aconnector)) {
5356 timing_out->h_addressable = mode_in->hdisplay;
5357 timing_out->h_total = mode_in->htotal;
5358 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5359 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5360 timing_out->v_total = mode_in->vtotal;
5361 timing_out->v_addressable = mode_in->vdisplay;
5362 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5363 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5364 timing_out->pix_clk_100hz = mode_in->clock * 10;
5366 timing_out->h_addressable = mode_in->crtc_hdisplay;
5367 timing_out->h_total = mode_in->crtc_htotal;
5368 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5369 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5370 timing_out->v_total = mode_in->crtc_vtotal;
5371 timing_out->v_addressable = mode_in->crtc_vdisplay;
5372 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5373 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5374 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5377 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5379 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5380 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5381 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5382 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5383 drm_mode_is_420_also(info, mode_in) &&
5384 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5385 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5386 adjust_colour_depth_from_display_info(timing_out, info);
5390 stream->output_color_space = get_output_color_space(timing_out);
5393 static void fill_audio_info(struct audio_info *audio_info,
5394 const struct drm_connector *drm_connector,
5395 const struct dc_sink *dc_sink)
5398 int cea_revision = 0;
5399 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5401 audio_info->manufacture_id = edid_caps->manufacturer_id;
5402 audio_info->product_id = edid_caps->product_id;
5404 cea_revision = drm_connector->display_info.cea_rev;
5406 strscpy(audio_info->display_name,
5407 edid_caps->display_name,
5408 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5410 if (cea_revision >= 3) {
5411 audio_info->mode_count = edid_caps->audio_mode_count;
5413 for (i = 0; i < audio_info->mode_count; ++i) {
5414 audio_info->modes[i].format_code =
5415 (enum audio_format_code)
5416 (edid_caps->audio_modes[i].format_code);
5417 audio_info->modes[i].channel_count =
5418 edid_caps->audio_modes[i].channel_count;
5419 audio_info->modes[i].sample_rates.all =
5420 edid_caps->audio_modes[i].sample_rate;
5421 audio_info->modes[i].sample_size =
5422 edid_caps->audio_modes[i].sample_size;
5426 audio_info->flags.all = edid_caps->speaker_flags;
5428 /* TODO: We only check for the progressive mode, check for interlace mode too */
5429 if (drm_connector->latency_present[0]) {
5430 audio_info->video_latency = drm_connector->video_latency[0];
5431 audio_info->audio_latency = drm_connector->audio_latency[0];
5434 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5439 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5440 struct drm_display_mode *dst_mode)
5442 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5443 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5444 dst_mode->crtc_clock = src_mode->crtc_clock;
5445 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5446 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5447 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5448 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5449 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5450 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5451 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5452 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5453 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5454 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5455 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5459 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5460 const struct drm_display_mode *native_mode,
5463 if (scale_enabled) {
5464 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5465 } else if (native_mode->clock == drm_mode->clock &&
5466 native_mode->htotal == drm_mode->htotal &&
5467 native_mode->vtotal == drm_mode->vtotal) {
5468 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5470 /* no scaling nor amdgpu inserted, no need to patch */
5474 static struct dc_sink *
5475 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5477 struct dc_sink_init_data sink_init_data = { 0 };
5478 struct dc_sink *sink = NULL;
5479 sink_init_data.link = aconnector->dc_link;
5480 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5482 sink = dc_sink_create(&sink_init_data);
5484 DRM_ERROR("Failed to create sink!\n");
5487 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5492 static void set_multisync_trigger_params(
5493 struct dc_stream_state *stream)
5495 struct dc_stream_state *master = NULL;
5497 if (stream->triggered_crtc_reset.enabled) {
5498 master = stream->triggered_crtc_reset.event_source;
5499 stream->triggered_crtc_reset.event =
5500 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5501 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5502 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5506 static void set_master_stream(struct dc_stream_state *stream_set[],
5509 int j, highest_rfr = 0, master_stream = 0;
5511 for (j = 0; j < stream_count; j++) {
5512 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5513 int refresh_rate = 0;
5515 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5516 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5517 if (refresh_rate > highest_rfr) {
5518 highest_rfr = refresh_rate;
5523 for (j = 0; j < stream_count; j++) {
5525 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5529 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5532 struct dc_stream_state *stream;
5534 if (context->stream_count < 2)
5536 for (i = 0; i < context->stream_count ; i++) {
5537 if (!context->streams[i])
5540 * TODO: add a function to read AMD VSDB bits and set
5541 * crtc_sync_master.multi_sync_enabled flag
5542 * For now it's set to false
5546 set_master_stream(context->streams, context->stream_count);
5548 for (i = 0; i < context->stream_count ; i++) {
5549 stream = context->streams[i];
5554 set_multisync_trigger_params(stream);
5559 * DOC: FreeSync Video
5561 * When a userspace application wants to play a video, the content follows a
5562 * standard format definition that usually specifies the FPS for that format.
5563 * The below list illustrates some video format and the expected FPS,
5566 * - TV/NTSC (23.976 FPS)
5569 * - TV/NTSC (29.97 FPS)
5570 * - TV/NTSC (30 FPS)
5571 * - Cinema HFR (48 FPS)
5573 * - Commonly used (60 FPS)
5574 * - Multiples of 24 (48,72,96 FPS)
5576 * The list of standards video format is not huge and can be added to the
5577 * connector modeset list beforehand. With that, userspace can leverage
5578 * FreeSync to extends the front porch in order to attain the target refresh
5579 * rate. Such a switch will happen seamlessly, without screen blanking or
5580 * reprogramming of the output in any other way. If the userspace requests a
5581 * modesetting change compatible with FreeSync modes that only differ in the
5582 * refresh rate, DC will skip the full update and avoid blink during the
5583 * transition. For example, the video player can change the modesetting from
5584 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5585 * causing any display blink. This same concept can be applied to a mode
5588 static struct drm_display_mode *
5589 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5590 bool use_probed_modes)
5592 struct drm_display_mode *m, *m_pref = NULL;
5593 u16 current_refresh, highest_refresh;
5594 struct list_head *list_head = use_probed_modes ?
5595 &aconnector->base.probed_modes :
5596 &aconnector->base.modes;
5598 if (aconnector->freesync_vid_base.clock != 0)
5599 return &aconnector->freesync_vid_base;
5601 /* Find the preferred mode */
5602 list_for_each_entry (m, list_head, head) {
5603 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5610 /* Probably an EDID with no preferred mode. Fallback to first entry */
5611 m_pref = list_first_entry_or_null(
5612 &aconnector->base.modes, struct drm_display_mode, head);
5614 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5619 highest_refresh = drm_mode_vrefresh(m_pref);
5622 * Find the mode with highest refresh rate with same resolution.
5623 * For some monitors, preferred mode is not the mode with highest
5624 * supported refresh rate.
5626 list_for_each_entry (m, list_head, head) {
5627 current_refresh = drm_mode_vrefresh(m);
5629 if (m->hdisplay == m_pref->hdisplay &&
5630 m->vdisplay == m_pref->vdisplay &&
5631 highest_refresh < current_refresh) {
5632 highest_refresh = current_refresh;
5637 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5641 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5642 struct amdgpu_dm_connector *aconnector)
5644 struct drm_display_mode *high_mode;
5647 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5648 if (!high_mode || !mode)
5651 timing_diff = high_mode->vtotal - mode->vtotal;
5653 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5654 high_mode->hdisplay != mode->hdisplay ||
5655 high_mode->vdisplay != mode->vdisplay ||
5656 high_mode->hsync_start != mode->hsync_start ||
5657 high_mode->hsync_end != mode->hsync_end ||
5658 high_mode->htotal != mode->htotal ||
5659 high_mode->hskew != mode->hskew ||
5660 high_mode->vscan != mode->vscan ||
5661 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5662 high_mode->vsync_end - mode->vsync_end != timing_diff)
5668 #if defined(CONFIG_DRM_AMD_DC_DCN)
5669 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5670 struct dc_sink *sink, struct dc_stream_state *stream,
5671 struct dsc_dec_dpcd_caps *dsc_caps)
5673 stream->timing.flags.DSC = 0;
5674 dsc_caps->is_dsc_supported = false;
5676 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5677 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5678 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5679 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5680 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5681 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5682 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5688 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5689 struct dc_sink *sink, struct dc_stream_state *stream,
5690 struct dsc_dec_dpcd_caps *dsc_caps,
5691 uint32_t max_dsc_target_bpp_limit_override)
5693 const struct dc_link_settings *verified_link_cap = NULL;
5694 u32 link_bw_in_kbps;
5695 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5696 struct dc *dc = sink->ctx->dc;
5697 struct dc_dsc_bw_range bw_range = {0};
5698 struct dc_dsc_config dsc_cfg = {0};
5700 verified_link_cap = dc_link_get_link_cap(stream->link);
5701 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5702 edp_min_bpp_x16 = 8 * 16;
5703 edp_max_bpp_x16 = 8 * 16;
5705 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5706 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5708 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5709 edp_min_bpp_x16 = edp_max_bpp_x16;
5711 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5712 dc->debug.dsc_min_slice_height_override,
5713 edp_min_bpp_x16, edp_max_bpp_x16,
5718 if (bw_range.max_kbps < link_bw_in_kbps) {
5719 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5721 dc->debug.dsc_min_slice_height_override,
5722 max_dsc_target_bpp_limit_override,
5726 stream->timing.dsc_cfg = dsc_cfg;
5727 stream->timing.flags.DSC = 1;
5728 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5734 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5736 dc->debug.dsc_min_slice_height_override,
5737 max_dsc_target_bpp_limit_override,
5741 stream->timing.dsc_cfg = dsc_cfg;
5742 stream->timing.flags.DSC = 1;
5747 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5748 struct dc_sink *sink, struct dc_stream_state *stream,
5749 struct dsc_dec_dpcd_caps *dsc_caps)
5751 struct drm_connector *drm_connector = &aconnector->base;
5752 u32 link_bandwidth_kbps;
5753 struct dc *dc = sink->ctx->dc;
5754 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5755 u32 dsc_max_supported_bw_in_kbps;
5756 u32 max_dsc_target_bpp_limit_override =
5757 drm_connector->display_info.max_dsc_bpp;
5759 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5760 dc_link_get_link_cap(aconnector->dc_link));
5762 /* Set DSC policy according to dsc_clock_en */
5763 dc_dsc_policy_set_enable_dsc_when_not_needed(
5764 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5766 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5767 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5768 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5770 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5772 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5773 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5774 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5776 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5777 max_dsc_target_bpp_limit_override,
5778 link_bandwidth_kbps,
5780 &stream->timing.dsc_cfg)) {
5781 stream->timing.flags.DSC = 1;
5782 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5784 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5785 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5786 max_supported_bw_in_kbps = link_bandwidth_kbps;
5787 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5789 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5790 max_supported_bw_in_kbps > 0 &&
5791 dsc_max_supported_bw_in_kbps > 0)
5792 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5794 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5795 max_dsc_target_bpp_limit_override,
5796 dsc_max_supported_bw_in_kbps,
5798 &stream->timing.dsc_cfg)) {
5799 stream->timing.flags.DSC = 1;
5800 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5801 __func__, drm_connector->name);
5806 /* Overwrite the stream flag if DSC is enabled through debugfs */
5807 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5808 stream->timing.flags.DSC = 1;
5810 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5811 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5813 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5814 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5816 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5817 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5819 #endif /* CONFIG_DRM_AMD_DC_DCN */
5821 static struct dc_stream_state *
5822 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5823 const struct drm_display_mode *drm_mode,
5824 const struct dm_connector_state *dm_state,
5825 const struct dc_stream_state *old_stream,
5828 struct drm_display_mode *preferred_mode = NULL;
5829 struct drm_connector *drm_connector;
5830 const struct drm_connector_state *con_state =
5831 dm_state ? &dm_state->base : NULL;
5832 struct dc_stream_state *stream = NULL;
5833 struct drm_display_mode mode;
5834 struct drm_display_mode saved_mode;
5835 struct drm_display_mode *freesync_mode = NULL;
5836 bool native_mode_found = false;
5837 bool recalculate_timing = false;
5838 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5840 int preferred_refresh = 0;
5841 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5842 #if defined(CONFIG_DRM_AMD_DC_DCN)
5843 struct dsc_dec_dpcd_caps dsc_caps;
5846 struct dc_sink *sink = NULL;
5848 drm_mode_init(&mode, drm_mode);
5849 memset(&saved_mode, 0, sizeof(saved_mode));
5851 if (aconnector == NULL) {
5852 DRM_ERROR("aconnector is NULL!\n");
5856 drm_connector = &aconnector->base;
5858 if (!aconnector->dc_sink) {
5859 sink = create_fake_sink(aconnector);
5863 sink = aconnector->dc_sink;
5864 dc_sink_retain(sink);
5867 stream = dc_create_stream_for_sink(sink);
5869 if (stream == NULL) {
5870 DRM_ERROR("Failed to create stream for sink!\n");
5874 stream->dm_stream_context = aconnector;
5876 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5877 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5879 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5880 /* Search for preferred mode */
5881 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5882 native_mode_found = true;
5886 if (!native_mode_found)
5887 preferred_mode = list_first_entry_or_null(
5888 &aconnector->base.modes,
5889 struct drm_display_mode,
5892 mode_refresh = drm_mode_vrefresh(&mode);
5894 if (preferred_mode == NULL) {
5896 * This may not be an error, the use case is when we have no
5897 * usermode calls to reset and set mode upon hotplug. In this
5898 * case, we call set mode ourselves to restore the previous mode
5899 * and the modelist may not be filled in in time.
5901 DRM_DEBUG_DRIVER("No preferred mode found\n");
5903 recalculate_timing = amdgpu_freesync_vid_mode &&
5904 is_freesync_video_mode(&mode, aconnector);
5905 if (recalculate_timing) {
5906 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5907 drm_mode_copy(&saved_mode, &mode);
5908 drm_mode_copy(&mode, freesync_mode);
5910 decide_crtc_timing_for_drm_display_mode(
5911 &mode, preferred_mode, scale);
5913 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5917 if (recalculate_timing)
5918 drm_mode_set_crtcinfo(&saved_mode, 0);
5920 drm_mode_set_crtcinfo(&mode, 0);
5923 * If scaling is enabled and refresh rate didn't change
5924 * we copy the vic and polarities of the old timings
5926 if (!scale || mode_refresh != preferred_refresh)
5927 fill_stream_properties_from_drm_display_mode(
5928 stream, &mode, &aconnector->base, con_state, NULL,
5931 fill_stream_properties_from_drm_display_mode(
5932 stream, &mode, &aconnector->base, con_state, old_stream,
5935 if (aconnector->timing_changed) {
5936 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
5938 stream->timing.display_color_depth,
5939 aconnector->timing_requested->display_color_depth);
5940 stream->timing = *aconnector->timing_requested;
5943 #if defined(CONFIG_DRM_AMD_DC_DCN)
5944 /* SST DSC determination policy */
5945 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5946 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5947 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
5950 update_stream_scaling_settings(&mode, dm_state, stream);
5953 &stream->audio_info,
5957 update_stream_signal(stream, sink);
5959 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5960 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5962 if (stream->link->psr_settings.psr_feature_enabled) {
5964 // should decide stream support vsc sdp colorimetry capability
5965 // before building vsc info packet
5967 stream->use_vsc_sdp_for_colorimetry = false;
5968 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5969 stream->use_vsc_sdp_for_colorimetry =
5970 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5972 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5973 stream->use_vsc_sdp_for_colorimetry = true;
5975 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
5976 tf = TRANSFER_FUNC_GAMMA_22;
5977 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
5978 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5982 dc_sink_release(sink);
5987 static enum drm_connector_status
5988 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5991 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5995 * 1. This interface is NOT called in context of HPD irq.
5996 * 2. This interface *is called* in context of user-mode ioctl. Which
5997 * makes it a bad place for *any* MST-related activity.
6000 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6001 !aconnector->fake_enable)
6002 connected = (aconnector->dc_sink != NULL);
6004 connected = (aconnector->base.force == DRM_FORCE_ON ||
6005 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6007 update_subconnector_property(aconnector);
6009 return (connected ? connector_status_connected :
6010 connector_status_disconnected);
6013 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6014 struct drm_connector_state *connector_state,
6015 struct drm_property *property,
6018 struct drm_device *dev = connector->dev;
6019 struct amdgpu_device *adev = drm_to_adev(dev);
6020 struct dm_connector_state *dm_old_state =
6021 to_dm_connector_state(connector->state);
6022 struct dm_connector_state *dm_new_state =
6023 to_dm_connector_state(connector_state);
6027 if (property == dev->mode_config.scaling_mode_property) {
6028 enum amdgpu_rmx_type rmx_type;
6031 case DRM_MODE_SCALE_CENTER:
6032 rmx_type = RMX_CENTER;
6034 case DRM_MODE_SCALE_ASPECT:
6035 rmx_type = RMX_ASPECT;
6037 case DRM_MODE_SCALE_FULLSCREEN:
6038 rmx_type = RMX_FULL;
6040 case DRM_MODE_SCALE_NONE:
6046 if (dm_old_state->scaling == rmx_type)
6049 dm_new_state->scaling = rmx_type;
6051 } else if (property == adev->mode_info.underscan_hborder_property) {
6052 dm_new_state->underscan_hborder = val;
6054 } else if (property == adev->mode_info.underscan_vborder_property) {
6055 dm_new_state->underscan_vborder = val;
6057 } else if (property == adev->mode_info.underscan_property) {
6058 dm_new_state->underscan_enable = val;
6060 } else if (property == adev->mode_info.abm_level_property) {
6061 dm_new_state->abm_level = val;
6068 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6069 const struct drm_connector_state *state,
6070 struct drm_property *property,
6073 struct drm_device *dev = connector->dev;
6074 struct amdgpu_device *adev = drm_to_adev(dev);
6075 struct dm_connector_state *dm_state =
6076 to_dm_connector_state(state);
6079 if (property == dev->mode_config.scaling_mode_property) {
6080 switch (dm_state->scaling) {
6082 *val = DRM_MODE_SCALE_CENTER;
6085 *val = DRM_MODE_SCALE_ASPECT;
6088 *val = DRM_MODE_SCALE_FULLSCREEN;
6092 *val = DRM_MODE_SCALE_NONE;
6096 } else if (property == adev->mode_info.underscan_hborder_property) {
6097 *val = dm_state->underscan_hborder;
6099 } else if (property == adev->mode_info.underscan_vborder_property) {
6100 *val = dm_state->underscan_vborder;
6102 } else if (property == adev->mode_info.underscan_property) {
6103 *val = dm_state->underscan_enable;
6105 } else if (property == adev->mode_info.abm_level_property) {
6106 *val = dm_state->abm_level;
6113 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6115 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6117 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6120 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6122 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6123 const struct dc_link *link = aconnector->dc_link;
6124 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6125 struct amdgpu_display_manager *dm = &adev->dm;
6129 * Call only if mst_mgr was initialized before since it's not done
6130 * for all connector types.
6132 if (aconnector->mst_mgr.dev)
6133 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
6136 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
6137 for (i = 0; i < dm->num_of_edps; i++) {
6138 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6139 backlight_device_unregister(dm->backlight_dev[i]);
6140 dm->backlight_dev[i] = NULL;
6145 if (aconnector->dc_em_sink)
6146 dc_sink_release(aconnector->dc_em_sink);
6147 aconnector->dc_em_sink = NULL;
6148 if (aconnector->dc_sink)
6149 dc_sink_release(aconnector->dc_sink);
6150 aconnector->dc_sink = NULL;
6152 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6153 drm_connector_unregister(connector);
6154 drm_connector_cleanup(connector);
6155 if (aconnector->i2c) {
6156 i2c_del_adapter(&aconnector->i2c->base);
6157 kfree(aconnector->i2c);
6159 kfree(aconnector->dm_dp_aux.aux.name);
6164 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6166 struct dm_connector_state *state =
6167 to_dm_connector_state(connector->state);
6169 if (connector->state)
6170 __drm_atomic_helper_connector_destroy_state(connector->state);
6174 state = kzalloc(sizeof(*state), GFP_KERNEL);
6177 state->scaling = RMX_OFF;
6178 state->underscan_enable = false;
6179 state->underscan_hborder = 0;
6180 state->underscan_vborder = 0;
6181 state->base.max_requested_bpc = 8;
6182 state->vcpi_slots = 0;
6185 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6186 state->abm_level = amdgpu_dm_abm_level;
6188 __drm_atomic_helper_connector_reset(connector, &state->base);
6192 struct drm_connector_state *
6193 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6195 struct dm_connector_state *state =
6196 to_dm_connector_state(connector->state);
6198 struct dm_connector_state *new_state =
6199 kmemdup(state, sizeof(*state), GFP_KERNEL);
6204 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6206 new_state->freesync_capable = state->freesync_capable;
6207 new_state->abm_level = state->abm_level;
6208 new_state->scaling = state->scaling;
6209 new_state->underscan_enable = state->underscan_enable;
6210 new_state->underscan_hborder = state->underscan_hborder;
6211 new_state->underscan_vborder = state->underscan_vborder;
6212 new_state->vcpi_slots = state->vcpi_slots;
6213 new_state->pbn = state->pbn;
6214 return &new_state->base;
6218 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6220 struct amdgpu_dm_connector *amdgpu_dm_connector =
6221 to_amdgpu_dm_connector(connector);
6224 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6225 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6226 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6227 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6232 #if defined(CONFIG_DEBUG_FS)
6233 connector_debugfs_init(amdgpu_dm_connector);
6239 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6240 .reset = amdgpu_dm_connector_funcs_reset,
6241 .detect = amdgpu_dm_connector_detect,
6242 .fill_modes = drm_helper_probe_single_connector_modes,
6243 .destroy = amdgpu_dm_connector_destroy,
6244 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6245 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6246 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6247 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6248 .late_register = amdgpu_dm_connector_late_register,
6249 .early_unregister = amdgpu_dm_connector_unregister
6252 static int get_modes(struct drm_connector *connector)
6254 return amdgpu_dm_connector_get_modes(connector);
6257 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6259 struct dc_sink_init_data init_params = {
6260 .link = aconnector->dc_link,
6261 .sink_signal = SIGNAL_TYPE_VIRTUAL
6265 if (!aconnector->base.edid_blob_ptr) {
6266 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6267 aconnector->base.name);
6269 aconnector->base.force = DRM_FORCE_OFF;
6273 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6275 aconnector->edid = edid;
6277 aconnector->dc_em_sink = dc_link_add_remote_sink(
6278 aconnector->dc_link,
6280 (edid->extensions + 1) * EDID_LENGTH,
6283 if (aconnector->base.force == DRM_FORCE_ON) {
6284 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6285 aconnector->dc_link->local_sink :
6286 aconnector->dc_em_sink;
6287 dc_sink_retain(aconnector->dc_sink);
6291 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6293 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6296 * In case of headless boot with force on for DP managed connector
6297 * Those settings have to be != 0 to get initial modeset
6299 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6300 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6301 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6304 create_eml_sink(aconnector);
6307 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6308 struct dc_stream_state *stream)
6310 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6311 struct dc_plane_state *dc_plane_state = NULL;
6312 struct dc_state *dc_state = NULL;
6317 dc_plane_state = dc_create_plane_state(dc);
6318 if (!dc_plane_state)
6321 dc_state = dc_create_state(dc);
6325 /* populate stream to plane */
6326 dc_plane_state->src_rect.height = stream->src.height;
6327 dc_plane_state->src_rect.width = stream->src.width;
6328 dc_plane_state->dst_rect.height = stream->src.height;
6329 dc_plane_state->dst_rect.width = stream->src.width;
6330 dc_plane_state->clip_rect.height = stream->src.height;
6331 dc_plane_state->clip_rect.width = stream->src.width;
6332 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6333 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6334 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6335 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6336 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6337 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6338 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6339 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6340 dc_plane_state->rotation = ROTATION_ANGLE_0;
6341 dc_plane_state->is_tiling_rotated = false;
6342 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6344 dc_result = dc_validate_stream(dc, stream);
6345 if (dc_result == DC_OK)
6346 dc_result = dc_validate_plane(dc, dc_plane_state);
6348 if (dc_result == DC_OK)
6349 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6351 if (dc_result == DC_OK && !dc_add_plane_to_context(
6356 dc_result = DC_FAIL_ATTACH_SURFACES;
6358 if (dc_result == DC_OK)
6359 dc_result = dc_validate_global_state(dc, dc_state, true);
6363 dc_release_state(dc_state);
6366 dc_plane_state_release(dc_plane_state);
6371 struct dc_stream_state *
6372 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6373 const struct drm_display_mode *drm_mode,
6374 const struct dm_connector_state *dm_state,
6375 const struct dc_stream_state *old_stream)
6377 struct drm_connector *connector = &aconnector->base;
6378 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6379 struct dc_stream_state *stream;
6380 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6381 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6382 enum dc_status dc_result = DC_OK;
6385 stream = create_stream_for_sink(aconnector, drm_mode,
6386 dm_state, old_stream,
6388 if (stream == NULL) {
6389 DRM_ERROR("Failed to create stream for sink!\n");
6393 dc_result = dc_validate_stream(adev->dm.dc, stream);
6394 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6395 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6397 if (dc_result == DC_OK)
6398 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6400 if (dc_result != DC_OK) {
6401 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6406 dc_status_to_str(dc_result));
6408 dc_stream_release(stream);
6410 requested_bpc -= 2; /* lower bpc to retry validation */
6413 } while (stream == NULL && requested_bpc >= 6);
6415 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6416 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6418 aconnector->force_yuv420_output = true;
6419 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6420 dm_state, old_stream);
6421 aconnector->force_yuv420_output = false;
6427 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6428 struct drm_display_mode *mode)
6430 int result = MODE_ERROR;
6431 struct dc_sink *dc_sink;
6432 /* TODO: Unhardcode stream count */
6433 struct dc_stream_state *stream;
6434 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6436 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6437 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6441 * Only run this the first time mode_valid is called to initilialize
6444 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6445 !aconnector->dc_em_sink)
6446 handle_edid_mgmt(aconnector);
6448 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6450 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6451 aconnector->base.force != DRM_FORCE_ON) {
6452 DRM_ERROR("dc_sink is NULL!\n");
6456 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6458 dc_stream_release(stream);
6463 /* TODO: error handling*/
6467 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6468 struct dc_info_packet *out)
6470 struct hdmi_drm_infoframe frame;
6471 unsigned char buf[30]; /* 26 + 4 */
6475 memset(out, 0, sizeof(*out));
6477 if (!state->hdr_output_metadata)
6480 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6484 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6488 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6492 /* Prepare the infopacket for DC. */
6493 switch (state->connector->connector_type) {
6494 case DRM_MODE_CONNECTOR_HDMIA:
6495 out->hb0 = 0x87; /* type */
6496 out->hb1 = 0x01; /* version */
6497 out->hb2 = 0x1A; /* length */
6498 out->sb[0] = buf[3]; /* checksum */
6502 case DRM_MODE_CONNECTOR_DisplayPort:
6503 case DRM_MODE_CONNECTOR_eDP:
6504 out->hb0 = 0x00; /* sdp id, zero */
6505 out->hb1 = 0x87; /* type */
6506 out->hb2 = 0x1D; /* payload len - 1 */
6507 out->hb3 = (0x13 << 2); /* sdp version */
6508 out->sb[0] = 0x01; /* version */
6509 out->sb[1] = 0x1A; /* length */
6517 memcpy(&out->sb[i], &buf[4], 26);
6520 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6521 sizeof(out->sb), false);
6527 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6528 struct drm_atomic_state *state)
6530 struct drm_connector_state *new_con_state =
6531 drm_atomic_get_new_connector_state(state, conn);
6532 struct drm_connector_state *old_con_state =
6533 drm_atomic_get_old_connector_state(state, conn);
6534 struct drm_crtc *crtc = new_con_state->crtc;
6535 struct drm_crtc_state *new_crtc_state;
6536 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6539 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6541 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6542 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6550 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6551 struct dc_info_packet hdr_infopacket;
6553 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6557 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6558 if (IS_ERR(new_crtc_state))
6559 return PTR_ERR(new_crtc_state);
6562 * DC considers the stream backends changed if the
6563 * static metadata changes. Forcing the modeset also
6564 * gives a simple way for userspace to switch from
6565 * 8bpc to 10bpc when setting the metadata to enter
6568 * Changing the static metadata after it's been
6569 * set is permissible, however. So only force a
6570 * modeset if we're entering or exiting HDR.
6572 new_crtc_state->mode_changed =
6573 !old_con_state->hdr_output_metadata ||
6574 !new_con_state->hdr_output_metadata;
6580 static const struct drm_connector_helper_funcs
6581 amdgpu_dm_connector_helper_funcs = {
6583 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6584 * modes will be filtered by drm_mode_validate_size(), and those modes
6585 * are missing after user start lightdm. So we need to renew modes list.
6586 * in get_modes call back, not just return the modes count
6588 .get_modes = get_modes,
6589 .mode_valid = amdgpu_dm_connector_mode_valid,
6590 .atomic_check = amdgpu_dm_connector_atomic_check,
6593 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6598 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6600 switch (display_color_depth) {
6601 case COLOR_DEPTH_666:
6603 case COLOR_DEPTH_888:
6605 case COLOR_DEPTH_101010:
6607 case COLOR_DEPTH_121212:
6609 case COLOR_DEPTH_141414:
6611 case COLOR_DEPTH_161616:
6619 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6620 struct drm_crtc_state *crtc_state,
6621 struct drm_connector_state *conn_state)
6623 struct drm_atomic_state *state = crtc_state->state;
6624 struct drm_connector *connector = conn_state->connector;
6625 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6626 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6627 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6628 struct drm_dp_mst_topology_mgr *mst_mgr;
6629 struct drm_dp_mst_port *mst_port;
6630 struct drm_dp_mst_topology_state *mst_state;
6631 enum dc_color_depth color_depth;
6633 bool is_y420 = false;
6635 if (!aconnector->mst_output_port || !aconnector->dc_sink)
6638 mst_port = aconnector->mst_output_port;
6639 mst_mgr = &aconnector->mst_root->mst_mgr;
6641 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6644 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6645 if (IS_ERR(mst_state))
6646 return PTR_ERR(mst_state);
6648 if (!mst_state->pbn_div)
6649 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6651 if (!state->duplicated) {
6652 int max_bpc = conn_state->max_requested_bpc;
6653 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6654 aconnector->force_yuv420_output;
6655 color_depth = convert_color_depth_from_display_info(connector,
6658 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6659 clock = adjusted_mode->clock;
6660 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6663 dm_new_connector_state->vcpi_slots =
6664 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6665 dm_new_connector_state->pbn);
6666 if (dm_new_connector_state->vcpi_slots < 0) {
6667 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6668 return dm_new_connector_state->vcpi_slots;
6673 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6674 .disable = dm_encoder_helper_disable,
6675 .atomic_check = dm_encoder_helper_atomic_check
6678 #if defined(CONFIG_DRM_AMD_DC_DCN)
6679 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6680 struct dc_state *dc_state,
6681 struct dsc_mst_fairness_vars *vars)
6683 struct dc_stream_state *stream = NULL;
6684 struct drm_connector *connector;
6685 struct drm_connector_state *new_con_state;
6686 struct amdgpu_dm_connector *aconnector;
6687 struct dm_connector_state *dm_conn_state;
6689 int vcpi, pbn_div, pbn, slot_num = 0;
6691 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6693 aconnector = to_amdgpu_dm_connector(connector);
6695 if (!aconnector->mst_output_port)
6698 if (!new_con_state || !new_con_state->crtc)
6701 dm_conn_state = to_dm_connector_state(new_con_state);
6703 for (j = 0; j < dc_state->stream_count; j++) {
6704 stream = dc_state->streams[j];
6708 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6717 pbn_div = dm_mst_get_pbn_divider(stream->link);
6718 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6719 for (j = 0; j < dc_state->stream_count; j++) {
6720 if (vars[j].aconnector == aconnector) {
6726 if (j == dc_state->stream_count)
6729 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6731 if (stream->timing.flags.DSC != 1) {
6732 dm_conn_state->pbn = pbn;
6733 dm_conn_state->vcpi_slots = slot_num;
6735 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6736 dm_conn_state->pbn, false);
6743 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6747 dm_conn_state->pbn = pbn;
6748 dm_conn_state->vcpi_slots = vcpi;
6754 static int to_drm_connector_type(enum signal_type st)
6757 case SIGNAL_TYPE_HDMI_TYPE_A:
6758 return DRM_MODE_CONNECTOR_HDMIA;
6759 case SIGNAL_TYPE_EDP:
6760 return DRM_MODE_CONNECTOR_eDP;
6761 case SIGNAL_TYPE_LVDS:
6762 return DRM_MODE_CONNECTOR_LVDS;
6763 case SIGNAL_TYPE_RGB:
6764 return DRM_MODE_CONNECTOR_VGA;
6765 case SIGNAL_TYPE_DISPLAY_PORT:
6766 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6767 return DRM_MODE_CONNECTOR_DisplayPort;
6768 case SIGNAL_TYPE_DVI_DUAL_LINK:
6769 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6770 return DRM_MODE_CONNECTOR_DVID;
6771 case SIGNAL_TYPE_VIRTUAL:
6772 return DRM_MODE_CONNECTOR_VIRTUAL;
6775 return DRM_MODE_CONNECTOR_Unknown;
6779 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6781 struct drm_encoder *encoder;
6783 /* There is only one encoder per connector */
6784 drm_connector_for_each_possible_encoder(connector, encoder)
6790 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6792 struct drm_encoder *encoder;
6793 struct amdgpu_encoder *amdgpu_encoder;
6795 encoder = amdgpu_dm_connector_to_encoder(connector);
6797 if (encoder == NULL)
6800 amdgpu_encoder = to_amdgpu_encoder(encoder);
6802 amdgpu_encoder->native_mode.clock = 0;
6804 if (!list_empty(&connector->probed_modes)) {
6805 struct drm_display_mode *preferred_mode = NULL;
6807 list_for_each_entry(preferred_mode,
6808 &connector->probed_modes,
6810 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6811 amdgpu_encoder->native_mode = *preferred_mode;
6819 static struct drm_display_mode *
6820 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6822 int hdisplay, int vdisplay)
6824 struct drm_device *dev = encoder->dev;
6825 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6826 struct drm_display_mode *mode = NULL;
6827 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6829 mode = drm_mode_duplicate(dev, native_mode);
6834 mode->hdisplay = hdisplay;
6835 mode->vdisplay = vdisplay;
6836 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6837 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6843 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6844 struct drm_connector *connector)
6846 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6847 struct drm_display_mode *mode = NULL;
6848 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6849 struct amdgpu_dm_connector *amdgpu_dm_connector =
6850 to_amdgpu_dm_connector(connector);
6854 char name[DRM_DISPLAY_MODE_LEN];
6857 } common_modes[] = {
6858 { "640x480", 640, 480},
6859 { "800x600", 800, 600},
6860 { "1024x768", 1024, 768},
6861 { "1280x720", 1280, 720},
6862 { "1280x800", 1280, 800},
6863 {"1280x1024", 1280, 1024},
6864 { "1440x900", 1440, 900},
6865 {"1680x1050", 1680, 1050},
6866 {"1600x1200", 1600, 1200},
6867 {"1920x1080", 1920, 1080},
6868 {"1920x1200", 1920, 1200}
6871 n = ARRAY_SIZE(common_modes);
6873 for (i = 0; i < n; i++) {
6874 struct drm_display_mode *curmode = NULL;
6875 bool mode_existed = false;
6877 if (common_modes[i].w > native_mode->hdisplay ||
6878 common_modes[i].h > native_mode->vdisplay ||
6879 (common_modes[i].w == native_mode->hdisplay &&
6880 common_modes[i].h == native_mode->vdisplay))
6883 list_for_each_entry(curmode, &connector->probed_modes, head) {
6884 if (common_modes[i].w == curmode->hdisplay &&
6885 common_modes[i].h == curmode->vdisplay) {
6886 mode_existed = true;
6894 mode = amdgpu_dm_create_common_mode(encoder,
6895 common_modes[i].name, common_modes[i].w,
6900 drm_mode_probed_add(connector, mode);
6901 amdgpu_dm_connector->num_modes++;
6905 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6907 struct drm_encoder *encoder;
6908 struct amdgpu_encoder *amdgpu_encoder;
6909 const struct drm_display_mode *native_mode;
6911 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6912 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6915 mutex_lock(&connector->dev->mode_config.mutex);
6916 amdgpu_dm_connector_get_modes(connector);
6917 mutex_unlock(&connector->dev->mode_config.mutex);
6919 encoder = amdgpu_dm_connector_to_encoder(connector);
6923 amdgpu_encoder = to_amdgpu_encoder(encoder);
6925 native_mode = &amdgpu_encoder->native_mode;
6926 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6929 drm_connector_set_panel_orientation_with_quirk(connector,
6930 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6931 native_mode->hdisplay,
6932 native_mode->vdisplay);
6935 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6938 struct amdgpu_dm_connector *amdgpu_dm_connector =
6939 to_amdgpu_dm_connector(connector);
6942 /* empty probed_modes */
6943 INIT_LIST_HEAD(&connector->probed_modes);
6944 amdgpu_dm_connector->num_modes =
6945 drm_add_edid_modes(connector, edid);
6947 /* sorting the probed modes before calling function
6948 * amdgpu_dm_get_native_mode() since EDID can have
6949 * more than one preferred mode. The modes that are
6950 * later in the probed mode list could be of higher
6951 * and preferred resolution. For example, 3840x2160
6952 * resolution in base EDID preferred timing and 4096x2160
6953 * preferred resolution in DID extension block later.
6955 drm_mode_sort(&connector->probed_modes);
6956 amdgpu_dm_get_native_mode(connector);
6958 /* Freesync capabilities are reset by calling
6959 * drm_add_edid_modes() and need to be
6962 amdgpu_dm_update_freesync_caps(connector, edid);
6964 amdgpu_dm_connector->num_modes = 0;
6968 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6969 struct drm_display_mode *mode)
6971 struct drm_display_mode *m;
6973 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6974 if (drm_mode_equal(m, mode))
6981 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6983 const struct drm_display_mode *m;
6984 struct drm_display_mode *new_mode;
6986 u32 new_modes_count = 0;
6988 /* Standard FPS values
6997 * 60 - Commonly used
6998 * 48,72,96,120 - Multiples of 24
7000 static const u32 common_rates[] = {
7001 23976, 24000, 25000, 29970, 30000,
7002 48000, 50000, 60000, 72000, 96000, 120000
7006 * Find mode with highest refresh rate with the same resolution
7007 * as the preferred mode. Some monitors report a preferred mode
7008 * with lower resolution than the highest refresh rate supported.
7011 m = get_highest_refresh_rate_mode(aconnector, true);
7015 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7016 u64 target_vtotal, target_vtotal_diff;
7019 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7022 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7023 common_rates[i] > aconnector->max_vfreq * 1000)
7026 num = (unsigned long long)m->clock * 1000 * 1000;
7027 den = common_rates[i] * (unsigned long long)m->htotal;
7028 target_vtotal = div_u64(num, den);
7029 target_vtotal_diff = target_vtotal - m->vtotal;
7031 /* Check for illegal modes */
7032 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7033 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7034 m->vtotal + target_vtotal_diff < m->vsync_end)
7037 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7041 new_mode->vtotal += (u16)target_vtotal_diff;
7042 new_mode->vsync_start += (u16)target_vtotal_diff;
7043 new_mode->vsync_end += (u16)target_vtotal_diff;
7044 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7045 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7047 if (!is_duplicate_mode(aconnector, new_mode)) {
7048 drm_mode_probed_add(&aconnector->base, new_mode);
7049 new_modes_count += 1;
7051 drm_mode_destroy(aconnector->base.dev, new_mode);
7054 return new_modes_count;
7057 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7060 struct amdgpu_dm_connector *amdgpu_dm_connector =
7061 to_amdgpu_dm_connector(connector);
7063 if (!(amdgpu_freesync_vid_mode && edid))
7066 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7067 amdgpu_dm_connector->num_modes +=
7068 add_fs_modes(amdgpu_dm_connector);
7071 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7073 struct amdgpu_dm_connector *amdgpu_dm_connector =
7074 to_amdgpu_dm_connector(connector);
7075 struct drm_encoder *encoder;
7076 struct edid *edid = amdgpu_dm_connector->edid;
7078 encoder = amdgpu_dm_connector_to_encoder(connector);
7080 if (!drm_edid_is_valid(edid)) {
7081 amdgpu_dm_connector->num_modes =
7082 drm_add_modes_noedid(connector, 640, 480);
7084 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7085 amdgpu_dm_connector_add_common_modes(encoder, connector);
7086 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7088 amdgpu_dm_fbc_init(connector);
7090 return amdgpu_dm_connector->num_modes;
7093 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7094 struct amdgpu_dm_connector *aconnector,
7096 struct dc_link *link,
7099 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7102 * Some of the properties below require access to state, like bpc.
7103 * Allocate some default initial connector state with our reset helper.
7105 if (aconnector->base.funcs->reset)
7106 aconnector->base.funcs->reset(&aconnector->base);
7108 aconnector->connector_id = link_index;
7109 aconnector->dc_link = link;
7110 aconnector->base.interlace_allowed = false;
7111 aconnector->base.doublescan_allowed = false;
7112 aconnector->base.stereo_allowed = false;
7113 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7114 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7115 aconnector->audio_inst = -1;
7116 mutex_init(&aconnector->hpd_lock);
7119 * configure support HPD hot plug connector_>polled default value is 0
7120 * which means HPD hot plug not supported
7122 switch (connector_type) {
7123 case DRM_MODE_CONNECTOR_HDMIA:
7124 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7125 aconnector->base.ycbcr_420_allowed =
7126 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7128 case DRM_MODE_CONNECTOR_DisplayPort:
7129 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7130 link->link_enc = link_enc_cfg_get_link_enc(link);
7131 ASSERT(link->link_enc);
7133 aconnector->base.ycbcr_420_allowed =
7134 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7136 case DRM_MODE_CONNECTOR_DVID:
7137 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7143 drm_object_attach_property(&aconnector->base.base,
7144 dm->ddev->mode_config.scaling_mode_property,
7145 DRM_MODE_SCALE_NONE);
7147 drm_object_attach_property(&aconnector->base.base,
7148 adev->mode_info.underscan_property,
7150 drm_object_attach_property(&aconnector->base.base,
7151 adev->mode_info.underscan_hborder_property,
7153 drm_object_attach_property(&aconnector->base.base,
7154 adev->mode_info.underscan_vborder_property,
7157 if (!aconnector->mst_root)
7158 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7160 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7161 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7162 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7164 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7165 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7166 drm_object_attach_property(&aconnector->base.base,
7167 adev->mode_info.abm_level_property, 0);
7170 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7171 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7172 connector_type == DRM_MODE_CONNECTOR_eDP) {
7173 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7175 if (!aconnector->mst_root)
7176 drm_connector_attach_vrr_capable_property(&aconnector->base);
7178 #ifdef CONFIG_DRM_AMD_DC_HDCP
7179 if (adev->dm.hdcp_workqueue)
7180 drm_connector_attach_content_protection_property(&aconnector->base, true);
7185 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7186 struct i2c_msg *msgs, int num)
7188 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7189 struct ddc_service *ddc_service = i2c->ddc_service;
7190 struct i2c_command cmd;
7194 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7199 cmd.number_of_payloads = num;
7200 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7203 for (i = 0; i < num; i++) {
7204 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7205 cmd.payloads[i].address = msgs[i].addr;
7206 cmd.payloads[i].length = msgs[i].len;
7207 cmd.payloads[i].data = msgs[i].buf;
7211 ddc_service->ctx->dc,
7212 ddc_service->link->link_index,
7216 kfree(cmd.payloads);
7220 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7222 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7225 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7226 .master_xfer = amdgpu_dm_i2c_xfer,
7227 .functionality = amdgpu_dm_i2c_func,
7230 static struct amdgpu_i2c_adapter *
7231 create_i2c(struct ddc_service *ddc_service,
7235 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7236 struct amdgpu_i2c_adapter *i2c;
7238 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7241 i2c->base.owner = THIS_MODULE;
7242 i2c->base.class = I2C_CLASS_DDC;
7243 i2c->base.dev.parent = &adev->pdev->dev;
7244 i2c->base.algo = &amdgpu_dm_i2c_algo;
7245 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7246 i2c_set_adapdata(&i2c->base, i2c);
7247 i2c->ddc_service = ddc_service;
7254 * Note: this function assumes that dc_link_detect() was called for the
7255 * dc_link which will be represented by this aconnector.
7257 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7258 struct amdgpu_dm_connector *aconnector,
7260 struct amdgpu_encoder *aencoder)
7264 struct dc *dc = dm->dc;
7265 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7266 struct amdgpu_i2c_adapter *i2c;
7268 link->priv = aconnector;
7270 DRM_DEBUG_DRIVER("%s()\n", __func__);
7272 i2c = create_i2c(link->ddc, link->link_index, &res);
7274 DRM_ERROR("Failed to create i2c adapter data\n");
7278 aconnector->i2c = i2c;
7279 res = i2c_add_adapter(&i2c->base);
7282 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7286 connector_type = to_drm_connector_type(link->connector_signal);
7288 res = drm_connector_init_with_ddc(
7291 &amdgpu_dm_connector_funcs,
7296 DRM_ERROR("connector_init failed\n");
7297 aconnector->connector_id = -1;
7301 drm_connector_helper_add(
7303 &amdgpu_dm_connector_helper_funcs);
7305 amdgpu_dm_connector_init_helper(
7312 drm_connector_attach_encoder(
7313 &aconnector->base, &aencoder->base);
7315 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7316 || connector_type == DRM_MODE_CONNECTOR_eDP)
7317 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7322 aconnector->i2c = NULL;
7327 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7329 switch (adev->mode_info.num_crtc) {
7346 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7347 struct amdgpu_encoder *aencoder,
7348 uint32_t link_index)
7350 struct amdgpu_device *adev = drm_to_adev(dev);
7352 int res = drm_encoder_init(dev,
7354 &amdgpu_dm_encoder_funcs,
7355 DRM_MODE_ENCODER_TMDS,
7358 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7361 aencoder->encoder_id = link_index;
7363 aencoder->encoder_id = -1;
7365 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7370 static void manage_dm_interrupts(struct amdgpu_device *adev,
7371 struct amdgpu_crtc *acrtc,
7375 * We have no guarantee that the frontend index maps to the same
7376 * backend index - some even map to more than one.
7378 * TODO: Use a different interrupt or check DC itself for the mapping.
7381 amdgpu_display_crtc_idx_to_irq_type(
7386 drm_crtc_vblank_on(&acrtc->base);
7389 &adev->pageflip_irq,
7391 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7398 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7406 &adev->pageflip_irq,
7408 drm_crtc_vblank_off(&acrtc->base);
7412 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7413 struct amdgpu_crtc *acrtc)
7416 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7419 * This reads the current state for the IRQ and force reapplies
7420 * the setting to hardware.
7422 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7426 is_scaling_state_different(const struct dm_connector_state *dm_state,
7427 const struct dm_connector_state *old_dm_state)
7429 if (dm_state->scaling != old_dm_state->scaling)
7431 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7432 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7434 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7435 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7437 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7438 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7443 #ifdef CONFIG_DRM_AMD_DC_HDCP
7444 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7445 struct drm_crtc_state *old_crtc_state,
7446 struct drm_connector_state *new_conn_state,
7447 struct drm_connector_state *old_conn_state,
7448 const struct drm_connector *connector,
7449 struct hdcp_workqueue *hdcp_w)
7451 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7452 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7454 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7455 connector->index, connector->status, connector->dpms);
7456 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7457 old_conn_state->content_protection, new_conn_state->content_protection);
7460 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7461 old_crtc_state->enable,
7462 old_crtc_state->active,
7463 old_crtc_state->mode_changed,
7464 old_crtc_state->active_changed,
7465 old_crtc_state->connectors_changed);
7468 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7469 new_crtc_state->enable,
7470 new_crtc_state->active,
7471 new_crtc_state->mode_changed,
7472 new_crtc_state->active_changed,
7473 new_crtc_state->connectors_changed);
7475 /* hdcp content type change */
7476 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7477 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7478 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7479 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7483 /* CP is being re enabled, ignore this */
7484 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7485 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7486 if (new_crtc_state && new_crtc_state->mode_changed) {
7487 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7488 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7491 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7492 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7496 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7498 * Handles: UNDESIRED -> ENABLED
7500 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7501 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7502 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7504 /* Stream removed and re-enabled
7506 * Can sometimes overlap with the HPD case,
7507 * thus set update_hdcp to false to avoid
7508 * setting HDCP multiple times.
7510 * Handles: DESIRED -> DESIRED (Special case)
7512 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7513 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7514 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7515 dm_con_state->update_hdcp = false;
7516 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7521 /* Hot-plug, headless s3, dpms
7523 * Only start HDCP if the display is connected/enabled.
7524 * update_hdcp flag will be set to false until the next
7527 * Handles: DESIRED -> DESIRED (Special case)
7529 if (dm_con_state->update_hdcp &&
7530 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7531 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7532 dm_con_state->update_hdcp = false;
7533 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7538 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7539 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7540 if (new_crtc_state && new_crtc_state->mode_changed) {
7541 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7545 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7550 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7554 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7555 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7560 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7565 static void remove_stream(struct amdgpu_device *adev,
7566 struct amdgpu_crtc *acrtc,
7567 struct dc_stream_state *stream)
7569 /* this is the update mode case */
7571 acrtc->otg_inst = -1;
7572 acrtc->enabled = false;
7575 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7578 assert_spin_locked(&acrtc->base.dev->event_lock);
7579 WARN_ON(acrtc->event);
7581 acrtc->event = acrtc->base.state->event;
7583 /* Set the flip status */
7584 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7586 /* Mark this event as consumed */
7587 acrtc->base.state->event = NULL;
7589 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7593 static void update_freesync_state_on_stream(
7594 struct amdgpu_display_manager *dm,
7595 struct dm_crtc_state *new_crtc_state,
7596 struct dc_stream_state *new_stream,
7597 struct dc_plane_state *surface,
7598 u32 flip_timestamp_in_us)
7600 struct mod_vrr_params vrr_params;
7601 struct dc_info_packet vrr_infopacket = {0};
7602 struct amdgpu_device *adev = dm->adev;
7603 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7604 unsigned long flags;
7605 bool pack_sdp_v1_3 = false;
7611 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7612 * For now it's sufficient to just guard against these conditions.
7615 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7618 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7619 vrr_params = acrtc->dm_irq_params.vrr_params;
7622 mod_freesync_handle_preflip(
7623 dm->freesync_module,
7626 flip_timestamp_in_us,
7629 if (adev->family < AMDGPU_FAMILY_AI &&
7630 amdgpu_dm_vrr_active(new_crtc_state)) {
7631 mod_freesync_handle_v_update(dm->freesync_module,
7632 new_stream, &vrr_params);
7634 /* Need to call this before the frame ends. */
7635 dc_stream_adjust_vmin_vmax(dm->dc,
7636 new_crtc_state->stream,
7637 &vrr_params.adjust);
7641 mod_freesync_build_vrr_infopacket(
7642 dm->freesync_module,
7646 TRANSFER_FUNC_UNKNOWN,
7650 new_crtc_state->freesync_vrr_info_changed |=
7651 (memcmp(&new_crtc_state->vrr_infopacket,
7653 sizeof(vrr_infopacket)) != 0);
7655 acrtc->dm_irq_params.vrr_params = vrr_params;
7656 new_crtc_state->vrr_infopacket = vrr_infopacket;
7658 new_stream->vrr_infopacket = vrr_infopacket;
7659 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7661 if (new_crtc_state->freesync_vrr_info_changed)
7662 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7663 new_crtc_state->base.crtc->base.id,
7664 (int)new_crtc_state->base.vrr_enabled,
7665 (int)vrr_params.state);
7667 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7670 static void update_stream_irq_parameters(
7671 struct amdgpu_display_manager *dm,
7672 struct dm_crtc_state *new_crtc_state)
7674 struct dc_stream_state *new_stream = new_crtc_state->stream;
7675 struct mod_vrr_params vrr_params;
7676 struct mod_freesync_config config = new_crtc_state->freesync_config;
7677 struct amdgpu_device *adev = dm->adev;
7678 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7679 unsigned long flags;
7685 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7686 * For now it's sufficient to just guard against these conditions.
7688 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7691 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7692 vrr_params = acrtc->dm_irq_params.vrr_params;
7694 if (new_crtc_state->vrr_supported &&
7695 config.min_refresh_in_uhz &&
7696 config.max_refresh_in_uhz) {
7698 * if freesync compatible mode was set, config.state will be set
7701 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7702 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7703 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7704 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7705 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7706 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7707 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7709 config.state = new_crtc_state->base.vrr_enabled ?
7710 VRR_STATE_ACTIVE_VARIABLE :
7714 config.state = VRR_STATE_UNSUPPORTED;
7717 mod_freesync_build_vrr_params(dm->freesync_module,
7719 &config, &vrr_params);
7721 new_crtc_state->freesync_config = config;
7722 /* Copy state for access from DM IRQ handler */
7723 acrtc->dm_irq_params.freesync_config = config;
7724 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7725 acrtc->dm_irq_params.vrr_params = vrr_params;
7726 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7729 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7730 struct dm_crtc_state *new_state)
7732 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7733 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7735 if (!old_vrr_active && new_vrr_active) {
7736 /* Transition VRR inactive -> active:
7737 * While VRR is active, we must not disable vblank irq, as a
7738 * reenable after disable would compute bogus vblank/pflip
7739 * timestamps if it likely happened inside display front-porch.
7741 * We also need vupdate irq for the actual core vblank handling
7744 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
7745 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7746 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7747 __func__, new_state->base.crtc->base.id);
7748 } else if (old_vrr_active && !new_vrr_active) {
7749 /* Transition VRR active -> inactive:
7750 * Allow vblank irq disable again for fixed refresh rate.
7752 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
7753 drm_crtc_vblank_put(new_state->base.crtc);
7754 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7755 __func__, new_state->base.crtc->base.id);
7759 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7761 struct drm_plane *plane;
7762 struct drm_plane_state *old_plane_state;
7766 * TODO: Make this per-stream so we don't issue redundant updates for
7767 * commits with multiple streams.
7769 for_each_old_plane_in_state(state, plane, old_plane_state, i)
7770 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7771 handle_cursor_update(plane, old_plane_state);
7774 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7775 struct dc_state *dc_state,
7776 struct drm_device *dev,
7777 struct amdgpu_display_manager *dm,
7778 struct drm_crtc *pcrtc,
7779 bool wait_for_vblank)
7783 struct drm_plane *plane;
7784 struct drm_plane_state *old_plane_state, *new_plane_state;
7785 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7786 struct drm_crtc_state *new_pcrtc_state =
7787 drm_atomic_get_new_crtc_state(state, pcrtc);
7788 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7789 struct dm_crtc_state *dm_old_crtc_state =
7790 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7791 int planes_count = 0, vpos, hpos;
7792 unsigned long flags;
7793 u32 target_vblank, last_flip_vblank;
7794 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7795 bool cursor_update = false;
7796 bool pflip_present = false;
7798 struct dc_surface_update surface_updates[MAX_SURFACES];
7799 struct dc_plane_info plane_infos[MAX_SURFACES];
7800 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7801 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7802 struct dc_stream_update stream_update;
7805 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7808 dm_error("Failed to allocate update bundle\n");
7813 * Disable the cursor first if we're disabling all the planes.
7814 * It'll remain on the screen after the planes are re-enabled
7817 if (acrtc_state->active_planes == 0)
7818 amdgpu_dm_commit_cursors(state);
7820 /* update planes when needed */
7821 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7822 struct drm_crtc *crtc = new_plane_state->crtc;
7823 struct drm_crtc_state *new_crtc_state;
7824 struct drm_framebuffer *fb = new_plane_state->fb;
7825 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7826 bool plane_needs_flip;
7827 struct dc_plane_state *dc_plane;
7828 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7830 /* Cursor plane is handled after stream updates */
7831 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7832 if ((fb && crtc == pcrtc) ||
7833 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7834 cursor_update = true;
7839 if (!fb || !crtc || pcrtc != crtc)
7842 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7843 if (!new_crtc_state->active)
7846 dc_plane = dm_new_plane_state->dc_state;
7848 bundle->surface_updates[planes_count].surface = dc_plane;
7849 if (new_pcrtc_state->color_mgmt_changed) {
7850 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7851 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7852 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7855 fill_dc_scaling_info(dm->adev, new_plane_state,
7856 &bundle->scaling_infos[planes_count]);
7858 bundle->surface_updates[planes_count].scaling_info =
7859 &bundle->scaling_infos[planes_count];
7861 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7863 pflip_present = pflip_present || plane_needs_flip;
7865 if (!plane_needs_flip) {
7870 fill_dc_plane_info_and_addr(
7871 dm->adev, new_plane_state,
7873 &bundle->plane_infos[planes_count],
7874 &bundle->flip_addrs[planes_count].address,
7875 afb->tmz_surface, false);
7877 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
7878 new_plane_state->plane->index,
7879 bundle->plane_infos[planes_count].dcc.enable);
7881 bundle->surface_updates[planes_count].plane_info =
7882 &bundle->plane_infos[planes_count];
7884 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7885 fill_dc_dirty_rects(plane, old_plane_state,
7886 new_plane_state, new_crtc_state,
7887 &bundle->flip_addrs[planes_count]);
7890 * Only allow immediate flips for fast updates that don't
7891 * change FB pitch, DCC state, rotation or mirroing.
7893 bundle->flip_addrs[planes_count].flip_immediate =
7894 crtc->state->async_flip &&
7895 acrtc_state->update_type == UPDATE_TYPE_FAST;
7897 timestamp_ns = ktime_get_ns();
7898 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7899 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7900 bundle->surface_updates[planes_count].surface = dc_plane;
7902 if (!bundle->surface_updates[planes_count].surface) {
7903 DRM_ERROR("No surface for CRTC: id=%d\n",
7904 acrtc_attach->crtc_id);
7908 if (plane == pcrtc->primary)
7909 update_freesync_state_on_stream(
7912 acrtc_state->stream,
7914 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7916 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
7918 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7919 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7925 if (pflip_present) {
7927 /* Use old throttling in non-vrr fixed refresh rate mode
7928 * to keep flip scheduling based on target vblank counts
7929 * working in a backwards compatible way, e.g., for
7930 * clients using the GLX_OML_sync_control extension or
7931 * DRI3/Present extension with defined target_msc.
7933 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7936 /* For variable refresh rate mode only:
7937 * Get vblank of last completed flip to avoid > 1 vrr
7938 * flips per video frame by use of throttling, but allow
7939 * flip programming anywhere in the possibly large
7940 * variable vrr vblank interval for fine-grained flip
7941 * timing control and more opportunity to avoid stutter
7942 * on late submission of flips.
7944 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7945 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7946 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7949 target_vblank = last_flip_vblank + wait_for_vblank;
7952 * Wait until we're out of the vertical blank period before the one
7953 * targeted by the flip
7955 while ((acrtc_attach->enabled &&
7956 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7957 0, &vpos, &hpos, NULL,
7958 NULL, &pcrtc->hwmode)
7959 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7960 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7961 (int)(target_vblank -
7962 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7963 usleep_range(1000, 1100);
7967 * Prepare the flip event for the pageflip interrupt to handle.
7969 * This only works in the case where we've already turned on the
7970 * appropriate hardware blocks (eg. HUBP) so in the transition case
7971 * from 0 -> n planes we have to skip a hardware generated event
7972 * and rely on sending it from software.
7974 if (acrtc_attach->base.state->event &&
7975 acrtc_state->active_planes > 0) {
7976 drm_crtc_vblank_get(pcrtc);
7978 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7980 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7981 prepare_flip_isr(acrtc_attach);
7983 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7986 if (acrtc_state->stream) {
7987 if (acrtc_state->freesync_vrr_info_changed)
7988 bundle->stream_update.vrr_infopacket =
7989 &acrtc_state->stream->vrr_infopacket;
7991 } else if (cursor_update && acrtc_state->active_planes > 0 &&
7992 acrtc_attach->base.state->event) {
7993 drm_crtc_vblank_get(pcrtc);
7995 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7997 acrtc_attach->event = acrtc_attach->base.state->event;
7998 acrtc_attach->base.state->event = NULL;
8000 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8003 /* Update the planes if changed or disable if we don't have any. */
8004 if ((planes_count || acrtc_state->active_planes == 0) &&
8005 acrtc_state->stream) {
8007 * If PSR or idle optimizations are enabled then flush out
8008 * any pending work before hardware programming.
8010 if (dm->vblank_control_workqueue)
8011 flush_workqueue(dm->vblank_control_workqueue);
8013 bundle->stream_update.stream = acrtc_state->stream;
8014 if (new_pcrtc_state->mode_changed) {
8015 bundle->stream_update.src = acrtc_state->stream->src;
8016 bundle->stream_update.dst = acrtc_state->stream->dst;
8019 if (new_pcrtc_state->color_mgmt_changed) {
8021 * TODO: This isn't fully correct since we've actually
8022 * already modified the stream in place.
8024 bundle->stream_update.gamut_remap =
8025 &acrtc_state->stream->gamut_remap_matrix;
8026 bundle->stream_update.output_csc_transform =
8027 &acrtc_state->stream->csc_color_matrix;
8028 bundle->stream_update.out_transfer_func =
8029 acrtc_state->stream->out_transfer_func;
8032 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8033 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8034 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8037 * If FreeSync state on the stream has changed then we need to
8038 * re-adjust the min/max bounds now that DC doesn't handle this
8039 * as part of commit.
8041 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8042 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8043 dc_stream_adjust_vmin_vmax(
8044 dm->dc, acrtc_state->stream,
8045 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8046 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8048 mutex_lock(&dm->dc_lock);
8049 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8050 acrtc_state->stream->link->psr_settings.psr_allow_active)
8051 amdgpu_dm_psr_disable(acrtc_state->stream);
8053 dc_commit_updates_for_stream(dm->dc,
8054 bundle->surface_updates,
8056 acrtc_state->stream,
8057 &bundle->stream_update,
8061 * Enable or disable the interrupts on the backend.
8063 * Most pipes are put into power gating when unused.
8065 * When power gating is enabled on a pipe we lose the
8066 * interrupt enablement state when power gating is disabled.
8068 * So we need to update the IRQ control state in hardware
8069 * whenever the pipe turns on (since it could be previously
8070 * power gated) or off (since some pipes can't be power gated
8073 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8074 dm_update_pflip_irq_state(drm_to_adev(dev),
8077 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8078 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8079 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8080 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8082 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8083 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8084 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8085 struct amdgpu_dm_connector *aconn =
8086 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8088 if (aconn->psr_skip_count > 0)
8089 aconn->psr_skip_count--;
8091 /* Allow PSR when skip count is 0. */
8092 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8095 * If sink supports PSR SU, there is no need to rely on
8096 * a vblank event disable request to enable PSR. PSR SU
8097 * can be enabled immediately once OS demonstrates an
8098 * adequate number of fast atomic commits to notify KMD
8099 * of update events. See `vblank_control_worker()`.
8101 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8102 acrtc_attach->dm_irq_params.allow_psr_entry &&
8103 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8104 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8106 !acrtc_state->stream->link->psr_settings.psr_allow_active)
8107 amdgpu_dm_psr_enable(acrtc_state->stream);
8109 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8112 mutex_unlock(&dm->dc_lock);
8116 * Update cursor state *after* programming all the planes.
8117 * This avoids redundant programming in the case where we're going
8118 * to be disabling a single plane - those pipes are being disabled.
8120 if (acrtc_state->active_planes)
8121 amdgpu_dm_commit_cursors(state);
8127 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8128 struct drm_atomic_state *state)
8130 struct amdgpu_device *adev = drm_to_adev(dev);
8131 struct amdgpu_dm_connector *aconnector;
8132 struct drm_connector *connector;
8133 struct drm_connector_state *old_con_state, *new_con_state;
8134 struct drm_crtc_state *new_crtc_state;
8135 struct dm_crtc_state *new_dm_crtc_state;
8136 const struct dc_stream_status *status;
8139 /* Notify device removals. */
8140 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8141 if (old_con_state->crtc != new_con_state->crtc) {
8142 /* CRTC changes require notification. */
8146 if (!new_con_state->crtc)
8149 new_crtc_state = drm_atomic_get_new_crtc_state(
8150 state, new_con_state->crtc);
8152 if (!new_crtc_state)
8155 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8159 aconnector = to_amdgpu_dm_connector(connector);
8161 mutex_lock(&adev->dm.audio_lock);
8162 inst = aconnector->audio_inst;
8163 aconnector->audio_inst = -1;
8164 mutex_unlock(&adev->dm.audio_lock);
8166 amdgpu_dm_audio_eld_notify(adev, inst);
8169 /* Notify audio device additions. */
8170 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8171 if (!new_con_state->crtc)
8174 new_crtc_state = drm_atomic_get_new_crtc_state(
8175 state, new_con_state->crtc);
8177 if (!new_crtc_state)
8180 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8183 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8184 if (!new_dm_crtc_state->stream)
8187 status = dc_stream_get_status(new_dm_crtc_state->stream);
8191 aconnector = to_amdgpu_dm_connector(connector);
8193 mutex_lock(&adev->dm.audio_lock);
8194 inst = status->audio_inst;
8195 aconnector->audio_inst = inst;
8196 mutex_unlock(&adev->dm.audio_lock);
8198 amdgpu_dm_audio_eld_notify(adev, inst);
8203 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8204 * @crtc_state: the DRM CRTC state
8205 * @stream_state: the DC stream state.
8207 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8208 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8210 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8211 struct dc_stream_state *stream_state)
8213 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8217 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8218 * @state: The atomic state to commit
8220 * This will tell DC to commit the constructed DC state from atomic_check,
8221 * programming the hardware. Any failures here implies a hardware failure, since
8222 * atomic check should have filtered anything non-kosher.
8224 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8226 struct drm_device *dev = state->dev;
8227 struct amdgpu_device *adev = drm_to_adev(dev);
8228 struct amdgpu_display_manager *dm = &adev->dm;
8229 struct dm_atomic_state *dm_state;
8230 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8232 struct drm_crtc *crtc;
8233 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8234 unsigned long flags;
8235 bool wait_for_vblank = true;
8236 struct drm_connector *connector;
8237 struct drm_connector_state *old_con_state, *new_con_state;
8238 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8239 int crtc_disable_count = 0;
8240 bool mode_set_reset_required = false;
8243 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8245 r = drm_atomic_helper_wait_for_fences(dev, state, false);
8247 DRM_ERROR("Waiting for fences timed out!");
8249 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8250 drm_dp_mst_atomic_wait_for_dependencies(state);
8252 dm_state = dm_atomic_get_new_state(state);
8253 if (dm_state && dm_state->context) {
8254 dc_state = dm_state->context;
8256 /* No state changes, retain current state. */
8257 dc_state_temp = dc_create_state(dm->dc);
8258 ASSERT(dc_state_temp);
8259 dc_state = dc_state_temp;
8260 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8263 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8264 new_crtc_state, i) {
8265 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8267 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8269 if (old_crtc_state->active &&
8270 (!new_crtc_state->active ||
8271 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8272 manage_dm_interrupts(adev, acrtc, false);
8273 dc_stream_release(dm_old_crtc_state->stream);
8277 drm_atomic_helper_calc_timestamping_constants(state);
8279 /* update changed items */
8280 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8281 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8283 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8284 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8286 drm_dbg_state(state->dev,
8287 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8288 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8289 "connectors_changed:%d\n",
8291 new_crtc_state->enable,
8292 new_crtc_state->active,
8293 new_crtc_state->planes_changed,
8294 new_crtc_state->mode_changed,
8295 new_crtc_state->active_changed,
8296 new_crtc_state->connectors_changed);
8298 /* Disable cursor if disabling crtc */
8299 if (old_crtc_state->active && !new_crtc_state->active) {
8300 struct dc_cursor_position position;
8302 memset(&position, 0, sizeof(position));
8303 mutex_lock(&dm->dc_lock);
8304 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8305 mutex_unlock(&dm->dc_lock);
8308 /* Copy all transient state flags into dc state */
8309 if (dm_new_crtc_state->stream) {
8310 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8311 dm_new_crtc_state->stream);
8314 /* handles headless hotplug case, updating new_state and
8315 * aconnector as needed
8318 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8320 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8322 if (!dm_new_crtc_state->stream) {
8324 * this could happen because of issues with
8325 * userspace notifications delivery.
8326 * In this case userspace tries to set mode on
8327 * display which is disconnected in fact.
8328 * dc_sink is NULL in this case on aconnector.
8329 * We expect reset mode will come soon.
8331 * This can also happen when unplug is done
8332 * during resume sequence ended
8334 * In this case, we want to pretend we still
8335 * have a sink to keep the pipe running so that
8336 * hw state is consistent with the sw state
8338 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8339 __func__, acrtc->base.base.id);
8343 if (dm_old_crtc_state->stream)
8344 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8346 pm_runtime_get_noresume(dev->dev);
8348 acrtc->enabled = true;
8349 acrtc->hw_mode = new_crtc_state->mode;
8350 crtc->hwmode = new_crtc_state->mode;
8351 mode_set_reset_required = true;
8352 } else if (modereset_required(new_crtc_state)) {
8353 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8354 /* i.e. reset mode */
8355 if (dm_old_crtc_state->stream)
8356 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8358 mode_set_reset_required = true;
8360 } /* for_each_crtc_in_state() */
8363 /* if there mode set or reset, disable eDP PSR */
8364 if (mode_set_reset_required) {
8365 if (dm->vblank_control_workqueue)
8366 flush_workqueue(dm->vblank_control_workqueue);
8368 amdgpu_dm_psr_disable_all(dm);
8371 dm_enable_per_frame_crtc_master_sync(dc_state);
8372 mutex_lock(&dm->dc_lock);
8373 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8375 /* Allow idle optimization when vblank count is 0 for display off */
8376 if (dm->active_vblank_irq_count == 0)
8377 dc_allow_idle_optimizations(dm->dc, true);
8378 mutex_unlock(&dm->dc_lock);
8381 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8382 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8384 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8386 if (dm_new_crtc_state->stream != NULL) {
8387 const struct dc_stream_status *status =
8388 dc_stream_get_status(dm_new_crtc_state->stream);
8391 status = dc_stream_get_status_from_state(dc_state,
8392 dm_new_crtc_state->stream);
8394 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8396 acrtc->otg_inst = status->primary_otg_inst;
8399 #ifdef CONFIG_DRM_AMD_DC_HDCP
8400 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8401 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8402 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8403 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8405 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8410 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8411 connector->index, connector->status, connector->dpms);
8412 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8413 old_con_state->content_protection, new_con_state->content_protection);
8415 if (aconnector->dc_sink) {
8416 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8417 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8418 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8419 aconnector->dc_sink->edid_caps.display_name);
8423 new_crtc_state = NULL;
8424 old_crtc_state = NULL;
8427 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8428 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8432 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8433 old_crtc_state->enable,
8434 old_crtc_state->active,
8435 old_crtc_state->mode_changed,
8436 old_crtc_state->active_changed,
8437 old_crtc_state->connectors_changed);
8440 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8441 new_crtc_state->enable,
8442 new_crtc_state->active,
8443 new_crtc_state->mode_changed,
8444 new_crtc_state->active_changed,
8445 new_crtc_state->connectors_changed);
8448 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8449 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8450 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8451 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8453 new_crtc_state = NULL;
8454 old_crtc_state = NULL;
8457 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8458 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8461 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8463 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8464 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8465 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8466 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8467 dm_new_con_state->update_hdcp = true;
8471 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8472 old_con_state, connector, adev->dm.hdcp_workqueue)) {
8473 /* when display is unplugged from mst hub, connctor will
8474 * be destroyed within dm_dp_mst_connector_destroy. connector
8475 * hdcp perperties, like type, undesired, desired, enabled,
8476 * will be lost. So, save hdcp properties into hdcp_work within
8477 * amdgpu_dm_atomic_commit_tail. if the same display is
8478 * plugged back with same display index, its hdcp properties
8479 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8482 bool enable_encryption = false;
8484 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8485 enable_encryption = true;
8487 if (aconnector->dc_link && aconnector->dc_sink &&
8488 aconnector->dc_link->type == dc_connection_mst_branch) {
8489 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8490 struct hdcp_workqueue *hdcp_w =
8491 &hdcp_work[aconnector->dc_link->link_index];
8493 hdcp_w->hdcp_content_type[connector->index] =
8494 new_con_state->hdcp_content_type;
8495 hdcp_w->content_protection[connector->index] =
8496 new_con_state->content_protection;
8499 if (new_crtc_state && new_crtc_state->mode_changed &&
8500 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8501 enable_encryption = true;
8503 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8505 hdcp_update_display(
8506 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8507 new_con_state->hdcp_content_type, enable_encryption);
8512 /* Handle connector state changes */
8513 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8514 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8515 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8516 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8517 struct dc_surface_update dummy_updates[MAX_SURFACES];
8518 struct dc_stream_update stream_update;
8519 struct dc_info_packet hdr_packet;
8520 struct dc_stream_status *status = NULL;
8521 bool abm_changed, hdr_changed, scaling_changed;
8523 memset(&dummy_updates, 0, sizeof(dummy_updates));
8524 memset(&stream_update, 0, sizeof(stream_update));
8527 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8528 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8531 /* Skip any modesets/resets */
8532 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8535 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8536 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8538 scaling_changed = is_scaling_state_different(dm_new_con_state,
8541 abm_changed = dm_new_crtc_state->abm_level !=
8542 dm_old_crtc_state->abm_level;
8545 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8547 if (!scaling_changed && !abm_changed && !hdr_changed)
8550 stream_update.stream = dm_new_crtc_state->stream;
8551 if (scaling_changed) {
8552 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8553 dm_new_con_state, dm_new_crtc_state->stream);
8555 stream_update.src = dm_new_crtc_state->stream->src;
8556 stream_update.dst = dm_new_crtc_state->stream->dst;
8560 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8562 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8566 fill_hdr_info_packet(new_con_state, &hdr_packet);
8567 stream_update.hdr_static_metadata = &hdr_packet;
8570 status = dc_stream_get_status(dm_new_crtc_state->stream);
8572 if (WARN_ON(!status))
8575 WARN_ON(!status->plane_count);
8578 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8579 * Here we create an empty update on each plane.
8580 * To fix this, DC should permit updating only stream properties.
8582 for (j = 0; j < status->plane_count; j++)
8583 dummy_updates[j].surface = status->plane_states[0];
8586 mutex_lock(&dm->dc_lock);
8587 dc_commit_updates_for_stream(dm->dc,
8589 status->plane_count,
8590 dm_new_crtc_state->stream,
8593 mutex_unlock(&dm->dc_lock);
8597 * Enable interrupts for CRTCs that are newly enabled or went through
8598 * a modeset. It was intentionally deferred until after the front end
8599 * state was modified to wait until the OTG was on and so the IRQ
8600 * handlers didn't access stale or invalid state.
8602 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8603 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8604 #ifdef CONFIG_DEBUG_FS
8605 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8607 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8608 if (old_crtc_state->active && !new_crtc_state->active)
8609 crtc_disable_count++;
8611 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8612 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8614 /* For freesync config update on crtc state and params for irq */
8615 update_stream_irq_parameters(dm, dm_new_crtc_state);
8617 #ifdef CONFIG_DEBUG_FS
8618 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8619 cur_crc_src = acrtc->dm_irq_params.crc_src;
8620 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8623 if (new_crtc_state->active &&
8624 (!old_crtc_state->active ||
8625 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8626 dc_stream_retain(dm_new_crtc_state->stream);
8627 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8628 manage_dm_interrupts(adev, acrtc, true);
8630 /* Handle vrr on->off / off->on transitions */
8631 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8633 #ifdef CONFIG_DEBUG_FS
8634 if (new_crtc_state->active &&
8635 (!old_crtc_state->active ||
8636 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8638 * Frontend may have changed so reapply the CRC capture
8639 * settings for the stream.
8641 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8642 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8643 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8644 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8645 acrtc->dm_irq_params.window_param.update_win = true;
8648 * It takes 2 frames for HW to stably generate CRC when
8649 * resuming from suspend, so we set skip_frame_cnt 2.
8651 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8652 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8655 if (amdgpu_dm_crtc_configure_crc_source(
8656 crtc, dm_new_crtc_state, cur_crc_src))
8657 DRM_DEBUG_DRIVER("Failed to configure crc source");
8663 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8664 if (new_crtc_state->async_flip)
8665 wait_for_vblank = false;
8667 /* update planes when needed per crtc*/
8668 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8669 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8671 if (dm_new_crtc_state->stream)
8672 amdgpu_dm_commit_planes(state, dc_state, dev,
8673 dm, crtc, wait_for_vblank);
8676 /* Update audio instances for each connector. */
8677 amdgpu_dm_commit_audio(dev, state);
8679 /* restore the backlight level */
8680 for (i = 0; i < dm->num_of_edps; i++) {
8681 if (dm->backlight_dev[i] &&
8682 (dm->actual_brightness[i] != dm->brightness[i]))
8683 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8687 * send vblank event on all events not handled in flip and
8688 * mark consumed event for drm_atomic_helper_commit_hw_done
8690 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8691 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8693 if (new_crtc_state->event)
8694 drm_send_event_locked(dev, &new_crtc_state->event->base);
8696 new_crtc_state->event = NULL;
8698 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8700 /* Signal HW programming completion */
8701 drm_atomic_helper_commit_hw_done(state);
8703 if (wait_for_vblank)
8704 drm_atomic_helper_wait_for_flip_done(dev, state);
8706 drm_atomic_helper_cleanup_planes(dev, state);
8708 /* return the stolen vga memory back to VRAM */
8709 if (!adev->mman.keep_stolen_vga_memory)
8710 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8711 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8714 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8715 * so we can put the GPU into runtime suspend if we're not driving any
8718 for (i = 0; i < crtc_disable_count; i++)
8719 pm_runtime_put_autosuspend(dev->dev);
8720 pm_runtime_mark_last_busy(dev->dev);
8723 dc_release_state(dc_state_temp);
8726 static int dm_force_atomic_commit(struct drm_connector *connector)
8729 struct drm_device *ddev = connector->dev;
8730 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8731 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8732 struct drm_plane *plane = disconnected_acrtc->base.primary;
8733 struct drm_connector_state *conn_state;
8734 struct drm_crtc_state *crtc_state;
8735 struct drm_plane_state *plane_state;
8740 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8742 /* Construct an atomic state to restore previous display setting */
8745 * Attach connectors to drm_atomic_state
8747 conn_state = drm_atomic_get_connector_state(state, connector);
8749 ret = PTR_ERR_OR_ZERO(conn_state);
8753 /* Attach crtc to drm_atomic_state*/
8754 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8756 ret = PTR_ERR_OR_ZERO(crtc_state);
8760 /* force a restore */
8761 crtc_state->mode_changed = true;
8763 /* Attach plane to drm_atomic_state */
8764 plane_state = drm_atomic_get_plane_state(state, plane);
8766 ret = PTR_ERR_OR_ZERO(plane_state);
8770 /* Call commit internally with the state we just constructed */
8771 ret = drm_atomic_commit(state);
8774 drm_atomic_state_put(state);
8776 DRM_ERROR("Restoring old state failed with %i\n", ret);
8782 * This function handles all cases when set mode does not come upon hotplug.
8783 * This includes when a display is unplugged then plugged back into the
8784 * same port and when running without usermode desktop manager supprot
8786 void dm_restore_drm_connector_state(struct drm_device *dev,
8787 struct drm_connector *connector)
8789 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8790 struct amdgpu_crtc *disconnected_acrtc;
8791 struct dm_crtc_state *acrtc_state;
8793 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8796 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8797 if (!disconnected_acrtc)
8800 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8801 if (!acrtc_state->stream)
8805 * If the previous sink is not released and different from the current,
8806 * we deduce we are in a state where we can not rely on usermode call
8807 * to turn on the display, so we do it here
8809 if (acrtc_state->stream->sink != aconnector->dc_sink)
8810 dm_force_atomic_commit(&aconnector->base);
8814 * Grabs all modesetting locks to serialize against any blocking commits,
8815 * Waits for completion of all non blocking commits.
8817 static int do_aquire_global_lock(struct drm_device *dev,
8818 struct drm_atomic_state *state)
8820 struct drm_crtc *crtc;
8821 struct drm_crtc_commit *commit;
8825 * Adding all modeset locks to aquire_ctx will
8826 * ensure that when the framework release it the
8827 * extra locks we are locking here will get released to
8829 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8833 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8834 spin_lock(&crtc->commit_lock);
8835 commit = list_first_entry_or_null(&crtc->commit_list,
8836 struct drm_crtc_commit, commit_entry);
8838 drm_crtc_commit_get(commit);
8839 spin_unlock(&crtc->commit_lock);
8845 * Make sure all pending HW programming completed and
8848 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8851 ret = wait_for_completion_interruptible_timeout(
8852 &commit->flip_done, 10*HZ);
8855 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8856 "timed out\n", crtc->base.id, crtc->name);
8858 drm_crtc_commit_put(commit);
8861 return ret < 0 ? ret : 0;
8864 static void get_freesync_config_for_crtc(
8865 struct dm_crtc_state *new_crtc_state,
8866 struct dm_connector_state *new_con_state)
8868 struct mod_freesync_config config = {0};
8869 struct amdgpu_dm_connector *aconnector =
8870 to_amdgpu_dm_connector(new_con_state->base.connector);
8871 struct drm_display_mode *mode = &new_crtc_state->base.mode;
8872 int vrefresh = drm_mode_vrefresh(mode);
8873 bool fs_vid_mode = false;
8875 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8876 vrefresh >= aconnector->min_vfreq &&
8877 vrefresh <= aconnector->max_vfreq;
8879 if (new_crtc_state->vrr_supported) {
8880 new_crtc_state->stream->ignore_msa_timing_param = true;
8881 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
8883 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8884 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
8885 config.vsif_supported = true;
8889 config.state = VRR_STATE_ACTIVE_FIXED;
8890 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8892 } else if (new_crtc_state->base.vrr_enabled) {
8893 config.state = VRR_STATE_ACTIVE_VARIABLE;
8895 config.state = VRR_STATE_INACTIVE;
8899 new_crtc_state->freesync_config = config;
8902 static void reset_freesync_config_for_crtc(
8903 struct dm_crtc_state *new_crtc_state)
8905 new_crtc_state->vrr_supported = false;
8907 memset(&new_crtc_state->vrr_infopacket, 0,
8908 sizeof(new_crtc_state->vrr_infopacket));
8912 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8913 struct drm_crtc_state *new_crtc_state)
8915 const struct drm_display_mode *old_mode, *new_mode;
8917 if (!old_crtc_state || !new_crtc_state)
8920 old_mode = &old_crtc_state->mode;
8921 new_mode = &new_crtc_state->mode;
8923 if (old_mode->clock == new_mode->clock &&
8924 old_mode->hdisplay == new_mode->hdisplay &&
8925 old_mode->vdisplay == new_mode->vdisplay &&
8926 old_mode->htotal == new_mode->htotal &&
8927 old_mode->vtotal != new_mode->vtotal &&
8928 old_mode->hsync_start == new_mode->hsync_start &&
8929 old_mode->vsync_start != new_mode->vsync_start &&
8930 old_mode->hsync_end == new_mode->hsync_end &&
8931 old_mode->vsync_end != new_mode->vsync_end &&
8932 old_mode->hskew == new_mode->hskew &&
8933 old_mode->vscan == new_mode->vscan &&
8934 (old_mode->vsync_end - old_mode->vsync_start) ==
8935 (new_mode->vsync_end - new_mode->vsync_start))
8941 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
8943 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8945 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8947 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8948 den = (unsigned long long)new_crtc_state->mode.htotal *
8949 (unsigned long long)new_crtc_state->mode.vtotal;
8951 res = div_u64(num, den);
8952 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8955 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8956 struct drm_atomic_state *state,
8957 struct drm_crtc *crtc,
8958 struct drm_crtc_state *old_crtc_state,
8959 struct drm_crtc_state *new_crtc_state,
8961 bool *lock_and_validation_needed)
8963 struct dm_atomic_state *dm_state = NULL;
8964 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8965 struct dc_stream_state *new_stream;
8969 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8970 * update changed items
8972 struct amdgpu_crtc *acrtc = NULL;
8973 struct amdgpu_dm_connector *aconnector = NULL;
8974 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8975 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8979 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8980 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8981 acrtc = to_amdgpu_crtc(crtc);
8982 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8984 /* TODO This hack should go away */
8985 if (aconnector && enable) {
8986 /* Make sure fake sink is created in plug-in scenario */
8987 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8989 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8992 if (IS_ERR(drm_new_conn_state)) {
8993 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8997 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8998 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9000 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9003 new_stream = create_validate_stream_for_sink(aconnector,
9004 &new_crtc_state->mode,
9006 dm_old_crtc_state->stream);
9009 * we can have no stream on ACTION_SET if a display
9010 * was disconnected during S3, in this case it is not an
9011 * error, the OS will be updated after detection, and
9012 * will do the right thing on next atomic commit
9016 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9017 __func__, acrtc->base.base.id);
9023 * TODO: Check VSDB bits to decide whether this should
9024 * be enabled or not.
9026 new_stream->triggered_crtc_reset.enabled =
9027 dm->force_timing_sync;
9029 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9031 ret = fill_hdr_info_packet(drm_new_conn_state,
9032 &new_stream->hdr_static_metadata);
9037 * If we already removed the old stream from the context
9038 * (and set the new stream to NULL) then we can't reuse
9039 * the old stream even if the stream and scaling are unchanged.
9040 * We'll hit the BUG_ON and black screen.
9042 * TODO: Refactor this function to allow this check to work
9043 * in all conditions.
9045 if (amdgpu_freesync_vid_mode &&
9046 dm_new_crtc_state->stream &&
9047 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9050 if (dm_new_crtc_state->stream &&
9051 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9052 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9053 new_crtc_state->mode_changed = false;
9054 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9055 new_crtc_state->mode_changed);
9059 /* mode_changed flag may get updated above, need to check again */
9060 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9063 drm_dbg_state(state->dev,
9064 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9065 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9066 "connectors_changed:%d\n",
9068 new_crtc_state->enable,
9069 new_crtc_state->active,
9070 new_crtc_state->planes_changed,
9071 new_crtc_state->mode_changed,
9072 new_crtc_state->active_changed,
9073 new_crtc_state->connectors_changed);
9075 /* Remove stream for any changed/disabled CRTC */
9078 if (!dm_old_crtc_state->stream)
9081 /* Unset freesync video if it was active before */
9082 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9083 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9084 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9087 /* Now check if we should set freesync video mode */
9088 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9089 is_timing_unchanged_for_freesync(new_crtc_state,
9091 new_crtc_state->mode_changed = false;
9093 "Mode change not required for front porch change, "
9094 "setting mode_changed to %d",
9095 new_crtc_state->mode_changed);
9097 set_freesync_fixed_config(dm_new_crtc_state);
9100 } else if (amdgpu_freesync_vid_mode && aconnector &&
9101 is_freesync_video_mode(&new_crtc_state->mode,
9103 struct drm_display_mode *high_mode;
9105 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9106 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9107 set_freesync_fixed_config(dm_new_crtc_state);
9111 ret = dm_atomic_get_state(state, &dm_state);
9115 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9118 /* i.e. reset mode */
9119 if (dc_remove_stream_from_ctx(
9122 dm_old_crtc_state->stream) != DC_OK) {
9127 dc_stream_release(dm_old_crtc_state->stream);
9128 dm_new_crtc_state->stream = NULL;
9130 reset_freesync_config_for_crtc(dm_new_crtc_state);
9132 *lock_and_validation_needed = true;
9134 } else {/* Add stream for any updated/enabled CRTC */
9136 * Quick fix to prevent NULL pointer on new_stream when
9137 * added MST connectors not found in existing crtc_state in the chained mode
9138 * TODO: need to dig out the root cause of that
9143 if (modereset_required(new_crtc_state))
9146 if (modeset_required(new_crtc_state, new_stream,
9147 dm_old_crtc_state->stream)) {
9149 WARN_ON(dm_new_crtc_state->stream);
9151 ret = dm_atomic_get_state(state, &dm_state);
9155 dm_new_crtc_state->stream = new_stream;
9157 dc_stream_retain(new_stream);
9159 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9162 if (dc_add_stream_to_ctx(
9165 dm_new_crtc_state->stream) != DC_OK) {
9170 *lock_and_validation_needed = true;
9175 /* Release extra reference */
9177 dc_stream_release(new_stream);
9180 * We want to do dc stream updates that do not require a
9181 * full modeset below.
9183 if (!(enable && aconnector && new_crtc_state->active))
9186 * Given above conditions, the dc state cannot be NULL because:
9187 * 1. We're in the process of enabling CRTCs (just been added
9188 * to the dc context, or already is on the context)
9189 * 2. Has a valid connector attached, and
9190 * 3. Is currently active and enabled.
9191 * => The dc stream state currently exists.
9193 BUG_ON(dm_new_crtc_state->stream == NULL);
9195 /* Scaling or underscan settings */
9196 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9197 drm_atomic_crtc_needs_modeset(new_crtc_state))
9198 update_stream_scaling_settings(
9199 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9202 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9205 * Color management settings. We also update color properties
9206 * when a modeset is needed, to ensure it gets reprogrammed.
9208 if (dm_new_crtc_state->base.color_mgmt_changed ||
9209 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9210 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9215 /* Update Freesync settings. */
9216 get_freesync_config_for_crtc(dm_new_crtc_state,
9223 dc_stream_release(new_stream);
9227 static bool should_reset_plane(struct drm_atomic_state *state,
9228 struct drm_plane *plane,
9229 struct drm_plane_state *old_plane_state,
9230 struct drm_plane_state *new_plane_state)
9232 struct drm_plane *other;
9233 struct drm_plane_state *old_other_state, *new_other_state;
9234 struct drm_crtc_state *new_crtc_state;
9238 * TODO: Remove this hack once the checks below are sufficient
9239 * enough to determine when we need to reset all the planes on
9242 if (state->allow_modeset)
9245 /* Exit early if we know that we're adding or removing the plane. */
9246 if (old_plane_state->crtc != new_plane_state->crtc)
9249 /* old crtc == new_crtc == NULL, plane not in context. */
9250 if (!new_plane_state->crtc)
9254 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9256 if (!new_crtc_state)
9259 /* CRTC Degamma changes currently require us to recreate planes. */
9260 if (new_crtc_state->color_mgmt_changed)
9263 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9267 * If there are any new primary or overlay planes being added or
9268 * removed then the z-order can potentially change. To ensure
9269 * correct z-order and pipe acquisition the current DC architecture
9270 * requires us to remove and recreate all existing planes.
9272 * TODO: Come up with a more elegant solution for this.
9274 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9275 struct amdgpu_framebuffer *old_afb, *new_afb;
9276 if (other->type == DRM_PLANE_TYPE_CURSOR)
9279 if (old_other_state->crtc != new_plane_state->crtc &&
9280 new_other_state->crtc != new_plane_state->crtc)
9283 if (old_other_state->crtc != new_other_state->crtc)
9286 /* Src/dst size and scaling updates. */
9287 if (old_other_state->src_w != new_other_state->src_w ||
9288 old_other_state->src_h != new_other_state->src_h ||
9289 old_other_state->crtc_w != new_other_state->crtc_w ||
9290 old_other_state->crtc_h != new_other_state->crtc_h)
9293 /* Rotation / mirroring updates. */
9294 if (old_other_state->rotation != new_other_state->rotation)
9297 /* Blending updates. */
9298 if (old_other_state->pixel_blend_mode !=
9299 new_other_state->pixel_blend_mode)
9302 /* Alpha updates. */
9303 if (old_other_state->alpha != new_other_state->alpha)
9306 /* Colorspace changes. */
9307 if (old_other_state->color_range != new_other_state->color_range ||
9308 old_other_state->color_encoding != new_other_state->color_encoding)
9311 /* Framebuffer checks fall at the end. */
9312 if (!old_other_state->fb || !new_other_state->fb)
9315 /* Pixel format changes can require bandwidth updates. */
9316 if (old_other_state->fb->format != new_other_state->fb->format)
9319 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9320 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9322 /* Tiling and DCC changes also require bandwidth updates. */
9323 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9324 old_afb->base.modifier != new_afb->base.modifier)
9331 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9332 struct drm_plane_state *new_plane_state,
9333 struct drm_framebuffer *fb)
9335 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9336 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9340 if (fb->width > new_acrtc->max_cursor_width ||
9341 fb->height > new_acrtc->max_cursor_height) {
9342 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9343 new_plane_state->fb->width,
9344 new_plane_state->fb->height);
9347 if (new_plane_state->src_w != fb->width << 16 ||
9348 new_plane_state->src_h != fb->height << 16) {
9349 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9353 /* Pitch in pixels */
9354 pitch = fb->pitches[0] / fb->format->cpp[0];
9356 if (fb->width != pitch) {
9357 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9366 /* FB pitch is supported by cursor plane */
9369 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9373 /* Core DRM takes care of checking FB modifiers, so we only need to
9374 * check tiling flags when the FB doesn't have a modifier. */
9375 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9376 if (adev->family < AMDGPU_FAMILY_AI) {
9377 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9378 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9379 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9381 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9384 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9392 static int dm_update_plane_state(struct dc *dc,
9393 struct drm_atomic_state *state,
9394 struct drm_plane *plane,
9395 struct drm_plane_state *old_plane_state,
9396 struct drm_plane_state *new_plane_state,
9398 bool *lock_and_validation_needed)
9401 struct dm_atomic_state *dm_state = NULL;
9402 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9403 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9404 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9405 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9406 struct amdgpu_crtc *new_acrtc;
9411 new_plane_crtc = new_plane_state->crtc;
9412 old_plane_crtc = old_plane_state->crtc;
9413 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9414 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9416 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9417 if (!enable || !new_plane_crtc ||
9418 drm_atomic_plane_disabling(plane->state, new_plane_state))
9421 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9423 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9424 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9428 if (new_plane_state->fb) {
9429 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9430 new_plane_state->fb);
9438 needs_reset = should_reset_plane(state, plane, old_plane_state,
9441 /* Remove any changed/removed planes */
9446 if (!old_plane_crtc)
9449 old_crtc_state = drm_atomic_get_old_crtc_state(
9450 state, old_plane_crtc);
9451 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9453 if (!dm_old_crtc_state->stream)
9456 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9457 plane->base.id, old_plane_crtc->base.id);
9459 ret = dm_atomic_get_state(state, &dm_state);
9463 if (!dc_remove_plane_from_context(
9465 dm_old_crtc_state->stream,
9466 dm_old_plane_state->dc_state,
9467 dm_state->context)) {
9473 dc_plane_state_release(dm_old_plane_state->dc_state);
9474 dm_new_plane_state->dc_state = NULL;
9476 *lock_and_validation_needed = true;
9478 } else { /* Add new planes */
9479 struct dc_plane_state *dc_new_plane_state;
9481 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9484 if (!new_plane_crtc)
9487 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9488 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9490 if (!dm_new_crtc_state->stream)
9496 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9500 WARN_ON(dm_new_plane_state->dc_state);
9502 dc_new_plane_state = dc_create_plane_state(dc);
9503 if (!dc_new_plane_state)
9506 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9507 plane->base.id, new_plane_crtc->base.id);
9509 ret = fill_dc_plane_attributes(
9510 drm_to_adev(new_plane_crtc->dev),
9515 dc_plane_state_release(dc_new_plane_state);
9519 ret = dm_atomic_get_state(state, &dm_state);
9521 dc_plane_state_release(dc_new_plane_state);
9526 * Any atomic check errors that occur after this will
9527 * not need a release. The plane state will be attached
9528 * to the stream, and therefore part of the atomic
9529 * state. It'll be released when the atomic state is
9532 if (!dc_add_plane_to_context(
9534 dm_new_crtc_state->stream,
9536 dm_state->context)) {
9538 dc_plane_state_release(dc_new_plane_state);
9542 dm_new_plane_state->dc_state = dc_new_plane_state;
9544 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9546 /* Tell DC to do a full surface update every time there
9547 * is a plane change. Inefficient, but works for now.
9549 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9551 *lock_and_validation_needed = true;
9558 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9559 int *src_w, int *src_h)
9561 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9562 case DRM_MODE_ROTATE_90:
9563 case DRM_MODE_ROTATE_270:
9564 *src_w = plane_state->src_h >> 16;
9565 *src_h = plane_state->src_w >> 16;
9567 case DRM_MODE_ROTATE_0:
9568 case DRM_MODE_ROTATE_180:
9570 *src_w = plane_state->src_w >> 16;
9571 *src_h = plane_state->src_h >> 16;
9576 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9577 struct drm_crtc *crtc,
9578 struct drm_crtc_state *new_crtc_state)
9580 struct drm_plane *cursor = crtc->cursor, *underlying;
9581 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9583 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9584 int cursor_src_w, cursor_src_h;
9585 int underlying_src_w, underlying_src_h;
9587 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9588 * cursor per pipe but it's going to inherit the scaling and
9589 * positioning from the underlying pipe. Check the cursor plane's
9590 * blending properties match the underlying planes'. */
9592 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9593 if (!new_cursor_state || !new_cursor_state->fb) {
9597 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9598 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9599 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9601 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9602 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9603 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9606 /* Ignore disabled planes */
9607 if (!new_underlying_state->fb)
9610 dm_get_oriented_plane_size(new_underlying_state,
9611 &underlying_src_w, &underlying_src_h);
9612 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9613 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9615 if (cursor_scale_w != underlying_scale_w ||
9616 cursor_scale_h != underlying_scale_h) {
9617 drm_dbg_atomic(crtc->dev,
9618 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9619 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9623 /* If this plane covers the whole CRTC, no need to check planes underneath */
9624 if (new_underlying_state->crtc_x <= 0 &&
9625 new_underlying_state->crtc_y <= 0 &&
9626 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9627 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9634 #if defined(CONFIG_DRM_AMD_DC_DCN)
9635 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9637 struct drm_connector *connector;
9638 struct drm_connector_state *conn_state, *old_conn_state;
9639 struct amdgpu_dm_connector *aconnector = NULL;
9641 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9642 if (!conn_state->crtc)
9643 conn_state = old_conn_state;
9645 if (conn_state->crtc != crtc)
9648 aconnector = to_amdgpu_dm_connector(connector);
9649 if (!aconnector->mst_output_port || !aconnector->mst_root)
9658 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9663 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9665 * @dev: The DRM device
9666 * @state: The atomic state to commit
9668 * Validate that the given atomic state is programmable by DC into hardware.
9669 * This involves constructing a &struct dc_state reflecting the new hardware
9670 * state we wish to commit, then querying DC to see if it is programmable. It's
9671 * important not to modify the existing DC state. Otherwise, atomic_check
9672 * may unexpectedly commit hardware changes.
9674 * When validating the DC state, it's important that the right locks are
9675 * acquired. For full updates case which removes/adds/updates streams on one
9676 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9677 * that any such full update commit will wait for completion of any outstanding
9678 * flip using DRMs synchronization events.
9680 * Note that DM adds the affected connectors for all CRTCs in state, when that
9681 * might not seem necessary. This is because DC stream creation requires the
9682 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9683 * be possible but non-trivial - a possible TODO item.
9685 * Return: -Error code if validation failed.
9687 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9688 struct drm_atomic_state *state)
9690 struct amdgpu_device *adev = drm_to_adev(dev);
9691 struct dm_atomic_state *dm_state = NULL;
9692 struct dc *dc = adev->dm.dc;
9693 struct drm_connector *connector;
9694 struct drm_connector_state *old_con_state, *new_con_state;
9695 struct drm_crtc *crtc;
9696 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9697 struct drm_plane *plane;
9698 struct drm_plane_state *old_plane_state, *new_plane_state;
9699 enum dc_status status;
9701 bool lock_and_validation_needed = false;
9702 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9703 #if defined(CONFIG_DRM_AMD_DC_DCN)
9704 struct drm_dp_mst_topology_mgr *mgr;
9705 struct drm_dp_mst_topology_state *mst_state;
9706 struct dsc_mst_fairness_vars vars[MAX_PIPES];
9709 trace_amdgpu_dm_atomic_check_begin(state);
9711 ret = drm_atomic_helper_check_modeset(dev, state);
9713 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9717 /* Check connector changes */
9718 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9719 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9720 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9722 /* Skip connectors that are disabled or part of modeset already. */
9723 if (!new_con_state->crtc)
9726 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9727 if (IS_ERR(new_crtc_state)) {
9728 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9729 ret = PTR_ERR(new_crtc_state);
9733 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9734 dm_old_con_state->scaling != dm_new_con_state->scaling)
9735 new_crtc_state->connectors_changed = true;
9738 #if defined(CONFIG_DRM_AMD_DC_DCN)
9739 if (dc_resource_is_dsc_encoding_supported(dc)) {
9740 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9741 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9742 ret = add_affected_mst_dsc_crtcs(state, crtc);
9744 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9751 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9752 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9754 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9755 !new_crtc_state->color_mgmt_changed &&
9756 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9757 dm_old_crtc_state->dsc_force_changed == false)
9760 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9762 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9766 if (!new_crtc_state->enable)
9769 ret = drm_atomic_add_affected_connectors(state, crtc);
9771 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9775 ret = drm_atomic_add_affected_planes(state, crtc);
9777 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9781 if (dm_old_crtc_state->dsc_force_changed)
9782 new_crtc_state->mode_changed = true;
9786 * Add all primary and overlay planes on the CRTC to the state
9787 * whenever a plane is enabled to maintain correct z-ordering
9788 * and to enable fast surface updates.
9790 drm_for_each_crtc(crtc, dev) {
9791 bool modified = false;
9793 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9794 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9797 if (new_plane_state->crtc == crtc ||
9798 old_plane_state->crtc == crtc) {
9807 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9808 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9812 drm_atomic_get_plane_state(state, plane);
9814 if (IS_ERR(new_plane_state)) {
9815 ret = PTR_ERR(new_plane_state);
9816 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9823 * DC consults the zpos (layer_index in DC terminology) to determine the
9824 * hw plane on which to enable the hw cursor (see
9825 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9826 * atomic state, so call drm helper to normalize zpos.
9828 drm_atomic_normalize_zpos(dev, state);
9830 /* Remove exiting planes if they are modified */
9831 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9832 ret = dm_update_plane_state(dc, state, plane,
9836 &lock_and_validation_needed);
9838 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9843 /* Disable all crtcs which require disable */
9844 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9845 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9849 &lock_and_validation_needed);
9851 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
9856 /* Enable all crtcs which require enable */
9857 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9858 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9862 &lock_and_validation_needed);
9864 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
9869 /* Add new/modified planes */
9870 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9871 ret = dm_update_plane_state(dc, state, plane,
9875 &lock_and_validation_needed);
9877 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9882 #if defined(CONFIG_DRM_AMD_DC_DCN)
9883 if (dc_resource_is_dsc_encoding_supported(dc)) {
9884 ret = pre_validate_dsc(state, &dm_state, vars);
9890 /* Run this here since we want to validate the streams we created */
9891 ret = drm_atomic_helper_check_planes(dev, state);
9893 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
9897 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9898 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9899 if (dm_new_crtc_state->mpo_requested)
9900 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9903 /* Check cursor planes scaling */
9904 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9905 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9907 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
9912 if (state->legacy_cursor_update) {
9914 * This is a fast cursor update coming from the plane update
9915 * helper, check if it can be done asynchronously for better
9918 state->async_update =
9919 !drm_atomic_helper_async_check(dev, state);
9922 * Skip the remaining global validation if this is an async
9923 * update. Cursor updates can be done without affecting
9924 * state or bandwidth calcs and this avoids the performance
9925 * penalty of locking the private state object and
9926 * allocating a new dc_state.
9928 if (state->async_update)
9932 /* Check scaling and underscan changes*/
9933 /* TODO Removed scaling changes validation due to inability to commit
9934 * new stream into context w\o causing full reset. Need to
9935 * decide how to handle.
9937 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9938 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9939 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9940 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9942 /* Skip any modesets/resets */
9943 if (!acrtc || drm_atomic_crtc_needs_modeset(
9944 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9947 /* Skip any thing not scale or underscan changes */
9948 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9951 lock_and_validation_needed = true;
9954 #if defined(CONFIG_DRM_AMD_DC_DCN)
9955 /* set the slot info for each mst_state based on the link encoding format */
9956 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
9957 struct amdgpu_dm_connector *aconnector;
9958 struct drm_connector *connector;
9959 struct drm_connector_list_iter iter;
9962 drm_connector_list_iter_begin(dev, &iter);
9963 drm_for_each_connector_iter(connector, &iter) {
9964 if (connector->index == mst_state->mgr->conn_base_id) {
9965 aconnector = to_amdgpu_dm_connector(connector);
9966 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
9967 drm_dp_mst_update_slots(mst_state, link_coding_cap);
9972 drm_connector_list_iter_end(&iter);
9977 * Streams and planes are reset when there are changes that affect
9978 * bandwidth. Anything that affects bandwidth needs to go through
9979 * DC global validation to ensure that the configuration can be applied
9982 * We have to currently stall out here in atomic_check for outstanding
9983 * commits to finish in this case because our IRQ handlers reference
9984 * DRM state directly - we can end up disabling interrupts too early
9987 * TODO: Remove this stall and drop DM state private objects.
9989 if (lock_and_validation_needed) {
9990 ret = dm_atomic_get_state(state, &dm_state);
9992 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
9996 ret = do_aquire_global_lock(dev, state);
9998 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10002 #if defined(CONFIG_DRM_AMD_DC_DCN)
10003 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10005 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10009 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10011 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10017 * Perform validation of MST topology in the state:
10018 * We need to perform MST atomic check before calling
10019 * dc_validate_global_state(), or there is a chance
10020 * to get stuck in an infinite loop and hang eventually.
10022 ret = drm_dp_mst_atomic_check(state);
10024 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10027 status = dc_validate_global_state(dc, dm_state->context, true);
10028 if (status != DC_OK) {
10029 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10030 dc_status_to_str(status), status);
10036 * The commit is a fast update. Fast updates shouldn't change
10037 * the DC context, affect global validation, and can have their
10038 * commit work done in parallel with other commits not touching
10039 * the same resource. If we have a new DC context as part of
10040 * the DM atomic state from validation we need to free it and
10041 * retain the existing one instead.
10043 * Furthermore, since the DM atomic state only contains the DC
10044 * context and can safely be annulled, we can free the state
10045 * and clear the associated private object now to free
10046 * some memory and avoid a possible use-after-free later.
10049 for (i = 0; i < state->num_private_objs; i++) {
10050 struct drm_private_obj *obj = state->private_objs[i].ptr;
10052 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10053 int j = state->num_private_objs-1;
10055 dm_atomic_destroy_state(obj,
10056 state->private_objs[i].state);
10058 /* If i is not at the end of the array then the
10059 * last element needs to be moved to where i was
10060 * before the array can safely be truncated.
10063 state->private_objs[i] =
10064 state->private_objs[j];
10066 state->private_objs[j].ptr = NULL;
10067 state->private_objs[j].state = NULL;
10068 state->private_objs[j].old_state = NULL;
10069 state->private_objs[j].new_state = NULL;
10071 state->num_private_objs = j;
10077 /* Store the overall update type for use later in atomic check. */
10078 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10079 struct dm_crtc_state *dm_new_crtc_state =
10080 to_dm_crtc_state(new_crtc_state);
10082 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10087 /* Must be success */
10090 trace_amdgpu_dm_atomic_check_finish(state, ret);
10095 if (ret == -EDEADLK)
10096 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10097 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10098 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10100 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10102 trace_amdgpu_dm_atomic_check_finish(state, ret);
10107 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10108 struct amdgpu_dm_connector *amdgpu_dm_connector)
10111 bool capable = false;
10113 if (amdgpu_dm_connector->dc_link &&
10114 dm_helpers_dp_read_dpcd(
10116 amdgpu_dm_connector->dc_link,
10117 DP_DOWN_STREAM_PORT_COUNT,
10119 sizeof(dpcd_data))) {
10120 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10126 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10127 unsigned int offset,
10128 unsigned int total_length,
10130 unsigned int length,
10131 struct amdgpu_hdmi_vsdb_info *vsdb)
10134 union dmub_rb_cmd cmd;
10135 struct dmub_cmd_send_edid_cea *input;
10136 struct dmub_cmd_edid_cea_output *output;
10138 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10141 memset(&cmd, 0, sizeof(cmd));
10143 input = &cmd.edid_cea.data.input;
10145 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10146 cmd.edid_cea.header.sub_type = 0;
10147 cmd.edid_cea.header.payload_bytes =
10148 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10149 input->offset = offset;
10150 input->length = length;
10151 input->cea_total_length = total_length;
10152 memcpy(input->payload, data, length);
10154 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10156 DRM_ERROR("EDID CEA parser failed\n");
10160 output = &cmd.edid_cea.data.output;
10162 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10163 if (!output->ack.success) {
10164 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10165 output->ack.offset);
10167 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10168 if (!output->amd_vsdb.vsdb_found)
10171 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10172 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10173 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10174 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10176 DRM_WARN("Unknown EDID CEA parser results\n");
10183 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10184 u8 *edid_ext, int len,
10185 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10189 /* send extension block to DMCU for parsing */
10190 for (i = 0; i < len; i += 8) {
10194 /* send 8 bytes a time */
10195 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10199 /* EDID block sent completed, expect result */
10200 int version, min_rate, max_rate;
10202 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10204 /* amd vsdb found */
10205 vsdb_info->freesync_supported = 1;
10206 vsdb_info->amd_vsdb_version = version;
10207 vsdb_info->min_refresh_rate_hz = min_rate;
10208 vsdb_info->max_refresh_rate_hz = max_rate;
10216 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10224 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10225 u8 *edid_ext, int len,
10226 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10230 /* send extension block to DMCU for parsing */
10231 for (i = 0; i < len; i += 8) {
10232 /* send 8 bytes a time */
10233 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10237 return vsdb_info->freesync_supported;
10240 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10241 u8 *edid_ext, int len,
10242 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10244 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10247 mutex_lock(&adev->dm.dc_lock);
10248 if (adev->dm.dmub_srv)
10249 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10251 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10252 mutex_unlock(&adev->dm.dc_lock);
10256 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10257 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10259 u8 *edid_ext = NULL;
10261 bool valid_vsdb_found = false;
10263 /*----- drm_find_cea_extension() -----*/
10264 /* No EDID or EDID extensions */
10265 if (edid == NULL || edid->extensions == 0)
10268 /* Find CEA extension */
10269 for (i = 0; i < edid->extensions; i++) {
10270 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10271 if (edid_ext[0] == CEA_EXT)
10275 if (i == edid->extensions)
10278 /*----- cea_db_offsets() -----*/
10279 if (edid_ext[0] != CEA_EXT)
10282 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10284 return valid_vsdb_found ? i : -ENODEV;
10288 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10290 * @connector: Connector to query.
10291 * @edid: EDID from monitor
10293 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10294 * track of some of the display information in the internal data struct used by
10295 * amdgpu_dm. This function checks which type of connector we need to set the
10296 * FreeSync parameters.
10298 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10302 struct detailed_timing *timing;
10303 struct detailed_non_pixel *data;
10304 struct detailed_data_monitor_range *range;
10305 struct amdgpu_dm_connector *amdgpu_dm_connector =
10306 to_amdgpu_dm_connector(connector);
10307 struct dm_connector_state *dm_con_state = NULL;
10308 struct dc_sink *sink;
10310 struct drm_device *dev = connector->dev;
10311 struct amdgpu_device *adev = drm_to_adev(dev);
10312 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10313 bool freesync_capable = false;
10315 if (!connector->state) {
10316 DRM_ERROR("%s - Connector has no state", __func__);
10320 sink = amdgpu_dm_connector->dc_sink ?
10321 amdgpu_dm_connector->dc_sink :
10322 amdgpu_dm_connector->dc_em_sink;
10324 if (!edid || !sink) {
10325 dm_con_state = to_dm_connector_state(connector->state);
10327 amdgpu_dm_connector->min_vfreq = 0;
10328 amdgpu_dm_connector->max_vfreq = 0;
10329 amdgpu_dm_connector->pixel_clock_mhz = 0;
10330 connector->display_info.monitor_range.min_vfreq = 0;
10331 connector->display_info.monitor_range.max_vfreq = 0;
10332 freesync_capable = false;
10337 dm_con_state = to_dm_connector_state(connector->state);
10339 if (!adev->dm.freesync_module)
10342 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10343 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10344 bool edid_check_required = false;
10347 edid_check_required = is_dp_capable_without_timing_msa(
10349 amdgpu_dm_connector);
10352 if (edid_check_required == true && (edid->version > 1 ||
10353 (edid->version == 1 && edid->revision > 1))) {
10354 for (i = 0; i < 4; i++) {
10356 timing = &edid->detailed_timings[i];
10357 data = &timing->data.other_data;
10358 range = &data->data.range;
10360 * Check if monitor has continuous frequency mode
10362 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10365 * Check for flag range limits only. If flag == 1 then
10366 * no additional timing information provided.
10367 * Default GTF, GTF Secondary curve and CVT are not
10370 if (range->flags != 1)
10373 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10374 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10375 amdgpu_dm_connector->pixel_clock_mhz =
10376 range->pixel_clock_mhz * 10;
10378 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10379 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10384 if (amdgpu_dm_connector->max_vfreq -
10385 amdgpu_dm_connector->min_vfreq > 10) {
10387 freesync_capable = true;
10390 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10391 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10392 if (i >= 0 && vsdb_info.freesync_supported) {
10393 timing = &edid->detailed_timings[i];
10394 data = &timing->data.other_data;
10396 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10397 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10398 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10399 freesync_capable = true;
10401 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10402 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10408 dm_con_state->freesync_capable = freesync_capable;
10410 if (connector->vrr_capable_property)
10411 drm_connector_set_vrr_capable_property(connector,
10415 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10417 struct amdgpu_device *adev = drm_to_adev(dev);
10418 struct dc *dc = adev->dm.dc;
10421 mutex_lock(&adev->dm.dc_lock);
10422 if (dc->current_state) {
10423 for (i = 0; i < dc->current_state->stream_count; ++i)
10424 dc->current_state->streams[i]
10425 ->triggered_crtc_reset.enabled =
10426 adev->dm.force_timing_sync;
10428 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10429 dc_trigger_sync(dc, dc->current_state);
10431 mutex_unlock(&adev->dm.dc_lock);
10434 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10435 u32 value, const char *func_name)
10437 #ifdef DM_CHECK_ADDR_0
10438 if (address == 0) {
10439 DC_ERR("invalid register write. address = 0");
10443 cgs_write_register(ctx->cgs_device, address, value);
10444 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10447 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10448 const char *func_name)
10451 #ifdef DM_CHECK_ADDR_0
10452 if (address == 0) {
10453 DC_ERR("invalid register read; address = 0\n");
10458 if (ctx->dmub_srv &&
10459 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10460 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10465 value = cgs_read_register(ctx->cgs_device, address);
10467 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10472 int amdgpu_dm_process_dmub_aux_transfer_sync(
10473 struct dc_context *ctx,
10474 unsigned int link_index,
10475 struct aux_payload *payload,
10476 enum aux_return_code_type *operation_result)
10478 struct amdgpu_device *adev = ctx->driver_context;
10479 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10482 mutex_lock(&adev->dm.dpia_aux_lock);
10483 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10484 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10488 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10489 DRM_ERROR("wait_for_completion_timeout timeout!");
10490 *operation_result = AUX_RET_ERROR_TIMEOUT;
10494 if (p_notify->result != AUX_RET_SUCCESS) {
10496 * Transient states before tunneling is enabled could
10497 * lead to this error. We can ignore this for now.
10499 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10500 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10501 payload->address, payload->length,
10504 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10509 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10510 if (!payload->write && p_notify->aux_reply.length &&
10511 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10513 if (payload->length != p_notify->aux_reply.length) {
10514 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10515 p_notify->aux_reply.length,
10516 payload->address, payload->length);
10517 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10521 memcpy(payload->data, p_notify->aux_reply.data,
10522 p_notify->aux_reply.length);
10526 ret = p_notify->aux_reply.length;
10527 *operation_result = p_notify->result;
10529 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10530 mutex_unlock(&adev->dm.dpia_aux_lock);
10534 int amdgpu_dm_process_dmub_set_config_sync(
10535 struct dc_context *ctx,
10536 unsigned int link_index,
10537 struct set_config_cmd_payload *payload,
10538 enum set_config_status *operation_result)
10540 struct amdgpu_device *adev = ctx->driver_context;
10541 bool is_cmd_complete;
10544 mutex_lock(&adev->dm.dpia_aux_lock);
10545 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10546 link_index, payload, adev->dm.dmub_notify);
10548 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10550 *operation_result = adev->dm.dmub_notify->sc_status;
10552 DRM_ERROR("wait_for_completion_timeout timeout!");
10554 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10557 if (!is_cmd_complete)
10558 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10559 mutex_unlock(&adev->dm.dpia_aux_lock);
10564 * Check whether seamless boot is supported.
10566 * So far we only support seamless boot on CHIP_VANGOGH.
10567 * If everything goes well, we may consider expanding
10568 * seamless boot to other ASICs.
10570 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10572 switch (adev->ip_versions[DCE_HWIP][0]) {
10573 case IP_VERSION(3, 0, 1):
10574 if (!adev->mman.keep_stolen_vga_memory)