2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc/inc/core_types.h"
32 #include "dal_asic_id.h"
33 #include "dmub/dmub_srv.h"
34 #include "dc/inc/hw/dmcu.h"
35 #include "dc/inc/hw/abm.h"
36 #include "dc/dc_dmub_srv.h"
37 #include "amdgpu_dm_trace.h"
41 #include "amdgpu_display.h"
42 #include "amdgpu_ucode.h"
44 #include "amdgpu_dm.h"
45 #ifdef CONFIG_DRM_AMD_DC_HDCP
46 #include "amdgpu_dm_hdcp.h"
47 #include <drm/drm_hdcp.h>
49 #include "amdgpu_pm.h"
51 #include "amd_shared.h"
52 #include "amdgpu_dm_irq.h"
53 #include "dm_helpers.h"
54 #include "amdgpu_dm_mst_types.h"
55 #if defined(CONFIG_DEBUG_FS)
56 #include "amdgpu_dm_debugfs.h"
59 #include "ivsrcid/ivsrcid_vislands30.h"
61 #include <linux/module.h>
62 #include <linux/moduleparam.h>
63 #include <linux/types.h>
64 #include <linux/pm_runtime.h>
65 #include <linux/pci.h>
66 #include <linux/firmware.h>
67 #include <linux/component.h>
69 #include <drm/drm_atomic.h>
70 #include <drm/drm_atomic_uapi.h>
71 #include <drm/drm_atomic_helper.h>
72 #include <drm/drm_dp_mst_helper.h>
73 #include <drm/drm_fb_helper.h>
74 #include <drm/drm_fourcc.h>
75 #include <drm/drm_edid.h>
76 #include <drm/drm_vblank.h>
77 #include <drm/drm_audio_component.h>
78 #include <drm/drm_hdcp.h>
80 #if defined(CONFIG_DRM_AMD_DC_DCN)
81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
83 #include "dcn/dcn_1_0_offset.h"
84 #include "dcn/dcn_1_0_sh_mask.h"
85 #include "soc15_hw_ip.h"
86 #include "vega10_ip_offset.h"
88 #include "soc15_common.h"
91 #include "modules/inc/mod_freesync.h"
92 #include "modules/power/power_helpers.h"
93 #include "modules/inc/mod_info_packet.h"
95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
97 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
98 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
99 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
100 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
101 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
102 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
103 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
104 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
105 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
106 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
108 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
109 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
111 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
112 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
114 /* Number of bytes in PSP header for firmware. */
115 #define PSP_HEADER_BYTES 0x100
117 /* Number of bytes in PSP footer for firmware. */
118 #define PSP_FOOTER_BYTES 0x100
123 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
124 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
125 * requests into DC requests, and DC responses into DRM responses.
127 * The root control structure is &struct amdgpu_display_manager.
130 /* basic init/fini API */
131 static int amdgpu_dm_init(struct amdgpu_device *adev);
132 static void amdgpu_dm_fini(struct amdgpu_device *adev);
134 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
136 switch (link->dpcd_caps.dongle_type) {
137 case DISPLAY_DONGLE_NONE:
138 return DRM_MODE_SUBCONNECTOR_Native;
139 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
140 return DRM_MODE_SUBCONNECTOR_VGA;
141 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
142 case DISPLAY_DONGLE_DP_DVI_DONGLE:
143 return DRM_MODE_SUBCONNECTOR_DVID;
144 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
145 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
146 return DRM_MODE_SUBCONNECTOR_HDMIA;
147 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
149 return DRM_MODE_SUBCONNECTOR_Unknown;
153 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
155 struct dc_link *link = aconnector->dc_link;
156 struct drm_connector *connector = &aconnector->base;
157 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
159 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
162 if (aconnector->dc_sink)
163 subconnector = get_subconnector_type(link);
165 drm_object_property_set_value(&connector->base,
166 connector->dev->mode_config.dp_subconnector_property,
171 * initializes drm_device display related structures, based on the information
172 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
173 * drm_encoder, drm_mode_config
175 * Returns 0 on success
177 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
178 /* removes and deallocates the drm structures, created by the above function */
179 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
181 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
182 struct drm_plane *plane,
183 unsigned long possible_crtcs,
184 const struct dc_plane_cap *plane_cap);
185 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
186 struct drm_plane *plane,
187 uint32_t link_index);
188 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
189 struct amdgpu_dm_connector *amdgpu_dm_connector,
191 struct amdgpu_encoder *amdgpu_encoder);
192 static int amdgpu_dm_encoder_init(struct drm_device *dev,
193 struct amdgpu_encoder *aencoder,
194 uint32_t link_index);
196 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
198 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
200 static int amdgpu_dm_atomic_check(struct drm_device *dev,
201 struct drm_atomic_state *state);
203 static void handle_cursor_update(struct drm_plane *plane,
204 struct drm_plane_state *old_plane_state);
206 static void amdgpu_dm_set_psr_caps(struct dc_link *link);
207 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
208 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
209 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
210 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
212 static const struct drm_format_info *
213 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
216 * dm_vblank_get_counter
219 * Get counter for number of vertical blanks
222 * struct amdgpu_device *adev - [in] desired amdgpu device
223 * int disp_idx - [in] which CRTC to get the counter from
226 * Counter for vertical blanks
228 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
230 if (crtc >= adev->mode_info.num_crtc)
233 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
235 if (acrtc->dm_irq_params.stream == NULL) {
236 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
241 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
245 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
246 u32 *vbl, u32 *position)
248 uint32_t v_blank_start, v_blank_end, h_position, v_position;
250 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
253 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
255 if (acrtc->dm_irq_params.stream == NULL) {
256 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
262 * TODO rework base driver to use values directly.
263 * for now parse it back into reg-format
265 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
271 *position = v_position | (h_position << 16);
272 *vbl = v_blank_start | (v_blank_end << 16);
278 static bool dm_is_idle(void *handle)
284 static int dm_wait_for_idle(void *handle)
290 static bool dm_check_soft_reset(void *handle)
295 static int dm_soft_reset(void *handle)
301 static struct amdgpu_crtc *
302 get_crtc_by_otg_inst(struct amdgpu_device *adev,
305 struct drm_device *dev = adev_to_drm(adev);
306 struct drm_crtc *crtc;
307 struct amdgpu_crtc *amdgpu_crtc;
309 if (otg_inst == -1) {
311 return adev->mode_info.crtcs[0];
314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
315 amdgpu_crtc = to_amdgpu_crtc(crtc);
317 if (amdgpu_crtc->otg_inst == otg_inst)
324 static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
326 return acrtc->dm_irq_params.freesync_config.state ==
327 VRR_STATE_ACTIVE_VARIABLE ||
328 acrtc->dm_irq_params.freesync_config.state ==
329 VRR_STATE_ACTIVE_FIXED;
332 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
334 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
335 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
339 * dm_pflip_high_irq() - Handle pageflip interrupt
340 * @interrupt_params: ignored
342 * Handles the pageflip interrupt by notifying all interested parties
343 * that the pageflip has been completed.
345 static void dm_pflip_high_irq(void *interrupt_params)
347 struct amdgpu_crtc *amdgpu_crtc;
348 struct common_irq_params *irq_params = interrupt_params;
349 struct amdgpu_device *adev = irq_params->adev;
351 struct drm_pending_vblank_event *e;
352 uint32_t vpos, hpos, v_blank_start, v_blank_end;
355 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
357 /* IRQ could occur when in initial stage */
358 /* TODO work and BO cleanup */
359 if (amdgpu_crtc == NULL) {
360 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
364 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
366 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
367 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
368 amdgpu_crtc->pflip_status,
369 AMDGPU_FLIP_SUBMITTED,
370 amdgpu_crtc->crtc_id,
372 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
376 /* page flip completed. */
377 e = amdgpu_crtc->event;
378 amdgpu_crtc->event = NULL;
383 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
385 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
387 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
388 &v_blank_end, &hpos, &vpos) ||
389 (vpos < v_blank_start)) {
390 /* Update to correct count and vblank timestamp if racing with
391 * vblank irq. This also updates to the correct vblank timestamp
392 * even in VRR mode, as scanout is past the front-porch atm.
394 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
396 /* Wake up userspace by sending the pageflip event with proper
397 * count and timestamp of vblank of flip completion.
400 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
402 /* Event sent, so done with vblank for this flip */
403 drm_crtc_vblank_put(&amdgpu_crtc->base);
406 /* VRR active and inside front-porch: vblank count and
407 * timestamp for pageflip event will only be up to date after
408 * drm_crtc_handle_vblank() has been executed from late vblank
409 * irq handler after start of back-porch (vline 0). We queue the
410 * pageflip event for send-out by drm_crtc_handle_vblank() with
411 * updated timestamp and count, once it runs after us.
413 * We need to open-code this instead of using the helper
414 * drm_crtc_arm_vblank_event(), as that helper would
415 * call drm_crtc_accurate_vblank_count(), which we must
416 * not call in VRR mode while we are in front-porch!
419 /* sequence will be replaced by real count during send-out. */
420 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
421 e->pipe = amdgpu_crtc->crtc_id;
423 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
427 /* Keep track of vblank of this flip for flip throttling. We use the
428 * cooked hw counter, as that one incremented at start of this vblank
429 * of pageflip completion, so last_flip_vblank is the forbidden count
430 * for queueing new pageflips if vsync + VRR is enabled.
432 amdgpu_crtc->dm_irq_params.last_flip_vblank =
433 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
435 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
436 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
438 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
439 amdgpu_crtc->crtc_id, amdgpu_crtc,
440 vrr_active, (int) !e);
443 static void dm_vupdate_high_irq(void *interrupt_params)
445 struct common_irq_params *irq_params = interrupt_params;
446 struct amdgpu_device *adev = irq_params->adev;
447 struct amdgpu_crtc *acrtc;
451 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
454 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
456 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n",
460 /* Core vblank handling is done here after end of front-porch in
461 * vrr mode, as vblank timestamping will give valid results
462 * while now done after front-porch. This will also deliver
463 * page-flip completion events that have been queued to us
464 * if a pageflip happened inside front-porch.
467 drm_crtc_handle_vblank(&acrtc->base);
469 /* BTR processing for pre-DCE12 ASICs */
470 if (acrtc->dm_irq_params.stream &&
471 adev->family < AMDGPU_FAMILY_AI) {
472 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
473 mod_freesync_handle_v_update(
474 adev->dm.freesync_module,
475 acrtc->dm_irq_params.stream,
476 &acrtc->dm_irq_params.vrr_params);
478 dc_stream_adjust_vmin_vmax(
480 acrtc->dm_irq_params.stream,
481 &acrtc->dm_irq_params.vrr_params.adjust);
482 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
489 * dm_crtc_high_irq() - Handles CRTC interrupt
490 * @interrupt_params: used for determining the CRTC instance
492 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
495 static void dm_crtc_high_irq(void *interrupt_params)
497 struct common_irq_params *irq_params = interrupt_params;
498 struct amdgpu_device *adev = irq_params->adev;
499 struct amdgpu_crtc *acrtc;
503 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
507 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
509 DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
510 vrr_active, acrtc->dm_irq_params.active_planes);
513 * Core vblank handling at start of front-porch is only possible
514 * in non-vrr mode, as only there vblank timestamping will give
515 * valid results while done in front-porch. Otherwise defer it
516 * to dm_vupdate_high_irq after end of front-porch.
519 drm_crtc_handle_vblank(&acrtc->base);
522 * Following stuff must happen at start of vblank, for crc
523 * computation and below-the-range btr support in vrr mode.
525 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
527 /* BTR updates need to happen before VUPDATE on Vega and above. */
528 if (adev->family < AMDGPU_FAMILY_AI)
531 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
533 if (acrtc->dm_irq_params.stream &&
534 acrtc->dm_irq_params.vrr_params.supported &&
535 acrtc->dm_irq_params.freesync_config.state ==
536 VRR_STATE_ACTIVE_VARIABLE) {
537 mod_freesync_handle_v_update(adev->dm.freesync_module,
538 acrtc->dm_irq_params.stream,
539 &acrtc->dm_irq_params.vrr_params);
541 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
542 &acrtc->dm_irq_params.vrr_params.adjust);
546 * If there aren't any active_planes then DCH HUBP may be clock-gated.
547 * In that case, pageflip completion interrupts won't fire and pageflip
548 * completion events won't get delivered. Prevent this by sending
549 * pending pageflip events from here if a flip is still pending.
551 * If any planes are enabled, use dm_pflip_high_irq() instead, to
552 * avoid race conditions between flip programming and completion,
553 * which could cause too early flip completion events.
555 if (adev->family >= AMDGPU_FAMILY_RV &&
556 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
557 acrtc->dm_irq_params.active_planes == 0) {
559 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
561 drm_crtc_vblank_put(&acrtc->base);
563 acrtc->pflip_status = AMDGPU_FLIP_NONE;
566 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
569 static int dm_set_clockgating_state(void *handle,
570 enum amd_clockgating_state state)
575 static int dm_set_powergating_state(void *handle,
576 enum amd_powergating_state state)
581 /* Prototypes of private functions */
582 static int dm_early_init(void* handle);
584 /* Allocate memory for FBC compressed data */
585 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
587 struct drm_device *dev = connector->dev;
588 struct amdgpu_device *adev = drm_to_adev(dev);
589 struct dm_compressor_info *compressor = &adev->dm.compressor;
590 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
591 struct drm_display_mode *mode;
592 unsigned long max_size = 0;
594 if (adev->dm.dc->fbc_compressor == NULL)
597 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
600 if (compressor->bo_ptr)
604 list_for_each_entry(mode, &connector->modes, head) {
605 if (max_size < mode->htotal * mode->vtotal)
606 max_size = mode->htotal * mode->vtotal;
610 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
611 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
612 &compressor->gpu_addr, &compressor->cpu_addr);
615 DRM_ERROR("DM: Failed to initialize FBC\n");
617 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
618 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
625 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
626 int pipe, bool *enabled,
627 unsigned char *buf, int max_bytes)
629 struct drm_device *dev = dev_get_drvdata(kdev);
630 struct amdgpu_device *adev = drm_to_adev(dev);
631 struct drm_connector *connector;
632 struct drm_connector_list_iter conn_iter;
633 struct amdgpu_dm_connector *aconnector;
638 mutex_lock(&adev->dm.audio_lock);
640 drm_connector_list_iter_begin(dev, &conn_iter);
641 drm_for_each_connector_iter(connector, &conn_iter) {
642 aconnector = to_amdgpu_dm_connector(connector);
643 if (aconnector->audio_inst != port)
647 ret = drm_eld_size(connector->eld);
648 memcpy(buf, connector->eld, min(max_bytes, ret));
652 drm_connector_list_iter_end(&conn_iter);
654 mutex_unlock(&adev->dm.audio_lock);
656 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
661 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
662 .get_eld = amdgpu_dm_audio_component_get_eld,
665 static int amdgpu_dm_audio_component_bind(struct device *kdev,
666 struct device *hda_kdev, void *data)
668 struct drm_device *dev = dev_get_drvdata(kdev);
669 struct amdgpu_device *adev = drm_to_adev(dev);
670 struct drm_audio_component *acomp = data;
672 acomp->ops = &amdgpu_dm_audio_component_ops;
674 adev->dm.audio_component = acomp;
679 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
680 struct device *hda_kdev, void *data)
682 struct drm_device *dev = dev_get_drvdata(kdev);
683 struct amdgpu_device *adev = drm_to_adev(dev);
684 struct drm_audio_component *acomp = data;
688 adev->dm.audio_component = NULL;
691 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
692 .bind = amdgpu_dm_audio_component_bind,
693 .unbind = amdgpu_dm_audio_component_unbind,
696 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
703 adev->mode_info.audio.enabled = true;
705 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
707 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
708 adev->mode_info.audio.pin[i].channels = -1;
709 adev->mode_info.audio.pin[i].rate = -1;
710 adev->mode_info.audio.pin[i].bits_per_sample = -1;
711 adev->mode_info.audio.pin[i].status_bits = 0;
712 adev->mode_info.audio.pin[i].category_code = 0;
713 adev->mode_info.audio.pin[i].connected = false;
714 adev->mode_info.audio.pin[i].id =
715 adev->dm.dc->res_pool->audios[i]->inst;
716 adev->mode_info.audio.pin[i].offset = 0;
719 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
723 adev->dm.audio_registered = true;
728 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
733 if (!adev->mode_info.audio.enabled)
736 if (adev->dm.audio_registered) {
737 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
738 adev->dm.audio_registered = false;
741 /* TODO: Disable audio? */
743 adev->mode_info.audio.enabled = false;
746 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
748 struct drm_audio_component *acomp = adev->dm.audio_component;
750 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
751 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
753 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
758 static int dm_dmub_hw_init(struct amdgpu_device *adev)
760 const struct dmcub_firmware_header_v1_0 *hdr;
761 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
762 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
763 const struct firmware *dmub_fw = adev->dm.dmub_fw;
764 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
765 struct abm *abm = adev->dm.dc->res_pool->abm;
766 struct dmub_srv_hw_params hw_params;
767 enum dmub_status status;
768 const unsigned char *fw_inst_const, *fw_bss_data;
769 uint32_t i, fw_inst_const_size, fw_bss_data_size;
773 /* DMUB isn't supported on the ASIC. */
777 DRM_ERROR("No framebuffer info for DMUB service.\n");
782 /* Firmware required for DMUB support. */
783 DRM_ERROR("No firmware provided for DMUB.\n");
787 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
788 if (status != DMUB_STATUS_OK) {
789 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
793 if (!has_hw_support) {
794 DRM_INFO("DMUB unsupported on ASIC\n");
798 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
800 fw_inst_const = dmub_fw->data +
801 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
804 fw_bss_data = dmub_fw->data +
805 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
806 le32_to_cpu(hdr->inst_const_bytes);
808 /* Copy firmware and bios info into FB memory. */
809 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
810 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
812 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
814 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
815 * amdgpu_ucode_init_single_fw will load dmub firmware
816 * fw_inst_const part to cw0; otherwise, the firmware back door load
817 * will be done by dm_dmub_hw_init
819 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
820 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
824 if (fw_bss_data_size)
825 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
826 fw_bss_data, fw_bss_data_size);
828 /* Copy firmware bios info into FB memory. */
829 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
832 /* Reset regions that need to be reset. */
833 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
834 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
836 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
837 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
839 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
840 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
842 /* Initialize hardware. */
843 memset(&hw_params, 0, sizeof(hw_params));
844 hw_params.fb_base = adev->gmc.fb_start;
845 hw_params.fb_offset = adev->gmc.aper_base;
847 /* backdoor load firmware and trigger dmub running */
848 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
849 hw_params.load_inst_const = true;
852 hw_params.psp_version = dmcu->psp_version;
854 for (i = 0; i < fb_info->num_fb; ++i)
855 hw_params.fb[i] = &fb_info->fb[i];
857 status = dmub_srv_hw_init(dmub_srv, &hw_params);
858 if (status != DMUB_STATUS_OK) {
859 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
863 /* Wait for firmware load to finish. */
864 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
865 if (status != DMUB_STATUS_OK)
866 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
868 /* Init DMCU and ABM if available. */
870 dmcu->funcs->dmcu_init(dmcu);
871 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
874 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
875 if (!adev->dm.dc->ctx->dmub_srv) {
876 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
880 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
881 adev->dm.dmcub_fw_version);
886 #if defined(CONFIG_DRM_AMD_DC_DCN)
887 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
890 uint32_t logical_addr_low;
891 uint32_t logical_addr_high;
892 uint32_t agp_base, agp_bot, agp_top;
893 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
895 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
896 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
898 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
900 * Raven2 has a HW issue that it is unable to use the vram which
901 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
902 * workaround that increase system aperture high address (add 1)
903 * to get rid of the VM fault and hardware hang.
905 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
907 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
910 agp_bot = adev->gmc.agp_start >> 24;
911 agp_top = adev->gmc.agp_end >> 24;
914 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
915 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
916 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
917 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
918 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
919 page_table_base.low_part = lower_32_bits(pt_base);
921 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
922 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
924 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
925 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
926 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
928 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
929 pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
930 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
932 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
933 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
934 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
936 pa_config->is_hvm_enabled = 0;
940 #if defined(CONFIG_DRM_AMD_DC_DCN)
941 static void event_mall_stutter(struct work_struct *work)
944 struct vblank_workqueue *vblank_work = container_of(work, struct vblank_workqueue, mall_work);
945 struct amdgpu_display_manager *dm = vblank_work->dm;
947 mutex_lock(&dm->dc_lock);
949 if (vblank_work->enable)
950 dm->active_vblank_irq_count++;
952 dm->active_vblank_irq_count--;
955 dc_allow_idle_optimizations(
956 dm->dc, dm->active_vblank_irq_count == 0 ? true : false);
958 DRM_DEBUG_DRIVER("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
961 mutex_unlock(&dm->dc_lock);
964 static struct vblank_workqueue *vblank_create_workqueue(struct amdgpu_device *adev, struct dc *dc)
967 int max_caps = dc->caps.max_links;
968 struct vblank_workqueue *vblank_work;
971 vblank_work = kcalloc(max_caps, sizeof(*vblank_work), GFP_KERNEL);
972 if (ZERO_OR_NULL_PTR(vblank_work)) {
977 for (i = 0; i < max_caps; i++)
978 INIT_WORK(&vblank_work[i].mall_work, event_mall_stutter);
983 static int amdgpu_dm_init(struct amdgpu_device *adev)
985 struct dc_init_data init_data;
986 #ifdef CONFIG_DRM_AMD_DC_HDCP
987 struct dc_callback_init init_params;
991 adev->dm.ddev = adev_to_drm(adev);
992 adev->dm.adev = adev;
994 /* Zero all the fields */
995 memset(&init_data, 0, sizeof(init_data));
996 #ifdef CONFIG_DRM_AMD_DC_HDCP
997 memset(&init_params, 0, sizeof(init_params));
1000 mutex_init(&adev->dm.dc_lock);
1001 mutex_init(&adev->dm.audio_lock);
1002 #if defined(CONFIG_DRM_AMD_DC_DCN)
1003 spin_lock_init(&adev->dm.vblank_lock);
1006 if(amdgpu_dm_irq_init(adev)) {
1007 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1011 init_data.asic_id.chip_family = adev->family;
1013 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1014 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1016 init_data.asic_id.vram_width = adev->gmc.vram_width;
1017 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1018 init_data.asic_id.atombios_base_address =
1019 adev->mode_info.atom_context->bios;
1021 init_data.driver = adev;
1023 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1025 if (!adev->dm.cgs_device) {
1026 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1030 init_data.cgs_device = adev->dm.cgs_device;
1032 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1034 switch (adev->asic_type) {
1039 init_data.flags.gpu_vm_support = true;
1040 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1041 init_data.flags.disable_dmcu = true;
1043 #if defined(CONFIG_DRM_AMD_DC_DCN)
1045 init_data.flags.gpu_vm_support = true;
1052 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1053 init_data.flags.fbc_support = true;
1055 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1056 init_data.flags.multi_mon_pp_mclk_switch = true;
1058 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1059 init_data.flags.disable_fractional_pwm = true;
1061 init_data.flags.power_down_display_on_boot = true;
1063 /* Display Core create. */
1064 adev->dm.dc = dc_create(&init_data);
1067 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1069 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1073 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1074 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1075 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1078 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1079 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1081 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1082 adev->dm.dc->debug.disable_stutter = true;
1084 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1085 adev->dm.dc->debug.disable_dsc = true;
1087 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1088 adev->dm.dc->debug.disable_clock_gate = true;
1090 r = dm_dmub_hw_init(adev);
1092 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1096 dc_hardware_init(adev->dm.dc);
1098 #if defined(CONFIG_DRM_AMD_DC_DCN)
1099 if (adev->apu_flags) {
1100 struct dc_phy_addr_space_config pa_config;
1102 mmhub_read_system_context(adev, &pa_config);
1104 // Call the DC init_memory func
1105 dc_setup_system_context(adev->dm.dc, &pa_config);
1109 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1110 if (!adev->dm.freesync_module) {
1112 "amdgpu: failed to initialize freesync_module.\n");
1114 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1115 adev->dm.freesync_module);
1117 amdgpu_dm_init_color_mod();
1119 #if defined(CONFIG_DRM_AMD_DC_DCN)
1120 if (adev->dm.dc->caps.max_links > 0) {
1121 adev->dm.vblank_workqueue = vblank_create_workqueue(adev, adev->dm.dc);
1123 if (!adev->dm.vblank_workqueue)
1124 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1126 DRM_DEBUG_DRIVER("amdgpu: vblank_workqueue init done %p.\n", adev->dm.vblank_workqueue);
1130 #ifdef CONFIG_DRM_AMD_DC_HDCP
1131 if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
1132 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1134 if (!adev->dm.hdcp_workqueue)
1135 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1137 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1139 dc_init_callbacks(adev->dm.dc, &init_params);
1142 if (amdgpu_dm_initialize_drm_device(adev)) {
1144 "amdgpu: failed to initialize sw for display support.\n");
1148 /* create fake encoders for MST */
1149 dm_dp_create_fake_mst_encoders(adev);
1151 /* TODO: Add_display_info? */
1153 /* TODO use dynamic cursor width */
1154 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1155 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1157 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1159 "amdgpu: failed to initialize sw for display support.\n");
1164 DRM_DEBUG_DRIVER("KMS initialized.\n");
1168 amdgpu_dm_fini(adev);
1173 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1177 for (i = 0; i < adev->dm.display_indexes_num; i++) {
1178 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1181 amdgpu_dm_audio_fini(adev);
1183 amdgpu_dm_destroy_drm_device(&adev->dm);
1185 #ifdef CONFIG_DRM_AMD_DC_HDCP
1186 if (adev->dm.hdcp_workqueue) {
1187 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1188 adev->dm.hdcp_workqueue = NULL;
1192 dc_deinit_callbacks(adev->dm.dc);
1194 if (adev->dm.dc->ctx->dmub_srv) {
1195 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1196 adev->dm.dc->ctx->dmub_srv = NULL;
1199 if (adev->dm.dmub_bo)
1200 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1201 &adev->dm.dmub_bo_gpu_addr,
1202 &adev->dm.dmub_bo_cpu_addr);
1204 /* DC Destroy TODO: Replace destroy DAL */
1206 dc_destroy(&adev->dm.dc);
1208 * TODO: pageflip, vlank interrupt
1210 * amdgpu_dm_irq_fini(adev);
1213 if (adev->dm.cgs_device) {
1214 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1215 adev->dm.cgs_device = NULL;
1217 if (adev->dm.freesync_module) {
1218 mod_freesync_destroy(adev->dm.freesync_module);
1219 adev->dm.freesync_module = NULL;
1222 mutex_destroy(&adev->dm.audio_lock);
1223 mutex_destroy(&adev->dm.dc_lock);
1228 static int load_dmcu_fw(struct amdgpu_device *adev)
1230 const char *fw_name_dmcu = NULL;
1232 const struct dmcu_firmware_header_v1_0 *hdr;
1234 switch(adev->asic_type) {
1235 #if defined(CONFIG_DRM_AMD_DC_SI)
1250 case CHIP_POLARIS11:
1251 case CHIP_POLARIS10:
1252 case CHIP_POLARIS12:
1260 case CHIP_SIENNA_CICHLID:
1261 case CHIP_NAVY_FLOUNDER:
1262 case CHIP_DIMGREY_CAVEFISH:
1266 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1269 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1270 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1271 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1272 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1277 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1281 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1282 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1286 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1288 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1289 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1290 adev->dm.fw_dmcu = NULL;
1294 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1299 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1301 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1303 release_firmware(adev->dm.fw_dmcu);
1304 adev->dm.fw_dmcu = NULL;
1308 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1309 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1310 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1311 adev->firmware.fw_size +=
1312 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1314 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1315 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1316 adev->firmware.fw_size +=
1317 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1319 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1321 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1326 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1328 struct amdgpu_device *adev = ctx;
1330 return dm_read_reg(adev->dm.dc->ctx, address);
1333 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1336 struct amdgpu_device *adev = ctx;
1338 return dm_write_reg(adev->dm.dc->ctx, address, value);
1341 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1343 struct dmub_srv_create_params create_params;
1344 struct dmub_srv_region_params region_params;
1345 struct dmub_srv_region_info region_info;
1346 struct dmub_srv_fb_params fb_params;
1347 struct dmub_srv_fb_info *fb_info;
1348 struct dmub_srv *dmub_srv;
1349 const struct dmcub_firmware_header_v1_0 *hdr;
1350 const char *fw_name_dmub;
1351 enum dmub_asic dmub_asic;
1352 enum dmub_status status;
1355 switch (adev->asic_type) {
1357 dmub_asic = DMUB_ASIC_DCN21;
1358 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1359 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1360 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1362 case CHIP_SIENNA_CICHLID:
1363 dmub_asic = DMUB_ASIC_DCN30;
1364 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1366 case CHIP_NAVY_FLOUNDER:
1367 dmub_asic = DMUB_ASIC_DCN30;
1368 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1371 dmub_asic = DMUB_ASIC_DCN301;
1372 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1374 case CHIP_DIMGREY_CAVEFISH:
1375 dmub_asic = DMUB_ASIC_DCN302;
1376 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1380 /* ASIC doesn't support DMUB. */
1384 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1386 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1390 r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1392 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1396 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1398 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1399 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1400 AMDGPU_UCODE_ID_DMCUB;
1401 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1403 adev->firmware.fw_size +=
1404 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1406 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1407 adev->dm.dmcub_fw_version);
1410 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1412 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1413 dmub_srv = adev->dm.dmub_srv;
1416 DRM_ERROR("Failed to allocate DMUB service!\n");
1420 memset(&create_params, 0, sizeof(create_params));
1421 create_params.user_ctx = adev;
1422 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1423 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1424 create_params.asic = dmub_asic;
1426 /* Create the DMUB service. */
1427 status = dmub_srv_create(dmub_srv, &create_params);
1428 if (status != DMUB_STATUS_OK) {
1429 DRM_ERROR("Error creating DMUB service: %d\n", status);
1433 /* Calculate the size of all the regions for the DMUB service. */
1434 memset(®ion_params, 0, sizeof(region_params));
1436 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1437 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1438 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1439 region_params.vbios_size = adev->bios_size;
1440 region_params.fw_bss_data = region_params.bss_data_size ?
1441 adev->dm.dmub_fw->data +
1442 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1443 le32_to_cpu(hdr->inst_const_bytes) : NULL;
1444 region_params.fw_inst_const =
1445 adev->dm.dmub_fw->data +
1446 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1449 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
1452 if (status != DMUB_STATUS_OK) {
1453 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1458 * Allocate a framebuffer based on the total size of all the regions.
1459 * TODO: Move this into GART.
1461 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1462 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1463 &adev->dm.dmub_bo_gpu_addr,
1464 &adev->dm.dmub_bo_cpu_addr);
1468 /* Rebase the regions on the framebuffer address. */
1469 memset(&fb_params, 0, sizeof(fb_params));
1470 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1471 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1472 fb_params.region_info = ®ion_info;
1474 adev->dm.dmub_fb_info =
1475 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1476 fb_info = adev->dm.dmub_fb_info;
1480 "Failed to allocate framebuffer info for DMUB service!\n");
1484 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1485 if (status != DMUB_STATUS_OK) {
1486 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1493 static int dm_sw_init(void *handle)
1495 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1498 r = dm_dmub_sw_init(adev);
1502 return load_dmcu_fw(adev);
1505 static int dm_sw_fini(void *handle)
1507 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1509 kfree(adev->dm.dmub_fb_info);
1510 adev->dm.dmub_fb_info = NULL;
1512 if (adev->dm.dmub_srv) {
1513 dmub_srv_destroy(adev->dm.dmub_srv);
1514 adev->dm.dmub_srv = NULL;
1517 release_firmware(adev->dm.dmub_fw);
1518 adev->dm.dmub_fw = NULL;
1520 release_firmware(adev->dm.fw_dmcu);
1521 adev->dm.fw_dmcu = NULL;
1526 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1528 struct amdgpu_dm_connector *aconnector;
1529 struct drm_connector *connector;
1530 struct drm_connector_list_iter iter;
1533 drm_connector_list_iter_begin(dev, &iter);
1534 drm_for_each_connector_iter(connector, &iter) {
1535 aconnector = to_amdgpu_dm_connector(connector);
1536 if (aconnector->dc_link->type == dc_connection_mst_branch &&
1537 aconnector->mst_mgr.aux) {
1538 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1540 aconnector->base.base.id);
1542 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1544 DRM_ERROR("DM_MST: Failed to start MST\n");
1545 aconnector->dc_link->type =
1546 dc_connection_single;
1551 drm_connector_list_iter_end(&iter);
1556 static int dm_late_init(void *handle)
1558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560 struct dmcu_iram_parameters params;
1561 unsigned int linear_lut[16];
1563 struct dmcu *dmcu = NULL;
1566 dmcu = adev->dm.dc->res_pool->dmcu;
1568 for (i = 0; i < 16; i++)
1569 linear_lut[i] = 0xFFFF * i / 15;
1572 params.backlight_ramping_start = 0xCCCC;
1573 params.backlight_ramping_reduction = 0xCCCCCCCC;
1574 params.backlight_lut_array_size = 16;
1575 params.backlight_lut_array = linear_lut;
1577 /* Min backlight level after ABM reduction, Don't allow below 1%
1578 * 0xFFFF x 0.01 = 0x28F
1580 params.min_abm_backlight = 0x28F;
1582 /* In the case where abm is implemented on dmcub,
1583 * dmcu object will be null.
1584 * ABM 2.4 and up are implemented on dmcub.
1587 ret = dmcu_load_iram(dmcu, params);
1588 else if (adev->dm.dc->ctx->dmub_srv)
1589 ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
1594 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
1597 static void s3_handle_mst(struct drm_device *dev, bool suspend)
1599 struct amdgpu_dm_connector *aconnector;
1600 struct drm_connector *connector;
1601 struct drm_connector_list_iter iter;
1602 struct drm_dp_mst_topology_mgr *mgr;
1604 bool need_hotplug = false;
1606 drm_connector_list_iter_begin(dev, &iter);
1607 drm_for_each_connector_iter(connector, &iter) {
1608 aconnector = to_amdgpu_dm_connector(connector);
1609 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1610 aconnector->mst_port)
1613 mgr = &aconnector->mst_mgr;
1616 drm_dp_mst_topology_mgr_suspend(mgr);
1618 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
1620 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1621 need_hotplug = true;
1625 drm_connector_list_iter_end(&iter);
1628 drm_kms_helper_hotplug_event(dev);
1631 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
1633 struct smu_context *smu = &adev->smu;
1636 if (!is_support_sw_smu(adev))
1639 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
1640 * on window driver dc implementation.
1641 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
1642 * should be passed to smu during boot up and resume from s3.
1643 * boot up: dc calculate dcn watermark clock settings within dc_create,
1644 * dcn20_resource_construct
1645 * then call pplib functions below to pass the settings to smu:
1646 * smu_set_watermarks_for_clock_ranges
1647 * smu_set_watermarks_table
1648 * navi10_set_watermarks_table
1649 * smu_write_watermarks_table
1651 * For Renoir, clock settings of dcn watermark are also fixed values.
1652 * dc has implemented different flow for window driver:
1653 * dc_hardware_init / dc_set_power_state
1658 * smu_set_watermarks_for_clock_ranges
1659 * renoir_set_watermarks_table
1660 * smu_write_watermarks_table
1663 * dc_hardware_init -> amdgpu_dm_init
1664 * dc_set_power_state --> dm_resume
1666 * therefore, this function apply to navi10/12/14 but not Renoir
1669 switch(adev->asic_type) {
1678 ret = smu_write_watermarks_table(smu);
1680 DRM_ERROR("Failed to update WMTABLE!\n");
1688 * dm_hw_init() - Initialize DC device
1689 * @handle: The base driver device containing the amdgpu_dm device.
1691 * Initialize the &struct amdgpu_display_manager device. This involves calling
1692 * the initializers of each DM component, then populating the struct with them.
1694 * Although the function implies hardware initialization, both hardware and
1695 * software are initialized here. Splitting them out to their relevant init
1696 * hooks is a future TODO item.
1698 * Some notable things that are initialized here:
1700 * - Display Core, both software and hardware
1701 * - DC modules that we need (freesync and color management)
1702 * - DRM software states
1703 * - Interrupt sources and handlers
1705 * - Debug FS entries, if enabled
1707 static int dm_hw_init(void *handle)
1709 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1710 /* Create DAL display manager */
1711 amdgpu_dm_init(adev);
1712 amdgpu_dm_hpd_init(adev);
1718 * dm_hw_fini() - Teardown DC device
1719 * @handle: The base driver device containing the amdgpu_dm device.
1721 * Teardown components within &struct amdgpu_display_manager that require
1722 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1723 * were loaded. Also flush IRQ workqueues and disable them.
1725 static int dm_hw_fini(void *handle)
1727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1729 amdgpu_dm_hpd_fini(adev);
1731 amdgpu_dm_irq_fini(adev);
1732 amdgpu_dm_fini(adev);
1737 static int dm_enable_vblank(struct drm_crtc *crtc);
1738 static void dm_disable_vblank(struct drm_crtc *crtc);
1740 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
1741 struct dc_state *state, bool enable)
1743 enum dc_irq_source irq_source;
1744 struct amdgpu_crtc *acrtc;
1748 for (i = 0; i < state->stream_count; i++) {
1749 acrtc = get_crtc_by_otg_inst(
1750 adev, state->stream_status[i].primary_otg_inst);
1752 if (acrtc && state->stream_status[i].plane_count != 0) {
1753 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
1754 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
1755 DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n",
1756 acrtc->crtc_id, enable ? "en" : "dis", rc);
1758 DRM_WARN("Failed to %s pflip interrupts\n",
1759 enable ? "enable" : "disable");
1762 rc = dm_enable_vblank(&acrtc->base);
1764 DRM_WARN("Failed to enable vblank interrupts\n");
1766 dm_disable_vblank(&acrtc->base);
1774 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
1776 struct dc_state *context = NULL;
1777 enum dc_status res = DC_ERROR_UNEXPECTED;
1779 struct dc_stream_state *del_streams[MAX_PIPES];
1780 int del_streams_count = 0;
1782 memset(del_streams, 0, sizeof(del_streams));
1784 context = dc_create_state(dc);
1785 if (context == NULL)
1786 goto context_alloc_fail;
1788 dc_resource_state_copy_construct_current(dc, context);
1790 /* First remove from context all streams */
1791 for (i = 0; i < context->stream_count; i++) {
1792 struct dc_stream_state *stream = context->streams[i];
1794 del_streams[del_streams_count++] = stream;
1797 /* Remove all planes for removed streams and then remove the streams */
1798 for (i = 0; i < del_streams_count; i++) {
1799 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
1800 res = DC_FAIL_DETACH_SURFACES;
1804 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
1810 res = dc_validate_global_state(dc, context, false);
1813 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res);
1817 res = dc_commit_state(dc, context);
1820 dc_release_state(context);
1826 static int dm_suspend(void *handle)
1828 struct amdgpu_device *adev = handle;
1829 struct amdgpu_display_manager *dm = &adev->dm;
1832 if (amdgpu_in_reset(adev)) {
1833 mutex_lock(&dm->dc_lock);
1835 #if defined(CONFIG_DRM_AMD_DC_DCN)
1836 dc_allow_idle_optimizations(adev->dm.dc, false);
1839 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
1841 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
1843 amdgpu_dm_commit_zero_streams(dm->dc);
1845 amdgpu_dm_irq_suspend(adev);
1850 WARN_ON(adev->dm.cached_state);
1851 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
1853 s3_handle_mst(adev_to_drm(adev), true);
1855 amdgpu_dm_irq_suspend(adev);
1858 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1863 static struct amdgpu_dm_connector *
1864 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1865 struct drm_crtc *crtc)
1868 struct drm_connector_state *new_con_state;
1869 struct drm_connector *connector;
1870 struct drm_crtc *crtc_from_state;
1872 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1873 crtc_from_state = new_con_state->crtc;
1875 if (crtc_from_state == crtc)
1876 return to_amdgpu_dm_connector(connector);
1882 static void emulated_link_detect(struct dc_link *link)
1884 struct dc_sink_init_data sink_init_data = { 0 };
1885 struct display_sink_capability sink_caps = { 0 };
1886 enum dc_edid_status edid_status;
1887 struct dc_context *dc_ctx = link->ctx;
1888 struct dc_sink *sink = NULL;
1889 struct dc_sink *prev_sink = NULL;
1891 link->type = dc_connection_none;
1892 prev_sink = link->local_sink;
1895 dc_sink_release(prev_sink);
1897 switch (link->connector_signal) {
1898 case SIGNAL_TYPE_HDMI_TYPE_A: {
1899 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1900 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1904 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1905 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1906 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1910 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1911 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1912 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1916 case SIGNAL_TYPE_LVDS: {
1917 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1918 sink_caps.signal = SIGNAL_TYPE_LVDS;
1922 case SIGNAL_TYPE_EDP: {
1923 sink_caps.transaction_type =
1924 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1925 sink_caps.signal = SIGNAL_TYPE_EDP;
1929 case SIGNAL_TYPE_DISPLAY_PORT: {
1930 sink_caps.transaction_type =
1931 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1932 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1937 DC_ERROR("Invalid connector type! signal:%d\n",
1938 link->connector_signal);
1942 sink_init_data.link = link;
1943 sink_init_data.sink_signal = sink_caps.signal;
1945 sink = dc_sink_create(&sink_init_data);
1947 DC_ERROR("Failed to create sink!\n");
1951 /* dc_sink_create returns a new reference */
1952 link->local_sink = sink;
1954 edid_status = dm_helpers_read_local_edid(
1959 if (edid_status != EDID_OK)
1960 DC_ERROR("Failed to read EDID");
1964 static void dm_gpureset_commit_state(struct dc_state *dc_state,
1965 struct amdgpu_display_manager *dm)
1968 struct dc_surface_update surface_updates[MAX_SURFACES];
1969 struct dc_plane_info plane_infos[MAX_SURFACES];
1970 struct dc_scaling_info scaling_infos[MAX_SURFACES];
1971 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
1972 struct dc_stream_update stream_update;
1976 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
1979 dm_error("Failed to allocate update bundle\n");
1983 for (k = 0; k < dc_state->stream_count; k++) {
1984 bundle->stream_update.stream = dc_state->streams[k];
1986 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
1987 bundle->surface_updates[m].surface =
1988 dc_state->stream_status->plane_states[m];
1989 bundle->surface_updates[m].surface->force_full_update =
1992 dc_commit_updates_for_stream(
1993 dm->dc, bundle->surface_updates,
1994 dc_state->stream_status->plane_count,
1995 dc_state->streams[k], &bundle->stream_update, dc_state);
2004 static void dm_set_dpms_off(struct dc_link *link)
2006 struct dc_stream_state *stream_state;
2007 struct amdgpu_dm_connector *aconnector = link->priv;
2008 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
2009 struct dc_stream_update stream_update;
2010 bool dpms_off = true;
2012 memset(&stream_update, 0, sizeof(stream_update));
2013 stream_update.dpms_off = &dpms_off;
2015 mutex_lock(&adev->dm.dc_lock);
2016 stream_state = dc_stream_find_from_link(link);
2018 if (stream_state == NULL) {
2019 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n");
2020 mutex_unlock(&adev->dm.dc_lock);
2024 stream_update.stream = stream_state;
2025 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
2026 stream_state, &stream_update,
2027 stream_state->ctx->dc->current_state);
2028 mutex_unlock(&adev->dm.dc_lock);
2031 static int dm_resume(void *handle)
2033 struct amdgpu_device *adev = handle;
2034 struct drm_device *ddev = adev_to_drm(adev);
2035 struct amdgpu_display_manager *dm = &adev->dm;
2036 struct amdgpu_dm_connector *aconnector;
2037 struct drm_connector *connector;
2038 struct drm_connector_list_iter iter;
2039 struct drm_crtc *crtc;
2040 struct drm_crtc_state *new_crtc_state;
2041 struct dm_crtc_state *dm_new_crtc_state;
2042 struct drm_plane *plane;
2043 struct drm_plane_state *new_plane_state;
2044 struct dm_plane_state *dm_new_plane_state;
2045 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2046 enum dc_connection_type new_connection_type = dc_connection_none;
2047 struct dc_state *dc_state;
2050 if (amdgpu_in_reset(adev)) {
2051 dc_state = dm->cached_dc_state;
2053 r = dm_dmub_hw_init(adev);
2055 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2057 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2060 amdgpu_dm_irq_resume_early(adev);
2062 for (i = 0; i < dc_state->stream_count; i++) {
2063 dc_state->streams[i]->mode_changed = true;
2064 for (j = 0; j < dc_state->stream_status->plane_count; j++) {
2065 dc_state->stream_status->plane_states[j]->update_flags.raw
2070 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2072 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2074 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2076 dc_release_state(dm->cached_dc_state);
2077 dm->cached_dc_state = NULL;
2079 amdgpu_dm_irq_resume_late(adev);
2081 mutex_unlock(&dm->dc_lock);
2085 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2086 dc_release_state(dm_state->context);
2087 dm_state->context = dc_create_state(dm->dc);
2088 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2089 dc_resource_state_construct(dm->dc, dm_state->context);
2091 /* Before powering on DC we need to re-initialize DMUB. */
2092 r = dm_dmub_hw_init(adev);
2094 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2096 /* power on hardware */
2097 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2099 /* program HPD filter */
2103 * early enable HPD Rx IRQ, should be done before set mode as short
2104 * pulse interrupts are used for MST
2106 amdgpu_dm_irq_resume_early(adev);
2108 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2109 s3_handle_mst(ddev, false);
2112 drm_connector_list_iter_begin(ddev, &iter);
2113 drm_for_each_connector_iter(connector, &iter) {
2114 aconnector = to_amdgpu_dm_connector(connector);
2117 * this is the case when traversing through already created
2118 * MST connectors, should be skipped
2120 if (aconnector->mst_port)
2123 mutex_lock(&aconnector->hpd_lock);
2124 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2125 DRM_ERROR("KMS: Failed to detect connector\n");
2127 if (aconnector->base.force && new_connection_type == dc_connection_none)
2128 emulated_link_detect(aconnector->dc_link);
2130 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2132 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2133 aconnector->fake_enable = false;
2135 if (aconnector->dc_sink)
2136 dc_sink_release(aconnector->dc_sink);
2137 aconnector->dc_sink = NULL;
2138 amdgpu_dm_update_connector_after_detect(aconnector);
2139 mutex_unlock(&aconnector->hpd_lock);
2141 drm_connector_list_iter_end(&iter);
2143 /* Force mode set in atomic commit */
2144 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2145 new_crtc_state->active_changed = true;
2148 * atomic_check is expected to create the dc states. We need to release
2149 * them here, since they were duplicated as part of the suspend
2152 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2153 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2154 if (dm_new_crtc_state->stream) {
2155 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2156 dc_stream_release(dm_new_crtc_state->stream);
2157 dm_new_crtc_state->stream = NULL;
2161 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2162 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2163 if (dm_new_plane_state->dc_state) {
2164 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2165 dc_plane_state_release(dm_new_plane_state->dc_state);
2166 dm_new_plane_state->dc_state = NULL;
2170 drm_atomic_helper_resume(ddev, dm->cached_state);
2172 dm->cached_state = NULL;
2174 amdgpu_dm_irq_resume_late(adev);
2176 amdgpu_dm_smu_write_watermarks_table(adev);
2184 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2185 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2186 * the base driver's device list to be initialized and torn down accordingly.
2188 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2191 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2193 .early_init = dm_early_init,
2194 .late_init = dm_late_init,
2195 .sw_init = dm_sw_init,
2196 .sw_fini = dm_sw_fini,
2197 .hw_init = dm_hw_init,
2198 .hw_fini = dm_hw_fini,
2199 .suspend = dm_suspend,
2200 .resume = dm_resume,
2201 .is_idle = dm_is_idle,
2202 .wait_for_idle = dm_wait_for_idle,
2203 .check_soft_reset = dm_check_soft_reset,
2204 .soft_reset = dm_soft_reset,
2205 .set_clockgating_state = dm_set_clockgating_state,
2206 .set_powergating_state = dm_set_powergating_state,
2209 const struct amdgpu_ip_block_version dm_ip_block =
2211 .type = AMD_IP_BLOCK_TYPE_DCE,
2215 .funcs = &amdgpu_dm_funcs,
2225 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2226 .fb_create = amdgpu_display_user_framebuffer_create,
2227 .get_format_info = amd_get_format_info,
2228 .output_poll_changed = drm_fb_helper_output_poll_changed,
2229 .atomic_check = amdgpu_dm_atomic_check,
2230 .atomic_commit = drm_atomic_helper_commit,
2233 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2234 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
2237 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2239 u32 max_cll, min_cll, max, min, q, r;
2240 struct amdgpu_dm_backlight_caps *caps;
2241 struct amdgpu_display_manager *dm;
2242 struct drm_connector *conn_base;
2243 struct amdgpu_device *adev;
2244 struct dc_link *link = NULL;
2245 static const u8 pre_computed_values[] = {
2246 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
2247 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
2249 if (!aconnector || !aconnector->dc_link)
2252 link = aconnector->dc_link;
2253 if (link->connector_signal != SIGNAL_TYPE_EDP)
2256 conn_base = &aconnector->base;
2257 adev = drm_to_adev(conn_base->dev);
2259 caps = &dm->backlight_caps;
2260 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2261 caps->aux_support = false;
2262 max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
2263 min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
2265 if (caps->ext_caps->bits.oled == 1 ||
2266 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2267 caps->ext_caps->bits.hdr_aux_backlight_control == 1)
2268 caps->aux_support = true;
2270 if (amdgpu_backlight == 0)
2271 caps->aux_support = false;
2272 else if (amdgpu_backlight == 1)
2273 caps->aux_support = true;
2275 /* From the specification (CTA-861-G), for calculating the maximum
2276 * luminance we need to use:
2277 * Luminance = 50*2**(CV/32)
2278 * Where CV is a one-byte value.
2279 * For calculating this expression we may need float point precision;
2280 * to avoid this complexity level, we take advantage that CV is divided
2281 * by a constant. From the Euclids division algorithm, we know that CV
2282 * can be written as: CV = 32*q + r. Next, we replace CV in the
2283 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
2284 * need to pre-compute the value of r/32. For pre-computing the values
2285 * We just used the following Ruby line:
2286 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
2287 * The results of the above expressions can be verified at
2288 * pre_computed_values.
2292 max = (1 << q) * pre_computed_values[r];
2294 // min luminance: maxLum * (CV/255)^2 / 100
2295 q = DIV_ROUND_CLOSEST(min_cll, 255);
2296 min = max * DIV_ROUND_CLOSEST((q * q), 100);
2298 caps->aux_max_input_signal = max;
2299 caps->aux_min_input_signal = min;
2302 void amdgpu_dm_update_connector_after_detect(
2303 struct amdgpu_dm_connector *aconnector)
2305 struct drm_connector *connector = &aconnector->base;
2306 struct drm_device *dev = connector->dev;
2307 struct dc_sink *sink;
2309 /* MST handled by drm_mst framework */
2310 if (aconnector->mst_mgr.mst_state == true)
2313 sink = aconnector->dc_link->local_sink;
2315 dc_sink_retain(sink);
2318 * Edid mgmt connector gets first update only in mode_valid hook and then
2319 * the connector sink is set to either fake or physical sink depends on link status.
2320 * Skip if already done during boot.
2322 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2323 && aconnector->dc_em_sink) {
2326 * For S3 resume with headless use eml_sink to fake stream
2327 * because on resume connector->sink is set to NULL
2329 mutex_lock(&dev->mode_config.mutex);
2332 if (aconnector->dc_sink) {
2333 amdgpu_dm_update_freesync_caps(connector, NULL);
2335 * retain and release below are used to
2336 * bump up refcount for sink because the link doesn't point
2337 * to it anymore after disconnect, so on next crtc to connector
2338 * reshuffle by UMD we will get into unwanted dc_sink release
2340 dc_sink_release(aconnector->dc_sink);
2342 aconnector->dc_sink = sink;
2343 dc_sink_retain(aconnector->dc_sink);
2344 amdgpu_dm_update_freesync_caps(connector,
2347 amdgpu_dm_update_freesync_caps(connector, NULL);
2348 if (!aconnector->dc_sink) {
2349 aconnector->dc_sink = aconnector->dc_em_sink;
2350 dc_sink_retain(aconnector->dc_sink);
2354 mutex_unlock(&dev->mode_config.mutex);
2357 dc_sink_release(sink);
2362 * TODO: temporary guard to look for proper fix
2363 * if this sink is MST sink, we should not do anything
2365 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2366 dc_sink_release(sink);
2370 if (aconnector->dc_sink == sink) {
2372 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2375 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2376 aconnector->connector_id);
2378 dc_sink_release(sink);
2382 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2383 aconnector->connector_id, aconnector->dc_sink, sink);
2385 mutex_lock(&dev->mode_config.mutex);
2388 * 1. Update status of the drm connector
2389 * 2. Send an event and let userspace tell us what to do
2393 * TODO: check if we still need the S3 mode update workaround.
2394 * If yes, put it here.
2396 if (aconnector->dc_sink) {
2397 amdgpu_dm_update_freesync_caps(connector, NULL);
2398 dc_sink_release(aconnector->dc_sink);
2401 aconnector->dc_sink = sink;
2402 dc_sink_retain(aconnector->dc_sink);
2403 if (sink->dc_edid.length == 0) {
2404 aconnector->edid = NULL;
2405 if (aconnector->dc_link->aux_mode) {
2406 drm_dp_cec_unset_edid(
2407 &aconnector->dm_dp_aux.aux);
2411 (struct edid *)sink->dc_edid.raw_edid;
2413 drm_connector_update_edid_property(connector,
2415 if (aconnector->dc_link->aux_mode)
2416 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2420 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2421 update_connector_ext_caps(aconnector);
2423 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2424 amdgpu_dm_update_freesync_caps(connector, NULL);
2425 drm_connector_update_edid_property(connector, NULL);
2426 aconnector->num_modes = 0;
2427 dc_sink_release(aconnector->dc_sink);
2428 aconnector->dc_sink = NULL;
2429 aconnector->edid = NULL;
2430 #ifdef CONFIG_DRM_AMD_DC_HDCP
2431 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2432 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2433 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2437 mutex_unlock(&dev->mode_config.mutex);
2439 update_subconnector_property(aconnector);
2442 dc_sink_release(sink);
2445 static void handle_hpd_irq(void *param)
2447 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2448 struct drm_connector *connector = &aconnector->base;
2449 struct drm_device *dev = connector->dev;
2450 enum dc_connection_type new_connection_type = dc_connection_none;
2451 #ifdef CONFIG_DRM_AMD_DC_HDCP
2452 struct amdgpu_device *adev = drm_to_adev(dev);
2453 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
2457 * In case of failure or MST no need to update connector status or notify the OS
2458 * since (for MST case) MST does this in its own context.
2460 mutex_lock(&aconnector->hpd_lock);
2462 #ifdef CONFIG_DRM_AMD_DC_HDCP
2463 if (adev->dm.hdcp_workqueue) {
2464 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
2465 dm_con_state->update_hdcp = true;
2468 if (aconnector->fake_enable)
2469 aconnector->fake_enable = false;
2471 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2472 DRM_ERROR("KMS: Failed to detect connector\n");
2474 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2475 emulated_link_detect(aconnector->dc_link);
2478 drm_modeset_lock_all(dev);
2479 dm_restore_drm_connector_state(dev, connector);
2480 drm_modeset_unlock_all(dev);
2482 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2483 drm_kms_helper_hotplug_event(dev);
2485 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
2486 if (new_connection_type == dc_connection_none &&
2487 aconnector->dc_link->type == dc_connection_none)
2488 dm_set_dpms_off(aconnector->dc_link);
2490 amdgpu_dm_update_connector_after_detect(aconnector);
2492 drm_modeset_lock_all(dev);
2493 dm_restore_drm_connector_state(dev, connector);
2494 drm_modeset_unlock_all(dev);
2496 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2497 drm_kms_helper_hotplug_event(dev);
2499 mutex_unlock(&aconnector->hpd_lock);
2503 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
2505 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
2507 bool new_irq_handled = false;
2509 int dpcd_bytes_to_read;
2511 const int max_process_count = 30;
2512 int process_count = 0;
2514 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
2516 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
2517 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
2518 /* DPCD 0x200 - 0x201 for downstream IRQ */
2519 dpcd_addr = DP_SINK_COUNT;
2521 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
2522 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
2523 dpcd_addr = DP_SINK_COUNT_ESI;
2526 dret = drm_dp_dpcd_read(
2527 &aconnector->dm_dp_aux.aux,
2530 dpcd_bytes_to_read);
2532 while (dret == dpcd_bytes_to_read &&
2533 process_count < max_process_count) {
2539 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
2540 /* handle HPD short pulse irq */
2541 if (aconnector->mst_mgr.mst_state)
2543 &aconnector->mst_mgr,
2547 if (new_irq_handled) {
2548 /* ACK at DPCD to notify down stream */
2549 const int ack_dpcd_bytes_to_write =
2550 dpcd_bytes_to_read - 1;
2552 for (retry = 0; retry < 3; retry++) {
2555 wret = drm_dp_dpcd_write(
2556 &aconnector->dm_dp_aux.aux,
2559 ack_dpcd_bytes_to_write);
2560 if (wret == ack_dpcd_bytes_to_write)
2564 /* check if there is new irq to be handled */
2565 dret = drm_dp_dpcd_read(
2566 &aconnector->dm_dp_aux.aux,
2569 dpcd_bytes_to_read);
2571 new_irq_handled = false;
2577 if (process_count == max_process_count)
2578 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2581 static void handle_hpd_rx_irq(void *param)
2583 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2584 struct drm_connector *connector = &aconnector->base;
2585 struct drm_device *dev = connector->dev;
2586 struct dc_link *dc_link = aconnector->dc_link;
2587 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
2588 bool result = false;
2589 enum dc_connection_type new_connection_type = dc_connection_none;
2590 struct amdgpu_device *adev = drm_to_adev(dev);
2591 union hpd_irq_data hpd_irq_data;
2593 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
2596 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2597 * conflict, after implement i2c helper, this mutex should be
2600 if (dc_link->type != dc_connection_mst_branch)
2601 mutex_lock(&aconnector->hpd_lock);
2603 read_hpd_rx_irq_data(dc_link, &hpd_irq_data);
2605 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2606 (dc_link->type == dc_connection_mst_branch)) {
2607 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) {
2609 dm_handle_hpd_rx_irq(aconnector);
2611 } else if (hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
2613 dm_handle_hpd_rx_irq(aconnector);
2618 mutex_lock(&adev->dm.dc_lock);
2619 #ifdef CONFIG_DRM_AMD_DC_HDCP
2620 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL);
2622 result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL);
2624 mutex_unlock(&adev->dm.dc_lock);
2627 if (result && !is_mst_root_connector) {
2628 /* Downstream Port status changed. */
2629 if (!dc_link_detect_sink(dc_link, &new_connection_type))
2630 DRM_ERROR("KMS: Failed to detect connector\n");
2632 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2633 emulated_link_detect(dc_link);
2635 if (aconnector->fake_enable)
2636 aconnector->fake_enable = false;
2638 amdgpu_dm_update_connector_after_detect(aconnector);
2641 drm_modeset_lock_all(dev);
2642 dm_restore_drm_connector_state(dev, connector);
2643 drm_modeset_unlock_all(dev);
2645 drm_kms_helper_hotplug_event(dev);
2646 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
2648 if (aconnector->fake_enable)
2649 aconnector->fake_enable = false;
2651 amdgpu_dm_update_connector_after_detect(aconnector);
2654 drm_modeset_lock_all(dev);
2655 dm_restore_drm_connector_state(dev, connector);
2656 drm_modeset_unlock_all(dev);
2658 drm_kms_helper_hotplug_event(dev);
2661 #ifdef CONFIG_DRM_AMD_DC_HDCP
2662 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
2663 if (adev->dm.hdcp_workqueue)
2664 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2668 if (dc_link->type != dc_connection_mst_branch) {
2669 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
2670 mutex_unlock(&aconnector->hpd_lock);
2674 static void register_hpd_handlers(struct amdgpu_device *adev)
2676 struct drm_device *dev = adev_to_drm(adev);
2677 struct drm_connector *connector;
2678 struct amdgpu_dm_connector *aconnector;
2679 const struct dc_link *dc_link;
2680 struct dc_interrupt_params int_params = {0};
2682 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2683 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2685 list_for_each_entry(connector,
2686 &dev->mode_config.connector_list, head) {
2688 aconnector = to_amdgpu_dm_connector(connector);
2689 dc_link = aconnector->dc_link;
2691 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2692 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2693 int_params.irq_source = dc_link->irq_source_hpd;
2695 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2697 (void *) aconnector);
2700 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2702 /* Also register for DP short pulse (hpd_rx). */
2703 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2704 int_params.irq_source = dc_link->irq_source_hpd_rx;
2706 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2708 (void *) aconnector);
2713 #if defined(CONFIG_DRM_AMD_DC_SI)
2714 /* Register IRQ sources and initialize IRQ callbacks */
2715 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
2717 struct dc *dc = adev->dm.dc;
2718 struct common_irq_params *c_irq_params;
2719 struct dc_interrupt_params int_params = {0};
2722 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2724 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2725 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2728 * Actions of amdgpu_irq_add_id():
2729 * 1. Register a set() function with base driver.
2730 * Base driver will call set() function to enable/disable an
2731 * interrupt in DC hardware.
2732 * 2. Register amdgpu_dm_irq_handler().
2733 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2734 * coming from DC hardware.
2735 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2736 * for acknowledging and handling. */
2738 /* Use VBLANK interrupt */
2739 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2740 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
2742 DRM_ERROR("Failed to add crtc irq id!\n");
2746 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2747 int_params.irq_source =
2748 dc_interrupt_to_irq_source(dc, i+1 , 0);
2750 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2752 c_irq_params->adev = adev;
2753 c_irq_params->irq_src = int_params.irq_source;
2755 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2756 dm_crtc_high_irq, c_irq_params);
2759 /* Use GRPH_PFLIP interrupt */
2760 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2761 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2762 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2764 DRM_ERROR("Failed to add page flip irq id!\n");
2768 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2769 int_params.irq_source =
2770 dc_interrupt_to_irq_source(dc, i, 0);
2772 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2774 c_irq_params->adev = adev;
2775 c_irq_params->irq_src = int_params.irq_source;
2777 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2778 dm_pflip_high_irq, c_irq_params);
2783 r = amdgpu_irq_add_id(adev, client_id,
2784 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2786 DRM_ERROR("Failed to add hpd irq id!\n");
2790 register_hpd_handlers(adev);
2796 /* Register IRQ sources and initialize IRQ callbacks */
2797 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2799 struct dc *dc = adev->dm.dc;
2800 struct common_irq_params *c_irq_params;
2801 struct dc_interrupt_params int_params = {0};
2804 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2806 if (adev->asic_type >= CHIP_VEGA10)
2807 client_id = SOC15_IH_CLIENTID_DCE;
2809 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2810 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2813 * Actions of amdgpu_irq_add_id():
2814 * 1. Register a set() function with base driver.
2815 * Base driver will call set() function to enable/disable an
2816 * interrupt in DC hardware.
2817 * 2. Register amdgpu_dm_irq_handler().
2818 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2819 * coming from DC hardware.
2820 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2821 * for acknowledging and handling. */
2823 /* Use VBLANK interrupt */
2824 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2825 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
2827 DRM_ERROR("Failed to add crtc irq id!\n");
2831 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2832 int_params.irq_source =
2833 dc_interrupt_to_irq_source(dc, i, 0);
2835 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2837 c_irq_params->adev = adev;
2838 c_irq_params->irq_src = int_params.irq_source;
2840 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2841 dm_crtc_high_irq, c_irq_params);
2844 /* Use VUPDATE interrupt */
2845 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2846 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2848 DRM_ERROR("Failed to add vupdate irq id!\n");
2852 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2853 int_params.irq_source =
2854 dc_interrupt_to_irq_source(dc, i, 0);
2856 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2858 c_irq_params->adev = adev;
2859 c_irq_params->irq_src = int_params.irq_source;
2861 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2862 dm_vupdate_high_irq, c_irq_params);
2865 /* Use GRPH_PFLIP interrupt */
2866 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2867 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2868 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2870 DRM_ERROR("Failed to add page flip irq id!\n");
2874 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2875 int_params.irq_source =
2876 dc_interrupt_to_irq_source(dc, i, 0);
2878 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2880 c_irq_params->adev = adev;
2881 c_irq_params->irq_src = int_params.irq_source;
2883 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2884 dm_pflip_high_irq, c_irq_params);
2889 r = amdgpu_irq_add_id(adev, client_id,
2890 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2892 DRM_ERROR("Failed to add hpd irq id!\n");
2896 register_hpd_handlers(adev);
2901 #if defined(CONFIG_DRM_AMD_DC_DCN)
2902 /* Register IRQ sources and initialize IRQ callbacks */
2903 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
2905 struct dc *dc = adev->dm.dc;
2906 struct common_irq_params *c_irq_params;
2907 struct dc_interrupt_params int_params = {0};
2911 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2912 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2915 * Actions of amdgpu_irq_add_id():
2916 * 1. Register a set() function with base driver.
2917 * Base driver will call set() function to enable/disable an
2918 * interrupt in DC hardware.
2919 * 2. Register amdgpu_dm_irq_handler().
2920 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2921 * coming from DC hardware.
2922 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2923 * for acknowledging and handling.
2926 /* Use VSTARTUP interrupt */
2927 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
2928 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
2930 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
2933 DRM_ERROR("Failed to add crtc irq id!\n");
2937 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2938 int_params.irq_source =
2939 dc_interrupt_to_irq_source(dc, i, 0);
2941 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2943 c_irq_params->adev = adev;
2944 c_irq_params->irq_src = int_params.irq_source;
2946 amdgpu_dm_irq_register_interrupt(
2947 adev, &int_params, dm_crtc_high_irq, c_irq_params);
2950 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
2951 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
2952 * to trigger at end of each vblank, regardless of state of the lock,
2953 * matching DCE behaviour.
2955 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
2956 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
2958 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
2961 DRM_ERROR("Failed to add vupdate irq id!\n");
2965 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2966 int_params.irq_source =
2967 dc_interrupt_to_irq_source(dc, i, 0);
2969 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2971 c_irq_params->adev = adev;
2972 c_irq_params->irq_src = int_params.irq_source;
2974 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2975 dm_vupdate_high_irq, c_irq_params);
2978 /* Use GRPH_PFLIP interrupt */
2979 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
2980 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
2982 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
2984 DRM_ERROR("Failed to add page flip irq id!\n");
2988 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2989 int_params.irq_source =
2990 dc_interrupt_to_irq_source(dc, i, 0);
2992 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2994 c_irq_params->adev = adev;
2995 c_irq_params->irq_src = int_params.irq_source;
2997 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2998 dm_pflip_high_irq, c_irq_params);
3003 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3006 DRM_ERROR("Failed to add hpd irq id!\n");
3010 register_hpd_handlers(adev);
3017 * Acquires the lock for the atomic state object and returns
3018 * the new atomic state.
3020 * This should only be called during atomic check.
3022 static int dm_atomic_get_state(struct drm_atomic_state *state,
3023 struct dm_atomic_state **dm_state)
3025 struct drm_device *dev = state->dev;
3026 struct amdgpu_device *adev = drm_to_adev(dev);
3027 struct amdgpu_display_manager *dm = &adev->dm;
3028 struct drm_private_state *priv_state;
3033 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3034 if (IS_ERR(priv_state))
3035 return PTR_ERR(priv_state);
3037 *dm_state = to_dm_atomic_state(priv_state);
3042 static struct dm_atomic_state *
3043 dm_atomic_get_new_state(struct drm_atomic_state *state)
3045 struct drm_device *dev = state->dev;
3046 struct amdgpu_device *adev = drm_to_adev(dev);
3047 struct amdgpu_display_manager *dm = &adev->dm;
3048 struct drm_private_obj *obj;
3049 struct drm_private_state *new_obj_state;
3052 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3053 if (obj->funcs == dm->atomic_obj.funcs)
3054 return to_dm_atomic_state(new_obj_state);
3060 static struct drm_private_state *
3061 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3063 struct dm_atomic_state *old_state, *new_state;
3065 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3069 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3071 old_state = to_dm_atomic_state(obj->state);
3073 if (old_state && old_state->context)
3074 new_state->context = dc_copy_state(old_state->context);
3076 if (!new_state->context) {
3081 return &new_state->base;
3084 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3085 struct drm_private_state *state)
3087 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3089 if (dm_state && dm_state->context)
3090 dc_release_state(dm_state->context);
3095 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3096 .atomic_duplicate_state = dm_atomic_duplicate_state,
3097 .atomic_destroy_state = dm_atomic_destroy_state,
3100 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3102 struct dm_atomic_state *state;
3105 adev->mode_info.mode_config_initialized = true;
3107 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3108 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3110 adev_to_drm(adev)->mode_config.max_width = 16384;
3111 adev_to_drm(adev)->mode_config.max_height = 16384;
3113 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3114 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3115 /* indicates support for immediate flip */
3116 adev_to_drm(adev)->mode_config.async_page_flip = true;
3118 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
3120 state = kzalloc(sizeof(*state), GFP_KERNEL);
3124 state->context = dc_create_state(adev->dm.dc);
3125 if (!state->context) {
3130 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3132 drm_atomic_private_obj_init(adev_to_drm(adev),
3133 &adev->dm.atomic_obj,
3135 &dm_atomic_state_funcs);
3137 r = amdgpu_display_modeset_create_props(adev);
3139 dc_release_state(state->context);
3144 r = amdgpu_dm_audio_init(adev);
3146 dc_release_state(state->context);
3154 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3155 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3156 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3158 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3159 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3161 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
3163 #if defined(CONFIG_ACPI)
3164 struct amdgpu_dm_backlight_caps caps;
3166 memset(&caps, 0, sizeof(caps));
3168 if (dm->backlight_caps.caps_valid)
3171 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
3172 if (caps.caps_valid) {
3173 dm->backlight_caps.caps_valid = true;
3174 if (caps.aux_support)
3176 dm->backlight_caps.min_input_signal = caps.min_input_signal;
3177 dm->backlight_caps.max_input_signal = caps.max_input_signal;
3179 dm->backlight_caps.min_input_signal =
3180 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3181 dm->backlight_caps.max_input_signal =
3182 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3185 if (dm->backlight_caps.aux_support)
3188 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3189 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3193 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3194 unsigned *min, unsigned *max)
3199 if (caps->aux_support) {
3200 // Firmware limits are in nits, DC API wants millinits.
3201 *max = 1000 * caps->aux_max_input_signal;
3202 *min = 1000 * caps->aux_min_input_signal;
3204 // Firmware limits are 8-bit, PWM control is 16-bit.
3205 *max = 0x101 * caps->max_input_signal;
3206 *min = 0x101 * caps->min_input_signal;
3211 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3212 uint32_t brightness)
3216 if (!get_brightness_range(caps, &min, &max))
3219 // Rescale 0..255 to min..max
3220 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3221 AMDGPU_MAX_BL_LEVEL);
3224 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3225 uint32_t brightness)
3229 if (!get_brightness_range(caps, &min, &max))
3232 if (brightness < min)
3234 // Rescale min..max to 0..255
3235 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3239 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3241 struct amdgpu_display_manager *dm = bl_get_data(bd);
3242 struct amdgpu_dm_backlight_caps caps;
3243 struct dc_link *link = NULL;
3247 amdgpu_dm_update_backlight_caps(dm);
3248 caps = dm->backlight_caps;
3250 link = (struct dc_link *)dm->backlight_link;
3252 brightness = convert_brightness_from_user(&caps, bd->props.brightness);
3253 // Change brightness based on AUX property
3254 if (caps.aux_support)
3255 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3256 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3258 rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);
3263 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
3265 struct amdgpu_display_manager *dm = bl_get_data(bd);
3266 struct amdgpu_dm_backlight_caps caps;
3268 amdgpu_dm_update_backlight_caps(dm);
3269 caps = dm->backlight_caps;
3271 if (caps.aux_support) {
3272 struct dc_link *link = (struct dc_link *)dm->backlight_link;
3276 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
3278 return bd->props.brightness;
3279 return convert_brightness_to_user(&caps, avg);
3281 int ret = dc_link_get_backlight_level(dm->backlight_link);
3283 if (ret == DC_ERROR_UNEXPECTED)
3284 return bd->props.brightness;
3285 return convert_brightness_to_user(&caps, ret);
3289 static const struct backlight_ops amdgpu_dm_backlight_ops = {
3290 .options = BL_CORE_SUSPENDRESUME,
3291 .get_brightness = amdgpu_dm_backlight_get_brightness,
3292 .update_status = amdgpu_dm_backlight_update_status,
3296 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
3299 struct backlight_properties props = { 0 };
3301 amdgpu_dm_update_backlight_caps(dm);
3303 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
3304 props.brightness = AMDGPU_MAX_BL_LEVEL;
3305 props.type = BACKLIGHT_RAW;
3307 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
3308 adev_to_drm(dm->adev)->primary->index);
3310 dm->backlight_dev = backlight_device_register(bl_name,
3311 adev_to_drm(dm->adev)->dev,
3313 &amdgpu_dm_backlight_ops,
3316 if (IS_ERR(dm->backlight_dev))
3317 DRM_ERROR("DM: Backlight registration failed!\n");
3319 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
3324 static int initialize_plane(struct amdgpu_display_manager *dm,
3325 struct amdgpu_mode_info *mode_info, int plane_id,
3326 enum drm_plane_type plane_type,
3327 const struct dc_plane_cap *plane_cap)
3329 struct drm_plane *plane;
3330 unsigned long possible_crtcs;
3333 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
3335 DRM_ERROR("KMS: Failed to allocate plane\n");
3338 plane->type = plane_type;
3341 * HACK: IGT tests expect that the primary plane for a CRTC
3342 * can only have one possible CRTC. Only expose support for
3343 * any CRTC if they're not going to be used as a primary plane
3344 * for a CRTC - like overlay or underlay planes.
3346 possible_crtcs = 1 << plane_id;
3347 if (plane_id >= dm->dc->caps.max_streams)
3348 possible_crtcs = 0xff;
3350 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
3353 DRM_ERROR("KMS: Failed to initialize plane\n");
3359 mode_info->planes[plane_id] = plane;
3365 static void register_backlight_device(struct amdgpu_display_manager *dm,
3366 struct dc_link *link)
3368 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3369 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3371 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3372 link->type != dc_connection_none) {
3374 * Event if registration failed, we should continue with
3375 * DM initialization because not having a backlight control
3376 * is better then a black screen.
3378 amdgpu_dm_register_backlight_device(dm);
3380 if (dm->backlight_dev)
3381 dm->backlight_link = link;
3388 * In this architecture, the association
3389 * connector -> encoder -> crtc
3390 * id not really requried. The crtc and connector will hold the
3391 * display_index as an abstraction to use with DAL component
3393 * Returns 0 on success
3395 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
3397 struct amdgpu_display_manager *dm = &adev->dm;
3399 struct amdgpu_dm_connector *aconnector = NULL;
3400 struct amdgpu_encoder *aencoder = NULL;
3401 struct amdgpu_mode_info *mode_info = &adev->mode_info;
3403 int32_t primary_planes;
3404 enum dc_connection_type new_connection_type = dc_connection_none;
3405 const struct dc_plane_cap *plane;
3407 dm->display_indexes_num = dm->dc->caps.max_streams;
3408 /* Update the actual used number of crtc */
3409 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
3411 link_cnt = dm->dc->caps.max_links;
3412 if (amdgpu_dm_mode_config_init(dm->adev)) {
3413 DRM_ERROR("DM: Failed to initialize mode config\n");
3417 /* There is one primary plane per CRTC */
3418 primary_planes = dm->dc->caps.max_streams;
3419 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
3422 * Initialize primary planes, implicit planes for legacy IOCTLS.
3423 * Order is reversed to match iteration order in atomic check.
3425 for (i = (primary_planes - 1); i >= 0; i--) {
3426 plane = &dm->dc->caps.planes[i];
3428 if (initialize_plane(dm, mode_info, i,
3429 DRM_PLANE_TYPE_PRIMARY, plane)) {
3430 DRM_ERROR("KMS: Failed to initialize primary plane\n");
3436 * Initialize overlay planes, index starting after primary planes.
3437 * These planes have a higher DRM index than the primary planes since
3438 * they should be considered as having a higher z-order.
3439 * Order is reversed to match iteration order in atomic check.
3441 * Only support DCN for now, and only expose one so we don't encourage
3442 * userspace to use up all the pipes.
3444 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
3445 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
3447 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
3450 if (!plane->blends_with_above || !plane->blends_with_below)
3453 if (!plane->pixel_format_support.argb8888)
3456 if (initialize_plane(dm, NULL, primary_planes + i,
3457 DRM_PLANE_TYPE_OVERLAY, plane)) {
3458 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
3462 /* Only create one overlay plane. */
3466 for (i = 0; i < dm->dc->caps.max_streams; i++)
3467 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
3468 DRM_ERROR("KMS: Failed to initialize crtc\n");
3472 /* loops over all connectors on the board */
3473 for (i = 0; i < link_cnt; i++) {
3474 struct dc_link *link = NULL;
3476 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
3478 "KMS: Cannot support more than %d display indexes\n",
3479 AMDGPU_DM_MAX_DISPLAY_INDEX);
3483 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
3487 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
3491 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
3492 DRM_ERROR("KMS: Failed to initialize encoder\n");
3496 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
3497 DRM_ERROR("KMS: Failed to initialize connector\n");
3501 link = dc_get_link_at_index(dm->dc, i);
3503 if (!dc_link_detect_sink(link, &new_connection_type))
3504 DRM_ERROR("KMS: Failed to detect connector\n");
3506 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3507 emulated_link_detect(link);
3508 amdgpu_dm_update_connector_after_detect(aconnector);
3510 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
3511 amdgpu_dm_update_connector_after_detect(aconnector);
3512 register_backlight_device(dm, link);
3513 if (amdgpu_dc_feature_mask & DC_PSR_MASK)
3514 amdgpu_dm_set_psr_caps(link);
3520 /* Software is initialized. Now we can register interrupt handlers. */
3521 switch (adev->asic_type) {
3522 #if defined(CONFIG_DRM_AMD_DC_SI)
3527 if (dce60_register_irq_handlers(dm->adev)) {
3528 DRM_ERROR("DM: Failed to initialize IRQ\n");
3542 case CHIP_POLARIS11:
3543 case CHIP_POLARIS10:
3544 case CHIP_POLARIS12:
3549 if (dce110_register_irq_handlers(dm->adev)) {
3550 DRM_ERROR("DM: Failed to initialize IRQ\n");
3554 #if defined(CONFIG_DRM_AMD_DC_DCN)
3560 case CHIP_SIENNA_CICHLID:
3561 case CHIP_NAVY_FLOUNDER:
3562 case CHIP_DIMGREY_CAVEFISH:
3564 if (dcn10_register_irq_handlers(dm->adev)) {
3565 DRM_ERROR("DM: Failed to initialize IRQ\n");
3571 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3583 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
3585 drm_mode_config_cleanup(dm->ddev);
3586 drm_atomic_private_obj_fini(&dm->atomic_obj);
3590 /******************************************************************************
3591 * amdgpu_display_funcs functions
3592 *****************************************************************************/
3595 * dm_bandwidth_update - program display watermarks
3597 * @adev: amdgpu_device pointer
3599 * Calculate and program the display watermarks and line buffer allocation.
3601 static void dm_bandwidth_update(struct amdgpu_device *adev)
3603 /* TODO: implement later */
3606 static const struct amdgpu_display_funcs dm_display_funcs = {
3607 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
3608 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
3609 .backlight_set_level = NULL, /* never called for DC */
3610 .backlight_get_level = NULL, /* never called for DC */
3611 .hpd_sense = NULL,/* called unconditionally */
3612 .hpd_set_polarity = NULL, /* called unconditionally */
3613 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
3614 .page_flip_get_scanoutpos =
3615 dm_crtc_get_scanoutpos,/* called unconditionally */
3616 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
3617 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
3620 #if defined(CONFIG_DEBUG_KERNEL_DC)
3622 static ssize_t s3_debug_store(struct device *device,
3623 struct device_attribute *attr,
3629 struct drm_device *drm_dev = dev_get_drvdata(device);
3630 struct amdgpu_device *adev = drm_to_adev(drm_dev);
3632 ret = kstrtoint(buf, 0, &s3_state);
3637 drm_kms_helper_hotplug_event(adev_to_drm(adev));
3642 return ret == 0 ? count : 0;
3645 DEVICE_ATTR_WO(s3_debug);
3649 static int dm_early_init(void *handle)
3651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3653 switch (adev->asic_type) {
3654 #if defined(CONFIG_DRM_AMD_DC_SI)
3658 adev->mode_info.num_crtc = 6;
3659 adev->mode_info.num_hpd = 6;
3660 adev->mode_info.num_dig = 6;
3663 adev->mode_info.num_crtc = 2;
3664 adev->mode_info.num_hpd = 2;
3665 adev->mode_info.num_dig = 2;
3670 adev->mode_info.num_crtc = 6;
3671 adev->mode_info.num_hpd = 6;
3672 adev->mode_info.num_dig = 6;
3675 adev->mode_info.num_crtc = 4;
3676 adev->mode_info.num_hpd = 6;
3677 adev->mode_info.num_dig = 7;
3681 adev->mode_info.num_crtc = 2;
3682 adev->mode_info.num_hpd = 6;
3683 adev->mode_info.num_dig = 6;
3687 adev->mode_info.num_crtc = 6;
3688 adev->mode_info.num_hpd = 6;
3689 adev->mode_info.num_dig = 7;
3692 adev->mode_info.num_crtc = 3;
3693 adev->mode_info.num_hpd = 6;
3694 adev->mode_info.num_dig = 9;
3697 adev->mode_info.num_crtc = 2;
3698 adev->mode_info.num_hpd = 6;
3699 adev->mode_info.num_dig = 9;
3701 case CHIP_POLARIS11:
3702 case CHIP_POLARIS12:
3703 adev->mode_info.num_crtc = 5;
3704 adev->mode_info.num_hpd = 5;
3705 adev->mode_info.num_dig = 5;
3707 case CHIP_POLARIS10:
3709 adev->mode_info.num_crtc = 6;
3710 adev->mode_info.num_hpd = 6;
3711 adev->mode_info.num_dig = 6;
3716 adev->mode_info.num_crtc = 6;
3717 adev->mode_info.num_hpd = 6;
3718 adev->mode_info.num_dig = 6;
3720 #if defined(CONFIG_DRM_AMD_DC_DCN)
3724 adev->mode_info.num_crtc = 4;
3725 adev->mode_info.num_hpd = 4;
3726 adev->mode_info.num_dig = 4;
3730 case CHIP_SIENNA_CICHLID:
3731 case CHIP_NAVY_FLOUNDER:
3732 adev->mode_info.num_crtc = 6;
3733 adev->mode_info.num_hpd = 6;
3734 adev->mode_info.num_dig = 6;
3737 case CHIP_DIMGREY_CAVEFISH:
3738 adev->mode_info.num_crtc = 5;
3739 adev->mode_info.num_hpd = 5;
3740 adev->mode_info.num_dig = 5;
3744 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3748 amdgpu_dm_set_irq_funcs(adev);
3750 if (adev->mode_info.funcs == NULL)
3751 adev->mode_info.funcs = &dm_display_funcs;
3754 * Note: Do NOT change adev->audio_endpt_rreg and
3755 * adev->audio_endpt_wreg because they are initialised in
3756 * amdgpu_device_init()
3758 #if defined(CONFIG_DEBUG_KERNEL_DC)
3760 adev_to_drm(adev)->dev,
3761 &dev_attr_s3_debug);
3767 static bool modeset_required(struct drm_crtc_state *crtc_state,
3768 struct dc_stream_state *new_stream,
3769 struct dc_stream_state *old_stream)
3771 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3774 static bool modereset_required(struct drm_crtc_state *crtc_state)
3776 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3779 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3781 drm_encoder_cleanup(encoder);
3785 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3786 .destroy = amdgpu_dm_encoder_destroy,
3790 static void get_min_max_dc_plane_scaling(struct drm_device *dev,
3791 struct drm_framebuffer *fb,
3792 int *min_downscale, int *max_upscale)
3794 struct amdgpu_device *adev = drm_to_adev(dev);
3795 struct dc *dc = adev->dm.dc;
3796 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
3797 struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
3799 switch (fb->format->format) {
3800 case DRM_FORMAT_P010:
3801 case DRM_FORMAT_NV12:
3802 case DRM_FORMAT_NV21:
3803 *max_upscale = plane_cap->max_upscale_factor.nv12;
3804 *min_downscale = plane_cap->max_downscale_factor.nv12;
3807 case DRM_FORMAT_XRGB16161616F:
3808 case DRM_FORMAT_ARGB16161616F:
3809 case DRM_FORMAT_XBGR16161616F:
3810 case DRM_FORMAT_ABGR16161616F:
3811 *max_upscale = plane_cap->max_upscale_factor.fp16;
3812 *min_downscale = plane_cap->max_downscale_factor.fp16;
3816 *max_upscale = plane_cap->max_upscale_factor.argb8888;
3817 *min_downscale = plane_cap->max_downscale_factor.argb8888;
3822 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a
3823 * scaling factor of 1.0 == 1000 units.
3825 if (*max_upscale == 1)
3826 *max_upscale = 1000;
3828 if (*min_downscale == 1)
3829 *min_downscale = 1000;
3833 static int fill_dc_scaling_info(const struct drm_plane_state *state,
3834 struct dc_scaling_info *scaling_info)
3836 int scale_w, scale_h, min_downscale, max_upscale;
3838 memset(scaling_info, 0, sizeof(*scaling_info));
3840 /* Source is fixed 16.16 but we ignore mantissa for now... */
3841 scaling_info->src_rect.x = state->src_x >> 16;
3842 scaling_info->src_rect.y = state->src_y >> 16;
3844 scaling_info->src_rect.width = state->src_w >> 16;
3845 if (scaling_info->src_rect.width == 0)
3848 scaling_info->src_rect.height = state->src_h >> 16;
3849 if (scaling_info->src_rect.height == 0)
3852 scaling_info->dst_rect.x = state->crtc_x;
3853 scaling_info->dst_rect.y = state->crtc_y;
3855 if (state->crtc_w == 0)
3858 scaling_info->dst_rect.width = state->crtc_w;
3860 if (state->crtc_h == 0)
3863 scaling_info->dst_rect.height = state->crtc_h;
3865 /* DRM doesn't specify clipping on destination output. */
3866 scaling_info->clip_rect = scaling_info->dst_rect;
3868 /* Validate scaling per-format with DC plane caps */
3869 if (state->plane && state->plane->dev && state->fb) {
3870 get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
3871 &min_downscale, &max_upscale);
3873 min_downscale = 250;
3874 max_upscale = 16000;
3877 scale_w = scaling_info->dst_rect.width * 1000 /
3878 scaling_info->src_rect.width;
3880 if (scale_w < min_downscale || scale_w > max_upscale)
3883 scale_h = scaling_info->dst_rect.height * 1000 /
3884 scaling_info->src_rect.height;
3886 if (scale_h < min_downscale || scale_h > max_upscale)
3890 * The "scaling_quality" can be ignored for now, quality = 0 has DC
3891 * assume reasonable defaults based on the format.
3898 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
3899 uint64_t tiling_flags)
3901 /* Fill GFX8 params */
3902 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3903 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
3905 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3906 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3907 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
3908 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3909 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
3911 /* XXX fix me for VI */
3912 tiling_info->gfx8.num_banks = num_banks;
3913 tiling_info->gfx8.array_mode =
3914 DC_ARRAY_2D_TILED_THIN1;
3915 tiling_info->gfx8.tile_split = tile_split;
3916 tiling_info->gfx8.bank_width = bankw;
3917 tiling_info->gfx8.bank_height = bankh;
3918 tiling_info->gfx8.tile_aspect = mtaspect;
3919 tiling_info->gfx8.tile_mode =
3920 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
3921 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
3922 == DC_ARRAY_1D_TILED_THIN1) {
3923 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
3926 tiling_info->gfx8.pipe_config =
3927 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
3931 fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
3932 union dc_tiling_info *tiling_info)
3934 tiling_info->gfx9.num_pipes =
3935 adev->gfx.config.gb_addr_config_fields.num_pipes;
3936 tiling_info->gfx9.num_banks =
3937 adev->gfx.config.gb_addr_config_fields.num_banks;
3938 tiling_info->gfx9.pipe_interleave =
3939 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3940 tiling_info->gfx9.num_shader_engines =
3941 adev->gfx.config.gb_addr_config_fields.num_se;
3942 tiling_info->gfx9.max_compressed_frags =
3943 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3944 tiling_info->gfx9.num_rb_per_se =
3945 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3946 tiling_info->gfx9.shaderEnable = 1;
3947 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
3948 adev->asic_type == CHIP_NAVY_FLOUNDER ||
3949 adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
3950 adev->asic_type == CHIP_VANGOGH)
3951 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
3955 validate_dcc(struct amdgpu_device *adev,
3956 const enum surface_pixel_format format,
3957 const enum dc_rotation_angle rotation,
3958 const union dc_tiling_info *tiling_info,
3959 const struct dc_plane_dcc_param *dcc,
3960 const struct dc_plane_address *address,
3961 const struct plane_size *plane_size)
3963 struct dc *dc = adev->dm.dc;
3964 struct dc_dcc_surface_param input;
3965 struct dc_surface_dcc_cap output;
3967 memset(&input, 0, sizeof(input));
3968 memset(&output, 0, sizeof(output));
3973 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
3974 !dc->cap_funcs.get_dcc_compression_cap)
3977 input.format = format;
3978 input.surface_size.width = plane_size->surface_size.width;
3979 input.surface_size.height = plane_size->surface_size.height;
3980 input.swizzle_mode = tiling_info->gfx9.swizzle;
3982 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
3983 input.scan = SCAN_DIRECTION_HORIZONTAL;
3984 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
3985 input.scan = SCAN_DIRECTION_VERTICAL;
3987 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
3990 if (!output.capable)
3993 if (dcc->independent_64b_blks == 0 &&
3994 output.grph.rgb.independent_64b_blks != 0)
4001 modifier_has_dcc(uint64_t modifier)
4003 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
4007 modifier_gfx9_swizzle_mode(uint64_t modifier)
4009 if (modifier == DRM_FORMAT_MOD_LINEAR)
4012 return AMD_FMT_MOD_GET(TILE, modifier);
4015 static const struct drm_format_info *
4016 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
4018 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
4022 fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
4023 union dc_tiling_info *tiling_info,
4026 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
4027 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
4028 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
4029 unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
4031 fill_gfx9_tiling_info_from_device(adev, tiling_info);
4033 if (!IS_AMD_FMT_MOD(modifier))
4036 tiling_info->gfx9.num_pipes = 1u << pipes_log2;
4037 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
4039 if (adev->family >= AMDGPU_FAMILY_NV) {
4040 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
4042 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
4044 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
4048 enum dm_micro_swizzle {
4049 MICRO_SWIZZLE_Z = 0,
4050 MICRO_SWIZZLE_S = 1,
4051 MICRO_SWIZZLE_D = 2,
4055 static bool dm_plane_format_mod_supported(struct drm_plane *plane,
4059 struct amdgpu_device *adev = drm_to_adev(plane->dev);
4060 const struct drm_format_info *info = drm_format_info(format);
4062 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
4068 * We always have to allow this modifier, because core DRM still
4069 * checks LINEAR support if userspace does not provide modifers.
4071 if (modifier == DRM_FORMAT_MOD_LINEAR)
4075 * For D swizzle the canonical modifier depends on the bpp, so check
4078 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
4079 adev->family >= AMDGPU_FAMILY_NV) {
4080 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
4084 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
4088 if (modifier_has_dcc(modifier)) {
4089 /* Per radeonsi comments 16/64 bpp are more complicated. */
4090 if (info->cpp[0] != 4)
4092 /* We support multi-planar formats, but not when combined with
4093 * additional DCC metadata planes. */
4094 if (info->num_planes > 1)
4102 add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
4107 if (*cap - *size < 1) {
4108 uint64_t new_cap = *cap * 2;
4109 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
4117 memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
4123 (*mods)[*size] = mod;
4128 add_gfx9_modifiers(const struct amdgpu_device *adev,
4129 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4131 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4132 int pipe_xor_bits = min(8, pipes +
4133 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
4134 int bank_xor_bits = min(8 - pipe_xor_bits,
4135 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
4136 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
4137 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
4140 if (adev->family == AMDGPU_FAMILY_RV) {
4141 /* Raven2 and later */
4142 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
4145 * No _D DCC swizzles yet because we only allow 32bpp, which
4146 * doesn't support _D on DCN
4149 if (has_constant_encode) {
4150 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4151 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4152 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4153 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4154 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4155 AMD_FMT_MOD_SET(DCC, 1) |
4156 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4157 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4158 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
4161 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4162 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4163 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4164 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4165 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4166 AMD_FMT_MOD_SET(DCC, 1) |
4167 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4168 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4169 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
4171 if (has_constant_encode) {
4172 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4173 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4174 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4175 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4176 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4177 AMD_FMT_MOD_SET(DCC, 1) |
4178 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4179 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4180 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4182 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4183 AMD_FMT_MOD_SET(RB, rb) |
4184 AMD_FMT_MOD_SET(PIPE, pipes));
4187 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4188 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4189 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4190 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4191 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4192 AMD_FMT_MOD_SET(DCC, 1) |
4193 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4194 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4195 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4196 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
4197 AMD_FMT_MOD_SET(RB, rb) |
4198 AMD_FMT_MOD_SET(PIPE, pipes));
4202 * Only supported for 64bpp on Raven, will be filtered on format in
4203 * dm_plane_format_mod_supported.
4205 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4206 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
4207 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4208 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4209 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4211 if (adev->family == AMDGPU_FAMILY_RV) {
4212 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4213 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4214 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4215 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4216 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4220 * Only supported for 64bpp on Raven, will be filtered on format in
4221 * dm_plane_format_mod_supported.
4223 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4224 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4225 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4227 if (adev->family == AMDGPU_FAMILY_RV) {
4228 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4229 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4230 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4235 add_gfx10_1_modifiers(const struct amdgpu_device *adev,
4236 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4238 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4240 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4241 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4242 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4243 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4244 AMD_FMT_MOD_SET(DCC, 1) |
4245 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4246 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4247 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4249 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4250 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4251 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4252 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4253 AMD_FMT_MOD_SET(DCC, 1) |
4254 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4255 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4256 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4257 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4259 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4260 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4261 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4262 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4264 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4265 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4266 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4267 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4270 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4271 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4272 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4273 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4275 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4276 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4277 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4281 add_gfx10_3_modifiers(const struct amdgpu_device *adev,
4282 uint64_t **mods, uint64_t *size, uint64_t *capacity)
4284 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4285 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
4287 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4288 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4289 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4290 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4291 AMD_FMT_MOD_SET(PACKERS, pkrs) |
4292 AMD_FMT_MOD_SET(DCC, 1) |
4293 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4294 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4295 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4296 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4298 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4299 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4300 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4301 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4302 AMD_FMT_MOD_SET(PACKERS, pkrs) |
4303 AMD_FMT_MOD_SET(DCC, 1) |
4304 AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4305 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4306 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4307 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4308 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4310 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4311 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4312 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4313 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4314 AMD_FMT_MOD_SET(PACKERS, pkrs));
4316 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4317 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4318 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4319 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4320 AMD_FMT_MOD_SET(PACKERS, pkrs));
4322 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4323 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4324 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4325 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4327 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4328 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4329 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4333 get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
4335 uint64_t size = 0, capacity = 128;
4338 /* We have not hooked up any pre-GFX9 modifiers. */
4339 if (adev->family < AMDGPU_FAMILY_AI)
4342 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
4344 if (plane_type == DRM_PLANE_TYPE_CURSOR) {
4345 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4346 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4347 return *mods ? 0 : -ENOMEM;
4350 switch (adev->family) {
4351 case AMDGPU_FAMILY_AI:
4352 case AMDGPU_FAMILY_RV:
4353 add_gfx9_modifiers(adev, mods, &size, &capacity);
4355 case AMDGPU_FAMILY_NV:
4356 case AMDGPU_FAMILY_VGH:
4357 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4358 add_gfx10_3_modifiers(adev, mods, &size, &capacity);
4360 add_gfx10_1_modifiers(adev, mods, &size, &capacity);
4364 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4366 /* INVALID marks the end of the list. */
4367 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4376 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
4377 const struct amdgpu_framebuffer *afb,
4378 const enum surface_pixel_format format,
4379 const enum dc_rotation_angle rotation,
4380 const struct plane_size *plane_size,
4381 union dc_tiling_info *tiling_info,
4382 struct dc_plane_dcc_param *dcc,
4383 struct dc_plane_address *address,
4384 const bool force_disable_dcc)
4386 const uint64_t modifier = afb->base.modifier;
4389 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
4390 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
4392 if (modifier_has_dcc(modifier) && !force_disable_dcc) {
4393 uint64_t dcc_address = afb->address + afb->base.offsets[1];
4396 dcc->meta_pitch = afb->base.pitches[1];
4397 dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
4399 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
4400 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
4403 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
4411 fill_plane_buffer_attributes(struct amdgpu_device *adev,
4412 const struct amdgpu_framebuffer *afb,
4413 const enum surface_pixel_format format,
4414 const enum dc_rotation_angle rotation,
4415 const uint64_t tiling_flags,
4416 union dc_tiling_info *tiling_info,
4417 struct plane_size *plane_size,
4418 struct dc_plane_dcc_param *dcc,
4419 struct dc_plane_address *address,
4421 bool force_disable_dcc)
4423 const struct drm_framebuffer *fb = &afb->base;
4426 memset(tiling_info, 0, sizeof(*tiling_info));
4427 memset(plane_size, 0, sizeof(*plane_size));
4428 memset(dcc, 0, sizeof(*dcc));
4429 memset(address, 0, sizeof(*address));
4431 address->tmz_surface = tmz_surface;
4433 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
4434 uint64_t addr = afb->address + fb->offsets[0];
4436 plane_size->surface_size.x = 0;
4437 plane_size->surface_size.y = 0;
4438 plane_size->surface_size.width = fb->width;
4439 plane_size->surface_size.height = fb->height;
4440 plane_size->surface_pitch =
4441 fb->pitches[0] / fb->format->cpp[0];
4443 address->type = PLN_ADDR_TYPE_GRAPHICS;
4444 address->grph.addr.low_part = lower_32_bits(addr);
4445 address->grph.addr.high_part = upper_32_bits(addr);
4446 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
4447 uint64_t luma_addr = afb->address + fb->offsets[0];
4448 uint64_t chroma_addr = afb->address + fb->offsets[1];
4450 plane_size->surface_size.x = 0;
4451 plane_size->surface_size.y = 0;
4452 plane_size->surface_size.width = fb->width;
4453 plane_size->surface_size.height = fb->height;
4454 plane_size->surface_pitch =
4455 fb->pitches[0] / fb->format->cpp[0];
4457 plane_size->chroma_size.x = 0;
4458 plane_size->chroma_size.y = 0;
4459 /* TODO: set these based on surface format */
4460 plane_size->chroma_size.width = fb->width / 2;
4461 plane_size->chroma_size.height = fb->height / 2;
4463 plane_size->chroma_pitch =
4464 fb->pitches[1] / fb->format->cpp[1];
4466 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
4467 address->video_progressive.luma_addr.low_part =
4468 lower_32_bits(luma_addr);
4469 address->video_progressive.luma_addr.high_part =
4470 upper_32_bits(luma_addr);
4471 address->video_progressive.chroma_addr.low_part =
4472 lower_32_bits(chroma_addr);
4473 address->video_progressive.chroma_addr.high_part =
4474 upper_32_bits(chroma_addr);
4477 if (adev->family >= AMDGPU_FAMILY_AI) {
4478 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
4479 rotation, plane_size,
4486 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
4493 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
4494 bool *per_pixel_alpha, bool *global_alpha,
4495 int *global_alpha_value)
4497 *per_pixel_alpha = false;
4498 *global_alpha = false;
4499 *global_alpha_value = 0xff;
4501 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
4504 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
4505 static const uint32_t alpha_formats[] = {
4506 DRM_FORMAT_ARGB8888,
4507 DRM_FORMAT_RGBA8888,
4508 DRM_FORMAT_ABGR8888,
4510 uint32_t format = plane_state->fb->format->format;
4513 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
4514 if (format == alpha_formats[i]) {
4515 *per_pixel_alpha = true;
4521 if (plane_state->alpha < 0xffff) {
4522 *global_alpha = true;
4523 *global_alpha_value = plane_state->alpha >> 8;
4528 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4529 const enum surface_pixel_format format,
4530 enum dc_color_space *color_space)
4534 *color_space = COLOR_SPACE_SRGB;
4536 /* DRM color properties only affect non-RGB formats. */
4537 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4540 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4542 switch (plane_state->color_encoding) {
4543 case DRM_COLOR_YCBCR_BT601:
4545 *color_space = COLOR_SPACE_YCBCR601;
4547 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4550 case DRM_COLOR_YCBCR_BT709:
4552 *color_space = COLOR_SPACE_YCBCR709;
4554 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4557 case DRM_COLOR_YCBCR_BT2020:
4559 *color_space = COLOR_SPACE_2020_YCBCR;
4572 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4573 const struct drm_plane_state *plane_state,
4574 const uint64_t tiling_flags,
4575 struct dc_plane_info *plane_info,
4576 struct dc_plane_address *address,
4578 bool force_disable_dcc)
4580 const struct drm_framebuffer *fb = plane_state->fb;
4581 const struct amdgpu_framebuffer *afb =
4582 to_amdgpu_framebuffer(plane_state->fb);
4583 struct drm_format_name_buf format_name;
4586 memset(plane_info, 0, sizeof(*plane_info));
4588 switch (fb->format->format) {
4590 plane_info->format =
4591 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4593 case DRM_FORMAT_RGB565:
4594 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4596 case DRM_FORMAT_XRGB8888:
4597 case DRM_FORMAT_ARGB8888:
4598 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4600 case DRM_FORMAT_XRGB2101010:
4601 case DRM_FORMAT_ARGB2101010:
4602 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4604 case DRM_FORMAT_XBGR2101010:
4605 case DRM_FORMAT_ABGR2101010:
4606 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4608 case DRM_FORMAT_XBGR8888:
4609 case DRM_FORMAT_ABGR8888:
4610 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4612 case DRM_FORMAT_NV21:
4613 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4615 case DRM_FORMAT_NV12:
4616 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4618 case DRM_FORMAT_P010:
4619 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4621 case DRM_FORMAT_XRGB16161616F:
4622 case DRM_FORMAT_ARGB16161616F:
4623 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4625 case DRM_FORMAT_XBGR16161616F:
4626 case DRM_FORMAT_ABGR16161616F:
4627 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4631 "Unsupported screen format %s\n",
4632 drm_get_format_name(fb->format->format, &format_name));
4636 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4637 case DRM_MODE_ROTATE_0:
4638 plane_info->rotation = ROTATION_ANGLE_0;
4640 case DRM_MODE_ROTATE_90:
4641 plane_info->rotation = ROTATION_ANGLE_90;
4643 case DRM_MODE_ROTATE_180:
4644 plane_info->rotation = ROTATION_ANGLE_180;
4646 case DRM_MODE_ROTATE_270:
4647 plane_info->rotation = ROTATION_ANGLE_270;
4650 plane_info->rotation = ROTATION_ANGLE_0;
4654 plane_info->visible = true;
4655 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4657 plane_info->layer_index = 0;
4659 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4660 &plane_info->color_space);
4664 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4665 plane_info->rotation, tiling_flags,
4666 &plane_info->tiling_info,
4667 &plane_info->plane_size,
4668 &plane_info->dcc, address, tmz_surface,
4673 fill_blending_from_plane_state(
4674 plane_state, &plane_info->per_pixel_alpha,
4675 &plane_info->global_alpha, &plane_info->global_alpha_value);
4680 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4681 struct dc_plane_state *dc_plane_state,
4682 struct drm_plane_state *plane_state,
4683 struct drm_crtc_state *crtc_state)
4685 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4686 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4687 struct dc_scaling_info scaling_info;
4688 struct dc_plane_info plane_info;
4690 bool force_disable_dcc = false;
4692 ret = fill_dc_scaling_info(plane_state, &scaling_info);
4696 dc_plane_state->src_rect = scaling_info.src_rect;
4697 dc_plane_state->dst_rect = scaling_info.dst_rect;
4698 dc_plane_state->clip_rect = scaling_info.clip_rect;
4699 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4701 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4702 ret = fill_dc_plane_info_and_addr(adev, plane_state,
4705 &dc_plane_state->address,
4711 dc_plane_state->format = plane_info.format;
4712 dc_plane_state->color_space = plane_info.color_space;
4713 dc_plane_state->format = plane_info.format;
4714 dc_plane_state->plane_size = plane_info.plane_size;
4715 dc_plane_state->rotation = plane_info.rotation;
4716 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4717 dc_plane_state->stereo_format = plane_info.stereo_format;
4718 dc_plane_state->tiling_info = plane_info.tiling_info;
4719 dc_plane_state->visible = plane_info.visible;
4720 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4721 dc_plane_state->global_alpha = plane_info.global_alpha;
4722 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4723 dc_plane_state->dcc = plane_info.dcc;
4724 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
4725 dc_plane_state->flip_int_enabled = true;
4728 * Always set input transfer function, since plane state is refreshed
4731 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4738 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4739 const struct dm_connector_state *dm_state,
4740 struct dc_stream_state *stream)
4742 enum amdgpu_rmx_type rmx_type;
4744 struct rect src = { 0 }; /* viewport in composition space*/
4745 struct rect dst = { 0 }; /* stream addressable area */
4747 /* no mode. nothing to be done */
4751 /* Full screen scaling by default */
4752 src.width = mode->hdisplay;
4753 src.height = mode->vdisplay;
4754 dst.width = stream->timing.h_addressable;
4755 dst.height = stream->timing.v_addressable;
4758 rmx_type = dm_state->scaling;
4759 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4760 if (src.width * dst.height <
4761 src.height * dst.width) {
4762 /* height needs less upscaling/more downscaling */
4763 dst.width = src.width *
4764 dst.height / src.height;
4766 /* width needs less upscaling/more downscaling */
4767 dst.height = src.height *
4768 dst.width / src.width;
4770 } else if (rmx_type == RMX_CENTER) {
4774 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4775 dst.y = (stream->timing.v_addressable - dst.height) / 2;
4777 if (dm_state->underscan_enable) {
4778 dst.x += dm_state->underscan_hborder / 2;
4779 dst.y += dm_state->underscan_vborder / 2;
4780 dst.width -= dm_state->underscan_hborder;
4781 dst.height -= dm_state->underscan_vborder;
4788 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
4789 dst.x, dst.y, dst.width, dst.height);
4793 static enum dc_color_depth
4794 convert_color_depth_from_display_info(const struct drm_connector *connector,
4795 bool is_y420, int requested_bpc)
4802 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
4803 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
4805 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
4807 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
4810 bpc = (uint8_t)connector->display_info.bpc;
4811 /* Assume 8 bpc by default if no bpc is specified. */
4812 bpc = bpc ? bpc : 8;
4815 if (requested_bpc > 0) {
4817 * Cap display bpc based on the user requested value.
4819 * The value for state->max_bpc may not correctly updated
4820 * depending on when the connector gets added to the state
4821 * or if this was called outside of atomic check, so it
4822 * can't be used directly.
4824 bpc = min_t(u8, bpc, requested_bpc);
4826 /* Round down to the nearest even number. */
4827 bpc = bpc - (bpc & 1);
4833 * Temporary Work around, DRM doesn't parse color depth for
4834 * EDID revision before 1.4
4835 * TODO: Fix edid parsing
4837 return COLOR_DEPTH_888;
4839 return COLOR_DEPTH_666;
4841 return COLOR_DEPTH_888;
4843 return COLOR_DEPTH_101010;
4845 return COLOR_DEPTH_121212;
4847 return COLOR_DEPTH_141414;
4849 return COLOR_DEPTH_161616;
4851 return COLOR_DEPTH_UNDEFINED;
4855 static enum dc_aspect_ratio
4856 get_aspect_ratio(const struct drm_display_mode *mode_in)
4858 /* 1-1 mapping, since both enums follow the HDMI spec. */
4859 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
4862 static enum dc_color_space
4863 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
4865 enum dc_color_space color_space = COLOR_SPACE_SRGB;
4867 switch (dc_crtc_timing->pixel_encoding) {
4868 case PIXEL_ENCODING_YCBCR422:
4869 case PIXEL_ENCODING_YCBCR444:
4870 case PIXEL_ENCODING_YCBCR420:
4873 * 27030khz is the separation point between HDTV and SDTV
4874 * according to HDMI spec, we use YCbCr709 and YCbCr601
4877 if (dc_crtc_timing->pix_clk_100hz > 270300) {
4878 if (dc_crtc_timing->flags.Y_ONLY)
4880 COLOR_SPACE_YCBCR709_LIMITED;
4882 color_space = COLOR_SPACE_YCBCR709;
4884 if (dc_crtc_timing->flags.Y_ONLY)
4886 COLOR_SPACE_YCBCR601_LIMITED;
4888 color_space = COLOR_SPACE_YCBCR601;
4893 case PIXEL_ENCODING_RGB:
4894 color_space = COLOR_SPACE_SRGB;
4905 static bool adjust_colour_depth_from_display_info(
4906 struct dc_crtc_timing *timing_out,
4907 const struct drm_display_info *info)
4909 enum dc_color_depth depth = timing_out->display_color_depth;
4912 normalized_clk = timing_out->pix_clk_100hz / 10;
4913 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
4914 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4915 normalized_clk /= 2;
4916 /* Adjusting pix clock following on HDMI spec based on colour depth */
4918 case COLOR_DEPTH_888:
4920 case COLOR_DEPTH_101010:
4921 normalized_clk = (normalized_clk * 30) / 24;
4923 case COLOR_DEPTH_121212:
4924 normalized_clk = (normalized_clk * 36) / 24;
4926 case COLOR_DEPTH_161616:
4927 normalized_clk = (normalized_clk * 48) / 24;
4930 /* The above depths are the only ones valid for HDMI. */
4933 if (normalized_clk <= info->max_tmds_clock) {
4934 timing_out->display_color_depth = depth;
4937 } while (--depth > COLOR_DEPTH_666);
4941 static void fill_stream_properties_from_drm_display_mode(
4942 struct dc_stream_state *stream,
4943 const struct drm_display_mode *mode_in,
4944 const struct drm_connector *connector,
4945 const struct drm_connector_state *connector_state,
4946 const struct dc_stream_state *old_stream,
4949 struct dc_crtc_timing *timing_out = &stream->timing;
4950 const struct drm_display_info *info = &connector->display_info;
4951 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4952 struct hdmi_vendor_infoframe hv_frame;
4953 struct hdmi_avi_infoframe avi_frame;
4955 memset(&hv_frame, 0, sizeof(hv_frame));
4956 memset(&avi_frame, 0, sizeof(avi_frame));
4958 timing_out->h_border_left = 0;
4959 timing_out->h_border_right = 0;
4960 timing_out->v_border_top = 0;
4961 timing_out->v_border_bottom = 0;
4962 /* TODO: un-hardcode */
4963 if (drm_mode_is_420_only(info, mode_in)
4964 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4965 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
4966 else if (drm_mode_is_420_also(info, mode_in)
4967 && aconnector->force_yuv420_output)
4968 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
4969 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
4970 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4971 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
4973 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
4975 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
4976 timing_out->display_color_depth = convert_color_depth_from_display_info(
4978 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
4980 timing_out->scan_type = SCANNING_TYPE_NODATA;
4981 timing_out->hdmi_vic = 0;
4984 timing_out->vic = old_stream->timing.vic;
4985 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
4986 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
4988 timing_out->vic = drm_match_cea_mode(mode_in);
4989 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
4990 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
4991 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
4992 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
4995 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4996 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
4997 timing_out->vic = avi_frame.video_code;
4998 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
4999 timing_out->hdmi_vic = hv_frame.vic;
5002 timing_out->h_addressable = mode_in->crtc_hdisplay;
5003 timing_out->h_total = mode_in->crtc_htotal;
5004 timing_out->h_sync_width =
5005 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5006 timing_out->h_front_porch =
5007 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5008 timing_out->v_total = mode_in->crtc_vtotal;
5009 timing_out->v_addressable = mode_in->crtc_vdisplay;
5010 timing_out->v_front_porch =
5011 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5012 timing_out->v_sync_width =
5013 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5014 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5015 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5017 stream->output_color_space = get_output_color_space(timing_out);
5019 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5020 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5021 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5022 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5023 drm_mode_is_420_also(info, mode_in) &&
5024 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5025 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5026 adjust_colour_depth_from_display_info(timing_out, info);
5031 static void fill_audio_info(struct audio_info *audio_info,
5032 const struct drm_connector *drm_connector,
5033 const struct dc_sink *dc_sink)
5036 int cea_revision = 0;
5037 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5039 audio_info->manufacture_id = edid_caps->manufacturer_id;
5040 audio_info->product_id = edid_caps->product_id;
5042 cea_revision = drm_connector->display_info.cea_rev;
5044 strscpy(audio_info->display_name,
5045 edid_caps->display_name,
5046 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5048 if (cea_revision >= 3) {
5049 audio_info->mode_count = edid_caps->audio_mode_count;
5051 for (i = 0; i < audio_info->mode_count; ++i) {
5052 audio_info->modes[i].format_code =
5053 (enum audio_format_code)
5054 (edid_caps->audio_modes[i].format_code);
5055 audio_info->modes[i].channel_count =
5056 edid_caps->audio_modes[i].channel_count;
5057 audio_info->modes[i].sample_rates.all =
5058 edid_caps->audio_modes[i].sample_rate;
5059 audio_info->modes[i].sample_size =
5060 edid_caps->audio_modes[i].sample_size;
5064 audio_info->flags.all = edid_caps->speaker_flags;
5066 /* TODO: We only check for the progressive mode, check for interlace mode too */
5067 if (drm_connector->latency_present[0]) {
5068 audio_info->video_latency = drm_connector->video_latency[0];
5069 audio_info->audio_latency = drm_connector->audio_latency[0];
5072 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5077 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5078 struct drm_display_mode *dst_mode)
5080 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5081 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5082 dst_mode->crtc_clock = src_mode->crtc_clock;
5083 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5084 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5085 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5086 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5087 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5088 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5089 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5090 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5091 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5092 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5093 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5097 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5098 const struct drm_display_mode *native_mode,
5101 if (scale_enabled) {
5102 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5103 } else if (native_mode->clock == drm_mode->clock &&
5104 native_mode->htotal == drm_mode->htotal &&
5105 native_mode->vtotal == drm_mode->vtotal) {
5106 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5108 /* no scaling nor amdgpu inserted, no need to patch */
5112 static struct dc_sink *
5113 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5115 struct dc_sink_init_data sink_init_data = { 0 };
5116 struct dc_sink *sink = NULL;
5117 sink_init_data.link = aconnector->dc_link;
5118 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5120 sink = dc_sink_create(&sink_init_data);
5122 DRM_ERROR("Failed to create sink!\n");
5125 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5130 static void set_multisync_trigger_params(
5131 struct dc_stream_state *stream)
5133 if (stream->triggered_crtc_reset.enabled) {
5134 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
5135 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
5139 static void set_master_stream(struct dc_stream_state *stream_set[],
5142 int j, highest_rfr = 0, master_stream = 0;
5144 for (j = 0; j < stream_count; j++) {
5145 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5146 int refresh_rate = 0;
5148 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5149 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5150 if (refresh_rate > highest_rfr) {
5151 highest_rfr = refresh_rate;
5156 for (j = 0; j < stream_count; j++) {
5158 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5162 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5166 if (context->stream_count < 2)
5168 for (i = 0; i < context->stream_count ; i++) {
5169 if (!context->streams[i])
5172 * TODO: add a function to read AMD VSDB bits and set
5173 * crtc_sync_master.multi_sync_enabled flag
5174 * For now it's set to false
5176 set_multisync_trigger_params(context->streams[i]);
5178 set_master_stream(context->streams, context->stream_count);
5181 static struct dc_stream_state *
5182 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5183 const struct drm_display_mode *drm_mode,
5184 const struct dm_connector_state *dm_state,
5185 const struct dc_stream_state *old_stream,
5188 struct drm_display_mode *preferred_mode = NULL;
5189 struct drm_connector *drm_connector;
5190 const struct drm_connector_state *con_state =
5191 dm_state ? &dm_state->base : NULL;
5192 struct dc_stream_state *stream = NULL;
5193 struct drm_display_mode mode = *drm_mode;
5194 bool native_mode_found = false;
5195 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5197 int preferred_refresh = 0;
5198 #if defined(CONFIG_DRM_AMD_DC_DCN)
5199 struct dsc_dec_dpcd_caps dsc_caps;
5200 uint32_t link_bandwidth_kbps;
5202 struct dc_sink *sink = NULL;
5203 if (aconnector == NULL) {
5204 DRM_ERROR("aconnector is NULL!\n");
5208 drm_connector = &aconnector->base;
5210 if (!aconnector->dc_sink) {
5211 sink = create_fake_sink(aconnector);
5215 sink = aconnector->dc_sink;
5216 dc_sink_retain(sink);
5219 stream = dc_create_stream_for_sink(sink);
5221 if (stream == NULL) {
5222 DRM_ERROR("Failed to create stream for sink!\n");
5226 stream->dm_stream_context = aconnector;
5228 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5229 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5231 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5232 /* Search for preferred mode */
5233 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5234 native_mode_found = true;
5238 if (!native_mode_found)
5239 preferred_mode = list_first_entry_or_null(
5240 &aconnector->base.modes,
5241 struct drm_display_mode,
5244 mode_refresh = drm_mode_vrefresh(&mode);
5246 if (preferred_mode == NULL) {
5248 * This may not be an error, the use case is when we have no
5249 * usermode calls to reset and set mode upon hotplug. In this
5250 * case, we call set mode ourselves to restore the previous mode
5251 * and the modelist may not be filled in in time.
5253 DRM_DEBUG_DRIVER("No preferred mode found\n");
5255 decide_crtc_timing_for_drm_display_mode(
5256 &mode, preferred_mode,
5257 dm_state ? (dm_state->scaling != RMX_OFF) : false);
5258 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5262 drm_mode_set_crtcinfo(&mode, 0);
5265 * If scaling is enabled and refresh rate didn't change
5266 * we copy the vic and polarities of the old timings
5268 if (!scale || mode_refresh != preferred_refresh)
5269 fill_stream_properties_from_drm_display_mode(stream,
5270 &mode, &aconnector->base, con_state, NULL, requested_bpc);
5272 fill_stream_properties_from_drm_display_mode(stream,
5273 &mode, &aconnector->base, con_state, old_stream, requested_bpc);
5275 stream->timing.flags.DSC = 0;
5277 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5278 #if defined(CONFIG_DRM_AMD_DC_DCN)
5279 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5280 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5281 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5283 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5284 dc_link_get_link_cap(aconnector->dc_link));
5286 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) {
5287 /* Set DSC policy according to dsc_clock_en */
5288 dc_dsc_policy_set_enable_dsc_when_not_needed(
5289 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5291 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5293 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5295 link_bandwidth_kbps,
5297 &stream->timing.dsc_cfg))
5298 stream->timing.flags.DSC = 1;
5299 /* Overwrite the stream flag if DSC is enabled through debugfs */
5300 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5301 stream->timing.flags.DSC = 1;
5303 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5304 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5306 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5307 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5309 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5310 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5315 update_stream_scaling_settings(&mode, dm_state, stream);
5318 &stream->audio_info,
5322 update_stream_signal(stream, sink);
5324 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5325 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5327 if (stream->link->psr_settings.psr_feature_enabled) {
5329 // should decide stream support vsc sdp colorimetry capability
5330 // before building vsc info packet
5332 stream->use_vsc_sdp_for_colorimetry = false;
5333 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5334 stream->use_vsc_sdp_for_colorimetry =
5335 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5337 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5338 stream->use_vsc_sdp_for_colorimetry = true;
5340 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
5343 dc_sink_release(sink);
5348 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
5350 drm_crtc_cleanup(crtc);
5354 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
5355 struct drm_crtc_state *state)
5357 struct dm_crtc_state *cur = to_dm_crtc_state(state);
5359 /* TODO Destroy dc_stream objects are stream object is flattened */
5361 dc_stream_release(cur->stream);
5364 __drm_atomic_helper_crtc_destroy_state(state);
5370 static void dm_crtc_reset_state(struct drm_crtc *crtc)
5372 struct dm_crtc_state *state;
5375 dm_crtc_destroy_state(crtc, crtc->state);
5377 state = kzalloc(sizeof(*state), GFP_KERNEL);
5378 if (WARN_ON(!state))
5381 __drm_atomic_helper_crtc_reset(crtc, &state->base);
5384 static struct drm_crtc_state *
5385 dm_crtc_duplicate_state(struct drm_crtc *crtc)
5387 struct dm_crtc_state *state, *cur;
5389 cur = to_dm_crtc_state(crtc->state);
5391 if (WARN_ON(!crtc->state))
5394 state = kzalloc(sizeof(*state), GFP_KERNEL);
5398 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
5401 state->stream = cur->stream;
5402 dc_stream_retain(state->stream);
5405 state->active_planes = cur->active_planes;
5406 state->vrr_infopacket = cur->vrr_infopacket;
5407 state->abm_level = cur->abm_level;
5408 state->vrr_supported = cur->vrr_supported;
5409 state->freesync_config = cur->freesync_config;
5410 state->crc_src = cur->crc_src;
5411 state->cm_has_degamma = cur->cm_has_degamma;
5412 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
5414 /* TODO Duplicate dc_stream after objects are stream object is flattened */
5416 return &state->base;
5419 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
5421 enum dc_irq_source irq_source;
5422 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5423 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
5426 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
5428 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
5430 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
5431 acrtc->crtc_id, enable ? "en" : "dis", rc);
5435 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
5437 enum dc_irq_source irq_source;
5438 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5439 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
5440 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
5441 #if defined(CONFIG_DRM_AMD_DC_DCN)
5442 struct amdgpu_display_manager *dm = &adev->dm;
5443 unsigned long flags;
5448 /* vblank irq on -> Only need vupdate irq in vrr mode */
5449 if (amdgpu_dm_vrr_active(acrtc_state))
5450 rc = dm_set_vupdate_irq(crtc, true);
5452 /* vblank irq off -> vupdate irq off */
5453 rc = dm_set_vupdate_irq(crtc, false);
5459 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
5461 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
5464 if (amdgpu_in_reset(adev))
5467 #if defined(CONFIG_DRM_AMD_DC_DCN)
5468 spin_lock_irqsave(&dm->vblank_lock, flags);
5469 dm->vblank_workqueue->dm = dm;
5470 dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
5471 dm->vblank_workqueue->enable = enable;
5472 spin_unlock_irqrestore(&dm->vblank_lock, flags);
5473 schedule_work(&dm->vblank_workqueue->mall_work);
5479 static int dm_enable_vblank(struct drm_crtc *crtc)
5481 return dm_set_vblank(crtc, true);
5484 static void dm_disable_vblank(struct drm_crtc *crtc)
5486 dm_set_vblank(crtc, false);
5489 /* Implemented only the options currently availible for the driver */
5490 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
5491 .reset = dm_crtc_reset_state,
5492 .destroy = amdgpu_dm_crtc_destroy,
5493 .set_config = drm_atomic_helper_set_config,
5494 .page_flip = drm_atomic_helper_page_flip,
5495 .atomic_duplicate_state = dm_crtc_duplicate_state,
5496 .atomic_destroy_state = dm_crtc_destroy_state,
5497 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
5498 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
5499 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
5500 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
5501 .enable_vblank = dm_enable_vblank,
5502 .disable_vblank = dm_disable_vblank,
5503 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
5506 static enum drm_connector_status
5507 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5510 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5514 * 1. This interface is NOT called in context of HPD irq.
5515 * 2. This interface *is called* in context of user-mode ioctl. Which
5516 * makes it a bad place for *any* MST-related activity.
5519 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5520 !aconnector->fake_enable)
5521 connected = (aconnector->dc_sink != NULL);
5523 connected = (aconnector->base.force == DRM_FORCE_ON);
5525 update_subconnector_property(aconnector);
5527 return (connected ? connector_status_connected :
5528 connector_status_disconnected);
5531 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5532 struct drm_connector_state *connector_state,
5533 struct drm_property *property,
5536 struct drm_device *dev = connector->dev;
5537 struct amdgpu_device *adev = drm_to_adev(dev);
5538 struct dm_connector_state *dm_old_state =
5539 to_dm_connector_state(connector->state);
5540 struct dm_connector_state *dm_new_state =
5541 to_dm_connector_state(connector_state);
5545 if (property == dev->mode_config.scaling_mode_property) {
5546 enum amdgpu_rmx_type rmx_type;
5549 case DRM_MODE_SCALE_CENTER:
5550 rmx_type = RMX_CENTER;
5552 case DRM_MODE_SCALE_ASPECT:
5553 rmx_type = RMX_ASPECT;
5555 case DRM_MODE_SCALE_FULLSCREEN:
5556 rmx_type = RMX_FULL;
5558 case DRM_MODE_SCALE_NONE:
5564 if (dm_old_state->scaling == rmx_type)
5567 dm_new_state->scaling = rmx_type;
5569 } else if (property == adev->mode_info.underscan_hborder_property) {
5570 dm_new_state->underscan_hborder = val;
5572 } else if (property == adev->mode_info.underscan_vborder_property) {
5573 dm_new_state->underscan_vborder = val;
5575 } else if (property == adev->mode_info.underscan_property) {
5576 dm_new_state->underscan_enable = val;
5578 } else if (property == adev->mode_info.abm_level_property) {
5579 dm_new_state->abm_level = val;
5586 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5587 const struct drm_connector_state *state,
5588 struct drm_property *property,
5591 struct drm_device *dev = connector->dev;
5592 struct amdgpu_device *adev = drm_to_adev(dev);
5593 struct dm_connector_state *dm_state =
5594 to_dm_connector_state(state);
5597 if (property == dev->mode_config.scaling_mode_property) {
5598 switch (dm_state->scaling) {
5600 *val = DRM_MODE_SCALE_CENTER;
5603 *val = DRM_MODE_SCALE_ASPECT;
5606 *val = DRM_MODE_SCALE_FULLSCREEN;
5610 *val = DRM_MODE_SCALE_NONE;
5614 } else if (property == adev->mode_info.underscan_hborder_property) {
5615 *val = dm_state->underscan_hborder;
5617 } else if (property == adev->mode_info.underscan_vborder_property) {
5618 *val = dm_state->underscan_vborder;
5620 } else if (property == adev->mode_info.underscan_property) {
5621 *val = dm_state->underscan_enable;
5623 } else if (property == adev->mode_info.abm_level_property) {
5624 *val = dm_state->abm_level;
5631 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5633 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5635 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5638 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5640 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5641 const struct dc_link *link = aconnector->dc_link;
5642 struct amdgpu_device *adev = drm_to_adev(connector->dev);
5643 struct amdgpu_display_manager *dm = &adev->dm;
5646 * Call only if mst_mgr was iniitalized before since it's not done
5647 * for all connector types.
5649 if (aconnector->mst_mgr.dev)
5650 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5652 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5653 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5655 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5656 link->type != dc_connection_none &&
5657 dm->backlight_dev) {
5658 backlight_device_unregister(dm->backlight_dev);
5659 dm->backlight_dev = NULL;
5663 if (aconnector->dc_em_sink)
5664 dc_sink_release(aconnector->dc_em_sink);
5665 aconnector->dc_em_sink = NULL;
5666 if (aconnector->dc_sink)
5667 dc_sink_release(aconnector->dc_sink);
5668 aconnector->dc_sink = NULL;
5670 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
5671 drm_connector_unregister(connector);
5672 drm_connector_cleanup(connector);
5673 if (aconnector->i2c) {
5674 i2c_del_adapter(&aconnector->i2c->base);
5675 kfree(aconnector->i2c);
5677 kfree(aconnector->dm_dp_aux.aux.name);
5682 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
5684 struct dm_connector_state *state =
5685 to_dm_connector_state(connector->state);
5687 if (connector->state)
5688 __drm_atomic_helper_connector_destroy_state(connector->state);
5692 state = kzalloc(sizeof(*state), GFP_KERNEL);
5695 state->scaling = RMX_OFF;
5696 state->underscan_enable = false;
5697 state->underscan_hborder = 0;
5698 state->underscan_vborder = 0;
5699 state->base.max_requested_bpc = 8;
5700 state->vcpi_slots = 0;
5702 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5703 state->abm_level = amdgpu_dm_abm_level;
5705 __drm_atomic_helper_connector_reset(connector, &state->base);
5709 struct drm_connector_state *
5710 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
5712 struct dm_connector_state *state =
5713 to_dm_connector_state(connector->state);
5715 struct dm_connector_state *new_state =
5716 kmemdup(state, sizeof(*state), GFP_KERNEL);
5721 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
5723 new_state->freesync_capable = state->freesync_capable;
5724 new_state->abm_level = state->abm_level;
5725 new_state->scaling = state->scaling;
5726 new_state->underscan_enable = state->underscan_enable;
5727 new_state->underscan_hborder = state->underscan_hborder;
5728 new_state->underscan_vborder = state->underscan_vborder;
5729 new_state->vcpi_slots = state->vcpi_slots;
5730 new_state->pbn = state->pbn;
5731 return &new_state->base;
5735 amdgpu_dm_connector_late_register(struct drm_connector *connector)
5737 struct amdgpu_dm_connector *amdgpu_dm_connector =
5738 to_amdgpu_dm_connector(connector);
5741 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
5742 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
5743 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
5744 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
5749 #if defined(CONFIG_DEBUG_FS)
5750 connector_debugfs_init(amdgpu_dm_connector);
5756 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
5757 .reset = amdgpu_dm_connector_funcs_reset,
5758 .detect = amdgpu_dm_connector_detect,
5759 .fill_modes = drm_helper_probe_single_connector_modes,
5760 .destroy = amdgpu_dm_connector_destroy,
5761 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
5762 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5763 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
5764 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
5765 .late_register = amdgpu_dm_connector_late_register,
5766 .early_unregister = amdgpu_dm_connector_unregister
5769 static int get_modes(struct drm_connector *connector)
5771 return amdgpu_dm_connector_get_modes(connector);
5774 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
5776 struct dc_sink_init_data init_params = {
5777 .link = aconnector->dc_link,
5778 .sink_signal = SIGNAL_TYPE_VIRTUAL
5782 if (!aconnector->base.edid_blob_ptr) {
5783 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
5784 aconnector->base.name);
5786 aconnector->base.force = DRM_FORCE_OFF;
5787 aconnector->base.override_edid = false;
5791 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
5793 aconnector->edid = edid;
5795 aconnector->dc_em_sink = dc_link_add_remote_sink(
5796 aconnector->dc_link,
5798 (edid->extensions + 1) * EDID_LENGTH,
5801 if (aconnector->base.force == DRM_FORCE_ON) {
5802 aconnector->dc_sink = aconnector->dc_link->local_sink ?
5803 aconnector->dc_link->local_sink :
5804 aconnector->dc_em_sink;
5805 dc_sink_retain(aconnector->dc_sink);
5809 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
5811 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
5814 * In case of headless boot with force on for DP managed connector
5815 * Those settings have to be != 0 to get initial modeset
5817 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5818 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
5819 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
5823 aconnector->base.override_edid = true;
5824 create_eml_sink(aconnector);
5827 static struct dc_stream_state *
5828 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5829 const struct drm_display_mode *drm_mode,
5830 const struct dm_connector_state *dm_state,
5831 const struct dc_stream_state *old_stream)
5833 struct drm_connector *connector = &aconnector->base;
5834 struct amdgpu_device *adev = drm_to_adev(connector->dev);
5835 struct dc_stream_state *stream;
5836 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
5837 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
5838 enum dc_status dc_result = DC_OK;
5841 stream = create_stream_for_sink(aconnector, drm_mode,
5842 dm_state, old_stream,
5844 if (stream == NULL) {
5845 DRM_ERROR("Failed to create stream for sink!\n");
5849 dc_result = dc_validate_stream(adev->dm.dc, stream);
5851 if (dc_result != DC_OK) {
5852 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
5857 dc_status_to_str(dc_result));
5859 dc_stream_release(stream);
5861 requested_bpc -= 2; /* lower bpc to retry validation */
5864 } while (stream == NULL && requested_bpc >= 6);
5869 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
5870 struct drm_display_mode *mode)
5872 int result = MODE_ERROR;
5873 struct dc_sink *dc_sink;
5874 /* TODO: Unhardcode stream count */
5875 struct dc_stream_state *stream;
5876 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5878 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
5879 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
5883 * Only run this the first time mode_valid is called to initilialize
5886 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
5887 !aconnector->dc_em_sink)
5888 handle_edid_mgmt(aconnector);
5890 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
5892 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
5893 aconnector->base.force != DRM_FORCE_ON) {
5894 DRM_ERROR("dc_sink is NULL!\n");
5898 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
5900 dc_stream_release(stream);
5905 /* TODO: error handling*/
5909 static int fill_hdr_info_packet(const struct drm_connector_state *state,
5910 struct dc_info_packet *out)
5912 struct hdmi_drm_infoframe frame;
5913 unsigned char buf[30]; /* 26 + 4 */
5917 memset(out, 0, sizeof(*out));
5919 if (!state->hdr_output_metadata)
5922 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
5926 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
5930 /* Static metadata is a fixed 26 bytes + 4 byte header. */
5934 /* Prepare the infopacket for DC. */
5935 switch (state->connector->connector_type) {
5936 case DRM_MODE_CONNECTOR_HDMIA:
5937 out->hb0 = 0x87; /* type */
5938 out->hb1 = 0x01; /* version */
5939 out->hb2 = 0x1A; /* length */
5940 out->sb[0] = buf[3]; /* checksum */
5944 case DRM_MODE_CONNECTOR_DisplayPort:
5945 case DRM_MODE_CONNECTOR_eDP:
5946 out->hb0 = 0x00; /* sdp id, zero */
5947 out->hb1 = 0x87; /* type */
5948 out->hb2 = 0x1D; /* payload len - 1 */
5949 out->hb3 = (0x13 << 2); /* sdp version */
5950 out->sb[0] = 0x01; /* version */
5951 out->sb[1] = 0x1A; /* length */
5959 memcpy(&out->sb[i], &buf[4], 26);
5962 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
5963 sizeof(out->sb), false);
5969 is_hdr_metadata_different(const struct drm_connector_state *old_state,
5970 const struct drm_connector_state *new_state)
5972 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
5973 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
5975 if (old_blob != new_blob) {
5976 if (old_blob && new_blob &&
5977 old_blob->length == new_blob->length)
5978 return memcmp(old_blob->data, new_blob->data,
5988 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
5989 struct drm_atomic_state *state)
5991 struct drm_connector_state *new_con_state =
5992 drm_atomic_get_new_connector_state(state, conn);
5993 struct drm_connector_state *old_con_state =
5994 drm_atomic_get_old_connector_state(state, conn);
5995 struct drm_crtc *crtc = new_con_state->crtc;
5996 struct drm_crtc_state *new_crtc_state;
5999 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6004 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
6005 struct dc_info_packet hdr_infopacket;
6007 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6011 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6012 if (IS_ERR(new_crtc_state))
6013 return PTR_ERR(new_crtc_state);
6016 * DC considers the stream backends changed if the
6017 * static metadata changes. Forcing the modeset also
6018 * gives a simple way for userspace to switch from
6019 * 8bpc to 10bpc when setting the metadata to enter
6022 * Changing the static metadata after it's been
6023 * set is permissible, however. So only force a
6024 * modeset if we're entering or exiting HDR.
6026 new_crtc_state->mode_changed =
6027 !old_con_state->hdr_output_metadata ||
6028 !new_con_state->hdr_output_metadata;
6034 static const struct drm_connector_helper_funcs
6035 amdgpu_dm_connector_helper_funcs = {
6037 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6038 * modes will be filtered by drm_mode_validate_size(), and those modes
6039 * are missing after user start lightdm. So we need to renew modes list.
6040 * in get_modes call back, not just return the modes count
6042 .get_modes = get_modes,
6043 .mode_valid = amdgpu_dm_connector_mode_valid,
6044 .atomic_check = amdgpu_dm_connector_atomic_check,
6047 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
6051 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
6053 struct drm_atomic_state *state = new_crtc_state->state;
6054 struct drm_plane *plane;
6057 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
6058 struct drm_plane_state *new_plane_state;
6060 /* Cursor planes are "fake". */
6061 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6064 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
6066 if (!new_plane_state) {
6068 * The plane is enable on the CRTC and hasn't changed
6069 * state. This means that it previously passed
6070 * validation and is therefore enabled.
6076 /* We need a framebuffer to be considered enabled. */
6077 num_active += (new_plane_state->fb != NULL);
6083 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
6084 struct drm_crtc_state *new_crtc_state)
6086 struct dm_crtc_state *dm_new_crtc_state =
6087 to_dm_crtc_state(new_crtc_state);
6089 dm_new_crtc_state->active_planes = 0;
6091 if (!dm_new_crtc_state->stream)
6094 dm_new_crtc_state->active_planes =
6095 count_crtc_active_planes(new_crtc_state);
6098 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
6099 struct drm_atomic_state *state)
6101 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
6103 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
6104 struct dc *dc = adev->dm.dc;
6105 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
6108 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
6110 dm_update_crtc_active_planes(crtc, crtc_state);
6112 if (unlikely(!dm_crtc_state->stream &&
6113 modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {
6119 * We require the primary plane to be enabled whenever the CRTC is, otherwise
6120 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
6121 * planes are disabled, which is not supported by the hardware. And there is legacy
6122 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
6124 if (crtc_state->enable &&
6125 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
6126 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
6130 /* In some use cases, like reset, no stream is attached */
6131 if (!dm_crtc_state->stream)
6134 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
6137 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
6141 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
6142 const struct drm_display_mode *mode,
6143 struct drm_display_mode *adjusted_mode)
6148 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
6149 .disable = dm_crtc_helper_disable,
6150 .atomic_check = dm_crtc_helper_atomic_check,
6151 .mode_fixup = dm_crtc_helper_mode_fixup,
6152 .get_scanout_position = amdgpu_crtc_get_scanout_position,
6155 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6160 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
6162 switch (display_color_depth) {
6163 case COLOR_DEPTH_666:
6165 case COLOR_DEPTH_888:
6167 case COLOR_DEPTH_101010:
6169 case COLOR_DEPTH_121212:
6171 case COLOR_DEPTH_141414:
6173 case COLOR_DEPTH_161616:
6181 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6182 struct drm_crtc_state *crtc_state,
6183 struct drm_connector_state *conn_state)
6185 struct drm_atomic_state *state = crtc_state->state;
6186 struct drm_connector *connector = conn_state->connector;
6187 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6188 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6189 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6190 struct drm_dp_mst_topology_mgr *mst_mgr;
6191 struct drm_dp_mst_port *mst_port;
6192 enum dc_color_depth color_depth;
6194 bool is_y420 = false;
6196 if (!aconnector->port || !aconnector->dc_sink)
6199 mst_port = aconnector->port;
6200 mst_mgr = &aconnector->mst_port->mst_mgr;
6202 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6205 if (!state->duplicated) {
6206 int max_bpc = conn_state->max_requested_bpc;
6207 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6208 aconnector->force_yuv420_output;
6209 color_depth = convert_color_depth_from_display_info(connector,
6212 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6213 clock = adjusted_mode->clock;
6214 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6216 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
6219 dm_new_connector_state->pbn,
6220 dm_mst_get_pbn_divider(aconnector->dc_link));
6221 if (dm_new_connector_state->vcpi_slots < 0) {
6222 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6223 return dm_new_connector_state->vcpi_slots;
6228 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6229 .disable = dm_encoder_helper_disable,
6230 .atomic_check = dm_encoder_helper_atomic_check
6233 #if defined(CONFIG_DRM_AMD_DC_DCN)
6234 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6235 struct dc_state *dc_state)
6237 struct dc_stream_state *stream = NULL;
6238 struct drm_connector *connector;
6239 struct drm_connector_state *new_con_state, *old_con_state;
6240 struct amdgpu_dm_connector *aconnector;
6241 struct dm_connector_state *dm_conn_state;
6242 int i, j, clock, bpp;
6243 int vcpi, pbn_div, pbn = 0;
6245 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6247 aconnector = to_amdgpu_dm_connector(connector);
6249 if (!aconnector->port)
6252 if (!new_con_state || !new_con_state->crtc)
6255 dm_conn_state = to_dm_connector_state(new_con_state);
6257 for (j = 0; j < dc_state->stream_count; j++) {
6258 stream = dc_state->streams[j];
6262 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
6271 if (stream->timing.flags.DSC != 1) {
6272 drm_dp_mst_atomic_enable_dsc(state,
6280 pbn_div = dm_mst_get_pbn_divider(stream->link);
6281 bpp = stream->timing.dsc_cfg.bits_per_pixel;
6282 clock = stream->timing.pix_clk_100hz / 10;
6283 pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
6284 vcpi = drm_dp_mst_atomic_enable_dsc(state,
6291 dm_conn_state->pbn = pbn;
6292 dm_conn_state->vcpi_slots = vcpi;
6298 static void dm_drm_plane_reset(struct drm_plane *plane)
6300 struct dm_plane_state *amdgpu_state = NULL;
6303 plane->funcs->atomic_destroy_state(plane, plane->state);
6305 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
6306 WARN_ON(amdgpu_state == NULL);
6309 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
6312 static struct drm_plane_state *
6313 dm_drm_plane_duplicate_state(struct drm_plane *plane)
6315 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
6317 old_dm_plane_state = to_dm_plane_state(plane->state);
6318 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
6319 if (!dm_plane_state)
6322 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
6324 if (old_dm_plane_state->dc_state) {
6325 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
6326 dc_plane_state_retain(dm_plane_state->dc_state);
6329 return &dm_plane_state->base;
6332 static void dm_drm_plane_destroy_state(struct drm_plane *plane,
6333 struct drm_plane_state *state)
6335 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
6337 if (dm_plane_state->dc_state)
6338 dc_plane_state_release(dm_plane_state->dc_state);
6340 drm_atomic_helper_plane_destroy_state(plane, state);
6343 static const struct drm_plane_funcs dm_plane_funcs = {
6344 .update_plane = drm_atomic_helper_update_plane,
6345 .disable_plane = drm_atomic_helper_disable_plane,
6346 .destroy = drm_primary_helper_destroy,
6347 .reset = dm_drm_plane_reset,
6348 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
6349 .atomic_destroy_state = dm_drm_plane_destroy_state,
6350 .format_mod_supported = dm_plane_format_mod_supported,
6353 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
6354 struct drm_plane_state *new_state)
6356 struct amdgpu_framebuffer *afb;
6357 struct drm_gem_object *obj;
6358 struct amdgpu_device *adev;
6359 struct amdgpu_bo *rbo;
6360 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
6361 struct list_head list;
6362 struct ttm_validate_buffer tv;
6363 struct ww_acquire_ctx ticket;
6367 if (!new_state->fb) {
6368 DRM_DEBUG_DRIVER("No FB bound\n");
6372 afb = to_amdgpu_framebuffer(new_state->fb);
6373 obj = new_state->fb->obj[0];
6374 rbo = gem_to_amdgpu_bo(obj);
6375 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
6376 INIT_LIST_HEAD(&list);
6380 list_add(&tv.head, &list);
6382 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
6384 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
6388 if (plane->type != DRM_PLANE_TYPE_CURSOR)
6389 domain = amdgpu_display_supported_domains(adev, rbo->flags);
6391 domain = AMDGPU_GEM_DOMAIN_VRAM;
6393 r = amdgpu_bo_pin(rbo, domain);
6394 if (unlikely(r != 0)) {
6395 if (r != -ERESTARTSYS)
6396 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
6397 ttm_eu_backoff_reservation(&ticket, &list);
6401 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
6402 if (unlikely(r != 0)) {
6403 amdgpu_bo_unpin(rbo);
6404 ttm_eu_backoff_reservation(&ticket, &list);
6405 DRM_ERROR("%p bind failed\n", rbo);
6409 ttm_eu_backoff_reservation(&ticket, &list);
6411 afb->address = amdgpu_bo_gpu_offset(rbo);
6416 * We don't do surface updates on planes that have been newly created,
6417 * but we also don't have the afb->address during atomic check.
6419 * Fill in buffer attributes depending on the address here, but only on
6420 * newly created planes since they're not being used by DC yet and this
6421 * won't modify global state.
6423 dm_plane_state_old = to_dm_plane_state(plane->state);
6424 dm_plane_state_new = to_dm_plane_state(new_state);
6426 if (dm_plane_state_new->dc_state &&
6427 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
6428 struct dc_plane_state *plane_state =
6429 dm_plane_state_new->dc_state;
6430 bool force_disable_dcc = !plane_state->dcc.enable;
6432 fill_plane_buffer_attributes(
6433 adev, afb, plane_state->format, plane_state->rotation,
6435 &plane_state->tiling_info, &plane_state->plane_size,
6436 &plane_state->dcc, &plane_state->address,
6437 afb->tmz_surface, force_disable_dcc);
6443 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
6444 struct drm_plane_state *old_state)
6446 struct amdgpu_bo *rbo;
6452 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
6453 r = amdgpu_bo_reserve(rbo, false);
6455 DRM_ERROR("failed to reserve rbo before unpin\n");
6459 amdgpu_bo_unpin(rbo);
6460 amdgpu_bo_unreserve(rbo);
6461 amdgpu_bo_unref(&rbo);
6464 static int dm_plane_helper_check_state(struct drm_plane_state *state,
6465 struct drm_crtc_state *new_crtc_state)
6467 struct drm_framebuffer *fb = state->fb;
6468 int min_downscale, max_upscale;
6470 int max_scale = INT_MAX;
6472 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */
6473 if (fb && state->crtc) {
6474 /* Validate viewport to cover the case when only the position changes */
6475 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {
6476 int viewport_width = state->crtc_w;
6477 int viewport_height = state->crtc_h;
6479 if (state->crtc_x < 0)
6480 viewport_width += state->crtc_x;
6481 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay)
6482 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x;
6484 if (state->crtc_y < 0)
6485 viewport_height += state->crtc_y;
6486 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay)
6487 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
6489 /* If completely outside of screen, viewport_width and/or viewport_height will be negative,
6490 * which is still OK to satisfy the condition below, thereby also covering these cases
6491 * (when plane is completely outside of screen).
6492 * x2 for width is because of pipe-split.
6494 if (viewport_width < MIN_VIEWPORT_SIZE*2 || viewport_height < MIN_VIEWPORT_SIZE)
6498 /* Get min/max allowed scaling factors from plane caps. */
6499 get_min_max_dc_plane_scaling(state->crtc->dev, fb,
6500 &min_downscale, &max_upscale);
6502 * Convert to drm convention: 16.16 fixed point, instead of dc's
6503 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's
6504 * dst/src, so min_scale = 1.0 / max_upscale, etc.
6506 min_scale = (1000 << 16) / max_upscale;
6507 max_scale = (1000 << 16) / min_downscale;
6510 return drm_atomic_helper_check_plane_state(
6511 state, new_crtc_state, min_scale, max_scale, true, true);
6514 static int dm_plane_atomic_check(struct drm_plane *plane,
6515 struct drm_plane_state *state)
6517 struct amdgpu_device *adev = drm_to_adev(plane->dev);
6518 struct dc *dc = adev->dm.dc;
6519 struct dm_plane_state *dm_plane_state;
6520 struct dc_scaling_info scaling_info;
6521 struct drm_crtc_state *new_crtc_state;
6524 trace_amdgpu_dm_plane_atomic_check(state);
6526 dm_plane_state = to_dm_plane_state(state);
6528 if (!dm_plane_state->dc_state)
6532 drm_atomic_get_new_crtc_state(state->state, state->crtc);
6533 if (!new_crtc_state)
6536 ret = dm_plane_helper_check_state(state, new_crtc_state);
6540 ret = fill_dc_scaling_info(state, &scaling_info);
6544 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
6550 static int dm_plane_atomic_async_check(struct drm_plane *plane,
6551 struct drm_plane_state *new_plane_state)
6553 /* Only support async updates on cursor planes. */
6554 if (plane->type != DRM_PLANE_TYPE_CURSOR)
6560 static void dm_plane_atomic_async_update(struct drm_plane *plane,
6561 struct drm_plane_state *new_state)
6563 struct drm_plane_state *old_state =
6564 drm_atomic_get_old_plane_state(new_state->state, plane);
6566 trace_amdgpu_dm_atomic_update_cursor(new_state);
6568 swap(plane->state->fb, new_state->fb);
6570 plane->state->src_x = new_state->src_x;
6571 plane->state->src_y = new_state->src_y;
6572 plane->state->src_w = new_state->src_w;
6573 plane->state->src_h = new_state->src_h;
6574 plane->state->crtc_x = new_state->crtc_x;
6575 plane->state->crtc_y = new_state->crtc_y;
6576 plane->state->crtc_w = new_state->crtc_w;
6577 plane->state->crtc_h = new_state->crtc_h;
6579 handle_cursor_update(plane, old_state);
6582 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
6583 .prepare_fb = dm_plane_helper_prepare_fb,
6584 .cleanup_fb = dm_plane_helper_cleanup_fb,
6585 .atomic_check = dm_plane_atomic_check,
6586 .atomic_async_check = dm_plane_atomic_async_check,
6587 .atomic_async_update = dm_plane_atomic_async_update
6591 * TODO: these are currently initialized to rgb formats only.
6592 * For future use cases we should either initialize them dynamically based on
6593 * plane capabilities, or initialize this array to all formats, so internal drm
6594 * check will succeed, and let DC implement proper check
6596 static const uint32_t rgb_formats[] = {
6597 DRM_FORMAT_XRGB8888,
6598 DRM_FORMAT_ARGB8888,
6599 DRM_FORMAT_RGBA8888,
6600 DRM_FORMAT_XRGB2101010,
6601 DRM_FORMAT_XBGR2101010,
6602 DRM_FORMAT_ARGB2101010,
6603 DRM_FORMAT_ABGR2101010,
6604 DRM_FORMAT_XBGR8888,
6605 DRM_FORMAT_ABGR8888,
6609 static const uint32_t overlay_formats[] = {
6610 DRM_FORMAT_XRGB8888,
6611 DRM_FORMAT_ARGB8888,
6612 DRM_FORMAT_RGBA8888,
6613 DRM_FORMAT_XBGR8888,
6614 DRM_FORMAT_ABGR8888,
6618 static const u32 cursor_formats[] = {
6622 static int get_plane_formats(const struct drm_plane *plane,
6623 const struct dc_plane_cap *plane_cap,
6624 uint32_t *formats, int max_formats)
6626 int i, num_formats = 0;
6629 * TODO: Query support for each group of formats directly from
6630 * DC plane caps. This will require adding more formats to the
6634 switch (plane->type) {
6635 case DRM_PLANE_TYPE_PRIMARY:
6636 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
6637 if (num_formats >= max_formats)
6640 formats[num_formats++] = rgb_formats[i];
6643 if (plane_cap && plane_cap->pixel_format_support.nv12)
6644 formats[num_formats++] = DRM_FORMAT_NV12;
6645 if (plane_cap && plane_cap->pixel_format_support.p010)
6646 formats[num_formats++] = DRM_FORMAT_P010;
6647 if (plane_cap && plane_cap->pixel_format_support.fp16) {
6648 formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
6649 formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
6650 formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
6651 formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
6655 case DRM_PLANE_TYPE_OVERLAY:
6656 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
6657 if (num_formats >= max_formats)
6660 formats[num_formats++] = overlay_formats[i];
6664 case DRM_PLANE_TYPE_CURSOR:
6665 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
6666 if (num_formats >= max_formats)
6669 formats[num_formats++] = cursor_formats[i];
6677 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
6678 struct drm_plane *plane,
6679 unsigned long possible_crtcs,
6680 const struct dc_plane_cap *plane_cap)
6682 uint32_t formats[32];
6685 unsigned int supported_rotations;
6686 uint64_t *modifiers = NULL;
6688 num_formats = get_plane_formats(plane, plane_cap, formats,
6689 ARRAY_SIZE(formats));
6691 res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
6695 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
6696 &dm_plane_funcs, formats, num_formats,
6697 modifiers, plane->type, NULL);
6702 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
6703 plane_cap && plane_cap->per_pixel_alpha) {
6704 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
6705 BIT(DRM_MODE_BLEND_PREMULTI);
6707 drm_plane_create_alpha_property(plane);
6708 drm_plane_create_blend_mode_property(plane, blend_caps);
6711 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
6713 (plane_cap->pixel_format_support.nv12 ||
6714 plane_cap->pixel_format_support.p010)) {
6715 /* This only affects YUV formats. */
6716 drm_plane_create_color_properties(
6718 BIT(DRM_COLOR_YCBCR_BT601) |
6719 BIT(DRM_COLOR_YCBCR_BT709) |
6720 BIT(DRM_COLOR_YCBCR_BT2020),
6721 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
6722 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
6723 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
6726 supported_rotations =
6727 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
6728 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
6730 if (dm->adev->asic_type >= CHIP_BONAIRE &&
6731 plane->type != DRM_PLANE_TYPE_CURSOR)
6732 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
6733 supported_rotations);
6735 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
6737 /* Create (reset) the plane state */
6738 if (plane->funcs->reset)
6739 plane->funcs->reset(plane);
6744 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
6745 struct drm_plane *plane,
6746 uint32_t crtc_index)
6748 struct amdgpu_crtc *acrtc = NULL;
6749 struct drm_plane *cursor_plane;
6753 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
6757 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
6758 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
6760 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
6764 res = drm_crtc_init_with_planes(
6769 &amdgpu_dm_crtc_funcs, NULL);
6774 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
6776 /* Create (reset) the plane state */
6777 if (acrtc->base.funcs->reset)
6778 acrtc->base.funcs->reset(&acrtc->base);
6780 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
6781 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
6783 acrtc->crtc_id = crtc_index;
6784 acrtc->base.enabled = false;
6785 acrtc->otg_inst = -1;
6787 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
6788 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
6789 true, MAX_COLOR_LUT_ENTRIES);
6790 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
6796 kfree(cursor_plane);
6801 static int to_drm_connector_type(enum signal_type st)
6804 case SIGNAL_TYPE_HDMI_TYPE_A:
6805 return DRM_MODE_CONNECTOR_HDMIA;
6806 case SIGNAL_TYPE_EDP:
6807 return DRM_MODE_CONNECTOR_eDP;
6808 case SIGNAL_TYPE_LVDS:
6809 return DRM_MODE_CONNECTOR_LVDS;
6810 case SIGNAL_TYPE_RGB:
6811 return DRM_MODE_CONNECTOR_VGA;
6812 case SIGNAL_TYPE_DISPLAY_PORT:
6813 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6814 return DRM_MODE_CONNECTOR_DisplayPort;
6815 case SIGNAL_TYPE_DVI_DUAL_LINK:
6816 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6817 return DRM_MODE_CONNECTOR_DVID;
6818 case SIGNAL_TYPE_VIRTUAL:
6819 return DRM_MODE_CONNECTOR_VIRTUAL;
6822 return DRM_MODE_CONNECTOR_Unknown;
6826 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6828 struct drm_encoder *encoder;
6830 /* There is only one encoder per connector */
6831 drm_connector_for_each_possible_encoder(connector, encoder)
6837 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6839 struct drm_encoder *encoder;
6840 struct amdgpu_encoder *amdgpu_encoder;
6842 encoder = amdgpu_dm_connector_to_encoder(connector);
6844 if (encoder == NULL)
6847 amdgpu_encoder = to_amdgpu_encoder(encoder);
6849 amdgpu_encoder->native_mode.clock = 0;
6851 if (!list_empty(&connector->probed_modes)) {
6852 struct drm_display_mode *preferred_mode = NULL;
6854 list_for_each_entry(preferred_mode,
6855 &connector->probed_modes,
6857 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6858 amdgpu_encoder->native_mode = *preferred_mode;
6866 static struct drm_display_mode *
6867 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6869 int hdisplay, int vdisplay)
6871 struct drm_device *dev = encoder->dev;
6872 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6873 struct drm_display_mode *mode = NULL;
6874 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6876 mode = drm_mode_duplicate(dev, native_mode);
6881 mode->hdisplay = hdisplay;
6882 mode->vdisplay = vdisplay;
6883 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6884 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6890 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6891 struct drm_connector *connector)
6893 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6894 struct drm_display_mode *mode = NULL;
6895 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6896 struct amdgpu_dm_connector *amdgpu_dm_connector =
6897 to_amdgpu_dm_connector(connector);
6901 char name[DRM_DISPLAY_MODE_LEN];
6904 } common_modes[] = {
6905 { "640x480", 640, 480},
6906 { "800x600", 800, 600},
6907 { "1024x768", 1024, 768},
6908 { "1280x720", 1280, 720},
6909 { "1280x800", 1280, 800},
6910 {"1280x1024", 1280, 1024},
6911 { "1440x900", 1440, 900},
6912 {"1680x1050", 1680, 1050},
6913 {"1600x1200", 1600, 1200},
6914 {"1920x1080", 1920, 1080},
6915 {"1920x1200", 1920, 1200}
6918 n = ARRAY_SIZE(common_modes);
6920 for (i = 0; i < n; i++) {
6921 struct drm_display_mode *curmode = NULL;
6922 bool mode_existed = false;
6924 if (common_modes[i].w > native_mode->hdisplay ||
6925 common_modes[i].h > native_mode->vdisplay ||
6926 (common_modes[i].w == native_mode->hdisplay &&
6927 common_modes[i].h == native_mode->vdisplay))
6930 list_for_each_entry(curmode, &connector->probed_modes, head) {
6931 if (common_modes[i].w == curmode->hdisplay &&
6932 common_modes[i].h == curmode->vdisplay) {
6933 mode_existed = true;
6941 mode = amdgpu_dm_create_common_mode(encoder,
6942 common_modes[i].name, common_modes[i].w,
6944 drm_mode_probed_add(connector, mode);
6945 amdgpu_dm_connector->num_modes++;
6949 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6952 struct amdgpu_dm_connector *amdgpu_dm_connector =
6953 to_amdgpu_dm_connector(connector);
6956 /* empty probed_modes */
6957 INIT_LIST_HEAD(&connector->probed_modes);
6958 amdgpu_dm_connector->num_modes =
6959 drm_add_edid_modes(connector, edid);
6961 /* sorting the probed modes before calling function
6962 * amdgpu_dm_get_native_mode() since EDID can have
6963 * more than one preferred mode. The modes that are
6964 * later in the probed mode list could be of higher
6965 * and preferred resolution. For example, 3840x2160
6966 * resolution in base EDID preferred timing and 4096x2160
6967 * preferred resolution in DID extension block later.
6969 drm_mode_sort(&connector->probed_modes);
6970 amdgpu_dm_get_native_mode(connector);
6972 amdgpu_dm_connector->num_modes = 0;
6976 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6978 struct amdgpu_dm_connector *amdgpu_dm_connector =
6979 to_amdgpu_dm_connector(connector);
6980 struct drm_encoder *encoder;
6981 struct edid *edid = amdgpu_dm_connector->edid;
6983 encoder = amdgpu_dm_connector_to_encoder(connector);
6985 if (!drm_edid_is_valid(edid)) {
6986 amdgpu_dm_connector->num_modes =
6987 drm_add_modes_noedid(connector, 640, 480);
6989 amdgpu_dm_connector_ddc_get_modes(connector, edid);
6990 amdgpu_dm_connector_add_common_modes(encoder, connector);
6992 amdgpu_dm_fbc_init(connector);
6994 return amdgpu_dm_connector->num_modes;
6997 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
6998 struct amdgpu_dm_connector *aconnector,
7000 struct dc_link *link,
7003 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7006 * Some of the properties below require access to state, like bpc.
7007 * Allocate some default initial connector state with our reset helper.
7009 if (aconnector->base.funcs->reset)
7010 aconnector->base.funcs->reset(&aconnector->base);
7012 aconnector->connector_id = link_index;
7013 aconnector->dc_link = link;
7014 aconnector->base.interlace_allowed = false;
7015 aconnector->base.doublescan_allowed = false;
7016 aconnector->base.stereo_allowed = false;
7017 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7018 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7019 aconnector->audio_inst = -1;
7020 mutex_init(&aconnector->hpd_lock);
7023 * configure support HPD hot plug connector_>polled default value is 0
7024 * which means HPD hot plug not supported
7026 switch (connector_type) {
7027 case DRM_MODE_CONNECTOR_HDMIA:
7028 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7029 aconnector->base.ycbcr_420_allowed =
7030 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7032 case DRM_MODE_CONNECTOR_DisplayPort:
7033 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7034 aconnector->base.ycbcr_420_allowed =
7035 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7037 case DRM_MODE_CONNECTOR_DVID:
7038 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7044 drm_object_attach_property(&aconnector->base.base,
7045 dm->ddev->mode_config.scaling_mode_property,
7046 DRM_MODE_SCALE_NONE);
7048 drm_object_attach_property(&aconnector->base.base,
7049 adev->mode_info.underscan_property,
7051 drm_object_attach_property(&aconnector->base.base,
7052 adev->mode_info.underscan_hborder_property,
7054 drm_object_attach_property(&aconnector->base.base,
7055 adev->mode_info.underscan_vborder_property,
7058 if (!aconnector->mst_port)
7059 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7061 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7062 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7063 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7065 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7066 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7067 drm_object_attach_property(&aconnector->base.base,
7068 adev->mode_info.abm_level_property, 0);
7071 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7072 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7073 connector_type == DRM_MODE_CONNECTOR_eDP) {
7074 drm_object_attach_property(
7075 &aconnector->base.base,
7076 dm->ddev->mode_config.hdr_output_metadata_property, 0);
7078 if (!aconnector->mst_port)
7079 drm_connector_attach_vrr_capable_property(&aconnector->base);
7081 #ifdef CONFIG_DRM_AMD_DC_HDCP
7082 if (adev->dm.hdcp_workqueue)
7083 drm_connector_attach_content_protection_property(&aconnector->base, true);
7088 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7089 struct i2c_msg *msgs, int num)
7091 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7092 struct ddc_service *ddc_service = i2c->ddc_service;
7093 struct i2c_command cmd;
7097 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7102 cmd.number_of_payloads = num;
7103 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7106 for (i = 0; i < num; i++) {
7107 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7108 cmd.payloads[i].address = msgs[i].addr;
7109 cmd.payloads[i].length = msgs[i].len;
7110 cmd.payloads[i].data = msgs[i].buf;
7114 ddc_service->ctx->dc,
7115 ddc_service->ddc_pin->hw_info.ddc_channel,
7119 kfree(cmd.payloads);
7123 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7125 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7128 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7129 .master_xfer = amdgpu_dm_i2c_xfer,
7130 .functionality = amdgpu_dm_i2c_func,
7133 static struct amdgpu_i2c_adapter *
7134 create_i2c(struct ddc_service *ddc_service,
7138 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7139 struct amdgpu_i2c_adapter *i2c;
7141 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7144 i2c->base.owner = THIS_MODULE;
7145 i2c->base.class = I2C_CLASS_DDC;
7146 i2c->base.dev.parent = &adev->pdev->dev;
7147 i2c->base.algo = &amdgpu_dm_i2c_algo;
7148 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7149 i2c_set_adapdata(&i2c->base, i2c);
7150 i2c->ddc_service = ddc_service;
7151 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
7158 * Note: this function assumes that dc_link_detect() was called for the
7159 * dc_link which will be represented by this aconnector.
7161 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7162 struct amdgpu_dm_connector *aconnector,
7163 uint32_t link_index,
7164 struct amdgpu_encoder *aencoder)
7168 struct dc *dc = dm->dc;
7169 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7170 struct amdgpu_i2c_adapter *i2c;
7172 link->priv = aconnector;
7174 DRM_DEBUG_DRIVER("%s()\n", __func__);
7176 i2c = create_i2c(link->ddc, link->link_index, &res);
7178 DRM_ERROR("Failed to create i2c adapter data\n");
7182 aconnector->i2c = i2c;
7183 res = i2c_add_adapter(&i2c->base);
7186 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7190 connector_type = to_drm_connector_type(link->connector_signal);
7192 res = drm_connector_init_with_ddc(
7195 &amdgpu_dm_connector_funcs,
7200 DRM_ERROR("connector_init failed\n");
7201 aconnector->connector_id = -1;
7205 drm_connector_helper_add(
7207 &amdgpu_dm_connector_helper_funcs);
7209 amdgpu_dm_connector_init_helper(
7216 drm_connector_attach_encoder(
7217 &aconnector->base, &aencoder->base);
7219 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7220 || connector_type == DRM_MODE_CONNECTOR_eDP)
7221 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7226 aconnector->i2c = NULL;
7231 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7233 switch (adev->mode_info.num_crtc) {
7250 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7251 struct amdgpu_encoder *aencoder,
7252 uint32_t link_index)
7254 struct amdgpu_device *adev = drm_to_adev(dev);
7256 int res = drm_encoder_init(dev,
7258 &amdgpu_dm_encoder_funcs,
7259 DRM_MODE_ENCODER_TMDS,
7262 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7265 aencoder->encoder_id = link_index;
7267 aencoder->encoder_id = -1;
7269 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7274 static void manage_dm_interrupts(struct amdgpu_device *adev,
7275 struct amdgpu_crtc *acrtc,
7279 * We have no guarantee that the frontend index maps to the same
7280 * backend index - some even map to more than one.
7282 * TODO: Use a different interrupt or check DC itself for the mapping.
7285 amdgpu_display_crtc_idx_to_irq_type(
7290 drm_crtc_vblank_on(&acrtc->base);
7293 &adev->pageflip_irq,
7299 &adev->pageflip_irq,
7301 drm_crtc_vblank_off(&acrtc->base);
7305 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7306 struct amdgpu_crtc *acrtc)
7309 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7312 * This reads the current state for the IRQ and force reapplies
7313 * the setting to hardware.
7315 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7319 is_scaling_state_different(const struct dm_connector_state *dm_state,
7320 const struct dm_connector_state *old_dm_state)
7322 if (dm_state->scaling != old_dm_state->scaling)
7324 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7325 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7327 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7328 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7330 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7331 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7336 #ifdef CONFIG_DRM_AMD_DC_HDCP
7337 static bool is_content_protection_different(struct drm_connector_state *state,
7338 const struct drm_connector_state *old_state,
7339 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7341 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7342 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7344 /* Handle: Type0/1 change */
7345 if (old_state->hdcp_content_type != state->hdcp_content_type &&
7346 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7347 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7351 /* CP is being re enabled, ignore this
7353 * Handles: ENABLED -> DESIRED
7355 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7356 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7357 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7361 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7363 * Handles: UNDESIRED -> ENABLED
7365 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7366 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7367 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7369 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
7370 * hot-plug, headless s3, dpms
7372 * Handles: DESIRED -> DESIRED (Special case)
7374 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7375 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7376 dm_con_state->update_hdcp = false;
7381 * Handles: UNDESIRED -> UNDESIRED
7382 * DESIRED -> DESIRED
7383 * ENABLED -> ENABLED
7385 if (old_state->content_protection == state->content_protection)
7389 * Handles: UNDESIRED -> DESIRED
7390 * DESIRED -> UNDESIRED
7391 * ENABLED -> UNDESIRED
7393 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7397 * Handles: DESIRED -> ENABLED
7403 static void remove_stream(struct amdgpu_device *adev,
7404 struct amdgpu_crtc *acrtc,
7405 struct dc_stream_state *stream)
7407 /* this is the update mode case */
7409 acrtc->otg_inst = -1;
7410 acrtc->enabled = false;
7413 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
7414 struct dc_cursor_position *position)
7416 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7418 int xorigin = 0, yorigin = 0;
7420 position->enable = false;
7424 if (!crtc || !plane->state->fb)
7427 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
7428 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
7429 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
7431 plane->state->crtc_w,
7432 plane->state->crtc_h);
7436 x = plane->state->crtc_x;
7437 y = plane->state->crtc_y;
7439 if (x <= -amdgpu_crtc->max_cursor_width ||
7440 y <= -amdgpu_crtc->max_cursor_height)
7444 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
7448 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
7451 position->enable = true;
7452 position->translate_by_source = true;
7455 position->x_hotspot = xorigin;
7456 position->y_hotspot = yorigin;
7461 static void handle_cursor_update(struct drm_plane *plane,
7462 struct drm_plane_state *old_plane_state)
7464 struct amdgpu_device *adev = drm_to_adev(plane->dev);
7465 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
7466 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
7467 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
7468 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7469 uint64_t address = afb ? afb->address : 0;
7470 struct dc_cursor_position position;
7471 struct dc_cursor_attributes attributes;
7474 if (!plane->state->fb && !old_plane_state->fb)
7477 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
7479 amdgpu_crtc->crtc_id,
7480 plane->state->crtc_w,
7481 plane->state->crtc_h);
7483 ret = get_cursor_position(plane, crtc, &position);
7487 if (!position.enable) {
7488 /* turn off cursor */
7489 if (crtc_state && crtc_state->stream) {
7490 mutex_lock(&adev->dm.dc_lock);
7491 dc_stream_set_cursor_position(crtc_state->stream,
7493 mutex_unlock(&adev->dm.dc_lock);
7498 amdgpu_crtc->cursor_width = plane->state->crtc_w;
7499 amdgpu_crtc->cursor_height = plane->state->crtc_h;
7501 memset(&attributes, 0, sizeof(attributes));
7502 attributes.address.high_part = upper_32_bits(address);
7503 attributes.address.low_part = lower_32_bits(address);
7504 attributes.width = plane->state->crtc_w;
7505 attributes.height = plane->state->crtc_h;
7506 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
7507 attributes.rotation_angle = 0;
7508 attributes.attribute_flags.value = 0;
7510 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
7512 if (crtc_state->stream) {
7513 mutex_lock(&adev->dm.dc_lock);
7514 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
7516 DRM_ERROR("DC failed to set cursor attributes\n");
7518 if (!dc_stream_set_cursor_position(crtc_state->stream,
7520 DRM_ERROR("DC failed to set cursor position\n");
7521 mutex_unlock(&adev->dm.dc_lock);
7525 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7528 assert_spin_locked(&acrtc->base.dev->event_lock);
7529 WARN_ON(acrtc->event);
7531 acrtc->event = acrtc->base.state->event;
7533 /* Set the flip status */
7534 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7536 /* Mark this event as consumed */
7537 acrtc->base.state->event = NULL;
7539 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7543 static void update_freesync_state_on_stream(
7544 struct amdgpu_display_manager *dm,
7545 struct dm_crtc_state *new_crtc_state,
7546 struct dc_stream_state *new_stream,
7547 struct dc_plane_state *surface,
7548 u32 flip_timestamp_in_us)
7550 struct mod_vrr_params vrr_params;
7551 struct dc_info_packet vrr_infopacket = {0};
7552 struct amdgpu_device *adev = dm->adev;
7553 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7554 unsigned long flags;
7560 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7561 * For now it's sufficient to just guard against these conditions.
7564 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7567 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7568 vrr_params = acrtc->dm_irq_params.vrr_params;
7571 mod_freesync_handle_preflip(
7572 dm->freesync_module,
7575 flip_timestamp_in_us,
7578 if (adev->family < AMDGPU_FAMILY_AI &&
7579 amdgpu_dm_vrr_active(new_crtc_state)) {
7580 mod_freesync_handle_v_update(dm->freesync_module,
7581 new_stream, &vrr_params);
7583 /* Need to call this before the frame ends. */
7584 dc_stream_adjust_vmin_vmax(dm->dc,
7585 new_crtc_state->stream,
7586 &vrr_params.adjust);
7590 mod_freesync_build_vrr_infopacket(
7591 dm->freesync_module,
7595 TRANSFER_FUNC_UNKNOWN,
7598 new_crtc_state->freesync_timing_changed |=
7599 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7601 sizeof(vrr_params.adjust)) != 0);
7603 new_crtc_state->freesync_vrr_info_changed |=
7604 (memcmp(&new_crtc_state->vrr_infopacket,
7606 sizeof(vrr_infopacket)) != 0);
7608 acrtc->dm_irq_params.vrr_params = vrr_params;
7609 new_crtc_state->vrr_infopacket = vrr_infopacket;
7611 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
7612 new_stream->vrr_infopacket = vrr_infopacket;
7614 if (new_crtc_state->freesync_vrr_info_changed)
7615 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7616 new_crtc_state->base.crtc->base.id,
7617 (int)new_crtc_state->base.vrr_enabled,
7618 (int)vrr_params.state);
7620 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7623 static void update_stream_irq_parameters(
7624 struct amdgpu_display_manager *dm,
7625 struct dm_crtc_state *new_crtc_state)
7627 struct dc_stream_state *new_stream = new_crtc_state->stream;
7628 struct mod_vrr_params vrr_params;
7629 struct mod_freesync_config config = new_crtc_state->freesync_config;
7630 struct amdgpu_device *adev = dm->adev;
7631 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7632 unsigned long flags;
7638 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7639 * For now it's sufficient to just guard against these conditions.
7641 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7644 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7645 vrr_params = acrtc->dm_irq_params.vrr_params;
7647 if (new_crtc_state->vrr_supported &&
7648 config.min_refresh_in_uhz &&
7649 config.max_refresh_in_uhz) {
7650 config.state = new_crtc_state->base.vrr_enabled ?
7651 VRR_STATE_ACTIVE_VARIABLE :
7654 config.state = VRR_STATE_UNSUPPORTED;
7657 mod_freesync_build_vrr_params(dm->freesync_module,
7659 &config, &vrr_params);
7661 new_crtc_state->freesync_timing_changed |=
7662 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7663 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0);
7665 new_crtc_state->freesync_config = config;
7666 /* Copy state for access from DM IRQ handler */
7667 acrtc->dm_irq_params.freesync_config = config;
7668 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7669 acrtc->dm_irq_params.vrr_params = vrr_params;
7670 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7673 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7674 struct dm_crtc_state *new_state)
7676 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7677 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7679 if (!old_vrr_active && new_vrr_active) {
7680 /* Transition VRR inactive -> active:
7681 * While VRR is active, we must not disable vblank irq, as a
7682 * reenable after disable would compute bogus vblank/pflip
7683 * timestamps if it likely happened inside display front-porch.
7685 * We also need vupdate irq for the actual core vblank handling
7688 dm_set_vupdate_irq(new_state->base.crtc, true);
7689 drm_crtc_vblank_get(new_state->base.crtc);
7690 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7691 __func__, new_state->base.crtc->base.id);
7692 } else if (old_vrr_active && !new_vrr_active) {
7693 /* Transition VRR active -> inactive:
7694 * Allow vblank irq disable again for fixed refresh rate.
7696 dm_set_vupdate_irq(new_state->base.crtc, false);
7697 drm_crtc_vblank_put(new_state->base.crtc);
7698 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7699 __func__, new_state->base.crtc->base.id);
7703 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7705 struct drm_plane *plane;
7706 struct drm_plane_state *old_plane_state, *new_plane_state;
7710 * TODO: Make this per-stream so we don't issue redundant updates for
7711 * commits with multiple streams.
7713 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
7715 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7716 handle_cursor_update(plane, old_plane_state);
7719 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7720 struct dc_state *dc_state,
7721 struct drm_device *dev,
7722 struct amdgpu_display_manager *dm,
7723 struct drm_crtc *pcrtc,
7724 bool wait_for_vblank)
7727 uint64_t timestamp_ns;
7728 struct drm_plane *plane;
7729 struct drm_plane_state *old_plane_state, *new_plane_state;
7730 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7731 struct drm_crtc_state *new_pcrtc_state =
7732 drm_atomic_get_new_crtc_state(state, pcrtc);
7733 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7734 struct dm_crtc_state *dm_old_crtc_state =
7735 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7736 int planes_count = 0, vpos, hpos;
7738 unsigned long flags;
7739 struct amdgpu_bo *abo;
7740 uint32_t target_vblank, last_flip_vblank;
7741 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7742 bool pflip_present = false;
7744 struct dc_surface_update surface_updates[MAX_SURFACES];
7745 struct dc_plane_info plane_infos[MAX_SURFACES];
7746 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7747 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7748 struct dc_stream_update stream_update;
7751 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7754 dm_error("Failed to allocate update bundle\n");
7759 * Disable the cursor first if we're disabling all the planes.
7760 * It'll remain on the screen after the planes are re-enabled
7763 if (acrtc_state->active_planes == 0)
7764 amdgpu_dm_commit_cursors(state);
7766 /* update planes when needed */
7767 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7768 struct drm_crtc *crtc = new_plane_state->crtc;
7769 struct drm_crtc_state *new_crtc_state;
7770 struct drm_framebuffer *fb = new_plane_state->fb;
7771 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7772 bool plane_needs_flip;
7773 struct dc_plane_state *dc_plane;
7774 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7776 /* Cursor plane is handled after stream updates */
7777 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7780 if (!fb || !crtc || pcrtc != crtc)
7783 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7784 if (!new_crtc_state->active)
7787 dc_plane = dm_new_plane_state->dc_state;
7789 bundle->surface_updates[planes_count].surface = dc_plane;
7790 if (new_pcrtc_state->color_mgmt_changed) {
7791 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7792 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7793 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7796 fill_dc_scaling_info(new_plane_state,
7797 &bundle->scaling_infos[planes_count]);
7799 bundle->surface_updates[planes_count].scaling_info =
7800 &bundle->scaling_infos[planes_count];
7802 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7804 pflip_present = pflip_present || plane_needs_flip;
7806 if (!plane_needs_flip) {
7811 abo = gem_to_amdgpu_bo(fb->obj[0]);
7814 * Wait for all fences on this FB. Do limited wait to avoid
7815 * deadlock during GPU reset when this fence will not signal
7816 * but we hold reservation lock for the BO.
7818 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
7820 msecs_to_jiffies(5000));
7821 if (unlikely(r <= 0))
7822 DRM_ERROR("Waiting for fences timed out!");
7824 fill_dc_plane_info_and_addr(
7825 dm->adev, new_plane_state,
7827 &bundle->plane_infos[planes_count],
7828 &bundle->flip_addrs[planes_count].address,
7829 afb->tmz_surface, false);
7831 DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
7832 new_plane_state->plane->index,
7833 bundle->plane_infos[planes_count].dcc.enable);
7835 bundle->surface_updates[planes_count].plane_info =
7836 &bundle->plane_infos[planes_count];
7839 * Only allow immediate flips for fast updates that don't
7840 * change FB pitch, DCC state, rotation or mirroing.
7842 bundle->flip_addrs[planes_count].flip_immediate =
7843 crtc->state->async_flip &&
7844 acrtc_state->update_type == UPDATE_TYPE_FAST;
7846 timestamp_ns = ktime_get_ns();
7847 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7848 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7849 bundle->surface_updates[planes_count].surface = dc_plane;
7851 if (!bundle->surface_updates[planes_count].surface) {
7852 DRM_ERROR("No surface for CRTC: id=%d\n",
7853 acrtc_attach->crtc_id);
7857 if (plane == pcrtc->primary)
7858 update_freesync_state_on_stream(
7861 acrtc_state->stream,
7863 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7865 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
7867 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7868 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7874 if (pflip_present) {
7876 /* Use old throttling in non-vrr fixed refresh rate mode
7877 * to keep flip scheduling based on target vblank counts
7878 * working in a backwards compatible way, e.g., for
7879 * clients using the GLX_OML_sync_control extension or
7880 * DRI3/Present extension with defined target_msc.
7882 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7885 /* For variable refresh rate mode only:
7886 * Get vblank of last completed flip to avoid > 1 vrr
7887 * flips per video frame by use of throttling, but allow
7888 * flip programming anywhere in the possibly large
7889 * variable vrr vblank interval for fine-grained flip
7890 * timing control and more opportunity to avoid stutter
7891 * on late submission of flips.
7893 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7894 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7895 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7898 target_vblank = last_flip_vblank + wait_for_vblank;
7901 * Wait until we're out of the vertical blank period before the one
7902 * targeted by the flip
7904 while ((acrtc_attach->enabled &&
7905 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7906 0, &vpos, &hpos, NULL,
7907 NULL, &pcrtc->hwmode)
7908 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7909 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7910 (int)(target_vblank -
7911 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7912 usleep_range(1000, 1100);
7916 * Prepare the flip event for the pageflip interrupt to handle.
7918 * This only works in the case where we've already turned on the
7919 * appropriate hardware blocks (eg. HUBP) so in the transition case
7920 * from 0 -> n planes we have to skip a hardware generated event
7921 * and rely on sending it from software.
7923 if (acrtc_attach->base.state->event &&
7924 acrtc_state->active_planes > 0) {
7925 drm_crtc_vblank_get(pcrtc);
7927 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7929 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7930 prepare_flip_isr(acrtc_attach);
7932 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7935 if (acrtc_state->stream) {
7936 if (acrtc_state->freesync_vrr_info_changed)
7937 bundle->stream_update.vrr_infopacket =
7938 &acrtc_state->stream->vrr_infopacket;
7942 /* Update the planes if changed or disable if we don't have any. */
7943 if ((planes_count || acrtc_state->active_planes == 0) &&
7944 acrtc_state->stream) {
7945 bundle->stream_update.stream = acrtc_state->stream;
7946 if (new_pcrtc_state->mode_changed) {
7947 bundle->stream_update.src = acrtc_state->stream->src;
7948 bundle->stream_update.dst = acrtc_state->stream->dst;
7951 if (new_pcrtc_state->color_mgmt_changed) {
7953 * TODO: This isn't fully correct since we've actually
7954 * already modified the stream in place.
7956 bundle->stream_update.gamut_remap =
7957 &acrtc_state->stream->gamut_remap_matrix;
7958 bundle->stream_update.output_csc_transform =
7959 &acrtc_state->stream->csc_color_matrix;
7960 bundle->stream_update.out_transfer_func =
7961 acrtc_state->stream->out_transfer_func;
7964 acrtc_state->stream->abm_level = acrtc_state->abm_level;
7965 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7966 bundle->stream_update.abm_level = &acrtc_state->abm_level;
7969 * If FreeSync state on the stream has changed then we need to
7970 * re-adjust the min/max bounds now that DC doesn't handle this
7971 * as part of commit.
7973 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
7974 amdgpu_dm_vrr_active(acrtc_state)) {
7975 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7976 dc_stream_adjust_vmin_vmax(
7977 dm->dc, acrtc_state->stream,
7978 &acrtc_attach->dm_irq_params.vrr_params.adjust);
7979 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7981 mutex_lock(&dm->dc_lock);
7982 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7983 acrtc_state->stream->link->psr_settings.psr_allow_active)
7984 amdgpu_dm_psr_disable(acrtc_state->stream);
7986 dc_commit_updates_for_stream(dm->dc,
7987 bundle->surface_updates,
7989 acrtc_state->stream,
7990 &bundle->stream_update,
7994 * Enable or disable the interrupts on the backend.
7996 * Most pipes are put into power gating when unused.
7998 * When power gating is enabled on a pipe we lose the
7999 * interrupt enablement state when power gating is disabled.
8001 * So we need to update the IRQ control state in hardware
8002 * whenever the pipe turns on (since it could be previously
8003 * power gated) or off (since some pipes can't be power gated
8006 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8007 dm_update_pflip_irq_state(drm_to_adev(dev),
8010 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8011 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8012 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8013 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8014 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
8015 acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
8016 !acrtc_state->stream->link->psr_settings.psr_allow_active) {
8017 amdgpu_dm_psr_enable(acrtc_state->stream);
8020 mutex_unlock(&dm->dc_lock);
8024 * Update cursor state *after* programming all the planes.
8025 * This avoids redundant programming in the case where we're going
8026 * to be disabling a single plane - those pipes are being disabled.
8028 if (acrtc_state->active_planes)
8029 amdgpu_dm_commit_cursors(state);
8035 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8036 struct drm_atomic_state *state)
8038 struct amdgpu_device *adev = drm_to_adev(dev);
8039 struct amdgpu_dm_connector *aconnector;
8040 struct drm_connector *connector;
8041 struct drm_connector_state *old_con_state, *new_con_state;
8042 struct drm_crtc_state *new_crtc_state;
8043 struct dm_crtc_state *new_dm_crtc_state;
8044 const struct dc_stream_status *status;
8047 /* Notify device removals. */
8048 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8049 if (old_con_state->crtc != new_con_state->crtc) {
8050 /* CRTC changes require notification. */
8054 if (!new_con_state->crtc)
8057 new_crtc_state = drm_atomic_get_new_crtc_state(
8058 state, new_con_state->crtc);
8060 if (!new_crtc_state)
8063 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8067 aconnector = to_amdgpu_dm_connector(connector);
8069 mutex_lock(&adev->dm.audio_lock);
8070 inst = aconnector->audio_inst;
8071 aconnector->audio_inst = -1;
8072 mutex_unlock(&adev->dm.audio_lock);
8074 amdgpu_dm_audio_eld_notify(adev, inst);
8077 /* Notify audio device additions. */
8078 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8079 if (!new_con_state->crtc)
8082 new_crtc_state = drm_atomic_get_new_crtc_state(
8083 state, new_con_state->crtc);
8085 if (!new_crtc_state)
8088 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8091 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8092 if (!new_dm_crtc_state->stream)
8095 status = dc_stream_get_status(new_dm_crtc_state->stream);
8099 aconnector = to_amdgpu_dm_connector(connector);
8101 mutex_lock(&adev->dm.audio_lock);
8102 inst = status->audio_inst;
8103 aconnector->audio_inst = inst;
8104 mutex_unlock(&adev->dm.audio_lock);
8106 amdgpu_dm_audio_eld_notify(adev, inst);
8111 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8112 * @crtc_state: the DRM CRTC state
8113 * @stream_state: the DC stream state.
8115 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8116 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8118 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8119 struct dc_stream_state *stream_state)
8121 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8125 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8126 * @state: The atomic state to commit
8128 * This will tell DC to commit the constructed DC state from atomic_check,
8129 * programming the hardware. Any failures here implies a hardware failure, since
8130 * atomic check should have filtered anything non-kosher.
8132 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8134 struct drm_device *dev = state->dev;
8135 struct amdgpu_device *adev = drm_to_adev(dev);
8136 struct amdgpu_display_manager *dm = &adev->dm;
8137 struct dm_atomic_state *dm_state;
8138 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8140 struct drm_crtc *crtc;
8141 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8142 unsigned long flags;
8143 bool wait_for_vblank = true;
8144 struct drm_connector *connector;
8145 struct drm_connector_state *old_con_state, *new_con_state;
8146 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8147 int crtc_disable_count = 0;
8148 bool mode_set_reset_required = false;
8150 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8152 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8154 dm_state = dm_atomic_get_new_state(state);
8155 if (dm_state && dm_state->context) {
8156 dc_state = dm_state->context;
8158 /* No state changes, retain current state. */
8159 dc_state_temp = dc_create_state(dm->dc);
8160 ASSERT(dc_state_temp);
8161 dc_state = dc_state_temp;
8162 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8165 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8166 new_crtc_state, i) {
8167 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8169 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8171 if (old_crtc_state->active &&
8172 (!new_crtc_state->active ||
8173 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8174 manage_dm_interrupts(adev, acrtc, false);
8175 dc_stream_release(dm_old_crtc_state->stream);
8179 drm_atomic_helper_calc_timestamping_constants(state);
8181 /* update changed items */
8182 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8183 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8185 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8186 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8189 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8190 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8191 "connectors_changed:%d\n",
8193 new_crtc_state->enable,
8194 new_crtc_state->active,
8195 new_crtc_state->planes_changed,
8196 new_crtc_state->mode_changed,
8197 new_crtc_state->active_changed,
8198 new_crtc_state->connectors_changed);
8200 /* Disable cursor if disabling crtc */
8201 if (old_crtc_state->active && !new_crtc_state->active) {
8202 struct dc_cursor_position position;
8204 memset(&position, 0, sizeof(position));
8205 mutex_lock(&dm->dc_lock);
8206 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8207 mutex_unlock(&dm->dc_lock);
8210 /* Copy all transient state flags into dc state */
8211 if (dm_new_crtc_state->stream) {
8212 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8213 dm_new_crtc_state->stream);
8216 /* handles headless hotplug case, updating new_state and
8217 * aconnector as needed
8220 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8222 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8224 if (!dm_new_crtc_state->stream) {
8226 * this could happen because of issues with
8227 * userspace notifications delivery.
8228 * In this case userspace tries to set mode on
8229 * display which is disconnected in fact.
8230 * dc_sink is NULL in this case on aconnector.
8231 * We expect reset mode will come soon.
8233 * This can also happen when unplug is done
8234 * during resume sequence ended
8236 * In this case, we want to pretend we still
8237 * have a sink to keep the pipe running so that
8238 * hw state is consistent with the sw state
8240 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8241 __func__, acrtc->base.base.id);
8245 if (dm_old_crtc_state->stream)
8246 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8248 pm_runtime_get_noresume(dev->dev);
8250 acrtc->enabled = true;
8251 acrtc->hw_mode = new_crtc_state->mode;
8252 crtc->hwmode = new_crtc_state->mode;
8253 mode_set_reset_required = true;
8254 } else if (modereset_required(new_crtc_state)) {
8255 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8256 /* i.e. reset mode */
8257 if (dm_old_crtc_state->stream)
8258 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8259 mode_set_reset_required = true;
8261 } /* for_each_crtc_in_state() */
8264 /* if there mode set or reset, disable eDP PSR */
8265 if (mode_set_reset_required)
8266 amdgpu_dm_psr_disable_all(dm);
8268 dm_enable_per_frame_crtc_master_sync(dc_state);
8269 mutex_lock(&dm->dc_lock);
8270 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8271 mutex_unlock(&dm->dc_lock);
8274 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8275 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8277 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8279 if (dm_new_crtc_state->stream != NULL) {
8280 const struct dc_stream_status *status =
8281 dc_stream_get_status(dm_new_crtc_state->stream);
8284 status = dc_stream_get_status_from_state(dc_state,
8285 dm_new_crtc_state->stream);
8287 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8289 acrtc->otg_inst = status->primary_otg_inst;
8292 #ifdef CONFIG_DRM_AMD_DC_HDCP
8293 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8294 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8295 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8296 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8298 new_crtc_state = NULL;
8301 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8303 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8305 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8306 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8307 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8308 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8309 dm_new_con_state->update_hdcp = true;
8313 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8314 hdcp_update_display(
8315 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8316 new_con_state->hdcp_content_type,
8317 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
8322 /* Handle connector state changes */
8323 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8324 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8325 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8326 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8327 struct dc_surface_update dummy_updates[MAX_SURFACES];
8328 struct dc_stream_update stream_update;
8329 struct dc_info_packet hdr_packet;
8330 struct dc_stream_status *status = NULL;
8331 bool abm_changed, hdr_changed, scaling_changed;
8333 memset(&dummy_updates, 0, sizeof(dummy_updates));
8334 memset(&stream_update, 0, sizeof(stream_update));
8337 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8338 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8341 /* Skip any modesets/resets */
8342 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8345 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8346 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8348 scaling_changed = is_scaling_state_different(dm_new_con_state,
8351 abm_changed = dm_new_crtc_state->abm_level !=
8352 dm_old_crtc_state->abm_level;
8355 is_hdr_metadata_different(old_con_state, new_con_state);
8357 if (!scaling_changed && !abm_changed && !hdr_changed)
8360 stream_update.stream = dm_new_crtc_state->stream;
8361 if (scaling_changed) {
8362 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8363 dm_new_con_state, dm_new_crtc_state->stream);
8365 stream_update.src = dm_new_crtc_state->stream->src;
8366 stream_update.dst = dm_new_crtc_state->stream->dst;
8370 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8372 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8376 fill_hdr_info_packet(new_con_state, &hdr_packet);
8377 stream_update.hdr_static_metadata = &hdr_packet;
8380 status = dc_stream_get_status(dm_new_crtc_state->stream);
8382 WARN_ON(!status->plane_count);
8385 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8386 * Here we create an empty update on each plane.
8387 * To fix this, DC should permit updating only stream properties.
8389 for (j = 0; j < status->plane_count; j++)
8390 dummy_updates[j].surface = status->plane_states[0];
8393 mutex_lock(&dm->dc_lock);
8394 dc_commit_updates_for_stream(dm->dc,
8396 status->plane_count,
8397 dm_new_crtc_state->stream,
8400 mutex_unlock(&dm->dc_lock);
8403 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8404 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8405 new_crtc_state, i) {
8406 if (old_crtc_state->active && !new_crtc_state->active)
8407 crtc_disable_count++;
8409 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8410 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8412 /* For freesync config update on crtc state and params for irq */
8413 update_stream_irq_parameters(dm, dm_new_crtc_state);
8415 /* Handle vrr on->off / off->on transitions */
8416 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
8421 * Enable interrupts for CRTCs that are newly enabled or went through
8422 * a modeset. It was intentionally deferred until after the front end
8423 * state was modified to wait until the OTG was on and so the IRQ
8424 * handlers didn't access stale or invalid state.
8426 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8427 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8429 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8431 if (new_crtc_state->active &&
8432 (!old_crtc_state->active ||
8433 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8434 dc_stream_retain(dm_new_crtc_state->stream);
8435 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8436 manage_dm_interrupts(adev, acrtc, true);
8438 #ifdef CONFIG_DEBUG_FS
8440 * Frontend may have changed so reapply the CRC capture
8441 * settings for the stream.
8443 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8445 if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
8446 amdgpu_dm_crtc_configure_crc_source(
8447 crtc, dm_new_crtc_state,
8448 dm_new_crtc_state->crc_src);
8454 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8455 if (new_crtc_state->async_flip)
8456 wait_for_vblank = false;
8458 /* update planes when needed per crtc*/
8459 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8460 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8462 if (dm_new_crtc_state->stream)
8463 amdgpu_dm_commit_planes(state, dc_state, dev,
8464 dm, crtc, wait_for_vblank);
8467 /* Update audio instances for each connector. */
8468 amdgpu_dm_commit_audio(dev, state);
8471 * send vblank event on all events not handled in flip and
8472 * mark consumed event for drm_atomic_helper_commit_hw_done
8474 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8475 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8477 if (new_crtc_state->event)
8478 drm_send_event_locked(dev, &new_crtc_state->event->base);
8480 new_crtc_state->event = NULL;
8482 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8484 /* Signal HW programming completion */
8485 drm_atomic_helper_commit_hw_done(state);
8487 if (wait_for_vblank)
8488 drm_atomic_helper_wait_for_flip_done(dev, state);
8490 drm_atomic_helper_cleanup_planes(dev, state);
8492 /* return the stolen vga memory back to VRAM */
8493 if (!adev->mman.keep_stolen_vga_memory)
8494 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8495 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8498 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8499 * so we can put the GPU into runtime suspend if we're not driving any
8502 for (i = 0; i < crtc_disable_count; i++)
8503 pm_runtime_put_autosuspend(dev->dev);
8504 pm_runtime_mark_last_busy(dev->dev);
8507 dc_release_state(dc_state_temp);
8511 static int dm_force_atomic_commit(struct drm_connector *connector)
8514 struct drm_device *ddev = connector->dev;
8515 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8516 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8517 struct drm_plane *plane = disconnected_acrtc->base.primary;
8518 struct drm_connector_state *conn_state;
8519 struct drm_crtc_state *crtc_state;
8520 struct drm_plane_state *plane_state;
8525 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8527 /* Construct an atomic state to restore previous display setting */
8530 * Attach connectors to drm_atomic_state
8532 conn_state = drm_atomic_get_connector_state(state, connector);
8534 ret = PTR_ERR_OR_ZERO(conn_state);
8538 /* Attach crtc to drm_atomic_state*/
8539 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8541 ret = PTR_ERR_OR_ZERO(crtc_state);
8545 /* force a restore */
8546 crtc_state->mode_changed = true;
8548 /* Attach plane to drm_atomic_state */
8549 plane_state = drm_atomic_get_plane_state(state, plane);
8551 ret = PTR_ERR_OR_ZERO(plane_state);
8555 /* Call commit internally with the state we just constructed */
8556 ret = drm_atomic_commit(state);
8559 drm_atomic_state_put(state);
8561 DRM_ERROR("Restoring old state failed with %i\n", ret);
8567 * This function handles all cases when set mode does not come upon hotplug.
8568 * This includes when a display is unplugged then plugged back into the
8569 * same port and when running without usermode desktop manager supprot
8571 void dm_restore_drm_connector_state(struct drm_device *dev,
8572 struct drm_connector *connector)
8574 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8575 struct amdgpu_crtc *disconnected_acrtc;
8576 struct dm_crtc_state *acrtc_state;
8578 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8581 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8582 if (!disconnected_acrtc)
8585 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8586 if (!acrtc_state->stream)
8590 * If the previous sink is not released and different from the current,
8591 * we deduce we are in a state where we can not rely on usermode call
8592 * to turn on the display, so we do it here
8594 if (acrtc_state->stream->sink != aconnector->dc_sink)
8595 dm_force_atomic_commit(&aconnector->base);
8599 * Grabs all modesetting locks to serialize against any blocking commits,
8600 * Waits for completion of all non blocking commits.
8602 static int do_aquire_global_lock(struct drm_device *dev,
8603 struct drm_atomic_state *state)
8605 struct drm_crtc *crtc;
8606 struct drm_crtc_commit *commit;
8610 * Adding all modeset locks to aquire_ctx will
8611 * ensure that when the framework release it the
8612 * extra locks we are locking here will get released to
8614 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8618 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8619 spin_lock(&crtc->commit_lock);
8620 commit = list_first_entry_or_null(&crtc->commit_list,
8621 struct drm_crtc_commit, commit_entry);
8623 drm_crtc_commit_get(commit);
8624 spin_unlock(&crtc->commit_lock);
8630 * Make sure all pending HW programming completed and
8633 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8636 ret = wait_for_completion_interruptible_timeout(
8637 &commit->flip_done, 10*HZ);
8640 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8641 "timed out\n", crtc->base.id, crtc->name);
8643 drm_crtc_commit_put(commit);
8646 return ret < 0 ? ret : 0;
8649 static void get_freesync_config_for_crtc(
8650 struct dm_crtc_state *new_crtc_state,
8651 struct dm_connector_state *new_con_state)
8653 struct mod_freesync_config config = {0};
8654 struct amdgpu_dm_connector *aconnector =
8655 to_amdgpu_dm_connector(new_con_state->base.connector);
8656 struct drm_display_mode *mode = &new_crtc_state->base.mode;
8657 int vrefresh = drm_mode_vrefresh(mode);
8659 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8660 vrefresh >= aconnector->min_vfreq &&
8661 vrefresh <= aconnector->max_vfreq;
8663 if (new_crtc_state->vrr_supported) {
8664 new_crtc_state->stream->ignore_msa_timing_param = true;
8665 config.state = new_crtc_state->base.vrr_enabled ?
8666 VRR_STATE_ACTIVE_VARIABLE :
8668 config.min_refresh_in_uhz =
8669 aconnector->min_vfreq * 1000000;
8670 config.max_refresh_in_uhz =
8671 aconnector->max_vfreq * 1000000;
8672 config.vsif_supported = true;
8676 new_crtc_state->freesync_config = config;
8679 static void reset_freesync_config_for_crtc(
8680 struct dm_crtc_state *new_crtc_state)
8682 new_crtc_state->vrr_supported = false;
8684 memset(&new_crtc_state->vrr_infopacket, 0,
8685 sizeof(new_crtc_state->vrr_infopacket));
8688 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8689 struct drm_atomic_state *state,
8690 struct drm_crtc *crtc,
8691 struct drm_crtc_state *old_crtc_state,
8692 struct drm_crtc_state *new_crtc_state,
8694 bool *lock_and_validation_needed)
8696 struct dm_atomic_state *dm_state = NULL;
8697 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8698 struct dc_stream_state *new_stream;
8702 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8703 * update changed items
8705 struct amdgpu_crtc *acrtc = NULL;
8706 struct amdgpu_dm_connector *aconnector = NULL;
8707 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8708 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8712 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8713 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8714 acrtc = to_amdgpu_crtc(crtc);
8715 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8717 /* TODO This hack should go away */
8718 if (aconnector && enable) {
8719 /* Make sure fake sink is created in plug-in scenario */
8720 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8722 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8725 if (IS_ERR(drm_new_conn_state)) {
8726 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8730 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8731 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
8733 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8736 new_stream = create_validate_stream_for_sink(aconnector,
8737 &new_crtc_state->mode,
8739 dm_old_crtc_state->stream);
8742 * we can have no stream on ACTION_SET if a display
8743 * was disconnected during S3, in this case it is not an
8744 * error, the OS will be updated after detection, and
8745 * will do the right thing on next atomic commit
8749 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8750 __func__, acrtc->base.base.id);
8756 * TODO: Check VSDB bits to decide whether this should
8757 * be enabled or not.
8759 new_stream->triggered_crtc_reset.enabled =
8760 dm->force_timing_sync;
8762 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8764 ret = fill_hdr_info_packet(drm_new_conn_state,
8765 &new_stream->hdr_static_metadata);
8770 * If we already removed the old stream from the context
8771 * (and set the new stream to NULL) then we can't reuse
8772 * the old stream even if the stream and scaling are unchanged.
8773 * We'll hit the BUG_ON and black screen.
8775 * TODO: Refactor this function to allow this check to work
8776 * in all conditions.
8778 if (dm_new_crtc_state->stream &&
8779 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
8780 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
8781 new_crtc_state->mode_changed = false;
8782 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
8783 new_crtc_state->mode_changed);
8787 /* mode_changed flag may get updated above, need to check again */
8788 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8792 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8793 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8794 "connectors_changed:%d\n",
8796 new_crtc_state->enable,
8797 new_crtc_state->active,
8798 new_crtc_state->planes_changed,
8799 new_crtc_state->mode_changed,
8800 new_crtc_state->active_changed,
8801 new_crtc_state->connectors_changed);
8803 /* Remove stream for any changed/disabled CRTC */
8806 if (!dm_old_crtc_state->stream)
8809 ret = dm_atomic_get_state(state, &dm_state);
8813 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
8816 /* i.e. reset mode */
8817 if (dc_remove_stream_from_ctx(
8820 dm_old_crtc_state->stream) != DC_OK) {
8825 dc_stream_release(dm_old_crtc_state->stream);
8826 dm_new_crtc_state->stream = NULL;
8828 reset_freesync_config_for_crtc(dm_new_crtc_state);
8830 *lock_and_validation_needed = true;
8832 } else {/* Add stream for any updated/enabled CRTC */
8834 * Quick fix to prevent NULL pointer on new_stream when
8835 * added MST connectors not found in existing crtc_state in the chained mode
8836 * TODO: need to dig out the root cause of that
8838 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
8841 if (modereset_required(new_crtc_state))
8844 if (modeset_required(new_crtc_state, new_stream,
8845 dm_old_crtc_state->stream)) {
8847 WARN_ON(dm_new_crtc_state->stream);
8849 ret = dm_atomic_get_state(state, &dm_state);
8853 dm_new_crtc_state->stream = new_stream;
8855 dc_stream_retain(new_stream);
8857 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
8860 if (dc_add_stream_to_ctx(
8863 dm_new_crtc_state->stream) != DC_OK) {
8868 *lock_and_validation_needed = true;
8873 /* Release extra reference */
8875 dc_stream_release(new_stream);
8878 * We want to do dc stream updates that do not require a
8879 * full modeset below.
8881 if (!(enable && aconnector && new_crtc_state->active))
8884 * Given above conditions, the dc state cannot be NULL because:
8885 * 1. We're in the process of enabling CRTCs (just been added
8886 * to the dc context, or already is on the context)
8887 * 2. Has a valid connector attached, and
8888 * 3. Is currently active and enabled.
8889 * => The dc stream state currently exists.
8891 BUG_ON(dm_new_crtc_state->stream == NULL);
8893 /* Scaling or underscan settings */
8894 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
8895 update_stream_scaling_settings(
8896 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
8899 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8902 * Color management settings. We also update color properties
8903 * when a modeset is needed, to ensure it gets reprogrammed.
8905 if (dm_new_crtc_state->base.color_mgmt_changed ||
8906 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
8907 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
8912 /* Update Freesync settings. */
8913 get_freesync_config_for_crtc(dm_new_crtc_state,
8920 dc_stream_release(new_stream);
8924 static bool should_reset_plane(struct drm_atomic_state *state,
8925 struct drm_plane *plane,
8926 struct drm_plane_state *old_plane_state,
8927 struct drm_plane_state *new_plane_state)
8929 struct drm_plane *other;
8930 struct drm_plane_state *old_other_state, *new_other_state;
8931 struct drm_crtc_state *new_crtc_state;
8935 * TODO: Remove this hack once the checks below are sufficient
8936 * enough to determine when we need to reset all the planes on
8939 if (state->allow_modeset)
8942 /* Exit early if we know that we're adding or removing the plane. */
8943 if (old_plane_state->crtc != new_plane_state->crtc)
8946 /* old crtc == new_crtc == NULL, plane not in context. */
8947 if (!new_plane_state->crtc)
8951 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
8953 if (!new_crtc_state)
8956 /* CRTC Degamma changes currently require us to recreate planes. */
8957 if (new_crtc_state->color_mgmt_changed)
8960 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
8964 * If there are any new primary or overlay planes being added or
8965 * removed then the z-order can potentially change. To ensure
8966 * correct z-order and pipe acquisition the current DC architecture
8967 * requires us to remove and recreate all existing planes.
8969 * TODO: Come up with a more elegant solution for this.
8971 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
8972 struct amdgpu_framebuffer *old_afb, *new_afb;
8973 if (other->type == DRM_PLANE_TYPE_CURSOR)
8976 if (old_other_state->crtc != new_plane_state->crtc &&
8977 new_other_state->crtc != new_plane_state->crtc)
8980 if (old_other_state->crtc != new_other_state->crtc)
8983 /* Src/dst size and scaling updates. */
8984 if (old_other_state->src_w != new_other_state->src_w ||
8985 old_other_state->src_h != new_other_state->src_h ||
8986 old_other_state->crtc_w != new_other_state->crtc_w ||
8987 old_other_state->crtc_h != new_other_state->crtc_h)
8990 /* Rotation / mirroring updates. */
8991 if (old_other_state->rotation != new_other_state->rotation)
8994 /* Blending updates. */
8995 if (old_other_state->pixel_blend_mode !=
8996 new_other_state->pixel_blend_mode)
8999 /* Alpha updates. */
9000 if (old_other_state->alpha != new_other_state->alpha)
9003 /* Colorspace changes. */
9004 if (old_other_state->color_range != new_other_state->color_range ||
9005 old_other_state->color_encoding != new_other_state->color_encoding)
9008 /* Framebuffer checks fall at the end. */
9009 if (!old_other_state->fb || !new_other_state->fb)
9012 /* Pixel format changes can require bandwidth updates. */
9013 if (old_other_state->fb->format != new_other_state->fb->format)
9016 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9017 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9019 /* Tiling and DCC changes also require bandwidth updates. */
9020 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9021 old_afb->base.modifier != new_afb->base.modifier)
9028 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9029 struct drm_plane_state *new_plane_state,
9030 struct drm_framebuffer *fb)
9032 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9033 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9037 if (fb->width > new_acrtc->max_cursor_width ||
9038 fb->height > new_acrtc->max_cursor_height) {
9039 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9040 new_plane_state->fb->width,
9041 new_plane_state->fb->height);
9044 if (new_plane_state->src_w != fb->width << 16 ||
9045 new_plane_state->src_h != fb->height << 16) {
9046 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9050 /* Pitch in pixels */
9051 pitch = fb->pitches[0] / fb->format->cpp[0];
9053 if (fb->width != pitch) {
9054 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9063 /* FB pitch is supported by cursor plane */
9066 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9070 /* Core DRM takes care of checking FB modifiers, so we only need to
9071 * check tiling flags when the FB doesn't have a modifier. */
9072 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9073 if (adev->family < AMDGPU_FAMILY_AI) {
9074 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9075 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9076 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9078 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9081 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9089 static int dm_update_plane_state(struct dc *dc,
9090 struct drm_atomic_state *state,
9091 struct drm_plane *plane,
9092 struct drm_plane_state *old_plane_state,
9093 struct drm_plane_state *new_plane_state,
9095 bool *lock_and_validation_needed)
9098 struct dm_atomic_state *dm_state = NULL;
9099 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9100 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9101 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9102 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9103 struct amdgpu_crtc *new_acrtc;
9108 new_plane_crtc = new_plane_state->crtc;
9109 old_plane_crtc = old_plane_state->crtc;
9110 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9111 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9113 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9114 if (!enable || !new_plane_crtc ||
9115 drm_atomic_plane_disabling(plane->state, new_plane_state))
9118 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9120 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9121 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9125 if (new_plane_state->fb) {
9126 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9127 new_plane_state->fb);
9135 needs_reset = should_reset_plane(state, plane, old_plane_state,
9138 /* Remove any changed/removed planes */
9143 if (!old_plane_crtc)
9146 old_crtc_state = drm_atomic_get_old_crtc_state(
9147 state, old_plane_crtc);
9148 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9150 if (!dm_old_crtc_state->stream)
9153 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9154 plane->base.id, old_plane_crtc->base.id);
9156 ret = dm_atomic_get_state(state, &dm_state);
9160 if (!dc_remove_plane_from_context(
9162 dm_old_crtc_state->stream,
9163 dm_old_plane_state->dc_state,
9164 dm_state->context)) {
9170 dc_plane_state_release(dm_old_plane_state->dc_state);
9171 dm_new_plane_state->dc_state = NULL;
9173 *lock_and_validation_needed = true;
9175 } else { /* Add new planes */
9176 struct dc_plane_state *dc_new_plane_state;
9178 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9181 if (!new_plane_crtc)
9184 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9185 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9187 if (!dm_new_crtc_state->stream)
9193 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9197 WARN_ON(dm_new_plane_state->dc_state);
9199 dc_new_plane_state = dc_create_plane_state(dc);
9200 if (!dc_new_plane_state)
9203 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
9204 plane->base.id, new_plane_crtc->base.id);
9206 ret = fill_dc_plane_attributes(
9207 drm_to_adev(new_plane_crtc->dev),
9212 dc_plane_state_release(dc_new_plane_state);
9216 ret = dm_atomic_get_state(state, &dm_state);
9218 dc_plane_state_release(dc_new_plane_state);
9223 * Any atomic check errors that occur after this will
9224 * not need a release. The plane state will be attached
9225 * to the stream, and therefore part of the atomic
9226 * state. It'll be released when the atomic state is
9229 if (!dc_add_plane_to_context(
9231 dm_new_crtc_state->stream,
9233 dm_state->context)) {
9235 dc_plane_state_release(dc_new_plane_state);
9239 dm_new_plane_state->dc_state = dc_new_plane_state;
9241 /* Tell DC to do a full surface update every time there
9242 * is a plane change. Inefficient, but works for now.
9244 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9246 *lock_and_validation_needed = true;
9253 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9254 struct drm_crtc *crtc,
9255 struct drm_crtc_state *new_crtc_state)
9257 struct drm_plane_state *new_cursor_state, *new_primary_state;
9258 int cursor_scale_w, cursor_scale_h, primary_scale_w, primary_scale_h;
9260 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9261 * cursor per pipe but it's going to inherit the scaling and
9262 * positioning from the underlying pipe. Check the cursor plane's
9263 * blending properties match the primary plane's. */
9265 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
9266 new_primary_state = drm_atomic_get_new_plane_state(state, crtc->primary);
9267 if (!new_cursor_state || !new_primary_state || !new_cursor_state->fb) {
9271 cursor_scale_w = new_cursor_state->crtc_w * 1000 /
9272 (new_cursor_state->src_w >> 16);
9273 cursor_scale_h = new_cursor_state->crtc_h * 1000 /
9274 (new_cursor_state->src_h >> 16);
9276 primary_scale_w = new_primary_state->crtc_w * 1000 /
9277 (new_primary_state->src_w >> 16);
9278 primary_scale_h = new_primary_state->crtc_h * 1000 /
9279 (new_primary_state->src_h >> 16);
9281 if (cursor_scale_w != primary_scale_w ||
9282 cursor_scale_h != primary_scale_h) {
9283 DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary plane\n");
9290 #if defined(CONFIG_DRM_AMD_DC_DCN)
9291 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9293 struct drm_connector *connector;
9294 struct drm_connector_state *conn_state;
9295 struct amdgpu_dm_connector *aconnector = NULL;
9297 for_each_new_connector_in_state(state, connector, conn_state, i) {
9298 if (conn_state->crtc != crtc)
9301 aconnector = to_amdgpu_dm_connector(connector);
9302 if (!aconnector->port || !aconnector->mst_port)
9311 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9316 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9317 * @dev: The DRM device
9318 * @state: The atomic state to commit
9320 * Validate that the given atomic state is programmable by DC into hardware.
9321 * This involves constructing a &struct dc_state reflecting the new hardware
9322 * state we wish to commit, then querying DC to see if it is programmable. It's
9323 * important not to modify the existing DC state. Otherwise, atomic_check
9324 * may unexpectedly commit hardware changes.
9326 * When validating the DC state, it's important that the right locks are
9327 * acquired. For full updates case which removes/adds/updates streams on one
9328 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9329 * that any such full update commit will wait for completion of any outstanding
9330 * flip using DRMs synchronization events.
9332 * Note that DM adds the affected connectors for all CRTCs in state, when that
9333 * might not seem necessary. This is because DC stream creation requires the
9334 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9335 * be possible but non-trivial - a possible TODO item.
9337 * Return: -Error code if validation failed.
9339 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9340 struct drm_atomic_state *state)
9342 struct amdgpu_device *adev = drm_to_adev(dev);
9343 struct dm_atomic_state *dm_state = NULL;
9344 struct dc *dc = adev->dm.dc;
9345 struct drm_connector *connector;
9346 struct drm_connector_state *old_con_state, *new_con_state;
9347 struct drm_crtc *crtc;
9348 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9349 struct drm_plane *plane;
9350 struct drm_plane_state *old_plane_state, *new_plane_state;
9351 enum dc_status status;
9353 bool lock_and_validation_needed = false;
9354 struct dm_crtc_state *dm_old_crtc_state;
9356 trace_amdgpu_dm_atomic_check_begin(state);
9358 ret = drm_atomic_helper_check_modeset(dev, state);
9362 /* Check connector changes */
9363 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9364 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9365 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9367 /* Skip connectors that are disabled or part of modeset already. */
9368 if (!old_con_state->crtc && !new_con_state->crtc)
9371 if (!new_con_state->crtc)
9374 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9375 if (IS_ERR(new_crtc_state)) {
9376 ret = PTR_ERR(new_crtc_state);
9380 if (dm_old_con_state->abm_level !=
9381 dm_new_con_state->abm_level)
9382 new_crtc_state->connectors_changed = true;
9385 #if defined(CONFIG_DRM_AMD_DC_DCN)
9386 if (adev->asic_type >= CHIP_NAVI10) {
9387 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9388 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9389 ret = add_affected_mst_dsc_crtcs(state, crtc);
9396 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9397 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9399 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9400 !new_crtc_state->color_mgmt_changed &&
9401 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9402 dm_old_crtc_state->dsc_force_changed == false)
9405 if (!new_crtc_state->enable)
9408 ret = drm_atomic_add_affected_connectors(state, crtc);
9412 ret = drm_atomic_add_affected_planes(state, crtc);
9416 if (dm_old_crtc_state->dsc_force_changed)
9417 new_crtc_state->mode_changed = true;
9421 * Add all primary and overlay planes on the CRTC to the state
9422 * whenever a plane is enabled to maintain correct z-ordering
9423 * and to enable fast surface updates.
9425 drm_for_each_crtc(crtc, dev) {
9426 bool modified = false;
9428 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9429 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9432 if (new_plane_state->crtc == crtc ||
9433 old_plane_state->crtc == crtc) {
9442 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9443 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9447 drm_atomic_get_plane_state(state, plane);
9449 if (IS_ERR(new_plane_state)) {
9450 ret = PTR_ERR(new_plane_state);
9456 /* Remove exiting planes if they are modified */
9457 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9458 ret = dm_update_plane_state(dc, state, plane,
9462 &lock_and_validation_needed);
9467 /* Disable all crtcs which require disable */
9468 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9469 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9473 &lock_and_validation_needed);
9478 /* Enable all crtcs which require enable */
9479 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9480 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9484 &lock_and_validation_needed);
9489 /* Add new/modified planes */
9490 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9491 ret = dm_update_plane_state(dc, state, plane,
9495 &lock_and_validation_needed);
9500 /* Run this here since we want to validate the streams we created */
9501 ret = drm_atomic_helper_check_planes(dev, state);
9505 /* Check cursor planes scaling */
9506 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9507 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9512 if (state->legacy_cursor_update) {
9514 * This is a fast cursor update coming from the plane update
9515 * helper, check if it can be done asynchronously for better
9518 state->async_update =
9519 !drm_atomic_helper_async_check(dev, state);
9522 * Skip the remaining global validation if this is an async
9523 * update. Cursor updates can be done without affecting
9524 * state or bandwidth calcs and this avoids the performance
9525 * penalty of locking the private state object and
9526 * allocating a new dc_state.
9528 if (state->async_update)
9532 /* Check scaling and underscan changes*/
9533 /* TODO Removed scaling changes validation due to inability to commit
9534 * new stream into context w\o causing full reset. Need to
9535 * decide how to handle.
9537 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9538 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9539 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9540 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9542 /* Skip any modesets/resets */
9543 if (!acrtc || drm_atomic_crtc_needs_modeset(
9544 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9547 /* Skip any thing not scale or underscan changes */
9548 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9551 lock_and_validation_needed = true;
9555 * Streams and planes are reset when there are changes that affect
9556 * bandwidth. Anything that affects bandwidth needs to go through
9557 * DC global validation to ensure that the configuration can be applied
9560 * We have to currently stall out here in atomic_check for outstanding
9561 * commits to finish in this case because our IRQ handlers reference
9562 * DRM state directly - we can end up disabling interrupts too early
9565 * TODO: Remove this stall and drop DM state private objects.
9567 if (lock_and_validation_needed) {
9568 ret = dm_atomic_get_state(state, &dm_state);
9572 ret = do_aquire_global_lock(dev, state);
9576 #if defined(CONFIG_DRM_AMD_DC_DCN)
9577 if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
9580 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
9586 * Perform validation of MST topology in the state:
9587 * We need to perform MST atomic check before calling
9588 * dc_validate_global_state(), or there is a chance
9589 * to get stuck in an infinite loop and hang eventually.
9591 ret = drm_dp_mst_atomic_check(state);
9594 status = dc_validate_global_state(dc, dm_state->context, false);
9595 if (status != DC_OK) {
9596 DC_LOG_WARNING("DC global validation failure: %s (%d)",
9597 dc_status_to_str(status), status);
9603 * The commit is a fast update. Fast updates shouldn't change
9604 * the DC context, affect global validation, and can have their
9605 * commit work done in parallel with other commits not touching
9606 * the same resource. If we have a new DC context as part of
9607 * the DM atomic state from validation we need to free it and
9608 * retain the existing one instead.
9610 * Furthermore, since the DM atomic state only contains the DC
9611 * context and can safely be annulled, we can free the state
9612 * and clear the associated private object now to free
9613 * some memory and avoid a possible use-after-free later.
9616 for (i = 0; i < state->num_private_objs; i++) {
9617 struct drm_private_obj *obj = state->private_objs[i].ptr;
9619 if (obj->funcs == adev->dm.atomic_obj.funcs) {
9620 int j = state->num_private_objs-1;
9622 dm_atomic_destroy_state(obj,
9623 state->private_objs[i].state);
9625 /* If i is not at the end of the array then the
9626 * last element needs to be moved to where i was
9627 * before the array can safely be truncated.
9630 state->private_objs[i] =
9631 state->private_objs[j];
9633 state->private_objs[j].ptr = NULL;
9634 state->private_objs[j].state = NULL;
9635 state->private_objs[j].old_state = NULL;
9636 state->private_objs[j].new_state = NULL;
9638 state->num_private_objs = j;
9644 /* Store the overall update type for use later in atomic check. */
9645 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
9646 struct dm_crtc_state *dm_new_crtc_state =
9647 to_dm_crtc_state(new_crtc_state);
9649 dm_new_crtc_state->update_type = lock_and_validation_needed ?
9654 /* Must be success */
9657 trace_amdgpu_dm_atomic_check_finish(state, ret);
9662 if (ret == -EDEADLK)
9663 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
9664 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
9665 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
9667 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
9669 trace_amdgpu_dm_atomic_check_finish(state, ret);
9674 static bool is_dp_capable_without_timing_msa(struct dc *dc,
9675 struct amdgpu_dm_connector *amdgpu_dm_connector)
9678 bool capable = false;
9680 if (amdgpu_dm_connector->dc_link &&
9681 dm_helpers_dp_read_dpcd(
9683 amdgpu_dm_connector->dc_link,
9684 DP_DOWN_STREAM_PORT_COUNT,
9686 sizeof(dpcd_data))) {
9687 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
9692 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
9696 bool edid_check_required;
9697 struct detailed_timing *timing;
9698 struct detailed_non_pixel *data;
9699 struct detailed_data_monitor_range *range;
9700 struct amdgpu_dm_connector *amdgpu_dm_connector =
9701 to_amdgpu_dm_connector(connector);
9702 struct dm_connector_state *dm_con_state = NULL;
9704 struct drm_device *dev = connector->dev;
9705 struct amdgpu_device *adev = drm_to_adev(dev);
9706 bool freesync_capable = false;
9708 if (!connector->state) {
9709 DRM_ERROR("%s - Connector has no state", __func__);
9714 dm_con_state = to_dm_connector_state(connector->state);
9716 amdgpu_dm_connector->min_vfreq = 0;
9717 amdgpu_dm_connector->max_vfreq = 0;
9718 amdgpu_dm_connector->pixel_clock_mhz = 0;
9723 dm_con_state = to_dm_connector_state(connector->state);
9725 edid_check_required = false;
9726 if (!amdgpu_dm_connector->dc_sink) {
9727 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
9730 if (!adev->dm.freesync_module)
9733 * if edid non zero restrict freesync only for dp and edp
9736 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
9737 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
9738 edid_check_required = is_dp_capable_without_timing_msa(
9740 amdgpu_dm_connector);
9743 if (edid_check_required == true && (edid->version > 1 ||
9744 (edid->version == 1 && edid->revision > 1))) {
9745 for (i = 0; i < 4; i++) {
9747 timing = &edid->detailed_timings[i];
9748 data = &timing->data.other_data;
9749 range = &data->data.range;
9751 * Check if monitor has continuous frequency mode
9753 if (data->type != EDID_DETAIL_MONITOR_RANGE)
9756 * Check for flag range limits only. If flag == 1 then
9757 * no additional timing information provided.
9758 * Default GTF, GTF Secondary curve and CVT are not
9761 if (range->flags != 1)
9764 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
9765 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
9766 amdgpu_dm_connector->pixel_clock_mhz =
9767 range->pixel_clock_mhz * 10;
9769 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
9770 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
9775 if (amdgpu_dm_connector->max_vfreq -
9776 amdgpu_dm_connector->min_vfreq > 10) {
9778 freesync_capable = true;
9784 dm_con_state->freesync_capable = freesync_capable;
9786 if (connector->vrr_capable_property)
9787 drm_connector_set_vrr_capable_property(connector,
9791 static void amdgpu_dm_set_psr_caps(struct dc_link *link)
9793 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
9795 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
9797 if (link->type == dc_connection_none)
9799 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
9800 dpcd_data, sizeof(dpcd_data))) {
9801 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
9803 if (dpcd_data[0] == 0) {
9804 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
9805 link->psr_settings.psr_feature_enabled = false;
9807 link->psr_settings.psr_version = DC_PSR_VERSION_1;
9808 link->psr_settings.psr_feature_enabled = true;
9811 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
9816 * amdgpu_dm_link_setup_psr() - configure psr link
9817 * @stream: stream state
9819 * Return: true if success
9821 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
9823 struct dc_link *link = NULL;
9824 struct psr_config psr_config = {0};
9825 struct psr_context psr_context = {0};
9831 link = stream->link;
9833 psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
9835 if (psr_config.psr_version > 0) {
9836 psr_config.psr_exit_link_training_required = 0x1;
9837 psr_config.psr_frame_capture_indication_req = 0;
9838 psr_config.psr_rfb_setup_time = 0x37;
9839 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
9840 psr_config.allow_smu_optimizations = 0x0;
9842 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
9845 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
9851 * amdgpu_dm_psr_enable() - enable psr f/w
9852 * @stream: stream state
9854 * Return: true if success
9856 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
9858 struct dc_link *link = stream->link;
9859 unsigned int vsync_rate_hz = 0;
9860 struct dc_static_screen_params params = {0};
9861 /* Calculate number of static frames before generating interrupt to
9864 // Init fail safe of 2 frames static
9865 unsigned int num_frames_static = 2;
9867 DRM_DEBUG_DRIVER("Enabling psr...\n");
9869 vsync_rate_hz = div64_u64(div64_u64((
9870 stream->timing.pix_clk_100hz * 100),
9871 stream->timing.v_total),
9872 stream->timing.h_total);
9875 * Calculate number of frames such that at least 30 ms of time has
9878 if (vsync_rate_hz != 0) {
9879 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
9880 num_frames_static = (30000 / frame_time_microsec) + 1;
9883 params.triggers.cursor_update = true;
9884 params.triggers.overlay_update = true;
9885 params.triggers.surface_update = true;
9886 params.num_frames = num_frames_static;
9888 dc_stream_set_static_screen_params(link->ctx->dc,
9892 return dc_link_set_psr_allow_active(link, true, false, false);
9896 * amdgpu_dm_psr_disable() - disable psr f/w
9897 * @stream: stream state
9899 * Return: true if success
9901 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
9904 DRM_DEBUG_DRIVER("Disabling psr...\n");
9906 return dc_link_set_psr_allow_active(stream->link, false, true, false);
9910 * amdgpu_dm_psr_disable() - disable psr f/w
9911 * if psr is enabled on any stream
9913 * Return: true if success
9915 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
9917 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
9918 return dc_set_psr_allow_active(dm->dc, false);
9921 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
9923 struct amdgpu_device *adev = drm_to_adev(dev);
9924 struct dc *dc = adev->dm.dc;
9927 mutex_lock(&adev->dm.dc_lock);
9928 if (dc->current_state) {
9929 for (i = 0; i < dc->current_state->stream_count; ++i)
9930 dc->current_state->streams[i]
9931 ->triggered_crtc_reset.enabled =
9932 adev->dm.force_timing_sync;
9934 dm_enable_per_frame_crtc_master_sync(dc->current_state);
9935 dc_trigger_sync(dc, dc->current_state);
9937 mutex_unlock(&adev->dm.dc_lock);
9940 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
9941 uint32_t value, const char *func_name)
9943 #ifdef DM_CHECK_ADDR_0
9945 DC_ERR("invalid register write. address = 0");
9949 cgs_write_register(ctx->cgs_device, address, value);
9950 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
9953 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
9954 const char *func_name)
9957 #ifdef DM_CHECK_ADDR_0
9959 DC_ERR("invalid register read; address = 0\n");
9964 if (ctx->dmub_srv &&
9965 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
9966 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
9971 value = cgs_read_register(ctx->cgs_device, address);
9973 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);