2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
44 #include "link/protocols/link_dp_capability.h"
45 #include "link/protocols/link_ddc.h"
49 #include "amdgpu_display.h"
50 #include "amdgpu_ucode.h"
52 #include "amdgpu_dm.h"
53 #include "amdgpu_dm_plane.h"
54 #include "amdgpu_dm_crtc.h"
55 #include "amdgpu_dm_hdcp.h"
56 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
67 #include "amdgpu_dm_psr.h"
68 #include "amdgpu_dm_replay.h"
70 #include "ivsrcid/ivsrcid_vislands30.h"
72 #include <linux/backlight.h>
73 #include <linux/module.h>
74 #include <linux/moduleparam.h>
75 #include <linux/types.h>
76 #include <linux/pm_runtime.h>
77 #include <linux/pci.h>
78 #include <linux/firmware.h>
79 #include <linux/component.h>
80 #include <linux/dmi.h>
82 #include <drm/display/drm_dp_mst_helper.h>
83 #include <drm/display/drm_hdmi_helper.h>
84 #include <drm/drm_atomic.h>
85 #include <drm/drm_atomic_uapi.h>
86 #include <drm/drm_atomic_helper.h>
87 #include <drm/drm_blend.h>
88 #include <drm/drm_fourcc.h>
89 #include <drm/drm_edid.h>
90 #include <drm/drm_vblank.h>
91 #include <drm/drm_audio_component.h>
92 #include <drm/drm_gem_atomic_helper.h>
93 #include <drm/drm_plane_helper.h>
95 #include <acpi/video.h>
97 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
99 #include "dcn/dcn_1_0_offset.h"
100 #include "dcn/dcn_1_0_sh_mask.h"
101 #include "soc15_hw_ip.h"
102 #include "soc15_common.h"
103 #include "vega10_ip_offset.h"
105 #include "gc/gc_11_0_0_offset.h"
106 #include "gc/gc_11_0_0_sh_mask.h"
108 #include "modules/inc/mod_freesync.h"
109 #include "modules/power/power_helpers.h"
111 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
112 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
113 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
114 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
115 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
116 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
117 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
118 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
119 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
120 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
121 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
122 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
123 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
124 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
125 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
126 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
127 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
128 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
129 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
130 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
131 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
132 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
134 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
136 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
139 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
140 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
142 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
143 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
145 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
146 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
148 /* Number of bytes in PSP header for firmware. */
149 #define PSP_HEADER_BYTES 0x100
151 /* Number of bytes in PSP footer for firmware. */
152 #define PSP_FOOTER_BYTES 0x100
157 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
158 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
159 * requests into DC requests, and DC responses into DRM responses.
161 * The root control structure is &struct amdgpu_display_manager.
164 /* basic init/fini API */
165 static int amdgpu_dm_init(struct amdgpu_device *adev);
166 static void amdgpu_dm_fini(struct amdgpu_device *adev);
167 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
169 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
171 switch (link->dpcd_caps.dongle_type) {
172 case DISPLAY_DONGLE_NONE:
173 return DRM_MODE_SUBCONNECTOR_Native;
174 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
175 return DRM_MODE_SUBCONNECTOR_VGA;
176 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
177 case DISPLAY_DONGLE_DP_DVI_DONGLE:
178 return DRM_MODE_SUBCONNECTOR_DVID;
179 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
180 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
181 return DRM_MODE_SUBCONNECTOR_HDMIA;
182 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
184 return DRM_MODE_SUBCONNECTOR_Unknown;
188 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
190 struct dc_link *link = aconnector->dc_link;
191 struct drm_connector *connector = &aconnector->base;
192 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
194 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
197 if (aconnector->dc_sink)
198 subconnector = get_subconnector_type(link);
200 drm_object_property_set_value(&connector->base,
201 connector->dev->mode_config.dp_subconnector_property,
206 * initializes drm_device display related structures, based on the information
207 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
208 * drm_encoder, drm_mode_config
210 * Returns 0 on success
212 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
213 /* removes and deallocates the drm structures, created by the above function */
214 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
216 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
217 struct amdgpu_dm_connector *amdgpu_dm_connector,
219 struct amdgpu_encoder *amdgpu_encoder);
220 static int amdgpu_dm_encoder_init(struct drm_device *dev,
221 struct amdgpu_encoder *aencoder,
222 uint32_t link_index);
224 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
226 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
228 static int amdgpu_dm_atomic_check(struct drm_device *dev,
229 struct drm_atomic_state *state);
231 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
232 static void handle_hpd_rx_irq(void *param);
235 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
236 struct drm_crtc_state *new_crtc_state);
238 * dm_vblank_get_counter
241 * Get counter for number of vertical blanks
244 * struct amdgpu_device *adev - [in] desired amdgpu device
245 * int disp_idx - [in] which CRTC to get the counter from
248 * Counter for vertical blanks
250 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
252 struct amdgpu_crtc *acrtc = NULL;
254 if (crtc >= adev->mode_info.num_crtc)
257 acrtc = adev->mode_info.crtcs[crtc];
259 if (!acrtc->dm_irq_params.stream) {
260 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
265 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
268 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
269 u32 *vbl, u32 *position)
271 u32 v_blank_start, v_blank_end, h_position, v_position;
272 struct amdgpu_crtc *acrtc = NULL;
274 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
277 acrtc = adev->mode_info.crtcs[crtc];
279 if (!acrtc->dm_irq_params.stream) {
280 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
286 * TODO rework base driver to use values directly.
287 * for now parse it back into reg-format
289 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
295 *position = v_position | (h_position << 16);
296 *vbl = v_blank_start | (v_blank_end << 16);
301 static bool dm_is_idle(void *handle)
307 static int dm_wait_for_idle(void *handle)
313 static bool dm_check_soft_reset(void *handle)
318 static int dm_soft_reset(void *handle)
324 static struct amdgpu_crtc *
325 get_crtc_by_otg_inst(struct amdgpu_device *adev,
328 struct drm_device *dev = adev_to_drm(adev);
329 struct drm_crtc *crtc;
330 struct amdgpu_crtc *amdgpu_crtc;
332 if (WARN_ON(otg_inst == -1))
333 return adev->mode_info.crtcs[0];
335 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
336 amdgpu_crtc = to_amdgpu_crtc(crtc);
338 if (amdgpu_crtc->otg_inst == otg_inst)
345 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
346 struct dm_crtc_state *new_state)
348 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
350 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
356 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
361 for (i = 0, j = planes_count - 1; i < j; i++, j--)
362 swap(array_of_surface_update[i], array_of_surface_update[j]);
366 * update_planes_and_stream_adapter() - Send planes to be updated in DC
368 * DC has a generic way to update planes and stream via
369 * dc_update_planes_and_stream function; however, DM might need some
370 * adjustments and preparation before calling it. This function is a wrapper
371 * for the dc_update_planes_and_stream that does any required configuration
372 * before passing control to DC.
374 * @dc: Display Core control structure
375 * @update_type: specify whether it is FULL/MEDIUM/FAST update
376 * @planes_count: planes count to update
377 * @stream: stream state
378 * @stream_update: stream update
379 * @array_of_surface_update: dc surface update pointer
382 static inline bool update_planes_and_stream_adapter(struct dc *dc,
385 struct dc_stream_state *stream,
386 struct dc_stream_update *stream_update,
387 struct dc_surface_update *array_of_surface_update)
389 reverse_planes_order(array_of_surface_update, planes_count);
392 * Previous frame finished and HW is ready for optimization.
394 if (update_type == UPDATE_TYPE_FAST)
395 dc_post_update_surfaces_to_stream(dc);
397 return dc_update_planes_and_stream(dc,
398 array_of_surface_update,
405 * dm_pflip_high_irq() - Handle pageflip interrupt
406 * @interrupt_params: ignored
408 * Handles the pageflip interrupt by notifying all interested parties
409 * that the pageflip has been completed.
411 static void dm_pflip_high_irq(void *interrupt_params)
413 struct amdgpu_crtc *amdgpu_crtc;
414 struct common_irq_params *irq_params = interrupt_params;
415 struct amdgpu_device *adev = irq_params->adev;
416 struct drm_device *dev = adev_to_drm(adev);
418 struct drm_pending_vblank_event *e;
419 u32 vpos, hpos, v_blank_start, v_blank_end;
422 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
424 /* IRQ could occur when in initial stage */
425 /* TODO work and BO cleanup */
426 if (amdgpu_crtc == NULL) {
427 drm_dbg_state(dev, "CRTC is null, returning.\n");
431 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
433 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
435 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
436 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
437 amdgpu_crtc->crtc_id, amdgpu_crtc);
438 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
442 /* page flip completed. */
443 e = amdgpu_crtc->event;
444 amdgpu_crtc->event = NULL;
448 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
450 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
452 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
453 &v_blank_end, &hpos, &vpos) ||
454 (vpos < v_blank_start)) {
455 /* Update to correct count and vblank timestamp if racing with
456 * vblank irq. This also updates to the correct vblank timestamp
457 * even in VRR mode, as scanout is past the front-porch atm.
459 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
461 /* Wake up userspace by sending the pageflip event with proper
462 * count and timestamp of vblank of flip completion.
465 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
467 /* Event sent, so done with vblank for this flip */
468 drm_crtc_vblank_put(&amdgpu_crtc->base);
471 /* VRR active and inside front-porch: vblank count and
472 * timestamp for pageflip event will only be up to date after
473 * drm_crtc_handle_vblank() has been executed from late vblank
474 * irq handler after start of back-porch (vline 0). We queue the
475 * pageflip event for send-out by drm_crtc_handle_vblank() with
476 * updated timestamp and count, once it runs after us.
478 * We need to open-code this instead of using the helper
479 * drm_crtc_arm_vblank_event(), as that helper would
480 * call drm_crtc_accurate_vblank_count(), which we must
481 * not call in VRR mode while we are in front-porch!
484 /* sequence will be replaced by real count during send-out. */
485 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
486 e->pipe = amdgpu_crtc->crtc_id;
488 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
492 /* Keep track of vblank of this flip for flip throttling. We use the
493 * cooked hw counter, as that one incremented at start of this vblank
494 * of pageflip completion, so last_flip_vblank is the forbidden count
495 * for queueing new pageflips if vsync + VRR is enabled.
497 amdgpu_crtc->dm_irq_params.last_flip_vblank =
498 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
500 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
501 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
504 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
505 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
508 static void dm_vupdate_high_irq(void *interrupt_params)
510 struct common_irq_params *irq_params = interrupt_params;
511 struct amdgpu_device *adev = irq_params->adev;
512 struct amdgpu_crtc *acrtc;
513 struct drm_device *drm_dev;
514 struct drm_vblank_crtc *vblank;
515 ktime_t frame_duration_ns, previous_timestamp;
519 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
522 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
523 drm_dev = acrtc->base.dev;
524 vblank = &drm_dev->vblank[acrtc->base.index];
525 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
526 frame_duration_ns = vblank->time - previous_timestamp;
528 if (frame_duration_ns > 0) {
529 trace_amdgpu_refresh_rate_track(acrtc->base.index,
531 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
532 atomic64_set(&irq_params->previous_timestamp, vblank->time);
536 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
539 /* Core vblank handling is done here after end of front-porch in
540 * vrr mode, as vblank timestamping will give valid results
541 * while now done after front-porch. This will also deliver
542 * page-flip completion events that have been queued to us
543 * if a pageflip happened inside front-porch.
546 amdgpu_dm_crtc_handle_vblank(acrtc);
548 /* BTR processing for pre-DCE12 ASICs */
549 if (acrtc->dm_irq_params.stream &&
550 adev->family < AMDGPU_FAMILY_AI) {
551 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
552 mod_freesync_handle_v_update(
553 adev->dm.freesync_module,
554 acrtc->dm_irq_params.stream,
555 &acrtc->dm_irq_params.vrr_params);
557 dc_stream_adjust_vmin_vmax(
559 acrtc->dm_irq_params.stream,
560 &acrtc->dm_irq_params.vrr_params.adjust);
561 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
568 * dm_crtc_high_irq() - Handles CRTC interrupt
569 * @interrupt_params: used for determining the CRTC instance
571 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
574 static void dm_crtc_high_irq(void *interrupt_params)
576 struct common_irq_params *irq_params = interrupt_params;
577 struct amdgpu_device *adev = irq_params->adev;
578 struct amdgpu_crtc *acrtc;
582 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
586 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
588 drm_dbg_vbl(adev_to_drm(adev),
589 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
590 vrr_active, acrtc->dm_irq_params.active_planes);
593 * Core vblank handling at start of front-porch is only possible
594 * in non-vrr mode, as only there vblank timestamping will give
595 * valid results while done in front-porch. Otherwise defer it
596 * to dm_vupdate_high_irq after end of front-porch.
599 amdgpu_dm_crtc_handle_vblank(acrtc);
602 * Following stuff must happen at start of vblank, for crc
603 * computation and below-the-range btr support in vrr mode.
605 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
607 /* BTR updates need to happen before VUPDATE on Vega and above. */
608 if (adev->family < AMDGPU_FAMILY_AI)
611 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
613 if (acrtc->dm_irq_params.stream &&
614 acrtc->dm_irq_params.vrr_params.supported &&
615 acrtc->dm_irq_params.freesync_config.state ==
616 VRR_STATE_ACTIVE_VARIABLE) {
617 mod_freesync_handle_v_update(adev->dm.freesync_module,
618 acrtc->dm_irq_params.stream,
619 &acrtc->dm_irq_params.vrr_params);
621 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
622 &acrtc->dm_irq_params.vrr_params.adjust);
626 * If there aren't any active_planes then DCH HUBP may be clock-gated.
627 * In that case, pageflip completion interrupts won't fire and pageflip
628 * completion events won't get delivered. Prevent this by sending
629 * pending pageflip events from here if a flip is still pending.
631 * If any planes are enabled, use dm_pflip_high_irq() instead, to
632 * avoid race conditions between flip programming and completion,
633 * which could cause too early flip completion events.
635 if (adev->family >= AMDGPU_FAMILY_RV &&
636 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
637 acrtc->dm_irq_params.active_planes == 0) {
639 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
641 drm_crtc_vblank_put(&acrtc->base);
643 acrtc->pflip_status = AMDGPU_FLIP_NONE;
646 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
649 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
651 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
652 * DCN generation ASICs
653 * @interrupt_params: interrupt parameters
655 * Used to set crc window/read out crc value at vertical line 0 position
657 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
659 struct common_irq_params *irq_params = interrupt_params;
660 struct amdgpu_device *adev = irq_params->adev;
661 struct amdgpu_crtc *acrtc;
663 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
668 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
670 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
673 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
674 * @adev: amdgpu_device pointer
675 * @notify: dmub notification structure
677 * Dmub AUX or SET_CONFIG command completion processing callback
678 * Copies dmub notification to DM which is to be read by AUX command.
679 * issuing thread and also signals the event to wake up the thread.
681 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
682 struct dmub_notification *notify)
684 if (adev->dm.dmub_notify)
685 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
686 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
687 complete(&adev->dm.dmub_aux_transfer_done);
691 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
692 * @adev: amdgpu_device pointer
693 * @notify: dmub notification structure
695 * Dmub Hpd interrupt processing callback. Gets displayindex through the
696 * ink index and calls helper to do the processing.
698 static void dmub_hpd_callback(struct amdgpu_device *adev,
699 struct dmub_notification *notify)
701 struct amdgpu_dm_connector *aconnector;
702 struct amdgpu_dm_connector *hpd_aconnector = NULL;
703 struct drm_connector *connector;
704 struct drm_connector_list_iter iter;
705 struct dc_link *link;
707 struct drm_device *dev;
712 if (notify == NULL) {
713 DRM_ERROR("DMUB HPD callback notification was NULL");
717 if (notify->link_index > adev->dm.dc->link_count) {
718 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
722 link_index = notify->link_index;
723 link = adev->dm.dc->links[link_index];
726 drm_connector_list_iter_begin(dev, &iter);
727 drm_for_each_connector_iter(connector, &iter) {
728 aconnector = to_amdgpu_dm_connector(connector);
729 if (link && aconnector->dc_link == link) {
730 if (notify->type == DMUB_NOTIFICATION_HPD)
731 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
732 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
733 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
735 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
736 notify->type, link_index);
738 hpd_aconnector = aconnector;
742 drm_connector_list_iter_end(&iter);
744 if (hpd_aconnector) {
745 if (notify->type == DMUB_NOTIFICATION_HPD)
746 handle_hpd_irq_helper(hpd_aconnector);
747 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
748 handle_hpd_rx_irq(hpd_aconnector);
753 * register_dmub_notify_callback - Sets callback for DMUB notify
754 * @adev: amdgpu_device pointer
755 * @type: Type of dmub notification
756 * @callback: Dmub interrupt callback function
757 * @dmub_int_thread_offload: offload indicator
759 * API to register a dmub callback handler for a dmub notification
760 * Also sets indicator whether callback processing to be offloaded.
761 * to dmub interrupt handling thread
762 * Return: true if successfully registered, false if there is existing registration
764 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
765 enum dmub_notification_type type,
766 dmub_notify_interrupt_callback_t callback,
767 bool dmub_int_thread_offload)
769 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
770 adev->dm.dmub_callback[type] = callback;
771 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
778 static void dm_handle_hpd_work(struct work_struct *work)
780 struct dmub_hpd_work *dmub_hpd_wrk;
782 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
784 if (!dmub_hpd_wrk->dmub_notify) {
785 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
789 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
790 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
791 dmub_hpd_wrk->dmub_notify);
794 kfree(dmub_hpd_wrk->dmub_notify);
799 #define DMUB_TRACE_MAX_READ 64
801 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
802 * @interrupt_params: used for determining the Outbox instance
804 * Handles the Outbox Interrupt
807 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
809 struct dmub_notification notify;
810 struct common_irq_params *irq_params = interrupt_params;
811 struct amdgpu_device *adev = irq_params->adev;
812 struct amdgpu_display_manager *dm = &adev->dm;
813 struct dmcub_trace_buf_entry entry = { 0 };
815 struct dmub_hpd_work *dmub_hpd_wrk;
816 struct dc_link *plink = NULL;
818 if (dc_enable_dmub_notifications(adev->dm.dc) &&
819 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
822 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
823 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
824 DRM_ERROR("DM: notify type %d invalid!", notify.type);
827 if (!dm->dmub_callback[notify.type]) {
828 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
831 if (dm->dmub_thread_offload[notify.type] == true) {
832 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
834 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
837 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification),
839 if (!dmub_hpd_wrk->dmub_notify) {
841 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
844 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
845 dmub_hpd_wrk->adev = adev;
846 if (notify.type == DMUB_NOTIFICATION_HPD) {
847 plink = adev->dm.dc->links[notify.link_index];
850 notify.hpd_status == DP_HPD_PLUG;
853 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
855 dm->dmub_callback[notify.type](adev, ¬ify);
857 } while (notify.pending_notification);
862 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
863 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
864 entry.param0, entry.param1);
866 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
867 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
873 } while (count <= DMUB_TRACE_MAX_READ);
875 if (count > DMUB_TRACE_MAX_READ)
876 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
879 static int dm_set_clockgating_state(void *handle,
880 enum amd_clockgating_state state)
885 static int dm_set_powergating_state(void *handle,
886 enum amd_powergating_state state)
891 /* Prototypes of private functions */
892 static int dm_early_init(void *handle);
894 /* Allocate memory for FBC compressed data */
895 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
897 struct drm_device *dev = connector->dev;
898 struct amdgpu_device *adev = drm_to_adev(dev);
899 struct dm_compressor_info *compressor = &adev->dm.compressor;
900 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
901 struct drm_display_mode *mode;
902 unsigned long max_size = 0;
904 if (adev->dm.dc->fbc_compressor == NULL)
907 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
910 if (compressor->bo_ptr)
914 list_for_each_entry(mode, &connector->modes, head) {
915 if (max_size < mode->htotal * mode->vtotal)
916 max_size = mode->htotal * mode->vtotal;
920 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
921 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
922 &compressor->gpu_addr, &compressor->cpu_addr);
925 DRM_ERROR("DM: Failed to initialize FBC\n");
927 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
928 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
935 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
936 int pipe, bool *enabled,
937 unsigned char *buf, int max_bytes)
939 struct drm_device *dev = dev_get_drvdata(kdev);
940 struct amdgpu_device *adev = drm_to_adev(dev);
941 struct drm_connector *connector;
942 struct drm_connector_list_iter conn_iter;
943 struct amdgpu_dm_connector *aconnector;
948 mutex_lock(&adev->dm.audio_lock);
950 drm_connector_list_iter_begin(dev, &conn_iter);
951 drm_for_each_connector_iter(connector, &conn_iter) {
952 aconnector = to_amdgpu_dm_connector(connector);
953 if (aconnector->audio_inst != port)
957 ret = drm_eld_size(connector->eld);
958 memcpy(buf, connector->eld, min(max_bytes, ret));
962 drm_connector_list_iter_end(&conn_iter);
964 mutex_unlock(&adev->dm.audio_lock);
966 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
971 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
972 .get_eld = amdgpu_dm_audio_component_get_eld,
975 static int amdgpu_dm_audio_component_bind(struct device *kdev,
976 struct device *hda_kdev, void *data)
978 struct drm_device *dev = dev_get_drvdata(kdev);
979 struct amdgpu_device *adev = drm_to_adev(dev);
980 struct drm_audio_component *acomp = data;
982 acomp->ops = &amdgpu_dm_audio_component_ops;
984 adev->dm.audio_component = acomp;
989 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
990 struct device *hda_kdev, void *data)
992 struct drm_device *dev = dev_get_drvdata(kdev);
993 struct amdgpu_device *adev = drm_to_adev(dev);
994 struct drm_audio_component *acomp = data;
998 adev->dm.audio_component = NULL;
1001 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1002 .bind = amdgpu_dm_audio_component_bind,
1003 .unbind = amdgpu_dm_audio_component_unbind,
1006 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1013 adev->mode_info.audio.enabled = true;
1015 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1017 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1018 adev->mode_info.audio.pin[i].channels = -1;
1019 adev->mode_info.audio.pin[i].rate = -1;
1020 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1021 adev->mode_info.audio.pin[i].status_bits = 0;
1022 adev->mode_info.audio.pin[i].category_code = 0;
1023 adev->mode_info.audio.pin[i].connected = false;
1024 adev->mode_info.audio.pin[i].id =
1025 adev->dm.dc->res_pool->audios[i]->inst;
1026 adev->mode_info.audio.pin[i].offset = 0;
1029 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1033 adev->dm.audio_registered = true;
1038 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1043 if (!adev->mode_info.audio.enabled)
1046 if (adev->dm.audio_registered) {
1047 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1048 adev->dm.audio_registered = false;
1051 /* TODO: Disable audio? */
1053 adev->mode_info.audio.enabled = false;
1056 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1058 struct drm_audio_component *acomp = adev->dm.audio_component;
1060 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1061 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1063 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1068 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1070 const struct dmcub_firmware_header_v1_0 *hdr;
1071 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1072 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1073 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1074 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1075 struct abm *abm = adev->dm.dc->res_pool->abm;
1076 struct dc_context *ctx = adev->dm.dc->ctx;
1077 struct dmub_srv_hw_params hw_params;
1078 enum dmub_status status;
1079 const unsigned char *fw_inst_const, *fw_bss_data;
1080 u32 i, fw_inst_const_size, fw_bss_data_size;
1081 bool has_hw_support;
1084 /* DMUB isn't supported on the ASIC. */
1088 DRM_ERROR("No framebuffer info for DMUB service.\n");
1093 /* Firmware required for DMUB support. */
1094 DRM_ERROR("No firmware provided for DMUB.\n");
1098 /* initialize register offsets for ASICs with runtime initialization available */
1099 if (dmub_srv->hw_funcs.init_reg_offsets)
1100 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1102 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1103 if (status != DMUB_STATUS_OK) {
1104 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1108 if (!has_hw_support) {
1109 DRM_INFO("DMUB unsupported on ASIC\n");
1113 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1114 status = dmub_srv_hw_reset(dmub_srv);
1115 if (status != DMUB_STATUS_OK)
1116 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1118 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1120 fw_inst_const = dmub_fw->data +
1121 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1124 fw_bss_data = dmub_fw->data +
1125 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1126 le32_to_cpu(hdr->inst_const_bytes);
1128 /* Copy firmware and bios info into FB memory. */
1129 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1130 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1132 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1134 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1135 * amdgpu_ucode_init_single_fw will load dmub firmware
1136 * fw_inst_const part to cw0; otherwise, the firmware back door load
1137 * will be done by dm_dmub_hw_init
1139 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1140 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1141 fw_inst_const_size);
1144 if (fw_bss_data_size)
1145 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1146 fw_bss_data, fw_bss_data_size);
1148 /* Copy firmware bios info into FB memory. */
1149 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1152 /* Reset regions that need to be reset. */
1153 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1154 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1156 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1157 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1159 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1160 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1162 /* Initialize hardware. */
1163 memset(&hw_params, 0, sizeof(hw_params));
1164 hw_params.fb_base = adev->gmc.fb_start;
1165 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1167 /* backdoor load firmware and trigger dmub running */
1168 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1169 hw_params.load_inst_const = true;
1172 hw_params.psp_version = dmcu->psp_version;
1174 for (i = 0; i < fb_info->num_fb; ++i)
1175 hw_params.fb[i] = &fb_info->fb[i];
1177 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1178 case IP_VERSION(3, 1, 3):
1179 case IP_VERSION(3, 1, 4):
1180 case IP_VERSION(3, 5, 0):
1181 hw_params.dpia_supported = true;
1182 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1188 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1189 if (status != DMUB_STATUS_OK) {
1190 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1194 /* Wait for firmware load to finish. */
1195 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1196 if (status != DMUB_STATUS_OK)
1197 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1199 /* Init DMCU and ABM if available. */
1201 dmcu->funcs->dmcu_init(dmcu);
1202 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1205 if (!adev->dm.dc->ctx->dmub_srv)
1206 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1207 if (!adev->dm.dc->ctx->dmub_srv) {
1208 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1212 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1213 adev->dm.dmcub_fw_version);
1218 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1220 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1221 enum dmub_status status;
1225 /* DMUB isn't supported on the ASIC. */
1229 status = dmub_srv_is_hw_init(dmub_srv, &init);
1230 if (status != DMUB_STATUS_OK)
1231 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1233 if (status == DMUB_STATUS_OK && init) {
1234 /* Wait for firmware load to finish. */
1235 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1236 if (status != DMUB_STATUS_OK)
1237 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1239 /* Perform the full hardware initialization. */
1240 dm_dmub_hw_init(adev);
1244 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1247 u32 logical_addr_low;
1248 u32 logical_addr_high;
1249 u32 agp_base, agp_bot, agp_top;
1250 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1252 memset(pa_config, 0, sizeof(*pa_config));
1255 agp_bot = adev->gmc.agp_start >> 24;
1256 agp_top = adev->gmc.agp_end >> 24;
1258 /* AGP aperture is disabled */
1259 if (agp_bot > agp_top) {
1260 logical_addr_low = adev->gmc.fb_start >> 18;
1261 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1263 * Raven2 has a HW issue that it is unable to use the vram which
1264 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1265 * workaround that increase system aperture high address (add 1)
1266 * to get rid of the VM fault and hardware hang.
1268 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1270 logical_addr_high = adev->gmc.fb_end >> 18;
1272 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1273 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1275 * Raven2 has a HW issue that it is unable to use the vram which
1276 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1277 * workaround that increase system aperture high address (add 1)
1278 * to get rid of the VM fault and hardware hang.
1280 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1282 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1285 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1287 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1288 AMDGPU_GPU_PAGE_SHIFT);
1289 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1290 AMDGPU_GPU_PAGE_SHIFT);
1291 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1292 AMDGPU_GPU_PAGE_SHIFT);
1293 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1294 AMDGPU_GPU_PAGE_SHIFT);
1295 page_table_base.high_part = upper_32_bits(pt_base);
1296 page_table_base.low_part = lower_32_bits(pt_base);
1298 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1299 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1301 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1302 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1303 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1305 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1306 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1307 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1309 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1310 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1311 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1313 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1317 static void force_connector_state(
1318 struct amdgpu_dm_connector *aconnector,
1319 enum drm_connector_force force_state)
1321 struct drm_connector *connector = &aconnector->base;
1323 mutex_lock(&connector->dev->mode_config.mutex);
1324 aconnector->base.force = force_state;
1325 mutex_unlock(&connector->dev->mode_config.mutex);
1327 mutex_lock(&aconnector->hpd_lock);
1328 drm_kms_helper_connector_hotplug_event(connector);
1329 mutex_unlock(&aconnector->hpd_lock);
1332 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1334 struct hpd_rx_irq_offload_work *offload_work;
1335 struct amdgpu_dm_connector *aconnector;
1336 struct dc_link *dc_link;
1337 struct amdgpu_device *adev;
1338 enum dc_connection_type new_connection_type = dc_connection_none;
1339 unsigned long flags;
1340 union test_response test_response;
1342 memset(&test_response, 0, sizeof(test_response));
1344 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1345 aconnector = offload_work->offload_wq->aconnector;
1348 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1352 adev = drm_to_adev(aconnector->base.dev);
1353 dc_link = aconnector->dc_link;
1355 mutex_lock(&aconnector->hpd_lock);
1356 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1357 DRM_ERROR("KMS: Failed to detect connector\n");
1358 mutex_unlock(&aconnector->hpd_lock);
1360 if (new_connection_type == dc_connection_none)
1363 if (amdgpu_in_reset(adev))
1366 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1367 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1368 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1369 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1370 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1371 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1375 mutex_lock(&adev->dm.dc_lock);
1376 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1377 dc_link_dp_handle_automated_test(dc_link);
1379 if (aconnector->timing_changed) {
1380 /* force connector disconnect and reconnect */
1381 force_connector_state(aconnector, DRM_FORCE_OFF);
1383 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1386 test_response.bits.ACK = 1;
1388 core_link_write_dpcd(
1392 sizeof(test_response));
1393 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1394 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1395 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1396 /* offload_work->data is from handle_hpd_rx_irq->
1397 * schedule_hpd_rx_offload_work.this is defer handle
1398 * for hpd short pulse. upon here, link status may be
1399 * changed, need get latest link status from dpcd
1400 * registers. if link status is good, skip run link
1403 union hpd_irq_data irq_data;
1405 memset(&irq_data, 0, sizeof(irq_data));
1407 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1408 * request be added to work queue if link lost at end of dc_link_
1409 * dp_handle_link_loss
1411 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1412 offload_work->offload_wq->is_handling_link_loss = false;
1413 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1415 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1416 dc_link_check_link_loss_status(dc_link, &irq_data))
1417 dc_link_dp_handle_link_loss(dc_link);
1419 mutex_unlock(&adev->dm.dc_lock);
1422 kfree(offload_work);
1426 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1428 int max_caps = dc->caps.max_links;
1430 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1432 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1434 if (!hpd_rx_offload_wq)
1438 for (i = 0; i < max_caps; i++) {
1439 hpd_rx_offload_wq[i].wq =
1440 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1442 if (hpd_rx_offload_wq[i].wq == NULL) {
1443 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1447 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1450 return hpd_rx_offload_wq;
1453 for (i = 0; i < max_caps; i++) {
1454 if (hpd_rx_offload_wq[i].wq)
1455 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1457 kfree(hpd_rx_offload_wq);
1461 struct amdgpu_stutter_quirk {
1469 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1470 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1471 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1475 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1477 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1479 while (p && p->chip_device != 0) {
1480 if (pdev->vendor == p->chip_vendor &&
1481 pdev->device == p->chip_device &&
1482 pdev->subsystem_vendor == p->subsys_vendor &&
1483 pdev->subsystem_device == p->subsys_device &&
1484 pdev->revision == p->revision) {
1492 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1495 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1496 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1501 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1502 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1507 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1508 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1513 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1514 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1519 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1520 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1525 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1526 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1531 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1532 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1537 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1538 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1543 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1544 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1548 /* TODO: refactor this from a fixed table to a dynamic option */
1551 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1553 const struct dmi_system_id *dmi_id;
1555 dm->aux_hpd_discon_quirk = false;
1557 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1559 dm->aux_hpd_discon_quirk = true;
1560 DRM_INFO("aux_hpd_discon_quirk attached\n");
1564 static int amdgpu_dm_init(struct amdgpu_device *adev)
1566 struct dc_init_data init_data;
1567 struct dc_callback_init init_params;
1570 adev->dm.ddev = adev_to_drm(adev);
1571 adev->dm.adev = adev;
1573 /* Zero all the fields */
1574 memset(&init_data, 0, sizeof(init_data));
1575 memset(&init_params, 0, sizeof(init_params));
1577 mutex_init(&adev->dm.dpia_aux_lock);
1578 mutex_init(&adev->dm.dc_lock);
1579 mutex_init(&adev->dm.audio_lock);
1581 if (amdgpu_dm_irq_init(adev)) {
1582 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1586 init_data.asic_id.chip_family = adev->family;
1588 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1589 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1590 init_data.asic_id.chip_id = adev->pdev->device;
1592 init_data.asic_id.vram_width = adev->gmc.vram_width;
1593 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1594 init_data.asic_id.atombios_base_address =
1595 adev->mode_info.atom_context->bios;
1597 init_data.driver = adev;
1599 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1601 if (!adev->dm.cgs_device) {
1602 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1606 init_data.cgs_device = adev->dm.cgs_device;
1608 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1610 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1611 case IP_VERSION(2, 1, 0):
1612 switch (adev->dm.dmcub_fw_version) {
1613 case 0: /* development */
1614 case 0x1: /* linux-firmware.git hash 6d9f399 */
1615 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1616 init_data.flags.disable_dmcu = false;
1619 init_data.flags.disable_dmcu = true;
1622 case IP_VERSION(2, 0, 3):
1623 init_data.flags.disable_dmcu = true;
1629 /* APU support S/G display by default except:
1630 * ASICs before Carrizo,
1631 * RAVEN1 (Users reported stability issue)
1634 if (adev->asic_type < CHIP_CARRIZO) {
1635 init_data.flags.gpu_vm_support = false;
1636 } else if (adev->asic_type == CHIP_RAVEN) {
1637 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1638 init_data.flags.gpu_vm_support = false;
1640 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1642 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1645 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1647 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1648 init_data.flags.fbc_support = true;
1650 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1651 init_data.flags.multi_mon_pp_mclk_switch = true;
1653 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1654 init_data.flags.disable_fractional_pwm = true;
1656 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1657 init_data.flags.edp_no_power_sequencing = true;
1659 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1660 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1661 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1662 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1664 init_data.flags.seamless_boot_edp_requested = false;
1666 if (amdgpu_device_seamless_boot_supported(adev)) {
1667 init_data.flags.seamless_boot_edp_requested = true;
1668 init_data.flags.allow_seamless_boot_optimization = true;
1669 DRM_INFO("Seamless boot condition check passed\n");
1672 init_data.flags.enable_mipi_converter_optimization = true;
1674 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1675 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1676 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1678 INIT_LIST_HEAD(&adev->dm.da_list);
1680 retrieve_dmi_info(&adev->dm);
1682 /* Display Core create. */
1683 adev->dm.dc = dc_create(&init_data);
1686 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1687 dce_version_to_string(adev->dm.dc->ctx->dce_version));
1689 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1693 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1694 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1695 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1698 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1699 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1700 if (dm_should_disable_stutter(adev->pdev))
1701 adev->dm.dc->debug.disable_stutter = true;
1703 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1704 adev->dm.dc->debug.disable_stutter = true;
1706 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1707 adev->dm.dc->debug.disable_dsc = true;
1709 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1710 adev->dm.dc->debug.disable_clock_gate = true;
1712 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1713 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1715 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1717 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1718 adev->dm.dc->debug.ignore_cable_id = true;
1720 /* TODO: There is a new drm mst change where the freedom of
1721 * vc_next_start_slot update is revoked/moved into drm, instead of in
1722 * driver. This forces us to make sure to get vc_next_start_slot updated
1723 * in drm function each time without considering if mst_state is active
1724 * or not. Otherwise, next time hotplug will give wrong start_slot
1725 * number. We are implementing a temporary solution to even notify drm
1726 * mst deallocation when link is no longer of MST type when uncommitting
1727 * the stream so we will have more time to work on a proper solution.
1728 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1729 * should notify drm to do a complete "reset" of its states and stop
1730 * calling further drm mst functions when link is no longer of an MST
1731 * type. This could happen when we unplug an MST hubs/displays. When
1732 * uncommit stream comes later after unplug, we should just reset
1733 * hardware states only.
1735 adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1737 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1738 DRM_INFO("DP-HDMI FRL PCON supported\n");
1740 r = dm_dmub_hw_init(adev);
1742 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1746 dc_hardware_init(adev->dm.dc);
1748 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1749 if (!adev->dm.hpd_rx_offload_wq) {
1750 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1754 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1755 struct dc_phy_addr_space_config pa_config;
1757 mmhub_read_system_context(adev, &pa_config);
1759 // Call the DC init_memory func
1760 dc_setup_system_context(adev->dm.dc, &pa_config);
1763 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1764 if (!adev->dm.freesync_module) {
1766 "amdgpu: failed to initialize freesync_module.\n");
1768 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1769 adev->dm.freesync_module);
1771 amdgpu_dm_init_color_mod();
1773 if (adev->dm.dc->caps.max_links > 0) {
1774 adev->dm.vblank_control_workqueue =
1775 create_singlethread_workqueue("dm_vblank_control_workqueue");
1776 if (!adev->dm.vblank_control_workqueue)
1777 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1780 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1781 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1783 if (!adev->dm.hdcp_workqueue)
1784 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1786 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1788 dc_init_callbacks(adev->dm.dc, &init_params);
1790 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1791 init_completion(&adev->dm.dmub_aux_transfer_done);
1792 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1793 if (!adev->dm.dmub_notify) {
1794 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1798 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1799 if (!adev->dm.delayed_hpd_wq) {
1800 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1804 amdgpu_dm_outbox_init(adev);
1805 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1806 dmub_aux_setconfig_callback, false)) {
1807 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1810 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1811 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1814 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1815 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1820 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1821 * It is expected that DMUB will resend any pending notifications at this point, for
1822 * example HPD from DPIA.
1824 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1825 dc_enable_dmub_outbox(adev->dm.dc);
1827 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1828 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1829 dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1832 if (amdgpu_dm_initialize_drm_device(adev)) {
1834 "amdgpu: failed to initialize sw for display support.\n");
1838 /* create fake encoders for MST */
1839 dm_dp_create_fake_mst_encoders(adev);
1841 /* TODO: Add_display_info? */
1843 /* TODO use dynamic cursor width */
1844 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1845 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1847 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1849 "amdgpu: failed to initialize sw for display support.\n");
1853 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1854 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1855 if (!adev->dm.secure_display_ctxs)
1856 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1859 DRM_DEBUG_DRIVER("KMS initialized.\n");
1863 amdgpu_dm_fini(adev);
1868 static int amdgpu_dm_early_fini(void *handle)
1870 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1872 amdgpu_dm_audio_fini(adev);
1877 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1881 if (adev->dm.vblank_control_workqueue) {
1882 destroy_workqueue(adev->dm.vblank_control_workqueue);
1883 adev->dm.vblank_control_workqueue = NULL;
1886 amdgpu_dm_destroy_drm_device(&adev->dm);
1888 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1889 if (adev->dm.secure_display_ctxs) {
1890 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1891 if (adev->dm.secure_display_ctxs[i].crtc) {
1892 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1893 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1896 kfree(adev->dm.secure_display_ctxs);
1897 adev->dm.secure_display_ctxs = NULL;
1900 if (adev->dm.hdcp_workqueue) {
1901 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1902 adev->dm.hdcp_workqueue = NULL;
1906 dc_deinit_callbacks(adev->dm.dc);
1909 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1911 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1912 kfree(adev->dm.dmub_notify);
1913 adev->dm.dmub_notify = NULL;
1914 destroy_workqueue(adev->dm.delayed_hpd_wq);
1915 adev->dm.delayed_hpd_wq = NULL;
1918 if (adev->dm.dmub_bo)
1919 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1920 &adev->dm.dmub_bo_gpu_addr,
1921 &adev->dm.dmub_bo_cpu_addr);
1923 if (adev->dm.hpd_rx_offload_wq) {
1924 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1925 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1926 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1927 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1931 kfree(adev->dm.hpd_rx_offload_wq);
1932 adev->dm.hpd_rx_offload_wq = NULL;
1935 /* DC Destroy TODO: Replace destroy DAL */
1937 dc_destroy(&adev->dm.dc);
1939 * TODO: pageflip, vlank interrupt
1941 * amdgpu_dm_irq_fini(adev);
1944 if (adev->dm.cgs_device) {
1945 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1946 adev->dm.cgs_device = NULL;
1948 if (adev->dm.freesync_module) {
1949 mod_freesync_destroy(adev->dm.freesync_module);
1950 adev->dm.freesync_module = NULL;
1953 mutex_destroy(&adev->dm.audio_lock);
1954 mutex_destroy(&adev->dm.dc_lock);
1955 mutex_destroy(&adev->dm.dpia_aux_lock);
1958 static int load_dmcu_fw(struct amdgpu_device *adev)
1960 const char *fw_name_dmcu = NULL;
1962 const struct dmcu_firmware_header_v1_0 *hdr;
1964 switch (adev->asic_type) {
1965 #if defined(CONFIG_DRM_AMD_DC_SI)
1980 case CHIP_POLARIS11:
1981 case CHIP_POLARIS10:
1982 case CHIP_POLARIS12:
1989 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1992 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1993 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1994 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1995 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2000 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2001 case IP_VERSION(2, 0, 2):
2002 case IP_VERSION(2, 0, 3):
2003 case IP_VERSION(2, 0, 0):
2004 case IP_VERSION(2, 1, 0):
2005 case IP_VERSION(3, 0, 0):
2006 case IP_VERSION(3, 0, 2):
2007 case IP_VERSION(3, 0, 3):
2008 case IP_VERSION(3, 0, 1):
2009 case IP_VERSION(3, 1, 2):
2010 case IP_VERSION(3, 1, 3):
2011 case IP_VERSION(3, 1, 4):
2012 case IP_VERSION(3, 1, 5):
2013 case IP_VERSION(3, 1, 6):
2014 case IP_VERSION(3, 2, 0):
2015 case IP_VERSION(3, 2, 1):
2016 case IP_VERSION(3, 5, 0):
2021 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2025 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2026 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2030 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2032 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2033 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2034 adev->dm.fw_dmcu = NULL;
2038 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2040 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2044 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2045 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2046 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2047 adev->firmware.fw_size +=
2048 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2050 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2051 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2052 adev->firmware.fw_size +=
2053 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2055 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2057 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2062 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2064 struct amdgpu_device *adev = ctx;
2066 return dm_read_reg(adev->dm.dc->ctx, address);
2069 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2072 struct amdgpu_device *adev = ctx;
2074 return dm_write_reg(adev->dm.dc->ctx, address, value);
2077 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2079 struct dmub_srv_create_params create_params;
2080 struct dmub_srv_region_params region_params;
2081 struct dmub_srv_region_info region_info;
2082 struct dmub_srv_fb_params fb_params;
2083 struct dmub_srv_fb_info *fb_info;
2084 struct dmub_srv *dmub_srv;
2085 const struct dmcub_firmware_header_v1_0 *hdr;
2086 enum dmub_asic dmub_asic;
2087 enum dmub_status status;
2090 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2091 case IP_VERSION(2, 1, 0):
2092 dmub_asic = DMUB_ASIC_DCN21;
2094 case IP_VERSION(3, 0, 0):
2095 dmub_asic = DMUB_ASIC_DCN30;
2097 case IP_VERSION(3, 0, 1):
2098 dmub_asic = DMUB_ASIC_DCN301;
2100 case IP_VERSION(3, 0, 2):
2101 dmub_asic = DMUB_ASIC_DCN302;
2103 case IP_VERSION(3, 0, 3):
2104 dmub_asic = DMUB_ASIC_DCN303;
2106 case IP_VERSION(3, 1, 2):
2107 case IP_VERSION(3, 1, 3):
2108 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2110 case IP_VERSION(3, 1, 4):
2111 dmub_asic = DMUB_ASIC_DCN314;
2113 case IP_VERSION(3, 1, 5):
2114 dmub_asic = DMUB_ASIC_DCN315;
2116 case IP_VERSION(3, 1, 6):
2117 dmub_asic = DMUB_ASIC_DCN316;
2119 case IP_VERSION(3, 2, 0):
2120 dmub_asic = DMUB_ASIC_DCN32;
2122 case IP_VERSION(3, 2, 1):
2123 dmub_asic = DMUB_ASIC_DCN321;
2125 case IP_VERSION(3, 5, 0):
2126 dmub_asic = DMUB_ASIC_DCN35;
2129 /* ASIC doesn't support DMUB. */
2133 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2134 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2136 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2137 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2138 AMDGPU_UCODE_ID_DMCUB;
2139 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2141 adev->firmware.fw_size +=
2142 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2144 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2145 adev->dm.dmcub_fw_version);
2149 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2150 dmub_srv = adev->dm.dmub_srv;
2153 DRM_ERROR("Failed to allocate DMUB service!\n");
2157 memset(&create_params, 0, sizeof(create_params));
2158 create_params.user_ctx = adev;
2159 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2160 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2161 create_params.asic = dmub_asic;
2163 /* Create the DMUB service. */
2164 status = dmub_srv_create(dmub_srv, &create_params);
2165 if (status != DMUB_STATUS_OK) {
2166 DRM_ERROR("Error creating DMUB service: %d\n", status);
2170 /* Calculate the size of all the regions for the DMUB service. */
2171 memset(®ion_params, 0, sizeof(region_params));
2173 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2174 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2175 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2176 region_params.vbios_size = adev->bios_size;
2177 region_params.fw_bss_data = region_params.bss_data_size ?
2178 adev->dm.dmub_fw->data +
2179 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2180 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2181 region_params.fw_inst_const =
2182 adev->dm.dmub_fw->data +
2183 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2186 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2189 if (status != DMUB_STATUS_OK) {
2190 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2195 * Allocate a framebuffer based on the total size of all the regions.
2196 * TODO: Move this into GART.
2198 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2199 AMDGPU_GEM_DOMAIN_VRAM |
2200 AMDGPU_GEM_DOMAIN_GTT,
2202 &adev->dm.dmub_bo_gpu_addr,
2203 &adev->dm.dmub_bo_cpu_addr);
2207 /* Rebase the regions on the framebuffer address. */
2208 memset(&fb_params, 0, sizeof(fb_params));
2209 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2210 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2211 fb_params.region_info = ®ion_info;
2213 adev->dm.dmub_fb_info =
2214 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2215 fb_info = adev->dm.dmub_fb_info;
2219 "Failed to allocate framebuffer info for DMUB service!\n");
2223 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2224 if (status != DMUB_STATUS_OK) {
2225 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2232 static int dm_sw_init(void *handle)
2234 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2237 r = dm_dmub_sw_init(adev);
2241 return load_dmcu_fw(adev);
2244 static int dm_sw_fini(void *handle)
2246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2248 kfree(adev->dm.dmub_fb_info);
2249 adev->dm.dmub_fb_info = NULL;
2251 if (adev->dm.dmub_srv) {
2252 dmub_srv_destroy(adev->dm.dmub_srv);
2253 adev->dm.dmub_srv = NULL;
2256 amdgpu_ucode_release(&adev->dm.dmub_fw);
2257 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2262 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2264 struct amdgpu_dm_connector *aconnector;
2265 struct drm_connector *connector;
2266 struct drm_connector_list_iter iter;
2269 drm_connector_list_iter_begin(dev, &iter);
2270 drm_for_each_connector_iter(connector, &iter) {
2271 aconnector = to_amdgpu_dm_connector(connector);
2272 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2273 aconnector->mst_mgr.aux) {
2274 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2276 aconnector->base.base.id);
2278 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2280 DRM_ERROR("DM_MST: Failed to start MST\n");
2281 aconnector->dc_link->type =
2282 dc_connection_single;
2283 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2284 aconnector->dc_link);
2289 drm_connector_list_iter_end(&iter);
2294 static int dm_late_init(void *handle)
2296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2298 struct dmcu_iram_parameters params;
2299 unsigned int linear_lut[16];
2301 struct dmcu *dmcu = NULL;
2303 dmcu = adev->dm.dc->res_pool->dmcu;
2305 for (i = 0; i < 16; i++)
2306 linear_lut[i] = 0xFFFF * i / 15;
2309 params.backlight_ramping_override = false;
2310 params.backlight_ramping_start = 0xCCCC;
2311 params.backlight_ramping_reduction = 0xCCCCCCCC;
2312 params.backlight_lut_array_size = 16;
2313 params.backlight_lut_array = linear_lut;
2315 /* Min backlight level after ABM reduction, Don't allow below 1%
2316 * 0xFFFF x 0.01 = 0x28F
2318 params.min_abm_backlight = 0x28F;
2319 /* In the case where abm is implemented on dmcub,
2320 * dmcu object will be null.
2321 * ABM 2.4 and up are implemented on dmcub.
2324 if (!dmcu_load_iram(dmcu, params))
2326 } else if (adev->dm.dc->ctx->dmub_srv) {
2327 struct dc_link *edp_links[MAX_NUM_EDP];
2330 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2331 for (i = 0; i < edp_num; i++) {
2332 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2337 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2340 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2346 mutex_lock(&mgr->lock);
2347 if (!mgr->mst_primary)
2350 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2351 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2355 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2358 DP_UPSTREAM_IS_SRC);
2360 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2364 /* Some hubs forget their guids after they resume */
2365 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2367 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2371 if (memchr_inv(guid, 0, 16) == NULL) {
2372 tmp64 = get_jiffies_64();
2373 memcpy(&guid[0], &tmp64, sizeof(u64));
2374 memcpy(&guid[8], &tmp64, sizeof(u64));
2376 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2379 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2384 memcpy(mgr->mst_primary->guid, guid, 16);
2387 mutex_unlock(&mgr->lock);
2390 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2392 struct amdgpu_dm_connector *aconnector;
2393 struct drm_connector *connector;
2394 struct drm_connector_list_iter iter;
2395 struct drm_dp_mst_topology_mgr *mgr;
2397 drm_connector_list_iter_begin(dev, &iter);
2398 drm_for_each_connector_iter(connector, &iter) {
2399 aconnector = to_amdgpu_dm_connector(connector);
2400 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2401 aconnector->mst_root)
2404 mgr = &aconnector->mst_mgr;
2407 drm_dp_mst_topology_mgr_suspend(mgr);
2409 /* if extended timeout is supported in hardware,
2410 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2411 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2413 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2414 if (!dp_is_lttpr_present(aconnector->dc_link))
2415 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2417 /* TODO: move resume_mst_branch_status() into drm mst resume again
2418 * once topology probing work is pulled out from mst resume into mst
2419 * resume 2nd step. mst resume 2nd step should be called after old
2420 * state getting restored (i.e. drm_atomic_helper_resume()).
2422 resume_mst_branch_status(mgr);
2425 drm_connector_list_iter_end(&iter);
2428 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2432 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2433 * on window driver dc implementation.
2434 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2435 * should be passed to smu during boot up and resume from s3.
2436 * boot up: dc calculate dcn watermark clock settings within dc_create,
2437 * dcn20_resource_construct
2438 * then call pplib functions below to pass the settings to smu:
2439 * smu_set_watermarks_for_clock_ranges
2440 * smu_set_watermarks_table
2441 * navi10_set_watermarks_table
2442 * smu_write_watermarks_table
2444 * For Renoir, clock settings of dcn watermark are also fixed values.
2445 * dc has implemented different flow for window driver:
2446 * dc_hardware_init / dc_set_power_state
2451 * smu_set_watermarks_for_clock_ranges
2452 * renoir_set_watermarks_table
2453 * smu_write_watermarks_table
2456 * dc_hardware_init -> amdgpu_dm_init
2457 * dc_set_power_state --> dm_resume
2459 * therefore, this function apply to navi10/12/14 but not Renoir
2462 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2463 case IP_VERSION(2, 0, 2):
2464 case IP_VERSION(2, 0, 0):
2470 ret = amdgpu_dpm_write_watermarks_table(adev);
2472 DRM_ERROR("Failed to update WMTABLE!\n");
2480 * dm_hw_init() - Initialize DC device
2481 * @handle: The base driver device containing the amdgpu_dm device.
2483 * Initialize the &struct amdgpu_display_manager device. This involves calling
2484 * the initializers of each DM component, then populating the struct with them.
2486 * Although the function implies hardware initialization, both hardware and
2487 * software are initialized here. Splitting them out to their relevant init
2488 * hooks is a future TODO item.
2490 * Some notable things that are initialized here:
2492 * - Display Core, both software and hardware
2493 * - DC modules that we need (freesync and color management)
2494 * - DRM software states
2495 * - Interrupt sources and handlers
2497 * - Debug FS entries, if enabled
2499 static int dm_hw_init(void *handle)
2501 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2502 /* Create DAL display manager */
2503 amdgpu_dm_init(adev);
2504 amdgpu_dm_hpd_init(adev);
2510 * dm_hw_fini() - Teardown DC device
2511 * @handle: The base driver device containing the amdgpu_dm device.
2513 * Teardown components within &struct amdgpu_display_manager that require
2514 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2515 * were loaded. Also flush IRQ workqueues and disable them.
2517 static int dm_hw_fini(void *handle)
2519 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2521 amdgpu_dm_hpd_fini(adev);
2523 amdgpu_dm_irq_fini(adev);
2524 amdgpu_dm_fini(adev);
2529 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2530 struct dc_state *state, bool enable)
2532 enum dc_irq_source irq_source;
2533 struct amdgpu_crtc *acrtc;
2537 for (i = 0; i < state->stream_count; i++) {
2538 acrtc = get_crtc_by_otg_inst(
2539 adev, state->stream_status[i].primary_otg_inst);
2541 if (acrtc && state->stream_status[i].plane_count != 0) {
2542 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2543 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2545 DRM_WARN("Failed to %s pflip interrupts\n",
2546 enable ? "enable" : "disable");
2549 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2550 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2552 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2555 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2557 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2558 /* During gpu-reset we disable and then enable vblank irq, so
2559 * don't use amdgpu_irq_get/put() to avoid refcount change.
2561 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2562 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2568 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2570 struct dc_state *context = NULL;
2571 enum dc_status res = DC_ERROR_UNEXPECTED;
2573 struct dc_stream_state *del_streams[MAX_PIPES];
2574 int del_streams_count = 0;
2576 memset(del_streams, 0, sizeof(del_streams));
2578 context = dc_create_state(dc);
2579 if (context == NULL)
2580 goto context_alloc_fail;
2582 dc_resource_state_copy_construct_current(dc, context);
2584 /* First remove from context all streams */
2585 for (i = 0; i < context->stream_count; i++) {
2586 struct dc_stream_state *stream = context->streams[i];
2588 del_streams[del_streams_count++] = stream;
2591 /* Remove all planes for removed streams and then remove the streams */
2592 for (i = 0; i < del_streams_count; i++) {
2593 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2594 res = DC_FAIL_DETACH_SURFACES;
2598 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2603 res = dc_commit_streams(dc, context->streams, context->stream_count);
2606 dc_release_state(context);
2612 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2616 if (dm->hpd_rx_offload_wq) {
2617 for (i = 0; i < dm->dc->caps.max_links; i++)
2618 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2622 static int dm_suspend(void *handle)
2624 struct amdgpu_device *adev = handle;
2625 struct amdgpu_display_manager *dm = &adev->dm;
2628 if (amdgpu_in_reset(adev)) {
2629 mutex_lock(&dm->dc_lock);
2631 dc_allow_idle_optimizations(adev->dm.dc, false);
2633 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2635 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2637 amdgpu_dm_commit_zero_streams(dm->dc);
2639 amdgpu_dm_irq_suspend(adev);
2641 hpd_rx_irq_work_suspend(dm);
2646 WARN_ON(adev->dm.cached_state);
2647 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2648 if (IS_ERR(adev->dm.cached_state))
2649 return PTR_ERR(adev->dm.cached_state);
2651 s3_handle_mst(adev_to_drm(adev), true);
2653 amdgpu_dm_irq_suspend(adev);
2655 hpd_rx_irq_work_suspend(dm);
2657 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2662 struct amdgpu_dm_connector *
2663 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2664 struct drm_crtc *crtc)
2667 struct drm_connector_state *new_con_state;
2668 struct drm_connector *connector;
2669 struct drm_crtc *crtc_from_state;
2671 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2672 crtc_from_state = new_con_state->crtc;
2674 if (crtc_from_state == crtc)
2675 return to_amdgpu_dm_connector(connector);
2681 static void emulated_link_detect(struct dc_link *link)
2683 struct dc_sink_init_data sink_init_data = { 0 };
2684 struct display_sink_capability sink_caps = { 0 };
2685 enum dc_edid_status edid_status;
2686 struct dc_context *dc_ctx = link->ctx;
2687 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2688 struct dc_sink *sink = NULL;
2689 struct dc_sink *prev_sink = NULL;
2691 link->type = dc_connection_none;
2692 prev_sink = link->local_sink;
2695 dc_sink_release(prev_sink);
2697 switch (link->connector_signal) {
2698 case SIGNAL_TYPE_HDMI_TYPE_A: {
2699 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2700 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2704 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2705 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2706 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2710 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2711 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2712 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2716 case SIGNAL_TYPE_LVDS: {
2717 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2718 sink_caps.signal = SIGNAL_TYPE_LVDS;
2722 case SIGNAL_TYPE_EDP: {
2723 sink_caps.transaction_type =
2724 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2725 sink_caps.signal = SIGNAL_TYPE_EDP;
2729 case SIGNAL_TYPE_DISPLAY_PORT: {
2730 sink_caps.transaction_type =
2731 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2732 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2737 drm_err(dev, "Invalid connector type! signal:%d\n",
2738 link->connector_signal);
2742 sink_init_data.link = link;
2743 sink_init_data.sink_signal = sink_caps.signal;
2745 sink = dc_sink_create(&sink_init_data);
2747 drm_err(dev, "Failed to create sink!\n");
2751 /* dc_sink_create returns a new reference */
2752 link->local_sink = sink;
2754 edid_status = dm_helpers_read_local_edid(
2759 if (edid_status != EDID_OK)
2760 drm_err(dev, "Failed to read EDID\n");
2764 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2765 struct amdgpu_display_manager *dm)
2768 struct dc_surface_update surface_updates[MAX_SURFACES];
2769 struct dc_plane_info plane_infos[MAX_SURFACES];
2770 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2771 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2772 struct dc_stream_update stream_update;
2776 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2779 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2783 for (k = 0; k < dc_state->stream_count; k++) {
2784 bundle->stream_update.stream = dc_state->streams[k];
2786 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2787 bundle->surface_updates[m].surface =
2788 dc_state->stream_status->plane_states[m];
2789 bundle->surface_updates[m].surface->force_full_update =
2793 update_planes_and_stream_adapter(dm->dc,
2795 dc_state->stream_status->plane_count,
2796 dc_state->streams[k],
2797 &bundle->stream_update,
2798 bundle->surface_updates);
2805 static int dm_resume(void *handle)
2807 struct amdgpu_device *adev = handle;
2808 struct drm_device *ddev = adev_to_drm(adev);
2809 struct amdgpu_display_manager *dm = &adev->dm;
2810 struct amdgpu_dm_connector *aconnector;
2811 struct drm_connector *connector;
2812 struct drm_connector_list_iter iter;
2813 struct drm_crtc *crtc;
2814 struct drm_crtc_state *new_crtc_state;
2815 struct dm_crtc_state *dm_new_crtc_state;
2816 struct drm_plane *plane;
2817 struct drm_plane_state *new_plane_state;
2818 struct dm_plane_state *dm_new_plane_state;
2819 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2820 enum dc_connection_type new_connection_type = dc_connection_none;
2821 struct dc_state *dc_state;
2823 bool need_hotplug = false;
2825 if (dm->dc->caps.ips_support) {
2826 dc_dmub_srv_exit_low_power_state(dm->dc);
2829 if (amdgpu_in_reset(adev)) {
2830 dc_state = dm->cached_dc_state;
2833 * The dc->current_state is backed up into dm->cached_dc_state
2834 * before we commit 0 streams.
2836 * DC will clear link encoder assignments on the real state
2837 * but the changes won't propagate over to the copy we made
2838 * before the 0 streams commit.
2840 * DC expects that link encoder assignments are *not* valid
2841 * when committing a state, so as a workaround we can copy
2842 * off of the current state.
2844 * We lose the previous assignments, but we had already
2845 * commit 0 streams anyway.
2847 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2849 r = dm_dmub_hw_init(adev);
2851 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2853 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2857 amdgpu_dm_irq_resume_early(adev);
2859 for (i = 0; i < dc_state->stream_count; i++) {
2860 dc_state->streams[i]->mode_changed = true;
2861 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2862 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2867 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2868 amdgpu_dm_outbox_init(adev);
2869 dc_enable_dmub_outbox(adev->dm.dc);
2872 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2874 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2876 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2878 dc_release_state(dm->cached_dc_state);
2879 dm->cached_dc_state = NULL;
2881 amdgpu_dm_irq_resume_late(adev);
2883 mutex_unlock(&dm->dc_lock);
2887 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2888 dc_release_state(dm_state->context);
2889 dm_state->context = dc_create_state(dm->dc);
2890 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2891 dc_resource_state_construct(dm->dc, dm_state->context);
2893 /* Before powering on DC we need to re-initialize DMUB. */
2894 dm_dmub_hw_resume(adev);
2896 /* Re-enable outbox interrupts for DPIA. */
2897 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2898 amdgpu_dm_outbox_init(adev);
2899 dc_enable_dmub_outbox(adev->dm.dc);
2902 /* power on hardware */
2903 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2905 /* program HPD filter */
2909 * early enable HPD Rx IRQ, should be done before set mode as short
2910 * pulse interrupts are used for MST
2912 amdgpu_dm_irq_resume_early(adev);
2914 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2915 s3_handle_mst(ddev, false);
2918 drm_connector_list_iter_begin(ddev, &iter);
2919 drm_for_each_connector_iter(connector, &iter) {
2920 aconnector = to_amdgpu_dm_connector(connector);
2922 if (!aconnector->dc_link)
2926 * this is the case when traversing through already created end sink
2927 * MST connectors, should be skipped
2929 if (aconnector && aconnector->mst_root)
2932 mutex_lock(&aconnector->hpd_lock);
2933 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2934 DRM_ERROR("KMS: Failed to detect connector\n");
2936 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2937 emulated_link_detect(aconnector->dc_link);
2939 mutex_lock(&dm->dc_lock);
2940 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2941 mutex_unlock(&dm->dc_lock);
2944 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2945 aconnector->fake_enable = false;
2947 if (aconnector->dc_sink)
2948 dc_sink_release(aconnector->dc_sink);
2949 aconnector->dc_sink = NULL;
2950 amdgpu_dm_update_connector_after_detect(aconnector);
2951 mutex_unlock(&aconnector->hpd_lock);
2953 drm_connector_list_iter_end(&iter);
2955 /* Force mode set in atomic commit */
2956 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2957 new_crtc_state->active_changed = true;
2960 * atomic_check is expected to create the dc states. We need to release
2961 * them here, since they were duplicated as part of the suspend
2964 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2965 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2966 if (dm_new_crtc_state->stream) {
2967 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2968 dc_stream_release(dm_new_crtc_state->stream);
2969 dm_new_crtc_state->stream = NULL;
2973 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2974 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2975 if (dm_new_plane_state->dc_state) {
2976 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2977 dc_plane_state_release(dm_new_plane_state->dc_state);
2978 dm_new_plane_state->dc_state = NULL;
2982 drm_atomic_helper_resume(ddev, dm->cached_state);
2984 dm->cached_state = NULL;
2986 /* Do mst topology probing after resuming cached state*/
2987 drm_connector_list_iter_begin(ddev, &iter);
2988 drm_for_each_connector_iter(connector, &iter) {
2989 aconnector = to_amdgpu_dm_connector(connector);
2990 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2991 aconnector->mst_root)
2994 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2997 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2998 aconnector->dc_link);
2999 need_hotplug = true;
3002 drm_connector_list_iter_end(&iter);
3005 drm_kms_helper_hotplug_event(ddev);
3007 amdgpu_dm_irq_resume_late(adev);
3009 amdgpu_dm_smu_write_watermarks_table(adev);
3017 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3018 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3019 * the base driver's device list to be initialized and torn down accordingly.
3021 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3024 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3026 .early_init = dm_early_init,
3027 .late_init = dm_late_init,
3028 .sw_init = dm_sw_init,
3029 .sw_fini = dm_sw_fini,
3030 .early_fini = amdgpu_dm_early_fini,
3031 .hw_init = dm_hw_init,
3032 .hw_fini = dm_hw_fini,
3033 .suspend = dm_suspend,
3034 .resume = dm_resume,
3035 .is_idle = dm_is_idle,
3036 .wait_for_idle = dm_wait_for_idle,
3037 .check_soft_reset = dm_check_soft_reset,
3038 .soft_reset = dm_soft_reset,
3039 .set_clockgating_state = dm_set_clockgating_state,
3040 .set_powergating_state = dm_set_powergating_state,
3043 const struct amdgpu_ip_block_version dm_ip_block = {
3044 .type = AMD_IP_BLOCK_TYPE_DCE,
3048 .funcs = &amdgpu_dm_funcs,
3058 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3059 .fb_create = amdgpu_display_user_framebuffer_create,
3060 .get_format_info = amdgpu_dm_plane_get_format_info,
3061 .atomic_check = amdgpu_dm_atomic_check,
3062 .atomic_commit = drm_atomic_helper_commit,
3065 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3066 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3067 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3070 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3072 struct amdgpu_dm_backlight_caps *caps;
3073 struct drm_connector *conn_base;
3074 struct amdgpu_device *adev;
3075 struct drm_luminance_range_info *luminance_range;
3077 if (aconnector->bl_idx == -1 ||
3078 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3081 conn_base = &aconnector->base;
3082 adev = drm_to_adev(conn_base->dev);
3084 caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3085 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3086 caps->aux_support = false;
3088 if (caps->ext_caps->bits.oled == 1
3091 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3092 * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3094 caps->aux_support = true;
3096 if (amdgpu_backlight == 0)
3097 caps->aux_support = false;
3098 else if (amdgpu_backlight == 1)
3099 caps->aux_support = true;
3101 luminance_range = &conn_base->display_info.luminance_range;
3103 if (luminance_range->max_luminance) {
3104 caps->aux_min_input_signal = luminance_range->min_luminance;
3105 caps->aux_max_input_signal = luminance_range->max_luminance;
3107 caps->aux_min_input_signal = 0;
3108 caps->aux_max_input_signal = 512;
3112 void amdgpu_dm_update_connector_after_detect(
3113 struct amdgpu_dm_connector *aconnector)
3115 struct drm_connector *connector = &aconnector->base;
3116 struct drm_device *dev = connector->dev;
3117 struct dc_sink *sink;
3119 /* MST handled by drm_mst framework */
3120 if (aconnector->mst_mgr.mst_state == true)
3123 sink = aconnector->dc_link->local_sink;
3125 dc_sink_retain(sink);
3128 * Edid mgmt connector gets first update only in mode_valid hook and then
3129 * the connector sink is set to either fake or physical sink depends on link status.
3130 * Skip if already done during boot.
3132 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3133 && aconnector->dc_em_sink) {
3136 * For S3 resume with headless use eml_sink to fake stream
3137 * because on resume connector->sink is set to NULL
3139 mutex_lock(&dev->mode_config.mutex);
3142 if (aconnector->dc_sink) {
3143 amdgpu_dm_update_freesync_caps(connector, NULL);
3145 * retain and release below are used to
3146 * bump up refcount for sink because the link doesn't point
3147 * to it anymore after disconnect, so on next crtc to connector
3148 * reshuffle by UMD we will get into unwanted dc_sink release
3150 dc_sink_release(aconnector->dc_sink);
3152 aconnector->dc_sink = sink;
3153 dc_sink_retain(aconnector->dc_sink);
3154 amdgpu_dm_update_freesync_caps(connector,
3157 amdgpu_dm_update_freesync_caps(connector, NULL);
3158 if (!aconnector->dc_sink) {
3159 aconnector->dc_sink = aconnector->dc_em_sink;
3160 dc_sink_retain(aconnector->dc_sink);
3164 mutex_unlock(&dev->mode_config.mutex);
3167 dc_sink_release(sink);
3172 * TODO: temporary guard to look for proper fix
3173 * if this sink is MST sink, we should not do anything
3175 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3176 dc_sink_release(sink);
3180 if (aconnector->dc_sink == sink) {
3182 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3185 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3186 aconnector->connector_id);
3188 dc_sink_release(sink);
3192 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3193 aconnector->connector_id, aconnector->dc_sink, sink);
3195 mutex_lock(&dev->mode_config.mutex);
3198 * 1. Update status of the drm connector
3199 * 2. Send an event and let userspace tell us what to do
3203 * TODO: check if we still need the S3 mode update workaround.
3204 * If yes, put it here.
3206 if (aconnector->dc_sink) {
3207 amdgpu_dm_update_freesync_caps(connector, NULL);
3208 dc_sink_release(aconnector->dc_sink);
3211 aconnector->dc_sink = sink;
3212 dc_sink_retain(aconnector->dc_sink);
3213 if (sink->dc_edid.length == 0) {
3214 aconnector->edid = NULL;
3215 if (aconnector->dc_link->aux_mode) {
3216 drm_dp_cec_unset_edid(
3217 &aconnector->dm_dp_aux.aux);
3221 (struct edid *)sink->dc_edid.raw_edid;
3223 if (aconnector->dc_link->aux_mode)
3224 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3228 if (!aconnector->timing_requested) {
3229 aconnector->timing_requested =
3230 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3231 if (!aconnector->timing_requested)
3233 "failed to create aconnector->requested_timing\n");
3236 drm_connector_update_edid_property(connector, aconnector->edid);
3237 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3238 update_connector_ext_caps(aconnector);
3240 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3241 amdgpu_dm_update_freesync_caps(connector, NULL);
3242 drm_connector_update_edid_property(connector, NULL);
3243 aconnector->num_modes = 0;
3244 dc_sink_release(aconnector->dc_sink);
3245 aconnector->dc_sink = NULL;
3246 aconnector->edid = NULL;
3247 kfree(aconnector->timing_requested);
3248 aconnector->timing_requested = NULL;
3249 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3250 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3251 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3254 mutex_unlock(&dev->mode_config.mutex);
3256 update_subconnector_property(aconnector);
3259 dc_sink_release(sink);
3262 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3264 struct drm_connector *connector = &aconnector->base;
3265 struct drm_device *dev = connector->dev;
3266 enum dc_connection_type new_connection_type = dc_connection_none;
3267 struct amdgpu_device *adev = drm_to_adev(dev);
3268 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3271 if (adev->dm.disable_hpd_irq)
3275 * In case of failure or MST no need to update connector status or notify the OS
3276 * since (for MST case) MST does this in its own context.
3278 mutex_lock(&aconnector->hpd_lock);
3280 if (adev->dm.hdcp_workqueue) {
3281 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3282 dm_con_state->update_hdcp = true;
3284 if (aconnector->fake_enable)
3285 aconnector->fake_enable = false;
3287 aconnector->timing_changed = false;
3289 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3290 DRM_ERROR("KMS: Failed to detect connector\n");
3292 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3293 emulated_link_detect(aconnector->dc_link);
3295 drm_modeset_lock_all(dev);
3296 dm_restore_drm_connector_state(dev, connector);
3297 drm_modeset_unlock_all(dev);
3299 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3300 drm_kms_helper_connector_hotplug_event(connector);
3302 mutex_lock(&adev->dm.dc_lock);
3303 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3304 mutex_unlock(&adev->dm.dc_lock);
3306 amdgpu_dm_update_connector_after_detect(aconnector);
3308 drm_modeset_lock_all(dev);
3309 dm_restore_drm_connector_state(dev, connector);
3310 drm_modeset_unlock_all(dev);
3312 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3313 drm_kms_helper_connector_hotplug_event(connector);
3316 mutex_unlock(&aconnector->hpd_lock);
3320 static void handle_hpd_irq(void *param)
3322 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3324 handle_hpd_irq_helper(aconnector);
3328 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3329 union hpd_irq_data hpd_irq_data)
3331 struct hpd_rx_irq_offload_work *offload_work =
3332 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3334 if (!offload_work) {
3335 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3339 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3340 offload_work->data = hpd_irq_data;
3341 offload_work->offload_wq = offload_wq;
3343 queue_work(offload_wq->wq, &offload_work->work);
3344 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3347 static void handle_hpd_rx_irq(void *param)
3349 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3350 struct drm_connector *connector = &aconnector->base;
3351 struct drm_device *dev = connector->dev;
3352 struct dc_link *dc_link = aconnector->dc_link;
3353 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3354 bool result = false;
3355 enum dc_connection_type new_connection_type = dc_connection_none;
3356 struct amdgpu_device *adev = drm_to_adev(dev);
3357 union hpd_irq_data hpd_irq_data;
3358 bool link_loss = false;
3359 bool has_left_work = false;
3360 int idx = dc_link->link_index;
3361 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3363 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3365 if (adev->dm.disable_hpd_irq)
3369 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3370 * conflict, after implement i2c helper, this mutex should be
3373 mutex_lock(&aconnector->hpd_lock);
3375 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3376 &link_loss, true, &has_left_work);
3381 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3382 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3386 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3387 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3388 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3392 * DOWN_REP_MSG_RDY is also handled by polling method
3393 * mgr->cbs->poll_hpd_irq()
3395 spin_lock(&offload_wq->offload_lock);
3396 skip = offload_wq->is_handling_mst_msg_rdy_event;
3399 offload_wq->is_handling_mst_msg_rdy_event = true;
3401 spin_unlock(&offload_wq->offload_lock);
3404 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3412 spin_lock(&offload_wq->offload_lock);
3413 skip = offload_wq->is_handling_link_loss;
3416 offload_wq->is_handling_link_loss = true;
3418 spin_unlock(&offload_wq->offload_lock);
3421 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3428 if (result && !is_mst_root_connector) {
3429 /* Downstream Port status changed. */
3430 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3431 DRM_ERROR("KMS: Failed to detect connector\n");
3433 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3434 emulated_link_detect(dc_link);
3436 if (aconnector->fake_enable)
3437 aconnector->fake_enable = false;
3439 amdgpu_dm_update_connector_after_detect(aconnector);
3442 drm_modeset_lock_all(dev);
3443 dm_restore_drm_connector_state(dev, connector);
3444 drm_modeset_unlock_all(dev);
3446 drm_kms_helper_connector_hotplug_event(connector);
3450 mutex_lock(&adev->dm.dc_lock);
3451 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3452 mutex_unlock(&adev->dm.dc_lock);
3455 if (aconnector->fake_enable)
3456 aconnector->fake_enable = false;
3458 amdgpu_dm_update_connector_after_detect(aconnector);
3460 drm_modeset_lock_all(dev);
3461 dm_restore_drm_connector_state(dev, connector);
3462 drm_modeset_unlock_all(dev);
3464 drm_kms_helper_connector_hotplug_event(connector);
3468 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3469 if (adev->dm.hdcp_workqueue)
3470 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3473 if (dc_link->type != dc_connection_mst_branch)
3474 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3476 mutex_unlock(&aconnector->hpd_lock);
3479 static void register_hpd_handlers(struct amdgpu_device *adev)
3481 struct drm_device *dev = adev_to_drm(adev);
3482 struct drm_connector *connector;
3483 struct amdgpu_dm_connector *aconnector;
3484 const struct dc_link *dc_link;
3485 struct dc_interrupt_params int_params = {0};
3487 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3488 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3490 list_for_each_entry(connector,
3491 &dev->mode_config.connector_list, head) {
3493 aconnector = to_amdgpu_dm_connector(connector);
3494 dc_link = aconnector->dc_link;
3496 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3497 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3498 int_params.irq_source = dc_link->irq_source_hpd;
3500 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3502 (void *) aconnector);
3505 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3507 /* Also register for DP short pulse (hpd_rx). */
3508 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3509 int_params.irq_source = dc_link->irq_source_hpd_rx;
3511 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3513 (void *) aconnector);
3516 if (adev->dm.hpd_rx_offload_wq)
3517 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3522 #if defined(CONFIG_DRM_AMD_DC_SI)
3523 /* Register IRQ sources and initialize IRQ callbacks */
3524 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3526 struct dc *dc = adev->dm.dc;
3527 struct common_irq_params *c_irq_params;
3528 struct dc_interrupt_params int_params = {0};
3531 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3533 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3534 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3537 * Actions of amdgpu_irq_add_id():
3538 * 1. Register a set() function with base driver.
3539 * Base driver will call set() function to enable/disable an
3540 * interrupt in DC hardware.
3541 * 2. Register amdgpu_dm_irq_handler().
3542 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3543 * coming from DC hardware.
3544 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3545 * for acknowledging and handling.
3548 /* Use VBLANK interrupt */
3549 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3550 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3552 DRM_ERROR("Failed to add crtc irq id!\n");
3556 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3557 int_params.irq_source =
3558 dc_interrupt_to_irq_source(dc, i + 1, 0);
3560 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3562 c_irq_params->adev = adev;
3563 c_irq_params->irq_src = int_params.irq_source;
3565 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3566 dm_crtc_high_irq, c_irq_params);
3569 /* Use GRPH_PFLIP interrupt */
3570 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3571 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3572 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3574 DRM_ERROR("Failed to add page flip irq id!\n");
3578 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3579 int_params.irq_source =
3580 dc_interrupt_to_irq_source(dc, i, 0);
3582 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3584 c_irq_params->adev = adev;
3585 c_irq_params->irq_src = int_params.irq_source;
3587 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3588 dm_pflip_high_irq, c_irq_params);
3593 r = amdgpu_irq_add_id(adev, client_id,
3594 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3596 DRM_ERROR("Failed to add hpd irq id!\n");
3600 register_hpd_handlers(adev);
3606 /* Register IRQ sources and initialize IRQ callbacks */
3607 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3609 struct dc *dc = adev->dm.dc;
3610 struct common_irq_params *c_irq_params;
3611 struct dc_interrupt_params int_params = {0};
3614 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3616 if (adev->family >= AMDGPU_FAMILY_AI)
3617 client_id = SOC15_IH_CLIENTID_DCE;
3619 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3620 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3623 * Actions of amdgpu_irq_add_id():
3624 * 1. Register a set() function with base driver.
3625 * Base driver will call set() function to enable/disable an
3626 * interrupt in DC hardware.
3627 * 2. Register amdgpu_dm_irq_handler().
3628 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3629 * coming from DC hardware.
3630 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3631 * for acknowledging and handling.
3634 /* Use VBLANK interrupt */
3635 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3636 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3638 DRM_ERROR("Failed to add crtc irq id!\n");
3642 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3643 int_params.irq_source =
3644 dc_interrupt_to_irq_source(dc, i, 0);
3646 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3648 c_irq_params->adev = adev;
3649 c_irq_params->irq_src = int_params.irq_source;
3651 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3652 dm_crtc_high_irq, c_irq_params);
3655 /* Use VUPDATE interrupt */
3656 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3657 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3659 DRM_ERROR("Failed to add vupdate irq id!\n");
3663 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3664 int_params.irq_source =
3665 dc_interrupt_to_irq_source(dc, i, 0);
3667 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3669 c_irq_params->adev = adev;
3670 c_irq_params->irq_src = int_params.irq_source;
3672 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3673 dm_vupdate_high_irq, c_irq_params);
3676 /* Use GRPH_PFLIP interrupt */
3677 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3678 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3679 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3681 DRM_ERROR("Failed to add page flip irq id!\n");
3685 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3686 int_params.irq_source =
3687 dc_interrupt_to_irq_source(dc, i, 0);
3689 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3691 c_irq_params->adev = adev;
3692 c_irq_params->irq_src = int_params.irq_source;
3694 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3695 dm_pflip_high_irq, c_irq_params);
3700 r = amdgpu_irq_add_id(adev, client_id,
3701 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3703 DRM_ERROR("Failed to add hpd irq id!\n");
3707 register_hpd_handlers(adev);
3712 /* Register IRQ sources and initialize IRQ callbacks */
3713 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3715 struct dc *dc = adev->dm.dc;
3716 struct common_irq_params *c_irq_params;
3717 struct dc_interrupt_params int_params = {0};
3720 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3721 static const unsigned int vrtl_int_srcid[] = {
3722 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3723 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3724 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3725 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3726 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3727 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3731 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3732 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3735 * Actions of amdgpu_irq_add_id():
3736 * 1. Register a set() function with base driver.
3737 * Base driver will call set() function to enable/disable an
3738 * interrupt in DC hardware.
3739 * 2. Register amdgpu_dm_irq_handler().
3740 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3741 * coming from DC hardware.
3742 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3743 * for acknowledging and handling.
3746 /* Use VSTARTUP interrupt */
3747 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3748 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3750 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3753 DRM_ERROR("Failed to add crtc irq id!\n");
3757 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3758 int_params.irq_source =
3759 dc_interrupt_to_irq_source(dc, i, 0);
3761 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3763 c_irq_params->adev = adev;
3764 c_irq_params->irq_src = int_params.irq_source;
3766 amdgpu_dm_irq_register_interrupt(
3767 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3770 /* Use otg vertical line interrupt */
3771 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3772 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3773 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3774 vrtl_int_srcid[i], &adev->vline0_irq);
3777 DRM_ERROR("Failed to add vline0 irq id!\n");
3781 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3782 int_params.irq_source =
3783 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3785 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3786 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3790 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3791 - DC_IRQ_SOURCE_DC1_VLINE0];
3793 c_irq_params->adev = adev;
3794 c_irq_params->irq_src = int_params.irq_source;
3796 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3797 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3801 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3802 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3803 * to trigger at end of each vblank, regardless of state of the lock,
3804 * matching DCE behaviour.
3806 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3807 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3809 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3812 DRM_ERROR("Failed to add vupdate irq id!\n");
3816 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3817 int_params.irq_source =
3818 dc_interrupt_to_irq_source(dc, i, 0);
3820 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3822 c_irq_params->adev = adev;
3823 c_irq_params->irq_src = int_params.irq_source;
3825 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3826 dm_vupdate_high_irq, c_irq_params);
3829 /* Use GRPH_PFLIP interrupt */
3830 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3831 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3833 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3835 DRM_ERROR("Failed to add page flip irq id!\n");
3839 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3840 int_params.irq_source =
3841 dc_interrupt_to_irq_source(dc, i, 0);
3843 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3845 c_irq_params->adev = adev;
3846 c_irq_params->irq_src = int_params.irq_source;
3848 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3849 dm_pflip_high_irq, c_irq_params);
3854 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3857 DRM_ERROR("Failed to add hpd irq id!\n");
3861 register_hpd_handlers(adev);
3865 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3866 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3868 struct dc *dc = adev->dm.dc;
3869 struct common_irq_params *c_irq_params;
3870 struct dc_interrupt_params int_params = {0};
3873 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3874 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3876 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3877 &adev->dmub_outbox_irq);
3879 DRM_ERROR("Failed to add outbox irq id!\n");
3883 if (dc->ctx->dmub_srv) {
3884 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3885 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3886 int_params.irq_source =
3887 dc_interrupt_to_irq_source(dc, i, 0);
3889 c_irq_params = &adev->dm.dmub_outbox_params[0];
3891 c_irq_params->adev = adev;
3892 c_irq_params->irq_src = int_params.irq_source;
3894 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3895 dm_dmub_outbox1_low_irq, c_irq_params);
3902 * Acquires the lock for the atomic state object and returns
3903 * the new atomic state.
3905 * This should only be called during atomic check.
3907 int dm_atomic_get_state(struct drm_atomic_state *state,
3908 struct dm_atomic_state **dm_state)
3910 struct drm_device *dev = state->dev;
3911 struct amdgpu_device *adev = drm_to_adev(dev);
3912 struct amdgpu_display_manager *dm = &adev->dm;
3913 struct drm_private_state *priv_state;
3918 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3919 if (IS_ERR(priv_state))
3920 return PTR_ERR(priv_state);
3922 *dm_state = to_dm_atomic_state(priv_state);
3927 static struct dm_atomic_state *
3928 dm_atomic_get_new_state(struct drm_atomic_state *state)
3930 struct drm_device *dev = state->dev;
3931 struct amdgpu_device *adev = drm_to_adev(dev);
3932 struct amdgpu_display_manager *dm = &adev->dm;
3933 struct drm_private_obj *obj;
3934 struct drm_private_state *new_obj_state;
3937 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3938 if (obj->funcs == dm->atomic_obj.funcs)
3939 return to_dm_atomic_state(new_obj_state);
3945 static struct drm_private_state *
3946 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3948 struct dm_atomic_state *old_state, *new_state;
3950 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3954 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3956 old_state = to_dm_atomic_state(obj->state);
3958 if (old_state && old_state->context)
3959 new_state->context = dc_copy_state(old_state->context);
3961 if (!new_state->context) {
3966 return &new_state->base;
3969 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3970 struct drm_private_state *state)
3972 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3974 if (dm_state && dm_state->context)
3975 dc_release_state(dm_state->context);
3980 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3981 .atomic_duplicate_state = dm_atomic_duplicate_state,
3982 .atomic_destroy_state = dm_atomic_destroy_state,
3985 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3987 struct dm_atomic_state *state;
3990 adev->mode_info.mode_config_initialized = true;
3992 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3993 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3995 adev_to_drm(adev)->mode_config.max_width = 16384;
3996 adev_to_drm(adev)->mode_config.max_height = 16384;
3998 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3999 if (adev->asic_type == CHIP_HAWAII)
4000 /* disable prefer shadow for now due to hibernation issues */
4001 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4003 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4004 /* indicates support for immediate flip */
4005 adev_to_drm(adev)->mode_config.async_page_flip = true;
4007 state = kzalloc(sizeof(*state), GFP_KERNEL);
4011 state->context = dc_create_state(adev->dm.dc);
4012 if (!state->context) {
4017 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4019 drm_atomic_private_obj_init(adev_to_drm(adev),
4020 &adev->dm.atomic_obj,
4022 &dm_atomic_state_funcs);
4024 r = amdgpu_display_modeset_create_props(adev);
4026 dc_release_state(state->context);
4031 r = amdgpu_dm_audio_init(adev);
4033 dc_release_state(state->context);
4041 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4042 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4043 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4045 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4048 #if defined(CONFIG_ACPI)
4049 struct amdgpu_dm_backlight_caps caps;
4051 memset(&caps, 0, sizeof(caps));
4053 if (dm->backlight_caps[bl_idx].caps_valid)
4056 amdgpu_acpi_get_backlight_caps(&caps);
4057 if (caps.caps_valid) {
4058 dm->backlight_caps[bl_idx].caps_valid = true;
4059 if (caps.aux_support)
4061 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4062 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4064 dm->backlight_caps[bl_idx].min_input_signal =
4065 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4066 dm->backlight_caps[bl_idx].max_input_signal =
4067 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4070 if (dm->backlight_caps[bl_idx].aux_support)
4073 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4074 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4078 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4079 unsigned int *min, unsigned int *max)
4084 if (caps->aux_support) {
4085 // Firmware limits are in nits, DC API wants millinits.
4086 *max = 1000 * caps->aux_max_input_signal;
4087 *min = 1000 * caps->aux_min_input_signal;
4089 // Firmware limits are 8-bit, PWM control is 16-bit.
4090 *max = 0x101 * caps->max_input_signal;
4091 *min = 0x101 * caps->min_input_signal;
4096 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4097 uint32_t brightness)
4099 unsigned int min, max;
4101 if (!get_brightness_range(caps, &min, &max))
4104 // Rescale 0..255 to min..max
4105 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4106 AMDGPU_MAX_BL_LEVEL);
4109 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4110 uint32_t brightness)
4112 unsigned int min, max;
4114 if (!get_brightness_range(caps, &min, &max))
4117 if (brightness < min)
4119 // Rescale min..max to 0..255
4120 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4124 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4126 u32 user_brightness)
4128 struct amdgpu_dm_backlight_caps caps;
4129 struct dc_link *link;
4133 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4134 caps = dm->backlight_caps[bl_idx];
4136 dm->brightness[bl_idx] = user_brightness;
4137 /* update scratch register */
4139 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4140 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4141 link = (struct dc_link *)dm->backlight_link[bl_idx];
4143 /* Change brightness based on AUX property */
4144 if (caps.aux_support) {
4145 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4146 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4148 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4150 rc = dc_link_set_backlight_level(link, brightness, 0);
4152 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4156 dm->actual_brightness[bl_idx] = user_brightness;
4159 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4161 struct amdgpu_display_manager *dm = bl_get_data(bd);
4164 for (i = 0; i < dm->num_of_edps; i++) {
4165 if (bd == dm->backlight_dev[i])
4168 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4170 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4175 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4179 struct amdgpu_dm_backlight_caps caps;
4180 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4182 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4183 caps = dm->backlight_caps[bl_idx];
4185 if (caps.aux_support) {
4189 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4191 return dm->brightness[bl_idx];
4192 return convert_brightness_to_user(&caps, avg);
4195 ret = dc_link_get_backlight_level(link);
4197 if (ret == DC_ERROR_UNEXPECTED)
4198 return dm->brightness[bl_idx];
4200 return convert_brightness_to_user(&caps, ret);
4203 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4205 struct amdgpu_display_manager *dm = bl_get_data(bd);
4208 for (i = 0; i < dm->num_of_edps; i++) {
4209 if (bd == dm->backlight_dev[i])
4212 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4214 return amdgpu_dm_backlight_get_level(dm, i);
4217 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4218 .options = BL_CORE_SUSPENDRESUME,
4219 .get_brightness = amdgpu_dm_backlight_get_brightness,
4220 .update_status = amdgpu_dm_backlight_update_status,
4224 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4226 struct drm_device *drm = aconnector->base.dev;
4227 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4228 struct backlight_properties props = { 0 };
4231 if (aconnector->bl_idx == -1)
4234 if (!acpi_video_backlight_use_native()) {
4235 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4236 /* Try registering an ACPI video backlight device instead. */
4237 acpi_video_register_backlight();
4241 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4242 props.brightness = AMDGPU_MAX_BL_LEVEL;
4243 props.type = BACKLIGHT_RAW;
4245 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4246 drm->primary->index + aconnector->bl_idx);
4248 dm->backlight_dev[aconnector->bl_idx] =
4249 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4250 &amdgpu_dm_backlight_ops, &props);
4252 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4253 DRM_ERROR("DM: Backlight registration failed!\n");
4254 dm->backlight_dev[aconnector->bl_idx] = NULL;
4256 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4259 static int initialize_plane(struct amdgpu_display_manager *dm,
4260 struct amdgpu_mode_info *mode_info, int plane_id,
4261 enum drm_plane_type plane_type,
4262 const struct dc_plane_cap *plane_cap)
4264 struct drm_plane *plane;
4265 unsigned long possible_crtcs;
4268 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4270 DRM_ERROR("KMS: Failed to allocate plane\n");
4273 plane->type = plane_type;
4276 * HACK: IGT tests expect that the primary plane for a CRTC
4277 * can only have one possible CRTC. Only expose support for
4278 * any CRTC if they're not going to be used as a primary plane
4279 * for a CRTC - like overlay or underlay planes.
4281 possible_crtcs = 1 << plane_id;
4282 if (plane_id >= dm->dc->caps.max_streams)
4283 possible_crtcs = 0xff;
4285 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4288 DRM_ERROR("KMS: Failed to initialize plane\n");
4294 mode_info->planes[plane_id] = plane;
4300 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4301 struct amdgpu_dm_connector *aconnector)
4303 struct dc_link *link = aconnector->dc_link;
4304 int bl_idx = dm->num_of_edps;
4306 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4307 link->type == dc_connection_none)
4310 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4311 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4315 aconnector->bl_idx = bl_idx;
4317 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4318 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4319 dm->backlight_link[bl_idx] = link;
4322 update_connector_ext_caps(aconnector);
4325 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4328 * In this architecture, the association
4329 * connector -> encoder -> crtc
4330 * id not really requried. The crtc and connector will hold the
4331 * display_index as an abstraction to use with DAL component
4333 * Returns 0 on success
4335 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4337 struct amdgpu_display_manager *dm = &adev->dm;
4339 struct amdgpu_dm_connector *aconnector = NULL;
4340 struct amdgpu_encoder *aencoder = NULL;
4341 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4344 enum dc_connection_type new_connection_type = dc_connection_none;
4345 const struct dc_plane_cap *plane;
4346 bool psr_feature_enabled = false;
4347 bool replay_feature_enabled = false;
4348 int max_overlay = dm->dc->caps.max_slave_planes;
4350 dm->display_indexes_num = dm->dc->caps.max_streams;
4351 /* Update the actual used number of crtc */
4352 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4354 amdgpu_dm_set_irq_funcs(adev);
4356 link_cnt = dm->dc->caps.max_links;
4357 if (amdgpu_dm_mode_config_init(dm->adev)) {
4358 DRM_ERROR("DM: Failed to initialize mode config\n");
4362 /* There is one primary plane per CRTC */
4363 primary_planes = dm->dc->caps.max_streams;
4364 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4367 * Initialize primary planes, implicit planes for legacy IOCTLS.
4368 * Order is reversed to match iteration order in atomic check.
4370 for (i = (primary_planes - 1); i >= 0; i--) {
4371 plane = &dm->dc->caps.planes[i];
4373 if (initialize_plane(dm, mode_info, i,
4374 DRM_PLANE_TYPE_PRIMARY, plane)) {
4375 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4381 * Initialize overlay planes, index starting after primary planes.
4382 * These planes have a higher DRM index than the primary planes since
4383 * they should be considered as having a higher z-order.
4384 * Order is reversed to match iteration order in atomic check.
4386 * Only support DCN for now, and only expose one so we don't encourage
4387 * userspace to use up all the pipes.
4389 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4390 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4392 /* Do not create overlay if MPO disabled */
4393 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4396 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4399 if (!plane->pixel_format_support.argb8888)
4402 if (max_overlay-- == 0)
4405 if (initialize_plane(dm, NULL, primary_planes + i,
4406 DRM_PLANE_TYPE_OVERLAY, plane)) {
4407 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4412 for (i = 0; i < dm->dc->caps.max_streams; i++)
4413 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4414 DRM_ERROR("KMS: Failed to initialize crtc\n");
4418 /* Use Outbox interrupt */
4419 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4420 case IP_VERSION(3, 0, 0):
4421 case IP_VERSION(3, 1, 2):
4422 case IP_VERSION(3, 1, 3):
4423 case IP_VERSION(3, 1, 4):
4424 case IP_VERSION(3, 1, 5):
4425 case IP_VERSION(3, 1, 6):
4426 case IP_VERSION(3, 2, 0):
4427 case IP_VERSION(3, 2, 1):
4428 case IP_VERSION(2, 1, 0):
4429 case IP_VERSION(3, 5, 0):
4430 if (register_outbox_irq_handlers(dm->adev)) {
4431 DRM_ERROR("DM: Failed to initialize IRQ\n");
4436 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4437 amdgpu_ip_version(adev, DCE_HWIP, 0));
4440 /* Determine whether to enable PSR support by default. */
4441 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4442 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4443 case IP_VERSION(3, 1, 2):
4444 case IP_VERSION(3, 1, 3):
4445 case IP_VERSION(3, 1, 4):
4446 case IP_VERSION(3, 1, 5):
4447 case IP_VERSION(3, 1, 6):
4448 case IP_VERSION(3, 2, 0):
4449 case IP_VERSION(3, 2, 1):
4450 case IP_VERSION(3, 5, 0):
4451 psr_feature_enabled = true;
4454 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4459 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4460 switch (adev->ip_versions[DCE_HWIP][0]) {
4461 case IP_VERSION(3, 1, 4):
4462 case IP_VERSION(3, 1, 5):
4463 case IP_VERSION(3, 1, 6):
4464 case IP_VERSION(3, 2, 0):
4465 case IP_VERSION(3, 2, 1):
4466 replay_feature_enabled = true;
4469 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4473 /* loops over all connectors on the board */
4474 for (i = 0; i < link_cnt; i++) {
4475 struct dc_link *link = NULL;
4477 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4479 "KMS: Cannot support more than %d display indexes\n",
4480 AMDGPU_DM_MAX_DISPLAY_INDEX);
4484 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4488 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4492 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4493 DRM_ERROR("KMS: Failed to initialize encoder\n");
4497 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4498 DRM_ERROR("KMS: Failed to initialize connector\n");
4502 link = dc_get_link_at_index(dm->dc, i);
4504 if (!dc_link_detect_connection_type(link, &new_connection_type))
4505 DRM_ERROR("KMS: Failed to detect connector\n");
4507 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4508 emulated_link_detect(link);
4509 amdgpu_dm_update_connector_after_detect(aconnector);
4513 mutex_lock(&dm->dc_lock);
4514 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4515 mutex_unlock(&dm->dc_lock);
4518 amdgpu_dm_update_connector_after_detect(aconnector);
4519 setup_backlight_device(dm, aconnector);
4522 * Disable psr if replay can be enabled
4524 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4525 psr_feature_enabled = false;
4527 if (psr_feature_enabled)
4528 amdgpu_dm_set_psr_caps(link);
4530 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4531 * PSR is also supported.
4533 if (link->psr_settings.psr_feature_enabled)
4534 adev_to_drm(adev)->vblank_disable_immediate = false;
4537 amdgpu_set_panel_orientation(&aconnector->base);
4540 /* Software is initialized. Now we can register interrupt handlers. */
4541 switch (adev->asic_type) {
4542 #if defined(CONFIG_DRM_AMD_DC_SI)
4547 if (dce60_register_irq_handlers(dm->adev)) {
4548 DRM_ERROR("DM: Failed to initialize IRQ\n");
4562 case CHIP_POLARIS11:
4563 case CHIP_POLARIS10:
4564 case CHIP_POLARIS12:
4569 if (dce110_register_irq_handlers(dm->adev)) {
4570 DRM_ERROR("DM: Failed to initialize IRQ\n");
4575 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4576 case IP_VERSION(1, 0, 0):
4577 case IP_VERSION(1, 0, 1):
4578 case IP_VERSION(2, 0, 2):
4579 case IP_VERSION(2, 0, 3):
4580 case IP_VERSION(2, 0, 0):
4581 case IP_VERSION(2, 1, 0):
4582 case IP_VERSION(3, 0, 0):
4583 case IP_VERSION(3, 0, 2):
4584 case IP_VERSION(3, 0, 3):
4585 case IP_VERSION(3, 0, 1):
4586 case IP_VERSION(3, 1, 2):
4587 case IP_VERSION(3, 1, 3):
4588 case IP_VERSION(3, 1, 4):
4589 case IP_VERSION(3, 1, 5):
4590 case IP_VERSION(3, 1, 6):
4591 case IP_VERSION(3, 2, 0):
4592 case IP_VERSION(3, 2, 1):
4593 case IP_VERSION(3, 5, 0):
4594 if (dcn10_register_irq_handlers(dm->adev)) {
4595 DRM_ERROR("DM: Failed to initialize IRQ\n");
4600 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4601 amdgpu_ip_version(adev, DCE_HWIP, 0));
4615 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4617 drm_atomic_private_obj_fini(&dm->atomic_obj);
4620 /******************************************************************************
4621 * amdgpu_display_funcs functions
4622 *****************************************************************************/
4625 * dm_bandwidth_update - program display watermarks
4627 * @adev: amdgpu_device pointer
4629 * Calculate and program the display watermarks and line buffer allocation.
4631 static void dm_bandwidth_update(struct amdgpu_device *adev)
4633 /* TODO: implement later */
4636 static const struct amdgpu_display_funcs dm_display_funcs = {
4637 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4638 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4639 .backlight_set_level = NULL, /* never called for DC */
4640 .backlight_get_level = NULL, /* never called for DC */
4641 .hpd_sense = NULL,/* called unconditionally */
4642 .hpd_set_polarity = NULL, /* called unconditionally */
4643 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4644 .page_flip_get_scanoutpos =
4645 dm_crtc_get_scanoutpos,/* called unconditionally */
4646 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4647 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4650 #if defined(CONFIG_DEBUG_KERNEL_DC)
4652 static ssize_t s3_debug_store(struct device *device,
4653 struct device_attribute *attr,
4659 struct drm_device *drm_dev = dev_get_drvdata(device);
4660 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4662 ret = kstrtoint(buf, 0, &s3_state);
4667 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4672 return ret == 0 ? count : 0;
4675 DEVICE_ATTR_WO(s3_debug);
4679 static int dm_init_microcode(struct amdgpu_device *adev)
4684 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4685 case IP_VERSION(2, 1, 0):
4686 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4687 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4688 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4690 case IP_VERSION(3, 0, 0):
4691 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4692 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4694 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4696 case IP_VERSION(3, 0, 1):
4697 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4699 case IP_VERSION(3, 0, 2):
4700 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4702 case IP_VERSION(3, 0, 3):
4703 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4705 case IP_VERSION(3, 1, 2):
4706 case IP_VERSION(3, 1, 3):
4707 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4709 case IP_VERSION(3, 1, 4):
4710 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4712 case IP_VERSION(3, 1, 5):
4713 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4715 case IP_VERSION(3, 1, 6):
4716 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4718 case IP_VERSION(3, 2, 0):
4719 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4721 case IP_VERSION(3, 2, 1):
4722 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4724 case IP_VERSION(3, 5, 0):
4725 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4728 /* ASIC doesn't support DMUB. */
4731 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4735 static int dm_early_init(void *handle)
4737 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4738 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4739 struct atom_context *ctx = mode_info->atom_context;
4740 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4743 /* if there is no object header, skip DM */
4744 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4745 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4746 dev_info(adev->dev, "No object header, skipping DM\n");
4750 switch (adev->asic_type) {
4751 #if defined(CONFIG_DRM_AMD_DC_SI)
4755 adev->mode_info.num_crtc = 6;
4756 adev->mode_info.num_hpd = 6;
4757 adev->mode_info.num_dig = 6;
4760 adev->mode_info.num_crtc = 2;
4761 adev->mode_info.num_hpd = 2;
4762 adev->mode_info.num_dig = 2;
4767 adev->mode_info.num_crtc = 6;
4768 adev->mode_info.num_hpd = 6;
4769 adev->mode_info.num_dig = 6;
4772 adev->mode_info.num_crtc = 4;
4773 adev->mode_info.num_hpd = 6;
4774 adev->mode_info.num_dig = 7;
4778 adev->mode_info.num_crtc = 2;
4779 adev->mode_info.num_hpd = 6;
4780 adev->mode_info.num_dig = 6;
4784 adev->mode_info.num_crtc = 6;
4785 adev->mode_info.num_hpd = 6;
4786 adev->mode_info.num_dig = 7;
4789 adev->mode_info.num_crtc = 3;
4790 adev->mode_info.num_hpd = 6;
4791 adev->mode_info.num_dig = 9;
4794 adev->mode_info.num_crtc = 2;
4795 adev->mode_info.num_hpd = 6;
4796 adev->mode_info.num_dig = 9;
4798 case CHIP_POLARIS11:
4799 case CHIP_POLARIS12:
4800 adev->mode_info.num_crtc = 5;
4801 adev->mode_info.num_hpd = 5;
4802 adev->mode_info.num_dig = 5;
4804 case CHIP_POLARIS10:
4806 adev->mode_info.num_crtc = 6;
4807 adev->mode_info.num_hpd = 6;
4808 adev->mode_info.num_dig = 6;
4813 adev->mode_info.num_crtc = 6;
4814 adev->mode_info.num_hpd = 6;
4815 adev->mode_info.num_dig = 6;
4819 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4820 case IP_VERSION(2, 0, 2):
4821 case IP_VERSION(3, 0, 0):
4822 adev->mode_info.num_crtc = 6;
4823 adev->mode_info.num_hpd = 6;
4824 adev->mode_info.num_dig = 6;
4826 case IP_VERSION(2, 0, 0):
4827 case IP_VERSION(3, 0, 2):
4828 adev->mode_info.num_crtc = 5;
4829 adev->mode_info.num_hpd = 5;
4830 adev->mode_info.num_dig = 5;
4832 case IP_VERSION(2, 0, 3):
4833 case IP_VERSION(3, 0, 3):
4834 adev->mode_info.num_crtc = 2;
4835 adev->mode_info.num_hpd = 2;
4836 adev->mode_info.num_dig = 2;
4838 case IP_VERSION(1, 0, 0):
4839 case IP_VERSION(1, 0, 1):
4840 case IP_VERSION(3, 0, 1):
4841 case IP_VERSION(2, 1, 0):
4842 case IP_VERSION(3, 1, 2):
4843 case IP_VERSION(3, 1, 3):
4844 case IP_VERSION(3, 1, 4):
4845 case IP_VERSION(3, 1, 5):
4846 case IP_VERSION(3, 1, 6):
4847 case IP_VERSION(3, 2, 0):
4848 case IP_VERSION(3, 2, 1):
4849 case IP_VERSION(3, 5, 0):
4850 adev->mode_info.num_crtc = 4;
4851 adev->mode_info.num_hpd = 4;
4852 adev->mode_info.num_dig = 4;
4855 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4856 amdgpu_ip_version(adev, DCE_HWIP, 0));
4862 if (adev->mode_info.funcs == NULL)
4863 adev->mode_info.funcs = &dm_display_funcs;
4866 * Note: Do NOT change adev->audio_endpt_rreg and
4867 * adev->audio_endpt_wreg because they are initialised in
4868 * amdgpu_device_init()
4870 #if defined(CONFIG_DEBUG_KERNEL_DC)
4872 adev_to_drm(adev)->dev,
4873 &dev_attr_s3_debug);
4875 adev->dc_enabled = true;
4877 return dm_init_microcode(adev);
4880 static bool modereset_required(struct drm_crtc_state *crtc_state)
4882 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4885 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4887 drm_encoder_cleanup(encoder);
4891 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4892 .destroy = amdgpu_dm_encoder_destroy,
4896 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4897 const enum surface_pixel_format format,
4898 enum dc_color_space *color_space)
4902 *color_space = COLOR_SPACE_SRGB;
4904 /* DRM color properties only affect non-RGB formats. */
4905 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4908 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4910 switch (plane_state->color_encoding) {
4911 case DRM_COLOR_YCBCR_BT601:
4913 *color_space = COLOR_SPACE_YCBCR601;
4915 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4918 case DRM_COLOR_YCBCR_BT709:
4920 *color_space = COLOR_SPACE_YCBCR709;
4922 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4925 case DRM_COLOR_YCBCR_BT2020:
4927 *color_space = COLOR_SPACE_2020_YCBCR;
4940 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4941 const struct drm_plane_state *plane_state,
4942 const u64 tiling_flags,
4943 struct dc_plane_info *plane_info,
4944 struct dc_plane_address *address,
4946 bool force_disable_dcc)
4948 const struct drm_framebuffer *fb = plane_state->fb;
4949 const struct amdgpu_framebuffer *afb =
4950 to_amdgpu_framebuffer(plane_state->fb);
4953 memset(plane_info, 0, sizeof(*plane_info));
4955 switch (fb->format->format) {
4957 plane_info->format =
4958 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4960 case DRM_FORMAT_RGB565:
4961 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4963 case DRM_FORMAT_XRGB8888:
4964 case DRM_FORMAT_ARGB8888:
4965 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4967 case DRM_FORMAT_XRGB2101010:
4968 case DRM_FORMAT_ARGB2101010:
4969 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4971 case DRM_FORMAT_XBGR2101010:
4972 case DRM_FORMAT_ABGR2101010:
4973 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4975 case DRM_FORMAT_XBGR8888:
4976 case DRM_FORMAT_ABGR8888:
4977 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4979 case DRM_FORMAT_NV21:
4980 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4982 case DRM_FORMAT_NV12:
4983 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4985 case DRM_FORMAT_P010:
4986 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4988 case DRM_FORMAT_XRGB16161616F:
4989 case DRM_FORMAT_ARGB16161616F:
4990 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4992 case DRM_FORMAT_XBGR16161616F:
4993 case DRM_FORMAT_ABGR16161616F:
4994 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4996 case DRM_FORMAT_XRGB16161616:
4997 case DRM_FORMAT_ARGB16161616:
4998 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5000 case DRM_FORMAT_XBGR16161616:
5001 case DRM_FORMAT_ABGR16161616:
5002 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5006 "Unsupported screen format %p4cc\n",
5007 &fb->format->format);
5011 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5012 case DRM_MODE_ROTATE_0:
5013 plane_info->rotation = ROTATION_ANGLE_0;
5015 case DRM_MODE_ROTATE_90:
5016 plane_info->rotation = ROTATION_ANGLE_90;
5018 case DRM_MODE_ROTATE_180:
5019 plane_info->rotation = ROTATION_ANGLE_180;
5021 case DRM_MODE_ROTATE_270:
5022 plane_info->rotation = ROTATION_ANGLE_270;
5025 plane_info->rotation = ROTATION_ANGLE_0;
5030 plane_info->visible = true;
5031 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5033 plane_info->layer_index = plane_state->normalized_zpos;
5035 ret = fill_plane_color_attributes(plane_state, plane_info->format,
5036 &plane_info->color_space);
5040 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5041 plane_info->rotation, tiling_flags,
5042 &plane_info->tiling_info,
5043 &plane_info->plane_size,
5044 &plane_info->dcc, address,
5045 tmz_surface, force_disable_dcc);
5049 amdgpu_dm_plane_fill_blending_from_plane_state(
5050 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5051 &plane_info->global_alpha, &plane_info->global_alpha_value);
5056 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5057 struct dc_plane_state *dc_plane_state,
5058 struct drm_plane_state *plane_state,
5059 struct drm_crtc_state *crtc_state)
5061 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5062 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5063 struct dc_scaling_info scaling_info;
5064 struct dc_plane_info plane_info;
5066 bool force_disable_dcc = false;
5068 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5072 dc_plane_state->src_rect = scaling_info.src_rect;
5073 dc_plane_state->dst_rect = scaling_info.dst_rect;
5074 dc_plane_state->clip_rect = scaling_info.clip_rect;
5075 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5077 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5078 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5081 &dc_plane_state->address,
5087 dc_plane_state->format = plane_info.format;
5088 dc_plane_state->color_space = plane_info.color_space;
5089 dc_plane_state->format = plane_info.format;
5090 dc_plane_state->plane_size = plane_info.plane_size;
5091 dc_plane_state->rotation = plane_info.rotation;
5092 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5093 dc_plane_state->stereo_format = plane_info.stereo_format;
5094 dc_plane_state->tiling_info = plane_info.tiling_info;
5095 dc_plane_state->visible = plane_info.visible;
5096 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5097 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5098 dc_plane_state->global_alpha = plane_info.global_alpha;
5099 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5100 dc_plane_state->dcc = plane_info.dcc;
5101 dc_plane_state->layer_index = plane_info.layer_index;
5102 dc_plane_state->flip_int_enabled = true;
5105 * Always set input transfer function, since plane state is refreshed
5108 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5115 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5116 struct rect *dirty_rect, int32_t x,
5117 s32 y, s32 width, s32 height,
5120 WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5124 dirty_rect->width = width;
5125 dirty_rect->height = height;
5129 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5130 plane->base.id, width, height);
5133 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5134 plane->base.id, x, y, width, height);
5140 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5142 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5144 * @old_plane_state: Old state of @plane
5145 * @new_plane_state: New state of @plane
5146 * @crtc_state: New state of CRTC connected to the @plane
5147 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5148 * @dirty_regions_changed: dirty regions changed
5150 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5151 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5152 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5155 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5156 * plane with regions that require flushing to the eDP remote buffer. In
5157 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5158 * implicitly provide damage clips without any client support via the plane
5161 static void fill_dc_dirty_rects(struct drm_plane *plane,
5162 struct drm_plane_state *old_plane_state,
5163 struct drm_plane_state *new_plane_state,
5164 struct drm_crtc_state *crtc_state,
5165 struct dc_flip_addrs *flip_addrs,
5166 bool *dirty_regions_changed)
5168 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5169 struct rect *dirty_rects = flip_addrs->dirty_rects;
5171 struct drm_mode_rect *clips;
5175 *dirty_regions_changed = false;
5178 * Cursor plane has it's own dirty rect update interface. See
5179 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5181 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5184 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5185 clips = drm_plane_get_damage_clips(new_plane_state);
5187 if (!dm_crtc_state->mpo_requested) {
5188 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5191 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5192 fill_dc_dirty_rect(new_plane_state->plane,
5193 &dirty_rects[flip_addrs->dirty_rect_count],
5194 clips->x1, clips->y1,
5195 clips->x2 - clips->x1, clips->y2 - clips->y1,
5196 &flip_addrs->dirty_rect_count,
5202 * MPO is requested. Add entire plane bounding box to dirty rects if
5203 * flipped to or damaged.
5205 * If plane is moved or resized, also add old bounding box to dirty
5208 fb_changed = old_plane_state->fb->base.id !=
5209 new_plane_state->fb->base.id;
5210 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5211 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5212 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5213 old_plane_state->crtc_h != new_plane_state->crtc_h);
5216 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5217 new_plane_state->plane->base.id,
5218 bb_changed, fb_changed, num_clips);
5220 *dirty_regions_changed = bb_changed;
5222 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5226 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5227 new_plane_state->crtc_x,
5228 new_plane_state->crtc_y,
5229 new_plane_state->crtc_w,
5230 new_plane_state->crtc_h, &i, false);
5232 /* Add old plane bounding-box if plane is moved or resized */
5233 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5234 old_plane_state->crtc_x,
5235 old_plane_state->crtc_y,
5236 old_plane_state->crtc_w,
5237 old_plane_state->crtc_h, &i, false);
5241 for (; i < num_clips; clips++)
5242 fill_dc_dirty_rect(new_plane_state->plane,
5243 &dirty_rects[i], clips->x1,
5244 clips->y1, clips->x2 - clips->x1,
5245 clips->y2 - clips->y1, &i, false);
5246 } else if (fb_changed && !bb_changed) {
5247 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5248 new_plane_state->crtc_x,
5249 new_plane_state->crtc_y,
5250 new_plane_state->crtc_w,
5251 new_plane_state->crtc_h, &i, false);
5254 flip_addrs->dirty_rect_count = i;
5258 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5259 dm_crtc_state->base.mode.crtc_hdisplay,
5260 dm_crtc_state->base.mode.crtc_vdisplay,
5261 &flip_addrs->dirty_rect_count, true);
5264 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5265 const struct dm_connector_state *dm_state,
5266 struct dc_stream_state *stream)
5268 enum amdgpu_rmx_type rmx_type;
5270 struct rect src = { 0 }; /* viewport in composition space*/
5271 struct rect dst = { 0 }; /* stream addressable area */
5273 /* no mode. nothing to be done */
5277 /* Full screen scaling by default */
5278 src.width = mode->hdisplay;
5279 src.height = mode->vdisplay;
5280 dst.width = stream->timing.h_addressable;
5281 dst.height = stream->timing.v_addressable;
5284 rmx_type = dm_state->scaling;
5285 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5286 if (src.width * dst.height <
5287 src.height * dst.width) {
5288 /* height needs less upscaling/more downscaling */
5289 dst.width = src.width *
5290 dst.height / src.height;
5292 /* width needs less upscaling/more downscaling */
5293 dst.height = src.height *
5294 dst.width / src.width;
5296 } else if (rmx_type == RMX_CENTER) {
5300 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5301 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5303 if (dm_state->underscan_enable) {
5304 dst.x += dm_state->underscan_hborder / 2;
5305 dst.y += dm_state->underscan_vborder / 2;
5306 dst.width -= dm_state->underscan_hborder;
5307 dst.height -= dm_state->underscan_vborder;
5314 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5315 dst.x, dst.y, dst.width, dst.height);
5319 static enum dc_color_depth
5320 convert_color_depth_from_display_info(const struct drm_connector *connector,
5321 bool is_y420, int requested_bpc)
5328 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5329 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5331 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5333 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5336 bpc = (uint8_t)connector->display_info.bpc;
5337 /* Assume 8 bpc by default if no bpc is specified. */
5338 bpc = bpc ? bpc : 8;
5341 if (requested_bpc > 0) {
5343 * Cap display bpc based on the user requested value.
5345 * The value for state->max_bpc may not correctly updated
5346 * depending on when the connector gets added to the state
5347 * or if this was called outside of atomic check, so it
5348 * can't be used directly.
5350 bpc = min_t(u8, bpc, requested_bpc);
5352 /* Round down to the nearest even number. */
5353 bpc = bpc - (bpc & 1);
5359 * Temporary Work around, DRM doesn't parse color depth for
5360 * EDID revision before 1.4
5361 * TODO: Fix edid parsing
5363 return COLOR_DEPTH_888;
5365 return COLOR_DEPTH_666;
5367 return COLOR_DEPTH_888;
5369 return COLOR_DEPTH_101010;
5371 return COLOR_DEPTH_121212;
5373 return COLOR_DEPTH_141414;
5375 return COLOR_DEPTH_161616;
5377 return COLOR_DEPTH_UNDEFINED;
5381 static enum dc_aspect_ratio
5382 get_aspect_ratio(const struct drm_display_mode *mode_in)
5384 /* 1-1 mapping, since both enums follow the HDMI spec. */
5385 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5388 static enum dc_color_space
5389 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5390 const struct drm_connector_state *connector_state)
5392 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5394 switch (connector_state->colorspace) {
5395 case DRM_MODE_COLORIMETRY_BT601_YCC:
5396 if (dc_crtc_timing->flags.Y_ONLY)
5397 color_space = COLOR_SPACE_YCBCR601_LIMITED;
5399 color_space = COLOR_SPACE_YCBCR601;
5401 case DRM_MODE_COLORIMETRY_BT709_YCC:
5402 if (dc_crtc_timing->flags.Y_ONLY)
5403 color_space = COLOR_SPACE_YCBCR709_LIMITED;
5405 color_space = COLOR_SPACE_YCBCR709;
5407 case DRM_MODE_COLORIMETRY_OPRGB:
5408 color_space = COLOR_SPACE_ADOBERGB;
5410 case DRM_MODE_COLORIMETRY_BT2020_RGB:
5411 case DRM_MODE_COLORIMETRY_BT2020_YCC:
5412 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5413 color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5415 color_space = COLOR_SPACE_2020_YCBCR;
5417 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5419 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5420 color_space = COLOR_SPACE_SRGB;
5422 * 27030khz is the separation point between HDTV and SDTV
5423 * according to HDMI spec, we use YCbCr709 and YCbCr601
5426 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5427 if (dc_crtc_timing->flags.Y_ONLY)
5429 COLOR_SPACE_YCBCR709_LIMITED;
5431 color_space = COLOR_SPACE_YCBCR709;
5433 if (dc_crtc_timing->flags.Y_ONLY)
5435 COLOR_SPACE_YCBCR601_LIMITED;
5437 color_space = COLOR_SPACE_YCBCR601;
5445 static enum display_content_type
5446 get_output_content_type(const struct drm_connector_state *connector_state)
5448 switch (connector_state->content_type) {
5450 case DRM_MODE_CONTENT_TYPE_NO_DATA:
5451 return DISPLAY_CONTENT_TYPE_NO_DATA;
5452 case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5453 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5454 case DRM_MODE_CONTENT_TYPE_PHOTO:
5455 return DISPLAY_CONTENT_TYPE_PHOTO;
5456 case DRM_MODE_CONTENT_TYPE_CINEMA:
5457 return DISPLAY_CONTENT_TYPE_CINEMA;
5458 case DRM_MODE_CONTENT_TYPE_GAME:
5459 return DISPLAY_CONTENT_TYPE_GAME;
5463 static bool adjust_colour_depth_from_display_info(
5464 struct dc_crtc_timing *timing_out,
5465 const struct drm_display_info *info)
5467 enum dc_color_depth depth = timing_out->display_color_depth;
5471 normalized_clk = timing_out->pix_clk_100hz / 10;
5472 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5473 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5474 normalized_clk /= 2;
5475 /* Adjusting pix clock following on HDMI spec based on colour depth */
5477 case COLOR_DEPTH_888:
5479 case COLOR_DEPTH_101010:
5480 normalized_clk = (normalized_clk * 30) / 24;
5482 case COLOR_DEPTH_121212:
5483 normalized_clk = (normalized_clk * 36) / 24;
5485 case COLOR_DEPTH_161616:
5486 normalized_clk = (normalized_clk * 48) / 24;
5489 /* The above depths are the only ones valid for HDMI. */
5492 if (normalized_clk <= info->max_tmds_clock) {
5493 timing_out->display_color_depth = depth;
5496 } while (--depth > COLOR_DEPTH_666);
5500 static void fill_stream_properties_from_drm_display_mode(
5501 struct dc_stream_state *stream,
5502 const struct drm_display_mode *mode_in,
5503 const struct drm_connector *connector,
5504 const struct drm_connector_state *connector_state,
5505 const struct dc_stream_state *old_stream,
5508 struct dc_crtc_timing *timing_out = &stream->timing;
5509 const struct drm_display_info *info = &connector->display_info;
5510 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5511 struct hdmi_vendor_infoframe hv_frame;
5512 struct hdmi_avi_infoframe avi_frame;
5514 memset(&hv_frame, 0, sizeof(hv_frame));
5515 memset(&avi_frame, 0, sizeof(avi_frame));
5517 timing_out->h_border_left = 0;
5518 timing_out->h_border_right = 0;
5519 timing_out->v_border_top = 0;
5520 timing_out->v_border_bottom = 0;
5521 /* TODO: un-hardcode */
5522 if (drm_mode_is_420_only(info, mode_in)
5523 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5524 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5525 else if (drm_mode_is_420_also(info, mode_in)
5526 && aconnector->force_yuv420_output)
5527 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5528 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5529 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5530 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5532 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5534 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5535 timing_out->display_color_depth = convert_color_depth_from_display_info(
5537 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5539 timing_out->scan_type = SCANNING_TYPE_NODATA;
5540 timing_out->hdmi_vic = 0;
5543 timing_out->vic = old_stream->timing.vic;
5544 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5545 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5547 timing_out->vic = drm_match_cea_mode(mode_in);
5548 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5549 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5550 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5551 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5554 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5555 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5556 timing_out->vic = avi_frame.video_code;
5557 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5558 timing_out->hdmi_vic = hv_frame.vic;
5561 if (is_freesync_video_mode(mode_in, aconnector)) {
5562 timing_out->h_addressable = mode_in->hdisplay;
5563 timing_out->h_total = mode_in->htotal;
5564 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5565 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5566 timing_out->v_total = mode_in->vtotal;
5567 timing_out->v_addressable = mode_in->vdisplay;
5568 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5569 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5570 timing_out->pix_clk_100hz = mode_in->clock * 10;
5572 timing_out->h_addressable = mode_in->crtc_hdisplay;
5573 timing_out->h_total = mode_in->crtc_htotal;
5574 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5575 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5576 timing_out->v_total = mode_in->crtc_vtotal;
5577 timing_out->v_addressable = mode_in->crtc_vdisplay;
5578 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5579 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5580 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5583 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5585 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5586 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5587 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5588 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5589 drm_mode_is_420_also(info, mode_in) &&
5590 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5591 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5592 adjust_colour_depth_from_display_info(timing_out, info);
5596 stream->output_color_space = get_output_color_space(timing_out, connector_state);
5597 stream->content_type = get_output_content_type(connector_state);
5600 static void fill_audio_info(struct audio_info *audio_info,
5601 const struct drm_connector *drm_connector,
5602 const struct dc_sink *dc_sink)
5605 int cea_revision = 0;
5606 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5608 audio_info->manufacture_id = edid_caps->manufacturer_id;
5609 audio_info->product_id = edid_caps->product_id;
5611 cea_revision = drm_connector->display_info.cea_rev;
5613 strscpy(audio_info->display_name,
5614 edid_caps->display_name,
5615 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5617 if (cea_revision >= 3) {
5618 audio_info->mode_count = edid_caps->audio_mode_count;
5620 for (i = 0; i < audio_info->mode_count; ++i) {
5621 audio_info->modes[i].format_code =
5622 (enum audio_format_code)
5623 (edid_caps->audio_modes[i].format_code);
5624 audio_info->modes[i].channel_count =
5625 edid_caps->audio_modes[i].channel_count;
5626 audio_info->modes[i].sample_rates.all =
5627 edid_caps->audio_modes[i].sample_rate;
5628 audio_info->modes[i].sample_size =
5629 edid_caps->audio_modes[i].sample_size;
5633 audio_info->flags.all = edid_caps->speaker_flags;
5635 /* TODO: We only check for the progressive mode, check for interlace mode too */
5636 if (drm_connector->latency_present[0]) {
5637 audio_info->video_latency = drm_connector->video_latency[0];
5638 audio_info->audio_latency = drm_connector->audio_latency[0];
5641 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5646 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5647 struct drm_display_mode *dst_mode)
5649 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5650 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5651 dst_mode->crtc_clock = src_mode->crtc_clock;
5652 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5653 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5654 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5655 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5656 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5657 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5658 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5659 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5660 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5661 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5662 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5666 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5667 const struct drm_display_mode *native_mode,
5670 if (scale_enabled) {
5671 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5672 } else if (native_mode->clock == drm_mode->clock &&
5673 native_mode->htotal == drm_mode->htotal &&
5674 native_mode->vtotal == drm_mode->vtotal) {
5675 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5677 /* no scaling nor amdgpu inserted, no need to patch */
5681 static struct dc_sink *
5682 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5684 struct dc_sink_init_data sink_init_data = { 0 };
5685 struct dc_sink *sink = NULL;
5687 sink_init_data.link = aconnector->dc_link;
5688 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5690 sink = dc_sink_create(&sink_init_data);
5692 DRM_ERROR("Failed to create sink!\n");
5695 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5700 static void set_multisync_trigger_params(
5701 struct dc_stream_state *stream)
5703 struct dc_stream_state *master = NULL;
5705 if (stream->triggered_crtc_reset.enabled) {
5706 master = stream->triggered_crtc_reset.event_source;
5707 stream->triggered_crtc_reset.event =
5708 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5709 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5710 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5714 static void set_master_stream(struct dc_stream_state *stream_set[],
5717 int j, highest_rfr = 0, master_stream = 0;
5719 for (j = 0; j < stream_count; j++) {
5720 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5721 int refresh_rate = 0;
5723 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5724 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5725 if (refresh_rate > highest_rfr) {
5726 highest_rfr = refresh_rate;
5731 for (j = 0; j < stream_count; j++) {
5733 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5737 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5740 struct dc_stream_state *stream;
5742 if (context->stream_count < 2)
5744 for (i = 0; i < context->stream_count ; i++) {
5745 if (!context->streams[i])
5748 * TODO: add a function to read AMD VSDB bits and set
5749 * crtc_sync_master.multi_sync_enabled flag
5750 * For now it's set to false
5754 set_master_stream(context->streams, context->stream_count);
5756 for (i = 0; i < context->stream_count ; i++) {
5757 stream = context->streams[i];
5762 set_multisync_trigger_params(stream);
5767 * DOC: FreeSync Video
5769 * When a userspace application wants to play a video, the content follows a
5770 * standard format definition that usually specifies the FPS for that format.
5771 * The below list illustrates some video format and the expected FPS,
5774 * - TV/NTSC (23.976 FPS)
5777 * - TV/NTSC (29.97 FPS)
5778 * - TV/NTSC (30 FPS)
5779 * - Cinema HFR (48 FPS)
5781 * - Commonly used (60 FPS)
5782 * - Multiples of 24 (48,72,96 FPS)
5784 * The list of standards video format is not huge and can be added to the
5785 * connector modeset list beforehand. With that, userspace can leverage
5786 * FreeSync to extends the front porch in order to attain the target refresh
5787 * rate. Such a switch will happen seamlessly, without screen blanking or
5788 * reprogramming of the output in any other way. If the userspace requests a
5789 * modesetting change compatible with FreeSync modes that only differ in the
5790 * refresh rate, DC will skip the full update and avoid blink during the
5791 * transition. For example, the video player can change the modesetting from
5792 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5793 * causing any display blink. This same concept can be applied to a mode
5796 static struct drm_display_mode *
5797 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5798 bool use_probed_modes)
5800 struct drm_display_mode *m, *m_pref = NULL;
5801 u16 current_refresh, highest_refresh;
5802 struct list_head *list_head = use_probed_modes ?
5803 &aconnector->base.probed_modes :
5804 &aconnector->base.modes;
5806 if (aconnector->freesync_vid_base.clock != 0)
5807 return &aconnector->freesync_vid_base;
5809 /* Find the preferred mode */
5810 list_for_each_entry(m, list_head, head) {
5811 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5818 /* Probably an EDID with no preferred mode. Fallback to first entry */
5819 m_pref = list_first_entry_or_null(
5820 &aconnector->base.modes, struct drm_display_mode, head);
5822 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5827 highest_refresh = drm_mode_vrefresh(m_pref);
5830 * Find the mode with highest refresh rate with same resolution.
5831 * For some monitors, preferred mode is not the mode with highest
5832 * supported refresh rate.
5834 list_for_each_entry(m, list_head, head) {
5835 current_refresh = drm_mode_vrefresh(m);
5837 if (m->hdisplay == m_pref->hdisplay &&
5838 m->vdisplay == m_pref->vdisplay &&
5839 highest_refresh < current_refresh) {
5840 highest_refresh = current_refresh;
5845 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5849 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5850 struct amdgpu_dm_connector *aconnector)
5852 struct drm_display_mode *high_mode;
5855 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5856 if (!high_mode || !mode)
5859 timing_diff = high_mode->vtotal - mode->vtotal;
5861 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5862 high_mode->hdisplay != mode->hdisplay ||
5863 high_mode->vdisplay != mode->vdisplay ||
5864 high_mode->hsync_start != mode->hsync_start ||
5865 high_mode->hsync_end != mode->hsync_end ||
5866 high_mode->htotal != mode->htotal ||
5867 high_mode->hskew != mode->hskew ||
5868 high_mode->vscan != mode->vscan ||
5869 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5870 high_mode->vsync_end - mode->vsync_end != timing_diff)
5876 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5877 struct dc_sink *sink, struct dc_stream_state *stream,
5878 struct dsc_dec_dpcd_caps *dsc_caps)
5880 stream->timing.flags.DSC = 0;
5881 dsc_caps->is_dsc_supported = false;
5883 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5884 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5885 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5886 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5887 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5888 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5889 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5895 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5896 struct dc_sink *sink, struct dc_stream_state *stream,
5897 struct dsc_dec_dpcd_caps *dsc_caps,
5898 uint32_t max_dsc_target_bpp_limit_override)
5900 const struct dc_link_settings *verified_link_cap = NULL;
5901 u32 link_bw_in_kbps;
5902 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5903 struct dc *dc = sink->ctx->dc;
5904 struct dc_dsc_bw_range bw_range = {0};
5905 struct dc_dsc_config dsc_cfg = {0};
5906 struct dc_dsc_config_options dsc_options = {0};
5908 dc_dsc_get_default_config_option(dc, &dsc_options);
5909 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5911 verified_link_cap = dc_link_get_link_cap(stream->link);
5912 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5913 edp_min_bpp_x16 = 8 * 16;
5914 edp_max_bpp_x16 = 8 * 16;
5916 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5917 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5919 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5920 edp_min_bpp_x16 = edp_max_bpp_x16;
5922 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5923 dc->debug.dsc_min_slice_height_override,
5924 edp_min_bpp_x16, edp_max_bpp_x16,
5927 dc_link_get_highest_encoding_format(aconnector->dc_link),
5930 if (bw_range.max_kbps < link_bw_in_kbps) {
5931 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5936 dc_link_get_highest_encoding_format(aconnector->dc_link),
5938 stream->timing.dsc_cfg = dsc_cfg;
5939 stream->timing.flags.DSC = 1;
5940 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5946 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5951 dc_link_get_highest_encoding_format(aconnector->dc_link),
5953 stream->timing.dsc_cfg = dsc_cfg;
5954 stream->timing.flags.DSC = 1;
5959 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5960 struct dc_sink *sink, struct dc_stream_state *stream,
5961 struct dsc_dec_dpcd_caps *dsc_caps)
5963 struct drm_connector *drm_connector = &aconnector->base;
5964 u32 link_bandwidth_kbps;
5965 struct dc *dc = sink->ctx->dc;
5966 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5967 u32 dsc_max_supported_bw_in_kbps;
5968 u32 max_dsc_target_bpp_limit_override =
5969 drm_connector->display_info.max_dsc_bpp;
5970 struct dc_dsc_config_options dsc_options = {0};
5972 dc_dsc_get_default_config_option(dc, &dsc_options);
5973 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5975 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5976 dc_link_get_link_cap(aconnector->dc_link));
5978 /* Set DSC policy according to dsc_clock_en */
5979 dc_dsc_policy_set_enable_dsc_when_not_needed(
5980 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5982 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5983 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5984 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5986 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5988 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5989 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5990 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5993 link_bandwidth_kbps,
5995 dc_link_get_highest_encoding_format(aconnector->dc_link),
5996 &stream->timing.dsc_cfg)) {
5997 stream->timing.flags.DSC = 1;
5998 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6000 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6001 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6002 dc_link_get_highest_encoding_format(aconnector->dc_link));
6003 max_supported_bw_in_kbps = link_bandwidth_kbps;
6004 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6006 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6007 max_supported_bw_in_kbps > 0 &&
6008 dsc_max_supported_bw_in_kbps > 0)
6009 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6012 dsc_max_supported_bw_in_kbps,
6014 dc_link_get_highest_encoding_format(aconnector->dc_link),
6015 &stream->timing.dsc_cfg)) {
6016 stream->timing.flags.DSC = 1;
6017 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6018 __func__, drm_connector->name);
6023 /* Overwrite the stream flag if DSC is enabled through debugfs */
6024 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6025 stream->timing.flags.DSC = 1;
6027 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6028 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6030 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6031 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6033 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6034 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6037 static struct dc_stream_state *
6038 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6039 const struct drm_display_mode *drm_mode,
6040 const struct dm_connector_state *dm_state,
6041 const struct dc_stream_state *old_stream,
6044 struct drm_display_mode *preferred_mode = NULL;
6045 struct drm_connector *drm_connector;
6046 const struct drm_connector_state *con_state = &dm_state->base;
6047 struct dc_stream_state *stream = NULL;
6048 struct drm_display_mode mode;
6049 struct drm_display_mode saved_mode;
6050 struct drm_display_mode *freesync_mode = NULL;
6051 bool native_mode_found = false;
6052 bool recalculate_timing = false;
6053 bool scale = dm_state->scaling != RMX_OFF;
6055 int preferred_refresh = 0;
6056 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6057 struct dsc_dec_dpcd_caps dsc_caps;
6059 struct dc_sink *sink = NULL;
6061 drm_mode_init(&mode, drm_mode);
6062 memset(&saved_mode, 0, sizeof(saved_mode));
6064 if (aconnector == NULL) {
6065 DRM_ERROR("aconnector is NULL!\n");
6069 drm_connector = &aconnector->base;
6071 if (!aconnector->dc_sink) {
6072 sink = create_fake_sink(aconnector);
6076 sink = aconnector->dc_sink;
6077 dc_sink_retain(sink);
6080 stream = dc_create_stream_for_sink(sink);
6082 if (stream == NULL) {
6083 DRM_ERROR("Failed to create stream for sink!\n");
6087 stream->dm_stream_context = aconnector;
6089 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6090 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6092 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6093 /* Search for preferred mode */
6094 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6095 native_mode_found = true;
6099 if (!native_mode_found)
6100 preferred_mode = list_first_entry_or_null(
6101 &aconnector->base.modes,
6102 struct drm_display_mode,
6105 mode_refresh = drm_mode_vrefresh(&mode);
6107 if (preferred_mode == NULL) {
6109 * This may not be an error, the use case is when we have no
6110 * usermode calls to reset and set mode upon hotplug. In this
6111 * case, we call set mode ourselves to restore the previous mode
6112 * and the modelist may not be filled in time.
6114 DRM_DEBUG_DRIVER("No preferred mode found\n");
6116 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6117 if (recalculate_timing) {
6118 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6119 drm_mode_copy(&saved_mode, &mode);
6120 drm_mode_copy(&mode, freesync_mode);
6122 decide_crtc_timing_for_drm_display_mode(
6123 &mode, preferred_mode, scale);
6125 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6129 if (recalculate_timing)
6130 drm_mode_set_crtcinfo(&saved_mode, 0);
6133 * If scaling is enabled and refresh rate didn't change
6134 * we copy the vic and polarities of the old timings
6136 if (!scale || mode_refresh != preferred_refresh)
6137 fill_stream_properties_from_drm_display_mode(
6138 stream, &mode, &aconnector->base, con_state, NULL,
6141 fill_stream_properties_from_drm_display_mode(
6142 stream, &mode, &aconnector->base, con_state, old_stream,
6145 if (aconnector->timing_changed) {
6146 drm_dbg(aconnector->base.dev,
6147 "overriding timing for automated test, bpc %d, changing to %d\n",
6148 stream->timing.display_color_depth,
6149 aconnector->timing_requested->display_color_depth);
6150 stream->timing = *aconnector->timing_requested;
6153 /* SST DSC determination policy */
6154 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6155 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6156 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6158 update_stream_scaling_settings(&mode, dm_state, stream);
6161 &stream->audio_info,
6165 update_stream_signal(stream, sink);
6167 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6168 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6170 if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6172 // should decide stream support vsc sdp colorimetry capability
6173 // before building vsc info packet
6175 stream->use_vsc_sdp_for_colorimetry = false;
6176 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6177 stream->use_vsc_sdp_for_colorimetry =
6178 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6180 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6181 stream->use_vsc_sdp_for_colorimetry = true;
6183 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6184 tf = TRANSFER_FUNC_GAMMA_22;
6185 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6186 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6190 dc_sink_release(sink);
6195 static enum drm_connector_status
6196 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6199 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6203 * 1. This interface is NOT called in context of HPD irq.
6204 * 2. This interface *is called* in context of user-mode ioctl. Which
6205 * makes it a bad place for *any* MST-related activity.
6208 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6209 !aconnector->fake_enable)
6210 connected = (aconnector->dc_sink != NULL);
6212 connected = (aconnector->base.force == DRM_FORCE_ON ||
6213 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6215 update_subconnector_property(aconnector);
6217 return (connected ? connector_status_connected :
6218 connector_status_disconnected);
6221 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6222 struct drm_connector_state *connector_state,
6223 struct drm_property *property,
6226 struct drm_device *dev = connector->dev;
6227 struct amdgpu_device *adev = drm_to_adev(dev);
6228 struct dm_connector_state *dm_old_state =
6229 to_dm_connector_state(connector->state);
6230 struct dm_connector_state *dm_new_state =
6231 to_dm_connector_state(connector_state);
6235 if (property == dev->mode_config.scaling_mode_property) {
6236 enum amdgpu_rmx_type rmx_type;
6239 case DRM_MODE_SCALE_CENTER:
6240 rmx_type = RMX_CENTER;
6242 case DRM_MODE_SCALE_ASPECT:
6243 rmx_type = RMX_ASPECT;
6245 case DRM_MODE_SCALE_FULLSCREEN:
6246 rmx_type = RMX_FULL;
6248 case DRM_MODE_SCALE_NONE:
6254 if (dm_old_state->scaling == rmx_type)
6257 dm_new_state->scaling = rmx_type;
6259 } else if (property == adev->mode_info.underscan_hborder_property) {
6260 dm_new_state->underscan_hborder = val;
6262 } else if (property == adev->mode_info.underscan_vborder_property) {
6263 dm_new_state->underscan_vborder = val;
6265 } else if (property == adev->mode_info.underscan_property) {
6266 dm_new_state->underscan_enable = val;
6268 } else if (property == adev->mode_info.abm_level_property) {
6269 dm_new_state->abm_level = val;
6276 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6277 const struct drm_connector_state *state,
6278 struct drm_property *property,
6281 struct drm_device *dev = connector->dev;
6282 struct amdgpu_device *adev = drm_to_adev(dev);
6283 struct dm_connector_state *dm_state =
6284 to_dm_connector_state(state);
6287 if (property == dev->mode_config.scaling_mode_property) {
6288 switch (dm_state->scaling) {
6290 *val = DRM_MODE_SCALE_CENTER;
6293 *val = DRM_MODE_SCALE_ASPECT;
6296 *val = DRM_MODE_SCALE_FULLSCREEN;
6300 *val = DRM_MODE_SCALE_NONE;
6304 } else if (property == adev->mode_info.underscan_hborder_property) {
6305 *val = dm_state->underscan_hborder;
6307 } else if (property == adev->mode_info.underscan_vborder_property) {
6308 *val = dm_state->underscan_vborder;
6310 } else if (property == adev->mode_info.underscan_property) {
6311 *val = dm_state->underscan_enable;
6313 } else if (property == adev->mode_info.abm_level_property) {
6314 *val = dm_state->abm_level;
6321 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6323 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6325 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6328 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6330 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6331 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6332 struct amdgpu_display_manager *dm = &adev->dm;
6335 * Call only if mst_mgr was initialized before since it's not done
6336 * for all connector types.
6338 if (aconnector->mst_mgr.dev)
6339 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6341 if (aconnector->bl_idx != -1) {
6342 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6343 dm->backlight_dev[aconnector->bl_idx] = NULL;
6346 if (aconnector->dc_em_sink)
6347 dc_sink_release(aconnector->dc_em_sink);
6348 aconnector->dc_em_sink = NULL;
6349 if (aconnector->dc_sink)
6350 dc_sink_release(aconnector->dc_sink);
6351 aconnector->dc_sink = NULL;
6353 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6354 drm_connector_unregister(connector);
6355 drm_connector_cleanup(connector);
6356 if (aconnector->i2c) {
6357 i2c_del_adapter(&aconnector->i2c->base);
6358 kfree(aconnector->i2c);
6360 kfree(aconnector->dm_dp_aux.aux.name);
6365 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6367 struct dm_connector_state *state =
6368 to_dm_connector_state(connector->state);
6370 if (connector->state)
6371 __drm_atomic_helper_connector_destroy_state(connector->state);
6375 state = kzalloc(sizeof(*state), GFP_KERNEL);
6378 state->scaling = RMX_OFF;
6379 state->underscan_enable = false;
6380 state->underscan_hborder = 0;
6381 state->underscan_vborder = 0;
6382 state->base.max_requested_bpc = 8;
6383 state->vcpi_slots = 0;
6386 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6387 state->abm_level = amdgpu_dm_abm_level;
6389 __drm_atomic_helper_connector_reset(connector, &state->base);
6393 struct drm_connector_state *
6394 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6396 struct dm_connector_state *state =
6397 to_dm_connector_state(connector->state);
6399 struct dm_connector_state *new_state =
6400 kmemdup(state, sizeof(*state), GFP_KERNEL);
6405 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6407 new_state->freesync_capable = state->freesync_capable;
6408 new_state->abm_level = state->abm_level;
6409 new_state->scaling = state->scaling;
6410 new_state->underscan_enable = state->underscan_enable;
6411 new_state->underscan_hborder = state->underscan_hborder;
6412 new_state->underscan_vborder = state->underscan_vborder;
6413 new_state->vcpi_slots = state->vcpi_slots;
6414 new_state->pbn = state->pbn;
6415 return &new_state->base;
6419 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6421 struct amdgpu_dm_connector *amdgpu_dm_connector =
6422 to_amdgpu_dm_connector(connector);
6425 amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6427 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6428 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6429 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6430 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6435 #if defined(CONFIG_DEBUG_FS)
6436 connector_debugfs_init(amdgpu_dm_connector);
6442 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6444 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6445 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6446 struct dc_link *dc_link = aconnector->dc_link;
6447 struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6451 * Note: drm_get_edid gets edid in the following order:
6452 * 1) override EDID if set via edid_override debugfs,
6453 * 2) firmware EDID if set via edid_firmware module parameter
6454 * 3) regular DDC read.
6456 edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6458 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6462 aconnector->edid = edid;
6464 /* Update emulated (virtual) sink's EDID */
6465 if (dc_em_sink && dc_link) {
6466 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6467 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6468 dm_helpers_parse_edid_caps(
6470 &dc_em_sink->dc_edid,
6471 &dc_em_sink->edid_caps);
6475 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6476 .reset = amdgpu_dm_connector_funcs_reset,
6477 .detect = amdgpu_dm_connector_detect,
6478 .fill_modes = drm_helper_probe_single_connector_modes,
6479 .destroy = amdgpu_dm_connector_destroy,
6480 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6481 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6482 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6483 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6484 .late_register = amdgpu_dm_connector_late_register,
6485 .early_unregister = amdgpu_dm_connector_unregister,
6486 .force = amdgpu_dm_connector_funcs_force
6489 static int get_modes(struct drm_connector *connector)
6491 return amdgpu_dm_connector_get_modes(connector);
6494 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6496 struct drm_connector *connector = &aconnector->base;
6497 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6498 struct dc_sink_init_data init_params = {
6499 .link = aconnector->dc_link,
6500 .sink_signal = SIGNAL_TYPE_VIRTUAL
6505 * Note: drm_get_edid gets edid in the following order:
6506 * 1) override EDID if set via edid_override debugfs,
6507 * 2) firmware EDID if set via edid_firmware module parameter
6508 * 3) regular DDC read.
6510 edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6512 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6516 if (drm_detect_hdmi_monitor(edid))
6517 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6519 aconnector->edid = edid;
6521 aconnector->dc_em_sink = dc_link_add_remote_sink(
6522 aconnector->dc_link,
6524 (edid->extensions + 1) * EDID_LENGTH,
6527 if (aconnector->base.force == DRM_FORCE_ON) {
6528 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6529 aconnector->dc_link->local_sink :
6530 aconnector->dc_em_sink;
6531 dc_sink_retain(aconnector->dc_sink);
6535 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6537 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6540 * In case of headless boot with force on for DP managed connector
6541 * Those settings have to be != 0 to get initial modeset
6543 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6544 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6545 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6548 create_eml_sink(aconnector);
6551 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6552 struct dc_stream_state *stream)
6554 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6555 struct dc_plane_state *dc_plane_state = NULL;
6556 struct dc_state *dc_state = NULL;
6561 dc_plane_state = dc_create_plane_state(dc);
6562 if (!dc_plane_state)
6565 dc_state = dc_create_state(dc);
6569 /* populate stream to plane */
6570 dc_plane_state->src_rect.height = stream->src.height;
6571 dc_plane_state->src_rect.width = stream->src.width;
6572 dc_plane_state->dst_rect.height = stream->src.height;
6573 dc_plane_state->dst_rect.width = stream->src.width;
6574 dc_plane_state->clip_rect.height = stream->src.height;
6575 dc_plane_state->clip_rect.width = stream->src.width;
6576 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6577 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6578 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6579 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6580 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6581 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6582 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6583 dc_plane_state->rotation = ROTATION_ANGLE_0;
6584 dc_plane_state->is_tiling_rotated = false;
6585 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6587 dc_result = dc_validate_stream(dc, stream);
6588 if (dc_result == DC_OK)
6589 dc_result = dc_validate_plane(dc, dc_plane_state);
6591 if (dc_result == DC_OK)
6592 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6594 if (dc_result == DC_OK && !dc_add_plane_to_context(
6599 dc_result = DC_FAIL_ATTACH_SURFACES;
6601 if (dc_result == DC_OK)
6602 dc_result = dc_validate_global_state(dc, dc_state, true);
6606 dc_release_state(dc_state);
6609 dc_plane_state_release(dc_plane_state);
6614 struct dc_stream_state *
6615 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6616 const struct drm_display_mode *drm_mode,
6617 const struct dm_connector_state *dm_state,
6618 const struct dc_stream_state *old_stream)
6620 struct drm_connector *connector = &aconnector->base;
6621 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6622 struct dc_stream_state *stream;
6623 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6624 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6625 enum dc_status dc_result = DC_OK;
6628 stream = create_stream_for_sink(aconnector, drm_mode,
6629 dm_state, old_stream,
6631 if (stream == NULL) {
6632 DRM_ERROR("Failed to create stream for sink!\n");
6636 dc_result = dc_validate_stream(adev->dm.dc, stream);
6637 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6638 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6640 if (dc_result == DC_OK)
6641 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6643 if (dc_result != DC_OK) {
6644 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6649 dc_status_to_str(dc_result));
6651 dc_stream_release(stream);
6653 requested_bpc -= 2; /* lower bpc to retry validation */
6656 } while (stream == NULL && requested_bpc >= 6);
6658 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6659 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6661 aconnector->force_yuv420_output = true;
6662 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6663 dm_state, old_stream);
6664 aconnector->force_yuv420_output = false;
6670 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6671 struct drm_display_mode *mode)
6673 int result = MODE_ERROR;
6674 struct dc_sink *dc_sink;
6675 /* TODO: Unhardcode stream count */
6676 struct dc_stream_state *stream;
6677 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6679 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6680 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6684 * Only run this the first time mode_valid is called to initilialize
6687 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6688 !aconnector->dc_em_sink)
6689 handle_edid_mgmt(aconnector);
6691 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6693 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6694 aconnector->base.force != DRM_FORCE_ON) {
6695 DRM_ERROR("dc_sink is NULL!\n");
6699 drm_mode_set_crtcinfo(mode, 0);
6701 stream = create_validate_stream_for_sink(aconnector, mode,
6702 to_dm_connector_state(connector->state),
6705 dc_stream_release(stream);
6710 /* TODO: error handling*/
6714 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6715 struct dc_info_packet *out)
6717 struct hdmi_drm_infoframe frame;
6718 unsigned char buf[30]; /* 26 + 4 */
6722 memset(out, 0, sizeof(*out));
6724 if (!state->hdr_output_metadata)
6727 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6731 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6735 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6739 /* Prepare the infopacket for DC. */
6740 switch (state->connector->connector_type) {
6741 case DRM_MODE_CONNECTOR_HDMIA:
6742 out->hb0 = 0x87; /* type */
6743 out->hb1 = 0x01; /* version */
6744 out->hb2 = 0x1A; /* length */
6745 out->sb[0] = buf[3]; /* checksum */
6749 case DRM_MODE_CONNECTOR_DisplayPort:
6750 case DRM_MODE_CONNECTOR_eDP:
6751 out->hb0 = 0x00; /* sdp id, zero */
6752 out->hb1 = 0x87; /* type */
6753 out->hb2 = 0x1D; /* payload len - 1 */
6754 out->hb3 = (0x13 << 2); /* sdp version */
6755 out->sb[0] = 0x01; /* version */
6756 out->sb[1] = 0x1A; /* length */
6764 memcpy(&out->sb[i], &buf[4], 26);
6767 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6768 sizeof(out->sb), false);
6774 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6775 struct drm_atomic_state *state)
6777 struct drm_connector_state *new_con_state =
6778 drm_atomic_get_new_connector_state(state, conn);
6779 struct drm_connector_state *old_con_state =
6780 drm_atomic_get_old_connector_state(state, conn);
6781 struct drm_crtc *crtc = new_con_state->crtc;
6782 struct drm_crtc_state *new_crtc_state;
6783 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6786 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6788 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6789 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6797 if (new_con_state->colorspace != old_con_state->colorspace) {
6798 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6799 if (IS_ERR(new_crtc_state))
6800 return PTR_ERR(new_crtc_state);
6802 new_crtc_state->mode_changed = true;
6805 if (new_con_state->content_type != old_con_state->content_type) {
6806 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6807 if (IS_ERR(new_crtc_state))
6808 return PTR_ERR(new_crtc_state);
6810 new_crtc_state->mode_changed = true;
6813 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6814 struct dc_info_packet hdr_infopacket;
6816 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6820 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6821 if (IS_ERR(new_crtc_state))
6822 return PTR_ERR(new_crtc_state);
6825 * DC considers the stream backends changed if the
6826 * static metadata changes. Forcing the modeset also
6827 * gives a simple way for userspace to switch from
6828 * 8bpc to 10bpc when setting the metadata to enter
6831 * Changing the static metadata after it's been
6832 * set is permissible, however. So only force a
6833 * modeset if we're entering or exiting HDR.
6835 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6836 !old_con_state->hdr_output_metadata ||
6837 !new_con_state->hdr_output_metadata;
6843 static const struct drm_connector_helper_funcs
6844 amdgpu_dm_connector_helper_funcs = {
6846 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6847 * modes will be filtered by drm_mode_validate_size(), and those modes
6848 * are missing after user start lightdm. So we need to renew modes list.
6849 * in get_modes call back, not just return the modes count
6851 .get_modes = get_modes,
6852 .mode_valid = amdgpu_dm_connector_mode_valid,
6853 .atomic_check = amdgpu_dm_connector_atomic_check,
6856 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6861 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6863 switch (display_color_depth) {
6864 case COLOR_DEPTH_666:
6866 case COLOR_DEPTH_888:
6868 case COLOR_DEPTH_101010:
6870 case COLOR_DEPTH_121212:
6872 case COLOR_DEPTH_141414:
6874 case COLOR_DEPTH_161616:
6882 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6883 struct drm_crtc_state *crtc_state,
6884 struct drm_connector_state *conn_state)
6886 struct drm_atomic_state *state = crtc_state->state;
6887 struct drm_connector *connector = conn_state->connector;
6888 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6889 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6890 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6891 struct drm_dp_mst_topology_mgr *mst_mgr;
6892 struct drm_dp_mst_port *mst_port;
6893 struct drm_dp_mst_topology_state *mst_state;
6894 enum dc_color_depth color_depth;
6896 bool is_y420 = false;
6898 if (!aconnector->mst_output_port)
6901 mst_port = aconnector->mst_output_port;
6902 mst_mgr = &aconnector->mst_root->mst_mgr;
6904 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6907 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6908 if (IS_ERR(mst_state))
6909 return PTR_ERR(mst_state);
6911 if (!mst_state->pbn_div)
6912 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6914 if (!state->duplicated) {
6915 int max_bpc = conn_state->max_requested_bpc;
6917 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6918 aconnector->force_yuv420_output;
6919 color_depth = convert_color_depth_from_display_info(connector,
6922 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6923 clock = adjusted_mode->clock;
6924 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6927 dm_new_connector_state->vcpi_slots =
6928 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6929 dm_new_connector_state->pbn);
6930 if (dm_new_connector_state->vcpi_slots < 0) {
6931 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6932 return dm_new_connector_state->vcpi_slots;
6937 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6938 .disable = dm_encoder_helper_disable,
6939 .atomic_check = dm_encoder_helper_atomic_check
6942 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6943 struct dc_state *dc_state,
6944 struct dsc_mst_fairness_vars *vars)
6946 struct dc_stream_state *stream = NULL;
6947 struct drm_connector *connector;
6948 struct drm_connector_state *new_con_state;
6949 struct amdgpu_dm_connector *aconnector;
6950 struct dm_connector_state *dm_conn_state;
6952 int vcpi, pbn_div, pbn, slot_num = 0;
6954 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6956 aconnector = to_amdgpu_dm_connector(connector);
6958 if (!aconnector->mst_output_port)
6961 if (!new_con_state || !new_con_state->crtc)
6964 dm_conn_state = to_dm_connector_state(new_con_state);
6966 for (j = 0; j < dc_state->stream_count; j++) {
6967 stream = dc_state->streams[j];
6971 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6980 pbn_div = dm_mst_get_pbn_divider(stream->link);
6981 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6982 for (j = 0; j < dc_state->stream_count; j++) {
6983 if (vars[j].aconnector == aconnector) {
6989 if (j == dc_state->stream_count)
6992 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6994 if (stream->timing.flags.DSC != 1) {
6995 dm_conn_state->pbn = pbn;
6996 dm_conn_state->vcpi_slots = slot_num;
6998 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6999 dm_conn_state->pbn, false);
7006 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7010 dm_conn_state->pbn = pbn;
7011 dm_conn_state->vcpi_slots = vcpi;
7016 static int to_drm_connector_type(enum signal_type st)
7019 case SIGNAL_TYPE_HDMI_TYPE_A:
7020 return DRM_MODE_CONNECTOR_HDMIA;
7021 case SIGNAL_TYPE_EDP:
7022 return DRM_MODE_CONNECTOR_eDP;
7023 case SIGNAL_TYPE_LVDS:
7024 return DRM_MODE_CONNECTOR_LVDS;
7025 case SIGNAL_TYPE_RGB:
7026 return DRM_MODE_CONNECTOR_VGA;
7027 case SIGNAL_TYPE_DISPLAY_PORT:
7028 case SIGNAL_TYPE_DISPLAY_PORT_MST:
7029 return DRM_MODE_CONNECTOR_DisplayPort;
7030 case SIGNAL_TYPE_DVI_DUAL_LINK:
7031 case SIGNAL_TYPE_DVI_SINGLE_LINK:
7032 return DRM_MODE_CONNECTOR_DVID;
7033 case SIGNAL_TYPE_VIRTUAL:
7034 return DRM_MODE_CONNECTOR_VIRTUAL;
7037 return DRM_MODE_CONNECTOR_Unknown;
7041 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7043 struct drm_encoder *encoder;
7045 /* There is only one encoder per connector */
7046 drm_connector_for_each_possible_encoder(connector, encoder)
7052 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7054 struct drm_encoder *encoder;
7055 struct amdgpu_encoder *amdgpu_encoder;
7057 encoder = amdgpu_dm_connector_to_encoder(connector);
7059 if (encoder == NULL)
7062 amdgpu_encoder = to_amdgpu_encoder(encoder);
7064 amdgpu_encoder->native_mode.clock = 0;
7066 if (!list_empty(&connector->probed_modes)) {
7067 struct drm_display_mode *preferred_mode = NULL;
7069 list_for_each_entry(preferred_mode,
7070 &connector->probed_modes,
7072 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7073 amdgpu_encoder->native_mode = *preferred_mode;
7081 static struct drm_display_mode *
7082 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7084 int hdisplay, int vdisplay)
7086 struct drm_device *dev = encoder->dev;
7087 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7088 struct drm_display_mode *mode = NULL;
7089 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7091 mode = drm_mode_duplicate(dev, native_mode);
7096 mode->hdisplay = hdisplay;
7097 mode->vdisplay = vdisplay;
7098 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7099 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7105 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7106 struct drm_connector *connector)
7108 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7109 struct drm_display_mode *mode = NULL;
7110 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7111 struct amdgpu_dm_connector *amdgpu_dm_connector =
7112 to_amdgpu_dm_connector(connector);
7116 char name[DRM_DISPLAY_MODE_LEN];
7119 } common_modes[] = {
7120 { "640x480", 640, 480},
7121 { "800x600", 800, 600},
7122 { "1024x768", 1024, 768},
7123 { "1280x720", 1280, 720},
7124 { "1280x800", 1280, 800},
7125 {"1280x1024", 1280, 1024},
7126 { "1440x900", 1440, 900},
7127 {"1680x1050", 1680, 1050},
7128 {"1600x1200", 1600, 1200},
7129 {"1920x1080", 1920, 1080},
7130 {"1920x1200", 1920, 1200}
7133 n = ARRAY_SIZE(common_modes);
7135 for (i = 0; i < n; i++) {
7136 struct drm_display_mode *curmode = NULL;
7137 bool mode_existed = false;
7139 if (common_modes[i].w > native_mode->hdisplay ||
7140 common_modes[i].h > native_mode->vdisplay ||
7141 (common_modes[i].w == native_mode->hdisplay &&
7142 common_modes[i].h == native_mode->vdisplay))
7145 list_for_each_entry(curmode, &connector->probed_modes, head) {
7146 if (common_modes[i].w == curmode->hdisplay &&
7147 common_modes[i].h == curmode->vdisplay) {
7148 mode_existed = true;
7156 mode = amdgpu_dm_create_common_mode(encoder,
7157 common_modes[i].name, common_modes[i].w,
7162 drm_mode_probed_add(connector, mode);
7163 amdgpu_dm_connector->num_modes++;
7167 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7169 struct drm_encoder *encoder;
7170 struct amdgpu_encoder *amdgpu_encoder;
7171 const struct drm_display_mode *native_mode;
7173 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7174 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7177 mutex_lock(&connector->dev->mode_config.mutex);
7178 amdgpu_dm_connector_get_modes(connector);
7179 mutex_unlock(&connector->dev->mode_config.mutex);
7181 encoder = amdgpu_dm_connector_to_encoder(connector);
7185 amdgpu_encoder = to_amdgpu_encoder(encoder);
7187 native_mode = &amdgpu_encoder->native_mode;
7188 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7191 drm_connector_set_panel_orientation_with_quirk(connector,
7192 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7193 native_mode->hdisplay,
7194 native_mode->vdisplay);
7197 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7200 struct amdgpu_dm_connector *amdgpu_dm_connector =
7201 to_amdgpu_dm_connector(connector);
7204 /* empty probed_modes */
7205 INIT_LIST_HEAD(&connector->probed_modes);
7206 amdgpu_dm_connector->num_modes =
7207 drm_add_edid_modes(connector, edid);
7209 /* sorting the probed modes before calling function
7210 * amdgpu_dm_get_native_mode() since EDID can have
7211 * more than one preferred mode. The modes that are
7212 * later in the probed mode list could be of higher
7213 * and preferred resolution. For example, 3840x2160
7214 * resolution in base EDID preferred timing and 4096x2160
7215 * preferred resolution in DID extension block later.
7217 drm_mode_sort(&connector->probed_modes);
7218 amdgpu_dm_get_native_mode(connector);
7220 /* Freesync capabilities are reset by calling
7221 * drm_add_edid_modes() and need to be
7224 amdgpu_dm_update_freesync_caps(connector, edid);
7226 amdgpu_dm_connector->num_modes = 0;
7230 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7231 struct drm_display_mode *mode)
7233 struct drm_display_mode *m;
7235 list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7236 if (drm_mode_equal(m, mode))
7243 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7245 const struct drm_display_mode *m;
7246 struct drm_display_mode *new_mode;
7248 u32 new_modes_count = 0;
7250 /* Standard FPS values
7259 * 60 - Commonly used
7260 * 48,72,96,120 - Multiples of 24
7262 static const u32 common_rates[] = {
7263 23976, 24000, 25000, 29970, 30000,
7264 48000, 50000, 60000, 72000, 96000, 120000
7268 * Find mode with highest refresh rate with the same resolution
7269 * as the preferred mode. Some monitors report a preferred mode
7270 * with lower resolution than the highest refresh rate supported.
7273 m = get_highest_refresh_rate_mode(aconnector, true);
7277 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7278 u64 target_vtotal, target_vtotal_diff;
7281 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7284 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7285 common_rates[i] > aconnector->max_vfreq * 1000)
7288 num = (unsigned long long)m->clock * 1000 * 1000;
7289 den = common_rates[i] * (unsigned long long)m->htotal;
7290 target_vtotal = div_u64(num, den);
7291 target_vtotal_diff = target_vtotal - m->vtotal;
7293 /* Check for illegal modes */
7294 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7295 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7296 m->vtotal + target_vtotal_diff < m->vsync_end)
7299 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7303 new_mode->vtotal += (u16)target_vtotal_diff;
7304 new_mode->vsync_start += (u16)target_vtotal_diff;
7305 new_mode->vsync_end += (u16)target_vtotal_diff;
7306 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7307 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7309 if (!is_duplicate_mode(aconnector, new_mode)) {
7310 drm_mode_probed_add(&aconnector->base, new_mode);
7311 new_modes_count += 1;
7313 drm_mode_destroy(aconnector->base.dev, new_mode);
7316 return new_modes_count;
7319 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7322 struct amdgpu_dm_connector *amdgpu_dm_connector =
7323 to_amdgpu_dm_connector(connector);
7328 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7329 amdgpu_dm_connector->num_modes +=
7330 add_fs_modes(amdgpu_dm_connector);
7333 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7335 struct amdgpu_dm_connector *amdgpu_dm_connector =
7336 to_amdgpu_dm_connector(connector);
7337 struct drm_encoder *encoder;
7338 struct edid *edid = amdgpu_dm_connector->edid;
7339 struct dc_link_settings *verified_link_cap =
7340 &amdgpu_dm_connector->dc_link->verified_link_cap;
7341 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7343 encoder = amdgpu_dm_connector_to_encoder(connector);
7345 if (!drm_edid_is_valid(edid)) {
7346 amdgpu_dm_connector->num_modes =
7347 drm_add_modes_noedid(connector, 640, 480);
7348 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7349 amdgpu_dm_connector->num_modes +=
7350 drm_add_modes_noedid(connector, 1920, 1080);
7352 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7353 amdgpu_dm_connector_add_common_modes(encoder, connector);
7354 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7356 amdgpu_dm_fbc_init(connector);
7358 return amdgpu_dm_connector->num_modes;
7361 static const u32 supported_colorspaces =
7362 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7363 BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7364 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7365 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7367 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7368 struct amdgpu_dm_connector *aconnector,
7370 struct dc_link *link,
7373 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7376 * Some of the properties below require access to state, like bpc.
7377 * Allocate some default initial connector state with our reset helper.
7379 if (aconnector->base.funcs->reset)
7380 aconnector->base.funcs->reset(&aconnector->base);
7382 aconnector->connector_id = link_index;
7383 aconnector->bl_idx = -1;
7384 aconnector->dc_link = link;
7385 aconnector->base.interlace_allowed = false;
7386 aconnector->base.doublescan_allowed = false;
7387 aconnector->base.stereo_allowed = false;
7388 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7389 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7390 aconnector->audio_inst = -1;
7391 aconnector->pack_sdp_v1_3 = false;
7392 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7393 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7394 mutex_init(&aconnector->hpd_lock);
7395 mutex_init(&aconnector->handle_mst_msg_ready);
7398 * configure support HPD hot plug connector_>polled default value is 0
7399 * which means HPD hot plug not supported
7401 switch (connector_type) {
7402 case DRM_MODE_CONNECTOR_HDMIA:
7403 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7404 aconnector->base.ycbcr_420_allowed =
7405 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7407 case DRM_MODE_CONNECTOR_DisplayPort:
7408 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7409 link->link_enc = link_enc_cfg_get_link_enc(link);
7410 ASSERT(link->link_enc);
7412 aconnector->base.ycbcr_420_allowed =
7413 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7415 case DRM_MODE_CONNECTOR_DVID:
7416 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7422 drm_object_attach_property(&aconnector->base.base,
7423 dm->ddev->mode_config.scaling_mode_property,
7424 DRM_MODE_SCALE_NONE);
7426 drm_object_attach_property(&aconnector->base.base,
7427 adev->mode_info.underscan_property,
7429 drm_object_attach_property(&aconnector->base.base,
7430 adev->mode_info.underscan_hborder_property,
7432 drm_object_attach_property(&aconnector->base.base,
7433 adev->mode_info.underscan_vborder_property,
7436 if (!aconnector->mst_root)
7437 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7439 aconnector->base.state->max_bpc = 16;
7440 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7442 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7443 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7444 drm_object_attach_property(&aconnector->base.base,
7445 adev->mode_info.abm_level_property, 0);
7448 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7449 /* Content Type is currently only implemented for HDMI. */
7450 drm_connector_attach_content_type_property(&aconnector->base);
7453 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7454 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7455 drm_connector_attach_colorspace_property(&aconnector->base);
7456 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7457 connector_type == DRM_MODE_CONNECTOR_eDP) {
7458 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7459 drm_connector_attach_colorspace_property(&aconnector->base);
7462 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7463 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7464 connector_type == DRM_MODE_CONNECTOR_eDP) {
7465 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7467 if (!aconnector->mst_root)
7468 drm_connector_attach_vrr_capable_property(&aconnector->base);
7470 if (adev->dm.hdcp_workqueue)
7471 drm_connector_attach_content_protection_property(&aconnector->base, true);
7475 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7476 struct i2c_msg *msgs, int num)
7478 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7479 struct ddc_service *ddc_service = i2c->ddc_service;
7480 struct i2c_command cmd;
7484 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7489 cmd.number_of_payloads = num;
7490 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7493 for (i = 0; i < num; i++) {
7494 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7495 cmd.payloads[i].address = msgs[i].addr;
7496 cmd.payloads[i].length = msgs[i].len;
7497 cmd.payloads[i].data = msgs[i].buf;
7501 ddc_service->ctx->dc,
7502 ddc_service->link->link_index,
7506 kfree(cmd.payloads);
7510 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7512 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7515 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7516 .master_xfer = amdgpu_dm_i2c_xfer,
7517 .functionality = amdgpu_dm_i2c_func,
7520 static struct amdgpu_i2c_adapter *
7521 create_i2c(struct ddc_service *ddc_service,
7525 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7526 struct amdgpu_i2c_adapter *i2c;
7528 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7531 i2c->base.owner = THIS_MODULE;
7532 i2c->base.class = I2C_CLASS_DDC;
7533 i2c->base.dev.parent = &adev->pdev->dev;
7534 i2c->base.algo = &amdgpu_dm_i2c_algo;
7535 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7536 i2c_set_adapdata(&i2c->base, i2c);
7537 i2c->ddc_service = ddc_service;
7544 * Note: this function assumes that dc_link_detect() was called for the
7545 * dc_link which will be represented by this aconnector.
7547 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7548 struct amdgpu_dm_connector *aconnector,
7550 struct amdgpu_encoder *aencoder)
7554 struct dc *dc = dm->dc;
7555 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7556 struct amdgpu_i2c_adapter *i2c;
7558 link->priv = aconnector;
7561 i2c = create_i2c(link->ddc, link->link_index, &res);
7563 DRM_ERROR("Failed to create i2c adapter data\n");
7567 aconnector->i2c = i2c;
7568 res = i2c_add_adapter(&i2c->base);
7571 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7575 connector_type = to_drm_connector_type(link->connector_signal);
7577 res = drm_connector_init_with_ddc(
7580 &amdgpu_dm_connector_funcs,
7585 DRM_ERROR("connector_init failed\n");
7586 aconnector->connector_id = -1;
7590 drm_connector_helper_add(
7592 &amdgpu_dm_connector_helper_funcs);
7594 amdgpu_dm_connector_init_helper(
7601 drm_connector_attach_encoder(
7602 &aconnector->base, &aencoder->base);
7604 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7605 || connector_type == DRM_MODE_CONNECTOR_eDP)
7606 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7611 aconnector->i2c = NULL;
7616 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7618 switch (adev->mode_info.num_crtc) {
7635 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7636 struct amdgpu_encoder *aencoder,
7637 uint32_t link_index)
7639 struct amdgpu_device *adev = drm_to_adev(dev);
7641 int res = drm_encoder_init(dev,
7643 &amdgpu_dm_encoder_funcs,
7644 DRM_MODE_ENCODER_TMDS,
7647 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7650 aencoder->encoder_id = link_index;
7652 aencoder->encoder_id = -1;
7654 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7659 static void manage_dm_interrupts(struct amdgpu_device *adev,
7660 struct amdgpu_crtc *acrtc,
7664 * We have no guarantee that the frontend index maps to the same
7665 * backend index - some even map to more than one.
7667 * TODO: Use a different interrupt or check DC itself for the mapping.
7670 amdgpu_display_crtc_idx_to_irq_type(
7675 drm_crtc_vblank_on(&acrtc->base);
7678 &adev->pageflip_irq,
7680 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7687 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7695 &adev->pageflip_irq,
7697 drm_crtc_vblank_off(&acrtc->base);
7701 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7702 struct amdgpu_crtc *acrtc)
7705 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7708 * This reads the current state for the IRQ and force reapplies
7709 * the setting to hardware.
7711 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7715 is_scaling_state_different(const struct dm_connector_state *dm_state,
7716 const struct dm_connector_state *old_dm_state)
7718 if (dm_state->scaling != old_dm_state->scaling)
7720 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7721 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7723 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7724 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7726 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7727 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7732 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7733 struct drm_crtc_state *old_crtc_state,
7734 struct drm_connector_state *new_conn_state,
7735 struct drm_connector_state *old_conn_state,
7736 const struct drm_connector *connector,
7737 struct hdcp_workqueue *hdcp_w)
7739 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7740 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7742 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7743 connector->index, connector->status, connector->dpms);
7744 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7745 old_conn_state->content_protection, new_conn_state->content_protection);
7748 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7749 old_crtc_state->enable,
7750 old_crtc_state->active,
7751 old_crtc_state->mode_changed,
7752 old_crtc_state->active_changed,
7753 old_crtc_state->connectors_changed);
7756 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7757 new_crtc_state->enable,
7758 new_crtc_state->active,
7759 new_crtc_state->mode_changed,
7760 new_crtc_state->active_changed,
7761 new_crtc_state->connectors_changed);
7763 /* hdcp content type change */
7764 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7765 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7766 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7767 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7771 /* CP is being re enabled, ignore this */
7772 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7773 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7774 if (new_crtc_state && new_crtc_state->mode_changed) {
7775 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7776 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7779 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7780 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7784 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7786 * Handles: UNDESIRED -> ENABLED
7788 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7789 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7790 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7792 /* Stream removed and re-enabled
7794 * Can sometimes overlap with the HPD case,
7795 * thus set update_hdcp to false to avoid
7796 * setting HDCP multiple times.
7798 * Handles: DESIRED -> DESIRED (Special case)
7800 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7801 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7802 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7803 dm_con_state->update_hdcp = false;
7804 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7809 /* Hot-plug, headless s3, dpms
7811 * Only start HDCP if the display is connected/enabled.
7812 * update_hdcp flag will be set to false until the next
7815 * Handles: DESIRED -> DESIRED (Special case)
7817 if (dm_con_state->update_hdcp &&
7818 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7819 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7820 dm_con_state->update_hdcp = false;
7821 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7826 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7827 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7828 if (new_crtc_state && new_crtc_state->mode_changed) {
7829 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7833 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7838 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7842 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7843 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7848 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7852 static void remove_stream(struct amdgpu_device *adev,
7853 struct amdgpu_crtc *acrtc,
7854 struct dc_stream_state *stream)
7856 /* this is the update mode case */
7858 acrtc->otg_inst = -1;
7859 acrtc->enabled = false;
7862 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7865 assert_spin_locked(&acrtc->base.dev->event_lock);
7866 WARN_ON(acrtc->event);
7868 acrtc->event = acrtc->base.state->event;
7870 /* Set the flip status */
7871 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7873 /* Mark this event as consumed */
7874 acrtc->base.state->event = NULL;
7876 drm_dbg_state(acrtc->base.dev,
7877 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7881 static void update_freesync_state_on_stream(
7882 struct amdgpu_display_manager *dm,
7883 struct dm_crtc_state *new_crtc_state,
7884 struct dc_stream_state *new_stream,
7885 struct dc_plane_state *surface,
7886 u32 flip_timestamp_in_us)
7888 struct mod_vrr_params vrr_params;
7889 struct dc_info_packet vrr_infopacket = {0};
7890 struct amdgpu_device *adev = dm->adev;
7891 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7892 unsigned long flags;
7893 bool pack_sdp_v1_3 = false;
7894 struct amdgpu_dm_connector *aconn;
7895 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7901 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7902 * For now it's sufficient to just guard against these conditions.
7905 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7908 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7909 vrr_params = acrtc->dm_irq_params.vrr_params;
7912 mod_freesync_handle_preflip(
7913 dm->freesync_module,
7916 flip_timestamp_in_us,
7919 if (adev->family < AMDGPU_FAMILY_AI &&
7920 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7921 mod_freesync_handle_v_update(dm->freesync_module,
7922 new_stream, &vrr_params);
7924 /* Need to call this before the frame ends. */
7925 dc_stream_adjust_vmin_vmax(dm->dc,
7926 new_crtc_state->stream,
7927 &vrr_params.adjust);
7931 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7933 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7934 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7936 if (aconn->vsdb_info.amd_vsdb_version == 1)
7937 packet_type = PACKET_TYPE_FS_V1;
7938 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7939 packet_type = PACKET_TYPE_FS_V2;
7940 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7941 packet_type = PACKET_TYPE_FS_V3;
7943 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7944 &new_stream->adaptive_sync_infopacket);
7947 mod_freesync_build_vrr_infopacket(
7948 dm->freesync_module,
7952 TRANSFER_FUNC_UNKNOWN,
7956 new_crtc_state->freesync_vrr_info_changed |=
7957 (memcmp(&new_crtc_state->vrr_infopacket,
7959 sizeof(vrr_infopacket)) != 0);
7961 acrtc->dm_irq_params.vrr_params = vrr_params;
7962 new_crtc_state->vrr_infopacket = vrr_infopacket;
7964 new_stream->vrr_infopacket = vrr_infopacket;
7965 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7967 if (new_crtc_state->freesync_vrr_info_changed)
7968 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7969 new_crtc_state->base.crtc->base.id,
7970 (int)new_crtc_state->base.vrr_enabled,
7971 (int)vrr_params.state);
7973 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7976 static void update_stream_irq_parameters(
7977 struct amdgpu_display_manager *dm,
7978 struct dm_crtc_state *new_crtc_state)
7980 struct dc_stream_state *new_stream = new_crtc_state->stream;
7981 struct mod_vrr_params vrr_params;
7982 struct mod_freesync_config config = new_crtc_state->freesync_config;
7983 struct amdgpu_device *adev = dm->adev;
7984 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7985 unsigned long flags;
7991 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7992 * For now it's sufficient to just guard against these conditions.
7994 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7997 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7998 vrr_params = acrtc->dm_irq_params.vrr_params;
8000 if (new_crtc_state->vrr_supported &&
8001 config.min_refresh_in_uhz &&
8002 config.max_refresh_in_uhz) {
8004 * if freesync compatible mode was set, config.state will be set
8007 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8008 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8009 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8010 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8011 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8012 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8013 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8015 config.state = new_crtc_state->base.vrr_enabled ?
8016 VRR_STATE_ACTIVE_VARIABLE :
8020 config.state = VRR_STATE_UNSUPPORTED;
8023 mod_freesync_build_vrr_params(dm->freesync_module,
8025 &config, &vrr_params);
8027 new_crtc_state->freesync_config = config;
8028 /* Copy state for access from DM IRQ handler */
8029 acrtc->dm_irq_params.freesync_config = config;
8030 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8031 acrtc->dm_irq_params.vrr_params = vrr_params;
8032 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8035 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8036 struct dm_crtc_state *new_state)
8038 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8039 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8041 if (!old_vrr_active && new_vrr_active) {
8042 /* Transition VRR inactive -> active:
8043 * While VRR is active, we must not disable vblank irq, as a
8044 * reenable after disable would compute bogus vblank/pflip
8045 * timestamps if it likely happened inside display front-porch.
8047 * We also need vupdate irq for the actual core vblank handling
8050 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8051 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8052 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8053 __func__, new_state->base.crtc->base.id);
8054 } else if (old_vrr_active && !new_vrr_active) {
8055 /* Transition VRR active -> inactive:
8056 * Allow vblank irq disable again for fixed refresh rate.
8058 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8059 drm_crtc_vblank_put(new_state->base.crtc);
8060 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8061 __func__, new_state->base.crtc->base.id);
8065 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8067 struct drm_plane *plane;
8068 struct drm_plane_state *old_plane_state;
8072 * TODO: Make this per-stream so we don't issue redundant updates for
8073 * commits with multiple streams.
8075 for_each_old_plane_in_state(state, plane, old_plane_state, i)
8076 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8077 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8080 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8082 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8084 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8087 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8088 struct drm_device *dev,
8089 struct amdgpu_display_manager *dm,
8090 struct drm_crtc *pcrtc,
8091 bool wait_for_vblank)
8094 u64 timestamp_ns = ktime_get_ns();
8095 struct drm_plane *plane;
8096 struct drm_plane_state *old_plane_state, *new_plane_state;
8097 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8098 struct drm_crtc_state *new_pcrtc_state =
8099 drm_atomic_get_new_crtc_state(state, pcrtc);
8100 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8101 struct dm_crtc_state *dm_old_crtc_state =
8102 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8103 int planes_count = 0, vpos, hpos;
8104 unsigned long flags;
8105 u32 target_vblank, last_flip_vblank;
8106 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8107 bool cursor_update = false;
8108 bool pflip_present = false;
8109 bool dirty_rects_changed = false;
8111 struct dc_surface_update surface_updates[MAX_SURFACES];
8112 struct dc_plane_info plane_infos[MAX_SURFACES];
8113 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8114 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8115 struct dc_stream_update stream_update;
8118 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8121 drm_err(dev, "Failed to allocate update bundle\n");
8126 * Disable the cursor first if we're disabling all the planes.
8127 * It'll remain on the screen after the planes are re-enabled
8130 if (acrtc_state->active_planes == 0)
8131 amdgpu_dm_commit_cursors(state);
8133 /* update planes when needed */
8134 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8135 struct drm_crtc *crtc = new_plane_state->crtc;
8136 struct drm_crtc_state *new_crtc_state;
8137 struct drm_framebuffer *fb = new_plane_state->fb;
8138 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8139 bool plane_needs_flip;
8140 struct dc_plane_state *dc_plane;
8141 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8143 /* Cursor plane is handled after stream updates */
8144 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8145 if ((fb && crtc == pcrtc) ||
8146 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8147 cursor_update = true;
8152 if (!fb || !crtc || pcrtc != crtc)
8155 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8156 if (!new_crtc_state->active)
8159 dc_plane = dm_new_plane_state->dc_state;
8163 bundle->surface_updates[planes_count].surface = dc_plane;
8164 if (new_pcrtc_state->color_mgmt_changed) {
8165 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8166 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8167 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8170 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8171 &bundle->scaling_infos[planes_count]);
8173 bundle->surface_updates[planes_count].scaling_info =
8174 &bundle->scaling_infos[planes_count];
8176 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8178 pflip_present = pflip_present || plane_needs_flip;
8180 if (!plane_needs_flip) {
8185 fill_dc_plane_info_and_addr(
8186 dm->adev, new_plane_state,
8188 &bundle->plane_infos[planes_count],
8189 &bundle->flip_addrs[planes_count].address,
8190 afb->tmz_surface, false);
8192 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8193 new_plane_state->plane->index,
8194 bundle->plane_infos[planes_count].dcc.enable);
8196 bundle->surface_updates[planes_count].plane_info =
8197 &bundle->plane_infos[planes_count];
8199 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8200 acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8201 fill_dc_dirty_rects(plane, old_plane_state,
8202 new_plane_state, new_crtc_state,
8203 &bundle->flip_addrs[planes_count],
8204 &dirty_rects_changed);
8207 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8208 * and enabled it again after dirty regions are stable to avoid video glitch.
8209 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8210 * during the PSR-SU was disabled.
8212 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8213 acrtc_attach->dm_irq_params.allow_psr_entry &&
8214 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8215 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8217 dirty_rects_changed) {
8218 mutex_lock(&dm->dc_lock);
8219 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8221 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8222 amdgpu_dm_psr_disable(acrtc_state->stream);
8223 mutex_unlock(&dm->dc_lock);
8228 * Only allow immediate flips for fast updates that don't
8229 * change memory domain, FB pitch, DCC state, rotation or
8232 * dm_crtc_helper_atomic_check() only accepts async flips with
8235 if (crtc->state->async_flip &&
8236 (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8237 get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8238 drm_warn_once(state->dev,
8239 "[PLANE:%d:%s] async flip with non-fast update\n",
8240 plane->base.id, plane->name);
8242 bundle->flip_addrs[planes_count].flip_immediate =
8243 crtc->state->async_flip &&
8244 acrtc_state->update_type == UPDATE_TYPE_FAST &&
8245 get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8247 timestamp_ns = ktime_get_ns();
8248 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8249 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8250 bundle->surface_updates[planes_count].surface = dc_plane;
8252 if (!bundle->surface_updates[planes_count].surface) {
8253 DRM_ERROR("No surface for CRTC: id=%d\n",
8254 acrtc_attach->crtc_id);
8258 if (plane == pcrtc->primary)
8259 update_freesync_state_on_stream(
8262 acrtc_state->stream,
8264 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8266 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8268 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8269 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8275 if (pflip_present) {
8277 /* Use old throttling in non-vrr fixed refresh rate mode
8278 * to keep flip scheduling based on target vblank counts
8279 * working in a backwards compatible way, e.g., for
8280 * clients using the GLX_OML_sync_control extension or
8281 * DRI3/Present extension with defined target_msc.
8283 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8285 /* For variable refresh rate mode only:
8286 * Get vblank of last completed flip to avoid > 1 vrr
8287 * flips per video frame by use of throttling, but allow
8288 * flip programming anywhere in the possibly large
8289 * variable vrr vblank interval for fine-grained flip
8290 * timing control and more opportunity to avoid stutter
8291 * on late submission of flips.
8293 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8294 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8295 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8298 target_vblank = last_flip_vblank + wait_for_vblank;
8301 * Wait until we're out of the vertical blank period before the one
8302 * targeted by the flip
8304 while ((acrtc_attach->enabled &&
8305 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8306 0, &vpos, &hpos, NULL,
8307 NULL, &pcrtc->hwmode)
8308 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8309 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8310 (int)(target_vblank -
8311 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8312 usleep_range(1000, 1100);
8316 * Prepare the flip event for the pageflip interrupt to handle.
8318 * This only works in the case where we've already turned on the
8319 * appropriate hardware blocks (eg. HUBP) so in the transition case
8320 * from 0 -> n planes we have to skip a hardware generated event
8321 * and rely on sending it from software.
8323 if (acrtc_attach->base.state->event &&
8324 acrtc_state->active_planes > 0) {
8325 drm_crtc_vblank_get(pcrtc);
8327 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8329 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8330 prepare_flip_isr(acrtc_attach);
8332 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8335 if (acrtc_state->stream) {
8336 if (acrtc_state->freesync_vrr_info_changed)
8337 bundle->stream_update.vrr_infopacket =
8338 &acrtc_state->stream->vrr_infopacket;
8340 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8341 acrtc_attach->base.state->event) {
8342 drm_crtc_vblank_get(pcrtc);
8344 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8346 acrtc_attach->event = acrtc_attach->base.state->event;
8347 acrtc_attach->base.state->event = NULL;
8349 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8352 /* Update the planes if changed or disable if we don't have any. */
8353 if ((planes_count || acrtc_state->active_planes == 0) &&
8354 acrtc_state->stream) {
8356 * If PSR or idle optimizations are enabled then flush out
8357 * any pending work before hardware programming.
8359 if (dm->vblank_control_workqueue)
8360 flush_workqueue(dm->vblank_control_workqueue);
8362 bundle->stream_update.stream = acrtc_state->stream;
8363 if (new_pcrtc_state->mode_changed) {
8364 bundle->stream_update.src = acrtc_state->stream->src;
8365 bundle->stream_update.dst = acrtc_state->stream->dst;
8368 if (new_pcrtc_state->color_mgmt_changed) {
8370 * TODO: This isn't fully correct since we've actually
8371 * already modified the stream in place.
8373 bundle->stream_update.gamut_remap =
8374 &acrtc_state->stream->gamut_remap_matrix;
8375 bundle->stream_update.output_csc_transform =
8376 &acrtc_state->stream->csc_color_matrix;
8377 bundle->stream_update.out_transfer_func =
8378 acrtc_state->stream->out_transfer_func;
8381 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8382 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8383 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8385 mutex_lock(&dm->dc_lock);
8386 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8387 acrtc_state->stream->link->psr_settings.psr_allow_active)
8388 amdgpu_dm_psr_disable(acrtc_state->stream);
8389 mutex_unlock(&dm->dc_lock);
8392 * If FreeSync state on the stream has changed then we need to
8393 * re-adjust the min/max bounds now that DC doesn't handle this
8394 * as part of commit.
8396 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8397 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8398 dc_stream_adjust_vmin_vmax(
8399 dm->dc, acrtc_state->stream,
8400 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8401 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8403 mutex_lock(&dm->dc_lock);
8404 update_planes_and_stream_adapter(dm->dc,
8405 acrtc_state->update_type,
8407 acrtc_state->stream,
8408 &bundle->stream_update,
8409 bundle->surface_updates);
8412 * Enable or disable the interrupts on the backend.
8414 * Most pipes are put into power gating when unused.
8416 * When power gating is enabled on a pipe we lose the
8417 * interrupt enablement state when power gating is disabled.
8419 * So we need to update the IRQ control state in hardware
8420 * whenever the pipe turns on (since it could be previously
8421 * power gated) or off (since some pipes can't be power gated
8424 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8425 dm_update_pflip_irq_state(drm_to_adev(dev),
8428 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8429 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8430 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8431 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8433 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8434 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8435 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8436 struct amdgpu_dm_connector *aconn =
8437 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8439 if (aconn->psr_skip_count > 0)
8440 aconn->psr_skip_count--;
8442 /* Allow PSR when skip count is 0. */
8443 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8446 * If sink supports PSR SU, there is no need to rely on
8447 * a vblank event disable request to enable PSR. PSR SU
8448 * can be enabled immediately once OS demonstrates an
8449 * adequate number of fast atomic commits to notify KMD
8450 * of update events. See `vblank_control_worker()`.
8452 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8453 acrtc_attach->dm_irq_params.allow_psr_entry &&
8454 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8455 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8457 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8459 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8461 amdgpu_dm_psr_enable(acrtc_state->stream);
8463 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8466 mutex_unlock(&dm->dc_lock);
8470 * Update cursor state *after* programming all the planes.
8471 * This avoids redundant programming in the case where we're going
8472 * to be disabling a single plane - those pipes are being disabled.
8474 if (acrtc_state->active_planes)
8475 amdgpu_dm_commit_cursors(state);
8481 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8482 struct drm_atomic_state *state)
8484 struct amdgpu_device *adev = drm_to_adev(dev);
8485 struct amdgpu_dm_connector *aconnector;
8486 struct drm_connector *connector;
8487 struct drm_connector_state *old_con_state, *new_con_state;
8488 struct drm_crtc_state *new_crtc_state;
8489 struct dm_crtc_state *new_dm_crtc_state;
8490 const struct dc_stream_status *status;
8493 /* Notify device removals. */
8494 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8495 if (old_con_state->crtc != new_con_state->crtc) {
8496 /* CRTC changes require notification. */
8500 if (!new_con_state->crtc)
8503 new_crtc_state = drm_atomic_get_new_crtc_state(
8504 state, new_con_state->crtc);
8506 if (!new_crtc_state)
8509 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8513 aconnector = to_amdgpu_dm_connector(connector);
8515 mutex_lock(&adev->dm.audio_lock);
8516 inst = aconnector->audio_inst;
8517 aconnector->audio_inst = -1;
8518 mutex_unlock(&adev->dm.audio_lock);
8520 amdgpu_dm_audio_eld_notify(adev, inst);
8523 /* Notify audio device additions. */
8524 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8525 if (!new_con_state->crtc)
8528 new_crtc_state = drm_atomic_get_new_crtc_state(
8529 state, new_con_state->crtc);
8531 if (!new_crtc_state)
8534 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8537 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8538 if (!new_dm_crtc_state->stream)
8541 status = dc_stream_get_status(new_dm_crtc_state->stream);
8545 aconnector = to_amdgpu_dm_connector(connector);
8547 mutex_lock(&adev->dm.audio_lock);
8548 inst = status->audio_inst;
8549 aconnector->audio_inst = inst;
8550 mutex_unlock(&adev->dm.audio_lock);
8552 amdgpu_dm_audio_eld_notify(adev, inst);
8557 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8558 * @crtc_state: the DRM CRTC state
8559 * @stream_state: the DC stream state.
8561 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8562 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8564 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8565 struct dc_stream_state *stream_state)
8567 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8570 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8571 struct dc_state *dc_state)
8573 struct drm_device *dev = state->dev;
8574 struct amdgpu_device *adev = drm_to_adev(dev);
8575 struct amdgpu_display_manager *dm = &adev->dm;
8576 struct drm_crtc *crtc;
8577 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8578 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8579 bool mode_set_reset_required = false;
8582 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8583 new_crtc_state, i) {
8584 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8586 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8588 if (old_crtc_state->active &&
8589 (!new_crtc_state->active ||
8590 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8591 manage_dm_interrupts(adev, acrtc, false);
8592 dc_stream_release(dm_old_crtc_state->stream);
8596 drm_atomic_helper_calc_timestamping_constants(state);
8598 /* update changed items */
8599 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8600 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8602 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8603 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8605 drm_dbg_state(state->dev,
8606 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8608 new_crtc_state->enable,
8609 new_crtc_state->active,
8610 new_crtc_state->planes_changed,
8611 new_crtc_state->mode_changed,
8612 new_crtc_state->active_changed,
8613 new_crtc_state->connectors_changed);
8615 /* Disable cursor if disabling crtc */
8616 if (old_crtc_state->active && !new_crtc_state->active) {
8617 struct dc_cursor_position position;
8619 memset(&position, 0, sizeof(position));
8620 mutex_lock(&dm->dc_lock);
8621 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8622 mutex_unlock(&dm->dc_lock);
8625 /* Copy all transient state flags into dc state */
8626 if (dm_new_crtc_state->stream) {
8627 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8628 dm_new_crtc_state->stream);
8631 /* handles headless hotplug case, updating new_state and
8632 * aconnector as needed
8635 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8637 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8639 if (!dm_new_crtc_state->stream) {
8641 * this could happen because of issues with
8642 * userspace notifications delivery.
8643 * In this case userspace tries to set mode on
8644 * display which is disconnected in fact.
8645 * dc_sink is NULL in this case on aconnector.
8646 * We expect reset mode will come soon.
8648 * This can also happen when unplug is done
8649 * during resume sequence ended
8651 * In this case, we want to pretend we still
8652 * have a sink to keep the pipe running so that
8653 * hw state is consistent with the sw state
8655 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8656 __func__, acrtc->base.base.id);
8660 if (dm_old_crtc_state->stream)
8661 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8663 pm_runtime_get_noresume(dev->dev);
8665 acrtc->enabled = true;
8666 acrtc->hw_mode = new_crtc_state->mode;
8667 crtc->hwmode = new_crtc_state->mode;
8668 mode_set_reset_required = true;
8669 } else if (modereset_required(new_crtc_state)) {
8670 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8671 /* i.e. reset mode */
8672 if (dm_old_crtc_state->stream)
8673 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8675 mode_set_reset_required = true;
8677 } /* for_each_crtc_in_state() */
8679 /* if there mode set or reset, disable eDP PSR */
8680 if (mode_set_reset_required) {
8681 if (dm->vblank_control_workqueue)
8682 flush_workqueue(dm->vblank_control_workqueue);
8684 amdgpu_dm_psr_disable_all(dm);
8687 dm_enable_per_frame_crtc_master_sync(dc_state);
8688 mutex_lock(&dm->dc_lock);
8689 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8691 /* Allow idle optimization when vblank count is 0 for display off */
8692 if (dm->active_vblank_irq_count == 0)
8693 dc_allow_idle_optimizations(dm->dc, true);
8694 mutex_unlock(&dm->dc_lock);
8696 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8697 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8699 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8701 if (dm_new_crtc_state->stream != NULL) {
8702 const struct dc_stream_status *status =
8703 dc_stream_get_status(dm_new_crtc_state->stream);
8706 status = dc_stream_get_status_from_state(dc_state,
8707 dm_new_crtc_state->stream);
8710 "got no status for stream %p on acrtc%p\n",
8711 dm_new_crtc_state->stream, acrtc);
8713 acrtc->otg_inst = status->primary_otg_inst;
8719 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8720 * @state: The atomic state to commit
8722 * This will tell DC to commit the constructed DC state from atomic_check,
8723 * programming the hardware. Any failures here implies a hardware failure, since
8724 * atomic check should have filtered anything non-kosher.
8726 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8728 struct drm_device *dev = state->dev;
8729 struct amdgpu_device *adev = drm_to_adev(dev);
8730 struct amdgpu_display_manager *dm = &adev->dm;
8731 struct dm_atomic_state *dm_state;
8732 struct dc_state *dc_state = NULL;
8734 struct drm_crtc *crtc;
8735 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8736 unsigned long flags;
8737 bool wait_for_vblank = true;
8738 struct drm_connector *connector;
8739 struct drm_connector_state *old_con_state, *new_con_state;
8740 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8741 int crtc_disable_count = 0;
8743 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8745 if (dm->dc->caps.ips_support) {
8746 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8747 if (new_con_state->crtc &&
8748 new_con_state->crtc->state->active &&
8749 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8750 dc_dmub_srv_exit_low_power_state(dm->dc);
8756 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8757 drm_dp_mst_atomic_wait_for_dependencies(state);
8759 dm_state = dm_atomic_get_new_state(state);
8760 if (dm_state && dm_state->context) {
8761 dc_state = dm_state->context;
8762 amdgpu_dm_commit_streams(state, dc_state);
8765 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8766 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8767 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8768 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8770 if (!adev->dm.hdcp_workqueue)
8773 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8778 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8779 connector->index, connector->status, connector->dpms);
8780 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8781 old_con_state->content_protection, new_con_state->content_protection);
8783 if (aconnector->dc_sink) {
8784 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8785 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8786 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8787 aconnector->dc_sink->edid_caps.display_name);
8791 new_crtc_state = NULL;
8792 old_crtc_state = NULL;
8795 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8796 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8800 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8801 old_crtc_state->enable,
8802 old_crtc_state->active,
8803 old_crtc_state->mode_changed,
8804 old_crtc_state->active_changed,
8805 old_crtc_state->connectors_changed);
8808 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8809 new_crtc_state->enable,
8810 new_crtc_state->active,
8811 new_crtc_state->mode_changed,
8812 new_crtc_state->active_changed,
8813 new_crtc_state->connectors_changed);
8816 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8817 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8818 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8819 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8821 if (!adev->dm.hdcp_workqueue)
8824 new_crtc_state = NULL;
8825 old_crtc_state = NULL;
8828 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8829 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8832 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8834 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8835 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8836 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8837 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8838 dm_new_con_state->update_hdcp = true;
8842 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8843 old_con_state, connector, adev->dm.hdcp_workqueue)) {
8844 /* when display is unplugged from mst hub, connctor will
8845 * be destroyed within dm_dp_mst_connector_destroy. connector
8846 * hdcp perperties, like type, undesired, desired, enabled,
8847 * will be lost. So, save hdcp properties into hdcp_work within
8848 * amdgpu_dm_atomic_commit_tail. if the same display is
8849 * plugged back with same display index, its hdcp properties
8850 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8853 bool enable_encryption = false;
8855 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8856 enable_encryption = true;
8858 if (aconnector->dc_link && aconnector->dc_sink &&
8859 aconnector->dc_link->type == dc_connection_mst_branch) {
8860 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8861 struct hdcp_workqueue *hdcp_w =
8862 &hdcp_work[aconnector->dc_link->link_index];
8864 hdcp_w->hdcp_content_type[connector->index] =
8865 new_con_state->hdcp_content_type;
8866 hdcp_w->content_protection[connector->index] =
8867 new_con_state->content_protection;
8870 if (new_crtc_state && new_crtc_state->mode_changed &&
8871 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8872 enable_encryption = true;
8874 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8876 hdcp_update_display(
8877 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8878 new_con_state->hdcp_content_type, enable_encryption);
8882 /* Handle connector state changes */
8883 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8884 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8885 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8886 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8887 struct dc_surface_update *dummy_updates;
8888 struct dc_stream_update stream_update;
8889 struct dc_info_packet hdr_packet;
8890 struct dc_stream_status *status = NULL;
8891 bool abm_changed, hdr_changed, scaling_changed;
8893 memset(&stream_update, 0, sizeof(stream_update));
8896 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8897 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8900 /* Skip any modesets/resets */
8901 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8904 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8905 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8907 scaling_changed = is_scaling_state_different(dm_new_con_state,
8910 abm_changed = dm_new_crtc_state->abm_level !=
8911 dm_old_crtc_state->abm_level;
8914 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8916 if (!scaling_changed && !abm_changed && !hdr_changed)
8919 stream_update.stream = dm_new_crtc_state->stream;
8920 if (scaling_changed) {
8921 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8922 dm_new_con_state, dm_new_crtc_state->stream);
8924 stream_update.src = dm_new_crtc_state->stream->src;
8925 stream_update.dst = dm_new_crtc_state->stream->dst;
8929 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8931 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8935 fill_hdr_info_packet(new_con_state, &hdr_packet);
8936 stream_update.hdr_static_metadata = &hdr_packet;
8939 status = dc_stream_get_status(dm_new_crtc_state->stream);
8941 if (WARN_ON(!status))
8944 WARN_ON(!status->plane_count);
8947 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8948 * Here we create an empty update on each plane.
8949 * To fix this, DC should permit updating only stream properties.
8951 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8952 for (j = 0; j < status->plane_count; j++)
8953 dummy_updates[j].surface = status->plane_states[0];
8956 mutex_lock(&dm->dc_lock);
8957 dc_update_planes_and_stream(dm->dc,
8959 status->plane_count,
8960 dm_new_crtc_state->stream,
8962 mutex_unlock(&dm->dc_lock);
8963 kfree(dummy_updates);
8967 * Enable interrupts for CRTCs that are newly enabled or went through
8968 * a modeset. It was intentionally deferred until after the front end
8969 * state was modified to wait until the OTG was on and so the IRQ
8970 * handlers didn't access stale or invalid state.
8972 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8973 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8974 #ifdef CONFIG_DEBUG_FS
8975 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8977 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8978 if (old_crtc_state->active && !new_crtc_state->active)
8979 crtc_disable_count++;
8981 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8982 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8984 /* For freesync config update on crtc state and params for irq */
8985 update_stream_irq_parameters(dm, dm_new_crtc_state);
8987 #ifdef CONFIG_DEBUG_FS
8988 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8989 cur_crc_src = acrtc->dm_irq_params.crc_src;
8990 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8993 if (new_crtc_state->active &&
8994 (!old_crtc_state->active ||
8995 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8996 dc_stream_retain(dm_new_crtc_state->stream);
8997 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8998 manage_dm_interrupts(adev, acrtc, true);
9000 /* Handle vrr on->off / off->on transitions */
9001 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9003 #ifdef CONFIG_DEBUG_FS
9004 if (new_crtc_state->active &&
9005 (!old_crtc_state->active ||
9006 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9008 * Frontend may have changed so reapply the CRC capture
9009 * settings for the stream.
9011 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9012 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9013 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9014 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9015 acrtc->dm_irq_params.window_param.update_win = true;
9018 * It takes 2 frames for HW to stably generate CRC when
9019 * resuming from suspend, so we set skip_frame_cnt 2.
9021 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9022 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9025 if (amdgpu_dm_crtc_configure_crc_source(
9026 crtc, dm_new_crtc_state, cur_crc_src))
9027 DRM_DEBUG_DRIVER("Failed to configure crc source");
9033 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9034 if (new_crtc_state->async_flip)
9035 wait_for_vblank = false;
9037 /* update planes when needed per crtc*/
9038 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9039 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9041 if (dm_new_crtc_state->stream)
9042 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9045 /* Update audio instances for each connector. */
9046 amdgpu_dm_commit_audio(dev, state);
9048 /* restore the backlight level */
9049 for (i = 0; i < dm->num_of_edps; i++) {
9050 if (dm->backlight_dev[i] &&
9051 (dm->actual_brightness[i] != dm->brightness[i]))
9052 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9056 * send vblank event on all events not handled in flip and
9057 * mark consumed event for drm_atomic_helper_commit_hw_done
9059 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9060 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9062 if (new_crtc_state->event)
9063 drm_send_event_locked(dev, &new_crtc_state->event->base);
9065 new_crtc_state->event = NULL;
9067 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9069 /* Signal HW programming completion */
9070 drm_atomic_helper_commit_hw_done(state);
9072 if (wait_for_vblank)
9073 drm_atomic_helper_wait_for_flip_done(dev, state);
9075 drm_atomic_helper_cleanup_planes(dev, state);
9077 /* Don't free the memory if we are hitting this as part of suspend.
9078 * This way we don't free any memory during suspend; see
9079 * amdgpu_bo_free_kernel(). The memory will be freed in the first
9080 * non-suspend modeset or when the driver is torn down.
9082 if (!adev->in_suspend) {
9083 /* return the stolen vga memory back to VRAM */
9084 if (!adev->mman.keep_stolen_vga_memory)
9085 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9086 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9090 * Finally, drop a runtime PM reference for each newly disabled CRTC,
9091 * so we can put the GPU into runtime suspend if we're not driving any
9094 for (i = 0; i < crtc_disable_count; i++)
9095 pm_runtime_put_autosuspend(dev->dev);
9096 pm_runtime_mark_last_busy(dev->dev);
9099 static int dm_force_atomic_commit(struct drm_connector *connector)
9102 struct drm_device *ddev = connector->dev;
9103 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9104 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9105 struct drm_plane *plane = disconnected_acrtc->base.primary;
9106 struct drm_connector_state *conn_state;
9107 struct drm_crtc_state *crtc_state;
9108 struct drm_plane_state *plane_state;
9113 state->acquire_ctx = ddev->mode_config.acquire_ctx;
9115 /* Construct an atomic state to restore previous display setting */
9118 * Attach connectors to drm_atomic_state
9120 conn_state = drm_atomic_get_connector_state(state, connector);
9122 ret = PTR_ERR_OR_ZERO(conn_state);
9126 /* Attach crtc to drm_atomic_state*/
9127 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9129 ret = PTR_ERR_OR_ZERO(crtc_state);
9133 /* force a restore */
9134 crtc_state->mode_changed = true;
9136 /* Attach plane to drm_atomic_state */
9137 plane_state = drm_atomic_get_plane_state(state, plane);
9139 ret = PTR_ERR_OR_ZERO(plane_state);
9143 /* Call commit internally with the state we just constructed */
9144 ret = drm_atomic_commit(state);
9147 drm_atomic_state_put(state);
9149 DRM_ERROR("Restoring old state failed with %i\n", ret);
9155 * This function handles all cases when set mode does not come upon hotplug.
9156 * This includes when a display is unplugged then plugged back into the
9157 * same port and when running without usermode desktop manager supprot
9159 void dm_restore_drm_connector_state(struct drm_device *dev,
9160 struct drm_connector *connector)
9162 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9163 struct amdgpu_crtc *disconnected_acrtc;
9164 struct dm_crtc_state *acrtc_state;
9166 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9169 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9170 if (!disconnected_acrtc)
9173 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9174 if (!acrtc_state->stream)
9178 * If the previous sink is not released and different from the current,
9179 * we deduce we are in a state where we can not rely on usermode call
9180 * to turn on the display, so we do it here
9182 if (acrtc_state->stream->sink != aconnector->dc_sink)
9183 dm_force_atomic_commit(&aconnector->base);
9187 * Grabs all modesetting locks to serialize against any blocking commits,
9188 * Waits for completion of all non blocking commits.
9190 static int do_aquire_global_lock(struct drm_device *dev,
9191 struct drm_atomic_state *state)
9193 struct drm_crtc *crtc;
9194 struct drm_crtc_commit *commit;
9198 * Adding all modeset locks to aquire_ctx will
9199 * ensure that when the framework release it the
9200 * extra locks we are locking here will get released to
9202 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9207 spin_lock(&crtc->commit_lock);
9208 commit = list_first_entry_or_null(&crtc->commit_list,
9209 struct drm_crtc_commit, commit_entry);
9211 drm_crtc_commit_get(commit);
9212 spin_unlock(&crtc->commit_lock);
9218 * Make sure all pending HW programming completed and
9221 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9224 ret = wait_for_completion_interruptible_timeout(
9225 &commit->flip_done, 10*HZ);
9228 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9229 crtc->base.id, crtc->name);
9231 drm_crtc_commit_put(commit);
9234 return ret < 0 ? ret : 0;
9237 static void get_freesync_config_for_crtc(
9238 struct dm_crtc_state *new_crtc_state,
9239 struct dm_connector_state *new_con_state)
9241 struct mod_freesync_config config = {0};
9242 struct amdgpu_dm_connector *aconnector =
9243 to_amdgpu_dm_connector(new_con_state->base.connector);
9244 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9245 int vrefresh = drm_mode_vrefresh(mode);
9246 bool fs_vid_mode = false;
9248 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9249 vrefresh >= aconnector->min_vfreq &&
9250 vrefresh <= aconnector->max_vfreq;
9252 if (new_crtc_state->vrr_supported) {
9253 new_crtc_state->stream->ignore_msa_timing_param = true;
9254 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9256 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9257 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9258 config.vsif_supported = true;
9262 config.state = VRR_STATE_ACTIVE_FIXED;
9263 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9265 } else if (new_crtc_state->base.vrr_enabled) {
9266 config.state = VRR_STATE_ACTIVE_VARIABLE;
9268 config.state = VRR_STATE_INACTIVE;
9272 new_crtc_state->freesync_config = config;
9275 static void reset_freesync_config_for_crtc(
9276 struct dm_crtc_state *new_crtc_state)
9278 new_crtc_state->vrr_supported = false;
9280 memset(&new_crtc_state->vrr_infopacket, 0,
9281 sizeof(new_crtc_state->vrr_infopacket));
9285 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9286 struct drm_crtc_state *new_crtc_state)
9288 const struct drm_display_mode *old_mode, *new_mode;
9290 if (!old_crtc_state || !new_crtc_state)
9293 old_mode = &old_crtc_state->mode;
9294 new_mode = &new_crtc_state->mode;
9296 if (old_mode->clock == new_mode->clock &&
9297 old_mode->hdisplay == new_mode->hdisplay &&
9298 old_mode->vdisplay == new_mode->vdisplay &&
9299 old_mode->htotal == new_mode->htotal &&
9300 old_mode->vtotal != new_mode->vtotal &&
9301 old_mode->hsync_start == new_mode->hsync_start &&
9302 old_mode->vsync_start != new_mode->vsync_start &&
9303 old_mode->hsync_end == new_mode->hsync_end &&
9304 old_mode->vsync_end != new_mode->vsync_end &&
9305 old_mode->hskew == new_mode->hskew &&
9306 old_mode->vscan == new_mode->vscan &&
9307 (old_mode->vsync_end - old_mode->vsync_start) ==
9308 (new_mode->vsync_end - new_mode->vsync_start))
9314 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9317 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9319 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9321 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9322 den = (unsigned long long)new_crtc_state->mode.htotal *
9323 (unsigned long long)new_crtc_state->mode.vtotal;
9325 res = div_u64(num, den);
9326 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9329 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9330 struct drm_atomic_state *state,
9331 struct drm_crtc *crtc,
9332 struct drm_crtc_state *old_crtc_state,
9333 struct drm_crtc_state *new_crtc_state,
9335 bool *lock_and_validation_needed)
9337 struct dm_atomic_state *dm_state = NULL;
9338 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9339 struct dc_stream_state *new_stream;
9343 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9344 * update changed items
9346 struct amdgpu_crtc *acrtc = NULL;
9347 struct amdgpu_dm_connector *aconnector = NULL;
9348 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9349 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9353 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9354 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9355 acrtc = to_amdgpu_crtc(crtc);
9356 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9358 /* TODO This hack should go away */
9359 if (aconnector && enable) {
9360 /* Make sure fake sink is created in plug-in scenario */
9361 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9363 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9366 if (IS_ERR(drm_new_conn_state)) {
9367 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9371 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9372 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9374 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9377 new_stream = create_validate_stream_for_sink(aconnector,
9378 &new_crtc_state->mode,
9380 dm_old_crtc_state->stream);
9383 * we can have no stream on ACTION_SET if a display
9384 * was disconnected during S3, in this case it is not an
9385 * error, the OS will be updated after detection, and
9386 * will do the right thing on next atomic commit
9390 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9391 __func__, acrtc->base.base.id);
9397 * TODO: Check VSDB bits to decide whether this should
9398 * be enabled or not.
9400 new_stream->triggered_crtc_reset.enabled =
9401 dm->force_timing_sync;
9403 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9405 ret = fill_hdr_info_packet(drm_new_conn_state,
9406 &new_stream->hdr_static_metadata);
9411 * If we already removed the old stream from the context
9412 * (and set the new stream to NULL) then we can't reuse
9413 * the old stream even if the stream and scaling are unchanged.
9414 * We'll hit the BUG_ON and black screen.
9416 * TODO: Refactor this function to allow this check to work
9417 * in all conditions.
9419 if (dm_new_crtc_state->stream &&
9420 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9423 if (dm_new_crtc_state->stream &&
9424 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9425 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9426 new_crtc_state->mode_changed = false;
9427 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9428 new_crtc_state->mode_changed);
9432 /* mode_changed flag may get updated above, need to check again */
9433 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9436 drm_dbg_state(state->dev,
9437 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9439 new_crtc_state->enable,
9440 new_crtc_state->active,
9441 new_crtc_state->planes_changed,
9442 new_crtc_state->mode_changed,
9443 new_crtc_state->active_changed,
9444 new_crtc_state->connectors_changed);
9446 /* Remove stream for any changed/disabled CRTC */
9449 if (!dm_old_crtc_state->stream)
9452 /* Unset freesync video if it was active before */
9453 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9454 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9455 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9458 /* Now check if we should set freesync video mode */
9459 if (dm_new_crtc_state->stream &&
9460 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9461 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9462 is_timing_unchanged_for_freesync(new_crtc_state,
9464 new_crtc_state->mode_changed = false;
9466 "Mode change not required for front porch change, setting mode_changed to %d",
9467 new_crtc_state->mode_changed);
9469 set_freesync_fixed_config(dm_new_crtc_state);
9472 } else if (aconnector &&
9473 is_freesync_video_mode(&new_crtc_state->mode,
9475 struct drm_display_mode *high_mode;
9477 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9478 if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9479 set_freesync_fixed_config(dm_new_crtc_state);
9482 ret = dm_atomic_get_state(state, &dm_state);
9486 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9489 /* i.e. reset mode */
9490 if (dc_remove_stream_from_ctx(
9493 dm_old_crtc_state->stream) != DC_OK) {
9498 dc_stream_release(dm_old_crtc_state->stream);
9499 dm_new_crtc_state->stream = NULL;
9501 reset_freesync_config_for_crtc(dm_new_crtc_state);
9503 *lock_and_validation_needed = true;
9505 } else {/* Add stream for any updated/enabled CRTC */
9507 * Quick fix to prevent NULL pointer on new_stream when
9508 * added MST connectors not found in existing crtc_state in the chained mode
9509 * TODO: need to dig out the root cause of that
9514 if (modereset_required(new_crtc_state))
9517 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9518 dm_old_crtc_state->stream)) {
9520 WARN_ON(dm_new_crtc_state->stream);
9522 ret = dm_atomic_get_state(state, &dm_state);
9526 dm_new_crtc_state->stream = new_stream;
9528 dc_stream_retain(new_stream);
9530 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9533 if (dc_add_stream_to_ctx(
9536 dm_new_crtc_state->stream) != DC_OK) {
9541 *lock_and_validation_needed = true;
9546 /* Release extra reference */
9548 dc_stream_release(new_stream);
9551 * We want to do dc stream updates that do not require a
9552 * full modeset below.
9554 if (!(enable && aconnector && new_crtc_state->active))
9557 * Given above conditions, the dc state cannot be NULL because:
9558 * 1. We're in the process of enabling CRTCs (just been added
9559 * to the dc context, or already is on the context)
9560 * 2. Has a valid connector attached, and
9561 * 3. Is currently active and enabled.
9562 * => The dc stream state currently exists.
9564 BUG_ON(dm_new_crtc_state->stream == NULL);
9566 /* Scaling or underscan settings */
9567 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9568 drm_atomic_crtc_needs_modeset(new_crtc_state))
9569 update_stream_scaling_settings(
9570 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9573 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9576 * Color management settings. We also update color properties
9577 * when a modeset is needed, to ensure it gets reprogrammed.
9579 if (dm_new_crtc_state->base.color_mgmt_changed ||
9580 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9581 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9586 /* Update Freesync settings. */
9587 get_freesync_config_for_crtc(dm_new_crtc_state,
9594 dc_stream_release(new_stream);
9598 static bool should_reset_plane(struct drm_atomic_state *state,
9599 struct drm_plane *plane,
9600 struct drm_plane_state *old_plane_state,
9601 struct drm_plane_state *new_plane_state)
9603 struct drm_plane *other;
9604 struct drm_plane_state *old_other_state, *new_other_state;
9605 struct drm_crtc_state *new_crtc_state;
9609 * TODO: Remove this hack once the checks below are sufficient
9610 * enough to determine when we need to reset all the planes on
9613 if (state->allow_modeset)
9616 /* Exit early if we know that we're adding or removing the plane. */
9617 if (old_plane_state->crtc != new_plane_state->crtc)
9620 /* old crtc == new_crtc == NULL, plane not in context. */
9621 if (!new_plane_state->crtc)
9625 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9627 if (!new_crtc_state)
9630 /* CRTC Degamma changes currently require us to recreate planes. */
9631 if (new_crtc_state->color_mgmt_changed)
9634 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9638 * If there are any new primary or overlay planes being added or
9639 * removed then the z-order can potentially change. To ensure
9640 * correct z-order and pipe acquisition the current DC architecture
9641 * requires us to remove and recreate all existing planes.
9643 * TODO: Come up with a more elegant solution for this.
9645 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9646 struct amdgpu_framebuffer *old_afb, *new_afb;
9648 if (other->type == DRM_PLANE_TYPE_CURSOR)
9651 if (old_other_state->crtc != new_plane_state->crtc &&
9652 new_other_state->crtc != new_plane_state->crtc)
9655 if (old_other_state->crtc != new_other_state->crtc)
9658 /* Src/dst size and scaling updates. */
9659 if (old_other_state->src_w != new_other_state->src_w ||
9660 old_other_state->src_h != new_other_state->src_h ||
9661 old_other_state->crtc_w != new_other_state->crtc_w ||
9662 old_other_state->crtc_h != new_other_state->crtc_h)
9665 /* Rotation / mirroring updates. */
9666 if (old_other_state->rotation != new_other_state->rotation)
9669 /* Blending updates. */
9670 if (old_other_state->pixel_blend_mode !=
9671 new_other_state->pixel_blend_mode)
9674 /* Alpha updates. */
9675 if (old_other_state->alpha != new_other_state->alpha)
9678 /* Colorspace changes. */
9679 if (old_other_state->color_range != new_other_state->color_range ||
9680 old_other_state->color_encoding != new_other_state->color_encoding)
9683 /* Framebuffer checks fall at the end. */
9684 if (!old_other_state->fb || !new_other_state->fb)
9687 /* Pixel format changes can require bandwidth updates. */
9688 if (old_other_state->fb->format != new_other_state->fb->format)
9691 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9692 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9694 /* Tiling and DCC changes also require bandwidth updates. */
9695 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9696 old_afb->base.modifier != new_afb->base.modifier)
9703 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9704 struct drm_plane_state *new_plane_state,
9705 struct drm_framebuffer *fb)
9707 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9708 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9712 if (fb->width > new_acrtc->max_cursor_width ||
9713 fb->height > new_acrtc->max_cursor_height) {
9714 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9715 new_plane_state->fb->width,
9716 new_plane_state->fb->height);
9719 if (new_plane_state->src_w != fb->width << 16 ||
9720 new_plane_state->src_h != fb->height << 16) {
9721 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9725 /* Pitch in pixels */
9726 pitch = fb->pitches[0] / fb->format->cpp[0];
9728 if (fb->width != pitch) {
9729 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9738 /* FB pitch is supported by cursor plane */
9741 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9745 /* Core DRM takes care of checking FB modifiers, so we only need to
9746 * check tiling flags when the FB doesn't have a modifier.
9748 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9749 if (adev->family < AMDGPU_FAMILY_AI) {
9750 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9751 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9752 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9754 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9757 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9765 static int dm_update_plane_state(struct dc *dc,
9766 struct drm_atomic_state *state,
9767 struct drm_plane *plane,
9768 struct drm_plane_state *old_plane_state,
9769 struct drm_plane_state *new_plane_state,
9771 bool *lock_and_validation_needed,
9772 bool *is_top_most_overlay)
9775 struct dm_atomic_state *dm_state = NULL;
9776 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9777 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9778 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9779 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9780 struct amdgpu_crtc *new_acrtc;
9785 new_plane_crtc = new_plane_state->crtc;
9786 old_plane_crtc = old_plane_state->crtc;
9787 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9788 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9790 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9791 if (!enable || !new_plane_crtc ||
9792 drm_atomic_plane_disabling(plane->state, new_plane_state))
9795 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9797 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9798 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9802 if (new_plane_state->fb) {
9803 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9804 new_plane_state->fb);
9812 needs_reset = should_reset_plane(state, plane, old_plane_state,
9815 /* Remove any changed/removed planes */
9820 if (!old_plane_crtc)
9823 old_crtc_state = drm_atomic_get_old_crtc_state(
9824 state, old_plane_crtc);
9825 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9827 if (!dm_old_crtc_state->stream)
9830 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9831 plane->base.id, old_plane_crtc->base.id);
9833 ret = dm_atomic_get_state(state, &dm_state);
9837 if (!dc_remove_plane_from_context(
9839 dm_old_crtc_state->stream,
9840 dm_old_plane_state->dc_state,
9841 dm_state->context)) {
9846 if (dm_old_plane_state->dc_state)
9847 dc_plane_state_release(dm_old_plane_state->dc_state);
9849 dm_new_plane_state->dc_state = NULL;
9851 *lock_and_validation_needed = true;
9853 } else { /* Add new planes */
9854 struct dc_plane_state *dc_new_plane_state;
9856 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9859 if (!new_plane_crtc)
9862 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9863 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9865 if (!dm_new_crtc_state->stream)
9871 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9875 WARN_ON(dm_new_plane_state->dc_state);
9877 dc_new_plane_state = dc_create_plane_state(dc);
9878 if (!dc_new_plane_state)
9881 /* Block top most plane from being a video plane */
9882 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9883 if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9886 *is_top_most_overlay = false;
9889 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9890 plane->base.id, new_plane_crtc->base.id);
9892 ret = fill_dc_plane_attributes(
9893 drm_to_adev(new_plane_crtc->dev),
9898 dc_plane_state_release(dc_new_plane_state);
9902 ret = dm_atomic_get_state(state, &dm_state);
9904 dc_plane_state_release(dc_new_plane_state);
9909 * Any atomic check errors that occur after this will
9910 * not need a release. The plane state will be attached
9911 * to the stream, and therefore part of the atomic
9912 * state. It'll be released when the atomic state is
9915 if (!dc_add_plane_to_context(
9917 dm_new_crtc_state->stream,
9919 dm_state->context)) {
9921 dc_plane_state_release(dc_new_plane_state);
9925 dm_new_plane_state->dc_state = dc_new_plane_state;
9927 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9929 /* Tell DC to do a full surface update every time there
9930 * is a plane change. Inefficient, but works for now.
9932 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9934 *lock_and_validation_needed = true;
9941 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9942 int *src_w, int *src_h)
9944 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9945 case DRM_MODE_ROTATE_90:
9946 case DRM_MODE_ROTATE_270:
9947 *src_w = plane_state->src_h >> 16;
9948 *src_h = plane_state->src_w >> 16;
9950 case DRM_MODE_ROTATE_0:
9951 case DRM_MODE_ROTATE_180:
9953 *src_w = plane_state->src_w >> 16;
9954 *src_h = plane_state->src_h >> 16;
9960 dm_get_plane_scale(struct drm_plane_state *plane_state,
9961 int *out_plane_scale_w, int *out_plane_scale_h)
9963 int plane_src_w, plane_src_h;
9965 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9966 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9967 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9970 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9971 struct drm_crtc *crtc,
9972 struct drm_crtc_state *new_crtc_state)
9974 struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9975 struct drm_plane_state *old_plane_state, *new_plane_state;
9976 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9978 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9979 bool any_relevant_change = false;
9981 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9982 * cursor per pipe but it's going to inherit the scaling and
9983 * positioning from the underlying pipe. Check the cursor plane's
9984 * blending properties match the underlying planes'.
9987 /* If no plane was enabled or changed scaling, no need to check again */
9988 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9989 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9991 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9994 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
9995 any_relevant_change = true;
9999 if (new_plane_state->fb == old_plane_state->fb &&
10000 new_plane_state->crtc_w == old_plane_state->crtc_w &&
10001 new_plane_state->crtc_h == old_plane_state->crtc_h)
10004 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10005 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10007 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10008 any_relevant_change = true;
10013 if (!any_relevant_change)
10016 new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10017 if (IS_ERR(new_cursor_state))
10018 return PTR_ERR(new_cursor_state);
10020 if (!new_cursor_state->fb)
10023 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10025 /* Need to check all enabled planes, even if this commit doesn't change
10028 i = drm_atomic_add_affected_planes(state, crtc);
10032 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10033 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10034 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10037 /* Ignore disabled planes */
10038 if (!new_underlying_state->fb)
10041 dm_get_plane_scale(new_underlying_state,
10042 &underlying_scale_w, &underlying_scale_h);
10044 if (cursor_scale_w != underlying_scale_w ||
10045 cursor_scale_h != underlying_scale_h) {
10046 drm_dbg_atomic(crtc->dev,
10047 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10048 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10052 /* If this plane covers the whole CRTC, no need to check planes underneath */
10053 if (new_underlying_state->crtc_x <= 0 &&
10054 new_underlying_state->crtc_y <= 0 &&
10055 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10056 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10063 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10065 struct drm_connector *connector;
10066 struct drm_connector_state *conn_state, *old_conn_state;
10067 struct amdgpu_dm_connector *aconnector = NULL;
10070 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10071 if (!conn_state->crtc)
10072 conn_state = old_conn_state;
10074 if (conn_state->crtc != crtc)
10077 aconnector = to_amdgpu_dm_connector(connector);
10078 if (!aconnector->mst_output_port || !aconnector->mst_root)
10087 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10091 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10093 * @dev: The DRM device
10094 * @state: The atomic state to commit
10096 * Validate that the given atomic state is programmable by DC into hardware.
10097 * This involves constructing a &struct dc_state reflecting the new hardware
10098 * state we wish to commit, then querying DC to see if it is programmable. It's
10099 * important not to modify the existing DC state. Otherwise, atomic_check
10100 * may unexpectedly commit hardware changes.
10102 * When validating the DC state, it's important that the right locks are
10103 * acquired. For full updates case which removes/adds/updates streams on one
10104 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10105 * that any such full update commit will wait for completion of any outstanding
10106 * flip using DRMs synchronization events.
10108 * Note that DM adds the affected connectors for all CRTCs in state, when that
10109 * might not seem necessary. This is because DC stream creation requires the
10110 * DC sink, which is tied to the DRM connector state. Cleaning this up should
10111 * be possible but non-trivial - a possible TODO item.
10113 * Return: -Error code if validation failed.
10115 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10116 struct drm_atomic_state *state)
10118 struct amdgpu_device *adev = drm_to_adev(dev);
10119 struct dm_atomic_state *dm_state = NULL;
10120 struct dc *dc = adev->dm.dc;
10121 struct drm_connector *connector;
10122 struct drm_connector_state *old_con_state, *new_con_state;
10123 struct drm_crtc *crtc;
10124 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10125 struct drm_plane *plane;
10126 struct drm_plane_state *old_plane_state, *new_plane_state;
10127 enum dc_status status;
10129 bool lock_and_validation_needed = false;
10130 bool is_top_most_overlay = true;
10131 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10132 struct drm_dp_mst_topology_mgr *mgr;
10133 struct drm_dp_mst_topology_state *mst_state;
10134 struct dsc_mst_fairness_vars vars[MAX_PIPES];
10136 trace_amdgpu_dm_atomic_check_begin(state);
10138 ret = drm_atomic_helper_check_modeset(dev, state);
10140 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10144 /* Check connector changes */
10145 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10146 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10147 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10149 /* Skip connectors that are disabled or part of modeset already. */
10150 if (!new_con_state->crtc)
10153 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10154 if (IS_ERR(new_crtc_state)) {
10155 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10156 ret = PTR_ERR(new_crtc_state);
10160 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10161 dm_old_con_state->scaling != dm_new_con_state->scaling)
10162 new_crtc_state->connectors_changed = true;
10165 if (dc_resource_is_dsc_encoding_supported(dc)) {
10166 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10167 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10168 ret = add_affected_mst_dsc_crtcs(state, crtc);
10170 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10176 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10177 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10179 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10180 !new_crtc_state->color_mgmt_changed &&
10181 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10182 dm_old_crtc_state->dsc_force_changed == false)
10185 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10187 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10191 if (!new_crtc_state->enable)
10194 ret = drm_atomic_add_affected_connectors(state, crtc);
10196 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10200 ret = drm_atomic_add_affected_planes(state, crtc);
10202 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10206 if (dm_old_crtc_state->dsc_force_changed)
10207 new_crtc_state->mode_changed = true;
10211 * Add all primary and overlay planes on the CRTC to the state
10212 * whenever a plane is enabled to maintain correct z-ordering
10213 * and to enable fast surface updates.
10215 drm_for_each_crtc(crtc, dev) {
10216 bool modified = false;
10218 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10219 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10222 if (new_plane_state->crtc == crtc ||
10223 old_plane_state->crtc == crtc) {
10232 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10233 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10237 drm_atomic_get_plane_state(state, plane);
10239 if (IS_ERR(new_plane_state)) {
10240 ret = PTR_ERR(new_plane_state);
10241 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10248 * DC consults the zpos (layer_index in DC terminology) to determine the
10249 * hw plane on which to enable the hw cursor (see
10250 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10251 * atomic state, so call drm helper to normalize zpos.
10253 ret = drm_atomic_normalize_zpos(dev, state);
10255 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10259 /* Remove exiting planes if they are modified */
10260 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10261 if (old_plane_state->fb && new_plane_state->fb &&
10262 get_mem_type(old_plane_state->fb) !=
10263 get_mem_type(new_plane_state->fb))
10264 lock_and_validation_needed = true;
10266 ret = dm_update_plane_state(dc, state, plane,
10270 &lock_and_validation_needed,
10271 &is_top_most_overlay);
10273 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10278 /* Disable all crtcs which require disable */
10279 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10280 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10284 &lock_and_validation_needed);
10286 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10291 /* Enable all crtcs which require enable */
10292 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10293 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10297 &lock_and_validation_needed);
10299 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10304 /* Add new/modified planes */
10305 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10306 ret = dm_update_plane_state(dc, state, plane,
10310 &lock_and_validation_needed,
10311 &is_top_most_overlay);
10313 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10318 if (dc_resource_is_dsc_encoding_supported(dc)) {
10319 ret = pre_validate_dsc(state, &dm_state, vars);
10324 /* Run this here since we want to validate the streams we created */
10325 ret = drm_atomic_helper_check_planes(dev, state);
10327 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10331 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10332 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10333 if (dm_new_crtc_state->mpo_requested)
10334 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10337 /* Check cursor planes scaling */
10338 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10339 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10341 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10346 if (state->legacy_cursor_update) {
10348 * This is a fast cursor update coming from the plane update
10349 * helper, check if it can be done asynchronously for better
10352 state->async_update =
10353 !drm_atomic_helper_async_check(dev, state);
10356 * Skip the remaining global validation if this is an async
10357 * update. Cursor updates can be done without affecting
10358 * state or bandwidth calcs and this avoids the performance
10359 * penalty of locking the private state object and
10360 * allocating a new dc_state.
10362 if (state->async_update)
10366 /* Check scaling and underscan changes*/
10367 /* TODO Removed scaling changes validation due to inability to commit
10368 * new stream into context w\o causing full reset. Need to
10369 * decide how to handle.
10371 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10372 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10373 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10374 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10376 /* Skip any modesets/resets */
10377 if (!acrtc || drm_atomic_crtc_needs_modeset(
10378 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10381 /* Skip any thing not scale or underscan changes */
10382 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10385 lock_and_validation_needed = true;
10388 /* set the slot info for each mst_state based on the link encoding format */
10389 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10390 struct amdgpu_dm_connector *aconnector;
10391 struct drm_connector *connector;
10392 struct drm_connector_list_iter iter;
10393 u8 link_coding_cap;
10395 drm_connector_list_iter_begin(dev, &iter);
10396 drm_for_each_connector_iter(connector, &iter) {
10397 if (connector->index == mst_state->mgr->conn_base_id) {
10398 aconnector = to_amdgpu_dm_connector(connector);
10399 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10400 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10405 drm_connector_list_iter_end(&iter);
10409 * Streams and planes are reset when there are changes that affect
10410 * bandwidth. Anything that affects bandwidth needs to go through
10411 * DC global validation to ensure that the configuration can be applied
10414 * We have to currently stall out here in atomic_check for outstanding
10415 * commits to finish in this case because our IRQ handlers reference
10416 * DRM state directly - we can end up disabling interrupts too early
10419 * TODO: Remove this stall and drop DM state private objects.
10421 if (lock_and_validation_needed) {
10422 ret = dm_atomic_get_state(state, &dm_state);
10424 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10428 ret = do_aquire_global_lock(dev, state);
10430 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10434 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10436 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10441 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10443 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10448 * Perform validation of MST topology in the state:
10449 * We need to perform MST atomic check before calling
10450 * dc_validate_global_state(), or there is a chance
10451 * to get stuck in an infinite loop and hang eventually.
10453 ret = drm_dp_mst_atomic_check(state);
10455 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10458 status = dc_validate_global_state(dc, dm_state->context, true);
10459 if (status != DC_OK) {
10460 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10461 dc_status_to_str(status), status);
10467 * The commit is a fast update. Fast updates shouldn't change
10468 * the DC context, affect global validation, and can have their
10469 * commit work done in parallel with other commits not touching
10470 * the same resource. If we have a new DC context as part of
10471 * the DM atomic state from validation we need to free it and
10472 * retain the existing one instead.
10474 * Furthermore, since the DM atomic state only contains the DC
10475 * context and can safely be annulled, we can free the state
10476 * and clear the associated private object now to free
10477 * some memory and avoid a possible use-after-free later.
10480 for (i = 0; i < state->num_private_objs; i++) {
10481 struct drm_private_obj *obj = state->private_objs[i].ptr;
10483 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10484 int j = state->num_private_objs-1;
10486 dm_atomic_destroy_state(obj,
10487 state->private_objs[i].state);
10489 /* If i is not at the end of the array then the
10490 * last element needs to be moved to where i was
10491 * before the array can safely be truncated.
10494 state->private_objs[i] =
10495 state->private_objs[j];
10497 state->private_objs[j].ptr = NULL;
10498 state->private_objs[j].state = NULL;
10499 state->private_objs[j].old_state = NULL;
10500 state->private_objs[j].new_state = NULL;
10502 state->num_private_objs = j;
10508 /* Store the overall update type for use later in atomic check. */
10509 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10510 struct dm_crtc_state *dm_new_crtc_state =
10511 to_dm_crtc_state(new_crtc_state);
10514 * Only allow async flips for fast updates that don't change
10515 * the FB pitch, the DCC state, rotation, etc.
10517 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10518 drm_dbg_atomic(crtc->dev,
10519 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10520 crtc->base.id, crtc->name);
10525 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10526 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10529 /* Must be success */
10532 trace_amdgpu_dm_atomic_check_finish(state, ret);
10537 if (ret == -EDEADLK)
10538 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10539 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10540 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10542 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10544 trace_amdgpu_dm_atomic_check_finish(state, ret);
10549 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10550 struct amdgpu_dm_connector *amdgpu_dm_connector)
10553 bool capable = false;
10555 if (amdgpu_dm_connector->dc_link &&
10556 dm_helpers_dp_read_dpcd(
10558 amdgpu_dm_connector->dc_link,
10559 DP_DOWN_STREAM_PORT_COUNT,
10561 sizeof(dpcd_data))) {
10562 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10568 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10569 unsigned int offset,
10570 unsigned int total_length,
10572 unsigned int length,
10573 struct amdgpu_hdmi_vsdb_info *vsdb)
10576 union dmub_rb_cmd cmd;
10577 struct dmub_cmd_send_edid_cea *input;
10578 struct dmub_cmd_edid_cea_output *output;
10580 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10583 memset(&cmd, 0, sizeof(cmd));
10585 input = &cmd.edid_cea.data.input;
10587 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10588 cmd.edid_cea.header.sub_type = 0;
10589 cmd.edid_cea.header.payload_bytes =
10590 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10591 input->offset = offset;
10592 input->length = length;
10593 input->cea_total_length = total_length;
10594 memcpy(input->payload, data, length);
10596 res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10598 DRM_ERROR("EDID CEA parser failed\n");
10602 output = &cmd.edid_cea.data.output;
10604 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10605 if (!output->ack.success) {
10606 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10607 output->ack.offset);
10609 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10610 if (!output->amd_vsdb.vsdb_found)
10613 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10614 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10615 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10616 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10618 DRM_WARN("Unknown EDID CEA parser results\n");
10625 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10626 u8 *edid_ext, int len,
10627 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10631 /* send extension block to DMCU for parsing */
10632 for (i = 0; i < len; i += 8) {
10636 /* send 8 bytes a time */
10637 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10641 /* EDID block sent completed, expect result */
10642 int version, min_rate, max_rate;
10644 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10646 /* amd vsdb found */
10647 vsdb_info->freesync_supported = 1;
10648 vsdb_info->amd_vsdb_version = version;
10649 vsdb_info->min_refresh_rate_hz = min_rate;
10650 vsdb_info->max_refresh_rate_hz = max_rate;
10658 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10666 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10667 u8 *edid_ext, int len,
10668 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10672 /* send extension block to DMCU for parsing */
10673 for (i = 0; i < len; i += 8) {
10674 /* send 8 bytes a time */
10675 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10679 return vsdb_info->freesync_supported;
10682 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10683 u8 *edid_ext, int len,
10684 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10686 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10689 mutex_lock(&adev->dm.dc_lock);
10690 if (adev->dm.dmub_srv)
10691 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10693 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10694 mutex_unlock(&adev->dm.dc_lock);
10698 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10699 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10701 u8 *edid_ext = NULL;
10705 if (edid == NULL || edid->extensions == 0)
10708 /* Find DisplayID extension */
10709 for (i = 0; i < edid->extensions; i++) {
10710 edid_ext = (void *)(edid + (i + 1));
10711 if (edid_ext[0] == DISPLAYID_EXT)
10715 while (j < EDID_LENGTH) {
10716 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10717 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10719 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10720 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10721 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10722 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10723 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10733 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10734 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10736 u8 *edid_ext = NULL;
10738 bool valid_vsdb_found = false;
10740 /*----- drm_find_cea_extension() -----*/
10741 /* No EDID or EDID extensions */
10742 if (edid == NULL || edid->extensions == 0)
10745 /* Find CEA extension */
10746 for (i = 0; i < edid->extensions; i++) {
10747 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10748 if (edid_ext[0] == CEA_EXT)
10752 if (i == edid->extensions)
10755 /*----- cea_db_offsets() -----*/
10756 if (edid_ext[0] != CEA_EXT)
10759 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10761 return valid_vsdb_found ? i : -ENODEV;
10765 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10767 * @connector: Connector to query.
10768 * @edid: EDID from monitor
10770 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10771 * track of some of the display information in the internal data struct used by
10772 * amdgpu_dm. This function checks which type of connector we need to set the
10773 * FreeSync parameters.
10775 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10779 struct detailed_timing *timing;
10780 struct detailed_non_pixel *data;
10781 struct detailed_data_monitor_range *range;
10782 struct amdgpu_dm_connector *amdgpu_dm_connector =
10783 to_amdgpu_dm_connector(connector);
10784 struct dm_connector_state *dm_con_state = NULL;
10785 struct dc_sink *sink;
10787 struct drm_device *dev = connector->dev;
10788 struct amdgpu_device *adev = drm_to_adev(dev);
10789 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10790 bool freesync_capable = false;
10791 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10793 if (!connector->state) {
10794 DRM_ERROR("%s - Connector has no state", __func__);
10798 sink = amdgpu_dm_connector->dc_sink ?
10799 amdgpu_dm_connector->dc_sink :
10800 amdgpu_dm_connector->dc_em_sink;
10802 if (!edid || !sink) {
10803 dm_con_state = to_dm_connector_state(connector->state);
10805 amdgpu_dm_connector->min_vfreq = 0;
10806 amdgpu_dm_connector->max_vfreq = 0;
10807 amdgpu_dm_connector->pixel_clock_mhz = 0;
10808 connector->display_info.monitor_range.min_vfreq = 0;
10809 connector->display_info.monitor_range.max_vfreq = 0;
10810 freesync_capable = false;
10815 dm_con_state = to_dm_connector_state(connector->state);
10817 if (!adev->dm.freesync_module)
10820 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10821 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10822 bool edid_check_required = false;
10825 edid_check_required = is_dp_capable_without_timing_msa(
10827 amdgpu_dm_connector);
10830 if (edid_check_required == true && (edid->version > 1 ||
10831 (edid->version == 1 && edid->revision > 1))) {
10832 for (i = 0; i < 4; i++) {
10834 timing = &edid->detailed_timings[i];
10835 data = &timing->data.other_data;
10836 range = &data->data.range;
10838 * Check if monitor has continuous frequency mode
10840 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10843 * Check for flag range limits only. If flag == 1 then
10844 * no additional timing information provided.
10845 * Default GTF, GTF Secondary curve and CVT are not
10848 if (range->flags != 1)
10851 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10852 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10853 amdgpu_dm_connector->pixel_clock_mhz =
10854 range->pixel_clock_mhz * 10;
10856 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10857 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10862 if (amdgpu_dm_connector->max_vfreq -
10863 amdgpu_dm_connector->min_vfreq > 10) {
10865 freesync_capable = true;
10868 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10870 if (vsdb_info.replay_mode) {
10871 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10872 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10873 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10876 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10877 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10878 if (i >= 0 && vsdb_info.freesync_supported) {
10879 timing = &edid->detailed_timings[i];
10880 data = &timing->data.other_data;
10882 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10883 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10884 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10885 freesync_capable = true;
10887 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10888 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10892 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10894 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10895 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10896 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10898 amdgpu_dm_connector->pack_sdp_v1_3 = true;
10899 amdgpu_dm_connector->as_type = as_type;
10900 amdgpu_dm_connector->vsdb_info = vsdb_info;
10902 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10903 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10904 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10905 freesync_capable = true;
10907 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10908 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10914 dm_con_state->freesync_capable = freesync_capable;
10916 if (connector->vrr_capable_property)
10917 drm_connector_set_vrr_capable_property(connector,
10921 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10923 struct amdgpu_device *adev = drm_to_adev(dev);
10924 struct dc *dc = adev->dm.dc;
10927 mutex_lock(&adev->dm.dc_lock);
10928 if (dc->current_state) {
10929 for (i = 0; i < dc->current_state->stream_count; ++i)
10930 dc->current_state->streams[i]
10931 ->triggered_crtc_reset.enabled =
10932 adev->dm.force_timing_sync;
10934 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10935 dc_trigger_sync(dc, dc->current_state);
10937 mutex_unlock(&adev->dm.dc_lock);
10940 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10941 u32 value, const char *func_name)
10943 #ifdef DM_CHECK_ADDR_0
10944 if (address == 0) {
10945 drm_err(adev_to_drm(ctx->driver_context),
10946 "invalid register write. address = 0");
10950 cgs_write_register(ctx->cgs_device, address, value);
10951 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10954 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10955 const char *func_name)
10958 #ifdef DM_CHECK_ADDR_0
10959 if (address == 0) {
10960 drm_err(adev_to_drm(ctx->driver_context),
10961 "invalid register read; address = 0\n");
10966 if (ctx->dmub_srv &&
10967 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10968 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10973 value = cgs_read_register(ctx->cgs_device, address);
10975 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10980 int amdgpu_dm_process_dmub_aux_transfer_sync(
10981 struct dc_context *ctx,
10982 unsigned int link_index,
10983 struct aux_payload *payload,
10984 enum aux_return_code_type *operation_result)
10986 struct amdgpu_device *adev = ctx->driver_context;
10987 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10990 mutex_lock(&adev->dm.dpia_aux_lock);
10991 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10992 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10996 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10997 DRM_ERROR("wait_for_completion_timeout timeout!");
10998 *operation_result = AUX_RET_ERROR_TIMEOUT;
11002 if (p_notify->result != AUX_RET_SUCCESS) {
11004 * Transient states before tunneling is enabled could
11005 * lead to this error. We can ignore this for now.
11007 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11008 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11009 payload->address, payload->length,
11012 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11017 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11018 if (!payload->write && p_notify->aux_reply.length &&
11019 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11021 if (payload->length != p_notify->aux_reply.length) {
11022 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11023 p_notify->aux_reply.length,
11024 payload->address, payload->length);
11025 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11029 memcpy(payload->data, p_notify->aux_reply.data,
11030 p_notify->aux_reply.length);
11034 ret = p_notify->aux_reply.length;
11035 *operation_result = p_notify->result;
11037 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11038 mutex_unlock(&adev->dm.dpia_aux_lock);
11042 int amdgpu_dm_process_dmub_set_config_sync(
11043 struct dc_context *ctx,
11044 unsigned int link_index,
11045 struct set_config_cmd_payload *payload,
11046 enum set_config_status *operation_result)
11048 struct amdgpu_device *adev = ctx->driver_context;
11049 bool is_cmd_complete;
11052 mutex_lock(&adev->dm.dpia_aux_lock);
11053 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11054 link_index, payload, adev->dm.dmub_notify);
11056 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11058 *operation_result = adev->dm.dmub_notify->sc_status;
11060 DRM_ERROR("wait_for_completion_timeout timeout!");
11062 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11065 if (!is_cmd_complete)
11066 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11067 mutex_unlock(&adev->dm.dpia_aux_lock);
11071 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11073 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11076 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11078 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);