2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
44 #include "link/protocols/link_dp_capability.h"
45 #include "link/protocols/link_ddc.h"
49 #include "amdgpu_display.h"
50 #include "amdgpu_ucode.h"
52 #include "amdgpu_dm.h"
53 #include "amdgpu_dm_plane.h"
54 #include "amdgpu_dm_crtc.h"
55 #include "amdgpu_dm_hdcp.h"
56 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
67 #include "amdgpu_dm_psr.h"
69 #include "ivsrcid/ivsrcid_vislands30.h"
71 #include <linux/backlight.h>
72 #include <linux/module.h>
73 #include <linux/moduleparam.h>
74 #include <linux/types.h>
75 #include <linux/pm_runtime.h>
76 #include <linux/pci.h>
77 #include <linux/firmware.h>
78 #include <linux/component.h>
79 #include <linux/dmi.h>
81 #include <drm/display/drm_dp_mst_helper.h>
82 #include <drm/display/drm_hdmi_helper.h>
83 #include <drm/drm_atomic.h>
84 #include <drm/drm_atomic_uapi.h>
85 #include <drm/drm_atomic_helper.h>
86 #include <drm/drm_blend.h>
87 #include <drm/drm_fourcc.h>
88 #include <drm/drm_edid.h>
89 #include <drm/drm_vblank.h>
90 #include <drm/drm_audio_component.h>
91 #include <drm/drm_gem_atomic_helper.h>
92 #include <drm/drm_plane_helper.h>
94 #include <acpi/video.h>
96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
98 #include "dcn/dcn_1_0_offset.h"
99 #include "dcn/dcn_1_0_sh_mask.h"
100 #include "soc15_hw_ip.h"
101 #include "soc15_common.h"
102 #include "vega10_ip_offset.h"
104 #include "gc/gc_11_0_0_offset.h"
105 #include "gc/gc_11_0_0_sh_mask.h"
107 #include "modules/inc/mod_freesync.h"
108 #include "modules/power/power_helpers.h"
110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
144 /* Number of bytes in PSP header for firmware. */
145 #define PSP_HEADER_BYTES 0x100
147 /* Number of bytes in PSP footer for firmware. */
148 #define PSP_FOOTER_BYTES 0x100
153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
155 * requests into DC requests, and DC responses into DRM responses.
157 * The root control structure is &struct amdgpu_display_manager.
160 /* basic init/fini API */
161 static int amdgpu_dm_init(struct amdgpu_device *adev);
162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
167 switch (link->dpcd_caps.dongle_type) {
168 case DISPLAY_DONGLE_NONE:
169 return DRM_MODE_SUBCONNECTOR_Native;
170 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
171 return DRM_MODE_SUBCONNECTOR_VGA;
172 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
173 case DISPLAY_DONGLE_DP_DVI_DONGLE:
174 return DRM_MODE_SUBCONNECTOR_DVID;
175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
176 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
177 return DRM_MODE_SUBCONNECTOR_HDMIA;
178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
180 return DRM_MODE_SUBCONNECTOR_Unknown;
184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
186 struct dc_link *link = aconnector->dc_link;
187 struct drm_connector *connector = &aconnector->base;
188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
193 if (aconnector->dc_sink)
194 subconnector = get_subconnector_type(link);
196 drm_object_property_set_value(&connector->base,
197 connector->dev->mode_config.dp_subconnector_property,
202 * initializes drm_device display related structures, based on the information
203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
204 * drm_encoder, drm_mode_config
206 * Returns 0 on success
208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
209 /* removes and deallocates the drm structures, created by the above function */
210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
213 struct amdgpu_dm_connector *amdgpu_dm_connector,
215 struct amdgpu_encoder *amdgpu_encoder);
216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
217 struct amdgpu_encoder *aencoder,
218 uint32_t link_index);
220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
225 struct drm_atomic_state *state);
227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
228 static void handle_hpd_rx_irq(void *param);
231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
232 struct drm_crtc_state *new_crtc_state);
234 * dm_vblank_get_counter
237 * Get counter for number of vertical blanks
240 * struct amdgpu_device *adev - [in] desired amdgpu device
241 * int disp_idx - [in] which CRTC to get the counter from
244 * Counter for vertical blanks
246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
248 if (crtc >= adev->mode_info.num_crtc)
251 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
253 if (acrtc->dm_irq_params.stream == NULL) {
254 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
259 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
264 u32 *vbl, u32 *position)
266 u32 v_blank_start, v_blank_end, h_position, v_position;
268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
273 if (acrtc->dm_irq_params.stream == NULL) {
274 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
280 * TODO rework base driver to use values directly.
281 * for now parse it back into reg-format
283 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
289 *position = v_position | (h_position << 16);
290 *vbl = v_blank_start | (v_blank_end << 16);
296 static bool dm_is_idle(void *handle)
302 static int dm_wait_for_idle(void *handle)
308 static bool dm_check_soft_reset(void *handle)
313 static int dm_soft_reset(void *handle)
319 static struct amdgpu_crtc *
320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
323 struct drm_device *dev = adev_to_drm(adev);
324 struct drm_crtc *crtc;
325 struct amdgpu_crtc *amdgpu_crtc;
327 if (WARN_ON(otg_inst == -1))
328 return adev->mode_info.crtcs[0];
330 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
331 amdgpu_crtc = to_amdgpu_crtc(crtc);
333 if (amdgpu_crtc->otg_inst == otg_inst)
340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
341 struct dm_crtc_state *new_state)
343 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
345 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
356 for (i = 0, j = planes_count - 1; i < j; i++, j--)
357 swap(array_of_surface_update[i], array_of_surface_update[j]);
361 * update_planes_and_stream_adapter() - Send planes to be updated in DC
363 * DC has a generic way to update planes and stream via
364 * dc_update_planes_and_stream function; however, DM might need some
365 * adjustments and preparation before calling it. This function is a wrapper
366 * for the dc_update_planes_and_stream that does any required configuration
367 * before passing control to DC.
369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
372 struct dc_stream_state *stream,
373 struct dc_stream_update *stream_update,
374 struct dc_surface_update *array_of_surface_update)
376 reverse_planes_order(array_of_surface_update, planes_count);
379 * Previous frame finished and HW is ready for optimization.
381 if (update_type == UPDATE_TYPE_FAST)
382 dc_post_update_surfaces_to_stream(dc);
384 return dc_update_planes_and_stream(dc,
385 array_of_surface_update,
392 * dm_pflip_high_irq() - Handle pageflip interrupt
393 * @interrupt_params: ignored
395 * Handles the pageflip interrupt by notifying all interested parties
396 * that the pageflip has been completed.
398 static void dm_pflip_high_irq(void *interrupt_params)
400 struct amdgpu_crtc *amdgpu_crtc;
401 struct common_irq_params *irq_params = interrupt_params;
402 struct amdgpu_device *adev = irq_params->adev;
404 struct drm_pending_vblank_event *e;
405 u32 vpos, hpos, v_blank_start, v_blank_end;
408 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
410 /* IRQ could occur when in initial stage */
411 /* TODO work and BO cleanup */
412 if (amdgpu_crtc == NULL) {
413 DC_LOG_PFLIP("CRTC is null, returning.\n");
417 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
419 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
420 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
421 amdgpu_crtc->pflip_status,
422 AMDGPU_FLIP_SUBMITTED,
423 amdgpu_crtc->crtc_id,
425 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
429 /* page flip completed. */
430 e = amdgpu_crtc->event;
431 amdgpu_crtc->event = NULL;
435 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
437 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
439 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
440 &v_blank_end, &hpos, &vpos) ||
441 (vpos < v_blank_start)) {
442 /* Update to correct count and vblank timestamp if racing with
443 * vblank irq. This also updates to the correct vblank timestamp
444 * even in VRR mode, as scanout is past the front-porch atm.
446 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
448 /* Wake up userspace by sending the pageflip event with proper
449 * count and timestamp of vblank of flip completion.
452 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
454 /* Event sent, so done with vblank for this flip */
455 drm_crtc_vblank_put(&amdgpu_crtc->base);
458 /* VRR active and inside front-porch: vblank count and
459 * timestamp for pageflip event will only be up to date after
460 * drm_crtc_handle_vblank() has been executed from late vblank
461 * irq handler after start of back-porch (vline 0). We queue the
462 * pageflip event for send-out by drm_crtc_handle_vblank() with
463 * updated timestamp and count, once it runs after us.
465 * We need to open-code this instead of using the helper
466 * drm_crtc_arm_vblank_event(), as that helper would
467 * call drm_crtc_accurate_vblank_count(), which we must
468 * not call in VRR mode while we are in front-porch!
471 /* sequence will be replaced by real count during send-out. */
472 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
473 e->pipe = amdgpu_crtc->crtc_id;
475 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
479 /* Keep track of vblank of this flip for flip throttling. We use the
480 * cooked hw counter, as that one incremented at start of this vblank
481 * of pageflip completion, so last_flip_vblank is the forbidden count
482 * for queueing new pageflips if vsync + VRR is enabled.
484 amdgpu_crtc->dm_irq_params.last_flip_vblank =
485 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
487 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
488 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
490 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
491 amdgpu_crtc->crtc_id, amdgpu_crtc,
492 vrr_active, (int) !e);
495 static void dm_vupdate_high_irq(void *interrupt_params)
497 struct common_irq_params *irq_params = interrupt_params;
498 struct amdgpu_device *adev = irq_params->adev;
499 struct amdgpu_crtc *acrtc;
500 struct drm_device *drm_dev;
501 struct drm_vblank_crtc *vblank;
502 ktime_t frame_duration_ns, previous_timestamp;
506 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
509 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
510 drm_dev = acrtc->base.dev;
511 vblank = &drm_dev->vblank[acrtc->base.index];
512 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
513 frame_duration_ns = vblank->time - previous_timestamp;
515 if (frame_duration_ns > 0) {
516 trace_amdgpu_refresh_rate_track(acrtc->base.index,
518 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
519 atomic64_set(&irq_params->previous_timestamp, vblank->time);
522 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
526 /* Core vblank handling is done here after end of front-porch in
527 * vrr mode, as vblank timestamping will give valid results
528 * while now done after front-porch. This will also deliver
529 * page-flip completion events that have been queued to us
530 * if a pageflip happened inside front-porch.
533 amdgpu_dm_crtc_handle_vblank(acrtc);
535 /* BTR processing for pre-DCE12 ASICs */
536 if (acrtc->dm_irq_params.stream &&
537 adev->family < AMDGPU_FAMILY_AI) {
538 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
539 mod_freesync_handle_v_update(
540 adev->dm.freesync_module,
541 acrtc->dm_irq_params.stream,
542 &acrtc->dm_irq_params.vrr_params);
544 dc_stream_adjust_vmin_vmax(
546 acrtc->dm_irq_params.stream,
547 &acrtc->dm_irq_params.vrr_params.adjust);
548 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
555 * dm_crtc_high_irq() - Handles CRTC interrupt
556 * @interrupt_params: used for determining the CRTC instance
558 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
561 static void dm_crtc_high_irq(void *interrupt_params)
563 struct common_irq_params *irq_params = interrupt_params;
564 struct amdgpu_device *adev = irq_params->adev;
565 struct amdgpu_crtc *acrtc;
569 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
573 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
575 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
576 vrr_active, acrtc->dm_irq_params.active_planes);
579 * Core vblank handling at start of front-porch is only possible
580 * in non-vrr mode, as only there vblank timestamping will give
581 * valid results while done in front-porch. Otherwise defer it
582 * to dm_vupdate_high_irq after end of front-porch.
585 amdgpu_dm_crtc_handle_vblank(acrtc);
588 * Following stuff must happen at start of vblank, for crc
589 * computation and below-the-range btr support in vrr mode.
591 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
593 /* BTR updates need to happen before VUPDATE on Vega and above. */
594 if (adev->family < AMDGPU_FAMILY_AI)
597 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
599 if (acrtc->dm_irq_params.stream &&
600 acrtc->dm_irq_params.vrr_params.supported &&
601 acrtc->dm_irq_params.freesync_config.state ==
602 VRR_STATE_ACTIVE_VARIABLE) {
603 mod_freesync_handle_v_update(adev->dm.freesync_module,
604 acrtc->dm_irq_params.stream,
605 &acrtc->dm_irq_params.vrr_params);
607 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
608 &acrtc->dm_irq_params.vrr_params.adjust);
612 * If there aren't any active_planes then DCH HUBP may be clock-gated.
613 * In that case, pageflip completion interrupts won't fire and pageflip
614 * completion events won't get delivered. Prevent this by sending
615 * pending pageflip events from here if a flip is still pending.
617 * If any planes are enabled, use dm_pflip_high_irq() instead, to
618 * avoid race conditions between flip programming and completion,
619 * which could cause too early flip completion events.
621 if (adev->family >= AMDGPU_FAMILY_RV &&
622 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
623 acrtc->dm_irq_params.active_planes == 0) {
625 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
627 drm_crtc_vblank_put(&acrtc->base);
629 acrtc->pflip_status = AMDGPU_FLIP_NONE;
632 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
637 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
638 * DCN generation ASICs
639 * @interrupt_params: interrupt parameters
641 * Used to set crc window/read out crc value at vertical line 0 position
643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
645 struct common_irq_params *irq_params = interrupt_params;
646 struct amdgpu_device *adev = irq_params->adev;
647 struct amdgpu_crtc *acrtc;
649 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
654 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
659 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
660 * @adev: amdgpu_device pointer
661 * @notify: dmub notification structure
663 * Dmub AUX or SET_CONFIG command completion processing callback
664 * Copies dmub notification to DM which is to be read by AUX command.
665 * issuing thread and also signals the event to wake up the thread.
667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
668 struct dmub_notification *notify)
670 if (adev->dm.dmub_notify)
671 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
672 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
673 complete(&adev->dm.dmub_aux_transfer_done);
677 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
678 * @adev: amdgpu_device pointer
679 * @notify: dmub notification structure
681 * Dmub Hpd interrupt processing callback. Gets displayindex through the
682 * ink index and calls helper to do the processing.
684 static void dmub_hpd_callback(struct amdgpu_device *adev,
685 struct dmub_notification *notify)
687 struct amdgpu_dm_connector *aconnector;
688 struct amdgpu_dm_connector *hpd_aconnector = NULL;
689 struct drm_connector *connector;
690 struct drm_connector_list_iter iter;
691 struct dc_link *link;
693 struct drm_device *dev;
698 if (notify == NULL) {
699 DRM_ERROR("DMUB HPD callback notification was NULL");
703 if (notify->link_index > adev->dm.dc->link_count) {
704 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
708 link_index = notify->link_index;
709 link = adev->dm.dc->links[link_index];
712 drm_connector_list_iter_begin(dev, &iter);
713 drm_for_each_connector_iter(connector, &iter) {
714 aconnector = to_amdgpu_dm_connector(connector);
715 if (link && aconnector->dc_link == link) {
716 if (notify->type == DMUB_NOTIFICATION_HPD)
717 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
718 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
719 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
721 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
722 notify->type, link_index);
724 hpd_aconnector = aconnector;
728 drm_connector_list_iter_end(&iter);
730 if (hpd_aconnector) {
731 if (notify->type == DMUB_NOTIFICATION_HPD)
732 handle_hpd_irq_helper(hpd_aconnector);
733 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
734 handle_hpd_rx_irq(hpd_aconnector);
739 * register_dmub_notify_callback - Sets callback for DMUB notify
740 * @adev: amdgpu_device pointer
741 * @type: Type of dmub notification
742 * @callback: Dmub interrupt callback function
743 * @dmub_int_thread_offload: offload indicator
745 * API to register a dmub callback handler for a dmub notification
746 * Also sets indicator whether callback processing to be offloaded.
747 * to dmub interrupt handling thread
748 * Return: true if successfully registered, false if there is existing registration
750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
751 enum dmub_notification_type type,
752 dmub_notify_interrupt_callback_t callback,
753 bool dmub_int_thread_offload)
755 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
756 adev->dm.dmub_callback[type] = callback;
757 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
764 static void dm_handle_hpd_work(struct work_struct *work)
766 struct dmub_hpd_work *dmub_hpd_wrk;
768 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
770 if (!dmub_hpd_wrk->dmub_notify) {
771 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
775 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
776 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
777 dmub_hpd_wrk->dmub_notify);
780 kfree(dmub_hpd_wrk->dmub_notify);
785 #define DMUB_TRACE_MAX_READ 64
787 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
788 * @interrupt_params: used for determining the Outbox instance
790 * Handles the Outbox Interrupt
793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
795 struct dmub_notification notify;
796 struct common_irq_params *irq_params = interrupt_params;
797 struct amdgpu_device *adev = irq_params->adev;
798 struct amdgpu_display_manager *dm = &adev->dm;
799 struct dmcub_trace_buf_entry entry = { 0 };
801 struct dmub_hpd_work *dmub_hpd_wrk;
802 struct dc_link *plink = NULL;
804 if (dc_enable_dmub_notifications(adev->dm.dc) &&
805 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
808 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
809 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
810 DRM_ERROR("DM: notify type %d invalid!", notify.type);
813 if (!dm->dmub_callback[notify.type]) {
814 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
817 if (dm->dmub_thread_offload[notify.type] == true) {
818 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
820 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
823 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification),
825 if (!dmub_hpd_wrk->dmub_notify) {
827 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
830 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
831 dmub_hpd_wrk->adev = adev;
832 if (notify.type == DMUB_NOTIFICATION_HPD) {
833 plink = adev->dm.dc->links[notify.link_index];
836 notify.hpd_status == DP_HPD_PLUG;
839 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
841 dm->dmub_callback[notify.type](adev, ¬ify);
843 } while (notify.pending_notification);
848 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
849 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
850 entry.param0, entry.param1);
852 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
853 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
859 } while (count <= DMUB_TRACE_MAX_READ);
861 if (count > DMUB_TRACE_MAX_READ)
862 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
865 static int dm_set_clockgating_state(void *handle,
866 enum amd_clockgating_state state)
871 static int dm_set_powergating_state(void *handle,
872 enum amd_powergating_state state)
877 /* Prototypes of private functions */
878 static int dm_early_init(void* handle);
880 /* Allocate memory for FBC compressed data */
881 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
883 struct drm_device *dev = connector->dev;
884 struct amdgpu_device *adev = drm_to_adev(dev);
885 struct dm_compressor_info *compressor = &adev->dm.compressor;
886 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
887 struct drm_display_mode *mode;
888 unsigned long max_size = 0;
890 if (adev->dm.dc->fbc_compressor == NULL)
893 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
896 if (compressor->bo_ptr)
900 list_for_each_entry(mode, &connector->modes, head) {
901 if (max_size < mode->htotal * mode->vtotal)
902 max_size = mode->htotal * mode->vtotal;
906 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
907 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
908 &compressor->gpu_addr, &compressor->cpu_addr);
911 DRM_ERROR("DM: Failed to initialize FBC\n");
913 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
914 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
921 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
922 int pipe, bool *enabled,
923 unsigned char *buf, int max_bytes)
925 struct drm_device *dev = dev_get_drvdata(kdev);
926 struct amdgpu_device *adev = drm_to_adev(dev);
927 struct drm_connector *connector;
928 struct drm_connector_list_iter conn_iter;
929 struct amdgpu_dm_connector *aconnector;
934 mutex_lock(&adev->dm.audio_lock);
936 drm_connector_list_iter_begin(dev, &conn_iter);
937 drm_for_each_connector_iter(connector, &conn_iter) {
938 aconnector = to_amdgpu_dm_connector(connector);
939 if (aconnector->audio_inst != port)
943 ret = drm_eld_size(connector->eld);
944 memcpy(buf, connector->eld, min(max_bytes, ret));
948 drm_connector_list_iter_end(&conn_iter);
950 mutex_unlock(&adev->dm.audio_lock);
952 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
957 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
958 .get_eld = amdgpu_dm_audio_component_get_eld,
961 static int amdgpu_dm_audio_component_bind(struct device *kdev,
962 struct device *hda_kdev, void *data)
964 struct drm_device *dev = dev_get_drvdata(kdev);
965 struct amdgpu_device *adev = drm_to_adev(dev);
966 struct drm_audio_component *acomp = data;
968 acomp->ops = &amdgpu_dm_audio_component_ops;
970 adev->dm.audio_component = acomp;
975 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
976 struct device *hda_kdev, void *data)
978 struct drm_device *dev = dev_get_drvdata(kdev);
979 struct amdgpu_device *adev = drm_to_adev(dev);
980 struct drm_audio_component *acomp = data;
984 adev->dm.audio_component = NULL;
987 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
988 .bind = amdgpu_dm_audio_component_bind,
989 .unbind = amdgpu_dm_audio_component_unbind,
992 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
999 adev->mode_info.audio.enabled = true;
1001 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1003 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1004 adev->mode_info.audio.pin[i].channels = -1;
1005 adev->mode_info.audio.pin[i].rate = -1;
1006 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1007 adev->mode_info.audio.pin[i].status_bits = 0;
1008 adev->mode_info.audio.pin[i].category_code = 0;
1009 adev->mode_info.audio.pin[i].connected = false;
1010 adev->mode_info.audio.pin[i].id =
1011 adev->dm.dc->res_pool->audios[i]->inst;
1012 adev->mode_info.audio.pin[i].offset = 0;
1015 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1019 adev->dm.audio_registered = true;
1024 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1029 if (!adev->mode_info.audio.enabled)
1032 if (adev->dm.audio_registered) {
1033 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1034 adev->dm.audio_registered = false;
1037 /* TODO: Disable audio? */
1039 adev->mode_info.audio.enabled = false;
1042 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1044 struct drm_audio_component *acomp = adev->dm.audio_component;
1046 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1047 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1049 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1054 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1056 const struct dmcub_firmware_header_v1_0 *hdr;
1057 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1058 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1059 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1060 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1061 struct abm *abm = adev->dm.dc->res_pool->abm;
1062 struct dmub_srv_hw_params hw_params;
1063 enum dmub_status status;
1064 const unsigned char *fw_inst_const, *fw_bss_data;
1065 u32 i, fw_inst_const_size, fw_bss_data_size;
1066 bool has_hw_support;
1069 /* DMUB isn't supported on the ASIC. */
1073 DRM_ERROR("No framebuffer info for DMUB service.\n");
1078 /* Firmware required for DMUB support. */
1079 DRM_ERROR("No firmware provided for DMUB.\n");
1083 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1084 if (status != DMUB_STATUS_OK) {
1085 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1089 if (!has_hw_support) {
1090 DRM_INFO("DMUB unsupported on ASIC\n");
1094 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1095 status = dmub_srv_hw_reset(dmub_srv);
1096 if (status != DMUB_STATUS_OK)
1097 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1099 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1101 fw_inst_const = dmub_fw->data +
1102 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1105 fw_bss_data = dmub_fw->data +
1106 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1107 le32_to_cpu(hdr->inst_const_bytes);
1109 /* Copy firmware and bios info into FB memory. */
1110 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1111 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1113 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1115 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1116 * amdgpu_ucode_init_single_fw will load dmub firmware
1117 * fw_inst_const part to cw0; otherwise, the firmware back door load
1118 * will be done by dm_dmub_hw_init
1120 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1121 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1122 fw_inst_const_size);
1125 if (fw_bss_data_size)
1126 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1127 fw_bss_data, fw_bss_data_size);
1129 /* Copy firmware bios info into FB memory. */
1130 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1133 /* Reset regions that need to be reset. */
1134 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1135 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1137 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1138 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1140 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1141 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1143 /* Initialize hardware. */
1144 memset(&hw_params, 0, sizeof(hw_params));
1145 hw_params.fb_base = adev->gmc.fb_start;
1146 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1148 /* backdoor load firmware and trigger dmub running */
1149 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1150 hw_params.load_inst_const = true;
1153 hw_params.psp_version = dmcu->psp_version;
1155 for (i = 0; i < fb_info->num_fb; ++i)
1156 hw_params.fb[i] = &fb_info->fb[i];
1158 switch (adev->ip_versions[DCE_HWIP][0]) {
1159 case IP_VERSION(3, 1, 3):
1160 case IP_VERSION(3, 1, 4):
1161 hw_params.dpia_supported = true;
1162 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1168 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1169 if (status != DMUB_STATUS_OK) {
1170 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1174 /* Wait for firmware load to finish. */
1175 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1176 if (status != DMUB_STATUS_OK)
1177 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1179 /* Init DMCU and ABM if available. */
1181 dmcu->funcs->dmcu_init(dmcu);
1182 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1185 if (!adev->dm.dc->ctx->dmub_srv)
1186 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1187 if (!adev->dm.dc->ctx->dmub_srv) {
1188 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1192 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1193 adev->dm.dmcub_fw_version);
1198 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1200 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1201 enum dmub_status status;
1205 /* DMUB isn't supported on the ASIC. */
1209 status = dmub_srv_is_hw_init(dmub_srv, &init);
1210 if (status != DMUB_STATUS_OK)
1211 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1213 if (status == DMUB_STATUS_OK && init) {
1214 /* Wait for firmware load to finish. */
1215 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1216 if (status != DMUB_STATUS_OK)
1217 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1219 /* Perform the full hardware initialization. */
1220 dm_dmub_hw_init(adev);
1224 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1227 u32 logical_addr_low;
1228 u32 logical_addr_high;
1229 u32 agp_base, agp_bot, agp_top;
1230 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1232 memset(pa_config, 0, sizeof(*pa_config));
1235 agp_bot = adev->gmc.agp_start >> 24;
1236 agp_top = adev->gmc.agp_end >> 24;
1238 /* AGP aperture is disabled */
1239 if (agp_bot == agp_top) {
1240 logical_addr_low = adev->gmc.fb_start >> 18;
1241 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1243 * Raven2 has a HW issue that it is unable to use the vram which
1244 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1245 * workaround that increase system aperture high address (add 1)
1246 * to get rid of the VM fault and hardware hang.
1248 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1250 logical_addr_high = adev->gmc.fb_end >> 18;
1252 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1253 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1255 * Raven2 has a HW issue that it is unable to use the vram which
1256 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1257 * workaround that increase system aperture high address (add 1)
1258 * to get rid of the VM fault and hardware hang.
1260 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1262 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1265 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1267 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1268 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1269 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1270 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1271 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1272 page_table_base.low_part = lower_32_bits(pt_base);
1274 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1275 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1277 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1278 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1279 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1281 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1282 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1283 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1285 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1286 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1287 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1289 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1293 static void force_connector_state(
1294 struct amdgpu_dm_connector *aconnector,
1295 enum drm_connector_force force_state)
1297 struct drm_connector *connector = &aconnector->base;
1299 mutex_lock(&connector->dev->mode_config.mutex);
1300 aconnector->base.force = force_state;
1301 mutex_unlock(&connector->dev->mode_config.mutex);
1303 mutex_lock(&aconnector->hpd_lock);
1304 drm_kms_helper_connector_hotplug_event(connector);
1305 mutex_unlock(&aconnector->hpd_lock);
1308 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1310 struct hpd_rx_irq_offload_work *offload_work;
1311 struct amdgpu_dm_connector *aconnector;
1312 struct dc_link *dc_link;
1313 struct amdgpu_device *adev;
1314 enum dc_connection_type new_connection_type = dc_connection_none;
1315 unsigned long flags;
1316 union test_response test_response;
1318 memset(&test_response, 0, sizeof(test_response));
1320 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1321 aconnector = offload_work->offload_wq->aconnector;
1324 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1328 adev = drm_to_adev(aconnector->base.dev);
1329 dc_link = aconnector->dc_link;
1331 mutex_lock(&aconnector->hpd_lock);
1332 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1333 DRM_ERROR("KMS: Failed to detect connector\n");
1334 mutex_unlock(&aconnector->hpd_lock);
1336 if (new_connection_type == dc_connection_none)
1339 if (amdgpu_in_reset(adev))
1342 mutex_lock(&adev->dm.dc_lock);
1343 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1344 dc_link_dp_handle_automated_test(dc_link);
1346 if (aconnector->timing_changed) {
1347 /* force connector disconnect and reconnect */
1348 force_connector_state(aconnector, DRM_FORCE_OFF);
1350 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1353 test_response.bits.ACK = 1;
1355 core_link_write_dpcd(
1359 sizeof(test_response));
1361 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1362 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1363 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1364 /* offload_work->data is from handle_hpd_rx_irq->
1365 * schedule_hpd_rx_offload_work.this is defer handle
1366 * for hpd short pulse. upon here, link status may be
1367 * changed, need get latest link status from dpcd
1368 * registers. if link status is good, skip run link
1371 union hpd_irq_data irq_data;
1373 memset(&irq_data, 0, sizeof(irq_data));
1375 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1376 * request be added to work queue if link lost at end of dc_link_
1377 * dp_handle_link_loss
1379 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1380 offload_work->offload_wq->is_handling_link_loss = false;
1381 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1383 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1384 dc_link_check_link_loss_status(dc_link, &irq_data))
1385 dc_link_dp_handle_link_loss(dc_link);
1387 mutex_unlock(&adev->dm.dc_lock);
1390 kfree(offload_work);
1394 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1396 int max_caps = dc->caps.max_links;
1398 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1400 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1402 if (!hpd_rx_offload_wq)
1406 for (i = 0; i < max_caps; i++) {
1407 hpd_rx_offload_wq[i].wq =
1408 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1410 if (hpd_rx_offload_wq[i].wq == NULL) {
1411 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1415 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1418 return hpd_rx_offload_wq;
1421 for (i = 0; i < max_caps; i++) {
1422 if (hpd_rx_offload_wq[i].wq)
1423 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1425 kfree(hpd_rx_offload_wq);
1429 struct amdgpu_stutter_quirk {
1437 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1438 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1439 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1443 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1445 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1447 while (p && p->chip_device != 0) {
1448 if (pdev->vendor == p->chip_vendor &&
1449 pdev->device == p->chip_device &&
1450 pdev->subsystem_vendor == p->subsys_vendor &&
1451 pdev->subsystem_device == p->subsys_device &&
1452 pdev->revision == p->revision) {
1460 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1463 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1469 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1475 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1481 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1487 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1493 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1499 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1505 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1511 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1512 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1516 /* TODO: refactor this from a fixed table to a dynamic option */
1519 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1521 const struct dmi_system_id *dmi_id;
1523 dm->aux_hpd_discon_quirk = false;
1525 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1527 dm->aux_hpd_discon_quirk = true;
1528 DRM_INFO("aux_hpd_discon_quirk attached\n");
1532 static int amdgpu_dm_init(struct amdgpu_device *adev)
1534 struct dc_init_data init_data;
1535 struct dc_callback_init init_params;
1538 adev->dm.ddev = adev_to_drm(adev);
1539 adev->dm.adev = adev;
1541 /* Zero all the fields */
1542 memset(&init_data, 0, sizeof(init_data));
1543 memset(&init_params, 0, sizeof(init_params));
1545 mutex_init(&adev->dm.dpia_aux_lock);
1546 mutex_init(&adev->dm.dc_lock);
1547 mutex_init(&adev->dm.audio_lock);
1549 if(amdgpu_dm_irq_init(adev)) {
1550 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1554 init_data.asic_id.chip_family = adev->family;
1556 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1557 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1558 init_data.asic_id.chip_id = adev->pdev->device;
1560 init_data.asic_id.vram_width = adev->gmc.vram_width;
1561 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1562 init_data.asic_id.atombios_base_address =
1563 adev->mode_info.atom_context->bios;
1565 init_data.driver = adev;
1567 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1569 if (!adev->dm.cgs_device) {
1570 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1574 init_data.cgs_device = adev->dm.cgs_device;
1576 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1578 switch (adev->ip_versions[DCE_HWIP][0]) {
1579 case IP_VERSION(2, 1, 0):
1580 switch (adev->dm.dmcub_fw_version) {
1581 case 0: /* development */
1582 case 0x1: /* linux-firmware.git hash 6d9f399 */
1583 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1584 init_data.flags.disable_dmcu = false;
1587 init_data.flags.disable_dmcu = true;
1590 case IP_VERSION(2, 0, 3):
1591 init_data.flags.disable_dmcu = true;
1597 switch (adev->asic_type) {
1600 init_data.flags.gpu_vm_support = true;
1603 switch (adev->ip_versions[DCE_HWIP][0]) {
1604 case IP_VERSION(1, 0, 0):
1605 case IP_VERSION(1, 0, 1):
1606 /* enable S/G on PCO and RV2 */
1607 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1608 (adev->apu_flags & AMD_APU_IS_PICASSO))
1609 init_data.flags.gpu_vm_support = true;
1611 case IP_VERSION(2, 1, 0):
1612 case IP_VERSION(3, 0, 1):
1613 case IP_VERSION(3, 1, 2):
1614 case IP_VERSION(3, 1, 3):
1615 case IP_VERSION(3, 1, 4):
1616 case IP_VERSION(3, 1, 5):
1617 case IP_VERSION(3, 1, 6):
1618 init_data.flags.gpu_vm_support = true;
1625 if (init_data.flags.gpu_vm_support &&
1626 (amdgpu_sg_display == 0))
1627 init_data.flags.gpu_vm_support = false;
1629 if (init_data.flags.gpu_vm_support)
1630 adev->mode_info.gpu_vm_support = true;
1632 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1633 init_data.flags.fbc_support = true;
1635 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1636 init_data.flags.multi_mon_pp_mclk_switch = true;
1638 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1639 init_data.flags.disable_fractional_pwm = true;
1641 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1642 init_data.flags.edp_no_power_sequencing = true;
1644 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1645 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1646 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1647 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1649 /* Disable SubVP + DRR config by default */
1650 init_data.flags.disable_subvp_drr = true;
1651 if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1652 init_data.flags.disable_subvp_drr = false;
1654 init_data.flags.seamless_boot_edp_requested = false;
1656 if (check_seamless_boot_capability(adev)) {
1657 init_data.flags.seamless_boot_edp_requested = true;
1658 init_data.flags.allow_seamless_boot_optimization = true;
1659 DRM_INFO("Seamless boot condition check passed\n");
1662 init_data.flags.enable_mipi_converter_optimization = true;
1664 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1665 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1667 INIT_LIST_HEAD(&adev->dm.da_list);
1669 retrieve_dmi_info(&adev->dm);
1671 /* Display Core create. */
1672 adev->dm.dc = dc_create(&init_data);
1675 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1677 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1681 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1682 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1683 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1686 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1687 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1688 if (dm_should_disable_stutter(adev->pdev))
1689 adev->dm.dc->debug.disable_stutter = true;
1691 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1692 adev->dm.dc->debug.disable_stutter = true;
1694 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1695 adev->dm.dc->debug.disable_dsc = true;
1698 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1699 adev->dm.dc->debug.disable_clock_gate = true;
1701 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1702 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1704 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1706 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1707 adev->dm.dc->debug.ignore_cable_id = true;
1709 /* TODO: There is a new drm mst change where the freedom of
1710 * vc_next_start_slot update is revoked/moved into drm, instead of in
1711 * driver. This forces us to make sure to get vc_next_start_slot updated
1712 * in drm function each time without considering if mst_state is active
1713 * or not. Otherwise, next time hotplug will give wrong start_slot
1714 * number. We are implementing a temporary solution to even notify drm
1715 * mst deallocation when link is no longer of MST type when uncommitting
1716 * the stream so we will have more time to work on a proper solution.
1717 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1718 * should notify drm to do a complete "reset" of its states and stop
1719 * calling further drm mst functions when link is no longer of an MST
1720 * type. This could happen when we unplug an MST hubs/displays. When
1721 * uncommit stream comes later after unplug, we should just reset
1722 * hardware states only.
1724 adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1726 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1727 DRM_INFO("DP-HDMI FRL PCON supported\n");
1729 r = dm_dmub_hw_init(adev);
1731 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1735 dc_hardware_init(adev->dm.dc);
1737 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1738 if (!adev->dm.hpd_rx_offload_wq) {
1739 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1743 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1744 struct dc_phy_addr_space_config pa_config;
1746 mmhub_read_system_context(adev, &pa_config);
1748 // Call the DC init_memory func
1749 dc_setup_system_context(adev->dm.dc, &pa_config);
1752 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1753 if (!adev->dm.freesync_module) {
1755 "amdgpu: failed to initialize freesync_module.\n");
1757 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1758 adev->dm.freesync_module);
1760 amdgpu_dm_init_color_mod();
1762 if (adev->dm.dc->caps.max_links > 0) {
1763 adev->dm.vblank_control_workqueue =
1764 create_singlethread_workqueue("dm_vblank_control_workqueue");
1765 if (!adev->dm.vblank_control_workqueue)
1766 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1769 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1770 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1772 if (!adev->dm.hdcp_workqueue)
1773 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1775 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1777 dc_init_callbacks(adev->dm.dc, &init_params);
1779 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1780 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1781 if (!adev->dm.secure_display_ctxs) {
1782 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1785 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1786 init_completion(&adev->dm.dmub_aux_transfer_done);
1787 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1788 if (!adev->dm.dmub_notify) {
1789 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1793 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1794 if (!adev->dm.delayed_hpd_wq) {
1795 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1799 amdgpu_dm_outbox_init(adev);
1800 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1801 dmub_aux_setconfig_callback, false)) {
1802 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1805 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1806 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1809 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1810 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1815 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1816 * It is expected that DMUB will resend any pending notifications at this point, for
1817 * example HPD from DPIA.
1819 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1820 dc_enable_dmub_outbox(adev->dm.dc);
1822 if (amdgpu_dm_initialize_drm_device(adev)) {
1824 "amdgpu: failed to initialize sw for display support.\n");
1828 /* create fake encoders for MST */
1829 dm_dp_create_fake_mst_encoders(adev);
1831 /* TODO: Add_display_info? */
1833 /* TODO use dynamic cursor width */
1834 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1835 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1837 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1839 "amdgpu: failed to initialize sw for display support.\n");
1844 DRM_DEBUG_DRIVER("KMS initialized.\n");
1848 amdgpu_dm_fini(adev);
1853 static int amdgpu_dm_early_fini(void *handle)
1855 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1857 amdgpu_dm_audio_fini(adev);
1862 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1866 if (adev->dm.vblank_control_workqueue) {
1867 destroy_workqueue(adev->dm.vblank_control_workqueue);
1868 adev->dm.vblank_control_workqueue = NULL;
1871 amdgpu_dm_destroy_drm_device(&adev->dm);
1873 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1874 if (adev->dm.secure_display_ctxs) {
1875 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1876 if (adev->dm.secure_display_ctxs[i].crtc) {
1877 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1878 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1881 kfree(adev->dm.secure_display_ctxs);
1882 adev->dm.secure_display_ctxs = NULL;
1885 if (adev->dm.hdcp_workqueue) {
1886 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1887 adev->dm.hdcp_workqueue = NULL;
1891 dc_deinit_callbacks(adev->dm.dc);
1893 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1895 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1896 kfree(adev->dm.dmub_notify);
1897 adev->dm.dmub_notify = NULL;
1898 destroy_workqueue(adev->dm.delayed_hpd_wq);
1899 adev->dm.delayed_hpd_wq = NULL;
1902 if (adev->dm.dmub_bo)
1903 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1904 &adev->dm.dmub_bo_gpu_addr,
1905 &adev->dm.dmub_bo_cpu_addr);
1907 if (adev->dm.hpd_rx_offload_wq) {
1908 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1909 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1910 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1911 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1915 kfree(adev->dm.hpd_rx_offload_wq);
1916 adev->dm.hpd_rx_offload_wq = NULL;
1919 /* DC Destroy TODO: Replace destroy DAL */
1921 dc_destroy(&adev->dm.dc);
1923 * TODO: pageflip, vlank interrupt
1925 * amdgpu_dm_irq_fini(adev);
1928 if (adev->dm.cgs_device) {
1929 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1930 adev->dm.cgs_device = NULL;
1932 if (adev->dm.freesync_module) {
1933 mod_freesync_destroy(adev->dm.freesync_module);
1934 adev->dm.freesync_module = NULL;
1937 mutex_destroy(&adev->dm.audio_lock);
1938 mutex_destroy(&adev->dm.dc_lock);
1939 mutex_destroy(&adev->dm.dpia_aux_lock);
1944 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 const char *fw_name_dmcu = NULL;
1948 const struct dmcu_firmware_header_v1_0 *hdr;
1950 switch(adev->asic_type) {
1951 #if defined(CONFIG_DRM_AMD_DC_SI)
1966 case CHIP_POLARIS11:
1967 case CHIP_POLARIS10:
1968 case CHIP_POLARIS12:
1975 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1978 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1979 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1980 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1981 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1986 switch (adev->ip_versions[DCE_HWIP][0]) {
1987 case IP_VERSION(2, 0, 2):
1988 case IP_VERSION(2, 0, 3):
1989 case IP_VERSION(2, 0, 0):
1990 case IP_VERSION(2, 1, 0):
1991 case IP_VERSION(3, 0, 0):
1992 case IP_VERSION(3, 0, 2):
1993 case IP_VERSION(3, 0, 3):
1994 case IP_VERSION(3, 0, 1):
1995 case IP_VERSION(3, 1, 2):
1996 case IP_VERSION(3, 1, 3):
1997 case IP_VERSION(3, 1, 4):
1998 case IP_VERSION(3, 1, 5):
1999 case IP_VERSION(3, 1, 6):
2000 case IP_VERSION(3, 2, 0):
2001 case IP_VERSION(3, 2, 1):
2006 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2010 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2011 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2015 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2017 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2018 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2019 adev->dm.fw_dmcu = NULL;
2023 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2025 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2029 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2030 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2031 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2032 adev->firmware.fw_size +=
2033 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2035 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2036 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2037 adev->firmware.fw_size +=
2038 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2040 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2042 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2047 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2049 struct amdgpu_device *adev = ctx;
2051 return dm_read_reg(adev->dm.dc->ctx, address);
2054 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2057 struct amdgpu_device *adev = ctx;
2059 return dm_write_reg(adev->dm.dc->ctx, address, value);
2062 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2064 struct dmub_srv_create_params create_params;
2065 struct dmub_srv_region_params region_params;
2066 struct dmub_srv_region_info region_info;
2067 struct dmub_srv_fb_params fb_params;
2068 struct dmub_srv_fb_info *fb_info;
2069 struct dmub_srv *dmub_srv;
2070 const struct dmcub_firmware_header_v1_0 *hdr;
2071 enum dmub_asic dmub_asic;
2072 enum dmub_status status;
2075 switch (adev->ip_versions[DCE_HWIP][0]) {
2076 case IP_VERSION(2, 1, 0):
2077 dmub_asic = DMUB_ASIC_DCN21;
2079 case IP_VERSION(3, 0, 0):
2080 dmub_asic = DMUB_ASIC_DCN30;
2082 case IP_VERSION(3, 0, 1):
2083 dmub_asic = DMUB_ASIC_DCN301;
2085 case IP_VERSION(3, 0, 2):
2086 dmub_asic = DMUB_ASIC_DCN302;
2088 case IP_VERSION(3, 0, 3):
2089 dmub_asic = DMUB_ASIC_DCN303;
2091 case IP_VERSION(3, 1, 2):
2092 case IP_VERSION(3, 1, 3):
2093 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2095 case IP_VERSION(3, 1, 4):
2096 dmub_asic = DMUB_ASIC_DCN314;
2098 case IP_VERSION(3, 1, 5):
2099 dmub_asic = DMUB_ASIC_DCN315;
2101 case IP_VERSION(3, 1, 6):
2102 dmub_asic = DMUB_ASIC_DCN316;
2104 case IP_VERSION(3, 2, 0):
2105 dmub_asic = DMUB_ASIC_DCN32;
2107 case IP_VERSION(3, 2, 1):
2108 dmub_asic = DMUB_ASIC_DCN321;
2111 /* ASIC doesn't support DMUB. */
2115 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2116 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2119 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2120 AMDGPU_UCODE_ID_DMCUB;
2121 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2123 adev->firmware.fw_size +=
2124 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2126 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2127 adev->dm.dmcub_fw_version);
2131 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2132 dmub_srv = adev->dm.dmub_srv;
2135 DRM_ERROR("Failed to allocate DMUB service!\n");
2139 memset(&create_params, 0, sizeof(create_params));
2140 create_params.user_ctx = adev;
2141 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2142 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2143 create_params.asic = dmub_asic;
2145 /* Create the DMUB service. */
2146 status = dmub_srv_create(dmub_srv, &create_params);
2147 if (status != DMUB_STATUS_OK) {
2148 DRM_ERROR("Error creating DMUB service: %d\n", status);
2152 /* Calculate the size of all the regions for the DMUB service. */
2153 memset(®ion_params, 0, sizeof(region_params));
2155 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2156 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2157 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2158 region_params.vbios_size = adev->bios_size;
2159 region_params.fw_bss_data = region_params.bss_data_size ?
2160 adev->dm.dmub_fw->data +
2161 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2162 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2163 region_params.fw_inst_const =
2164 adev->dm.dmub_fw->data +
2165 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2168 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2171 if (status != DMUB_STATUS_OK) {
2172 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2177 * Allocate a framebuffer based on the total size of all the regions.
2178 * TODO: Move this into GART.
2180 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2181 AMDGPU_GEM_DOMAIN_VRAM |
2182 AMDGPU_GEM_DOMAIN_GTT,
2184 &adev->dm.dmub_bo_gpu_addr,
2185 &adev->dm.dmub_bo_cpu_addr);
2189 /* Rebase the regions on the framebuffer address. */
2190 memset(&fb_params, 0, sizeof(fb_params));
2191 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2192 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2193 fb_params.region_info = ®ion_info;
2195 adev->dm.dmub_fb_info =
2196 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2197 fb_info = adev->dm.dmub_fb_info;
2201 "Failed to allocate framebuffer info for DMUB service!\n");
2205 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2206 if (status != DMUB_STATUS_OK) {
2207 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2214 static int dm_sw_init(void *handle)
2216 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2219 r = dm_dmub_sw_init(adev);
2223 return load_dmcu_fw(adev);
2226 static int dm_sw_fini(void *handle)
2228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230 kfree(adev->dm.dmub_fb_info);
2231 adev->dm.dmub_fb_info = NULL;
2233 if (adev->dm.dmub_srv) {
2234 dmub_srv_destroy(adev->dm.dmub_srv);
2235 adev->dm.dmub_srv = NULL;
2238 amdgpu_ucode_release(&adev->dm.dmub_fw);
2239 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2244 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2246 struct amdgpu_dm_connector *aconnector;
2247 struct drm_connector *connector;
2248 struct drm_connector_list_iter iter;
2251 drm_connector_list_iter_begin(dev, &iter);
2252 drm_for_each_connector_iter(connector, &iter) {
2253 aconnector = to_amdgpu_dm_connector(connector);
2254 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2255 aconnector->mst_mgr.aux) {
2256 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2258 aconnector->base.base.id);
2260 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2262 DRM_ERROR("DM_MST: Failed to start MST\n");
2263 aconnector->dc_link->type =
2264 dc_connection_single;
2265 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2266 aconnector->dc_link);
2271 drm_connector_list_iter_end(&iter);
2276 static int dm_late_init(void *handle)
2278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2280 struct dmcu_iram_parameters params;
2281 unsigned int linear_lut[16];
2283 struct dmcu *dmcu = NULL;
2285 dmcu = adev->dm.dc->res_pool->dmcu;
2287 for (i = 0; i < 16; i++)
2288 linear_lut[i] = 0xFFFF * i / 15;
2291 params.backlight_ramping_override = false;
2292 params.backlight_ramping_start = 0xCCCC;
2293 params.backlight_ramping_reduction = 0xCCCCCCCC;
2294 params.backlight_lut_array_size = 16;
2295 params.backlight_lut_array = linear_lut;
2297 /* Min backlight level after ABM reduction, Don't allow below 1%
2298 * 0xFFFF x 0.01 = 0x28F
2300 params.min_abm_backlight = 0x28F;
2301 /* In the case where abm is implemented on dmcub,
2302 * dmcu object will be null.
2303 * ABM 2.4 and up are implemented on dmcub.
2306 if (!dmcu_load_iram(dmcu, params))
2308 } else if (adev->dm.dc->ctx->dmub_srv) {
2309 struct dc_link *edp_links[MAX_NUM_EDP];
2312 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2313 for (i = 0; i < edp_num; i++) {
2314 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2319 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2322 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2324 struct amdgpu_dm_connector *aconnector;
2325 struct drm_connector *connector;
2326 struct drm_connector_list_iter iter;
2327 struct drm_dp_mst_topology_mgr *mgr;
2329 bool need_hotplug = false;
2331 drm_connector_list_iter_begin(dev, &iter);
2332 drm_for_each_connector_iter(connector, &iter) {
2333 aconnector = to_amdgpu_dm_connector(connector);
2334 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2335 aconnector->mst_root)
2338 mgr = &aconnector->mst_mgr;
2341 drm_dp_mst_topology_mgr_suspend(mgr);
2343 /* if extended timeout is supported in hardware,
2344 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2345 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2347 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2348 if (!dp_is_lttpr_present(aconnector->dc_link))
2349 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2351 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2353 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2354 aconnector->dc_link);
2355 need_hotplug = true;
2359 drm_connector_list_iter_end(&iter);
2362 drm_kms_helper_hotplug_event(dev);
2365 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2369 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2370 * on window driver dc implementation.
2371 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2372 * should be passed to smu during boot up and resume from s3.
2373 * boot up: dc calculate dcn watermark clock settings within dc_create,
2374 * dcn20_resource_construct
2375 * then call pplib functions below to pass the settings to smu:
2376 * smu_set_watermarks_for_clock_ranges
2377 * smu_set_watermarks_table
2378 * navi10_set_watermarks_table
2379 * smu_write_watermarks_table
2381 * For Renoir, clock settings of dcn watermark are also fixed values.
2382 * dc has implemented different flow for window driver:
2383 * dc_hardware_init / dc_set_power_state
2388 * smu_set_watermarks_for_clock_ranges
2389 * renoir_set_watermarks_table
2390 * smu_write_watermarks_table
2393 * dc_hardware_init -> amdgpu_dm_init
2394 * dc_set_power_state --> dm_resume
2396 * therefore, this function apply to navi10/12/14 but not Renoir
2399 switch (adev->ip_versions[DCE_HWIP][0]) {
2400 case IP_VERSION(2, 0, 2):
2401 case IP_VERSION(2, 0, 0):
2407 ret = amdgpu_dpm_write_watermarks_table(adev);
2409 DRM_ERROR("Failed to update WMTABLE!\n");
2417 * dm_hw_init() - Initialize DC device
2418 * @handle: The base driver device containing the amdgpu_dm device.
2420 * Initialize the &struct amdgpu_display_manager device. This involves calling
2421 * the initializers of each DM component, then populating the struct with them.
2423 * Although the function implies hardware initialization, both hardware and
2424 * software are initialized here. Splitting them out to their relevant init
2425 * hooks is a future TODO item.
2427 * Some notable things that are initialized here:
2429 * - Display Core, both software and hardware
2430 * - DC modules that we need (freesync and color management)
2431 * - DRM software states
2432 * - Interrupt sources and handlers
2434 * - Debug FS entries, if enabled
2436 static int dm_hw_init(void *handle)
2438 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2439 /* Create DAL display manager */
2440 amdgpu_dm_init(adev);
2441 amdgpu_dm_hpd_init(adev);
2447 * dm_hw_fini() - Teardown DC device
2448 * @handle: The base driver device containing the amdgpu_dm device.
2450 * Teardown components within &struct amdgpu_display_manager that require
2451 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2452 * were loaded. Also flush IRQ workqueues and disable them.
2454 static int dm_hw_fini(void *handle)
2456 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458 amdgpu_dm_hpd_fini(adev);
2460 amdgpu_dm_irq_fini(adev);
2461 amdgpu_dm_fini(adev);
2466 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2467 struct dc_state *state, bool enable)
2469 enum dc_irq_source irq_source;
2470 struct amdgpu_crtc *acrtc;
2474 for (i = 0; i < state->stream_count; i++) {
2475 acrtc = get_crtc_by_otg_inst(
2476 adev, state->stream_status[i].primary_otg_inst);
2478 if (acrtc && state->stream_status[i].plane_count != 0) {
2479 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2480 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2481 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2482 acrtc->crtc_id, enable ? "en" : "dis", rc);
2484 DRM_WARN("Failed to %s pflip interrupts\n",
2485 enable ? "enable" : "disable");
2488 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2490 DRM_WARN("Failed to enable vblank interrupts\n");
2492 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2500 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2502 struct dc_state *context = NULL;
2503 enum dc_status res = DC_ERROR_UNEXPECTED;
2505 struct dc_stream_state *del_streams[MAX_PIPES];
2506 int del_streams_count = 0;
2508 memset(del_streams, 0, sizeof(del_streams));
2510 context = dc_create_state(dc);
2511 if (context == NULL)
2512 goto context_alloc_fail;
2514 dc_resource_state_copy_construct_current(dc, context);
2516 /* First remove from context all streams */
2517 for (i = 0; i < context->stream_count; i++) {
2518 struct dc_stream_state *stream = context->streams[i];
2520 del_streams[del_streams_count++] = stream;
2523 /* Remove all planes for removed streams and then remove the streams */
2524 for (i = 0; i < del_streams_count; i++) {
2525 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2526 res = DC_FAIL_DETACH_SURFACES;
2530 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2535 res = dc_commit_streams(dc, context->streams, context->stream_count);
2538 dc_release_state(context);
2544 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2548 if (dm->hpd_rx_offload_wq) {
2549 for (i = 0; i < dm->dc->caps.max_links; i++)
2550 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2554 static int dm_suspend(void *handle)
2556 struct amdgpu_device *adev = handle;
2557 struct amdgpu_display_manager *dm = &adev->dm;
2560 if (amdgpu_in_reset(adev)) {
2561 mutex_lock(&dm->dc_lock);
2563 dc_allow_idle_optimizations(adev->dm.dc, false);
2565 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2567 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2569 amdgpu_dm_commit_zero_streams(dm->dc);
2571 amdgpu_dm_irq_suspend(adev);
2573 hpd_rx_irq_work_suspend(dm);
2578 WARN_ON(adev->dm.cached_state);
2579 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2581 s3_handle_mst(adev_to_drm(adev), true);
2583 amdgpu_dm_irq_suspend(adev);
2585 hpd_rx_irq_work_suspend(dm);
2587 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2592 struct amdgpu_dm_connector *
2593 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2594 struct drm_crtc *crtc)
2597 struct drm_connector_state *new_con_state;
2598 struct drm_connector *connector;
2599 struct drm_crtc *crtc_from_state;
2601 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2602 crtc_from_state = new_con_state->crtc;
2604 if (crtc_from_state == crtc)
2605 return to_amdgpu_dm_connector(connector);
2611 static void emulated_link_detect(struct dc_link *link)
2613 struct dc_sink_init_data sink_init_data = { 0 };
2614 struct display_sink_capability sink_caps = { 0 };
2615 enum dc_edid_status edid_status;
2616 struct dc_context *dc_ctx = link->ctx;
2617 struct dc_sink *sink = NULL;
2618 struct dc_sink *prev_sink = NULL;
2620 link->type = dc_connection_none;
2621 prev_sink = link->local_sink;
2624 dc_sink_release(prev_sink);
2626 switch (link->connector_signal) {
2627 case SIGNAL_TYPE_HDMI_TYPE_A: {
2628 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2629 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2633 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2634 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2635 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2639 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2640 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2641 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2645 case SIGNAL_TYPE_LVDS: {
2646 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2647 sink_caps.signal = SIGNAL_TYPE_LVDS;
2651 case SIGNAL_TYPE_EDP: {
2652 sink_caps.transaction_type =
2653 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2654 sink_caps.signal = SIGNAL_TYPE_EDP;
2658 case SIGNAL_TYPE_DISPLAY_PORT: {
2659 sink_caps.transaction_type =
2660 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2661 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2666 DC_ERROR("Invalid connector type! signal:%d\n",
2667 link->connector_signal);
2671 sink_init_data.link = link;
2672 sink_init_data.sink_signal = sink_caps.signal;
2674 sink = dc_sink_create(&sink_init_data);
2676 DC_ERROR("Failed to create sink!\n");
2680 /* dc_sink_create returns a new reference */
2681 link->local_sink = sink;
2683 edid_status = dm_helpers_read_local_edid(
2688 if (edid_status != EDID_OK)
2689 DC_ERROR("Failed to read EDID");
2693 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2694 struct amdgpu_display_manager *dm)
2697 struct dc_surface_update surface_updates[MAX_SURFACES];
2698 struct dc_plane_info plane_infos[MAX_SURFACES];
2699 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2700 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2701 struct dc_stream_update stream_update;
2705 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2708 dm_error("Failed to allocate update bundle\n");
2712 for (k = 0; k < dc_state->stream_count; k++) {
2713 bundle->stream_update.stream = dc_state->streams[k];
2715 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2716 bundle->surface_updates[m].surface =
2717 dc_state->stream_status->plane_states[m];
2718 bundle->surface_updates[m].surface->force_full_update =
2722 update_planes_and_stream_adapter(dm->dc,
2724 dc_state->stream_status->plane_count,
2725 dc_state->streams[k],
2726 &bundle->stream_update,
2727 bundle->surface_updates);
2736 static int dm_resume(void *handle)
2738 struct amdgpu_device *adev = handle;
2739 struct drm_device *ddev = adev_to_drm(adev);
2740 struct amdgpu_display_manager *dm = &adev->dm;
2741 struct amdgpu_dm_connector *aconnector;
2742 struct drm_connector *connector;
2743 struct drm_connector_list_iter iter;
2744 struct drm_crtc *crtc;
2745 struct drm_crtc_state *new_crtc_state;
2746 struct dm_crtc_state *dm_new_crtc_state;
2747 struct drm_plane *plane;
2748 struct drm_plane_state *new_plane_state;
2749 struct dm_plane_state *dm_new_plane_state;
2750 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2751 enum dc_connection_type new_connection_type = dc_connection_none;
2752 struct dc_state *dc_state;
2755 if (amdgpu_in_reset(adev)) {
2756 dc_state = dm->cached_dc_state;
2759 * The dc->current_state is backed up into dm->cached_dc_state
2760 * before we commit 0 streams.
2762 * DC will clear link encoder assignments on the real state
2763 * but the changes won't propagate over to the copy we made
2764 * before the 0 streams commit.
2766 * DC expects that link encoder assignments are *not* valid
2767 * when committing a state, so as a workaround we can copy
2768 * off of the current state.
2770 * We lose the previous assignments, but we had already
2771 * commit 0 streams anyway.
2773 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2775 r = dm_dmub_hw_init(adev);
2777 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2779 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2782 amdgpu_dm_irq_resume_early(adev);
2784 for (i = 0; i < dc_state->stream_count; i++) {
2785 dc_state->streams[i]->mode_changed = true;
2786 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2787 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2792 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2793 amdgpu_dm_outbox_init(adev);
2794 dc_enable_dmub_outbox(adev->dm.dc);
2797 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2799 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2801 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2803 dc_release_state(dm->cached_dc_state);
2804 dm->cached_dc_state = NULL;
2806 amdgpu_dm_irq_resume_late(adev);
2808 mutex_unlock(&dm->dc_lock);
2812 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2813 dc_release_state(dm_state->context);
2814 dm_state->context = dc_create_state(dm->dc);
2815 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2816 dc_resource_state_construct(dm->dc, dm_state->context);
2818 /* Before powering on DC we need to re-initialize DMUB. */
2819 dm_dmub_hw_resume(adev);
2821 /* Re-enable outbox interrupts for DPIA. */
2822 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2823 amdgpu_dm_outbox_init(adev);
2824 dc_enable_dmub_outbox(adev->dm.dc);
2827 /* power on hardware */
2828 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2830 /* program HPD filter */
2834 * early enable HPD Rx IRQ, should be done before set mode as short
2835 * pulse interrupts are used for MST
2837 amdgpu_dm_irq_resume_early(adev);
2839 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2840 s3_handle_mst(ddev, false);
2843 drm_connector_list_iter_begin(ddev, &iter);
2844 drm_for_each_connector_iter(connector, &iter) {
2845 aconnector = to_amdgpu_dm_connector(connector);
2847 if (!aconnector->dc_link)
2851 * this is the case when traversing through already created
2852 * MST connectors, should be skipped
2854 if (aconnector->dc_link->type == dc_connection_mst_branch)
2857 mutex_lock(&aconnector->hpd_lock);
2858 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2859 DRM_ERROR("KMS: Failed to detect connector\n");
2861 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2862 emulated_link_detect(aconnector->dc_link);
2864 mutex_lock(&dm->dc_lock);
2865 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2866 mutex_unlock(&dm->dc_lock);
2869 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2870 aconnector->fake_enable = false;
2872 if (aconnector->dc_sink)
2873 dc_sink_release(aconnector->dc_sink);
2874 aconnector->dc_sink = NULL;
2875 amdgpu_dm_update_connector_after_detect(aconnector);
2876 mutex_unlock(&aconnector->hpd_lock);
2878 drm_connector_list_iter_end(&iter);
2880 /* Force mode set in atomic commit */
2881 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2882 new_crtc_state->active_changed = true;
2885 * atomic_check is expected to create the dc states. We need to release
2886 * them here, since they were duplicated as part of the suspend
2889 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2890 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2891 if (dm_new_crtc_state->stream) {
2892 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2893 dc_stream_release(dm_new_crtc_state->stream);
2894 dm_new_crtc_state->stream = NULL;
2898 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2899 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2900 if (dm_new_plane_state->dc_state) {
2901 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2902 dc_plane_state_release(dm_new_plane_state->dc_state);
2903 dm_new_plane_state->dc_state = NULL;
2907 drm_atomic_helper_resume(ddev, dm->cached_state);
2909 dm->cached_state = NULL;
2911 amdgpu_dm_irq_resume_late(adev);
2913 amdgpu_dm_smu_write_watermarks_table(adev);
2921 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2922 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2923 * the base driver's device list to be initialized and torn down accordingly.
2925 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2928 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2930 .early_init = dm_early_init,
2931 .late_init = dm_late_init,
2932 .sw_init = dm_sw_init,
2933 .sw_fini = dm_sw_fini,
2934 .early_fini = amdgpu_dm_early_fini,
2935 .hw_init = dm_hw_init,
2936 .hw_fini = dm_hw_fini,
2937 .suspend = dm_suspend,
2938 .resume = dm_resume,
2939 .is_idle = dm_is_idle,
2940 .wait_for_idle = dm_wait_for_idle,
2941 .check_soft_reset = dm_check_soft_reset,
2942 .soft_reset = dm_soft_reset,
2943 .set_clockgating_state = dm_set_clockgating_state,
2944 .set_powergating_state = dm_set_powergating_state,
2947 const struct amdgpu_ip_block_version dm_ip_block =
2949 .type = AMD_IP_BLOCK_TYPE_DCE,
2953 .funcs = &amdgpu_dm_funcs,
2963 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2964 .fb_create = amdgpu_display_user_framebuffer_create,
2965 .get_format_info = amdgpu_dm_plane_get_format_info,
2966 .atomic_check = amdgpu_dm_atomic_check,
2967 .atomic_commit = drm_atomic_helper_commit,
2970 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2971 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2972 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2975 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2977 struct amdgpu_dm_backlight_caps *caps;
2978 struct amdgpu_display_manager *dm;
2979 struct drm_connector *conn_base;
2980 struct amdgpu_device *adev;
2981 struct dc_link *link = NULL;
2982 struct drm_luminance_range_info *luminance_range;
2985 if (!aconnector || !aconnector->dc_link)
2988 link = aconnector->dc_link;
2989 if (link->connector_signal != SIGNAL_TYPE_EDP)
2992 conn_base = &aconnector->base;
2993 adev = drm_to_adev(conn_base->dev);
2995 for (i = 0; i < dm->num_of_edps; i++) {
2996 if (link == dm->backlight_link[i])
2999 if (i >= dm->num_of_edps)
3001 caps = &dm->backlight_caps[i];
3002 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3003 caps->aux_support = false;
3005 if (caps->ext_caps->bits.oled == 1 /*||
3006 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3007 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3008 caps->aux_support = true;
3010 if (amdgpu_backlight == 0)
3011 caps->aux_support = false;
3012 else if (amdgpu_backlight == 1)
3013 caps->aux_support = true;
3015 luminance_range = &conn_base->display_info.luminance_range;
3017 if (luminance_range->max_luminance) {
3018 caps->aux_min_input_signal = luminance_range->min_luminance;
3019 caps->aux_max_input_signal = luminance_range->max_luminance;
3021 caps->aux_min_input_signal = 0;
3022 caps->aux_max_input_signal = 512;
3026 void amdgpu_dm_update_connector_after_detect(
3027 struct amdgpu_dm_connector *aconnector)
3029 struct drm_connector *connector = &aconnector->base;
3030 struct drm_device *dev = connector->dev;
3031 struct dc_sink *sink;
3033 /* MST handled by drm_mst framework */
3034 if (aconnector->mst_mgr.mst_state == true)
3037 sink = aconnector->dc_link->local_sink;
3039 dc_sink_retain(sink);
3042 * Edid mgmt connector gets first update only in mode_valid hook and then
3043 * the connector sink is set to either fake or physical sink depends on link status.
3044 * Skip if already done during boot.
3046 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3047 && aconnector->dc_em_sink) {
3050 * For S3 resume with headless use eml_sink to fake stream
3051 * because on resume connector->sink is set to NULL
3053 mutex_lock(&dev->mode_config.mutex);
3056 if (aconnector->dc_sink) {
3057 amdgpu_dm_update_freesync_caps(connector, NULL);
3059 * retain and release below are used to
3060 * bump up refcount for sink because the link doesn't point
3061 * to it anymore after disconnect, so on next crtc to connector
3062 * reshuffle by UMD we will get into unwanted dc_sink release
3064 dc_sink_release(aconnector->dc_sink);
3066 aconnector->dc_sink = sink;
3067 dc_sink_retain(aconnector->dc_sink);
3068 amdgpu_dm_update_freesync_caps(connector,
3071 amdgpu_dm_update_freesync_caps(connector, NULL);
3072 if (!aconnector->dc_sink) {
3073 aconnector->dc_sink = aconnector->dc_em_sink;
3074 dc_sink_retain(aconnector->dc_sink);
3078 mutex_unlock(&dev->mode_config.mutex);
3081 dc_sink_release(sink);
3086 * TODO: temporary guard to look for proper fix
3087 * if this sink is MST sink, we should not do anything
3089 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3090 dc_sink_release(sink);
3094 if (aconnector->dc_sink == sink) {
3096 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3099 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3100 aconnector->connector_id);
3102 dc_sink_release(sink);
3106 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3107 aconnector->connector_id, aconnector->dc_sink, sink);
3109 mutex_lock(&dev->mode_config.mutex);
3112 * 1. Update status of the drm connector
3113 * 2. Send an event and let userspace tell us what to do
3117 * TODO: check if we still need the S3 mode update workaround.
3118 * If yes, put it here.
3120 if (aconnector->dc_sink) {
3121 amdgpu_dm_update_freesync_caps(connector, NULL);
3122 dc_sink_release(aconnector->dc_sink);
3125 aconnector->dc_sink = sink;
3126 dc_sink_retain(aconnector->dc_sink);
3127 if (sink->dc_edid.length == 0) {
3128 aconnector->edid = NULL;
3129 if (aconnector->dc_link->aux_mode) {
3130 drm_dp_cec_unset_edid(
3131 &aconnector->dm_dp_aux.aux);
3135 (struct edid *)sink->dc_edid.raw_edid;
3137 if (aconnector->dc_link->aux_mode)
3138 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3142 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3143 if (!aconnector->timing_requested)
3144 dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3146 drm_connector_update_edid_property(connector, aconnector->edid);
3147 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3148 update_connector_ext_caps(aconnector);
3150 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3151 amdgpu_dm_update_freesync_caps(connector, NULL);
3152 drm_connector_update_edid_property(connector, NULL);
3153 aconnector->num_modes = 0;
3154 dc_sink_release(aconnector->dc_sink);
3155 aconnector->dc_sink = NULL;
3156 aconnector->edid = NULL;
3157 kfree(aconnector->timing_requested);
3158 aconnector->timing_requested = NULL;
3159 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3160 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3161 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3164 mutex_unlock(&dev->mode_config.mutex);
3166 update_subconnector_property(aconnector);
3169 dc_sink_release(sink);
3172 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3174 struct drm_connector *connector = &aconnector->base;
3175 struct drm_device *dev = connector->dev;
3176 enum dc_connection_type new_connection_type = dc_connection_none;
3177 struct amdgpu_device *adev = drm_to_adev(dev);
3178 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3181 if (adev->dm.disable_hpd_irq)
3185 * In case of failure or MST no need to update connector status or notify the OS
3186 * since (for MST case) MST does this in its own context.
3188 mutex_lock(&aconnector->hpd_lock);
3190 if (adev->dm.hdcp_workqueue) {
3191 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3192 dm_con_state->update_hdcp = true;
3194 if (aconnector->fake_enable)
3195 aconnector->fake_enable = false;
3197 aconnector->timing_changed = false;
3199 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3200 DRM_ERROR("KMS: Failed to detect connector\n");
3202 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3203 emulated_link_detect(aconnector->dc_link);
3205 drm_modeset_lock_all(dev);
3206 dm_restore_drm_connector_state(dev, connector);
3207 drm_modeset_unlock_all(dev);
3209 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3210 drm_kms_helper_connector_hotplug_event(connector);
3212 mutex_lock(&adev->dm.dc_lock);
3213 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3214 mutex_unlock(&adev->dm.dc_lock);
3216 amdgpu_dm_update_connector_after_detect(aconnector);
3218 drm_modeset_lock_all(dev);
3219 dm_restore_drm_connector_state(dev, connector);
3220 drm_modeset_unlock_all(dev);
3222 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3223 drm_kms_helper_connector_hotplug_event(connector);
3226 mutex_unlock(&aconnector->hpd_lock);
3230 static void handle_hpd_irq(void *param)
3232 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3234 handle_hpd_irq_helper(aconnector);
3238 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3240 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3242 bool new_irq_handled = false;
3244 int dpcd_bytes_to_read;
3246 const int max_process_count = 30;
3247 int process_count = 0;
3249 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3251 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3252 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3253 /* DPCD 0x200 - 0x201 for downstream IRQ */
3254 dpcd_addr = DP_SINK_COUNT;
3256 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3257 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3258 dpcd_addr = DP_SINK_COUNT_ESI;
3261 dret = drm_dp_dpcd_read(
3262 &aconnector->dm_dp_aux.aux,
3265 dpcd_bytes_to_read);
3267 while (dret == dpcd_bytes_to_read &&
3268 process_count < max_process_count) {
3274 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3275 /* handle HPD short pulse irq */
3276 if (aconnector->mst_mgr.mst_state)
3278 &aconnector->mst_mgr,
3282 if (new_irq_handled) {
3283 /* ACK at DPCD to notify down stream */
3284 const int ack_dpcd_bytes_to_write =
3285 dpcd_bytes_to_read - 1;
3287 for (retry = 0; retry < 3; retry++) {
3290 wret = drm_dp_dpcd_write(
3291 &aconnector->dm_dp_aux.aux,
3294 ack_dpcd_bytes_to_write);
3295 if (wret == ack_dpcd_bytes_to_write)
3299 /* check if there is new irq to be handled */
3300 dret = drm_dp_dpcd_read(
3301 &aconnector->dm_dp_aux.aux,
3304 dpcd_bytes_to_read);
3306 new_irq_handled = false;
3312 if (process_count == max_process_count)
3313 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3316 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3317 union hpd_irq_data hpd_irq_data)
3319 struct hpd_rx_irq_offload_work *offload_work =
3320 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3322 if (!offload_work) {
3323 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3327 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3328 offload_work->data = hpd_irq_data;
3329 offload_work->offload_wq = offload_wq;
3331 queue_work(offload_wq->wq, &offload_work->work);
3332 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3335 static void handle_hpd_rx_irq(void *param)
3337 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3338 struct drm_connector *connector = &aconnector->base;
3339 struct drm_device *dev = connector->dev;
3340 struct dc_link *dc_link = aconnector->dc_link;
3341 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3342 bool result = false;
3343 enum dc_connection_type new_connection_type = dc_connection_none;
3344 struct amdgpu_device *adev = drm_to_adev(dev);
3345 union hpd_irq_data hpd_irq_data;
3346 bool link_loss = false;
3347 bool has_left_work = false;
3348 int idx = dc_link->link_index;
3349 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3351 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3353 if (adev->dm.disable_hpd_irq)
3357 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3358 * conflict, after implement i2c helper, this mutex should be
3361 mutex_lock(&aconnector->hpd_lock);
3363 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3364 &link_loss, true, &has_left_work);
3369 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3370 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3374 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3375 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3376 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3377 dm_handle_mst_sideband_msg(aconnector);
3384 spin_lock(&offload_wq->offload_lock);
3385 skip = offload_wq->is_handling_link_loss;
3388 offload_wq->is_handling_link_loss = true;
3390 spin_unlock(&offload_wq->offload_lock);
3393 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3400 if (result && !is_mst_root_connector) {
3401 /* Downstream Port status changed. */
3402 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3403 DRM_ERROR("KMS: Failed to detect connector\n");
3405 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3406 emulated_link_detect(dc_link);
3408 if (aconnector->fake_enable)
3409 aconnector->fake_enable = false;
3411 amdgpu_dm_update_connector_after_detect(aconnector);
3414 drm_modeset_lock_all(dev);
3415 dm_restore_drm_connector_state(dev, connector);
3416 drm_modeset_unlock_all(dev);
3418 drm_kms_helper_connector_hotplug_event(connector);
3422 mutex_lock(&adev->dm.dc_lock);
3423 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3424 mutex_unlock(&adev->dm.dc_lock);
3427 if (aconnector->fake_enable)
3428 aconnector->fake_enable = false;
3430 amdgpu_dm_update_connector_after_detect(aconnector);
3432 drm_modeset_lock_all(dev);
3433 dm_restore_drm_connector_state(dev, connector);
3434 drm_modeset_unlock_all(dev);
3436 drm_kms_helper_connector_hotplug_event(connector);
3440 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3441 if (adev->dm.hdcp_workqueue)
3442 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3445 if (dc_link->type != dc_connection_mst_branch)
3446 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3448 mutex_unlock(&aconnector->hpd_lock);
3451 static void register_hpd_handlers(struct amdgpu_device *adev)
3453 struct drm_device *dev = adev_to_drm(adev);
3454 struct drm_connector *connector;
3455 struct amdgpu_dm_connector *aconnector;
3456 const struct dc_link *dc_link;
3457 struct dc_interrupt_params int_params = {0};
3459 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3460 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3462 list_for_each_entry(connector,
3463 &dev->mode_config.connector_list, head) {
3465 aconnector = to_amdgpu_dm_connector(connector);
3466 dc_link = aconnector->dc_link;
3468 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3469 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3470 int_params.irq_source = dc_link->irq_source_hpd;
3472 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3474 (void *) aconnector);
3477 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3479 /* Also register for DP short pulse (hpd_rx). */
3480 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3481 int_params.irq_source = dc_link->irq_source_hpd_rx;
3483 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3485 (void *) aconnector);
3487 if (adev->dm.hpd_rx_offload_wq)
3488 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3494 #if defined(CONFIG_DRM_AMD_DC_SI)
3495 /* Register IRQ sources and initialize IRQ callbacks */
3496 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3498 struct dc *dc = adev->dm.dc;
3499 struct common_irq_params *c_irq_params;
3500 struct dc_interrupt_params int_params = {0};
3503 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3505 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3506 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3509 * Actions of amdgpu_irq_add_id():
3510 * 1. Register a set() function with base driver.
3511 * Base driver will call set() function to enable/disable an
3512 * interrupt in DC hardware.
3513 * 2. Register amdgpu_dm_irq_handler().
3514 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3515 * coming from DC hardware.
3516 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3517 * for acknowledging and handling. */
3519 /* Use VBLANK interrupt */
3520 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3521 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3523 DRM_ERROR("Failed to add crtc irq id!\n");
3527 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3528 int_params.irq_source =
3529 dc_interrupt_to_irq_source(dc, i+1 , 0);
3531 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3533 c_irq_params->adev = adev;
3534 c_irq_params->irq_src = int_params.irq_source;
3536 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3537 dm_crtc_high_irq, c_irq_params);
3540 /* Use GRPH_PFLIP interrupt */
3541 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3542 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3543 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3545 DRM_ERROR("Failed to add page flip irq id!\n");
3549 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3550 int_params.irq_source =
3551 dc_interrupt_to_irq_source(dc, i, 0);
3553 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3555 c_irq_params->adev = adev;
3556 c_irq_params->irq_src = int_params.irq_source;
3558 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3559 dm_pflip_high_irq, c_irq_params);
3564 r = amdgpu_irq_add_id(adev, client_id,
3565 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3567 DRM_ERROR("Failed to add hpd irq id!\n");
3571 register_hpd_handlers(adev);
3577 /* Register IRQ sources and initialize IRQ callbacks */
3578 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3580 struct dc *dc = adev->dm.dc;
3581 struct common_irq_params *c_irq_params;
3582 struct dc_interrupt_params int_params = {0};
3585 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3587 if (adev->family >= AMDGPU_FAMILY_AI)
3588 client_id = SOC15_IH_CLIENTID_DCE;
3590 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3591 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3594 * Actions of amdgpu_irq_add_id():
3595 * 1. Register a set() function with base driver.
3596 * Base driver will call set() function to enable/disable an
3597 * interrupt in DC hardware.
3598 * 2. Register amdgpu_dm_irq_handler().
3599 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3600 * coming from DC hardware.
3601 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3602 * for acknowledging and handling. */
3604 /* Use VBLANK interrupt */
3605 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3606 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3608 DRM_ERROR("Failed to add crtc irq id!\n");
3612 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3613 int_params.irq_source =
3614 dc_interrupt_to_irq_source(dc, i, 0);
3616 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3618 c_irq_params->adev = adev;
3619 c_irq_params->irq_src = int_params.irq_source;
3621 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3622 dm_crtc_high_irq, c_irq_params);
3625 /* Use VUPDATE interrupt */
3626 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3627 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3629 DRM_ERROR("Failed to add vupdate irq id!\n");
3633 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3634 int_params.irq_source =
3635 dc_interrupt_to_irq_source(dc, i, 0);
3637 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3639 c_irq_params->adev = adev;
3640 c_irq_params->irq_src = int_params.irq_source;
3642 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3643 dm_vupdate_high_irq, c_irq_params);
3646 /* Use GRPH_PFLIP interrupt */
3647 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3648 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3649 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3651 DRM_ERROR("Failed to add page flip irq id!\n");
3655 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3656 int_params.irq_source =
3657 dc_interrupt_to_irq_source(dc, i, 0);
3659 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3661 c_irq_params->adev = adev;
3662 c_irq_params->irq_src = int_params.irq_source;
3664 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3665 dm_pflip_high_irq, c_irq_params);
3670 r = amdgpu_irq_add_id(adev, client_id,
3671 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3673 DRM_ERROR("Failed to add hpd irq id!\n");
3677 register_hpd_handlers(adev);
3682 /* Register IRQ sources and initialize IRQ callbacks */
3683 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3685 struct dc *dc = adev->dm.dc;
3686 struct common_irq_params *c_irq_params;
3687 struct dc_interrupt_params int_params = {0};
3690 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3691 static const unsigned int vrtl_int_srcid[] = {
3692 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3693 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3694 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3695 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3696 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3697 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3701 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3702 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3705 * Actions of amdgpu_irq_add_id():
3706 * 1. Register a set() function with base driver.
3707 * Base driver will call set() function to enable/disable an
3708 * interrupt in DC hardware.
3709 * 2. Register amdgpu_dm_irq_handler().
3710 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3711 * coming from DC hardware.
3712 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3713 * for acknowledging and handling.
3716 /* Use VSTARTUP interrupt */
3717 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3718 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3720 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3723 DRM_ERROR("Failed to add crtc irq id!\n");
3727 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3728 int_params.irq_source =
3729 dc_interrupt_to_irq_source(dc, i, 0);
3731 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3733 c_irq_params->adev = adev;
3734 c_irq_params->irq_src = int_params.irq_source;
3736 amdgpu_dm_irq_register_interrupt(
3737 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3740 /* Use otg vertical line interrupt */
3741 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3742 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3743 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3744 vrtl_int_srcid[i], &adev->vline0_irq);
3747 DRM_ERROR("Failed to add vline0 irq id!\n");
3751 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3752 int_params.irq_source =
3753 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3755 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3756 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3760 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3761 - DC_IRQ_SOURCE_DC1_VLINE0];
3763 c_irq_params->adev = adev;
3764 c_irq_params->irq_src = int_params.irq_source;
3766 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3767 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3771 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3772 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3773 * to trigger at end of each vblank, regardless of state of the lock,
3774 * matching DCE behaviour.
3776 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3777 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3779 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3782 DRM_ERROR("Failed to add vupdate irq id!\n");
3786 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3787 int_params.irq_source =
3788 dc_interrupt_to_irq_source(dc, i, 0);
3790 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3792 c_irq_params->adev = adev;
3793 c_irq_params->irq_src = int_params.irq_source;
3795 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3796 dm_vupdate_high_irq, c_irq_params);
3799 /* Use GRPH_PFLIP interrupt */
3800 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3801 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3803 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3805 DRM_ERROR("Failed to add page flip irq id!\n");
3809 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3810 int_params.irq_source =
3811 dc_interrupt_to_irq_source(dc, i, 0);
3813 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3815 c_irq_params->adev = adev;
3816 c_irq_params->irq_src = int_params.irq_source;
3818 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3819 dm_pflip_high_irq, c_irq_params);
3824 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3827 DRM_ERROR("Failed to add hpd irq id!\n");
3831 register_hpd_handlers(adev);
3835 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3836 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3838 struct dc *dc = adev->dm.dc;
3839 struct common_irq_params *c_irq_params;
3840 struct dc_interrupt_params int_params = {0};
3843 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3844 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3846 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3847 &adev->dmub_outbox_irq);
3849 DRM_ERROR("Failed to add outbox irq id!\n");
3853 if (dc->ctx->dmub_srv) {
3854 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3855 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3856 int_params.irq_source =
3857 dc_interrupt_to_irq_source(dc, i, 0);
3859 c_irq_params = &adev->dm.dmub_outbox_params[0];
3861 c_irq_params->adev = adev;
3862 c_irq_params->irq_src = int_params.irq_source;
3864 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3865 dm_dmub_outbox1_low_irq, c_irq_params);
3872 * Acquires the lock for the atomic state object and returns
3873 * the new atomic state.
3875 * This should only be called during atomic check.
3877 int dm_atomic_get_state(struct drm_atomic_state *state,
3878 struct dm_atomic_state **dm_state)
3880 struct drm_device *dev = state->dev;
3881 struct amdgpu_device *adev = drm_to_adev(dev);
3882 struct amdgpu_display_manager *dm = &adev->dm;
3883 struct drm_private_state *priv_state;
3888 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3889 if (IS_ERR(priv_state))
3890 return PTR_ERR(priv_state);
3892 *dm_state = to_dm_atomic_state(priv_state);
3897 static struct dm_atomic_state *
3898 dm_atomic_get_new_state(struct drm_atomic_state *state)
3900 struct drm_device *dev = state->dev;
3901 struct amdgpu_device *adev = drm_to_adev(dev);
3902 struct amdgpu_display_manager *dm = &adev->dm;
3903 struct drm_private_obj *obj;
3904 struct drm_private_state *new_obj_state;
3907 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3908 if (obj->funcs == dm->atomic_obj.funcs)
3909 return to_dm_atomic_state(new_obj_state);
3915 static struct drm_private_state *
3916 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3918 struct dm_atomic_state *old_state, *new_state;
3920 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3924 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3926 old_state = to_dm_atomic_state(obj->state);
3928 if (old_state && old_state->context)
3929 new_state->context = dc_copy_state(old_state->context);
3931 if (!new_state->context) {
3936 return &new_state->base;
3939 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3940 struct drm_private_state *state)
3942 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3944 if (dm_state && dm_state->context)
3945 dc_release_state(dm_state->context);
3950 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3951 .atomic_duplicate_state = dm_atomic_duplicate_state,
3952 .atomic_destroy_state = dm_atomic_destroy_state,
3955 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3957 struct dm_atomic_state *state;
3960 adev->mode_info.mode_config_initialized = true;
3962 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3963 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3965 adev_to_drm(adev)->mode_config.max_width = 16384;
3966 adev_to_drm(adev)->mode_config.max_height = 16384;
3968 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3969 if (adev->asic_type == CHIP_HAWAII)
3970 /* disable prefer shadow for now due to hibernation issues */
3971 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3973 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3974 /* indicates support for immediate flip */
3975 adev_to_drm(adev)->mode_config.async_page_flip = true;
3977 state = kzalloc(sizeof(*state), GFP_KERNEL);
3981 state->context = dc_create_state(adev->dm.dc);
3982 if (!state->context) {
3987 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3989 drm_atomic_private_obj_init(adev_to_drm(adev),
3990 &adev->dm.atomic_obj,
3992 &dm_atomic_state_funcs);
3994 r = amdgpu_display_modeset_create_props(adev);
3996 dc_release_state(state->context);
4001 r = amdgpu_dm_audio_init(adev);
4003 dc_release_state(state->context);
4011 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4012 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4013 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4015 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4018 #if defined(CONFIG_ACPI)
4019 struct amdgpu_dm_backlight_caps caps;
4021 memset(&caps, 0, sizeof(caps));
4023 if (dm->backlight_caps[bl_idx].caps_valid)
4026 amdgpu_acpi_get_backlight_caps(&caps);
4027 if (caps.caps_valid) {
4028 dm->backlight_caps[bl_idx].caps_valid = true;
4029 if (caps.aux_support)
4031 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4032 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4034 dm->backlight_caps[bl_idx].min_input_signal =
4035 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4036 dm->backlight_caps[bl_idx].max_input_signal =
4037 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4040 if (dm->backlight_caps[bl_idx].aux_support)
4043 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4044 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4048 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4049 unsigned *min, unsigned *max)
4054 if (caps->aux_support) {
4055 // Firmware limits are in nits, DC API wants millinits.
4056 *max = 1000 * caps->aux_max_input_signal;
4057 *min = 1000 * caps->aux_min_input_signal;
4059 // Firmware limits are 8-bit, PWM control is 16-bit.
4060 *max = 0x101 * caps->max_input_signal;
4061 *min = 0x101 * caps->min_input_signal;
4066 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4067 uint32_t brightness)
4071 if (!get_brightness_range(caps, &min, &max))
4074 // Rescale 0..255 to min..max
4075 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4076 AMDGPU_MAX_BL_LEVEL);
4079 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4080 uint32_t brightness)
4084 if (!get_brightness_range(caps, &min, &max))
4087 if (brightness < min)
4089 // Rescale min..max to 0..255
4090 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4094 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4096 u32 user_brightness)
4098 struct amdgpu_dm_backlight_caps caps;
4099 struct dc_link *link;
4103 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4104 caps = dm->backlight_caps[bl_idx];
4106 dm->brightness[bl_idx] = user_brightness;
4107 /* update scratch register */
4109 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4110 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4111 link = (struct dc_link *)dm->backlight_link[bl_idx];
4113 /* Change brightness based on AUX property */
4114 if (caps.aux_support) {
4115 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4116 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4118 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4120 rc = dc_link_set_backlight_level(link, brightness, 0);
4122 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4126 dm->actual_brightness[bl_idx] = user_brightness;
4129 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4131 struct amdgpu_display_manager *dm = bl_get_data(bd);
4134 for (i = 0; i < dm->num_of_edps; i++) {
4135 if (bd == dm->backlight_dev[i])
4138 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4140 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4145 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4148 struct amdgpu_dm_backlight_caps caps;
4149 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4151 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4152 caps = dm->backlight_caps[bl_idx];
4154 if (caps.aux_support) {
4158 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4160 return dm->brightness[bl_idx];
4161 return convert_brightness_to_user(&caps, avg);
4163 int ret = dc_link_get_backlight_level(link);
4165 if (ret == DC_ERROR_UNEXPECTED)
4166 return dm->brightness[bl_idx];
4167 return convert_brightness_to_user(&caps, ret);
4171 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4173 struct amdgpu_display_manager *dm = bl_get_data(bd);
4176 for (i = 0; i < dm->num_of_edps; i++) {
4177 if (bd == dm->backlight_dev[i])
4180 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4182 return amdgpu_dm_backlight_get_level(dm, i);
4185 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4186 .options = BL_CORE_SUSPENDRESUME,
4187 .get_brightness = amdgpu_dm_backlight_get_brightness,
4188 .update_status = amdgpu_dm_backlight_update_status,
4192 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4195 struct backlight_properties props = { 0 };
4197 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4198 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4200 if (!acpi_video_backlight_use_native()) {
4201 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4202 /* Try registering an ACPI video backlight device instead. */
4203 acpi_video_register_backlight();
4207 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4208 props.brightness = AMDGPU_MAX_BL_LEVEL;
4209 props.type = BACKLIGHT_RAW;
4211 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4212 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4214 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4215 adev_to_drm(dm->adev)->dev,
4217 &amdgpu_dm_backlight_ops,
4220 if (IS_ERR(dm->backlight_dev[dm->num_of_edps])) {
4221 DRM_ERROR("DM: Backlight registration failed!\n");
4222 dm->backlight_dev[dm->num_of_edps] = NULL;
4224 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4227 static int initialize_plane(struct amdgpu_display_manager *dm,
4228 struct amdgpu_mode_info *mode_info, int plane_id,
4229 enum drm_plane_type plane_type,
4230 const struct dc_plane_cap *plane_cap)
4232 struct drm_plane *plane;
4233 unsigned long possible_crtcs;
4236 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4238 DRM_ERROR("KMS: Failed to allocate plane\n");
4241 plane->type = plane_type;
4244 * HACK: IGT tests expect that the primary plane for a CRTC
4245 * can only have one possible CRTC. Only expose support for
4246 * any CRTC if they're not going to be used as a primary plane
4247 * for a CRTC - like overlay or underlay planes.
4249 possible_crtcs = 1 << plane_id;
4250 if (plane_id >= dm->dc->caps.max_streams)
4251 possible_crtcs = 0xff;
4253 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4256 DRM_ERROR("KMS: Failed to initialize plane\n");
4262 mode_info->planes[plane_id] = plane;
4268 static void register_backlight_device(struct amdgpu_display_manager *dm,
4269 struct dc_link *link)
4271 int bl_idx = dm->num_of_edps;
4273 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4274 link->type == dc_connection_none)
4277 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4278 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4282 amdgpu_dm_register_backlight_device(dm);
4283 if (!dm->backlight_dev[bl_idx])
4286 dm->backlight_link[bl_idx] = link;
4290 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4293 * In this architecture, the association
4294 * connector -> encoder -> crtc
4295 * id not really requried. The crtc and connector will hold the
4296 * display_index as an abstraction to use with DAL component
4298 * Returns 0 on success
4300 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4302 struct amdgpu_display_manager *dm = &adev->dm;
4304 struct amdgpu_dm_connector *aconnector = NULL;
4305 struct amdgpu_encoder *aencoder = NULL;
4306 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4309 enum dc_connection_type new_connection_type = dc_connection_none;
4310 const struct dc_plane_cap *plane;
4311 bool psr_feature_enabled = false;
4312 int max_overlay = dm->dc->caps.max_slave_planes;
4314 dm->display_indexes_num = dm->dc->caps.max_streams;
4315 /* Update the actual used number of crtc */
4316 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4318 amdgpu_dm_set_irq_funcs(adev);
4320 link_cnt = dm->dc->caps.max_links;
4321 if (amdgpu_dm_mode_config_init(dm->adev)) {
4322 DRM_ERROR("DM: Failed to initialize mode config\n");
4326 /* There is one primary plane per CRTC */
4327 primary_planes = dm->dc->caps.max_streams;
4328 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4331 * Initialize primary planes, implicit planes for legacy IOCTLS.
4332 * Order is reversed to match iteration order in atomic check.
4334 for (i = (primary_planes - 1); i >= 0; i--) {
4335 plane = &dm->dc->caps.planes[i];
4337 if (initialize_plane(dm, mode_info, i,
4338 DRM_PLANE_TYPE_PRIMARY, plane)) {
4339 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4345 * Initialize overlay planes, index starting after primary planes.
4346 * These planes have a higher DRM index than the primary planes since
4347 * they should be considered as having a higher z-order.
4348 * Order is reversed to match iteration order in atomic check.
4350 * Only support DCN for now, and only expose one so we don't encourage
4351 * userspace to use up all the pipes.
4353 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4354 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4356 /* Do not create overlay if MPO disabled */
4357 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4360 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4363 if (!plane->pixel_format_support.argb8888)
4366 if (max_overlay-- == 0)
4369 if (initialize_plane(dm, NULL, primary_planes + i,
4370 DRM_PLANE_TYPE_OVERLAY, plane)) {
4371 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4376 for (i = 0; i < dm->dc->caps.max_streams; i++)
4377 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4378 DRM_ERROR("KMS: Failed to initialize crtc\n");
4382 /* Use Outbox interrupt */
4383 switch (adev->ip_versions[DCE_HWIP][0]) {
4384 case IP_VERSION(3, 0, 0):
4385 case IP_VERSION(3, 1, 2):
4386 case IP_VERSION(3, 1, 3):
4387 case IP_VERSION(3, 1, 4):
4388 case IP_VERSION(3, 1, 5):
4389 case IP_VERSION(3, 1, 6):
4390 case IP_VERSION(3, 2, 0):
4391 case IP_VERSION(3, 2, 1):
4392 case IP_VERSION(2, 1, 0):
4393 if (register_outbox_irq_handlers(dm->adev)) {
4394 DRM_ERROR("DM: Failed to initialize IRQ\n");
4399 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4400 adev->ip_versions[DCE_HWIP][0]);
4403 /* Determine whether to enable PSR support by default. */
4404 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4405 switch (adev->ip_versions[DCE_HWIP][0]) {
4406 case IP_VERSION(3, 1, 2):
4407 case IP_VERSION(3, 1, 3):
4408 case IP_VERSION(3, 1, 4):
4409 case IP_VERSION(3, 1, 5):
4410 case IP_VERSION(3, 1, 6):
4411 case IP_VERSION(3, 2, 0):
4412 case IP_VERSION(3, 2, 1):
4413 psr_feature_enabled = true;
4416 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4421 /* loops over all connectors on the board */
4422 for (i = 0; i < link_cnt; i++) {
4423 struct dc_link *link = NULL;
4425 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4427 "KMS: Cannot support more than %d display indexes\n",
4428 AMDGPU_DM_MAX_DISPLAY_INDEX);
4432 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4436 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4440 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4441 DRM_ERROR("KMS: Failed to initialize encoder\n");
4445 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4446 DRM_ERROR("KMS: Failed to initialize connector\n");
4450 link = dc_get_link_at_index(dm->dc, i);
4452 if (!dc_link_detect_connection_type(link, &new_connection_type))
4453 DRM_ERROR("KMS: Failed to detect connector\n");
4455 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4456 emulated_link_detect(link);
4457 amdgpu_dm_update_connector_after_detect(aconnector);
4461 mutex_lock(&dm->dc_lock);
4462 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4463 mutex_unlock(&dm->dc_lock);
4466 amdgpu_dm_update_connector_after_detect(aconnector);
4467 register_backlight_device(dm, link);
4469 if (dm->num_of_edps)
4470 update_connector_ext_caps(aconnector);
4472 if (psr_feature_enabled)
4473 amdgpu_dm_set_psr_caps(link);
4475 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4476 * PSR is also supported.
4478 if (link->psr_settings.psr_feature_enabled)
4479 adev_to_drm(adev)->vblank_disable_immediate = false;
4482 amdgpu_set_panel_orientation(&aconnector->base);
4485 /* If we didn't find a panel, notify the acpi video detection */
4486 if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4487 acpi_video_report_nolcd();
4489 /* Software is initialized. Now we can register interrupt handlers. */
4490 switch (adev->asic_type) {
4491 #if defined(CONFIG_DRM_AMD_DC_SI)
4496 if (dce60_register_irq_handlers(dm->adev)) {
4497 DRM_ERROR("DM: Failed to initialize IRQ\n");
4511 case CHIP_POLARIS11:
4512 case CHIP_POLARIS10:
4513 case CHIP_POLARIS12:
4518 if (dce110_register_irq_handlers(dm->adev)) {
4519 DRM_ERROR("DM: Failed to initialize IRQ\n");
4524 switch (adev->ip_versions[DCE_HWIP][0]) {
4525 case IP_VERSION(1, 0, 0):
4526 case IP_VERSION(1, 0, 1):
4527 case IP_VERSION(2, 0, 2):
4528 case IP_VERSION(2, 0, 3):
4529 case IP_VERSION(2, 0, 0):
4530 case IP_VERSION(2, 1, 0):
4531 case IP_VERSION(3, 0, 0):
4532 case IP_VERSION(3, 0, 2):
4533 case IP_VERSION(3, 0, 3):
4534 case IP_VERSION(3, 0, 1):
4535 case IP_VERSION(3, 1, 2):
4536 case IP_VERSION(3, 1, 3):
4537 case IP_VERSION(3, 1, 4):
4538 case IP_VERSION(3, 1, 5):
4539 case IP_VERSION(3, 1, 6):
4540 case IP_VERSION(3, 2, 0):
4541 case IP_VERSION(3, 2, 1):
4542 if (dcn10_register_irq_handlers(dm->adev)) {
4543 DRM_ERROR("DM: Failed to initialize IRQ\n");
4548 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4549 adev->ip_versions[DCE_HWIP][0]);
4563 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4565 drm_atomic_private_obj_fini(&dm->atomic_obj);
4569 /******************************************************************************
4570 * amdgpu_display_funcs functions
4571 *****************************************************************************/
4574 * dm_bandwidth_update - program display watermarks
4576 * @adev: amdgpu_device pointer
4578 * Calculate and program the display watermarks and line buffer allocation.
4580 static void dm_bandwidth_update(struct amdgpu_device *adev)
4582 /* TODO: implement later */
4585 static const struct amdgpu_display_funcs dm_display_funcs = {
4586 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4587 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4588 .backlight_set_level = NULL, /* never called for DC */
4589 .backlight_get_level = NULL, /* never called for DC */
4590 .hpd_sense = NULL,/* called unconditionally */
4591 .hpd_set_polarity = NULL, /* called unconditionally */
4592 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4593 .page_flip_get_scanoutpos =
4594 dm_crtc_get_scanoutpos,/* called unconditionally */
4595 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4596 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4599 #if defined(CONFIG_DEBUG_KERNEL_DC)
4601 static ssize_t s3_debug_store(struct device *device,
4602 struct device_attribute *attr,
4608 struct drm_device *drm_dev = dev_get_drvdata(device);
4609 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4611 ret = kstrtoint(buf, 0, &s3_state);
4616 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4621 return ret == 0 ? count : 0;
4624 DEVICE_ATTR_WO(s3_debug);
4628 static int dm_init_microcode(struct amdgpu_device *adev)
4633 switch (adev->ip_versions[DCE_HWIP][0]) {
4634 case IP_VERSION(2, 1, 0):
4635 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4636 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4637 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4639 case IP_VERSION(3, 0, 0):
4640 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4641 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4643 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4645 case IP_VERSION(3, 0, 1):
4646 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4648 case IP_VERSION(3, 0, 2):
4649 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4651 case IP_VERSION(3, 0, 3):
4652 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4654 case IP_VERSION(3, 1, 2):
4655 case IP_VERSION(3, 1, 3):
4656 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4658 case IP_VERSION(3, 1, 4):
4659 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4661 case IP_VERSION(3, 1, 5):
4662 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4664 case IP_VERSION(3, 1, 6):
4665 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4667 case IP_VERSION(3, 2, 0):
4668 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4670 case IP_VERSION(3, 2, 1):
4671 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4674 /* ASIC doesn't support DMUB. */
4677 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4679 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4683 static int dm_early_init(void *handle)
4685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4686 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4687 struct atom_context *ctx = mode_info->atom_context;
4688 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4691 /* if there is no object header, skip DM */
4692 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4693 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4694 dev_info(adev->dev, "No object header, skipping DM\n");
4698 switch (adev->asic_type) {
4699 #if defined(CONFIG_DRM_AMD_DC_SI)
4703 adev->mode_info.num_crtc = 6;
4704 adev->mode_info.num_hpd = 6;
4705 adev->mode_info.num_dig = 6;
4708 adev->mode_info.num_crtc = 2;
4709 adev->mode_info.num_hpd = 2;
4710 adev->mode_info.num_dig = 2;
4715 adev->mode_info.num_crtc = 6;
4716 adev->mode_info.num_hpd = 6;
4717 adev->mode_info.num_dig = 6;
4720 adev->mode_info.num_crtc = 4;
4721 adev->mode_info.num_hpd = 6;
4722 adev->mode_info.num_dig = 7;
4726 adev->mode_info.num_crtc = 2;
4727 adev->mode_info.num_hpd = 6;
4728 adev->mode_info.num_dig = 6;
4732 adev->mode_info.num_crtc = 6;
4733 adev->mode_info.num_hpd = 6;
4734 adev->mode_info.num_dig = 7;
4737 adev->mode_info.num_crtc = 3;
4738 adev->mode_info.num_hpd = 6;
4739 adev->mode_info.num_dig = 9;
4742 adev->mode_info.num_crtc = 2;
4743 adev->mode_info.num_hpd = 6;
4744 adev->mode_info.num_dig = 9;
4746 case CHIP_POLARIS11:
4747 case CHIP_POLARIS12:
4748 adev->mode_info.num_crtc = 5;
4749 adev->mode_info.num_hpd = 5;
4750 adev->mode_info.num_dig = 5;
4752 case CHIP_POLARIS10:
4754 adev->mode_info.num_crtc = 6;
4755 adev->mode_info.num_hpd = 6;
4756 adev->mode_info.num_dig = 6;
4761 adev->mode_info.num_crtc = 6;
4762 adev->mode_info.num_hpd = 6;
4763 adev->mode_info.num_dig = 6;
4767 switch (adev->ip_versions[DCE_HWIP][0]) {
4768 case IP_VERSION(2, 0, 2):
4769 case IP_VERSION(3, 0, 0):
4770 adev->mode_info.num_crtc = 6;
4771 adev->mode_info.num_hpd = 6;
4772 adev->mode_info.num_dig = 6;
4774 case IP_VERSION(2, 0, 0):
4775 case IP_VERSION(3, 0, 2):
4776 adev->mode_info.num_crtc = 5;
4777 adev->mode_info.num_hpd = 5;
4778 adev->mode_info.num_dig = 5;
4780 case IP_VERSION(2, 0, 3):
4781 case IP_VERSION(3, 0, 3):
4782 adev->mode_info.num_crtc = 2;
4783 adev->mode_info.num_hpd = 2;
4784 adev->mode_info.num_dig = 2;
4786 case IP_VERSION(1, 0, 0):
4787 case IP_VERSION(1, 0, 1):
4788 case IP_VERSION(3, 0, 1):
4789 case IP_VERSION(2, 1, 0):
4790 case IP_VERSION(3, 1, 2):
4791 case IP_VERSION(3, 1, 3):
4792 case IP_VERSION(3, 1, 4):
4793 case IP_VERSION(3, 1, 5):
4794 case IP_VERSION(3, 1, 6):
4795 case IP_VERSION(3, 2, 0):
4796 case IP_VERSION(3, 2, 1):
4797 adev->mode_info.num_crtc = 4;
4798 adev->mode_info.num_hpd = 4;
4799 adev->mode_info.num_dig = 4;
4802 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4803 adev->ip_versions[DCE_HWIP][0]);
4809 if (adev->mode_info.funcs == NULL)
4810 adev->mode_info.funcs = &dm_display_funcs;
4813 * Note: Do NOT change adev->audio_endpt_rreg and
4814 * adev->audio_endpt_wreg because they are initialised in
4815 * amdgpu_device_init()
4817 #if defined(CONFIG_DEBUG_KERNEL_DC)
4819 adev_to_drm(adev)->dev,
4820 &dev_attr_s3_debug);
4822 adev->dc_enabled = true;
4824 return dm_init_microcode(adev);
4827 static bool modereset_required(struct drm_crtc_state *crtc_state)
4829 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4832 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4834 drm_encoder_cleanup(encoder);
4838 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4839 .destroy = amdgpu_dm_encoder_destroy,
4843 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4844 const enum surface_pixel_format format,
4845 enum dc_color_space *color_space)
4849 *color_space = COLOR_SPACE_SRGB;
4851 /* DRM color properties only affect non-RGB formats. */
4852 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4855 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4857 switch (plane_state->color_encoding) {
4858 case DRM_COLOR_YCBCR_BT601:
4860 *color_space = COLOR_SPACE_YCBCR601;
4862 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4865 case DRM_COLOR_YCBCR_BT709:
4867 *color_space = COLOR_SPACE_YCBCR709;
4869 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4872 case DRM_COLOR_YCBCR_BT2020:
4874 *color_space = COLOR_SPACE_2020_YCBCR;
4887 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4888 const struct drm_plane_state *plane_state,
4889 const u64 tiling_flags,
4890 struct dc_plane_info *plane_info,
4891 struct dc_plane_address *address,
4893 bool force_disable_dcc)
4895 const struct drm_framebuffer *fb = plane_state->fb;
4896 const struct amdgpu_framebuffer *afb =
4897 to_amdgpu_framebuffer(plane_state->fb);
4900 memset(plane_info, 0, sizeof(*plane_info));
4902 switch (fb->format->format) {
4904 plane_info->format =
4905 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4907 case DRM_FORMAT_RGB565:
4908 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4910 case DRM_FORMAT_XRGB8888:
4911 case DRM_FORMAT_ARGB8888:
4912 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4914 case DRM_FORMAT_XRGB2101010:
4915 case DRM_FORMAT_ARGB2101010:
4916 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4918 case DRM_FORMAT_XBGR2101010:
4919 case DRM_FORMAT_ABGR2101010:
4920 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4922 case DRM_FORMAT_XBGR8888:
4923 case DRM_FORMAT_ABGR8888:
4924 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4926 case DRM_FORMAT_NV21:
4927 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4929 case DRM_FORMAT_NV12:
4930 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4932 case DRM_FORMAT_P010:
4933 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4935 case DRM_FORMAT_XRGB16161616F:
4936 case DRM_FORMAT_ARGB16161616F:
4937 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4939 case DRM_FORMAT_XBGR16161616F:
4940 case DRM_FORMAT_ABGR16161616F:
4941 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4943 case DRM_FORMAT_XRGB16161616:
4944 case DRM_FORMAT_ARGB16161616:
4945 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4947 case DRM_FORMAT_XBGR16161616:
4948 case DRM_FORMAT_ABGR16161616:
4949 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4953 "Unsupported screen format %p4cc\n",
4954 &fb->format->format);
4958 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4959 case DRM_MODE_ROTATE_0:
4960 plane_info->rotation = ROTATION_ANGLE_0;
4962 case DRM_MODE_ROTATE_90:
4963 plane_info->rotation = ROTATION_ANGLE_90;
4965 case DRM_MODE_ROTATE_180:
4966 plane_info->rotation = ROTATION_ANGLE_180;
4968 case DRM_MODE_ROTATE_270:
4969 plane_info->rotation = ROTATION_ANGLE_270;
4972 plane_info->rotation = ROTATION_ANGLE_0;
4977 plane_info->visible = true;
4978 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4980 plane_info->layer_index = plane_state->normalized_zpos;
4982 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4983 &plane_info->color_space);
4987 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4988 plane_info->rotation, tiling_flags,
4989 &plane_info->tiling_info,
4990 &plane_info->plane_size,
4991 &plane_info->dcc, address,
4992 tmz_surface, force_disable_dcc);
4996 amdgpu_dm_plane_fill_blending_from_plane_state(
4997 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4998 &plane_info->global_alpha, &plane_info->global_alpha_value);
5003 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5004 struct dc_plane_state *dc_plane_state,
5005 struct drm_plane_state *plane_state,
5006 struct drm_crtc_state *crtc_state)
5008 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5009 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5010 struct dc_scaling_info scaling_info;
5011 struct dc_plane_info plane_info;
5013 bool force_disable_dcc = false;
5015 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5019 dc_plane_state->src_rect = scaling_info.src_rect;
5020 dc_plane_state->dst_rect = scaling_info.dst_rect;
5021 dc_plane_state->clip_rect = scaling_info.clip_rect;
5022 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5024 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5025 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5028 &dc_plane_state->address,
5034 dc_plane_state->format = plane_info.format;
5035 dc_plane_state->color_space = plane_info.color_space;
5036 dc_plane_state->format = plane_info.format;
5037 dc_plane_state->plane_size = plane_info.plane_size;
5038 dc_plane_state->rotation = plane_info.rotation;
5039 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5040 dc_plane_state->stereo_format = plane_info.stereo_format;
5041 dc_plane_state->tiling_info = plane_info.tiling_info;
5042 dc_plane_state->visible = plane_info.visible;
5043 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5044 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5045 dc_plane_state->global_alpha = plane_info.global_alpha;
5046 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5047 dc_plane_state->dcc = plane_info.dcc;
5048 dc_plane_state->layer_index = plane_info.layer_index;
5049 dc_plane_state->flip_int_enabled = true;
5052 * Always set input transfer function, since plane state is refreshed
5055 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5062 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5063 struct rect *dirty_rect, int32_t x,
5064 s32 y, s32 width, s32 height,
5067 if (*i > DC_MAX_DIRTY_RECTS)
5070 if (*i == DC_MAX_DIRTY_RECTS)
5075 dirty_rect->width = width;
5076 dirty_rect->height = height;
5080 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5081 plane->base.id, width, height);
5084 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5085 plane->base.id, x, y, width, height);
5092 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5094 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5096 * @old_plane_state: Old state of @plane
5097 * @new_plane_state: New state of @plane
5098 * @crtc_state: New state of CRTC connected to the @plane
5099 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5100 * @dirty_regions_changed: dirty regions changed
5102 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5103 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5104 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5107 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5108 * plane with regions that require flushing to the eDP remote buffer. In
5109 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5110 * implicitly provide damage clips without any client support via the plane
5113 static void fill_dc_dirty_rects(struct drm_plane *plane,
5114 struct drm_plane_state *old_plane_state,
5115 struct drm_plane_state *new_plane_state,
5116 struct drm_crtc_state *crtc_state,
5117 struct dc_flip_addrs *flip_addrs,
5118 bool *dirty_regions_changed)
5120 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5121 struct rect *dirty_rects = flip_addrs->dirty_rects;
5123 struct drm_mode_rect *clips;
5127 *dirty_regions_changed = false;
5130 * Cursor plane has it's own dirty rect update interface. See
5131 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5133 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5136 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5137 clips = drm_plane_get_damage_clips(new_plane_state);
5139 if (!dm_crtc_state->mpo_requested) {
5140 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5143 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5144 fill_dc_dirty_rect(new_plane_state->plane,
5145 &dirty_rects[flip_addrs->dirty_rect_count],
5146 clips->x1, clips->y1,
5147 clips->x2 - clips->x1, clips->y2 - clips->y1,
5148 &flip_addrs->dirty_rect_count,
5154 * MPO is requested. Add entire plane bounding box to dirty rects if
5155 * flipped to or damaged.
5157 * If plane is moved or resized, also add old bounding box to dirty
5160 fb_changed = old_plane_state->fb->base.id !=
5161 new_plane_state->fb->base.id;
5162 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5163 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5164 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5165 old_plane_state->crtc_h != new_plane_state->crtc_h);
5168 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5169 new_plane_state->plane->base.id,
5170 bb_changed, fb_changed, num_clips);
5172 *dirty_regions_changed = bb_changed;
5175 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5176 new_plane_state->crtc_x,
5177 new_plane_state->crtc_y,
5178 new_plane_state->crtc_w,
5179 new_plane_state->crtc_h, &i, false);
5181 /* Add old plane bounding-box if plane is moved or resized */
5182 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5183 old_plane_state->crtc_x,
5184 old_plane_state->crtc_y,
5185 old_plane_state->crtc_w,
5186 old_plane_state->crtc_h, &i, false);
5190 for (; i < num_clips; clips++)
5191 fill_dc_dirty_rect(new_plane_state->plane,
5192 &dirty_rects[i], clips->x1,
5193 clips->y1, clips->x2 - clips->x1,
5194 clips->y2 - clips->y1, &i, false);
5195 } else if (fb_changed && !bb_changed) {
5196 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5197 new_plane_state->crtc_x,
5198 new_plane_state->crtc_y,
5199 new_plane_state->crtc_w,
5200 new_plane_state->crtc_h, &i, false);
5203 if (i > DC_MAX_DIRTY_RECTS)
5206 flip_addrs->dirty_rect_count = i;
5210 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5211 dm_crtc_state->base.mode.crtc_hdisplay,
5212 dm_crtc_state->base.mode.crtc_vdisplay,
5213 &flip_addrs->dirty_rect_count, true);
5216 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5217 const struct dm_connector_state *dm_state,
5218 struct dc_stream_state *stream)
5220 enum amdgpu_rmx_type rmx_type;
5222 struct rect src = { 0 }; /* viewport in composition space*/
5223 struct rect dst = { 0 }; /* stream addressable area */
5225 /* no mode. nothing to be done */
5229 /* Full screen scaling by default */
5230 src.width = mode->hdisplay;
5231 src.height = mode->vdisplay;
5232 dst.width = stream->timing.h_addressable;
5233 dst.height = stream->timing.v_addressable;
5236 rmx_type = dm_state->scaling;
5237 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5238 if (src.width * dst.height <
5239 src.height * dst.width) {
5240 /* height needs less upscaling/more downscaling */
5241 dst.width = src.width *
5242 dst.height / src.height;
5244 /* width needs less upscaling/more downscaling */
5245 dst.height = src.height *
5246 dst.width / src.width;
5248 } else if (rmx_type == RMX_CENTER) {
5252 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5253 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5255 if (dm_state->underscan_enable) {
5256 dst.x += dm_state->underscan_hborder / 2;
5257 dst.y += dm_state->underscan_vborder / 2;
5258 dst.width -= dm_state->underscan_hborder;
5259 dst.height -= dm_state->underscan_vborder;
5266 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5267 dst.x, dst.y, dst.width, dst.height);
5271 static enum dc_color_depth
5272 convert_color_depth_from_display_info(const struct drm_connector *connector,
5273 bool is_y420, int requested_bpc)
5280 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5281 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5283 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5285 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5288 bpc = (uint8_t)connector->display_info.bpc;
5289 /* Assume 8 bpc by default if no bpc is specified. */
5290 bpc = bpc ? bpc : 8;
5293 if (requested_bpc > 0) {
5295 * Cap display bpc based on the user requested value.
5297 * The value for state->max_bpc may not correctly updated
5298 * depending on when the connector gets added to the state
5299 * or if this was called outside of atomic check, so it
5300 * can't be used directly.
5302 bpc = min_t(u8, bpc, requested_bpc);
5304 /* Round down to the nearest even number. */
5305 bpc = bpc - (bpc & 1);
5311 * Temporary Work around, DRM doesn't parse color depth for
5312 * EDID revision before 1.4
5313 * TODO: Fix edid parsing
5315 return COLOR_DEPTH_888;
5317 return COLOR_DEPTH_666;
5319 return COLOR_DEPTH_888;
5321 return COLOR_DEPTH_101010;
5323 return COLOR_DEPTH_121212;
5325 return COLOR_DEPTH_141414;
5327 return COLOR_DEPTH_161616;
5329 return COLOR_DEPTH_UNDEFINED;
5333 static enum dc_aspect_ratio
5334 get_aspect_ratio(const struct drm_display_mode *mode_in)
5336 /* 1-1 mapping, since both enums follow the HDMI spec. */
5337 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5340 static enum dc_color_space
5341 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5343 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5345 switch (dc_crtc_timing->pixel_encoding) {
5346 case PIXEL_ENCODING_YCBCR422:
5347 case PIXEL_ENCODING_YCBCR444:
5348 case PIXEL_ENCODING_YCBCR420:
5351 * 27030khz is the separation point between HDTV and SDTV
5352 * according to HDMI spec, we use YCbCr709 and YCbCr601
5355 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5356 if (dc_crtc_timing->flags.Y_ONLY)
5358 COLOR_SPACE_YCBCR709_LIMITED;
5360 color_space = COLOR_SPACE_YCBCR709;
5362 if (dc_crtc_timing->flags.Y_ONLY)
5364 COLOR_SPACE_YCBCR601_LIMITED;
5366 color_space = COLOR_SPACE_YCBCR601;
5371 case PIXEL_ENCODING_RGB:
5372 color_space = COLOR_SPACE_SRGB;
5383 static bool adjust_colour_depth_from_display_info(
5384 struct dc_crtc_timing *timing_out,
5385 const struct drm_display_info *info)
5387 enum dc_color_depth depth = timing_out->display_color_depth;
5390 normalized_clk = timing_out->pix_clk_100hz / 10;
5391 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5392 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5393 normalized_clk /= 2;
5394 /* Adjusting pix clock following on HDMI spec based on colour depth */
5396 case COLOR_DEPTH_888:
5398 case COLOR_DEPTH_101010:
5399 normalized_clk = (normalized_clk * 30) / 24;
5401 case COLOR_DEPTH_121212:
5402 normalized_clk = (normalized_clk * 36) / 24;
5404 case COLOR_DEPTH_161616:
5405 normalized_clk = (normalized_clk * 48) / 24;
5408 /* The above depths are the only ones valid for HDMI. */
5411 if (normalized_clk <= info->max_tmds_clock) {
5412 timing_out->display_color_depth = depth;
5415 } while (--depth > COLOR_DEPTH_666);
5419 static void fill_stream_properties_from_drm_display_mode(
5420 struct dc_stream_state *stream,
5421 const struct drm_display_mode *mode_in,
5422 const struct drm_connector *connector,
5423 const struct drm_connector_state *connector_state,
5424 const struct dc_stream_state *old_stream,
5427 struct dc_crtc_timing *timing_out = &stream->timing;
5428 const struct drm_display_info *info = &connector->display_info;
5429 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5430 struct hdmi_vendor_infoframe hv_frame;
5431 struct hdmi_avi_infoframe avi_frame;
5433 memset(&hv_frame, 0, sizeof(hv_frame));
5434 memset(&avi_frame, 0, sizeof(avi_frame));
5436 timing_out->h_border_left = 0;
5437 timing_out->h_border_right = 0;
5438 timing_out->v_border_top = 0;
5439 timing_out->v_border_bottom = 0;
5440 /* TODO: un-hardcode */
5441 if (drm_mode_is_420_only(info, mode_in)
5442 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5443 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5444 else if (drm_mode_is_420_also(info, mode_in)
5445 && aconnector->force_yuv420_output)
5446 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5447 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5448 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5449 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5451 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5453 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5454 timing_out->display_color_depth = convert_color_depth_from_display_info(
5456 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5458 timing_out->scan_type = SCANNING_TYPE_NODATA;
5459 timing_out->hdmi_vic = 0;
5462 timing_out->vic = old_stream->timing.vic;
5463 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5464 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5466 timing_out->vic = drm_match_cea_mode(mode_in);
5467 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5468 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5469 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5470 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5473 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5474 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5475 timing_out->vic = avi_frame.video_code;
5476 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5477 timing_out->hdmi_vic = hv_frame.vic;
5480 if (is_freesync_video_mode(mode_in, aconnector)) {
5481 timing_out->h_addressable = mode_in->hdisplay;
5482 timing_out->h_total = mode_in->htotal;
5483 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5484 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5485 timing_out->v_total = mode_in->vtotal;
5486 timing_out->v_addressable = mode_in->vdisplay;
5487 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5488 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5489 timing_out->pix_clk_100hz = mode_in->clock * 10;
5491 timing_out->h_addressable = mode_in->crtc_hdisplay;
5492 timing_out->h_total = mode_in->crtc_htotal;
5493 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5494 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5495 timing_out->v_total = mode_in->crtc_vtotal;
5496 timing_out->v_addressable = mode_in->crtc_vdisplay;
5497 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5498 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5499 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5502 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5504 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5505 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5506 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5507 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5508 drm_mode_is_420_also(info, mode_in) &&
5509 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5510 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5511 adjust_colour_depth_from_display_info(timing_out, info);
5515 stream->output_color_space = get_output_color_space(timing_out);
5518 static void fill_audio_info(struct audio_info *audio_info,
5519 const struct drm_connector *drm_connector,
5520 const struct dc_sink *dc_sink)
5523 int cea_revision = 0;
5524 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5526 audio_info->manufacture_id = edid_caps->manufacturer_id;
5527 audio_info->product_id = edid_caps->product_id;
5529 cea_revision = drm_connector->display_info.cea_rev;
5531 strscpy(audio_info->display_name,
5532 edid_caps->display_name,
5533 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5535 if (cea_revision >= 3) {
5536 audio_info->mode_count = edid_caps->audio_mode_count;
5538 for (i = 0; i < audio_info->mode_count; ++i) {
5539 audio_info->modes[i].format_code =
5540 (enum audio_format_code)
5541 (edid_caps->audio_modes[i].format_code);
5542 audio_info->modes[i].channel_count =
5543 edid_caps->audio_modes[i].channel_count;
5544 audio_info->modes[i].sample_rates.all =
5545 edid_caps->audio_modes[i].sample_rate;
5546 audio_info->modes[i].sample_size =
5547 edid_caps->audio_modes[i].sample_size;
5551 audio_info->flags.all = edid_caps->speaker_flags;
5553 /* TODO: We only check for the progressive mode, check for interlace mode too */
5554 if (drm_connector->latency_present[0]) {
5555 audio_info->video_latency = drm_connector->video_latency[0];
5556 audio_info->audio_latency = drm_connector->audio_latency[0];
5559 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5564 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5565 struct drm_display_mode *dst_mode)
5567 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5568 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5569 dst_mode->crtc_clock = src_mode->crtc_clock;
5570 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5571 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5572 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5573 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5574 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5575 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5576 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5577 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5578 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5579 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5580 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5584 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5585 const struct drm_display_mode *native_mode,
5588 if (scale_enabled) {
5589 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5590 } else if (native_mode->clock == drm_mode->clock &&
5591 native_mode->htotal == drm_mode->htotal &&
5592 native_mode->vtotal == drm_mode->vtotal) {
5593 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5595 /* no scaling nor amdgpu inserted, no need to patch */
5599 static struct dc_sink *
5600 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5602 struct dc_sink_init_data sink_init_data = { 0 };
5603 struct dc_sink *sink = NULL;
5604 sink_init_data.link = aconnector->dc_link;
5605 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5607 sink = dc_sink_create(&sink_init_data);
5609 DRM_ERROR("Failed to create sink!\n");
5612 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5617 static void set_multisync_trigger_params(
5618 struct dc_stream_state *stream)
5620 struct dc_stream_state *master = NULL;
5622 if (stream->triggered_crtc_reset.enabled) {
5623 master = stream->triggered_crtc_reset.event_source;
5624 stream->triggered_crtc_reset.event =
5625 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5626 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5627 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5631 static void set_master_stream(struct dc_stream_state *stream_set[],
5634 int j, highest_rfr = 0, master_stream = 0;
5636 for (j = 0; j < stream_count; j++) {
5637 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5638 int refresh_rate = 0;
5640 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5641 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5642 if (refresh_rate > highest_rfr) {
5643 highest_rfr = refresh_rate;
5648 for (j = 0; j < stream_count; j++) {
5650 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5654 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5657 struct dc_stream_state *stream;
5659 if (context->stream_count < 2)
5661 for (i = 0; i < context->stream_count ; i++) {
5662 if (!context->streams[i])
5665 * TODO: add a function to read AMD VSDB bits and set
5666 * crtc_sync_master.multi_sync_enabled flag
5667 * For now it's set to false
5671 set_master_stream(context->streams, context->stream_count);
5673 for (i = 0; i < context->stream_count ; i++) {
5674 stream = context->streams[i];
5679 set_multisync_trigger_params(stream);
5684 * DOC: FreeSync Video
5686 * When a userspace application wants to play a video, the content follows a
5687 * standard format definition that usually specifies the FPS for that format.
5688 * The below list illustrates some video format and the expected FPS,
5691 * - TV/NTSC (23.976 FPS)
5694 * - TV/NTSC (29.97 FPS)
5695 * - TV/NTSC (30 FPS)
5696 * - Cinema HFR (48 FPS)
5698 * - Commonly used (60 FPS)
5699 * - Multiples of 24 (48,72,96 FPS)
5701 * The list of standards video format is not huge and can be added to the
5702 * connector modeset list beforehand. With that, userspace can leverage
5703 * FreeSync to extends the front porch in order to attain the target refresh
5704 * rate. Such a switch will happen seamlessly, without screen blanking or
5705 * reprogramming of the output in any other way. If the userspace requests a
5706 * modesetting change compatible with FreeSync modes that only differ in the
5707 * refresh rate, DC will skip the full update and avoid blink during the
5708 * transition. For example, the video player can change the modesetting from
5709 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5710 * causing any display blink. This same concept can be applied to a mode
5713 static struct drm_display_mode *
5714 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5715 bool use_probed_modes)
5717 struct drm_display_mode *m, *m_pref = NULL;
5718 u16 current_refresh, highest_refresh;
5719 struct list_head *list_head = use_probed_modes ?
5720 &aconnector->base.probed_modes :
5721 &aconnector->base.modes;
5723 if (aconnector->freesync_vid_base.clock != 0)
5724 return &aconnector->freesync_vid_base;
5726 /* Find the preferred mode */
5727 list_for_each_entry (m, list_head, head) {
5728 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5735 /* Probably an EDID with no preferred mode. Fallback to first entry */
5736 m_pref = list_first_entry_or_null(
5737 &aconnector->base.modes, struct drm_display_mode, head);
5739 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5744 highest_refresh = drm_mode_vrefresh(m_pref);
5747 * Find the mode with highest refresh rate with same resolution.
5748 * For some monitors, preferred mode is not the mode with highest
5749 * supported refresh rate.
5751 list_for_each_entry (m, list_head, head) {
5752 current_refresh = drm_mode_vrefresh(m);
5754 if (m->hdisplay == m_pref->hdisplay &&
5755 m->vdisplay == m_pref->vdisplay &&
5756 highest_refresh < current_refresh) {
5757 highest_refresh = current_refresh;
5762 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5766 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5767 struct amdgpu_dm_connector *aconnector)
5769 struct drm_display_mode *high_mode;
5772 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5773 if (!high_mode || !mode)
5776 timing_diff = high_mode->vtotal - mode->vtotal;
5778 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5779 high_mode->hdisplay != mode->hdisplay ||
5780 high_mode->vdisplay != mode->vdisplay ||
5781 high_mode->hsync_start != mode->hsync_start ||
5782 high_mode->hsync_end != mode->hsync_end ||
5783 high_mode->htotal != mode->htotal ||
5784 high_mode->hskew != mode->hskew ||
5785 high_mode->vscan != mode->vscan ||
5786 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5787 high_mode->vsync_end - mode->vsync_end != timing_diff)
5793 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5794 struct dc_sink *sink, struct dc_stream_state *stream,
5795 struct dsc_dec_dpcd_caps *dsc_caps)
5797 stream->timing.flags.DSC = 0;
5798 dsc_caps->is_dsc_supported = false;
5800 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5801 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5802 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5803 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5804 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5805 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5806 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5812 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5813 struct dc_sink *sink, struct dc_stream_state *stream,
5814 struct dsc_dec_dpcd_caps *dsc_caps,
5815 uint32_t max_dsc_target_bpp_limit_override)
5817 const struct dc_link_settings *verified_link_cap = NULL;
5818 u32 link_bw_in_kbps;
5819 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5820 struct dc *dc = sink->ctx->dc;
5821 struct dc_dsc_bw_range bw_range = {0};
5822 struct dc_dsc_config dsc_cfg = {0};
5823 struct dc_dsc_config_options dsc_options = {0};
5825 dc_dsc_get_default_config_option(dc, &dsc_options);
5826 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5828 verified_link_cap = dc_link_get_link_cap(stream->link);
5829 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5830 edp_min_bpp_x16 = 8 * 16;
5831 edp_max_bpp_x16 = 8 * 16;
5833 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5834 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5836 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5837 edp_min_bpp_x16 = edp_max_bpp_x16;
5839 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5840 dc->debug.dsc_min_slice_height_override,
5841 edp_min_bpp_x16, edp_max_bpp_x16,
5846 if (bw_range.max_kbps < link_bw_in_kbps) {
5847 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5853 stream->timing.dsc_cfg = dsc_cfg;
5854 stream->timing.flags.DSC = 1;
5855 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5861 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5867 stream->timing.dsc_cfg = dsc_cfg;
5868 stream->timing.flags.DSC = 1;
5873 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5874 struct dc_sink *sink, struct dc_stream_state *stream,
5875 struct dsc_dec_dpcd_caps *dsc_caps)
5877 struct drm_connector *drm_connector = &aconnector->base;
5878 u32 link_bandwidth_kbps;
5879 struct dc *dc = sink->ctx->dc;
5880 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5881 u32 dsc_max_supported_bw_in_kbps;
5882 u32 max_dsc_target_bpp_limit_override =
5883 drm_connector->display_info.max_dsc_bpp;
5884 struct dc_dsc_config_options dsc_options = {0};
5886 dc_dsc_get_default_config_option(dc, &dsc_options);
5887 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5889 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5890 dc_link_get_link_cap(aconnector->dc_link));
5892 /* Set DSC policy according to dsc_clock_en */
5893 dc_dsc_policy_set_enable_dsc_when_not_needed(
5894 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5896 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5897 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5898 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5900 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5902 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5903 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5904 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5907 link_bandwidth_kbps,
5909 &stream->timing.dsc_cfg)) {
5910 stream->timing.flags.DSC = 1;
5911 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5913 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5914 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5915 max_supported_bw_in_kbps = link_bandwidth_kbps;
5916 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5918 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5919 max_supported_bw_in_kbps > 0 &&
5920 dsc_max_supported_bw_in_kbps > 0)
5921 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5924 dsc_max_supported_bw_in_kbps,
5926 &stream->timing.dsc_cfg)) {
5927 stream->timing.flags.DSC = 1;
5928 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5929 __func__, drm_connector->name);
5934 /* Overwrite the stream flag if DSC is enabled through debugfs */
5935 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5936 stream->timing.flags.DSC = 1;
5938 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5939 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5941 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5942 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5944 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5945 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5948 static struct dc_stream_state *
5949 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5950 const struct drm_display_mode *drm_mode,
5951 const struct dm_connector_state *dm_state,
5952 const struct dc_stream_state *old_stream,
5955 struct drm_display_mode *preferred_mode = NULL;
5956 struct drm_connector *drm_connector;
5957 const struct drm_connector_state *con_state =
5958 dm_state ? &dm_state->base : NULL;
5959 struct dc_stream_state *stream = NULL;
5960 struct drm_display_mode mode;
5961 struct drm_display_mode saved_mode;
5962 struct drm_display_mode *freesync_mode = NULL;
5963 bool native_mode_found = false;
5964 bool recalculate_timing = false;
5965 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5967 int preferred_refresh = 0;
5968 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5969 struct dsc_dec_dpcd_caps dsc_caps;
5971 struct dc_sink *sink = NULL;
5973 drm_mode_init(&mode, drm_mode);
5974 memset(&saved_mode, 0, sizeof(saved_mode));
5976 if (aconnector == NULL) {
5977 DRM_ERROR("aconnector is NULL!\n");
5981 drm_connector = &aconnector->base;
5983 if (!aconnector->dc_sink) {
5984 sink = create_fake_sink(aconnector);
5988 sink = aconnector->dc_sink;
5989 dc_sink_retain(sink);
5992 stream = dc_create_stream_for_sink(sink);
5994 if (stream == NULL) {
5995 DRM_ERROR("Failed to create stream for sink!\n");
5999 stream->dm_stream_context = aconnector;
6001 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6002 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6004 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6005 /* Search for preferred mode */
6006 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6007 native_mode_found = true;
6011 if (!native_mode_found)
6012 preferred_mode = list_first_entry_or_null(
6013 &aconnector->base.modes,
6014 struct drm_display_mode,
6017 mode_refresh = drm_mode_vrefresh(&mode);
6019 if (preferred_mode == NULL) {
6021 * This may not be an error, the use case is when we have no
6022 * usermode calls to reset and set mode upon hotplug. In this
6023 * case, we call set mode ourselves to restore the previous mode
6024 * and the modelist may not be filled in in time.
6026 DRM_DEBUG_DRIVER("No preferred mode found\n");
6028 recalculate_timing = amdgpu_freesync_vid_mode &&
6029 is_freesync_video_mode(&mode, aconnector);
6030 if (recalculate_timing) {
6031 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6032 drm_mode_copy(&saved_mode, &mode);
6033 drm_mode_copy(&mode, freesync_mode);
6035 decide_crtc_timing_for_drm_display_mode(
6036 &mode, preferred_mode, scale);
6038 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6042 if (recalculate_timing)
6043 drm_mode_set_crtcinfo(&saved_mode, 0);
6045 drm_mode_set_crtcinfo(&mode, 0);
6048 * If scaling is enabled and refresh rate didn't change
6049 * we copy the vic and polarities of the old timings
6051 if (!scale || mode_refresh != preferred_refresh)
6052 fill_stream_properties_from_drm_display_mode(
6053 stream, &mode, &aconnector->base, con_state, NULL,
6056 fill_stream_properties_from_drm_display_mode(
6057 stream, &mode, &aconnector->base, con_state, old_stream,
6060 if (aconnector->timing_changed) {
6061 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6063 stream->timing.display_color_depth,
6064 aconnector->timing_requested->display_color_depth);
6065 stream->timing = *aconnector->timing_requested;
6068 /* SST DSC determination policy */
6069 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6070 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6071 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6073 update_stream_scaling_settings(&mode, dm_state, stream);
6076 &stream->audio_info,
6080 update_stream_signal(stream, sink);
6082 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6083 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6085 if (stream->link->psr_settings.psr_feature_enabled) {
6087 // should decide stream support vsc sdp colorimetry capability
6088 // before building vsc info packet
6090 stream->use_vsc_sdp_for_colorimetry = false;
6091 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6092 stream->use_vsc_sdp_for_colorimetry =
6093 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6095 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6096 stream->use_vsc_sdp_for_colorimetry = true;
6098 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6099 tf = TRANSFER_FUNC_GAMMA_22;
6100 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6101 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6105 dc_sink_release(sink);
6110 static enum drm_connector_status
6111 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6114 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6118 * 1. This interface is NOT called in context of HPD irq.
6119 * 2. This interface *is called* in context of user-mode ioctl. Which
6120 * makes it a bad place for *any* MST-related activity.
6123 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6124 !aconnector->fake_enable)
6125 connected = (aconnector->dc_sink != NULL);
6127 connected = (aconnector->base.force == DRM_FORCE_ON ||
6128 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6130 update_subconnector_property(aconnector);
6132 return (connected ? connector_status_connected :
6133 connector_status_disconnected);
6136 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6137 struct drm_connector_state *connector_state,
6138 struct drm_property *property,
6141 struct drm_device *dev = connector->dev;
6142 struct amdgpu_device *adev = drm_to_adev(dev);
6143 struct dm_connector_state *dm_old_state =
6144 to_dm_connector_state(connector->state);
6145 struct dm_connector_state *dm_new_state =
6146 to_dm_connector_state(connector_state);
6150 if (property == dev->mode_config.scaling_mode_property) {
6151 enum amdgpu_rmx_type rmx_type;
6154 case DRM_MODE_SCALE_CENTER:
6155 rmx_type = RMX_CENTER;
6157 case DRM_MODE_SCALE_ASPECT:
6158 rmx_type = RMX_ASPECT;
6160 case DRM_MODE_SCALE_FULLSCREEN:
6161 rmx_type = RMX_FULL;
6163 case DRM_MODE_SCALE_NONE:
6169 if (dm_old_state->scaling == rmx_type)
6172 dm_new_state->scaling = rmx_type;
6174 } else if (property == adev->mode_info.underscan_hborder_property) {
6175 dm_new_state->underscan_hborder = val;
6177 } else if (property == adev->mode_info.underscan_vborder_property) {
6178 dm_new_state->underscan_vborder = val;
6180 } else if (property == adev->mode_info.underscan_property) {
6181 dm_new_state->underscan_enable = val;
6183 } else if (property == adev->mode_info.abm_level_property) {
6184 dm_new_state->abm_level = val;
6191 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6192 const struct drm_connector_state *state,
6193 struct drm_property *property,
6196 struct drm_device *dev = connector->dev;
6197 struct amdgpu_device *adev = drm_to_adev(dev);
6198 struct dm_connector_state *dm_state =
6199 to_dm_connector_state(state);
6202 if (property == dev->mode_config.scaling_mode_property) {
6203 switch (dm_state->scaling) {
6205 *val = DRM_MODE_SCALE_CENTER;
6208 *val = DRM_MODE_SCALE_ASPECT;
6211 *val = DRM_MODE_SCALE_FULLSCREEN;
6215 *val = DRM_MODE_SCALE_NONE;
6219 } else if (property == adev->mode_info.underscan_hborder_property) {
6220 *val = dm_state->underscan_hborder;
6222 } else if (property == adev->mode_info.underscan_vborder_property) {
6223 *val = dm_state->underscan_vborder;
6225 } else if (property == adev->mode_info.underscan_property) {
6226 *val = dm_state->underscan_enable;
6228 } else if (property == adev->mode_info.abm_level_property) {
6229 *val = dm_state->abm_level;
6236 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6238 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6240 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6243 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6245 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6246 const struct dc_link *link = aconnector->dc_link;
6247 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6248 struct amdgpu_display_manager *dm = &adev->dm;
6252 * Call only if mst_mgr was initialized before since it's not done
6253 * for all connector types.
6255 if (aconnector->mst_mgr.dev)
6256 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6258 for (i = 0; i < dm->num_of_edps; i++) {
6259 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6260 backlight_device_unregister(dm->backlight_dev[i]);
6261 dm->backlight_dev[i] = NULL;
6265 if (aconnector->dc_em_sink)
6266 dc_sink_release(aconnector->dc_em_sink);
6267 aconnector->dc_em_sink = NULL;
6268 if (aconnector->dc_sink)
6269 dc_sink_release(aconnector->dc_sink);
6270 aconnector->dc_sink = NULL;
6272 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6273 drm_connector_unregister(connector);
6274 drm_connector_cleanup(connector);
6275 if (aconnector->i2c) {
6276 i2c_del_adapter(&aconnector->i2c->base);
6277 kfree(aconnector->i2c);
6279 kfree(aconnector->dm_dp_aux.aux.name);
6284 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6286 struct dm_connector_state *state =
6287 to_dm_connector_state(connector->state);
6289 if (connector->state)
6290 __drm_atomic_helper_connector_destroy_state(connector->state);
6294 state = kzalloc(sizeof(*state), GFP_KERNEL);
6297 state->scaling = RMX_OFF;
6298 state->underscan_enable = false;
6299 state->underscan_hborder = 0;
6300 state->underscan_vborder = 0;
6301 state->base.max_requested_bpc = 8;
6302 state->vcpi_slots = 0;
6305 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6306 state->abm_level = amdgpu_dm_abm_level;
6308 __drm_atomic_helper_connector_reset(connector, &state->base);
6312 struct drm_connector_state *
6313 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6315 struct dm_connector_state *state =
6316 to_dm_connector_state(connector->state);
6318 struct dm_connector_state *new_state =
6319 kmemdup(state, sizeof(*state), GFP_KERNEL);
6324 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6326 new_state->freesync_capable = state->freesync_capable;
6327 new_state->abm_level = state->abm_level;
6328 new_state->scaling = state->scaling;
6329 new_state->underscan_enable = state->underscan_enable;
6330 new_state->underscan_hborder = state->underscan_hborder;
6331 new_state->underscan_vborder = state->underscan_vborder;
6332 new_state->vcpi_slots = state->vcpi_slots;
6333 new_state->pbn = state->pbn;
6334 return &new_state->base;
6338 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6340 struct amdgpu_dm_connector *amdgpu_dm_connector =
6341 to_amdgpu_dm_connector(connector);
6344 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6345 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6346 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6347 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6352 #if defined(CONFIG_DEBUG_FS)
6353 connector_debugfs_init(amdgpu_dm_connector);
6359 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6360 .reset = amdgpu_dm_connector_funcs_reset,
6361 .detect = amdgpu_dm_connector_detect,
6362 .fill_modes = drm_helper_probe_single_connector_modes,
6363 .destroy = amdgpu_dm_connector_destroy,
6364 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6365 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6366 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6367 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6368 .late_register = amdgpu_dm_connector_late_register,
6369 .early_unregister = amdgpu_dm_connector_unregister
6372 static int get_modes(struct drm_connector *connector)
6374 return amdgpu_dm_connector_get_modes(connector);
6377 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6379 struct dc_sink_init_data init_params = {
6380 .link = aconnector->dc_link,
6381 .sink_signal = SIGNAL_TYPE_VIRTUAL
6385 if (!aconnector->base.edid_blob_ptr) {
6386 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6387 aconnector->base.name);
6389 aconnector->base.force = DRM_FORCE_OFF;
6393 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6395 aconnector->edid = edid;
6397 aconnector->dc_em_sink = dc_link_add_remote_sink(
6398 aconnector->dc_link,
6400 (edid->extensions + 1) * EDID_LENGTH,
6403 if (aconnector->base.force == DRM_FORCE_ON) {
6404 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6405 aconnector->dc_link->local_sink :
6406 aconnector->dc_em_sink;
6407 dc_sink_retain(aconnector->dc_sink);
6411 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6413 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6416 * In case of headless boot with force on for DP managed connector
6417 * Those settings have to be != 0 to get initial modeset
6419 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6420 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6421 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6424 create_eml_sink(aconnector);
6427 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6428 struct dc_stream_state *stream)
6430 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6431 struct dc_plane_state *dc_plane_state = NULL;
6432 struct dc_state *dc_state = NULL;
6437 dc_plane_state = dc_create_plane_state(dc);
6438 if (!dc_plane_state)
6441 dc_state = dc_create_state(dc);
6445 /* populate stream to plane */
6446 dc_plane_state->src_rect.height = stream->src.height;
6447 dc_plane_state->src_rect.width = stream->src.width;
6448 dc_plane_state->dst_rect.height = stream->src.height;
6449 dc_plane_state->dst_rect.width = stream->src.width;
6450 dc_plane_state->clip_rect.height = stream->src.height;
6451 dc_plane_state->clip_rect.width = stream->src.width;
6452 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6453 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6454 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6455 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6456 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6457 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6458 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6459 dc_plane_state->rotation = ROTATION_ANGLE_0;
6460 dc_plane_state->is_tiling_rotated = false;
6461 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6463 dc_result = dc_validate_stream(dc, stream);
6464 if (dc_result == DC_OK)
6465 dc_result = dc_validate_plane(dc, dc_plane_state);
6467 if (dc_result == DC_OK)
6468 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6470 if (dc_result == DC_OK && !dc_add_plane_to_context(
6475 dc_result = DC_FAIL_ATTACH_SURFACES;
6477 if (dc_result == DC_OK)
6478 dc_result = dc_validate_global_state(dc, dc_state, true);
6482 dc_release_state(dc_state);
6485 dc_plane_state_release(dc_plane_state);
6490 struct dc_stream_state *
6491 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6492 const struct drm_display_mode *drm_mode,
6493 const struct dm_connector_state *dm_state,
6494 const struct dc_stream_state *old_stream)
6496 struct drm_connector *connector = &aconnector->base;
6497 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6498 struct dc_stream_state *stream;
6499 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6500 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6501 enum dc_status dc_result = DC_OK;
6504 stream = create_stream_for_sink(aconnector, drm_mode,
6505 dm_state, old_stream,
6507 if (stream == NULL) {
6508 DRM_ERROR("Failed to create stream for sink!\n");
6512 dc_result = dc_validate_stream(adev->dm.dc, stream);
6513 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6514 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6516 if (dc_result == DC_OK)
6517 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6519 if (dc_result != DC_OK) {
6520 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6525 dc_status_to_str(dc_result));
6527 dc_stream_release(stream);
6529 requested_bpc -= 2; /* lower bpc to retry validation */
6532 } while (stream == NULL && requested_bpc >= 6);
6534 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6535 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6537 aconnector->force_yuv420_output = true;
6538 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6539 dm_state, old_stream);
6540 aconnector->force_yuv420_output = false;
6546 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6547 struct drm_display_mode *mode)
6549 int result = MODE_ERROR;
6550 struct dc_sink *dc_sink;
6551 /* TODO: Unhardcode stream count */
6552 struct dc_stream_state *stream;
6553 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6555 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6556 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6560 * Only run this the first time mode_valid is called to initilialize
6563 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6564 !aconnector->dc_em_sink)
6565 handle_edid_mgmt(aconnector);
6567 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6569 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6570 aconnector->base.force != DRM_FORCE_ON) {
6571 DRM_ERROR("dc_sink is NULL!\n");
6575 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6577 dc_stream_release(stream);
6582 /* TODO: error handling*/
6586 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6587 struct dc_info_packet *out)
6589 struct hdmi_drm_infoframe frame;
6590 unsigned char buf[30]; /* 26 + 4 */
6594 memset(out, 0, sizeof(*out));
6596 if (!state->hdr_output_metadata)
6599 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6603 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6607 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6611 /* Prepare the infopacket for DC. */
6612 switch (state->connector->connector_type) {
6613 case DRM_MODE_CONNECTOR_HDMIA:
6614 out->hb0 = 0x87; /* type */
6615 out->hb1 = 0x01; /* version */
6616 out->hb2 = 0x1A; /* length */
6617 out->sb[0] = buf[3]; /* checksum */
6621 case DRM_MODE_CONNECTOR_DisplayPort:
6622 case DRM_MODE_CONNECTOR_eDP:
6623 out->hb0 = 0x00; /* sdp id, zero */
6624 out->hb1 = 0x87; /* type */
6625 out->hb2 = 0x1D; /* payload len - 1 */
6626 out->hb3 = (0x13 << 2); /* sdp version */
6627 out->sb[0] = 0x01; /* version */
6628 out->sb[1] = 0x1A; /* length */
6636 memcpy(&out->sb[i], &buf[4], 26);
6639 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6640 sizeof(out->sb), false);
6646 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6647 struct drm_atomic_state *state)
6649 struct drm_connector_state *new_con_state =
6650 drm_atomic_get_new_connector_state(state, conn);
6651 struct drm_connector_state *old_con_state =
6652 drm_atomic_get_old_connector_state(state, conn);
6653 struct drm_crtc *crtc = new_con_state->crtc;
6654 struct drm_crtc_state *new_crtc_state;
6655 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6658 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6660 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6661 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6669 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6670 struct dc_info_packet hdr_infopacket;
6672 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6676 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6677 if (IS_ERR(new_crtc_state))
6678 return PTR_ERR(new_crtc_state);
6681 * DC considers the stream backends changed if the
6682 * static metadata changes. Forcing the modeset also
6683 * gives a simple way for userspace to switch from
6684 * 8bpc to 10bpc when setting the metadata to enter
6687 * Changing the static metadata after it's been
6688 * set is permissible, however. So only force a
6689 * modeset if we're entering or exiting HDR.
6691 new_crtc_state->mode_changed =
6692 !old_con_state->hdr_output_metadata ||
6693 !new_con_state->hdr_output_metadata;
6699 static const struct drm_connector_helper_funcs
6700 amdgpu_dm_connector_helper_funcs = {
6702 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6703 * modes will be filtered by drm_mode_validate_size(), and those modes
6704 * are missing after user start lightdm. So we need to renew modes list.
6705 * in get_modes call back, not just return the modes count
6707 .get_modes = get_modes,
6708 .mode_valid = amdgpu_dm_connector_mode_valid,
6709 .atomic_check = amdgpu_dm_connector_atomic_check,
6712 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6717 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6719 switch (display_color_depth) {
6720 case COLOR_DEPTH_666:
6722 case COLOR_DEPTH_888:
6724 case COLOR_DEPTH_101010:
6726 case COLOR_DEPTH_121212:
6728 case COLOR_DEPTH_141414:
6730 case COLOR_DEPTH_161616:
6738 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6739 struct drm_crtc_state *crtc_state,
6740 struct drm_connector_state *conn_state)
6742 struct drm_atomic_state *state = crtc_state->state;
6743 struct drm_connector *connector = conn_state->connector;
6744 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6745 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6746 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6747 struct drm_dp_mst_topology_mgr *mst_mgr;
6748 struct drm_dp_mst_port *mst_port;
6749 struct drm_dp_mst_topology_state *mst_state;
6750 enum dc_color_depth color_depth;
6752 bool is_y420 = false;
6754 if (!aconnector->mst_output_port || !aconnector->dc_sink)
6757 mst_port = aconnector->mst_output_port;
6758 mst_mgr = &aconnector->mst_root->mst_mgr;
6760 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6763 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6764 if (IS_ERR(mst_state))
6765 return PTR_ERR(mst_state);
6767 if (!mst_state->pbn_div)
6768 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6770 if (!state->duplicated) {
6771 int max_bpc = conn_state->max_requested_bpc;
6772 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6773 aconnector->force_yuv420_output;
6774 color_depth = convert_color_depth_from_display_info(connector,
6777 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6778 clock = adjusted_mode->clock;
6779 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6782 dm_new_connector_state->vcpi_slots =
6783 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6784 dm_new_connector_state->pbn);
6785 if (dm_new_connector_state->vcpi_slots < 0) {
6786 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6787 return dm_new_connector_state->vcpi_slots;
6792 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6793 .disable = dm_encoder_helper_disable,
6794 .atomic_check = dm_encoder_helper_atomic_check
6797 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6798 struct dc_state *dc_state,
6799 struct dsc_mst_fairness_vars *vars)
6801 struct dc_stream_state *stream = NULL;
6802 struct drm_connector *connector;
6803 struct drm_connector_state *new_con_state;
6804 struct amdgpu_dm_connector *aconnector;
6805 struct dm_connector_state *dm_conn_state;
6807 int vcpi, pbn_div, pbn, slot_num = 0;
6809 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6811 aconnector = to_amdgpu_dm_connector(connector);
6813 if (!aconnector->mst_output_port)
6816 if (!new_con_state || !new_con_state->crtc)
6819 dm_conn_state = to_dm_connector_state(new_con_state);
6821 for (j = 0; j < dc_state->stream_count; j++) {
6822 stream = dc_state->streams[j];
6826 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6835 pbn_div = dm_mst_get_pbn_divider(stream->link);
6836 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6837 for (j = 0; j < dc_state->stream_count; j++) {
6838 if (vars[j].aconnector == aconnector) {
6844 if (j == dc_state->stream_count)
6847 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6849 if (stream->timing.flags.DSC != 1) {
6850 dm_conn_state->pbn = pbn;
6851 dm_conn_state->vcpi_slots = slot_num;
6853 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6854 dm_conn_state->pbn, false);
6861 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6865 dm_conn_state->pbn = pbn;
6866 dm_conn_state->vcpi_slots = vcpi;
6871 static int to_drm_connector_type(enum signal_type st)
6874 case SIGNAL_TYPE_HDMI_TYPE_A:
6875 return DRM_MODE_CONNECTOR_HDMIA;
6876 case SIGNAL_TYPE_EDP:
6877 return DRM_MODE_CONNECTOR_eDP;
6878 case SIGNAL_TYPE_LVDS:
6879 return DRM_MODE_CONNECTOR_LVDS;
6880 case SIGNAL_TYPE_RGB:
6881 return DRM_MODE_CONNECTOR_VGA;
6882 case SIGNAL_TYPE_DISPLAY_PORT:
6883 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6884 return DRM_MODE_CONNECTOR_DisplayPort;
6885 case SIGNAL_TYPE_DVI_DUAL_LINK:
6886 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6887 return DRM_MODE_CONNECTOR_DVID;
6888 case SIGNAL_TYPE_VIRTUAL:
6889 return DRM_MODE_CONNECTOR_VIRTUAL;
6892 return DRM_MODE_CONNECTOR_Unknown;
6896 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6898 struct drm_encoder *encoder;
6900 /* There is only one encoder per connector */
6901 drm_connector_for_each_possible_encoder(connector, encoder)
6907 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6909 struct drm_encoder *encoder;
6910 struct amdgpu_encoder *amdgpu_encoder;
6912 encoder = amdgpu_dm_connector_to_encoder(connector);
6914 if (encoder == NULL)
6917 amdgpu_encoder = to_amdgpu_encoder(encoder);
6919 amdgpu_encoder->native_mode.clock = 0;
6921 if (!list_empty(&connector->probed_modes)) {
6922 struct drm_display_mode *preferred_mode = NULL;
6924 list_for_each_entry(preferred_mode,
6925 &connector->probed_modes,
6927 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6928 amdgpu_encoder->native_mode = *preferred_mode;
6936 static struct drm_display_mode *
6937 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6939 int hdisplay, int vdisplay)
6941 struct drm_device *dev = encoder->dev;
6942 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6943 struct drm_display_mode *mode = NULL;
6944 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6946 mode = drm_mode_duplicate(dev, native_mode);
6951 mode->hdisplay = hdisplay;
6952 mode->vdisplay = vdisplay;
6953 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6954 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6960 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6961 struct drm_connector *connector)
6963 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6964 struct drm_display_mode *mode = NULL;
6965 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6966 struct amdgpu_dm_connector *amdgpu_dm_connector =
6967 to_amdgpu_dm_connector(connector);
6971 char name[DRM_DISPLAY_MODE_LEN];
6974 } common_modes[] = {
6975 { "640x480", 640, 480},
6976 { "800x600", 800, 600},
6977 { "1024x768", 1024, 768},
6978 { "1280x720", 1280, 720},
6979 { "1280x800", 1280, 800},
6980 {"1280x1024", 1280, 1024},
6981 { "1440x900", 1440, 900},
6982 {"1680x1050", 1680, 1050},
6983 {"1600x1200", 1600, 1200},
6984 {"1920x1080", 1920, 1080},
6985 {"1920x1200", 1920, 1200}
6988 n = ARRAY_SIZE(common_modes);
6990 for (i = 0; i < n; i++) {
6991 struct drm_display_mode *curmode = NULL;
6992 bool mode_existed = false;
6994 if (common_modes[i].w > native_mode->hdisplay ||
6995 common_modes[i].h > native_mode->vdisplay ||
6996 (common_modes[i].w == native_mode->hdisplay &&
6997 common_modes[i].h == native_mode->vdisplay))
7000 list_for_each_entry(curmode, &connector->probed_modes, head) {
7001 if (common_modes[i].w == curmode->hdisplay &&
7002 common_modes[i].h == curmode->vdisplay) {
7003 mode_existed = true;
7011 mode = amdgpu_dm_create_common_mode(encoder,
7012 common_modes[i].name, common_modes[i].w,
7017 drm_mode_probed_add(connector, mode);
7018 amdgpu_dm_connector->num_modes++;
7022 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7024 struct drm_encoder *encoder;
7025 struct amdgpu_encoder *amdgpu_encoder;
7026 const struct drm_display_mode *native_mode;
7028 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7029 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7032 mutex_lock(&connector->dev->mode_config.mutex);
7033 amdgpu_dm_connector_get_modes(connector);
7034 mutex_unlock(&connector->dev->mode_config.mutex);
7036 encoder = amdgpu_dm_connector_to_encoder(connector);
7040 amdgpu_encoder = to_amdgpu_encoder(encoder);
7042 native_mode = &amdgpu_encoder->native_mode;
7043 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7046 drm_connector_set_panel_orientation_with_quirk(connector,
7047 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7048 native_mode->hdisplay,
7049 native_mode->vdisplay);
7052 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7055 struct amdgpu_dm_connector *amdgpu_dm_connector =
7056 to_amdgpu_dm_connector(connector);
7059 /* empty probed_modes */
7060 INIT_LIST_HEAD(&connector->probed_modes);
7061 amdgpu_dm_connector->num_modes =
7062 drm_add_edid_modes(connector, edid);
7064 /* sorting the probed modes before calling function
7065 * amdgpu_dm_get_native_mode() since EDID can have
7066 * more than one preferred mode. The modes that are
7067 * later in the probed mode list could be of higher
7068 * and preferred resolution. For example, 3840x2160
7069 * resolution in base EDID preferred timing and 4096x2160
7070 * preferred resolution in DID extension block later.
7072 drm_mode_sort(&connector->probed_modes);
7073 amdgpu_dm_get_native_mode(connector);
7075 /* Freesync capabilities are reset by calling
7076 * drm_add_edid_modes() and need to be
7079 amdgpu_dm_update_freesync_caps(connector, edid);
7081 amdgpu_dm_connector->num_modes = 0;
7085 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7086 struct drm_display_mode *mode)
7088 struct drm_display_mode *m;
7090 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7091 if (drm_mode_equal(m, mode))
7098 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7100 const struct drm_display_mode *m;
7101 struct drm_display_mode *new_mode;
7103 u32 new_modes_count = 0;
7105 /* Standard FPS values
7114 * 60 - Commonly used
7115 * 48,72,96,120 - Multiples of 24
7117 static const u32 common_rates[] = {
7118 23976, 24000, 25000, 29970, 30000,
7119 48000, 50000, 60000, 72000, 96000, 120000
7123 * Find mode with highest refresh rate with the same resolution
7124 * as the preferred mode. Some monitors report a preferred mode
7125 * with lower resolution than the highest refresh rate supported.
7128 m = get_highest_refresh_rate_mode(aconnector, true);
7132 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7133 u64 target_vtotal, target_vtotal_diff;
7136 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7139 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7140 common_rates[i] > aconnector->max_vfreq * 1000)
7143 num = (unsigned long long)m->clock * 1000 * 1000;
7144 den = common_rates[i] * (unsigned long long)m->htotal;
7145 target_vtotal = div_u64(num, den);
7146 target_vtotal_diff = target_vtotal - m->vtotal;
7148 /* Check for illegal modes */
7149 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7150 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7151 m->vtotal + target_vtotal_diff < m->vsync_end)
7154 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7158 new_mode->vtotal += (u16)target_vtotal_diff;
7159 new_mode->vsync_start += (u16)target_vtotal_diff;
7160 new_mode->vsync_end += (u16)target_vtotal_diff;
7161 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7162 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7164 if (!is_duplicate_mode(aconnector, new_mode)) {
7165 drm_mode_probed_add(&aconnector->base, new_mode);
7166 new_modes_count += 1;
7168 drm_mode_destroy(aconnector->base.dev, new_mode);
7171 return new_modes_count;
7174 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7177 struct amdgpu_dm_connector *amdgpu_dm_connector =
7178 to_amdgpu_dm_connector(connector);
7180 if (!(amdgpu_freesync_vid_mode && edid))
7183 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7184 amdgpu_dm_connector->num_modes +=
7185 add_fs_modes(amdgpu_dm_connector);
7188 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7190 struct amdgpu_dm_connector *amdgpu_dm_connector =
7191 to_amdgpu_dm_connector(connector);
7192 struct drm_encoder *encoder;
7193 struct edid *edid = amdgpu_dm_connector->edid;
7194 struct dc_link_settings *verified_link_cap =
7195 &amdgpu_dm_connector->dc_link->verified_link_cap;
7196 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7198 encoder = amdgpu_dm_connector_to_encoder(connector);
7200 if (!drm_edid_is_valid(edid)) {
7201 amdgpu_dm_connector->num_modes =
7202 drm_add_modes_noedid(connector, 640, 480);
7203 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7204 amdgpu_dm_connector->num_modes +=
7205 drm_add_modes_noedid(connector, 1920, 1080);
7207 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7208 amdgpu_dm_connector_add_common_modes(encoder, connector);
7209 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7211 amdgpu_dm_fbc_init(connector);
7213 return amdgpu_dm_connector->num_modes;
7216 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7217 struct amdgpu_dm_connector *aconnector,
7219 struct dc_link *link,
7222 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7225 * Some of the properties below require access to state, like bpc.
7226 * Allocate some default initial connector state with our reset helper.
7228 if (aconnector->base.funcs->reset)
7229 aconnector->base.funcs->reset(&aconnector->base);
7231 aconnector->connector_id = link_index;
7232 aconnector->dc_link = link;
7233 aconnector->base.interlace_allowed = false;
7234 aconnector->base.doublescan_allowed = false;
7235 aconnector->base.stereo_allowed = false;
7236 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7237 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7238 aconnector->audio_inst = -1;
7239 aconnector->pack_sdp_v1_3 = false;
7240 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7241 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7242 mutex_init(&aconnector->hpd_lock);
7245 * configure support HPD hot plug connector_>polled default value is 0
7246 * which means HPD hot plug not supported
7248 switch (connector_type) {
7249 case DRM_MODE_CONNECTOR_HDMIA:
7250 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7251 aconnector->base.ycbcr_420_allowed =
7252 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7254 case DRM_MODE_CONNECTOR_DisplayPort:
7255 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7256 link->link_enc = link_enc_cfg_get_link_enc(link);
7257 ASSERT(link->link_enc);
7259 aconnector->base.ycbcr_420_allowed =
7260 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7262 case DRM_MODE_CONNECTOR_DVID:
7263 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7269 drm_object_attach_property(&aconnector->base.base,
7270 dm->ddev->mode_config.scaling_mode_property,
7271 DRM_MODE_SCALE_NONE);
7273 drm_object_attach_property(&aconnector->base.base,
7274 adev->mode_info.underscan_property,
7276 drm_object_attach_property(&aconnector->base.base,
7277 adev->mode_info.underscan_hborder_property,
7279 drm_object_attach_property(&aconnector->base.base,
7280 adev->mode_info.underscan_vborder_property,
7283 if (!aconnector->mst_root)
7284 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7286 aconnector->base.state->max_bpc = 16;
7287 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7289 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7290 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7291 drm_object_attach_property(&aconnector->base.base,
7292 adev->mode_info.abm_level_property, 0);
7295 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7296 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7297 connector_type == DRM_MODE_CONNECTOR_eDP) {
7298 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7300 if (!aconnector->mst_root)
7301 drm_connector_attach_vrr_capable_property(&aconnector->base);
7303 if (adev->dm.hdcp_workqueue)
7304 drm_connector_attach_content_protection_property(&aconnector->base, true);
7308 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7309 struct i2c_msg *msgs, int num)
7311 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7312 struct ddc_service *ddc_service = i2c->ddc_service;
7313 struct i2c_command cmd;
7317 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7322 cmd.number_of_payloads = num;
7323 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7326 for (i = 0; i < num; i++) {
7327 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7328 cmd.payloads[i].address = msgs[i].addr;
7329 cmd.payloads[i].length = msgs[i].len;
7330 cmd.payloads[i].data = msgs[i].buf;
7334 ddc_service->ctx->dc,
7335 ddc_service->link->link_index,
7339 kfree(cmd.payloads);
7343 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7345 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7348 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7349 .master_xfer = amdgpu_dm_i2c_xfer,
7350 .functionality = amdgpu_dm_i2c_func,
7353 static struct amdgpu_i2c_adapter *
7354 create_i2c(struct ddc_service *ddc_service,
7358 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7359 struct amdgpu_i2c_adapter *i2c;
7361 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7364 i2c->base.owner = THIS_MODULE;
7365 i2c->base.class = I2C_CLASS_DDC;
7366 i2c->base.dev.parent = &adev->pdev->dev;
7367 i2c->base.algo = &amdgpu_dm_i2c_algo;
7368 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7369 i2c_set_adapdata(&i2c->base, i2c);
7370 i2c->ddc_service = ddc_service;
7377 * Note: this function assumes that dc_link_detect() was called for the
7378 * dc_link which will be represented by this aconnector.
7380 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7381 struct amdgpu_dm_connector *aconnector,
7383 struct amdgpu_encoder *aencoder)
7387 struct dc *dc = dm->dc;
7388 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7389 struct amdgpu_i2c_adapter *i2c;
7391 link->priv = aconnector;
7393 DRM_DEBUG_DRIVER("%s()\n", __func__);
7395 i2c = create_i2c(link->ddc, link->link_index, &res);
7397 DRM_ERROR("Failed to create i2c adapter data\n");
7401 aconnector->i2c = i2c;
7402 res = i2c_add_adapter(&i2c->base);
7405 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7409 connector_type = to_drm_connector_type(link->connector_signal);
7411 res = drm_connector_init_with_ddc(
7414 &amdgpu_dm_connector_funcs,
7419 DRM_ERROR("connector_init failed\n");
7420 aconnector->connector_id = -1;
7424 drm_connector_helper_add(
7426 &amdgpu_dm_connector_helper_funcs);
7428 amdgpu_dm_connector_init_helper(
7435 drm_connector_attach_encoder(
7436 &aconnector->base, &aencoder->base);
7438 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7439 || connector_type == DRM_MODE_CONNECTOR_eDP)
7440 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7445 aconnector->i2c = NULL;
7450 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7452 switch (adev->mode_info.num_crtc) {
7469 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7470 struct amdgpu_encoder *aencoder,
7471 uint32_t link_index)
7473 struct amdgpu_device *adev = drm_to_adev(dev);
7475 int res = drm_encoder_init(dev,
7477 &amdgpu_dm_encoder_funcs,
7478 DRM_MODE_ENCODER_TMDS,
7481 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7484 aencoder->encoder_id = link_index;
7486 aencoder->encoder_id = -1;
7488 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7493 static void manage_dm_interrupts(struct amdgpu_device *adev,
7494 struct amdgpu_crtc *acrtc,
7498 * We have no guarantee that the frontend index maps to the same
7499 * backend index - some even map to more than one.
7501 * TODO: Use a different interrupt or check DC itself for the mapping.
7504 amdgpu_display_crtc_idx_to_irq_type(
7509 drm_crtc_vblank_on(&acrtc->base);
7512 &adev->pageflip_irq,
7514 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7521 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7529 &adev->pageflip_irq,
7531 drm_crtc_vblank_off(&acrtc->base);
7535 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7536 struct amdgpu_crtc *acrtc)
7539 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7542 * This reads the current state for the IRQ and force reapplies
7543 * the setting to hardware.
7545 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7549 is_scaling_state_different(const struct dm_connector_state *dm_state,
7550 const struct dm_connector_state *old_dm_state)
7552 if (dm_state->scaling != old_dm_state->scaling)
7554 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7555 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7557 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7558 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7560 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7561 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7566 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7567 struct drm_crtc_state *old_crtc_state,
7568 struct drm_connector_state *new_conn_state,
7569 struct drm_connector_state *old_conn_state,
7570 const struct drm_connector *connector,
7571 struct hdcp_workqueue *hdcp_w)
7573 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7574 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7576 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7577 connector->index, connector->status, connector->dpms);
7578 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7579 old_conn_state->content_protection, new_conn_state->content_protection);
7582 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7583 old_crtc_state->enable,
7584 old_crtc_state->active,
7585 old_crtc_state->mode_changed,
7586 old_crtc_state->active_changed,
7587 old_crtc_state->connectors_changed);
7590 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7591 new_crtc_state->enable,
7592 new_crtc_state->active,
7593 new_crtc_state->mode_changed,
7594 new_crtc_state->active_changed,
7595 new_crtc_state->connectors_changed);
7597 /* hdcp content type change */
7598 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7599 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7600 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7601 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7605 /* CP is being re enabled, ignore this */
7606 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7607 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7608 if (new_crtc_state && new_crtc_state->mode_changed) {
7609 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7610 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7613 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7614 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7618 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7620 * Handles: UNDESIRED -> ENABLED
7622 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7623 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7624 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7626 /* Stream removed and re-enabled
7628 * Can sometimes overlap with the HPD case,
7629 * thus set update_hdcp to false to avoid
7630 * setting HDCP multiple times.
7632 * Handles: DESIRED -> DESIRED (Special case)
7634 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7635 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7636 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7637 dm_con_state->update_hdcp = false;
7638 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7643 /* Hot-plug, headless s3, dpms
7645 * Only start HDCP if the display is connected/enabled.
7646 * update_hdcp flag will be set to false until the next
7649 * Handles: DESIRED -> DESIRED (Special case)
7651 if (dm_con_state->update_hdcp &&
7652 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7653 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7654 dm_con_state->update_hdcp = false;
7655 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7660 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7661 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7662 if (new_crtc_state && new_crtc_state->mode_changed) {
7663 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7667 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7672 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7676 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7677 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7682 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7686 static void remove_stream(struct amdgpu_device *adev,
7687 struct amdgpu_crtc *acrtc,
7688 struct dc_stream_state *stream)
7690 /* this is the update mode case */
7692 acrtc->otg_inst = -1;
7693 acrtc->enabled = false;
7696 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7699 assert_spin_locked(&acrtc->base.dev->event_lock);
7700 WARN_ON(acrtc->event);
7702 acrtc->event = acrtc->base.state->event;
7704 /* Set the flip status */
7705 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7707 /* Mark this event as consumed */
7708 acrtc->base.state->event = NULL;
7710 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7714 static void update_freesync_state_on_stream(
7715 struct amdgpu_display_manager *dm,
7716 struct dm_crtc_state *new_crtc_state,
7717 struct dc_stream_state *new_stream,
7718 struct dc_plane_state *surface,
7719 u32 flip_timestamp_in_us)
7721 struct mod_vrr_params vrr_params;
7722 struct dc_info_packet vrr_infopacket = {0};
7723 struct amdgpu_device *adev = dm->adev;
7724 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7725 unsigned long flags;
7726 bool pack_sdp_v1_3 = false;
7727 struct amdgpu_dm_connector *aconn;
7728 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7734 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7735 * For now it's sufficient to just guard against these conditions.
7738 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7741 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7742 vrr_params = acrtc->dm_irq_params.vrr_params;
7745 mod_freesync_handle_preflip(
7746 dm->freesync_module,
7749 flip_timestamp_in_us,
7752 if (adev->family < AMDGPU_FAMILY_AI &&
7753 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7754 mod_freesync_handle_v_update(dm->freesync_module,
7755 new_stream, &vrr_params);
7757 /* Need to call this before the frame ends. */
7758 dc_stream_adjust_vmin_vmax(dm->dc,
7759 new_crtc_state->stream,
7760 &vrr_params.adjust);
7764 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7766 if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7767 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7769 if (aconn->vsdb_info.amd_vsdb_version == 1)
7770 packet_type = PACKET_TYPE_FS_V1;
7771 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7772 packet_type = PACKET_TYPE_FS_V2;
7773 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7774 packet_type = PACKET_TYPE_FS_V3;
7776 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7777 &new_stream->adaptive_sync_infopacket);
7780 mod_freesync_build_vrr_infopacket(
7781 dm->freesync_module,
7785 TRANSFER_FUNC_UNKNOWN,
7789 new_crtc_state->freesync_vrr_info_changed |=
7790 (memcmp(&new_crtc_state->vrr_infopacket,
7792 sizeof(vrr_infopacket)) != 0);
7794 acrtc->dm_irq_params.vrr_params = vrr_params;
7795 new_crtc_state->vrr_infopacket = vrr_infopacket;
7797 new_stream->vrr_infopacket = vrr_infopacket;
7798 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7800 if (new_crtc_state->freesync_vrr_info_changed)
7801 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7802 new_crtc_state->base.crtc->base.id,
7803 (int)new_crtc_state->base.vrr_enabled,
7804 (int)vrr_params.state);
7806 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7809 static void update_stream_irq_parameters(
7810 struct amdgpu_display_manager *dm,
7811 struct dm_crtc_state *new_crtc_state)
7813 struct dc_stream_state *new_stream = new_crtc_state->stream;
7814 struct mod_vrr_params vrr_params;
7815 struct mod_freesync_config config = new_crtc_state->freesync_config;
7816 struct amdgpu_device *adev = dm->adev;
7817 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7818 unsigned long flags;
7824 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7825 * For now it's sufficient to just guard against these conditions.
7827 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7830 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7831 vrr_params = acrtc->dm_irq_params.vrr_params;
7833 if (new_crtc_state->vrr_supported &&
7834 config.min_refresh_in_uhz &&
7835 config.max_refresh_in_uhz) {
7837 * if freesync compatible mode was set, config.state will be set
7840 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7841 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7842 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7843 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7844 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7845 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7846 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7848 config.state = new_crtc_state->base.vrr_enabled ?
7849 VRR_STATE_ACTIVE_VARIABLE :
7853 config.state = VRR_STATE_UNSUPPORTED;
7856 mod_freesync_build_vrr_params(dm->freesync_module,
7858 &config, &vrr_params);
7860 new_crtc_state->freesync_config = config;
7861 /* Copy state for access from DM IRQ handler */
7862 acrtc->dm_irq_params.freesync_config = config;
7863 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7864 acrtc->dm_irq_params.vrr_params = vrr_params;
7865 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7868 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7869 struct dm_crtc_state *new_state)
7871 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7872 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7874 if (!old_vrr_active && new_vrr_active) {
7875 /* Transition VRR inactive -> active:
7876 * While VRR is active, we must not disable vblank irq, as a
7877 * reenable after disable would compute bogus vblank/pflip
7878 * timestamps if it likely happened inside display front-porch.
7880 * We also need vupdate irq for the actual core vblank handling
7883 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7884 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7885 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7886 __func__, new_state->base.crtc->base.id);
7887 } else if (old_vrr_active && !new_vrr_active) {
7888 /* Transition VRR active -> inactive:
7889 * Allow vblank irq disable again for fixed refresh rate.
7891 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7892 drm_crtc_vblank_put(new_state->base.crtc);
7893 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7894 __func__, new_state->base.crtc->base.id);
7898 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7900 struct drm_plane *plane;
7901 struct drm_plane_state *old_plane_state;
7905 * TODO: Make this per-stream so we don't issue redundant updates for
7906 * commits with multiple streams.
7908 for_each_old_plane_in_state(state, plane, old_plane_state, i)
7909 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7910 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7913 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7914 struct dc_state *dc_state,
7915 struct drm_device *dev,
7916 struct amdgpu_display_manager *dm,
7917 struct drm_crtc *pcrtc,
7918 bool wait_for_vblank)
7921 u64 timestamp_ns = ktime_get_ns();
7922 struct drm_plane *plane;
7923 struct drm_plane_state *old_plane_state, *new_plane_state;
7924 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7925 struct drm_crtc_state *new_pcrtc_state =
7926 drm_atomic_get_new_crtc_state(state, pcrtc);
7927 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7928 struct dm_crtc_state *dm_old_crtc_state =
7929 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7930 int planes_count = 0, vpos, hpos;
7931 unsigned long flags;
7932 u32 target_vblank, last_flip_vblank;
7933 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7934 bool cursor_update = false;
7935 bool pflip_present = false;
7936 bool dirty_rects_changed = false;
7938 struct dc_surface_update surface_updates[MAX_SURFACES];
7939 struct dc_plane_info plane_infos[MAX_SURFACES];
7940 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7941 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7942 struct dc_stream_update stream_update;
7945 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7948 dm_error("Failed to allocate update bundle\n");
7953 * Disable the cursor first if we're disabling all the planes.
7954 * It'll remain on the screen after the planes are re-enabled
7957 if (acrtc_state->active_planes == 0)
7958 amdgpu_dm_commit_cursors(state);
7960 /* update planes when needed */
7961 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7962 struct drm_crtc *crtc = new_plane_state->crtc;
7963 struct drm_crtc_state *new_crtc_state;
7964 struct drm_framebuffer *fb = new_plane_state->fb;
7965 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7966 bool plane_needs_flip;
7967 struct dc_plane_state *dc_plane;
7968 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7970 /* Cursor plane is handled after stream updates */
7971 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7972 if ((fb && crtc == pcrtc) ||
7973 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7974 cursor_update = true;
7979 if (!fb || !crtc || pcrtc != crtc)
7982 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7983 if (!new_crtc_state->active)
7986 dc_plane = dm_new_plane_state->dc_state;
7988 bundle->surface_updates[planes_count].surface = dc_plane;
7989 if (new_pcrtc_state->color_mgmt_changed) {
7990 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7991 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7992 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7995 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7996 &bundle->scaling_infos[planes_count]);
7998 bundle->surface_updates[planes_count].scaling_info =
7999 &bundle->scaling_infos[planes_count];
8001 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8003 pflip_present = pflip_present || plane_needs_flip;
8005 if (!plane_needs_flip) {
8010 fill_dc_plane_info_and_addr(
8011 dm->adev, new_plane_state,
8013 &bundle->plane_infos[planes_count],
8014 &bundle->flip_addrs[planes_count].address,
8015 afb->tmz_surface, false);
8017 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8018 new_plane_state->plane->index,
8019 bundle->plane_infos[planes_count].dcc.enable);
8021 bundle->surface_updates[planes_count].plane_info =
8022 &bundle->plane_infos[planes_count];
8024 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8025 fill_dc_dirty_rects(plane, old_plane_state,
8026 new_plane_state, new_crtc_state,
8027 &bundle->flip_addrs[planes_count],
8028 &dirty_rects_changed);
8031 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8032 * and enabled it again after dirty regions are stable to avoid video glitch.
8033 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8034 * during the PSR-SU was disabled.
8036 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8037 acrtc_attach->dm_irq_params.allow_psr_entry &&
8038 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8039 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8041 dirty_rects_changed) {
8042 mutex_lock(&dm->dc_lock);
8043 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8045 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8046 amdgpu_dm_psr_disable(acrtc_state->stream);
8047 mutex_unlock(&dm->dc_lock);
8052 * Only allow immediate flips for fast updates that don't
8053 * change FB pitch, DCC state, rotation or mirroing.
8055 bundle->flip_addrs[planes_count].flip_immediate =
8056 crtc->state->async_flip &&
8057 acrtc_state->update_type == UPDATE_TYPE_FAST;
8059 timestamp_ns = ktime_get_ns();
8060 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8061 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8062 bundle->surface_updates[planes_count].surface = dc_plane;
8064 if (!bundle->surface_updates[planes_count].surface) {
8065 DRM_ERROR("No surface for CRTC: id=%d\n",
8066 acrtc_attach->crtc_id);
8070 if (plane == pcrtc->primary)
8071 update_freesync_state_on_stream(
8074 acrtc_state->stream,
8076 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8078 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8080 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8081 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8087 if (pflip_present) {
8089 /* Use old throttling in non-vrr fixed refresh rate mode
8090 * to keep flip scheduling based on target vblank counts
8091 * working in a backwards compatible way, e.g., for
8092 * clients using the GLX_OML_sync_control extension or
8093 * DRI3/Present extension with defined target_msc.
8095 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8098 /* For variable refresh rate mode only:
8099 * Get vblank of last completed flip to avoid > 1 vrr
8100 * flips per video frame by use of throttling, but allow
8101 * flip programming anywhere in the possibly large
8102 * variable vrr vblank interval for fine-grained flip
8103 * timing control and more opportunity to avoid stutter
8104 * on late submission of flips.
8106 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8107 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8108 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8111 target_vblank = last_flip_vblank + wait_for_vblank;
8114 * Wait until we're out of the vertical blank period before the one
8115 * targeted by the flip
8117 while ((acrtc_attach->enabled &&
8118 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8119 0, &vpos, &hpos, NULL,
8120 NULL, &pcrtc->hwmode)
8121 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8122 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8123 (int)(target_vblank -
8124 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8125 usleep_range(1000, 1100);
8129 * Prepare the flip event for the pageflip interrupt to handle.
8131 * This only works in the case where we've already turned on the
8132 * appropriate hardware blocks (eg. HUBP) so in the transition case
8133 * from 0 -> n planes we have to skip a hardware generated event
8134 * and rely on sending it from software.
8136 if (acrtc_attach->base.state->event &&
8137 acrtc_state->active_planes > 0) {
8138 drm_crtc_vblank_get(pcrtc);
8140 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8142 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8143 prepare_flip_isr(acrtc_attach);
8145 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8148 if (acrtc_state->stream) {
8149 if (acrtc_state->freesync_vrr_info_changed)
8150 bundle->stream_update.vrr_infopacket =
8151 &acrtc_state->stream->vrr_infopacket;
8153 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8154 acrtc_attach->base.state->event) {
8155 drm_crtc_vblank_get(pcrtc);
8157 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8159 acrtc_attach->event = acrtc_attach->base.state->event;
8160 acrtc_attach->base.state->event = NULL;
8162 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8165 /* Update the planes if changed or disable if we don't have any. */
8166 if ((planes_count || acrtc_state->active_planes == 0) &&
8167 acrtc_state->stream) {
8169 * If PSR or idle optimizations are enabled then flush out
8170 * any pending work before hardware programming.
8172 if (dm->vblank_control_workqueue)
8173 flush_workqueue(dm->vblank_control_workqueue);
8175 bundle->stream_update.stream = acrtc_state->stream;
8176 if (new_pcrtc_state->mode_changed) {
8177 bundle->stream_update.src = acrtc_state->stream->src;
8178 bundle->stream_update.dst = acrtc_state->stream->dst;
8181 if (new_pcrtc_state->color_mgmt_changed) {
8183 * TODO: This isn't fully correct since we've actually
8184 * already modified the stream in place.
8186 bundle->stream_update.gamut_remap =
8187 &acrtc_state->stream->gamut_remap_matrix;
8188 bundle->stream_update.output_csc_transform =
8189 &acrtc_state->stream->csc_color_matrix;
8190 bundle->stream_update.out_transfer_func =
8191 acrtc_state->stream->out_transfer_func;
8194 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8195 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8196 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8199 * If FreeSync state on the stream has changed then we need to
8200 * re-adjust the min/max bounds now that DC doesn't handle this
8201 * as part of commit.
8203 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8204 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8205 dc_stream_adjust_vmin_vmax(
8206 dm->dc, acrtc_state->stream,
8207 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8208 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8210 mutex_lock(&dm->dc_lock);
8211 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8212 acrtc_state->stream->link->psr_settings.psr_allow_active)
8213 amdgpu_dm_psr_disable(acrtc_state->stream);
8215 update_planes_and_stream_adapter(dm->dc,
8216 acrtc_state->update_type,
8218 acrtc_state->stream,
8219 &bundle->stream_update,
8220 bundle->surface_updates);
8223 * Enable or disable the interrupts on the backend.
8225 * Most pipes are put into power gating when unused.
8227 * When power gating is enabled on a pipe we lose the
8228 * interrupt enablement state when power gating is disabled.
8230 * So we need to update the IRQ control state in hardware
8231 * whenever the pipe turns on (since it could be previously
8232 * power gated) or off (since some pipes can't be power gated
8235 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8236 dm_update_pflip_irq_state(drm_to_adev(dev),
8239 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8240 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8241 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8242 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8244 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8245 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8246 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8247 struct amdgpu_dm_connector *aconn =
8248 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8250 if (aconn->psr_skip_count > 0)
8251 aconn->psr_skip_count--;
8253 /* Allow PSR when skip count is 0. */
8254 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8257 * If sink supports PSR SU, there is no need to rely on
8258 * a vblank event disable request to enable PSR. PSR SU
8259 * can be enabled immediately once OS demonstrates an
8260 * adequate number of fast atomic commits to notify KMD
8261 * of update events. See `vblank_control_worker()`.
8263 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8264 acrtc_attach->dm_irq_params.allow_psr_entry &&
8265 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8266 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8268 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8270 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8272 amdgpu_dm_psr_enable(acrtc_state->stream);
8274 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8277 mutex_unlock(&dm->dc_lock);
8281 * Update cursor state *after* programming all the planes.
8282 * This avoids redundant programming in the case where we're going
8283 * to be disabling a single plane - those pipes are being disabled.
8285 if (acrtc_state->active_planes)
8286 amdgpu_dm_commit_cursors(state);
8292 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8293 struct drm_atomic_state *state)
8295 struct amdgpu_device *adev = drm_to_adev(dev);
8296 struct amdgpu_dm_connector *aconnector;
8297 struct drm_connector *connector;
8298 struct drm_connector_state *old_con_state, *new_con_state;
8299 struct drm_crtc_state *new_crtc_state;
8300 struct dm_crtc_state *new_dm_crtc_state;
8301 const struct dc_stream_status *status;
8304 /* Notify device removals. */
8305 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8306 if (old_con_state->crtc != new_con_state->crtc) {
8307 /* CRTC changes require notification. */
8311 if (!new_con_state->crtc)
8314 new_crtc_state = drm_atomic_get_new_crtc_state(
8315 state, new_con_state->crtc);
8317 if (!new_crtc_state)
8320 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8324 aconnector = to_amdgpu_dm_connector(connector);
8326 mutex_lock(&adev->dm.audio_lock);
8327 inst = aconnector->audio_inst;
8328 aconnector->audio_inst = -1;
8329 mutex_unlock(&adev->dm.audio_lock);
8331 amdgpu_dm_audio_eld_notify(adev, inst);
8334 /* Notify audio device additions. */
8335 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8336 if (!new_con_state->crtc)
8339 new_crtc_state = drm_atomic_get_new_crtc_state(
8340 state, new_con_state->crtc);
8342 if (!new_crtc_state)
8345 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8348 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8349 if (!new_dm_crtc_state->stream)
8352 status = dc_stream_get_status(new_dm_crtc_state->stream);
8356 aconnector = to_amdgpu_dm_connector(connector);
8358 mutex_lock(&adev->dm.audio_lock);
8359 inst = status->audio_inst;
8360 aconnector->audio_inst = inst;
8361 mutex_unlock(&adev->dm.audio_lock);
8363 amdgpu_dm_audio_eld_notify(adev, inst);
8368 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8369 * @crtc_state: the DRM CRTC state
8370 * @stream_state: the DC stream state.
8372 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8373 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8375 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8376 struct dc_stream_state *stream_state)
8378 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8382 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8383 * @state: The atomic state to commit
8385 * This will tell DC to commit the constructed DC state from atomic_check,
8386 * programming the hardware. Any failures here implies a hardware failure, since
8387 * atomic check should have filtered anything non-kosher.
8389 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8391 struct drm_device *dev = state->dev;
8392 struct amdgpu_device *adev = drm_to_adev(dev);
8393 struct amdgpu_display_manager *dm = &adev->dm;
8394 struct dm_atomic_state *dm_state;
8395 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8397 struct drm_crtc *crtc;
8398 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8399 unsigned long flags;
8400 bool wait_for_vblank = true;
8401 struct drm_connector *connector;
8402 struct drm_connector_state *old_con_state, *new_con_state;
8403 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8404 int crtc_disable_count = 0;
8405 bool mode_set_reset_required = false;
8408 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8410 r = drm_atomic_helper_wait_for_fences(dev, state, false);
8412 DRM_ERROR("Waiting for fences timed out!");
8414 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8415 drm_dp_mst_atomic_wait_for_dependencies(state);
8417 dm_state = dm_atomic_get_new_state(state);
8418 if (dm_state && dm_state->context) {
8419 dc_state = dm_state->context;
8421 /* No state changes, retain current state. */
8422 dc_state_temp = dc_create_state(dm->dc);
8423 ASSERT(dc_state_temp);
8424 dc_state = dc_state_temp;
8425 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8428 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8429 new_crtc_state, i) {
8430 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8432 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8434 if (old_crtc_state->active &&
8435 (!new_crtc_state->active ||
8436 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8437 manage_dm_interrupts(adev, acrtc, false);
8438 dc_stream_release(dm_old_crtc_state->stream);
8442 drm_atomic_helper_calc_timestamping_constants(state);
8444 /* update changed items */
8445 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8446 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8448 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8449 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8451 drm_dbg_state(state->dev,
8452 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8453 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8454 "connectors_changed:%d\n",
8456 new_crtc_state->enable,
8457 new_crtc_state->active,
8458 new_crtc_state->planes_changed,
8459 new_crtc_state->mode_changed,
8460 new_crtc_state->active_changed,
8461 new_crtc_state->connectors_changed);
8463 /* Disable cursor if disabling crtc */
8464 if (old_crtc_state->active && !new_crtc_state->active) {
8465 struct dc_cursor_position position;
8467 memset(&position, 0, sizeof(position));
8468 mutex_lock(&dm->dc_lock);
8469 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8470 mutex_unlock(&dm->dc_lock);
8473 /* Copy all transient state flags into dc state */
8474 if (dm_new_crtc_state->stream) {
8475 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8476 dm_new_crtc_state->stream);
8479 /* handles headless hotplug case, updating new_state and
8480 * aconnector as needed
8483 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8485 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8487 if (!dm_new_crtc_state->stream) {
8489 * this could happen because of issues with
8490 * userspace notifications delivery.
8491 * In this case userspace tries to set mode on
8492 * display which is disconnected in fact.
8493 * dc_sink is NULL in this case on aconnector.
8494 * We expect reset mode will come soon.
8496 * This can also happen when unplug is done
8497 * during resume sequence ended
8499 * In this case, we want to pretend we still
8500 * have a sink to keep the pipe running so that
8501 * hw state is consistent with the sw state
8503 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8504 __func__, acrtc->base.base.id);
8508 if (dm_old_crtc_state->stream)
8509 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8511 pm_runtime_get_noresume(dev->dev);
8513 acrtc->enabled = true;
8514 acrtc->hw_mode = new_crtc_state->mode;
8515 crtc->hwmode = new_crtc_state->mode;
8516 mode_set_reset_required = true;
8517 } else if (modereset_required(new_crtc_state)) {
8518 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8519 /* i.e. reset mode */
8520 if (dm_old_crtc_state->stream)
8521 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8523 mode_set_reset_required = true;
8525 } /* for_each_crtc_in_state() */
8528 /* if there mode set or reset, disable eDP PSR */
8529 if (mode_set_reset_required) {
8530 if (dm->vblank_control_workqueue)
8531 flush_workqueue(dm->vblank_control_workqueue);
8533 amdgpu_dm_psr_disable_all(dm);
8536 dm_enable_per_frame_crtc_master_sync(dc_state);
8537 mutex_lock(&dm->dc_lock);
8538 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8540 /* Allow idle optimization when vblank count is 0 for display off */
8541 if (dm->active_vblank_irq_count == 0)
8542 dc_allow_idle_optimizations(dm->dc, true);
8543 mutex_unlock(&dm->dc_lock);
8546 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8547 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8549 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8551 if (dm_new_crtc_state->stream != NULL) {
8552 const struct dc_stream_status *status =
8553 dc_stream_get_status(dm_new_crtc_state->stream);
8556 status = dc_stream_get_status_from_state(dc_state,
8557 dm_new_crtc_state->stream);
8559 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8561 acrtc->otg_inst = status->primary_otg_inst;
8564 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8565 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8566 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8567 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8569 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8574 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8575 connector->index, connector->status, connector->dpms);
8576 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8577 old_con_state->content_protection, new_con_state->content_protection);
8579 if (aconnector->dc_sink) {
8580 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8581 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8582 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8583 aconnector->dc_sink->edid_caps.display_name);
8587 new_crtc_state = NULL;
8588 old_crtc_state = NULL;
8591 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8592 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8596 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8597 old_crtc_state->enable,
8598 old_crtc_state->active,
8599 old_crtc_state->mode_changed,
8600 old_crtc_state->active_changed,
8601 old_crtc_state->connectors_changed);
8604 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8605 new_crtc_state->enable,
8606 new_crtc_state->active,
8607 new_crtc_state->mode_changed,
8608 new_crtc_state->active_changed,
8609 new_crtc_state->connectors_changed);
8612 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8613 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8614 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8615 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8617 new_crtc_state = NULL;
8618 old_crtc_state = NULL;
8621 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8622 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8625 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8627 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8628 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8629 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8630 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8631 dm_new_con_state->update_hdcp = true;
8635 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8636 old_con_state, connector, adev->dm.hdcp_workqueue)) {
8637 /* when display is unplugged from mst hub, connctor will
8638 * be destroyed within dm_dp_mst_connector_destroy. connector
8639 * hdcp perperties, like type, undesired, desired, enabled,
8640 * will be lost. So, save hdcp properties into hdcp_work within
8641 * amdgpu_dm_atomic_commit_tail. if the same display is
8642 * plugged back with same display index, its hdcp properties
8643 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8646 bool enable_encryption = false;
8648 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8649 enable_encryption = true;
8651 if (aconnector->dc_link && aconnector->dc_sink &&
8652 aconnector->dc_link->type == dc_connection_mst_branch) {
8653 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8654 struct hdcp_workqueue *hdcp_w =
8655 &hdcp_work[aconnector->dc_link->link_index];
8657 hdcp_w->hdcp_content_type[connector->index] =
8658 new_con_state->hdcp_content_type;
8659 hdcp_w->content_protection[connector->index] =
8660 new_con_state->content_protection;
8663 if (new_crtc_state && new_crtc_state->mode_changed &&
8664 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8665 enable_encryption = true;
8667 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8669 hdcp_update_display(
8670 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8671 new_con_state->hdcp_content_type, enable_encryption);
8675 /* Handle connector state changes */
8676 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8677 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8678 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8679 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8680 struct dc_surface_update dummy_updates[MAX_SURFACES];
8681 struct dc_stream_update stream_update;
8682 struct dc_info_packet hdr_packet;
8683 struct dc_stream_status *status = NULL;
8684 bool abm_changed, hdr_changed, scaling_changed;
8686 memset(&dummy_updates, 0, sizeof(dummy_updates));
8687 memset(&stream_update, 0, sizeof(stream_update));
8690 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8691 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8694 /* Skip any modesets/resets */
8695 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8698 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8699 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8701 scaling_changed = is_scaling_state_different(dm_new_con_state,
8704 abm_changed = dm_new_crtc_state->abm_level !=
8705 dm_old_crtc_state->abm_level;
8708 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8710 if (!scaling_changed && !abm_changed && !hdr_changed)
8713 stream_update.stream = dm_new_crtc_state->stream;
8714 if (scaling_changed) {
8715 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8716 dm_new_con_state, dm_new_crtc_state->stream);
8718 stream_update.src = dm_new_crtc_state->stream->src;
8719 stream_update.dst = dm_new_crtc_state->stream->dst;
8723 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8725 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8729 fill_hdr_info_packet(new_con_state, &hdr_packet);
8730 stream_update.hdr_static_metadata = &hdr_packet;
8733 status = dc_stream_get_status(dm_new_crtc_state->stream);
8735 if (WARN_ON(!status))
8738 WARN_ON(!status->plane_count);
8741 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8742 * Here we create an empty update on each plane.
8743 * To fix this, DC should permit updating only stream properties.
8745 for (j = 0; j < status->plane_count; j++)
8746 dummy_updates[j].surface = status->plane_states[0];
8749 mutex_lock(&dm->dc_lock);
8750 dc_update_planes_and_stream(dm->dc,
8752 status->plane_count,
8753 dm_new_crtc_state->stream,
8755 mutex_unlock(&dm->dc_lock);
8759 * Enable interrupts for CRTCs that are newly enabled or went through
8760 * a modeset. It was intentionally deferred until after the front end
8761 * state was modified to wait until the OTG was on and so the IRQ
8762 * handlers didn't access stale or invalid state.
8764 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8765 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8766 #ifdef CONFIG_DEBUG_FS
8767 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8769 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8770 if (old_crtc_state->active && !new_crtc_state->active)
8771 crtc_disable_count++;
8773 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8774 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8776 /* For freesync config update on crtc state and params for irq */
8777 update_stream_irq_parameters(dm, dm_new_crtc_state);
8779 #ifdef CONFIG_DEBUG_FS
8780 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8781 cur_crc_src = acrtc->dm_irq_params.crc_src;
8782 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8785 if (new_crtc_state->active &&
8786 (!old_crtc_state->active ||
8787 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8788 dc_stream_retain(dm_new_crtc_state->stream);
8789 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8790 manage_dm_interrupts(adev, acrtc, true);
8792 /* Handle vrr on->off / off->on transitions */
8793 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8795 #ifdef CONFIG_DEBUG_FS
8796 if (new_crtc_state->active &&
8797 (!old_crtc_state->active ||
8798 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8800 * Frontend may have changed so reapply the CRC capture
8801 * settings for the stream.
8803 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8804 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8805 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8806 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8807 acrtc->dm_irq_params.window_param.update_win = true;
8810 * It takes 2 frames for HW to stably generate CRC when
8811 * resuming from suspend, so we set skip_frame_cnt 2.
8813 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8814 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8817 if (amdgpu_dm_crtc_configure_crc_source(
8818 crtc, dm_new_crtc_state, cur_crc_src))
8819 DRM_DEBUG_DRIVER("Failed to configure crc source");
8825 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8826 if (new_crtc_state->async_flip)
8827 wait_for_vblank = false;
8829 /* update planes when needed per crtc*/
8830 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8831 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8833 if (dm_new_crtc_state->stream)
8834 amdgpu_dm_commit_planes(state, dc_state, dev,
8835 dm, crtc, wait_for_vblank);
8838 /* Update audio instances for each connector. */
8839 amdgpu_dm_commit_audio(dev, state);
8841 /* restore the backlight level */
8842 for (i = 0; i < dm->num_of_edps; i++) {
8843 if (dm->backlight_dev[i] &&
8844 (dm->actual_brightness[i] != dm->brightness[i]))
8845 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8849 * send vblank event on all events not handled in flip and
8850 * mark consumed event for drm_atomic_helper_commit_hw_done
8852 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8853 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8855 if (new_crtc_state->event)
8856 drm_send_event_locked(dev, &new_crtc_state->event->base);
8858 new_crtc_state->event = NULL;
8860 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8862 /* Signal HW programming completion */
8863 drm_atomic_helper_commit_hw_done(state);
8865 if (wait_for_vblank)
8866 drm_atomic_helper_wait_for_flip_done(dev, state);
8868 drm_atomic_helper_cleanup_planes(dev, state);
8870 /* return the stolen vga memory back to VRAM */
8871 if (!adev->mman.keep_stolen_vga_memory)
8872 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8873 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8876 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8877 * so we can put the GPU into runtime suspend if we're not driving any
8880 for (i = 0; i < crtc_disable_count; i++)
8881 pm_runtime_put_autosuspend(dev->dev);
8882 pm_runtime_mark_last_busy(dev->dev);
8885 dc_release_state(dc_state_temp);
8888 static int dm_force_atomic_commit(struct drm_connector *connector)
8891 struct drm_device *ddev = connector->dev;
8892 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8893 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8894 struct drm_plane *plane = disconnected_acrtc->base.primary;
8895 struct drm_connector_state *conn_state;
8896 struct drm_crtc_state *crtc_state;
8897 struct drm_plane_state *plane_state;
8902 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8904 /* Construct an atomic state to restore previous display setting */
8907 * Attach connectors to drm_atomic_state
8909 conn_state = drm_atomic_get_connector_state(state, connector);
8911 ret = PTR_ERR_OR_ZERO(conn_state);
8915 /* Attach crtc to drm_atomic_state*/
8916 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8918 ret = PTR_ERR_OR_ZERO(crtc_state);
8922 /* force a restore */
8923 crtc_state->mode_changed = true;
8925 /* Attach plane to drm_atomic_state */
8926 plane_state = drm_atomic_get_plane_state(state, plane);
8928 ret = PTR_ERR_OR_ZERO(plane_state);
8932 /* Call commit internally with the state we just constructed */
8933 ret = drm_atomic_commit(state);
8936 drm_atomic_state_put(state);
8938 DRM_ERROR("Restoring old state failed with %i\n", ret);
8944 * This function handles all cases when set mode does not come upon hotplug.
8945 * This includes when a display is unplugged then plugged back into the
8946 * same port and when running without usermode desktop manager supprot
8948 void dm_restore_drm_connector_state(struct drm_device *dev,
8949 struct drm_connector *connector)
8951 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8952 struct amdgpu_crtc *disconnected_acrtc;
8953 struct dm_crtc_state *acrtc_state;
8955 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8958 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8959 if (!disconnected_acrtc)
8962 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8963 if (!acrtc_state->stream)
8967 * If the previous sink is not released and different from the current,
8968 * we deduce we are in a state where we can not rely on usermode call
8969 * to turn on the display, so we do it here
8971 if (acrtc_state->stream->sink != aconnector->dc_sink)
8972 dm_force_atomic_commit(&aconnector->base);
8976 * Grabs all modesetting locks to serialize against any blocking commits,
8977 * Waits for completion of all non blocking commits.
8979 static int do_aquire_global_lock(struct drm_device *dev,
8980 struct drm_atomic_state *state)
8982 struct drm_crtc *crtc;
8983 struct drm_crtc_commit *commit;
8987 * Adding all modeset locks to aquire_ctx will
8988 * ensure that when the framework release it the
8989 * extra locks we are locking here will get released to
8991 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8995 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8996 spin_lock(&crtc->commit_lock);
8997 commit = list_first_entry_or_null(&crtc->commit_list,
8998 struct drm_crtc_commit, commit_entry);
9000 drm_crtc_commit_get(commit);
9001 spin_unlock(&crtc->commit_lock);
9007 * Make sure all pending HW programming completed and
9010 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9013 ret = wait_for_completion_interruptible_timeout(
9014 &commit->flip_done, 10*HZ);
9017 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9018 "timed out\n", crtc->base.id, crtc->name);
9020 drm_crtc_commit_put(commit);
9023 return ret < 0 ? ret : 0;
9026 static void get_freesync_config_for_crtc(
9027 struct dm_crtc_state *new_crtc_state,
9028 struct dm_connector_state *new_con_state)
9030 struct mod_freesync_config config = {0};
9031 struct amdgpu_dm_connector *aconnector =
9032 to_amdgpu_dm_connector(new_con_state->base.connector);
9033 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9034 int vrefresh = drm_mode_vrefresh(mode);
9035 bool fs_vid_mode = false;
9037 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9038 vrefresh >= aconnector->min_vfreq &&
9039 vrefresh <= aconnector->max_vfreq;
9041 if (new_crtc_state->vrr_supported) {
9042 new_crtc_state->stream->ignore_msa_timing_param = true;
9043 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9045 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9046 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9047 config.vsif_supported = true;
9051 config.state = VRR_STATE_ACTIVE_FIXED;
9052 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9054 } else if (new_crtc_state->base.vrr_enabled) {
9055 config.state = VRR_STATE_ACTIVE_VARIABLE;
9057 config.state = VRR_STATE_INACTIVE;
9061 new_crtc_state->freesync_config = config;
9064 static void reset_freesync_config_for_crtc(
9065 struct dm_crtc_state *new_crtc_state)
9067 new_crtc_state->vrr_supported = false;
9069 memset(&new_crtc_state->vrr_infopacket, 0,
9070 sizeof(new_crtc_state->vrr_infopacket));
9074 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9075 struct drm_crtc_state *new_crtc_state)
9077 const struct drm_display_mode *old_mode, *new_mode;
9079 if (!old_crtc_state || !new_crtc_state)
9082 old_mode = &old_crtc_state->mode;
9083 new_mode = &new_crtc_state->mode;
9085 if (old_mode->clock == new_mode->clock &&
9086 old_mode->hdisplay == new_mode->hdisplay &&
9087 old_mode->vdisplay == new_mode->vdisplay &&
9088 old_mode->htotal == new_mode->htotal &&
9089 old_mode->vtotal != new_mode->vtotal &&
9090 old_mode->hsync_start == new_mode->hsync_start &&
9091 old_mode->vsync_start != new_mode->vsync_start &&
9092 old_mode->hsync_end == new_mode->hsync_end &&
9093 old_mode->vsync_end != new_mode->vsync_end &&
9094 old_mode->hskew == new_mode->hskew &&
9095 old_mode->vscan == new_mode->vscan &&
9096 (old_mode->vsync_end - old_mode->vsync_start) ==
9097 (new_mode->vsync_end - new_mode->vsync_start))
9103 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9105 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9107 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9109 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9110 den = (unsigned long long)new_crtc_state->mode.htotal *
9111 (unsigned long long)new_crtc_state->mode.vtotal;
9113 res = div_u64(num, den);
9114 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9117 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9118 struct drm_atomic_state *state,
9119 struct drm_crtc *crtc,
9120 struct drm_crtc_state *old_crtc_state,
9121 struct drm_crtc_state *new_crtc_state,
9123 bool *lock_and_validation_needed)
9125 struct dm_atomic_state *dm_state = NULL;
9126 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9127 struct dc_stream_state *new_stream;
9131 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9132 * update changed items
9134 struct amdgpu_crtc *acrtc = NULL;
9135 struct amdgpu_dm_connector *aconnector = NULL;
9136 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9137 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9141 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9142 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9143 acrtc = to_amdgpu_crtc(crtc);
9144 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9146 /* TODO This hack should go away */
9147 if (aconnector && enable) {
9148 /* Make sure fake sink is created in plug-in scenario */
9149 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9151 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9154 if (IS_ERR(drm_new_conn_state)) {
9155 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9159 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9160 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9162 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9165 new_stream = create_validate_stream_for_sink(aconnector,
9166 &new_crtc_state->mode,
9168 dm_old_crtc_state->stream);
9171 * we can have no stream on ACTION_SET if a display
9172 * was disconnected during S3, in this case it is not an
9173 * error, the OS will be updated after detection, and
9174 * will do the right thing on next atomic commit
9178 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9179 __func__, acrtc->base.base.id);
9185 * TODO: Check VSDB bits to decide whether this should
9186 * be enabled or not.
9188 new_stream->triggered_crtc_reset.enabled =
9189 dm->force_timing_sync;
9191 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9193 ret = fill_hdr_info_packet(drm_new_conn_state,
9194 &new_stream->hdr_static_metadata);
9199 * If we already removed the old stream from the context
9200 * (and set the new stream to NULL) then we can't reuse
9201 * the old stream even if the stream and scaling are unchanged.
9202 * We'll hit the BUG_ON and black screen.
9204 * TODO: Refactor this function to allow this check to work
9205 * in all conditions.
9207 if (amdgpu_freesync_vid_mode &&
9208 dm_new_crtc_state->stream &&
9209 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9212 if (dm_new_crtc_state->stream &&
9213 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9214 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9215 new_crtc_state->mode_changed = false;
9216 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9217 new_crtc_state->mode_changed);
9221 /* mode_changed flag may get updated above, need to check again */
9222 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9225 drm_dbg_state(state->dev,
9226 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9227 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9228 "connectors_changed:%d\n",
9230 new_crtc_state->enable,
9231 new_crtc_state->active,
9232 new_crtc_state->planes_changed,
9233 new_crtc_state->mode_changed,
9234 new_crtc_state->active_changed,
9235 new_crtc_state->connectors_changed);
9237 /* Remove stream for any changed/disabled CRTC */
9240 if (!dm_old_crtc_state->stream)
9243 /* Unset freesync video if it was active before */
9244 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9245 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9246 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9249 /* Now check if we should set freesync video mode */
9250 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9251 is_timing_unchanged_for_freesync(new_crtc_state,
9253 new_crtc_state->mode_changed = false;
9255 "Mode change not required for front porch change, "
9256 "setting mode_changed to %d",
9257 new_crtc_state->mode_changed);
9259 set_freesync_fixed_config(dm_new_crtc_state);
9262 } else if (amdgpu_freesync_vid_mode && aconnector &&
9263 is_freesync_video_mode(&new_crtc_state->mode,
9265 struct drm_display_mode *high_mode;
9267 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9268 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9269 set_freesync_fixed_config(dm_new_crtc_state);
9273 ret = dm_atomic_get_state(state, &dm_state);
9277 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9280 /* i.e. reset mode */
9281 if (dc_remove_stream_from_ctx(
9284 dm_old_crtc_state->stream) != DC_OK) {
9289 dc_stream_release(dm_old_crtc_state->stream);
9290 dm_new_crtc_state->stream = NULL;
9292 reset_freesync_config_for_crtc(dm_new_crtc_state);
9294 *lock_and_validation_needed = true;
9296 } else {/* Add stream for any updated/enabled CRTC */
9298 * Quick fix to prevent NULL pointer on new_stream when
9299 * added MST connectors not found in existing crtc_state in the chained mode
9300 * TODO: need to dig out the root cause of that
9305 if (modereset_required(new_crtc_state))
9308 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9309 dm_old_crtc_state->stream)) {
9311 WARN_ON(dm_new_crtc_state->stream);
9313 ret = dm_atomic_get_state(state, &dm_state);
9317 dm_new_crtc_state->stream = new_stream;
9319 dc_stream_retain(new_stream);
9321 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9324 if (dc_add_stream_to_ctx(
9327 dm_new_crtc_state->stream) != DC_OK) {
9332 *lock_and_validation_needed = true;
9337 /* Release extra reference */
9339 dc_stream_release(new_stream);
9342 * We want to do dc stream updates that do not require a
9343 * full modeset below.
9345 if (!(enable && aconnector && new_crtc_state->active))
9348 * Given above conditions, the dc state cannot be NULL because:
9349 * 1. We're in the process of enabling CRTCs (just been added
9350 * to the dc context, or already is on the context)
9351 * 2. Has a valid connector attached, and
9352 * 3. Is currently active and enabled.
9353 * => The dc stream state currently exists.
9355 BUG_ON(dm_new_crtc_state->stream == NULL);
9357 /* Scaling or underscan settings */
9358 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9359 drm_atomic_crtc_needs_modeset(new_crtc_state))
9360 update_stream_scaling_settings(
9361 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9364 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9367 * Color management settings. We also update color properties
9368 * when a modeset is needed, to ensure it gets reprogrammed.
9370 if (dm_new_crtc_state->base.color_mgmt_changed ||
9371 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9372 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9377 /* Update Freesync settings. */
9378 get_freesync_config_for_crtc(dm_new_crtc_state,
9385 dc_stream_release(new_stream);
9389 static bool should_reset_plane(struct drm_atomic_state *state,
9390 struct drm_plane *plane,
9391 struct drm_plane_state *old_plane_state,
9392 struct drm_plane_state *new_plane_state)
9394 struct drm_plane *other;
9395 struct drm_plane_state *old_other_state, *new_other_state;
9396 struct drm_crtc_state *new_crtc_state;
9400 * TODO: Remove this hack once the checks below are sufficient
9401 * enough to determine when we need to reset all the planes on
9404 if (state->allow_modeset)
9407 /* Exit early if we know that we're adding or removing the plane. */
9408 if (old_plane_state->crtc != new_plane_state->crtc)
9411 /* old crtc == new_crtc == NULL, plane not in context. */
9412 if (!new_plane_state->crtc)
9416 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9418 if (!new_crtc_state)
9421 /* CRTC Degamma changes currently require us to recreate planes. */
9422 if (new_crtc_state->color_mgmt_changed)
9425 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9429 * If there are any new primary or overlay planes being added or
9430 * removed then the z-order can potentially change. To ensure
9431 * correct z-order and pipe acquisition the current DC architecture
9432 * requires us to remove and recreate all existing planes.
9434 * TODO: Come up with a more elegant solution for this.
9436 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9437 struct amdgpu_framebuffer *old_afb, *new_afb;
9438 if (other->type == DRM_PLANE_TYPE_CURSOR)
9441 if (old_other_state->crtc != new_plane_state->crtc &&
9442 new_other_state->crtc != new_plane_state->crtc)
9445 if (old_other_state->crtc != new_other_state->crtc)
9448 /* Src/dst size and scaling updates. */
9449 if (old_other_state->src_w != new_other_state->src_w ||
9450 old_other_state->src_h != new_other_state->src_h ||
9451 old_other_state->crtc_w != new_other_state->crtc_w ||
9452 old_other_state->crtc_h != new_other_state->crtc_h)
9455 /* Rotation / mirroring updates. */
9456 if (old_other_state->rotation != new_other_state->rotation)
9459 /* Blending updates. */
9460 if (old_other_state->pixel_blend_mode !=
9461 new_other_state->pixel_blend_mode)
9464 /* Alpha updates. */
9465 if (old_other_state->alpha != new_other_state->alpha)
9468 /* Colorspace changes. */
9469 if (old_other_state->color_range != new_other_state->color_range ||
9470 old_other_state->color_encoding != new_other_state->color_encoding)
9473 /* Framebuffer checks fall at the end. */
9474 if (!old_other_state->fb || !new_other_state->fb)
9477 /* Pixel format changes can require bandwidth updates. */
9478 if (old_other_state->fb->format != new_other_state->fb->format)
9481 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9482 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9484 /* Tiling and DCC changes also require bandwidth updates. */
9485 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9486 old_afb->base.modifier != new_afb->base.modifier)
9493 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9494 struct drm_plane_state *new_plane_state,
9495 struct drm_framebuffer *fb)
9497 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9498 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9502 if (fb->width > new_acrtc->max_cursor_width ||
9503 fb->height > new_acrtc->max_cursor_height) {
9504 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9505 new_plane_state->fb->width,
9506 new_plane_state->fb->height);
9509 if (new_plane_state->src_w != fb->width << 16 ||
9510 new_plane_state->src_h != fb->height << 16) {
9511 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9515 /* Pitch in pixels */
9516 pitch = fb->pitches[0] / fb->format->cpp[0];
9518 if (fb->width != pitch) {
9519 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9528 /* FB pitch is supported by cursor plane */
9531 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9535 /* Core DRM takes care of checking FB modifiers, so we only need to
9536 * check tiling flags when the FB doesn't have a modifier. */
9537 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9538 if (adev->family < AMDGPU_FAMILY_AI) {
9539 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9540 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9541 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9543 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9546 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9554 static int dm_update_plane_state(struct dc *dc,
9555 struct drm_atomic_state *state,
9556 struct drm_plane *plane,
9557 struct drm_plane_state *old_plane_state,
9558 struct drm_plane_state *new_plane_state,
9560 bool *lock_and_validation_needed,
9561 bool *is_top_most_overlay)
9564 struct dm_atomic_state *dm_state = NULL;
9565 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9566 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9567 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9568 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9569 struct amdgpu_crtc *new_acrtc;
9574 new_plane_crtc = new_plane_state->crtc;
9575 old_plane_crtc = old_plane_state->crtc;
9576 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9577 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9579 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9580 if (!enable || !new_plane_crtc ||
9581 drm_atomic_plane_disabling(plane->state, new_plane_state))
9584 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9586 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9587 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9591 if (new_plane_state->fb) {
9592 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9593 new_plane_state->fb);
9601 needs_reset = should_reset_plane(state, plane, old_plane_state,
9604 /* Remove any changed/removed planes */
9609 if (!old_plane_crtc)
9612 old_crtc_state = drm_atomic_get_old_crtc_state(
9613 state, old_plane_crtc);
9614 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9616 if (!dm_old_crtc_state->stream)
9619 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9620 plane->base.id, old_plane_crtc->base.id);
9622 ret = dm_atomic_get_state(state, &dm_state);
9626 if (!dc_remove_plane_from_context(
9628 dm_old_crtc_state->stream,
9629 dm_old_plane_state->dc_state,
9630 dm_state->context)) {
9636 dc_plane_state_release(dm_old_plane_state->dc_state);
9637 dm_new_plane_state->dc_state = NULL;
9639 *lock_and_validation_needed = true;
9641 } else { /* Add new planes */
9642 struct dc_plane_state *dc_new_plane_state;
9644 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9647 if (!new_plane_crtc)
9650 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9651 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9653 if (!dm_new_crtc_state->stream)
9659 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9663 WARN_ON(dm_new_plane_state->dc_state);
9665 dc_new_plane_state = dc_create_plane_state(dc);
9666 if (!dc_new_plane_state)
9669 /* Block top most plane from being a video plane */
9670 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9671 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9674 *is_top_most_overlay = false;
9677 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9678 plane->base.id, new_plane_crtc->base.id);
9680 ret = fill_dc_plane_attributes(
9681 drm_to_adev(new_plane_crtc->dev),
9686 dc_plane_state_release(dc_new_plane_state);
9690 ret = dm_atomic_get_state(state, &dm_state);
9692 dc_plane_state_release(dc_new_plane_state);
9697 * Any atomic check errors that occur after this will
9698 * not need a release. The plane state will be attached
9699 * to the stream, and therefore part of the atomic
9700 * state. It'll be released when the atomic state is
9703 if (!dc_add_plane_to_context(
9705 dm_new_crtc_state->stream,
9707 dm_state->context)) {
9709 dc_plane_state_release(dc_new_plane_state);
9713 dm_new_plane_state->dc_state = dc_new_plane_state;
9715 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9717 /* Tell DC to do a full surface update every time there
9718 * is a plane change. Inefficient, but works for now.
9720 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9722 *lock_and_validation_needed = true;
9729 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9730 int *src_w, int *src_h)
9732 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9733 case DRM_MODE_ROTATE_90:
9734 case DRM_MODE_ROTATE_270:
9735 *src_w = plane_state->src_h >> 16;
9736 *src_h = plane_state->src_w >> 16;
9738 case DRM_MODE_ROTATE_0:
9739 case DRM_MODE_ROTATE_180:
9741 *src_w = plane_state->src_w >> 16;
9742 *src_h = plane_state->src_h >> 16;
9747 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9748 struct drm_crtc *crtc,
9749 struct drm_crtc_state *new_crtc_state)
9751 struct drm_plane *cursor = crtc->cursor, *underlying;
9752 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9754 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9755 int cursor_src_w, cursor_src_h;
9756 int underlying_src_w, underlying_src_h;
9758 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9759 * cursor per pipe but it's going to inherit the scaling and
9760 * positioning from the underlying pipe. Check the cursor plane's
9761 * blending properties match the underlying planes'. */
9763 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9764 if (!new_cursor_state || !new_cursor_state->fb) {
9768 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9769 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9770 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9772 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9773 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9774 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9777 /* Ignore disabled planes */
9778 if (!new_underlying_state->fb)
9781 dm_get_oriented_plane_size(new_underlying_state,
9782 &underlying_src_w, &underlying_src_h);
9783 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9784 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9786 if (cursor_scale_w != underlying_scale_w ||
9787 cursor_scale_h != underlying_scale_h) {
9788 drm_dbg_atomic(crtc->dev,
9789 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9790 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9794 /* If this plane covers the whole CRTC, no need to check planes underneath */
9795 if (new_underlying_state->crtc_x <= 0 &&
9796 new_underlying_state->crtc_y <= 0 &&
9797 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9798 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9805 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9807 struct drm_connector *connector;
9808 struct drm_connector_state *conn_state, *old_conn_state;
9809 struct amdgpu_dm_connector *aconnector = NULL;
9811 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9812 if (!conn_state->crtc)
9813 conn_state = old_conn_state;
9815 if (conn_state->crtc != crtc)
9818 aconnector = to_amdgpu_dm_connector(connector);
9819 if (!aconnector->mst_output_port || !aconnector->mst_root)
9828 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9832 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9834 * @dev: The DRM device
9835 * @state: The atomic state to commit
9837 * Validate that the given atomic state is programmable by DC into hardware.
9838 * This involves constructing a &struct dc_state reflecting the new hardware
9839 * state we wish to commit, then querying DC to see if it is programmable. It's
9840 * important not to modify the existing DC state. Otherwise, atomic_check
9841 * may unexpectedly commit hardware changes.
9843 * When validating the DC state, it's important that the right locks are
9844 * acquired. For full updates case which removes/adds/updates streams on one
9845 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9846 * that any such full update commit will wait for completion of any outstanding
9847 * flip using DRMs synchronization events.
9849 * Note that DM adds the affected connectors for all CRTCs in state, when that
9850 * might not seem necessary. This is because DC stream creation requires the
9851 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9852 * be possible but non-trivial - a possible TODO item.
9854 * Return: -Error code if validation failed.
9856 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9857 struct drm_atomic_state *state)
9859 struct amdgpu_device *adev = drm_to_adev(dev);
9860 struct dm_atomic_state *dm_state = NULL;
9861 struct dc *dc = adev->dm.dc;
9862 struct drm_connector *connector;
9863 struct drm_connector_state *old_con_state, *new_con_state;
9864 struct drm_crtc *crtc;
9865 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9866 struct drm_plane *plane;
9867 struct drm_plane_state *old_plane_state, *new_plane_state;
9868 enum dc_status status;
9870 bool lock_and_validation_needed = false;
9871 bool is_top_most_overlay = true;
9872 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9873 struct drm_dp_mst_topology_mgr *mgr;
9874 struct drm_dp_mst_topology_state *mst_state;
9875 struct dsc_mst_fairness_vars vars[MAX_PIPES];
9877 trace_amdgpu_dm_atomic_check_begin(state);
9879 ret = drm_atomic_helper_check_modeset(dev, state);
9881 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9885 /* Check connector changes */
9886 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9887 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9888 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9890 /* Skip connectors that are disabled or part of modeset already. */
9891 if (!new_con_state->crtc)
9894 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9895 if (IS_ERR(new_crtc_state)) {
9896 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9897 ret = PTR_ERR(new_crtc_state);
9901 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9902 dm_old_con_state->scaling != dm_new_con_state->scaling)
9903 new_crtc_state->connectors_changed = true;
9906 if (dc_resource_is_dsc_encoding_supported(dc)) {
9907 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9908 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9909 ret = add_affected_mst_dsc_crtcs(state, crtc);
9911 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9917 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9918 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9920 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9921 !new_crtc_state->color_mgmt_changed &&
9922 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9923 dm_old_crtc_state->dsc_force_changed == false)
9926 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9928 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9932 if (!new_crtc_state->enable)
9935 ret = drm_atomic_add_affected_connectors(state, crtc);
9937 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9941 ret = drm_atomic_add_affected_planes(state, crtc);
9943 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9947 if (dm_old_crtc_state->dsc_force_changed)
9948 new_crtc_state->mode_changed = true;
9952 * Add all primary and overlay planes on the CRTC to the state
9953 * whenever a plane is enabled to maintain correct z-ordering
9954 * and to enable fast surface updates.
9956 drm_for_each_crtc(crtc, dev) {
9957 bool modified = false;
9959 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9960 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9963 if (new_plane_state->crtc == crtc ||
9964 old_plane_state->crtc == crtc) {
9973 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9974 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9978 drm_atomic_get_plane_state(state, plane);
9980 if (IS_ERR(new_plane_state)) {
9981 ret = PTR_ERR(new_plane_state);
9982 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9989 * DC consults the zpos (layer_index in DC terminology) to determine the
9990 * hw plane on which to enable the hw cursor (see
9991 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9992 * atomic state, so call drm helper to normalize zpos.
9994 ret = drm_atomic_normalize_zpos(dev, state);
9996 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10000 /* Remove exiting planes if they are modified */
10001 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10002 ret = dm_update_plane_state(dc, state, plane,
10006 &lock_and_validation_needed,
10007 &is_top_most_overlay);
10009 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10014 /* Disable all crtcs which require disable */
10015 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10016 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10020 &lock_and_validation_needed);
10022 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10027 /* Enable all crtcs which require enable */
10028 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10029 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10033 &lock_and_validation_needed);
10035 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10040 /* Add new/modified planes */
10041 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10042 ret = dm_update_plane_state(dc, state, plane,
10046 &lock_and_validation_needed,
10047 &is_top_most_overlay);
10049 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10054 if (dc_resource_is_dsc_encoding_supported(dc)) {
10055 ret = pre_validate_dsc(state, &dm_state, vars);
10060 /* Run this here since we want to validate the streams we created */
10061 ret = drm_atomic_helper_check_planes(dev, state);
10063 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10067 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10068 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10069 if (dm_new_crtc_state->mpo_requested)
10070 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10073 /* Check cursor planes scaling */
10074 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10075 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10077 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10082 if (state->legacy_cursor_update) {
10084 * This is a fast cursor update coming from the plane update
10085 * helper, check if it can be done asynchronously for better
10088 state->async_update =
10089 !drm_atomic_helper_async_check(dev, state);
10092 * Skip the remaining global validation if this is an async
10093 * update. Cursor updates can be done without affecting
10094 * state or bandwidth calcs and this avoids the performance
10095 * penalty of locking the private state object and
10096 * allocating a new dc_state.
10098 if (state->async_update)
10102 /* Check scaling and underscan changes*/
10103 /* TODO Removed scaling changes validation due to inability to commit
10104 * new stream into context w\o causing full reset. Need to
10105 * decide how to handle.
10107 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10108 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10109 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10110 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10112 /* Skip any modesets/resets */
10113 if (!acrtc || drm_atomic_crtc_needs_modeset(
10114 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10117 /* Skip any thing not scale or underscan changes */
10118 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10121 lock_and_validation_needed = true;
10124 /* set the slot info for each mst_state based on the link encoding format */
10125 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10126 struct amdgpu_dm_connector *aconnector;
10127 struct drm_connector *connector;
10128 struct drm_connector_list_iter iter;
10129 u8 link_coding_cap;
10131 drm_connector_list_iter_begin(dev, &iter);
10132 drm_for_each_connector_iter(connector, &iter) {
10133 if (connector->index == mst_state->mgr->conn_base_id) {
10134 aconnector = to_amdgpu_dm_connector(connector);
10135 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10136 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10141 drm_connector_list_iter_end(&iter);
10145 * Streams and planes are reset when there are changes that affect
10146 * bandwidth. Anything that affects bandwidth needs to go through
10147 * DC global validation to ensure that the configuration can be applied
10150 * We have to currently stall out here in atomic_check for outstanding
10151 * commits to finish in this case because our IRQ handlers reference
10152 * DRM state directly - we can end up disabling interrupts too early
10155 * TODO: Remove this stall and drop DM state private objects.
10157 if (lock_and_validation_needed) {
10158 ret = dm_atomic_get_state(state, &dm_state);
10160 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10164 ret = do_aquire_global_lock(dev, state);
10166 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10170 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10172 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10176 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10178 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10183 * Perform validation of MST topology in the state:
10184 * We need to perform MST atomic check before calling
10185 * dc_validate_global_state(), or there is a chance
10186 * to get stuck in an infinite loop and hang eventually.
10188 ret = drm_dp_mst_atomic_check(state);
10190 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10193 status = dc_validate_global_state(dc, dm_state->context, true);
10194 if (status != DC_OK) {
10195 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10196 dc_status_to_str(status), status);
10202 * The commit is a fast update. Fast updates shouldn't change
10203 * the DC context, affect global validation, and can have their
10204 * commit work done in parallel with other commits not touching
10205 * the same resource. If we have a new DC context as part of
10206 * the DM atomic state from validation we need to free it and
10207 * retain the existing one instead.
10209 * Furthermore, since the DM atomic state only contains the DC
10210 * context and can safely be annulled, we can free the state
10211 * and clear the associated private object now to free
10212 * some memory and avoid a possible use-after-free later.
10215 for (i = 0; i < state->num_private_objs; i++) {
10216 struct drm_private_obj *obj = state->private_objs[i].ptr;
10218 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10219 int j = state->num_private_objs-1;
10221 dm_atomic_destroy_state(obj,
10222 state->private_objs[i].state);
10224 /* If i is not at the end of the array then the
10225 * last element needs to be moved to where i was
10226 * before the array can safely be truncated.
10229 state->private_objs[i] =
10230 state->private_objs[j];
10232 state->private_objs[j].ptr = NULL;
10233 state->private_objs[j].state = NULL;
10234 state->private_objs[j].old_state = NULL;
10235 state->private_objs[j].new_state = NULL;
10237 state->num_private_objs = j;
10243 /* Store the overall update type for use later in atomic check. */
10244 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10245 struct dm_crtc_state *dm_new_crtc_state =
10246 to_dm_crtc_state(new_crtc_state);
10248 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10253 /* Must be success */
10256 trace_amdgpu_dm_atomic_check_finish(state, ret);
10261 if (ret == -EDEADLK)
10262 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10263 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10264 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10266 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10268 trace_amdgpu_dm_atomic_check_finish(state, ret);
10273 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10274 struct amdgpu_dm_connector *amdgpu_dm_connector)
10277 bool capable = false;
10279 if (amdgpu_dm_connector->dc_link &&
10280 dm_helpers_dp_read_dpcd(
10282 amdgpu_dm_connector->dc_link,
10283 DP_DOWN_STREAM_PORT_COUNT,
10285 sizeof(dpcd_data))) {
10286 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10292 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10293 unsigned int offset,
10294 unsigned int total_length,
10296 unsigned int length,
10297 struct amdgpu_hdmi_vsdb_info *vsdb)
10300 union dmub_rb_cmd cmd;
10301 struct dmub_cmd_send_edid_cea *input;
10302 struct dmub_cmd_edid_cea_output *output;
10304 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10307 memset(&cmd, 0, sizeof(cmd));
10309 input = &cmd.edid_cea.data.input;
10311 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10312 cmd.edid_cea.header.sub_type = 0;
10313 cmd.edid_cea.header.payload_bytes =
10314 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10315 input->offset = offset;
10316 input->length = length;
10317 input->cea_total_length = total_length;
10318 memcpy(input->payload, data, length);
10320 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10322 DRM_ERROR("EDID CEA parser failed\n");
10326 output = &cmd.edid_cea.data.output;
10328 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10329 if (!output->ack.success) {
10330 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10331 output->ack.offset);
10333 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10334 if (!output->amd_vsdb.vsdb_found)
10337 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10338 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10339 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10340 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10342 DRM_WARN("Unknown EDID CEA parser results\n");
10349 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10350 u8 *edid_ext, int len,
10351 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10355 /* send extension block to DMCU for parsing */
10356 for (i = 0; i < len; i += 8) {
10360 /* send 8 bytes a time */
10361 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10365 /* EDID block sent completed, expect result */
10366 int version, min_rate, max_rate;
10368 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10370 /* amd vsdb found */
10371 vsdb_info->freesync_supported = 1;
10372 vsdb_info->amd_vsdb_version = version;
10373 vsdb_info->min_refresh_rate_hz = min_rate;
10374 vsdb_info->max_refresh_rate_hz = max_rate;
10382 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10390 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10391 u8 *edid_ext, int len,
10392 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10396 /* send extension block to DMCU for parsing */
10397 for (i = 0; i < len; i += 8) {
10398 /* send 8 bytes a time */
10399 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10403 return vsdb_info->freesync_supported;
10406 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10407 u8 *edid_ext, int len,
10408 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10410 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10413 mutex_lock(&adev->dm.dc_lock);
10414 if (adev->dm.dmub_srv)
10415 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10417 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10418 mutex_unlock(&adev->dm.dc_lock);
10422 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10423 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10425 u8 *edid_ext = NULL;
10427 bool valid_vsdb_found = false;
10429 /*----- drm_find_cea_extension() -----*/
10430 /* No EDID or EDID extensions */
10431 if (edid == NULL || edid->extensions == 0)
10434 /* Find CEA extension */
10435 for (i = 0; i < edid->extensions; i++) {
10436 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10437 if (edid_ext[0] == CEA_EXT)
10441 if (i == edid->extensions)
10444 /*----- cea_db_offsets() -----*/
10445 if (edid_ext[0] != CEA_EXT)
10448 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10450 return valid_vsdb_found ? i : -ENODEV;
10454 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10456 * @connector: Connector to query.
10457 * @edid: EDID from monitor
10459 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10460 * track of some of the display information in the internal data struct used by
10461 * amdgpu_dm. This function checks which type of connector we need to set the
10462 * FreeSync parameters.
10464 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10468 struct detailed_timing *timing;
10469 struct detailed_non_pixel *data;
10470 struct detailed_data_monitor_range *range;
10471 struct amdgpu_dm_connector *amdgpu_dm_connector =
10472 to_amdgpu_dm_connector(connector);
10473 struct dm_connector_state *dm_con_state = NULL;
10474 struct dc_sink *sink;
10476 struct drm_device *dev = connector->dev;
10477 struct amdgpu_device *adev = drm_to_adev(dev);
10478 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10479 bool freesync_capable = false;
10480 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10482 if (!connector->state) {
10483 DRM_ERROR("%s - Connector has no state", __func__);
10487 sink = amdgpu_dm_connector->dc_sink ?
10488 amdgpu_dm_connector->dc_sink :
10489 amdgpu_dm_connector->dc_em_sink;
10491 if (!edid || !sink) {
10492 dm_con_state = to_dm_connector_state(connector->state);
10494 amdgpu_dm_connector->min_vfreq = 0;
10495 amdgpu_dm_connector->max_vfreq = 0;
10496 amdgpu_dm_connector->pixel_clock_mhz = 0;
10497 connector->display_info.monitor_range.min_vfreq = 0;
10498 connector->display_info.monitor_range.max_vfreq = 0;
10499 freesync_capable = false;
10504 dm_con_state = to_dm_connector_state(connector->state);
10506 if (!adev->dm.freesync_module)
10509 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10510 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10511 bool edid_check_required = false;
10514 edid_check_required = is_dp_capable_without_timing_msa(
10516 amdgpu_dm_connector);
10519 if (edid_check_required == true && (edid->version > 1 ||
10520 (edid->version == 1 && edid->revision > 1))) {
10521 for (i = 0; i < 4; i++) {
10523 timing = &edid->detailed_timings[i];
10524 data = &timing->data.other_data;
10525 range = &data->data.range;
10527 * Check if monitor has continuous frequency mode
10529 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10532 * Check for flag range limits only. If flag == 1 then
10533 * no additional timing information provided.
10534 * Default GTF, GTF Secondary curve and CVT are not
10537 if (range->flags != 1)
10540 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10541 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10542 amdgpu_dm_connector->pixel_clock_mhz =
10543 range->pixel_clock_mhz * 10;
10545 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10546 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10551 if (amdgpu_dm_connector->max_vfreq -
10552 amdgpu_dm_connector->min_vfreq > 10) {
10554 freesync_capable = true;
10557 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10558 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10559 if (i >= 0 && vsdb_info.freesync_supported) {
10560 timing = &edid->detailed_timings[i];
10561 data = &timing->data.other_data;
10563 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10564 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10565 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10566 freesync_capable = true;
10568 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10569 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10573 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10575 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10576 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10577 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10579 amdgpu_dm_connector->pack_sdp_v1_3 = true;
10580 amdgpu_dm_connector->as_type = as_type;
10581 amdgpu_dm_connector->vsdb_info = vsdb_info;
10583 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10584 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10585 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10586 freesync_capable = true;
10588 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10589 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10595 dm_con_state->freesync_capable = freesync_capable;
10597 if (connector->vrr_capable_property)
10598 drm_connector_set_vrr_capable_property(connector,
10602 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10604 struct amdgpu_device *adev = drm_to_adev(dev);
10605 struct dc *dc = adev->dm.dc;
10608 mutex_lock(&adev->dm.dc_lock);
10609 if (dc->current_state) {
10610 for (i = 0; i < dc->current_state->stream_count; ++i)
10611 dc->current_state->streams[i]
10612 ->triggered_crtc_reset.enabled =
10613 adev->dm.force_timing_sync;
10615 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10616 dc_trigger_sync(dc, dc->current_state);
10618 mutex_unlock(&adev->dm.dc_lock);
10621 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10622 u32 value, const char *func_name)
10624 #ifdef DM_CHECK_ADDR_0
10625 if (address == 0) {
10626 DC_ERR("invalid register write. address = 0");
10630 cgs_write_register(ctx->cgs_device, address, value);
10631 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10634 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10635 const char *func_name)
10638 #ifdef DM_CHECK_ADDR_0
10639 if (address == 0) {
10640 DC_ERR("invalid register read; address = 0\n");
10645 if (ctx->dmub_srv &&
10646 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10647 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10652 value = cgs_read_register(ctx->cgs_device, address);
10654 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10659 int amdgpu_dm_process_dmub_aux_transfer_sync(
10660 struct dc_context *ctx,
10661 unsigned int link_index,
10662 struct aux_payload *payload,
10663 enum aux_return_code_type *operation_result)
10665 struct amdgpu_device *adev = ctx->driver_context;
10666 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10669 mutex_lock(&adev->dm.dpia_aux_lock);
10670 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10671 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10675 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10676 DRM_ERROR("wait_for_completion_timeout timeout!");
10677 *operation_result = AUX_RET_ERROR_TIMEOUT;
10681 if (p_notify->result != AUX_RET_SUCCESS) {
10683 * Transient states before tunneling is enabled could
10684 * lead to this error. We can ignore this for now.
10686 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10687 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10688 payload->address, payload->length,
10691 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10696 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10697 if (!payload->write && p_notify->aux_reply.length &&
10698 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10700 if (payload->length != p_notify->aux_reply.length) {
10701 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10702 p_notify->aux_reply.length,
10703 payload->address, payload->length);
10704 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10708 memcpy(payload->data, p_notify->aux_reply.data,
10709 p_notify->aux_reply.length);
10713 ret = p_notify->aux_reply.length;
10714 *operation_result = p_notify->result;
10716 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10717 mutex_unlock(&adev->dm.dpia_aux_lock);
10721 int amdgpu_dm_process_dmub_set_config_sync(
10722 struct dc_context *ctx,
10723 unsigned int link_index,
10724 struct set_config_cmd_payload *payload,
10725 enum set_config_status *operation_result)
10727 struct amdgpu_device *adev = ctx->driver_context;
10728 bool is_cmd_complete;
10731 mutex_lock(&adev->dm.dpia_aux_lock);
10732 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10733 link_index, payload, adev->dm.dmub_notify);
10735 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10737 *operation_result = adev->dm.dmub_notify->sc_status;
10739 DRM_ERROR("wait_for_completion_timeout timeout!");
10741 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10744 if (!is_cmd_complete)
10745 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10746 mutex_unlock(&adev->dm.dpia_aux_lock);
10751 * Check whether seamless boot is supported.
10753 * So far we only support seamless boot on CHIP_VANGOGH.
10754 * If everything goes well, we may consider expanding
10755 * seamless boot to other ASICs.
10757 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10759 switch (adev->ip_versions[DCE_HWIP][0]) {
10760 case IP_VERSION(3, 0, 1):
10761 if (!adev->mman.keep_stolen_vga_memory)